From 6c5f9ffb0a0bfa200400e278826097f3ca3b4fa5 Mon Sep 17 00:00:00 2001 From: yandld <1453363089@qq.com> Date: Sun, 27 Nov 2022 15:25:35 +0800 Subject: [PATCH] [bsp][lpc55sxx] update NXP SDK to 2_12_0 update NXP SDK to 2_12_0 --- .../CMSIS/{ => Core}/Include/cmsis_armcc.h | 600 +- .../CMSIS/Core/Include/cmsis_armclang.h | 1503 ++ .../Include/cmsis_armclang_ltm.h} | 1433 +- .../CMSIS/{ => Core}/Include/cmsis_compiler.h | 29 +- .../CMSIS/{ => Core}/Include/cmsis_gcc.h | 1621 +- .../CMSIS/{ => Core}/Include/cmsis_iccarm.h | 143 +- .../CMSIS/{ => Core}/Include/cmsis_version.h | 8 +- .../CMSIS/{ => Core}/Include/core_cm33.h | 832 +- .../CMSIS/{ => Core}/Include/mpu_armv8.h | 69 +- .../CMSIS/{ => Core}/Include/tz_context.h | 0 .../CMSIS/Include/arm_common_tables.h | 121 - .../CMSIS/Include/arm_const_structs.h | 66 - .../LPC55S6X/CMSIS/Include/arm_math.h | 7160 --------- .../LPC55S6X/CMSIS/Include/core_armv8mbl.h | 1896 --- .../LPC55S6X/CMSIS/Include/core_armv8mml.h | 2960 ---- .../LPC55S6X/CMSIS/Include/core_dsp.h | 74 - .../LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.h | 13337 +++++++++++----- .../LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml | 12015 ++++++-------- .../LPC55S6X/LPC55S69_cm33_core0_features.h | 188 +- .../LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h | 13336 ++++++++++----- .../LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml | 12015 ++++++-------- .../LPC55S6X/LPC55S69_cm33_core1_features.h | 188 +- .../arm/LPC55S69_cm33_core0_flash.scf | 25 +- .../arm/LPC55S69_cm33_core0_flash_ns.scf | 52 +- .../arm/LPC55S69_cm33_core0_flash_s.scf | 54 +- .../LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf | 25 +- .../arm/LPC55S69_cm33_core1_flash.scf | 30 +- .../LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf | 33 +- .../arm/LPC55S69_cm33_core1_ram_s.scf | 27 +- .../LPC55S6X/LPC55S6X/arm/LPC55XX_640.FLM | Bin 23308 -> 22132 bytes .../LPC55S6X/LPC55S6X/arm/LPC55XX_S_640.FLM | Bin 23316 -> 22140 bytes .../arm/keil_lib_power_cm33_core0.lib | Bin 10032 -> 0 bytes ...er_cm33_core0_disable_short_enum_wchar.lib | Bin 10032 -> 0 bytes .../arm/keil_lib_power_cm33_core0_s.lib | Bin 10032 -> 0 bytes ..._cm33_core0_s_disable_short_enum_wchar.lib | Bin 10032 -> 0 bytes .../arm/keil_lib_power_cm33_core1.lib | Bin 10024 -> 0 bytes ...er_cm33_core1_disable_short_enum_wchar.lib | Bin 10024 -> 0 bytes .../arm/startup_LPC55S69_cm33_core0.s | 1533 +- .../arm/startup_LPC55S69_cm33_core0_ns.s | 732 - .../arm/startup_LPC55S69_cm33_core1.s | 1527 +- ...sis_flexcomm_i2c_LPC55S69_cm33_core0.cmake | 17 + ...sis_flexcomm_spi_LPC55S69_cm33_core0.cmake | 17 + ...s_flexcomm_usart_LPC55S69_cm33_core0.cmake | 17 + .../LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.c | 3279 ++++ .../LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.h | 93 + .../LPC55S6X/cmsis_drivers/fsl_spi_cmsis.c | 3712 +++++ .../LPC55S6X/cmsis_drivers/fsl_spi_cmsis.h | 93 + .../LPC55S6X/cmsis_drivers/fsl_usart_cmsis.c | 3743 +++++ .../LPC55S6X/cmsis_drivers/fsl_usart_cmsis.h | 94 + .../LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c | 215 +- .../LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h | 365 +- .../LPC55S6X/LPC55S6X/drivers/fsl_casper.c | 2689 ++-- .../LPC55S6X/LPC55S6X/drivers/fsl_casper.h | 181 +- .../LPC55S6X/LPC55S6X/drivers/fsl_clock.c | 743 +- .../LPC55S6X/LPC55S6X/drivers/fsl_clock.h | 1060 +- .../LPC55S6X/LPC55S6X/drivers/fsl_cmp.c | 107 +- .../LPC55S6X/LPC55S6X/drivers/fsl_cmp.h | 344 +- .../LPC55S6X/LPC55S6X/drivers/fsl_common.c | 146 +- .../LPC55S6X/LPC55S6X/drivers/fsl_common.h | 709 +- .../LPC55S6X/drivers/fsl_common_arm.c | 233 + .../LPC55S6X/drivers/fsl_common_arm.h | 671 + .../LPC55S6X/LPC55S6X/drivers/fsl_crc.c | 29 +- .../LPC55S6X/LPC55S6X/drivers/fsl_crc.h | 22 +- .../LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c | 241 +- .../LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h | 87 +- .../LPC55S6X/LPC55S6X/drivers/fsl_dma.c | 489 +- .../LPC55S6X/LPC55S6X/drivers/fsl_dma.h | 189 +- .../LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c | 310 +- .../LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h | 8 +- .../LPC55S6X/LPC55S6X/drivers/fsl_fro_calib.h | 61 + .../LPC55S6X/LPC55S6X/drivers/fsl_gint.c | 70 +- .../LPC55S6X/LPC55S6X/drivers/fsl_gint.h | 4 +- .../LPC55S6X/LPC55S6X/drivers/fsl_gpio.c | 90 +- .../LPC55S6X/LPC55S6X/drivers/fsl_gpio.h | 27 +- .../LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c | 781 +- .../LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h | 127 +- .../LPC55S6X/LPC55S6X/drivers/fsl_i2c.c | 1004 +- .../LPC55S6X/LPC55S6X/drivers/fsl_i2c.h | 232 +- .../LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c | 302 +- .../LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h | 14 +- .../LPC55S6X/drivers/fsl_i2c_freertos.c | 125 + .../LPC55S6X/drivers/fsl_i2c_freertos.h | 107 + .../LPC55S6X/LPC55S6X/drivers/fsl_i2s.c | 612 +- .../LPC55S6X/LPC55S6X/drivers/fsl_i2s.h | 55 +- .../LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c | 409 +- .../LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h | 79 +- .../LPC55S6X/LPC55S6X/drivers/fsl_iap.c | 581 +- .../LPC55S6X/LPC55S6X/drivers/fsl_iap.h | 74 +- .../LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h | 189 +- .../LPC55S6X/LPC55S6X/drivers/fsl_iap_kbp.h | 245 + .../drivers/fsl_iap_skboot_authenticate.h | 77 + .../LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c | 28 +- .../LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h | 6 +- .../drivers/fsl_inputmux_connections.h | 565 +- .../LPC55S6X/LPC55S6X/drivers/fsl_iocon.h | 139 +- .../LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c | 35 +- .../LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h | 155 +- .../LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h | 95 +- .../LPC55S6X/LPC55S6X/drivers/fsl_mrt.c | 14 +- .../LPC55S6X/LPC55S6X/drivers/fsl_mrt.h | 32 +- .../LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c | 181 +- .../LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h | 94 +- .../LPC55S6X/LPC55S6X/drivers/fsl_pint.c | 462 +- .../LPC55S6X/LPC55S6X/drivers/fsl_pint.h | 112 +- .../LPC55S6X/LPC55S6X/drivers/fsl_plu.c | 68 +- .../LPC55S6X/LPC55S6X/drivers/fsl_plu.h | 118 +- .../LPC55S6X/LPC55S6X/drivers/fsl_power.c | 1816 ++- .../LPC55S6X/LPC55S6X/drivers/fsl_power.h | 760 +- .../LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h | 374 +- .../LPC55S6X/drivers/fsl_powerquad_basic.c | 30 +- .../LPC55S6X/drivers/fsl_powerquad_cmsis.c | 774 +- .../LPC55S6X/drivers/fsl_powerquad_data.c | 3 +- .../LPC55S6X/drivers/fsl_powerquad_data.h | 14 +- .../LPC55S6X/drivers/fsl_powerquad_filter.c | 126 +- .../LPC55S6X/drivers/fsl_powerquad_math.c | 460 +- .../LPC55S6X/drivers/fsl_powerquad_matrix.c | 123 +- .../drivers/fsl_powerquad_transform.c | 94 +- .../LPC55S6X/LPC55S6X/drivers/fsl_prince.c | 884 +- .../LPC55S6X/LPC55S6X/drivers/fsl_prince.h | 332 +- .../LPC55S6X/LPC55S6X/drivers/fsl_puf.c | 360 +- .../LPC55S6X/LPC55S6X/drivers/fsl_puf.h | 126 +- .../LPC55S6X/LPC55S6X/drivers/fsl_reset.c | 8 +- .../LPC55S6X/LPC55S6X/drivers/fsl_reset.h | 162 +- .../LPC55S6X/LPC55S6X/drivers/fsl_rng.c | 136 +- .../LPC55S6X/LPC55S6X/drivers/fsl_rng.h | 21 +- .../LPC55S6X/LPC55S6X/drivers/fsl_rtc.c | 71 +- .../LPC55S6X/LPC55S6X/drivers/fsl_rtc.h | 225 +- .../LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c | 540 +- .../LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h | 657 +- .../LPC55S6X/LPC55S6X/drivers/fsl_sdif.c | 689 +- .../LPC55S6X/LPC55S6X/drivers/fsl_sdif.h | 180 +- .../LPC55S6X/LPC55S6X/drivers/fsl_spi.c | 378 +- .../LPC55S6X/LPC55S6X/drivers/fsl_spi.h | 103 +- .../LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c | 234 +- .../LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h | 8 +- .../LPC55S6X/drivers/fsl_spi_freertos.c | 138 + .../LPC55S6X/drivers/fsl_spi_freertos.h | 105 + .../LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c | 33 +- .../LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h | 31 +- .../LPC55S6X/LPC55S6X/drivers/fsl_usart.c | 587 +- .../LPC55S6X/LPC55S6X/drivers/fsl_usart.h | 251 +- .../LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c | 193 +- .../LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h | 20 +- .../LPC55S6X/drivers/fsl_usart_freertos.c | 368 + .../LPC55S6X/drivers/fsl_usart_freertos.h | 132 + .../LPC55S6X/LPC55S6X/drivers/fsl_utick.c | 44 +- .../LPC55S6X/LPC55S6X/drivers/fsl_utick.h | 6 +- .../LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c | 65 +- .../LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h | 10 +- .../LPC55S6X/LPC55S6X/fsl_device_registers.h | 10 +- .../LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld | 25 +- .../gcc/LPC55S69_cm33_core0_flash_ns.ld | 27 +- .../gcc/LPC55S69_cm33_core0_flash_s.ld | 25 +- .../LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld | 25 +- .../LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld | 19 +- .../LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld | 19 +- .../LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld | 19 +- .../LPC55S6X/LPC55S6X/gcc/libpower_hardabi.a | Bin 50644 -> 0 bytes .../LPC55S6X/gcc/libpower_hardabi_s.a | Bin 50612 -> 0 bytes .../LPC55S6X/LPC55S6X/gcc/libpower_soft.a | Bin 50600 -> 0 bytes .../LPC55S6X/LPC55S6X/gcc/libpower_softabi.a | Bin 50644 -> 0 bytes .../LPC55S6X/gcc/libpower_softabi_s.a | Bin 50612 -> 0 bytes .../gcc/startup_LPC55S69_cm33_core0.S | 27 +- .../gcc/startup_LPC55S69_cm33_core1.S | 14 +- .../iar/LPC55S69_cm33_core0_flash.icf | 21 +- .../iar/LPC55S69_cm33_core0_flash_ns.icf | 23 +- .../iar/LPC55S69_cm33_core0_flash_s.icf | 23 +- .../LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf | 21 +- .../iar/LPC55S69_cm33_core1_flash.icf | 17 +- .../LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf | 19 +- .../iar/LPC55S69_cm33_core1_ram_s.icf | 19 +- .../LPC55S6X/iar/iar_lib_power_cm33_core0.a | Bin 13510 -> 0 bytes .../LPC55S6X/iar/iar_lib_power_cm33_core0_s.a | Bin 13526 -> 0 bytes .../LPC55S6X/iar/iar_lib_power_cm33_core1.a | Bin 12664 -> 0 bytes .../iar/startup_LPC55S69_cm33_core0.s | 24 +- .../iar/startup_LPC55S69_cm33_core1.s | 17 +- .../mcuxpresso/boot_multicore_slave.c | 72 +- .../mcuxpresso/boot_multicore_slave.h | 26 +- .../mcuxpresso/startup_lpc55s69_cm33_core0.c | 34 +- .../startup_lpc55s69_cm33_core0.cpp | 34 +- .../mcuxpresso/startup_lpc55s69_cm33_core1.c | 20 +- .../startup_lpc55s69_cm33_core1.cpp | 20 +- .../LPC55S6X/project_template/board.c | 31 + .../LPC55S6X/project_template/board.h | 251 + .../LPC55S6X/project_template/clock_config.c | 374 + .../LPC55S6X/project_template/clock_config.h | 167 + .../LPC55S6X/project_template/peripherals.c | 23 + .../LPC55S6X/project_template/peripherals.h | 23 + .../LPC55S6X/project_template/pin_mux.c | 61 + .../LPC55S6X/project_template/pin_mux.h | 52 + .../LPC55S6X/system_LPC55S69_cm33_core0.c | 164 +- .../LPC55S6X/system_LPC55S69_cm33_core0.h | 17 +- .../LPC55S6X/system_LPC55S69_cm33_core1.c | 155 +- .../LPC55S6X/system_LPC55S69_cm33_core1.h | 17 +- .../LPC55S6X/LPC55S6X/template/RTE_Device.h | 231 + .../debug_console/fsl_debug_console.c | 1417 ++ .../debug_console/fsl_debug_console.h | 317 + .../debug_console/fsl_debug_console_conf.h | 160 + .../utilities/debug_console_lite/fsl_assert.c | 66 + .../debug_console_lite/fsl_debug_console.c | 1956 +++ .../debug_console_lite/fsl_debug_console.h | 260 + ...lity_assert_lite_LPC55S69_cm33_core0.cmake | 10 + ...lity_assert_lite_LPC55S69_cm33_core1.cmake | 10 + ...bug_console_lite_LPC55S69_cm33_core0.cmake | 17 + ...bug_console_lite_LPC55S69_cm33_core1.cmake | 17 + .../LPC55S6X/LPC55S6X/utilities/fsl_assert.c | 66 + .../LPC55S6X/LPC55S6X/utilities/fsl_memcpy.S | 279 + .../LPC55S6X/utilities/fsl_notifier.c | 209 + .../LPC55S6X/utilities/fsl_notifier.h | 237 + .../LPC55S6X/LPC55S6X/utilities/fsl_sbrk.c | 53 + .../LPC55S6X/LPC55S6X/utilities/fsl_shell.c | 1153 ++ .../LPC55S6X/LPC55S6X/utilities/fsl_shell.h | 337 + .../LPC55S6X/utilities/incbin/fsl_incbin.S | 37 + .../utility_incbin_LPC55S69_cm33_core0.cmake | 8 + .../LPC55S6X/LPC55S6X/utilities/str/fsl_str.c | 1638 ++ .../LPC55S6X/LPC55S6X/utilities/str/fsl_str.h | 66 + ...s_misc_utilities_LPC55S69_cm33_core0.cmake | 9 + ...s_misc_utilities_LPC55S69_cm33_core1.cmake | 9 + .../utility_assert_LPC55S69_cm33_core0.cmake | 10 + .../utility_assert_LPC55S69_cm33_core1.cmake | 10 + ...ty_debug_console_LPC55S69_cm33_core0.cmake | 19 + ...ty_debug_console_LPC55S69_cm33_core1.cmake | 19 + .../utility_shell_LPC55S69_cm33_core0.cmake | 19 + bsp/lpc55sxx/Libraries/LPC55S6X/SConscript | 14 +- .../components/codec/fsl_codec_common.c | 238 - .../components/codec/fsl_codec_common.h | 363 - .../components/codec/i2c/fsl_codec_i2c.c | 113 - .../components/codec/i2c/fsl_codec_i2c.h | 107 - .../components/codec/port/fsl_codec_adapter.h | 145 - .../codec/port/wm8904/fsl_codec_adapter.c | 245 - .../components/codec/wm8904/fsl_wm8904.c | 1092 -- .../components/codec/wm8904/fsl_wm8904.h | 496 - .../sdmmc/common/fsl_sdmmc_common.c | 166 + .../sdmmc/{inc => common}/fsl_sdmmc_common.h | 280 +- .../sdmmc/{inc => common}/fsl_sdmmc_spec.h | 277 +- .../sdmmc/host/sdif/ChangeLogKSDK.txt | 41 + .../sdmmc/host/sdif/blocking/fsl_sdmmc_host.c | 238 + .../sdmmc/host/sdif/fsl_sdmmc_host.h | 405 + .../host/sdif/non_blocking/fsl_sdmmc_host.c | 457 + .../LPC55S6X/middleware/sdmmc/inc/fsl_mmc.h | 321 - .../LPC55S6X/middleware/sdmmc/inc/fsl_sd.h | 315 - .../middleware/sdmmc/inc/fsl_sdmmc_host.h | 780 - .../middleware/sdmmc/mmc/ChangeLogKSDK.txt | 113 + .../LPC55S6X/middleware/sdmmc/mmc/fsl_mmc.c | 2998 ++++ .../LPC55S6X/middleware/sdmmc/mmc/fsl_mmc.h | 445 + .../middleware/sdmmc/osa/fsl_sdmmc_osa.c | 275 + .../middleware/sdmmc/osa/fsl_sdmmc_osa.h | 170 + .../middleware/sdmmc/port/fsl_sdmmc_event.h | 87 - .../port/sdif/freertos/fsl_sdmmc_event.c | 152 - .../sdmmc/port/sdif/freertos/fsl_sdmmc_host.c | 296 - .../port/sdif/interrupt/fsl_sdmmc_event.c | 143 - .../port/sdif/interrupt/fsl_sdmmc_host.c | 311 - .../sdmmc/port/sdif/polling/fsl_sdmmc_event.c | 142 - .../sdmmc/port/sdif/polling/fsl_sdmmc_host.c | 245 - .../port/sdif/rt_thread/fsl_sdmmc_event.c | 149 - .../port/sdif/rt_thread/fsl_sdmmc_host.c | 274 - .../middleware/sdmmc/sd/ChangeLogKSDK.txt | 123 + .../LPC55S6X/middleware/sdmmc/sd/fsl_sd.c | 2290 +++ .../LPC55S6X/middleware/sdmmc/sd/fsl_sd.h | 349 + .../middleware/sdmmc/sdio/ChangeLogKSDK.txt | 98 + .../LPC55S6X/middleware/sdmmc/sdio/fsl_sdio.c | 2109 +++ .../middleware/sdmmc/{inc => sdio}/fsl_sdio.h | 166 +- .../LPC55S6X/middleware/sdmmc/src/fsl_mmc.c | 2671 ---- .../LPC55S6X/middleware/sdmmc/src/fsl_sd.c | 1982 --- .../LPC55S6X/middleware/sdmmc/src/fsl_sdio.c | 1700 -- .../middleware/sdmmc/src/fsl_sdmmc_common.c | 393 - .../sdmmc/template/sdhc/sdmmc_config.c | 58 + .../sdmmc/template/sdhc/sdmmc_config.h | 101 + .../sdmmc/template/sdif/sdmmc_config.c | 115 + .../sdmmc/template/sdif/sdmmc_config.h | 92 + .../sdmmc/template/usdhc/sdmmc_config.c | 149 + .../sdmmc/template/usdhc/sdmmc_config.h | 115 + bsp/lpc55sxx/Libraries/drivers/drv_uart.c | 16 +- .../Libraries/template/lpc55s6xxxx/README.md | 2 + .../lpc55s69_nxp_evk/.vscode/launch.json | 16 - ..._mdk.scf => LPC55S69_cm33_core0_flash.scf} | 29 +- .../LPC55S69_cm33_core0_flash_ns_mdk.scf | 111 - bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvoptx | 1146 +- bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvprojx | 318 +- .../lpc55s69_nxp_evk/project_ns.uvoptx | 1867 --- .../lpc55s69_nxp_evk/project_ns.uvprojx | 1182 -- bsp/lpc55sxx/lpc55s69_nxp_evk/template.uvoptx | 2 +- .../lpc55s69_nxp_evk/template.uvprojx | 10 +- bsp/lpc55sxx/lpc55s69_nxp_evk_ns/.config | 828 - bsp/lpc55sxx/lpc55s69_nxp_evk_ns/Kconfig | 26 - bsp/lpc55sxx/lpc55s69_nxp_evk_ns/SConscript | 18 - bsp/lpc55sxx/lpc55s69_nxp_evk_ns/SConstruct | 65 - .../lpc55s69_nxp_evk_ns/project.uvoptx | 199 - .../lpc55s69_nxp_evk_ns/project.uvprojx | 1314 -- bsp/lpc55sxx/lpc55s69_nxp_evk_ns/rtconfig.h | 269 - bsp/lpc55sxx/lpc55s69_nxp_evk_ns/rtconfig.py | 161 - .../lpc55s69_nxp_evk_ns/template.uvoptx | 199 - .../lpc55s69_nxp_evk_ns/template.uvprojx | 391 - 293 files changed, 88210 insertions(+), 67512 deletions(-) rename bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/{ => Core}/Include/cmsis_armcc.h (94%) create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang.h rename bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/{Include/cmsis_armclang.h => Core/Include/cmsis_armclang_ltm.h} (93%) rename bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/{ => Core}/Include/cmsis_compiler.h (89%) rename bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/{ => Core}/Include/cmsis_gcc.h (86%) rename bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/{ => Core}/Include/cmsis_iccarm.h (85%) rename bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/{ => Core}/Include/cmsis_version.h (89%) rename bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/{ => Core}/Include/core_cm33.h (78%) rename bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/{ => Core}/Include/mpu_armv8.h (84%) rename bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/{ => Core}/Include/tz_context.h (100%) delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_common_tables.h delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_const_structs.h delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_math.h delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mbl.h delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mml.h delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_dsp.h delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/keil_lib_power_cm33_core0.lib delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/keil_lib_power_cm33_core0_disable_short_enum_wchar.lib delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/keil_lib_power_cm33_core0_s.lib delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/keil_lib_power_cm33_core0_s_disable_short_enum_wchar.lib delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/keil_lib_power_cm33_core1.lib delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/keil_lib_power_cm33_core1_disable_short_enum_wchar.lib delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0_ns.s create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_i2c_LPC55S69_cm33_core0.cmake create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_spi_LPC55S69_cm33_core0.cmake create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_usart_LPC55S69_cm33_core0.cmake create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_usart_cmsis.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_usart_cmsis.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_fro_calib.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_kbp.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_skboot_authenticate.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.h delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/libpower_hardabi.a delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/libpower_hardabi_s.a delete mode 100644 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bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_shell.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_shell.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/incbin/fsl_incbin.S create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/incbin/utility_incbin_LPC55S69_cm33_core0.cmake create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/str/fsl_str.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/str/fsl_str.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utilities_misc_utilities_LPC55S69_cm33_core0.cmake create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utilities_misc_utilities_LPC55S69_cm33_core1.cmake create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_assert_LPC55S69_cm33_core0.cmake create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_assert_LPC55S69_cm33_core1.cmake create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_debug_console_LPC55S69_cm33_core0.cmake create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_debug_console_LPC55S69_cm33_core1.cmake create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_shell_LPC55S69_cm33_core0.cmake delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.h delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.h delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/fsl_codec_adapter.h delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/wm8904/fsl_codec_adapter.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/common/fsl_sdmmc_common.c rename bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/{inc => common}/fsl_sdmmc_common.h (51%) rename bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/{inc => common}/fsl_sdmmc_spec.h (89%) create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/ChangeLogKSDK.txt create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/blocking/fsl_sdmmc_host.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/fsl_sdmmc_host.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/non_blocking/fsl_sdmmc_host.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_mmc.h delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sd.h delete mode 100644 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bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_host.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_event.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_host.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_event.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_host.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/ChangeLogKSDK.txt create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/fsl_sd.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/fsl_sd.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sdio/ChangeLogKSDK.txt create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sdio/fsl_sdio.c rename bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/{inc => sdio}/fsl_sdio.h (80%) delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_mmc.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sd.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdio.c delete mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdmmc_common.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdhc/sdmmc_config.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdhc/sdmmc_config.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdif/sdmmc_config.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdif/sdmmc_config.h create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/usdhc/sdmmc_config.c create mode 100644 bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/usdhc/sdmmc_config.h delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk/.vscode/launch.json rename bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/{LPC55S69_cm33_core0_flash_mdk.scf => LPC55S69_cm33_core0_flash.scf} (81%) delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvoptx delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk/project_ns.uvprojx delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk_ns/.config delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk_ns/Kconfig delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk_ns/SConscript delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk_ns/SConstruct delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk_ns/project.uvoptx delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk_ns/project.uvprojx delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk_ns/rtconfig.h delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk_ns/rtconfig.py delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk_ns/template.uvoptx delete mode 100644 bsp/lpc55sxx/lpc55s69_nxp_evk_ns/template.uvprojx diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armcc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armcc.h similarity index 94% rename from bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armcc.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armcc.h index 093d35b9e5..a955d47139 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armcc.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_armcc.h * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.3.2 + * @date 27. May 2021 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -46,7 +46,12 @@ /* __ARM_ARCH_8M_BASE__ not applicable */ /* __ARM_ARCH_8M_MAIN__ not applicable */ + /* __ARM_ARCH_8_1M_MAIN__ not applicable */ +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif /* CMSIS compiler specific defines */ #ifndef __ASM @@ -58,9 +63,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE static __forceinline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __declspec(noreturn) #endif @@ -100,284 +105,31 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() #endif -} +/* ######################### Startup and Lowlevel Init ######################## */ -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; +#ifndef __PROGRAM_START +#define __PROGRAM_START __main #endif -} -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif -/*@} end of CMSIS_Core_RegAccFunctions */ - +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface @@ -420,35 +172,23 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() do {\ - __schedule_barrier();\ - __isb(0xF);\ - __schedule_barrier();\ - } while (0U) +#define __ISB() __isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() do {\ - __schedule_barrier();\ - __dsb(0xF);\ - __schedule_barrier();\ - } while (0U) +#define __DSB() __dsb(0xF) /** \brief Data Memory Barrier \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() do {\ - __schedule_barrier();\ - __dmb(0xF);\ - __schedule_barrier();\ - } while (0U) +#define __DMB() __dmb(0xF) + - /** \brief Reverse byte order (32 bit) \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. @@ -786,6 +526,280 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @@ -863,6 +877,10 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint #define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ ((int64_t)(ARG3) << 32U) ) >> 32U)) +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ /*@} end of group CMSIS_SIMD_intrinsics */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang.h new file mode 100644 index 0000000000..6911417747 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armclang.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang_ltm.h similarity index 93% rename from bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armclang.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang_ltm.h index 5c4c20e877..1e255d5907 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_armclang.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_armclang_ltm.h @@ -1,11 +1,11 @@ /**************************************************************************//** - * @file cmsis_armclang.h + * @file cmsis_armclang_ltm.h * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.0.4 - * @date 10. January 2018 + * @version V1.5.3 + * @date 27. May 2021 ******************************************************************************/ /* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -29,10 +29,6 @@ #pragma clang system_header /* treat file as system include file */ -#ifndef __ARM_COMPAT_H -#include /* Compatibility header for Arm Compiler 5 intrinsics */ -#endif - /* CMSIS compiler specific defines */ #ifndef __ASM #define __ASM __asm @@ -43,9 +39,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static __inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif @@ -110,674 +106,52 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +/* ######################### Startup and Lowlevel Init ######################## */ -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); see arm_compat.h */ +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); see arm_compat.h */ +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL #endif -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; } #endif -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @@ -829,14 +203,14 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() __builtin_arm_isb(0xF); +#define __ISB() __builtin_arm_isb(0xF) /** \brief Data Synchronization Barrier \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() __builtin_arm_dsb(0xF); +#define __DSB() __builtin_arm_dsb(0xF) /** @@ -844,7 +218,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) \details Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() __builtin_arm_dmb(0xF); +#define __DMB() __builtin_arm_dmb(0xF) /** @@ -916,7 +290,23 @@ __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ (uint8_t)__builtin_clz +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -1185,7 +575,7 @@ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint8_t) result); } @@ -1200,7 +590,7 @@ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint16_t) result); } @@ -1215,7 +605,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return(result); } @@ -1228,7 +618,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } @@ -1240,7 +630,7 @@ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } @@ -1252,7 +642,7 @@ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } @@ -1321,6 +711,682 @@ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @@ -1837,31 +1903,16 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) return(result); } -#if 0 -#define __PKHBT(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) -#endif - #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_compiler.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_compiler.h similarity index 89% rename from bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_compiler.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_compiler.h index 94212eb87a..adbf296f15 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_compiler.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_compiler.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_compiler.h * @brief CMSIS compiler generic header file - * @version V5.0.4 - * @date 10. January 2018 + * @version V5.1.0 + * @date 09. October 2018 ******************************************************************************/ /* * Copyright (c) 2009-2018 Arm Limited. All rights reserved. @@ -35,9 +35,15 @@ /* - * Arm Compiler 6 (armclang) + * Arm Compiler 6.6 LTM (armclang) */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) #include "cmsis_armclang.h" @@ -115,8 +121,11 @@ #define __ALIGNED(x) __attribute__((aligned(x))) #endif #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 #endif @@ -187,6 +196,10 @@ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif /* @@ -255,6 +268,10 @@ #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. #define __RESTRICT #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif #else diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_gcc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_gcc.h similarity index 86% rename from bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_gcc.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_gcc.h index 5d0f07e8ac..67bda4ef3c 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_gcc.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_gcc.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file - * @version V5.0.3 - * @date 16. January 2018 + * @version V5.4.1 + * @date 27. May 2021 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -46,9 +46,9 @@ #ifndef __STATIC_INLINE #define __STATIC_INLINE static inline #endif -#ifndef __STATIC_FORCEINLINE +#ifndef __STATIC_FORCEINLINE #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif +#endif #ifndef __NO_RETURN #define __NO_RETURN __attribute__((__noreturn__)) #endif @@ -113,706 +113,95 @@ #ifndef __RESTRICT #define __RESTRICT __restrict #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif +/* ######################### Startup and Lowlevel Init ######################## */ -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ +#ifndef __PROGRAM_START /** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing the I-bit in the CPSR. - Can only be executed in Privileged modes. + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + */ -__STATIC_FORCEINLINE void __enable_irq(void) +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) { - __ASM volatile ("cpsie i" : : : "memory"); + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); } +#define __PROGRAM_START __cmsis_start +#endif -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting the I-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL #endif -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; } #endif -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - register uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting the F-bit in the CPSR. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - register uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - -#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - /* ########################## Core Instruction Access ######################### */ /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface Access to dedicated instructions @@ -842,7 +231,7 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) \brief Wait For Interrupt \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -#define __WFI() __ASM volatile ("wfi") +#define __WFI() __ASM volatile ("wfi":::"memory") /** @@ -850,7 +239,7 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) \details Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -#define __WFE() __ASM volatile ("wfe") +#define __WFE() __ASM volatile ("wfe":::"memory") /** @@ -907,7 +296,7 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) #else uint32_t result; - __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } @@ -923,7 +312,7 @@ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) { uint32_t result; - __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; } @@ -941,7 +330,7 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) #else int16_t result; - __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); return result; #endif } @@ -988,7 +377,7 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); #else uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ @@ -1011,7 +400,23 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) \param [in] value Value to count the leading zeros \return number of leading zeros in value */ -#define __CLZ (uint8_t)__builtin_clz +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ @@ -1153,11 +558,11 @@ __STATIC_FORCEINLINE void __CLREX(void) \param [in] ARG2 Bit position to saturate to (1..32) \return Saturated value */ -#define __SSAT(ARG1,ARG2) \ +#define __SSAT(ARG1, ARG2) \ __extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) @@ -1169,11 +574,11 @@ __extension__ \ \param [in] ARG2 Bit position to saturate to (0..31) \return Saturated value */ -#define __USAT(ARG1,ARG2) \ - __extension__ \ +#define __USAT(ARG1, ARG2) \ +__extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) @@ -1358,7 +763,7 @@ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t result; - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint8_t) result); } @@ -1373,7 +778,7 @@ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t result; - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint16_t) result); } @@ -1388,7 +793,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) { uint32_t result; - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return(result); } @@ -1401,7 +806,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) */ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } @@ -1413,7 +818,7 @@ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) */ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) { - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } @@ -1425,7 +830,7 @@ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) */ __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) { - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); } @@ -1439,7 +844,7 @@ __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t result; - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint8_t) result); } @@ -1454,7 +859,7 @@ __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t result; - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return ((uint16_t) result); } @@ -1469,7 +874,7 @@ __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t result; - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); return(result); } @@ -1486,7 +891,7 @@ __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t result; - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); return(result); } @@ -1503,7 +908,7 @@ __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t result; - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); return(result); } @@ -1520,7 +925,7 @@ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t result; - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); return(result); } @@ -1530,6 +935,703 @@ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + /* ################### Compiler specific Intrinsics ########################### */ /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics Access to dedicated SIMD instructions @@ -1550,7 +1652,7 @@ __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1558,7 +1660,7 @@ __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1574,7 +1676,7 @@ __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1582,7 +1684,7 @@ __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1599,7 +1701,7 @@ __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1607,7 +1709,7 @@ __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1623,7 +1725,7 @@ __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1631,7 +1733,7 @@ __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1648,7 +1750,7 @@ __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1656,7 +1758,7 @@ __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1672,7 +1774,7 @@ __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1680,7 +1782,7 @@ __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1696,7 +1798,7 @@ __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1704,7 +1806,7 @@ __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1720,7 +1822,7 @@ __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1728,7 +1830,7 @@ __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1744,7 +1846,7 @@ __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1752,7 +1854,7 @@ __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1768,7 +1870,7 @@ __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1776,7 +1878,7 @@ __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1792,7 +1894,7 @@ __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1800,7 +1902,7 @@ __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1816,7 +1918,7 @@ __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1824,7 +1926,7 @@ __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1832,7 +1934,7 @@ __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1840,21 +1942,23 @@ __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) { uint32_t result; - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); return(result); } -#define __SSAT16(ARG1,ARG2) \ +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ ({ \ int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) -#define __USAT16(ARG1,ARG2) \ +#define __USAT16(ARG1, ARG2) \ +__extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ __RES; \ }) @@ -1862,7 +1966,7 @@ __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) { uint32_t result; - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } @@ -1870,7 +1974,7 @@ __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } @@ -1878,18 +1982,41 @@ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) { uint32_t result; - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); return(result); } +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + __STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) { uint32_t result; - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); return(result); } +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + __STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) { uint32_t result; @@ -2046,8 +2173,9 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) return(result); } -#if 0 + #define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ @@ -2055,6 +2183,7 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) }) #define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ ({ \ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ if (ARG3 == 0) \ @@ -2063,19 +2192,13 @@ __STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ __RES; \ }) -#endif -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) { int32_t result; - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); return(result); } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_iccarm.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_iccarm.h similarity index 85% rename from bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_iccarm.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_iccarm.h index edcaee3d4a..65b824b009 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_iccarm.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_iccarm.h @@ -1,13 +1,16 @@ /**************************************************************************//** * @file cmsis_iccarm.h * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.0.5 - * @date 10. January 2018 + * @version V5.3.0 + * @date 14. April 2021 ******************************************************************************/ //------------------------------------------------------------------------------ // -// Copyright (c) 2017-2018 IAR Systems +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 // // Licensed under the Apache License, Version 2.0 (the "License") // you may not use this file except in compliance with the License. @@ -110,6 +113,10 @@ #define __ASM __asm #endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + #ifndef __INLINE #define __INLINE inline #endif @@ -150,7 +157,12 @@ #endif #ifndef __RESTRICT - #define __RESTRICT restrict + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif #endif #ifndef __STATIC_INLINE @@ -226,6 +238,7 @@ __packed struct __iar_u32 { uint32_t v; }; #endif #endif +#undef __WEAK /* undo the definition from DLib_Defaults.h */ #ifndef __WEAK #if __ICCARM_V8 #define __WEAK __attribute__((weak)) @@ -234,6 +247,43 @@ __packed struct __iar_u32 { uint32_t v; }; #endif #endif +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif #ifndef __ICCARM_INTRINSICS_VERSION__ #define __ICCARM_INTRINSICS_VERSION__ 0 @@ -305,7 +355,13 @@ __packed struct __iar_u32 { uint32_t v; }; #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) @@ -327,7 +383,13 @@ __packed struct __iar_u32 { uint32_t v; }; #endif #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) @@ -340,8 +402,17 @@ __packed struct __iar_u32 { uint32_t v; }; #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) @@ -558,7 +629,7 @@ __packed struct __iar_u32 { uint32_t v; }; __IAR_FT uint32_t __RRX(uint32_t value) { uint32_t result; - __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); return(result); } @@ -640,6 +711,7 @@ __packed struct __iar_u32 { uint32_t v; }; __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) { __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); } __IAR_FT uint32_t __TZ_get_PSP_NS(void) @@ -716,12 +788,25 @@ __packed struct __iar_u32 { uint32_t v; }; __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) { uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif return res; } + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif } __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) @@ -784,37 +869,37 @@ __packed struct __iar_u32 { uint32_t v; }; __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t res; - __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t res; - __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) { uint32_t res; - __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); return res; } __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) { - __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) { - __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); } __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) { - __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); } #endif /* (__CORTEX_M >= 0x03) */ @@ -826,78 +911,78 @@ __packed struct __iar_u32 { uint32_t v; }; __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) { uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) { uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) { uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) { - __ASM volatile ("STLB %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) { - __ASM volatile ("STLH %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) { - __ASM volatile ("STL %1, [%0]" :: "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); } __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) { uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint8_t)res); } __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) { uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return ((uint16_t)res); } __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) { uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (*ptr) : "memory"); + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); return res; } __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) { uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) { uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) { uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (*ptr), "r" (value) : "memory"); + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); return res; } @@ -910,4 +995,8 @@ __packed struct __iar_u32 { uint32_t v; }; #pragma diag_default=Pe940 #pragma diag_default=Pe177 +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + #endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_version.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_version.h similarity index 89% rename from bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_version.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_version.h index 660f612aa3..2f048e4552 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/cmsis_version.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/cmsis_version.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file cmsis_version.h * @brief CMSIS Core(M) Version definitions - * @version V5.0.2 - * @date 19. April 2017 + * @version V5.0.4 + * @date 23. July 2019 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ /* CMSIS Version definitions */ #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */ #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_cm33.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/core_cm33.h similarity index 78% rename from bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_cm33.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/core_cm33.h index b1efbcae7c..f9cf6ab183 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_cm33.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/core_cm33.h @@ -1,11 +1,11 @@ /**************************************************************************//** * @file core_cm33.h * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.0.5 - * @date 08. January 2018 + * @version V5.2.2 + * @date 04. June 2021 ******************************************************************************/ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -23,9 +23,11 @@ */ #if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ + #pragma system_include /* treat file as system include file for MISRA check */ #elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ #endif #ifndef __CORE_CM33_H_GENERIC @@ -61,14 +63,14 @@ */ #include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ -#define __CORTEX_M (33U) /*!< Cortex-M Core */ +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. @@ -90,14 +92,14 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U #endif #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_PCS_VFP) + #if defined (__ARM_FP) #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) #define __FPU_USED 1U #else @@ -113,7 +115,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -136,7 +138,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -159,7 +161,7 @@ #define __DSP_USED 1U #else #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U + #define __DSP_USED 0U #endif #else #define __DSP_USED 0U @@ -248,6 +250,11 @@ #warning "__DSP_PRESENT not defined in device header file; using default!" #endif + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + #ifndef __NVIC_PRIO_BITS #define __NVIC_PRIO_BITS 3U #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" @@ -538,14 +545,7 @@ typedef struct __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ } SCB_Type; /* SCB CPUID Register Definitions */ @@ -568,6 +568,9 @@ typedef struct #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ @@ -743,22 +746,22 @@ typedef struct #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ @@ -918,78 +921,6 @@ typedef struct #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - /*@} end of group CMSIS_SCB */ @@ -1094,10 +1025,7 @@ typedef struct __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ uint32_t RESERVED2[15U]; __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED3[32U]; uint32_t RESERVED4[43U]; __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ @@ -1160,18 +1088,6 @@ typedef struct #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ @@ -1383,7 +1299,7 @@ typedef struct */ typedef struct { - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ uint32_t RESERVED0[2U]; __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ @@ -1392,29 +1308,26 @@ typedef struct uint32_t RESERVED2[131U]; __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ uint32_t RESERVED5[39U]; __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ } TPI_Type; /* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< @Deprecated TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< @Deprecated TPI ACPR: PRESCALER Mask */ - -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ @@ -1437,6 +1350,9 @@ typedef struct #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ @@ -1444,61 +1360,79 @@ typedef struct #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ @@ -1510,22 +1444,19 @@ typedef struct #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1590,8 +1521,8 @@ typedef struct #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ @@ -1745,8 +1676,9 @@ typedef struct __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ } FPU_Type; /* Floating-Point Context Control Register Definitions */ @@ -1818,7 +1750,7 @@ typedef struct #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ -/* Media and FP Feature Register 0 Definitions */ +/* Media and VFP Feature Register 0 Definitions */ #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ @@ -1843,7 +1775,7 @@ typedef struct #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ -/* Media and FP Feature Register 1 Definitions */ +/* Media and VFP Feature Register 1 Definitions */ #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ @@ -1856,9 +1788,13 @@ typedef struct #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + /*@} end of group CMSIS_FPU */ - +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ /** \ingroup CMSIS_core_register \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) @@ -1867,7 +1803,7 @@ typedef struct */ /** - \brief Structure type to access the Core Debug Register (CoreDebug). + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). */ typedef struct { @@ -1875,124 +1811,354 @@ typedef struct __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; + uint32_t RESERVED0[1U]; __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ } CoreDebug_Type; /* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ /* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ /* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ /*@} end of group CMSIS_CoreDebug */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + /** \ingroup CMSIS_core_register \defgroup CMSIS_core_bitfield Core register bit field macros @@ -2031,7 +2197,9 @@ typedef struct #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ @@ -2043,7 +2211,9 @@ typedef struct #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ @@ -2060,7 +2230,9 @@ typedef struct #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ @@ -2069,7 +2241,9 @@ typedef struct #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ @@ -2139,6 +2313,27 @@ typedef struct #define NVIC_USER_IRQ_OFFSET 16 +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + /** \brief Set Priority Grouping @@ -2158,7 +2353,7 @@ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */ + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ SCB->AIRCR = reg_value; } @@ -2184,7 +2379,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { if ((int32_t)(IRQn) >= 0) { + __COMPILER_BARRIER(); NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); } } @@ -2476,6 +2673,7 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { uint32_t *vectors = (uint32_t *)SCB->VTOR; vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); } @@ -2498,7 +2696,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) \brief System Reset \details Initiates a system reset request to reset the MCU. */ -__STATIC_INLINE void __NVIC_SystemReset(void) +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ @@ -2802,6 +3000,110 @@ __STATIC_INLINE void TZ_SAU_Disable(void) +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + /* ################################## SysTick function ############################################ */ /** \ingroup CMSIS_Core_FunctionInterface diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/mpu_armv8.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/mpu_armv8.h similarity index 84% rename from bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/mpu_armv8.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/mpu_armv8.h index 0ccfc74fe5..3de16efc86 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/mpu_armv8.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/mpu_armv8.h @@ -1,11 +1,11 @@ /****************************************************************************** * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M MPU - * @version V5.0.4 - * @date 10. January 2018 + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 ******************************************************************************/ /* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -44,7 +44,7 @@ * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. */ #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) @@ -62,7 +62,7 @@ * \param O Outer memory attributes * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes */ -#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) /** \brief Normal memory non-shareable */ #define ARM_MPU_SH_NON (0U) @@ -77,7 +77,7 @@ * \param RO Read-Only: Set to 1 for read-only memory. * \param NP Non-Privileged: Set to 1 for non-privileged memory. */ -#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) /** \brief Region Base Address Register value * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. @@ -87,20 +87,35 @@ * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. */ #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - ((BASE & MPU_RBAR_BASE_Pos) | \ - ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) /** \brief Region Limit Address Register value * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. * \param IDX The attribute index to be associated with this memory region. */ #define ARM_MPU_RLAR(LIMIT, IDX) \ - ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ - ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ (MPU_RLAR_EN_Msk)) +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + /** * Struct for a single MPU Region */ @@ -114,24 +129,26 @@ typedef struct { */ __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) { - __DSB(); - __ISB(); + __DMB(); MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif + __DSB(); + __ISB(); } /** Disable the MPU. */ __STATIC_INLINE void ARM_MPU_Disable(void) { - __DSB(); - __ISB(); + __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); } #ifdef MPU_NS @@ -140,24 +157,26 @@ __STATIC_INLINE void ARM_MPU_Disable(void) */ __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) { - __DSB(); - __ISB(); + __DMB(); MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; #endif + __DSB(); + __ISB(); } /** Disable the Non-secure MPU. */ __STATIC_INLINE void ARM_MPU_Disable_NS(void) { - __DSB(); - __ISB(); + __DMB(); #ifdef SCB_SHCSR_MEMFAULTENA_Msk SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; #endif MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); } #endif @@ -262,12 +281,12 @@ __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t } #endif -/** Memcopy with strictly ordered memory access, e.g. for register targets. +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() * \param dst Destination data is copied to. * \param src Source data is copied from. * \param len Amount of data words to be copied. */ -__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) { uint32_t i; for (i = 0U; i < len; ++i) @@ -287,7 +306,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { mpu->RNR = rnr; - orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); } else { uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; @@ -295,7 +314,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ mpu->RNR = rnrBase; while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); table += c; cnt -= c; rnrOffset = 0U; @@ -303,7 +322,7 @@ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_ mpu->RNR = rnrBase; } - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/tz_context.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/tz_context.h similarity index 100% rename from bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/tz_context.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Core/Include/tz_context.h diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_common_tables.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_common_tables.h deleted file mode 100644 index dfea7460e9..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_common_tables.h +++ /dev/null @@ -1,121 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_common_tables.h - * Description: Extern declaration for common tables - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_COMMON_TABLES_H -#define _ARM_COMMON_TABLES_H - -#include "arm_math.h" - -extern const uint16_t armBitRevTable[1024]; -extern const q15_t armRecipTableQ15[64]; -extern const q31_t armRecipTableQ31[64]; -extern const float32_t twiddleCoef_16[32]; -extern const float32_t twiddleCoef_32[64]; -extern const float32_t twiddleCoef_64[128]; -extern const float32_t twiddleCoef_128[256]; -extern const float32_t twiddleCoef_256[512]; -extern const float32_t twiddleCoef_512[1024]; -extern const float32_t twiddleCoef_1024[2048]; -extern const float32_t twiddleCoef_2048[4096]; -extern const float32_t twiddleCoef_4096[8192]; -#define twiddleCoef twiddleCoef_4096 -extern const q31_t twiddleCoef_16_q31[24]; -extern const q31_t twiddleCoef_32_q31[48]; -extern const q31_t twiddleCoef_64_q31[96]; -extern const q31_t twiddleCoef_128_q31[192]; -extern const q31_t twiddleCoef_256_q31[384]; -extern const q31_t twiddleCoef_512_q31[768]; -extern const q31_t twiddleCoef_1024_q31[1536]; -extern const q31_t twiddleCoef_2048_q31[3072]; -extern const q31_t twiddleCoef_4096_q31[6144]; -extern const q15_t twiddleCoef_16_q15[24]; -extern const q15_t twiddleCoef_32_q15[48]; -extern const q15_t twiddleCoef_64_q15[96]; -extern const q15_t twiddleCoef_128_q15[192]; -extern const q15_t twiddleCoef_256_q15[384]; -extern const q15_t twiddleCoef_512_q15[768]; -extern const q15_t twiddleCoef_1024_q15[1536]; -extern const q15_t twiddleCoef_2048_q15[3072]; -extern const q15_t twiddleCoef_4096_q15[6144]; -extern const float32_t twiddleCoef_rfft_32[32]; -extern const float32_t twiddleCoef_rfft_64[64]; -extern const float32_t twiddleCoef_rfft_128[128]; -extern const float32_t twiddleCoef_rfft_256[256]; -extern const float32_t twiddleCoef_rfft_512[512]; -extern const float32_t twiddleCoef_rfft_1024[1024]; -extern const float32_t twiddleCoef_rfft_2048[2048]; -extern const float32_t twiddleCoef_rfft_4096[4096]; - -/* floating-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20) -#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48) -#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) -#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) -#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) -#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800) -#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808) -#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH]; - -/* fixed-point bit reversal tables */ -#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12) -#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24) -#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56) -#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112) -#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240) -#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480) -#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992) -#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984) -#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032) - -extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH]; -extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH]; - -/* Tables for Fast Math Sine and Cosine */ -extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; -extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; -extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; - -#endif /* ARM_COMMON_TABLES_H */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_const_structs.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_const_structs.h deleted file mode 100644 index 80a3e8bbe7..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_const_structs.h +++ /dev/null @@ -1,66 +0,0 @@ -/* ---------------------------------------------------------------------- - * Project: CMSIS DSP Library - * Title: arm_const_structs.h - * Description: Constant structs that are initialized for user convenience. - * For example, some can be given as arguments to the arm_cfft_f32() function. - * - * $Date: 27. January 2017 - * $Revision: V.1.5.1 - * - * Target Processor: Cortex-M cores - * -------------------------------------------------------------------- */ -/* - * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef _ARM_CONST_STRUCTS_H -#define _ARM_CONST_STRUCTS_H - -#include "arm_math.h" -#include "arm_common_tables.h" - - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; - extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; - - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048; - extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096; - - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048; - extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096; - -#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_math.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_math.h deleted file mode 100644 index 62f87bec87..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7160 +0,0 @@ -/****************************************************************************** - * @file arm_math.h - * @brief Public header file for CMSIS DSP LibraryU - * @version V1.5.3 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2010-2018 Arm Limited or its affiliates. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM7lfdp_math.lib (Cortex-M7, Little endian, Double Precision Floating Point Unit) - * - arm_cortexM7bfdp_math.lib (Cortex-M7, Big endian, Double Precision Floating Point Unit) - * - arm_cortexM7lfsp_math.lib (Cortex-M7, Little endian, Single Precision Floating Point Unit) - * - arm_cortexM7bfsp_math.lib (Cortex-M7, Big endian and Single Precision Floating Point Unit on) - * - arm_cortexM7l_math.lib (Cortex-M7, Little endian) - * - arm_cortexM7b_math.lib (Cortex-M7, Big endian) - * - arm_cortexM4lf_math.lib (Cortex-M4, Little endian, Floating Point Unit) - * - arm_cortexM4bf_math.lib (Cortex-M4, Big endian, Floating Point Unit) - * - arm_cortexM4l_math.lib (Cortex-M4, Little endian) - * - arm_cortexM4b_math.lib (Cortex-M4, Big endian) - * - arm_cortexM3l_math.lib (Cortex-M3, Little endian) - * - arm_cortexM3b_math.lib (Cortex-M3, Big endian) - * - arm_cortexM0l_math.lib (Cortex-M0 / Cortex-M0+, Little endian) - * - arm_cortexM0b_math.lib (Cortex-M0 / Cortex-M0+, Big endian) - * - arm_ARMv8MBLl_math.lib (Armv8-M Baseline, Little endian) - * - arm_ARMv8MMLl_math.lib (Armv8-M Mainline, Little endian) - * - arm_ARMv8MMLlfsp_math.lib (Armv8-M Mainline, Little endian, Single Precision Floating Point Unit) - * - arm_ARMv8MMLld_math.lib (Armv8-M Mainline, Little endian, DSP instructions) - * - arm_ARMv8MMLldfsp_math.lib (Armv8-M Mainline, Little endian, DSP instructions, Single Precision Floating Point Unit) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M cores with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate preprocessor macro ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * For Armv8-M cores define preprocessor macro ARM_MATH_ARMV8MBL or ARM_MATH_ARMV8MML. - * Set preprocessor macro __DSP_PRESENT if Armv8-M Mainline core supports DSP instructions. - * - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK version 5.14.0.0 - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to rebuild libraries on MDK toolchain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvprojx - * - * - * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional preprocessor macros detailed above. - * - * Preprocessor Macros - * ------------ - * - * Each library project have different preprocessor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and - * ARM_MATH_CM7 for building the library on cortex-M7. - * - * - ARM_MATH_ARMV8MxL: - * - * Define macro ARM_MATH_ARMV8MBL for building the library on Armv8-M Baseline target, ARM_MATH_ARMV8MML for building library - * on Armv8-M Mainline target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for floating point libraries. - * - * - __DSP_PRESENT: - * - * Initialize macro __DSP_PRESENT = 1 when Armv8-M Mainline core supports DSP instructions. - * - *
- * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
- * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2015 Arm Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
- *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
- * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
- *     pData[i*numCols + j]
- *
- * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
- * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
- * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
- *     ARM_MATH_SIZE_MISMATCH
- *
- * Otherwise the functions return - * 
- *     ARM_MATH_SUCCESS
- *
- * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
- *     ARM_MATH_MATRIX_CHECK
- *
- * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -/* Compiler specific diagnostic adjustment */ -#if defined ( __CC_ARM ) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - -#elif defined ( __GNUC__ ) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -#elif defined ( __ICCARM__ ) - -#elif defined ( __TI_ARM__ ) - -#elif defined ( __CSMC__ ) - -#elif defined ( __TASKING__ ) - -#else - #error Unknown compiler -#endif - - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined(ARM_MATH_CM7) - #include "core_cm7.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM4) - #include "core_cm4.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM33) - #include "core_cm33.h" - #define ARM_MATH_DSP -#elif defined (ARM_MATH_CM3) - #include "core_cm3.h" -#elif defined (ARM_MATH_CM0) - #include "core_cm0.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) - #include "core_cm0plus.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MBL) - #include "core_armv8mbl.h" - #define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_ARMV8MML) - #include "core_armv8mml.h" - #if (defined (__DSP_PRESENT) && (__DSP_PRESENT == 1)) - #define ARM_MATH_DSP - #endif -#else - #error "Define according the used Cortex core ARM_MATH_CM7, ARM_MATH_CM4, ARM_MATH_CM3, ARM_MATH_CM0PLUS, ARM_MATH_CM0, ARM_MATH_ARMV8MBL, ARM_MATH_ARMV8MML" -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI - #define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined ( __CC_ARM ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __GNUC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE __attribute__((always_inline)) - -#elif defined ( __ICCARM__ ) - #define __SIMD32_TYPE int32_t __packed - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TI_ARM__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED __attribute__((unused)) - #define CMSIS_INLINE - -#elif defined ( __CSMC__ ) - #define __SIMD32_TYPE int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#elif defined ( __TASKING__ ) - #define __SIMD32_TYPE __unaligned int32_t - #define CMSIS_UNUSED - #define CMSIS_INLINE - -#else - #error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if !defined (ARM_MATH_DSP) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif /* !defined (ARM_MATH_DSP) */ - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - CMSIS_INLINE __STATIC_INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - CMSIS_INLINE __STATIC_INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - CMSIS_INLINE __STATIC_INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - CMSIS_INLINE __STATIC_INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - q31_t out; - uint32_t tempVal; - uint32_t index, i; - uint32_t signBits; - - if (in > 0) - { - signBits = ((uint32_t) (__CLZ( in) - 1)); - } - else - { - signBits = ((uint32_t) (__CLZ(-in) - 1)); - } - - /* Convert input sample to 1.31 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 24); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0U; i < 2U; i++) - { - tempVal = (uint32_t) (((q63_t) in * out) >> 31); - tempVal = 0x7FFFFFFFu - tempVal; - /* 1.31 with exp 1 */ - /* out = (q31_t) (((q63_t) out * tempVal) >> 30); */ - out = clip_q63_to_q31(((q63_t) out * tempVal) >> 30); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1U); - } - - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - CMSIS_INLINE __STATIC_INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - q15_t out = 0; - uint32_t tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if (in > 0) - { - signBits = ((uint32_t)(__CLZ( in) - 17)); - } - else - { - signBits = ((uint32_t)(__CLZ(-in) - 17)); - } - - /* Convert input sample to 1.15 format */ - in = (in << signBits); - - /* calculation of index for initial approximated Val */ - index = (uint32_t)(in >> 8); - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0U; i < 2U; i++) - { - tempVal = (uint32_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFFu - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - /* out = clip_q31_to_q15(((q31_t) out * tempVal) >> 14); */ - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - } - - -/* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if !defined (ARM_MATH_DSP) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) + (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) + (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) + (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) + (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB8( - uint32_t x, - uint32_t y) - { - q31_t r, s, t, u; - - r = __SSAT(((((q31_t)x << 24) >> 24) - (((q31_t)y << 24) >> 24)), 8) & (int32_t)0x000000FF; - s = __SSAT(((((q31_t)x << 16) >> 24) - (((q31_t)y << 16) >> 24)), 8) & (int32_t)0x000000FF; - t = __SSAT(((((q31_t)x << 8) >> 24) - (((q31_t)y << 8) >> 24)), 8) & (int32_t)0x000000FF; - u = __SSAT(((((q31_t)x ) >> 24) - (((q31_t)y ) >> 24)), 8) & (int32_t)0x000000FF; - - return ((uint32_t)((u << 24) | (t << 16) | (s << 8) | (r ))); - } - - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QADD16( - uint32_t x, - uint32_t y) - { -/* q31_t r, s; without initialisation 'arm_offset_q15 test' fails but 'intrinsic' tests pass! for armCC */ - q31_t r = 0, s = 0; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHADD16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSUB16( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHASX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) - (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) + (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __QSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = __SSAT(((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)), 16) & (int32_t)0x0000FFFF; - s = __SSAT(((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)), 16) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SHSAX( - uint32_t x, - uint32_t y) - { - q31_t r, s; - - r = (((((q31_t)x << 16) >> 16) + (((q31_t)y ) >> 16)) >> 1) & (int32_t)0x0000FFFF; - s = (((((q31_t)x ) >> 16) - (((q31_t)y << 16) >> 16)) >> 1) & (int32_t)0x0000FFFF; - - return ((uint32_t)((s << 16) | (r ))); - } - - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSDX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUADX( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) )); - } - - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QADD( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x + (q31_t)y))); - } - - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __QSUB( - int32_t x, - int32_t y) - { - return ((int32_t)(clip_q63_to_q31((q63_t)x - (q31_t)y))); - } - - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLAD( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLADX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMLSDX( - uint32_t x, - uint32_t y, - uint32_t sum) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q31_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALD( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + ((q15_t) x * (q15_t) y)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint64_t __SMLALDX( - uint32_t x, - uint32_t y, - uint64_t sum) - { -/* return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + ((q15_t) x * (q15_t) (y >> 16)); */ - return ((uint64_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y ) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y << 16) >> 16)) + - ( ((q63_t)sum ) ) )); - } - - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUAD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) + - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SMUSD( - uint32_t x, - uint32_t y) - { - return ((uint32_t)(((((q31_t)x << 16) >> 16) * (((q31_t)y << 16) >> 16)) - - ((((q31_t)x ) >> 16) * (((q31_t)y ) >> 16)) )); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE uint32_t __SXTB16( - uint32_t x) - { - return ((uint32_t)(((((q31_t)x << 24) >> 24) & (q31_t)0x0000FFFF) | - ((((q31_t)x << 8) >> 8) & (q31_t)0xFFFF0000) )); - } - - /* - * @brief C custom defined SMMLA for M3 and M0 processors - */ - CMSIS_INLINE __STATIC_INLINE int32_t __SMMLA( - int32_t x, - int32_t y, - int32_t sum) - { - return (sum + (int32_t) (((int64_t) x * y) >> 32)); - } - -#endif /* !defined (ARM_MATH_DSP) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] S points to an instance of the Q7 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] S points to an instance of the Q15 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] S points to an instance of the Q31 FIR filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] S points to an instance of the floating-point FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q15; - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_casd_df1_inst_f32; - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float64_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f64; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_q31; - - - /** - * @brief Floating-point matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix addition. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix transpose. - * @param[in] pSrc points to the input matrix - * @param[out] pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @param[in] pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - - /** - * @brief Q31 matrix multiplication - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix subtraction - * @param[in] pSrcA points to the first input matrix structure - * @param[in] pSrcB points to the second input matrix structure - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix scaling. - * @param[in] pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - - /** - * @brief Q31 matrix scaling. - * @param[in] pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - - /** - * @brief Q15 matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] pData points to the matrix data array. - */ - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#if !defined (ARM_MATH_DSP) - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] S points to an instance of the q15 PID Control structure - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector multiplication. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - -/* Deprecated */ - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - -/* Deprecated */ - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q15_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q15; - -void arm_cfft_q15( - const arm_cfft_instance_q15 * S, - q15_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the fixed-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_q31; - -void arm_cfft_q31( - const arm_cfft_instance_q31 * S, - q31_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - const arm_cfft_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] S points to an instance of the Q31 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] S points to an instance of the Q15 DCT4 structure. - * @param[in] pState points to state buffer. - * @param[in,out] pInlineBuffer points to the in-place input and output buffer. - */ - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - - /** - * @brief Floating-point vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector addition. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector subtraction. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in each vector - */ - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q7 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Floating-point vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q15 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Q31 vector absolute value. - * @param[in] pSrc points to the input buffer - * @param[out] pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - */ - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Dot product of floating-point vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - - /** - * @brief Dot product of Q7 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - - /** - * @brief Dot product of Q15 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Dot product of Q31 vectors. - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] result output result returned here - */ - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] blockSize number of samples in the vector - */ - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - */ - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - */ - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length srcALen+srcBLen-1. - */ - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_f32; - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] S points to an instance of the floating-point FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q15 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] S points to an instance of the Q31 FIR decimator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] S points to an instance of the Q15 FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] pCoeffs points to the filter coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - */ - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_stereo_df2T_instance_f32; - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float64_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float64_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f64; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. 2 channels - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_stereo_df2T_f32( - const arm_biquad_cascade_stereo_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] S points to an instance of the filter data structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_biquad_cascade_df2T_f64( - const arm_biquad_cascade_df2T_instance_f64 * S, - float64_t * pSrc, - float64_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_stereo_df2T_init_f32( - arm_biquad_cascade_stereo_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] pCoeffs points to the filter coefficients. - * @param[in] pState points to the state buffer. - */ - void arm_biquad_cascade_df2T_init_f64( - arm_biquad_cascade_df2T_instance_f64 * S, - uint8_t numStages, - float64_t * pCoeffs, - float64_t * pState); - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] S points to an instance of the Q15 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] S points to an instance of the Q31 FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] pState points to the state buffer. The array is of length numStages. - */ - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] S points to an instance of the floating-point FIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] blockSize number of samples to process. - */ - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the Q15 IIR lattice structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - */ - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - */ - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to the coefficient buffer. - * @param[in] pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q31; - - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] S points to an instance of the Q15 LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] pSrc points to the block of input data. - * @param[in] pRef points to the block of reference data. - * @param[out] pOut points to the block of output data. - * @param[out] pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - */ - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] pCoeffs points to coefficient buffer. - * @param[in] pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - */ - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - - /** - * @brief Correlation of floating-point sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - */ - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q31 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - */ - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - */ - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] S points to an instance of the floating-point sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] S points to an instance of the Q31 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] S points to an instance of the Q15 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] S points to an instance of the Q7 sparse FIR structure. - * @param[in] pSrc points to the block of input data. - * @param[out] pDst points to the block of output data - * @param[in] pScratchIn points to a temporary buffer of size blockSize. - * @param[in] pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - */ - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] pCoeffs points to the array of filter coefficients. - * @param[in] pState points to the state buffer. - * @param[in] pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - */ - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /** - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cos output. - */ - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCosVal); - - - /** - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] pSinVal points to the processed sine output. - * @param[out] pCosVal points to the processed cosine output. - */ - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex conjugate. - * @param[in] pSrc points to the input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude squared - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
-   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
- * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31U); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#if defined (ARM_MATH_DSP) - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD((uint32_t)S->A0, (uint32_t)in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = (q63_t)__SMLALD((uint32_t)S->A1, (uint32_t)*vstate, (uint64_t)acc); -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - /** - * @brief Floating-point matrix inverse. - * @param[in] src points to the instance of the input floating-point matrix structure. - * @param[out] dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - arm_status arm_mat_inverse_f64( - const arm_matrix_instance_f64 * src, - arm_matrix_instance_f64 * dst); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - } - - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5f * Ialpha + 0.8660254039f * Ibeta; - } - - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] pIa points to output three-phase coordinate a - * @param[out] pIb points to output three-phase coordinate b - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] pSrc input pointer - * @param[out] pDst output pointer - * @param[in] blockSize number of samples to process - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * The function implements the forward Park transform. - * - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - } - - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] pId points to output rotor reference frame d - * @param[out] pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - CMSIS_INLINE __STATIC_INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
-   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
- * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if (i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if ((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (q31_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1U); - } - } - - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & (int32_t)0xFFF00000) >> 20); - - if (index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if (index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (q15_t) (y >> 20); - } - } - - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - if (index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (q7_t) (y >> 20); - } - } - - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - float32_t arm_sin_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q31_t arm_sin_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - q15_t arm_sin_q15( - q15_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - float32_t arm_cos_f32( - float32_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q31_t arm_cos_q31( - q31_t x); - - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
-   *      x1 = x0 - f(x0)/f'(x0)
-   *
- * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
-   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
- */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - CMSIS_INLINE __STATIC_INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if (in >= 0.0f) - { - -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#elif (__FPU_USED == 1) && (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined(__GNUC__) - *pOut = __builtin_sqrtf(in); -#elif (__FPU_USED == 1) && defined ( __ICCARM__ ) && (__VER__ >= 6040000) - __ASM("VSQRT.F32 %0,%1" : "=t"(*pOut) : "t"(in)); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - /** - * @brief floating-point Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q15 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q15 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0U; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if (wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = (uint16_t)wOffset; - } - - - /** - * @brief Q7 Circular Read function. - */ - CMSIS_INLINE __STATIC_INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while (i > 0U) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if (dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if (rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - - /** - * @brief Mean value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Mean value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Mean value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output value. - */ - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - - /** - * @brief Floating-point complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex magnitude - * @param[in] pSrc points to the complex input vector - * @param[out] pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - */ - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q15 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - - /** - * @brief Q31 complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - - /** - * @brief Floating-point complex dot product - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] realResult real part of the result returned here - * @param[out] imagResult imaginary part of the result returned here - */ - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] pSrcCmplx points to the complex input vector - * @param[in] pSrcReal points to the real input vector - * @param[out] pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - */ - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - */ - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[in] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] pResult is output pointer - * @param[out] pIndex is the array index of the minimum value in the input buffer. - */ - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] pResult maximum value returned here - * @param[out] pIndex index of maximum value returned here - */ - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] pSrcA points to the first input vector - * @param[in] pSrcB points to the second input vector - * @param[out] pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - */ - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] pSrc points to the floating-point input vector - * @param[out] pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] pSrc is input pointer - * @param[out] pDst is output pointer - * @param[in] blockSize is the number of samples to process - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
-   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
- * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
-   *     XF = floor(x)
-   *     YF = floor(y)
-   *
- * \par - * The interpolated output point is computed as: - * 
-   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
- * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - } - - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11U; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + (int32_t)nCols * (cI) ]; - x2 = pYData[(rI) + (int32_t)nCols * (cI) + 1]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11U; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + (int32_t)nCols * (cI + 1) ]; - y2 = pYData[(rI) + (int32_t)nCols * (cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return ((q31_t)(acc << 2)); - } - - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4U); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4U); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4U); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4U); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return ((q15_t)(acc >> 36)); - } - - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - CMSIS_INLINE __STATIC_INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & (q31_t)0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & (q31_t)0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) ]; - x2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI) + 1]; - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & (q31_t)0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) ]; - y2 = pYData[((uint32_t)rI) + nCols * ((uint32_t)cI + 1) + 1]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return ((q7_t)(acc >> 40)); - } - - /** - * @} end of BilinearInterpolate group - */ - - -/* SMMLAR */ -#define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMLSR */ -#define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -/* SMMULR */ -#define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -/* SMMLA */ -#define multAcc_32x32_keep32(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - -/* SMMLS */ -#define multSub_32x32_keep32(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -/* SMMUL */ -#define mult_32x32_keep32(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - -#if defined ( __CC_ARM ) - /* Enter low optimization region - place directly above function definition */ - #if defined( ARM_MATH_CM4 ) || defined( ARM_MATH_CM7) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - #else - #define LOW_OPTIMIZATION_EXIT - #endif - - /* Enter low optimization region - place directly above function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __GNUC__ ) - #define LOW_OPTIMIZATION_ENTER \ - __attribute__(( optimize("-O1") )) - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __ICCARM__ ) - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define LOW_OPTIMIZATION_EXIT - - /* Enter low optimization region - place directly above function definition */ - #if defined ( ARM_MATH_CM4 ) || defined ( ARM_MATH_CM7 ) - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - #else - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #endif - - /* Exit low optimization region - place directly after end of function definition */ - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TI_ARM__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __CSMC__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined ( __TASKING__ ) - #define LOW_OPTIMIZATION_ENTER - #define LOW_OPTIMIZATION_EXIT - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - -#ifdef __cplusplus -} -#endif - -/* Compiler specific diagnostic adjustment */ -#if defined ( __CC_ARM ) - -#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 ) - -#elif defined ( __GNUC__ ) -#pragma GCC diagnostic pop - -#elif defined ( __ICCARM__ ) - -#elif defined ( __TI_ARM__ ) - -#elif defined ( __CSMC__ ) - -#elif defined ( __TASKING__ ) - -#else - #error Unknown compiler -#endif - -#endif /* _ARM_MATH_H */ - -/** - * - * End of file. - */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mbl.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mbl.h deleted file mode 100644 index 47a39893ac..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mbl.h +++ /dev/null @@ -1,1896 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MBL_REV - #define __ARMv8MBL_REV 0x0000U - #warning "__ARMv8MBL_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mml.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mml.h deleted file mode 100644 index 0951a1f781..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_armv8mml.h +++ /dev/null @@ -1,2960 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mml.h - * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File - * @version V5.0.4 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_ARMV8MML_H_GENERIC -#define __CORE_ARMV8MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MML - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS Armv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_PCS_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MML_H_DEPENDANT -#define __CORE_ARMV8MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MML_REV - #define __ARMv8MML_REV 0x0000U - #warning "__ARMv8MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED3[92U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - uint32_t RESERVED7[6U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29U]; - __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED4[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_dsp.h b/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_dsp.h deleted file mode 100644 index 6c21a47d80..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/CMSIS/Include/core_dsp.h +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************//** - * @file cmsis_xcc.h - * @brief CMSIS DSP Core Peripheral Access Layer Header File - * @version V1.0 - * @date 20. January 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CORE_DSP_H_GENERIC -#define __CORE_DSP_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -#define __STATIC_INLINE static inline - -#define __BKPT(value) do {} while(0) -#define __NOP() do {} while(0) - -#define NVIC_SetPriorityGrouping(value) do {} while(0) -#define NVIC_GetPriorityGrouping() do {} while(0) -#define NVIC_EnableIRQ(value) do {} while(0) -#define NVIC_GetEnableIRQ(value) do {} while(0) -#define NVIC_DisableIRQ(value) do {} while(0) -#define NVIC_GetPendingIRQ(value) do {} while(0) -#define NVIC_SetPendingIRQ(value) do {} while(0) -#define NVIC_ClearPendingIRQ(value) do {} while(0) -#define NVIC_GetActive(value) do {} while(0) - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_DSP_H_GENERIC */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.h index ce7569307d..10871c87a0 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.h @@ -2,22 +2,22 @@ ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 ** LPC55S69JBD64_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b190430 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b211009 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -28,14 +28,16 @@ ** Revisions: ** - rev. 1.0 (2018-08-22) ** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM ** ** ################################################################### */ /*! * @file LPC55S69_cm33_core0.h - * @version 1.0 - * @date 2018-08-22 + * @version 1.1 + * @date 2019-05-16 * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 * * CMSIS Peripheral Access Layer for LPC55S69_cm33_core0 @@ -48,7 +50,7 @@ * compatible) */ #define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U +#define MCU_MEM_MAP_VERSION_MINOR 0x0001U /* ---------------------------------------------------------------------------- @@ -126,7 +128,7 @@ typedef enum IRQn { Reserved59_IRQn = 43, /**< Reserved interrupt */ Reserved60_IRQn = 44, /**< Reserved interrupt */ Reserved61_IRQn = 45, /**< Reserved interrupt */ - USB1_UTMI_IRQn = 46, /**< USB1_UTMI */ + USB1_PHY_IRQn = 46, /**< USB1_PHY */ USB1_IRQn = 47, /**< USB1 interrupt */ USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ @@ -216,9 +218,9 @@ typedef enum _dma_request_source kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma1RequestFlexcomm2Rx = 8U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma1RequestFlexcomm2Tx = 9U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ @@ -292,7 +294,7 @@ typedef struct { __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ uint8_t RESERVED_1[12]; - __IO uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ uint8_t RESERVED_2[4]; __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ @@ -329,6 +331,7 @@ typedef struct { /*! @name VERID - Version ID Register */ /*! @{ */ + #define ADC_VERID_RES_MASK (0x1U) #define ADC_VERID_RES_SHIFT (0U) /*! RES - Resolution @@ -336,6 +339,7 @@ typedef struct { * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. */ #define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + #define ADC_VERID_DIFFEN_MASK (0x2U) #define ADC_VERID_DIFFEN_SHIFT (1U) /*! DIFFEN - Differential Supported @@ -343,6 +347,7 @@ typedef struct { * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. */ #define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + #define ADC_VERID_MVI_MASK (0x8U) #define ADC_VERID_MVI_SHIFT (3U) /*! MVI - Multi Vref Implemented @@ -350,6 +355,7 @@ typedef struct { * 0b1..Multiple voltage reference high (VREFH) inputs supported. */ #define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + #define ADC_VERID_CSW_MASK (0x70U) #define ADC_VERID_CSW_SHIFT (4U) /*! CSW - Channel Scale Width @@ -358,6 +364,7 @@ typedef struct { * 0b110..Channel scaling supported. 6-bit CSCALE control field. */ #define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + #define ADC_VERID_VR1RNGI_MASK (0x100U) #define ADC_VERID_VR1RNGI_SHIFT (8U) /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented @@ -365,6 +372,7 @@ typedef struct { * 0b1..Range control required. CFG[VREF1RNG] is implemented. */ #define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + #define ADC_VERID_IADCKI_MASK (0x200U) #define ADC_VERID_IADCKI_SHIFT (9U) /*! IADCKI - Internal ADC Clock implemented @@ -372,6 +380,7 @@ typedef struct { * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. */ #define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + #define ADC_VERID_CALOFSI_MASK (0x400U) #define ADC_VERID_CALOFSI_SHIFT (10U) /*! CALOFSI - Calibration Function Implemented @@ -379,6 +388,7 @@ typedef struct { * 0b1..Calibration Implemented. */ #define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + #define ADC_VERID_NUM_SEC_MASK (0x800U) #define ADC_VERID_NUM_SEC_SHIFT (11U) /*! NUM_SEC - Number of Single Ended Outputs Supported @@ -386,6 +396,7 @@ typedef struct { * 0b1..This design supports two simultanious single ended conversions. */ #define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + #define ADC_VERID_NUM_FIFO_MASK (0x7000U) #define ADC_VERID_NUM_FIFO_SHIFT (12U) /*! NUM_FIFO - Number of FIFOs @@ -396,19 +407,29 @@ typedef struct { * 0b100..This design supports four result FIFOs. */ #define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + #define ADC_VERID_MINOR_MASK (0xFF0000U) #define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ #define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + #define ADC_VERID_MAJOR_MASK (0xFF000000U) #define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ #define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ + #define ADC_PARAM_TRIG_NUM_MASK (0xFFU) #define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number + */ #define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + #define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) #define ADC_PARAM_FIFOSIZE_SHIFT (8U) /*! FIFOSIZE - Result FIFO Depth @@ -420,16 +441,23 @@ typedef struct { * 0b01000000..Result FIFO depth = 64 datawords. */ #define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + #define ADC_PARAM_CV_NUM_MASK (0xFF0000U) #define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number + */ #define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + #define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) #define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number + */ #define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) /*! @} */ /*! @name CTRL - ADC Control Register */ /*! @{ */ + #define ADC_CTRL_ADCEN_MASK (0x1U) #define ADC_CTRL_ADCEN_SHIFT (0U) /*! ADCEN - ADC Enable @@ -437,6 +465,7 @@ typedef struct { * 0b1..ADC is enabled. */ #define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + #define ADC_CTRL_RST_MASK (0x2U) #define ADC_CTRL_RST_SHIFT (1U) /*! RST - Software Reset @@ -444,6 +473,7 @@ typedef struct { * 0b1..ADC logic is reset. */ #define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + #define ADC_CTRL_DOZEN_MASK (0x4U) #define ADC_CTRL_DOZEN_SHIFT (2U) /*! DOZEN - Doze Enable @@ -451,6 +481,7 @@ typedef struct { * 0b1..ADC is disabled in Doze mode. */ #define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + #define ADC_CTRL_CAL_REQ_MASK (0x8U) #define ADC_CTRL_CAL_REQ_SHIFT (3U) /*! CAL_REQ - Auto-Calibration Request @@ -458,6 +489,7 @@ typedef struct { * 0b1..A request for auto-calibration has been made */ #define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + #define ADC_CTRL_CALOFS_MASK (0x10U) #define ADC_CTRL_CALOFS_SHIFT (4U) /*! CALOFS - Configure for offset calibration function @@ -465,6 +497,7 @@ typedef struct { * 0b1..Request for offset calibration function */ #define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + #define ADC_CTRL_RSTFIFO0_MASK (0x100U) #define ADC_CTRL_RSTFIFO0_SHIFT (8U) /*! RSTFIFO0 - Reset FIFO 0 @@ -472,6 +505,7 @@ typedef struct { * 0b1..FIFO 0 is reset. */ #define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + #define ADC_CTRL_RSTFIFO1_MASK (0x200U) #define ADC_CTRL_RSTFIFO1_SHIFT (9U) /*! RSTFIFO1 - Reset FIFO 1 @@ -479,6 +513,7 @@ typedef struct { * 0b1..FIFO 1 is reset. */ #define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) + #define ADC_CTRL_CAL_AVGS_MASK (0x70000U) #define ADC_CTRL_CAL_AVGS_SHIFT (16U) /*! CAL_AVGS - Auto-Calibration Averages @@ -496,6 +531,7 @@ typedef struct { /*! @name STAT - ADC Status Register */ /*! @{ */ + #define ADC_STAT_RDY0_MASK (0x1U) #define ADC_STAT_RDY0_SHIFT (0U) /*! RDY0 - Result FIFO 0 Ready Flag @@ -503,6 +539,7 @@ typedef struct { * 0b1..Result FIFO 0 holding data above watermark level. */ #define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + #define ADC_STAT_FOF0_MASK (0x2U) #define ADC_STAT_FOF0_SHIFT (1U) /*! FOF0 - Result FIFO 0 Overflow Flag @@ -510,6 +547,7 @@ typedef struct { * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. */ #define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + #define ADC_STAT_RDY1_MASK (0x4U) #define ADC_STAT_RDY1_SHIFT (2U) /*! RDY1 - Result FIFO1 Ready Flag @@ -517,6 +555,7 @@ typedef struct { * 0b1..Result FIFO1 holding data above watermark level. */ #define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) + #define ADC_STAT_FOF1_MASK (0x8U) #define ADC_STAT_FOF1_SHIFT (3U) /*! FOF1 - Result FIFO1 Overflow Flag @@ -524,6 +563,7 @@ typedef struct { * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. */ #define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) + #define ADC_STAT_TEXC_INT_MASK (0x100U) #define ADC_STAT_TEXC_INT_SHIFT (8U) /*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception @@ -531,6 +571,7 @@ typedef struct { * 0b1..A trigger exception has occurred and is pending acknowledgement. */ #define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + #define ADC_STAT_TCOMP_INT_MASK (0x200U) #define ADC_STAT_TCOMP_INT_SHIFT (9U) /*! TCOMP_INT - Interrupt Flag For Trigger Completion @@ -538,6 +579,7 @@ typedef struct { * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. */ #define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + #define ADC_STAT_CAL_RDY_MASK (0x400U) #define ADC_STAT_CAL_RDY_SHIFT (10U) /*! CAL_RDY - Calibration Ready @@ -545,6 +587,7 @@ typedef struct { * 0b1..The ADC is calibrated. */ #define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + #define ADC_STAT_ADC_ACTIVE_MASK (0x800U) #define ADC_STAT_ADC_ACTIVE_SHIFT (11U) /*! ADC_ACTIVE - ADC Active @@ -552,6 +595,7 @@ typedef struct { * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. */ #define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + #define ADC_STAT_TRGACT_MASK (0xF0000U) #define ADC_STAT_TRGACT_SHIFT (16U) /*! TRGACT - Trigger Active @@ -561,6 +605,7 @@ typedef struct { * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. */ #define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + #define ADC_STAT_CMDACT_MASK (0xF000000U) #define ADC_STAT_CMDACT_SHIFT (24U) /*! CMDACT - Command Active @@ -574,6 +619,7 @@ typedef struct { /*! @name IE - Interrupt Enable Register */ /*! @{ */ + #define ADC_IE_FWMIE0_MASK (0x1U) #define ADC_IE_FWMIE0_SHIFT (0U) /*! FWMIE0 - FIFO 0 Watermark Interrupt Enable @@ -581,6 +627,7 @@ typedef struct { * 0b1..FIFO 0 watermark interrupts are enabled. */ #define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + #define ADC_IE_FOFIE0_MASK (0x2U) #define ADC_IE_FOFIE0_SHIFT (1U) /*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable @@ -588,6 +635,7 @@ typedef struct { * 0b1..FIFO 0 overflow interrupts are enabled. */ #define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + #define ADC_IE_FWMIE1_MASK (0x4U) #define ADC_IE_FWMIE1_SHIFT (2U) /*! FWMIE1 - FIFO1 Watermark Interrupt Enable @@ -595,6 +643,7 @@ typedef struct { * 0b1..FIFO1 watermark interrupts are enabled. */ #define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) + #define ADC_IE_FOFIE1_MASK (0x8U) #define ADC_IE_FOFIE1_SHIFT (3U) /*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable @@ -602,6 +651,7 @@ typedef struct { * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. */ #define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) + #define ADC_IE_TEXC_IE_MASK (0x100U) #define ADC_IE_TEXC_IE_SHIFT (8U) /*! TEXC_IE - Trigger Exception Interrupt Enable @@ -609,6 +659,7 @@ typedef struct { * 0b1..Trigger exception interrupts are enabled. */ #define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + #define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) #define ADC_IE_TCOMP_IE_SHIFT (16U) /*! TCOMP_IE - Trigger Completion Interrupt Enable @@ -623,6 +674,7 @@ typedef struct { /*! @name DE - DMA Enable Register */ /*! @{ */ + #define ADC_DE_FWMDE0_MASK (0x1U) #define ADC_DE_FWMDE0_SHIFT (0U) /*! FWMDE0 - FIFO 0 Watermark DMA Enable @@ -630,6 +682,7 @@ typedef struct { * 0b1..DMA request enabled. */ #define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) + #define ADC_DE_FWMDE1_MASK (0x2U) #define ADC_DE_FWMDE1_SHIFT (1U) /*! FWMDE1 - FIFO1 Watermark DMA Enable @@ -641,6 +694,7 @@ typedef struct { /*! @name CFG - ADC Configuration Register */ /*! @{ */ + #define ADC_CFG_TPRICTRL_MASK (0x3U) #define ADC_CFG_TPRICTRL_SHIFT (0U) /*! TPRICTRL - ADC trigger priority control @@ -654,6 +708,7 @@ typedef struct { * 0b11..RESERVED */ #define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + #define ADC_CFG_PWRSEL_MASK (0x30U) #define ADC_CFG_PWRSEL_SHIFT (4U) /*! PWRSEL - Power Configuration Select @@ -663,6 +718,7 @@ typedef struct { * 0b11..Highest power setting. */ #define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + #define ADC_CFG_REFSEL_MASK (0xC0U) #define ADC_CFG_REFSEL_SHIFT (6U) /*! REFSEL - Voltage Reference Selection @@ -672,6 +728,7 @@ typedef struct { * 0b11..Reserved */ #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + #define ADC_CFG_TRES_MASK (0x100U) #define ADC_CFG_TRES_SHIFT (8U) /*! TRES - Trigger Resume Enable @@ -679,6 +736,7 @@ typedef struct { * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. */ #define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + #define ADC_CFG_TCMDRES_MASK (0x200U) #define ADC_CFG_TCMDRES_SHIFT (9U) /*! TCMDRES - Trigger Command Resume @@ -686,6 +744,7 @@ typedef struct { * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. */ #define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + #define ADC_CFG_HPT_EXDI_MASK (0x400U) #define ADC_CFG_HPT_EXDI_SHIFT (10U) /*! HPT_EXDI - High Priority Trigger Exception Disable @@ -693,9 +752,13 @@ typedef struct { * 0b1..High priority trigger exceptions are disabled. */ #define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + #define ADC_CFG_PUDLY_MASK (0xFF0000U) #define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power Up Delay + */ #define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + #define ADC_CFG_PWREN_MASK (0x10000000U) #define ADC_CFG_PWREN_SHIFT (28U) /*! PWREN - ADC Analog Pre-Enable @@ -711,9 +774,13 @@ typedef struct { /*! @name PAUSE - ADC Pause Register */ /*! @{ */ + #define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) #define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay + */ #define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + #define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) #define ADC_PAUSE_PAUSEEN_SHIFT (31U) /*! PAUSEEN - PAUSE Option Enable @@ -725,6 +792,7 @@ typedef struct { /*! @name SWTRIG - Software Trigger Register */ /*! @{ */ + #define ADC_SWTRIG_SWT0_MASK (0x1U) #define ADC_SWTRIG_SWT0_SHIFT (0U) /*! SWT0 - Software trigger 0 event @@ -732,6 +800,7 @@ typedef struct { * 0b1..Trigger 0 event generated. */ #define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + #define ADC_SWTRIG_SWT1_MASK (0x2U) #define ADC_SWTRIG_SWT1_SHIFT (1U) /*! SWT1 - Software trigger 1 event @@ -739,6 +808,7 @@ typedef struct { * 0b1..Trigger 1 event generated. */ #define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + #define ADC_SWTRIG_SWT2_MASK (0x4U) #define ADC_SWTRIG_SWT2_SHIFT (2U) /*! SWT2 - Software trigger 2 event @@ -746,6 +816,7 @@ typedef struct { * 0b1..Trigger 2 event generated. */ #define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + #define ADC_SWTRIG_SWT3_MASK (0x8U) #define ADC_SWTRIG_SWT3_SHIFT (3U) /*! SWT3 - Software trigger 3 event @@ -753,6 +824,7 @@ typedef struct { * 0b1..Trigger 3 event generated. */ #define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) + #define ADC_SWTRIG_SWT4_MASK (0x10U) #define ADC_SWTRIG_SWT4_SHIFT (4U) /*! SWT4 - Software trigger 4 event @@ -760,6 +832,7 @@ typedef struct { * 0b1..Trigger 4 event generated. */ #define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) + #define ADC_SWTRIG_SWT5_MASK (0x20U) #define ADC_SWTRIG_SWT5_SHIFT (5U) /*! SWT5 - Software trigger 5 event @@ -767,6 +840,7 @@ typedef struct { * 0b1..Trigger 5 event generated. */ #define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) + #define ADC_SWTRIG_SWT6_MASK (0x40U) #define ADC_SWTRIG_SWT6_SHIFT (6U) /*! SWT6 - Software trigger 6 event @@ -774,6 +848,7 @@ typedef struct { * 0b1..Trigger 6 event generated. */ #define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) + #define ADC_SWTRIG_SWT7_MASK (0x80U) #define ADC_SWTRIG_SWT7_SHIFT (7U) /*! SWT7 - Software trigger 7 event @@ -781,6 +856,7 @@ typedef struct { * 0b1..Trigger 7 event generated. */ #define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) + #define ADC_SWTRIG_SWT8_MASK (0x100U) #define ADC_SWTRIG_SWT8_SHIFT (8U) /*! SWT8 - Software trigger 8 event @@ -788,6 +864,7 @@ typedef struct { * 0b1..Trigger 8 event generated. */ #define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) + #define ADC_SWTRIG_SWT9_MASK (0x200U) #define ADC_SWTRIG_SWT9_SHIFT (9U) /*! SWT9 - Software trigger 9 event @@ -795,6 +872,7 @@ typedef struct { * 0b1..Trigger 9 event generated. */ #define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) + #define ADC_SWTRIG_SWT10_MASK (0x400U) #define ADC_SWTRIG_SWT10_SHIFT (10U) /*! SWT10 - Software trigger 10 event @@ -802,6 +880,7 @@ typedef struct { * 0b1..Trigger 10 event generated. */ #define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) + #define ADC_SWTRIG_SWT11_MASK (0x800U) #define ADC_SWTRIG_SWT11_SHIFT (11U) /*! SWT11 - Software trigger 11 event @@ -809,6 +888,7 @@ typedef struct { * 0b1..Trigger 11 event generated. */ #define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) + #define ADC_SWTRIG_SWT12_MASK (0x1000U) #define ADC_SWTRIG_SWT12_SHIFT (12U) /*! SWT12 - Software trigger 12 event @@ -816,6 +896,7 @@ typedef struct { * 0b1..Trigger 12 event generated. */ #define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) + #define ADC_SWTRIG_SWT13_MASK (0x2000U) #define ADC_SWTRIG_SWT13_SHIFT (13U) /*! SWT13 - Software trigger 13 event @@ -823,6 +904,7 @@ typedef struct { * 0b1..Trigger 13 event generated. */ #define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) + #define ADC_SWTRIG_SWT14_MASK (0x4000U) #define ADC_SWTRIG_SWT14_SHIFT (14U) /*! SWT14 - Software trigger 14 event @@ -830,6 +912,7 @@ typedef struct { * 0b1..Trigger 14 event generated. */ #define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) + #define ADC_SWTRIG_SWT15_MASK (0x8000U) #define ADC_SWTRIG_SWT15_SHIFT (15U) /*! SWT15 - Software trigger 15 event @@ -841,6 +924,7 @@ typedef struct { /*! @name TSTAT - Trigger Status Register */ /*! @{ */ + #define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) #define ADC_TSTAT_TEXC_NUM_SHIFT (0U) /*! TEXC_NUM - Trigger Exception Number @@ -851,6 +935,7 @@ typedef struct { * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. */ #define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + #define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) #define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) /*! TCOMP_FLAG - Trigger Completion Flag @@ -865,16 +950,23 @@ typedef struct { /*! @name OFSTRIM - ADC Offset Trim Register */ /*! @{ */ + #define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) #define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +/*! OFSTRIM_A - Trim for offset + */ #define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) + #define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) #define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +/*! OFSTRIM_B - Trim for offset + */ #define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) /*! @} */ /*! @name TCTRL - Trigger Control Register */ /*! @{ */ + #define ADC_TCTRL_HTEN_MASK (0x1U) #define ADC_TCTRL_HTEN_SHIFT (0U) /*! HTEN - Trigger enable @@ -882,6 +974,7 @@ typedef struct { * 0b1..Hardware trigger source enabled */ #define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + #define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) #define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) /*! FIFO_SEL_A - SAR Result Destination For Channel A @@ -889,6 +982,7 @@ typedef struct { * 0b1..Result written to FIFO 1 */ #define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) + #define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) #define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) /*! FIFO_SEL_B - SAR Result Destination For Channel B @@ -896,6 +990,7 @@ typedef struct { * 0b1..Result written to FIFO 1 */ #define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) + #define ADC_TCTRL_TPRI_MASK (0xF00U) #define ADC_TCTRL_TPRI_SHIFT (8U) /*! TPRI - Trigger priority setting @@ -904,12 +999,19 @@ typedef struct { * 0b1111..Set to lowest priority, Level 16 */ #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + #define ADC_TCTRL_RSYNC_MASK (0x8000U) #define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync + */ #define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + #define ADC_TCTRL_TDLY_MASK (0xF0000U) #define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger delay select + */ #define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + #define ADC_TCTRL_TCMD_MASK (0xF000000U) #define ADC_TCTRL_TCMD_SHIFT (24U) /*! TCMD - Trigger command select @@ -926,11 +1028,17 @@ typedef struct { /*! @name FCTRL - FIFO Control Register */ /*! @{ */ + #define ADC_FCTRL_FCOUNT_MASK (0x1FU) #define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO counter + */ #define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + #define ADC_FCTRL_FWMARK_MASK (0xF0000U) #define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark level selection + */ #define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) /*! @} */ @@ -939,9 +1047,13 @@ typedef struct { /*! @name GCC - Gain Calibration Control */ /*! @{ */ + #define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) #define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value + */ #define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + #define ADC_GCC_RDY_MASK (0x1000000U) #define ADC_GCC_RDY_SHIFT (24U) /*! RDY - Gain Calibration Value Valid @@ -956,9 +1068,13 @@ typedef struct { /*! @name GCR - Gain Calculation Result */ /*! @{ */ + #define ADC_GCR_GCALR_MASK (0xFFFFU) #define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result + */ #define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + #define ADC_GCR_RDY_MASK (0x1000000U) #define ADC_GCR_RDY_SHIFT (24U) /*! RDY - Gain Calculation Ready @@ -973,6 +1089,7 @@ typedef struct { /*! @name CMDL - ADC Command Low Buffer Register */ /*! @{ */ + #define ADC_CMDL_ADCH_MASK (0x1FU) #define ADC_CMDL_ADCH_SHIFT (0U) /*! ADCH - Input channel select @@ -985,6 +1102,7 @@ typedef struct { * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. */ #define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + #define ADC_CMDL_CTYPE_MASK (0x60U) #define ADC_CMDL_CTYPE_SHIFT (5U) /*! CTYPE - Conversion Type @@ -994,6 +1112,7 @@ typedef struct { * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ #define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + #define ADC_CMDL_MODE_MASK (0x80U) #define ADC_CMDL_MODE_SHIFT (7U) /*! MODE - Select resolution of conversions @@ -1008,6 +1127,7 @@ typedef struct { /*! @name CMDH - ADC Command High Buffer Register */ /*! @{ */ + #define ADC_CMDH_CMPEN_MASK (0x3U) #define ADC_CMDH_CMPEN_SHIFT (0U) /*! CMPEN - Compare Function Enable @@ -1017,6 +1137,7 @@ typedef struct { * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. */ #define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + #define ADC_CMDH_WAIT_TRIG_MASK (0x4U) #define ADC_CMDH_WAIT_TRIG_SHIFT (2U) /*! WAIT_TRIG - Wait for trigger assertion before execution. @@ -1024,6 +1145,7 @@ typedef struct { * 0b1..The active trigger must be asserted again before executing this command. */ #define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + #define ADC_CMDH_LWI_MASK (0x80U) #define ADC_CMDH_LWI_SHIFT (7U) /*! LWI - Loop with Increment @@ -1031,6 +1153,7 @@ typedef struct { * 0b1..Auto channel increment enabled */ #define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + #define ADC_CMDH_STS_MASK (0x700U) #define ADC_CMDH_STS_SHIFT (8U) /*! STS - Sample Time Select @@ -1044,6 +1167,7 @@ typedef struct { * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. */ #define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + #define ADC_CMDH_AVGS_MASK (0x7000U) #define ADC_CMDH_AVGS_SHIFT (12U) /*! AVGS - Hardware Average Select @@ -1057,6 +1181,7 @@ typedef struct { * 0b111..128 conversions averaged. */ #define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + #define ADC_CMDH_LOOP_MASK (0xF0000U) #define ADC_CMDH_LOOP_SHIFT (16U) /*! LOOP - Loop Count Select @@ -1067,6 +1192,7 @@ typedef struct { * 0b1111..Loop 15 times. Command executes 16 times. */ #define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + #define ADC_CMDH_NEXT_MASK (0xF000000U) #define ADC_CMDH_NEXT_SHIFT (24U) /*! NEXT - Next Command Select @@ -1084,11 +1210,17 @@ typedef struct { /*! @name CV - Compare Value Register */ /*! @{ */ + #define ADC_CV_CVL_MASK (0xFFFFU) #define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low. + */ #define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + #define ADC_CV_CVH_MASK (0xFFFF0000U) #define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High. + */ #define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) /*! @} */ @@ -1097,9 +1229,13 @@ typedef struct { /*! @name RESFIFO - ADC Data Result FIFO Register */ /*! @{ */ + #define ADC_RESFIFO_D_MASK (0xFFFFU) #define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data result + */ #define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + #define ADC_RESFIFO_TSRC_MASK (0xF0000U) #define ADC_RESFIFO_TSRC_SHIFT (16U) /*! TSRC - Trigger Source @@ -1109,6 +1245,7 @@ typedef struct { * 0b1111..Trigger source 15 initiated this conversion. */ #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + #define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) #define ADC_RESFIFO_LOOPCNT_SHIFT (20U) /*! LOOPCNT - Loop count value @@ -1118,6 +1255,7 @@ typedef struct { * 0b1111..Result is from 16th conversion in command. */ #define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + #define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) #define ADC_RESFIFO_CMDSRC_SHIFT (24U) /*! CMDSRC - Command Buffer Source @@ -1128,6 +1266,7 @@ typedef struct { * 0b1111..CMD15 buffer used as control settings for this conversion. */ #define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + #define ADC_RESFIFO_VALID_MASK (0x80000000U) #define ADC_RESFIFO_VALID_SHIFT (31U) /*! VALID - FIFO entry is valid @@ -1142,8 +1281,11 @@ typedef struct { /*! @name CAL_GAR - Calibration General A-Side Registers */ /*! @{ */ + #define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) #define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element + */ #define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) /*! @} */ @@ -1152,8 +1294,11 @@ typedef struct { /*! @name CAL_GBR - Calibration General B-Side Registers */ /*! @{ */ + #define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) #define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element + */ #define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) /*! @} */ @@ -1162,6 +1307,7 @@ typedef struct { /*! @name TST - ADC Test Register */ /*! @{ */ + #define ADC_TST_CST_LONG_MASK (0x1U) #define ADC_TST_CST_LONG_SHIFT (0U) /*! CST_LONG - Calibration Sample Time Long @@ -1169,6 +1315,7 @@ typedef struct { * 0b1..Increased sample time. 67 ADCK cycles total sample time. */ #define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) + #define ADC_TST_FOFFM_MASK (0x100U) #define ADC_TST_FOFFM_SHIFT (8U) /*! FOFFM - Force M-side positive offset @@ -1176,6 +1323,7 @@ typedef struct { * 0b1..Test configuration. Forced positive offset on MDAC. */ #define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) + #define ADC_TST_FOFFP_MASK (0x200U) #define ADC_TST_FOFFP_SHIFT (9U) /*! FOFFP - Force P-side positive offset @@ -1183,6 +1331,7 @@ typedef struct { * 0b1..Test configuration. Forced positive offset on PDAC. */ #define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) + #define ADC_TST_FOFFM2_MASK (0x400U) #define ADC_TST_FOFFM2_SHIFT (10U) /*! FOFFM2 - Force M-side negative offset @@ -1190,6 +1339,7 @@ typedef struct { * 0b1..Test configuration. Forced negative offset on MDAC. */ #define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) + #define ADC_TST_FOFFP2_MASK (0x800U) #define ADC_TST_FOFFP2_SHIFT (11U) /*! FOFFP2 - Force P-side negative offset @@ -1197,6 +1347,7 @@ typedef struct { * 0b1..Test configuration. Forced negative offset on PDAC. */ #define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) + #define ADC_TST_TESTEN_MASK (0x800000U) #define ADC_TST_TESTEN_SHIFT (23U) /*! TESTEN - Enable test configuration @@ -1213,7 +1364,7 @@ typedef struct { /* ADC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral ADC0 base address */ #define ADC0_BASE (0x500A0000u) /** Peripheral ADC0 base address */ @@ -1308,24 +1459,24 @@ typedef struct { __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ - uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL3; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x10C, array step: 0x30 */ + uint8_t RESERVED_1[4]; __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ } SEC_CTRL_APB_BRIDGE[1]; - __IO uint32_t SEC_CTRL_AHB0_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ - __IO uint32_t SEC_CTRL_AHB0_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ uint8_t RESERVED_6[8]; - __IO uint32_t SEC_CTRL_AHB1_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ - __IO uint32_t SEC_CTRL_AHB1_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ uint8_t RESERVED_7[8]; struct { /* offset: 0x140, array step: 0x14 */ - __IO uint32_t SEC_CTRL_AHB2_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ - __IO uint32_t SEC_CTRL_AHB2_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ + __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ + __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ uint8_t RESERVED_0[8]; - __IO uint32_t SEC_CTRL_AHB2_0_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_AHB2[1]; + __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_AHB_PORT10[1]; uint8_t RESERVED_8[12]; struct { /* offset: 0x160, array step: 0x14 */ __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ @@ -1333,9 +1484,9 @@ typedef struct { __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ } SEC_CTRL_USB_HS[1]; uint8_t RESERVED_9[3212]; - __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */ + __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */ uint8_t RESERVED_10[80]; - __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */ + __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */ uint8_t RESERVED_11[80]; __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ uint8_t RESERVED_12[124]; @@ -1350,8 +1501,8 @@ typedef struct { __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ uint8_t RESERVED_16[20]; - __IO uint32_t CM33_LOCK_REG; /**< Miscalleneous control signals for in CM33 (CPU0), offset: 0xFEC */ - __IO uint32_t MCM33_LOCK_REG; /**< Miscalleneous control signals for in micro-CM33 (CPU1), offset: 0xFF0 */ + __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ + __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */ uint8_t RESERVED_17[4]; __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ @@ -1368,6 +1519,7 @@ typedef struct { /*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) /*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF @@ -1377,6 +1529,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) + #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) /*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF @@ -1391,172 +1544,189 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ +/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) -/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ +/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) /*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) /*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF @@ -1571,90 +1741,99 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE - Security access rules for RAMX slaves. */ +/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT2 (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) /*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) /*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF @@ -1669,188 +1848,206 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE - Security access rules for RAM0 slaves. */ +/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT2 (2U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U) /*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT (0U) -/*! RAM0_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) +/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) /*! @} */ /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE - Security access rules for RAM1 slaves. */ +/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT2 (2U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U) /*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) /*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF @@ -1865,90 +2062,99 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE - Security access rules for RAM2 slaves. */ +/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT2 (2U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U) /*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) /*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF @@ -1963,90 +2169,99 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE - Security access rules for RAM3 slaves. */ +/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT2 (2U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U) /*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) /*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF @@ -2061,54 +2276,59 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE - Security access rules for RAM4 slaves. */ +/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT2 (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U) /*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) /*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 @@ -2118,6 +2338,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) + #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) /*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 @@ -2132,622 +2353,668 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) /*! SYSCON_RULE - System Configuration * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) /*! IOCON_RULE - I/O Configuration * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) /*! GINT0_RULE - GPIO input Interrupt 0 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) /*! GINT1_RULE - GPIO input Interrupt 1 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) /*! PINT_RULE - Pin Interrupt and Pattern match * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) /*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT (24U) -/*! PMUX_RULE - Peripherals mux +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) +/*! INPUTMUX_RULE - Peripheral input multiplexing * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) /*! CTIMER0_RULE - Standard counter/Timer 0 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) /*! CTIMER1_RULE - Standard counter/Timer 1 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) /*! WWDT_RULE - Windiwed wtachdog Timer * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) /*! MRT_RULE - Multi-rate Timer * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) /*! UTICK_RULE - Micro-Timer * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) /*! ANACTRL_RULE - Analog Modules controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT (20U) -/*! EFUSE_RULE - eFUSE (One Time Programmable) memory controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) /*! PMC_RULE - Power Management Controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) /*! SYSCTRL_RULE - System Controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) /*! CTIMER2_RULE - Standard counter/Timer 2 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) /*! CTIMER3_RULE - Standard counter/Timer 3 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) /*! CTIMER4_RULE - Standard counter/Timer 4 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) /*! RTC_RULE - Real Time Counter * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) /*! OSEVENT_RULE - OS Event Timer * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) /*! FLASH_CTRL_RULE - Flash Controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) /*! PRINCE_RULE - Prince * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) /*! USBHPHY_RULE - USB High Speed Phy controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) /*! RNG_RULE - True Random Number Generator * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT (12U) -/*! PUFF_RULE - PUF +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) +/*! PUF_RULE - PUF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) /*! PLU_RULE - Programmable Look-Up logic * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) -/*! @name SEC_CTRL_AHB0_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT (8U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) /*! DMA0_RULE - DMA Controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) /*! FS_USB_DEV_RULE - USB Full-speed device * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U) /*! SCT_RULE - SCTimer * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) /*! FLEXCOMM0_RULE - Flexcomm interface 0 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) /*! FLEXCOMM1_RULE - Flexcomm interface 1 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) /*! @} */ -/*! @name SEC_CTRL_AHB0_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) /*! FLEXCOMM2_RULE - Flexcomm interface 2 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) /*! FLEXCOMM3_RULE - Flexcomm interface 3 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) /*! FLEXCOMM4_RULE - Flexcomm interface 4 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U) /*! MAILBOX_RULE - Inter CPU communication Mailbox * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) /*! GPIO0_RULE - High Speed GPIO * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK) /*! @} */ -/*! @name SEC_CTRL_AHB1_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT (16U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) /*! USB_HS_DEV_RULE - USB high Speed device registers * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U) /*! CRC_RULE - CRC engine * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) /*! FLEXCOMM5_RULE - Flexcomm interface 5 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) /*! FLEXCOMM6_RULE - Flexcomm interface 6 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) /*! @} */ -/*! @name SEC_CTRL_AHB1_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) /*! FLEXCOMM7_RULE - Flexcomm interface 7 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U) /*! SDIO_RULE - SDMMC card interface * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) /*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) /*! HS_LSPI_RULE - High Speed SPI * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK) /*! @} */ -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U) /*! ADC_RULE - ADC * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) /*! USB_FS_HOST_RULE - USB Full Speed Host registers. * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) /*! USB_HS_HOST_RULE - USB High speed host registers * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U) /*! HASH_RULE - SHA-2 crypto registers * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) /*! CASPER_RULE - RSA/ECC crypto accelerator * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT (24U) -/*! PQ_RULE - Power Quad (CM33 processor hardware accelerator) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U) +/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator) * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) /*! DMA1_RULE - DMA Controller (Secure) * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U) -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) /*! GPIO1_RULE - Secure High Speed GPIO * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) /*! AHB_SEC_CTRL_RULE - AHB Secure Controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U) -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ +/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) /*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) /*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) /*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) /*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT2 (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) /*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) /*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF @@ -2762,64 +3029,72 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE - Security access rules for RAM_USB_HS. */ +/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) /*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) /*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) /*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) /*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT2 (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) -/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */ +/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +/*! SEC_VIO_ADDR - security violation address for AHB port + */ #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) /*! @} */ /* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ #define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U) -/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */ +/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) /*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. @@ -2827,6 +3102,7 @@ typedef struct { * 0b1..Write access. */ #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) /*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. @@ -2834,9 +3110,13 @@ typedef struct { * 0b1..Data access. */ #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level + */ #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) /*! SEC_VIO_INFO_MASTER - security violation master number @@ -2860,86 +3140,98 @@ typedef struct { /*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) -/*! VIO_INFO_VALID0 - violation information valid flag for AHB layer 0. Write 1 to clear. +/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) -/*! VIO_INFO_VALID1 - violation information valid flag for AHB layer 1. Write 1 to clear. +/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) -/*! VIO_INFO_VALID2 - violation information valid flag for AHB layer 2. Write 1 to clear. +/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) -/*! VIO_INFO_VALID3 - violation information valid flag for AHB layer 3. Write 1 to clear. +/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) -/*! VIO_INFO_VALID4 - violation information valid flag for AHB layer 4. Write 1 to clear. +/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) -/*! VIO_INFO_VALID5 - violation information valid flag for AHB layer 5. Write 1 to clear. +/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) -/*! VIO_INFO_VALID6 - violation information valid flag for AHB layer 6. Write 1 to clear. +/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) -/*! VIO_INFO_VALID7 - violation information valid flag for AHB layer 7. Write 1 to clear. +/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) -/*! VIO_INFO_VALID8 - violation information valid flag for AHB layer 8. Write 1 to clear. +/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) -/*! VIO_INFO_VALID9 - violation information valid flag for AHB layer 9. Write 1 to clear. +/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) -/*! VIO_INFO_VALID10 - violation information valid flag for AHB layer 10. Write 1 to clear. +/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) -/*! VIO_INFO_VALID11 - violation information valid flag for AHB layer 11. Write 1 to clear. +/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ @@ -2948,6 +3240,7 @@ typedef struct { /*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) /*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 @@ -2955,6 +3248,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) /*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 @@ -2962,6 +3256,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) /*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 @@ -2969,6 +3264,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) /*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 @@ -2976,6 +3272,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) /*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 @@ -2983,6 +3280,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) /*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 @@ -2990,6 +3288,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) /*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 @@ -2997,6 +3296,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) /*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 @@ -3004,6 +3304,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) /*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 @@ -3011,6 +3312,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) /*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 @@ -3018,6 +3320,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) /*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 @@ -3025,6 +3328,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) /*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 @@ -3032,6 +3336,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) /*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 @@ -3039,6 +3344,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) /*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 @@ -3046,6 +3352,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) /*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 @@ -3053,6 +3360,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) /*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 @@ -3060,6 +3368,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) /*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 @@ -3067,6 +3376,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) /*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 @@ -3074,6 +3384,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) /*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 @@ -3081,6 +3392,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) /*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 @@ -3088,6 +3400,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) /*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 @@ -3095,6 +3408,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) /*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 @@ -3102,6 +3416,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) /*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 @@ -3109,6 +3424,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) /*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 @@ -3116,6 +3432,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) /*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 @@ -3123,6 +3440,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) /*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 @@ -3130,6 +3448,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) /*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 @@ -3137,6 +3456,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) /*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 @@ -3144,6 +3464,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) /*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 @@ -3151,6 +3472,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) /*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 @@ -3158,6 +3480,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) /*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 @@ -3165,6 +3488,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) /*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 @@ -3176,6 +3500,7 @@ typedef struct { /*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) /*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 @@ -3183,6 +3508,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) /*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 @@ -3190,6 +3516,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) /*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 @@ -3197,6 +3524,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) /*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 @@ -3204,6 +3532,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) /*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 @@ -3211,6 +3540,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) /*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 @@ -3218,6 +3548,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) /*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 @@ -3225,6 +3556,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) /*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 @@ -3232,6 +3564,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) /*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 @@ -3239,6 +3572,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) /*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 @@ -3246,6 +3580,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) /*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 @@ -3253,6 +3588,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) /*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 @@ -3260,6 +3596,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) /*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 @@ -3267,6 +3604,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) /*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 @@ -3274,6 +3612,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) /*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 @@ -3281,6 +3620,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) /*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 @@ -3288,6 +3628,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) /*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 @@ -3295,6 +3636,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) /*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 @@ -3302,6 +3644,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) /*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 @@ -3309,6 +3652,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) /*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 @@ -3316,6 +3660,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) /*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 @@ -3323,6 +3668,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) /*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 @@ -3330,6 +3676,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) /*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 @@ -3337,6 +3684,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) /*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 @@ -3344,6 +3692,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) /*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 @@ -3351,6 +3700,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) /*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 @@ -3358,6 +3708,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) /*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 @@ -3365,6 +3716,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) /*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 @@ -3372,6 +3724,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) /*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 @@ -3379,6 +3732,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) /*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 @@ -3386,6 +3740,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) /*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 @@ -3393,6 +3748,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) /*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 @@ -3404,6 +3760,7 @@ typedef struct { /*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) /*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts @@ -3411,6 +3768,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) /*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. @@ -3418,6 +3776,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) /*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. @@ -3425,6 +3784,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) /*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. @@ -3432,6 +3792,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) /*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. @@ -3439,6 +3800,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) /*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. @@ -3446,6 +3808,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) /*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. @@ -3453,6 +3816,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) /*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. @@ -3460,6 +3824,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) /*! UTICK_IRQ - Micro Tick Timer interrupt. @@ -3467,6 +3832,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) /*! MRT_IRQ - Multi-Rate Timer interrupt. @@ -3474,6 +3840,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) /*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. @@ -3481,6 +3848,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) /*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. @@ -3488,6 +3856,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) /*! SCT_IRQ - SCTimer/PWM interrupt. @@ -3495,6 +3864,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) /*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. @@ -3502,6 +3872,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) /*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). @@ -3509,6 +3880,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) /*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). @@ -3516,6 +3888,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) /*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). @@ -3523,6 +3896,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) /*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). @@ -3530,6 +3904,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) /*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). @@ -3537,6 +3912,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) /*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). @@ -3544,6 +3920,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) /*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). @@ -3551,6 +3928,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) /*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). @@ -3558,6 +3936,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) /*! ADC_IRQ - General Purpose ADC interrupt. @@ -3565,6 +3944,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) /*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. @@ -3572,13 +3952,15 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT (24U) -/*! ACMP_CAPT0_IRQ - Analog Comparator interrupt. + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U) +/*! ACMP_IRQ - Analog Comparator interrupt. * 0b0.. * 0b1.. */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) /*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. @@ -3586,6 +3968,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) /*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. @@ -3593,6 +3976,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) /*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. @@ -3600,13 +3984,15 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) -/*! USB0_IRQ - USB High Speed Controller interrupt. +/*! USB0_IRQ - USB Full Speed Controller interrupt. * 0b0.. * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) /*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ @@ -3614,6 +4000,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) /*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. @@ -3621,6 +4008,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) /*! MAILBOX_IRQ - Mailbox interrupt. @@ -3632,6 +4020,7 @@ typedef struct { /*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) /*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. @@ -3639,6 +4028,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) /*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. @@ -3646,6 +4036,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) /*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. @@ -3653,6 +4044,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) /*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. @@ -3660,6 +4052,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) /*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. @@ -3667,6 +4060,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) /*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. @@ -3674,6 +4068,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) /*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts @@ -3681,6 +4076,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) /*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. @@ -3688,6 +4084,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) /*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. @@ -3695,6 +4092,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) /*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. @@ -3702,6 +4100,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) /*! SDIO_IRQ - SDIO Controller interrupt. @@ -3709,6 +4108,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) /*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. @@ -3716,6 +4116,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) /*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. @@ -3723,6 +4124,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) /*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. @@ -3730,13 +4132,15 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT (14U) -/*! USB1_UTMI_IRQ - USB High Speed Controller UTMI interrupt. + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U) +/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. * 0b0.. * 0b1.. */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) /*! USB1_IRQ - USB High Speed Controller interrupt. @@ -3744,6 +4148,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) /*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. @@ -3751,6 +4156,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) /*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. @@ -3758,6 +4164,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) /*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. @@ -3765,6 +4172,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) /*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. @@ -3772,6 +4180,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) /*! PLU_IRQ - Programmable Look-Up Controller interrupt. @@ -3779,6 +4188,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) /*! SEC_VIO_IRQ - Security Violation interrupt. @@ -3786,6 +4196,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) /*! SHA_IRQ - HASH-AES interrupt. @@ -3793,6 +4204,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) /*! CASPER_IRQ - CASPER interrupt. @@ -3800,13 +4212,15 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT (24U) -/*! QDDKEY_IRQ - PUF interrupt. + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U) +/*! PUFKEY_IRQ - PUF interrupt. * 0b0.. * 0b1.. */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) /*! PQ_IRQ - Power Quad interrupt. @@ -3814,6 +4228,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) /*! SDMA1_IRQ - System DMA 1 (Secure) interrupt @@ -3821,6 +4236,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) /*! LSPI_HS_IRQ - High Speed SPI interrupt @@ -3832,6 +4248,7 @@ typedef struct { /*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) /*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. @@ -3839,6 +4256,7 @@ typedef struct { * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) + #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) /*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. @@ -3846,6 +4264,7 @@ typedef struct { * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) + #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) /*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. @@ -3853,6 +4272,7 @@ typedef struct { * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) + #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) /*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. @@ -3864,24 +4284,27 @@ typedef struct { /*! @name MASTER_SEC_LEVEL - master secure level register */ /*! @{ */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT (4U) -/*! MCM33C - Micro-CM33 (CPU1) Code bus. + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT (6U) -/*! MCM33S - Micro-CM33 (CPU1) System bus. +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) /*! USBFSD - USB Full Speed Device. @@ -3891,6 +4314,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) /*! SDMA0 - System DMA 0. @@ -3900,6 +4324,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) /*! SDIO - SDIO. @@ -3909,6 +4334,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) /*! PQ - Power Quad. @@ -3918,6 +4344,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) /*! HASH - Hash. @@ -3927,6 +4354,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) /*! USBFSH - USB Full speed Host. @@ -3936,6 +4364,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) /*! SDMA1 - System DMA 1 security level. @@ -3945,6 +4374,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) /*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. @@ -3956,24 +4386,27 @@ typedef struct { /*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ /*! @{ */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT (4U) -/*! MCM33C - Micro-CM33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33C) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) * 0b11..Non-secure and Non-priviledge user access allowed. * 0b10..Non-secure and Privilege access allowed. * 0b01..Secure and Non-priviledge user access allowed. * 0b00..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT (6U) -/*! MCM33S - Micro-CM33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33S) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) * 0b11..Non-secure and Non-priviledge user access allowed. * 0b10..Non-secure and Privilege access allowed. * 0b01..Secure and Non-priviledge user access allowed. * 0b00..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) /*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) @@ -3983,6 +4416,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) /*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) @@ -3992,6 +4426,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) /*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) @@ -4001,6 +4436,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) /*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) @@ -4010,6 +4446,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) /*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) @@ -4019,6 +4456,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) /*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) @@ -4028,6 +4466,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) /*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) @@ -4037,6 +4476,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) /*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. @@ -4046,107 +4486,121 @@ typedef struct { #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) /*! @} */ -/*! @name CM33_LOCK_REG - Miscalleneous control signals for in CM33 (CPU0) */ +/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ /*! @{ */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - CM33 (CPU0) VTOR_NS register write-lock. + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - CM33 (CPU0) non-secure MPU register write-lock. +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) -/*! LOCK_S_VTAIRCR - CM33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U) -/*! LOCK_S_MPU - CM33 (CPU0) Secure MPU registers write-lock. +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U) -/*! LOCK_SAU - CM33 (CPU0) SAU registers write-lock. +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) -/*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG write-lock. +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) /*! @} */ -/*! @name MCM33_LOCK_REG - Miscalleneous control signals for in micro-CM33 (CPU1) */ +/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */ /*! @{ */ -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - micro-CM33 (CPU1) VTOR_NS register write-lock. + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - micro-CM33 (CPU1) non-secure MPU register write-lock. +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT (30U) -/*! MCM33_LOCK_REG_LOCK - MCM33_LOCK_REG write-lock. +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK) /*! @} */ /*! @name MISC_CTRL_DP_REG - secure control duplicate register */ /*! @{ */ + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - write lock. +/*! WRITE_LOCK - Write lock. * 0b10..Secure control registers can be written. * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. * 0b10..Disable check. * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. * 0b10..Disable check. * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. * 0b10..Disable check. * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. @@ -4154,6 +4608,7 @@ typedef struct { * 0b01..Disable abort fort secure checker. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. @@ -4161,6 +4616,7 @@ typedef struct { * 0b01..Simple master in tier mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. @@ -4168,6 +4624,7 @@ typedef struct { * 0b01..Smart master in tier mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) /*! IDAU_ALL_NS - Disable IDAU. @@ -4179,34 +4636,39 @@ typedef struct { /*! @name MISC_CTRL_REG - secure control register */ /*! @{ */ + #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - write lock. +/*! WRITE_LOCK - Write lock. * 0b10..Secure control registers can be written. * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. * 0b10..Disable check. - * 0b01..Restricted mode. + * 0b01..Enabled (restricted mode) */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. * 0b10..Disable check. - * 0b01..Restricted mode. + * 0b01..Enabled (restricted mode) */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. * 0b10..Disable check. - * 0b01..Restricted mode. + * 0b01..Enabled (restricted mode) */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. @@ -4214,6 +4676,7 @@ typedef struct { * 0b01..Disable abort fort secure checker. */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. @@ -4221,6 +4684,7 @@ typedef struct { * 0b01..Simple master in tier mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. @@ -4228,6 +4692,7 @@ typedef struct { * 0b01..Smart master in tier mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) /*! IDAU_ALL_NS - Disable IDAU. @@ -4244,7 +4709,7 @@ typedef struct { /* AHB_SECURE_CTRL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral AHB_SECURE_CTRL base address */ #define AHB_SECURE_CTRL_BASE (0x500AC000u) /** Peripheral AHB_SECURE_CTRL base address */ @@ -4296,8 +4761,8 @@ typedef struct { __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ uint8_t RESERVED_1[4]; - __IO uint32_t XO32M_CTRL; /**< 32 MHz Crystal Oscillator Control register, offset: 0x20 */ - __I uint32_t XO32M_STATUS; /**< 32 MHz Crystal Oscillator Status register, offset: 0x24 */ + __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ + __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ uint8_t RESERVED_2[8]; __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ @@ -4307,14 +4772,10 @@ typedef struct { __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ uint8_t RESERVED_4[100]; __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ - uint8_t RESERVED_5[12]; - __IO uint32_t XO_CAL_CFG; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register, offset: 0xC0 */ - __IO uint32_t XO_CAL_CMD; /**< All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register., offset: 0xC4 */ - __I uint32_t XO_CAL_STATUS; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register., offset: 0xC8 */ - uint8_t RESERVED_6[52]; + __IO uint32_t AUX_BIAS; /**< AUX_BIAS, offset: 0xB4 */ + uint8_t RESERVED_5[72]; __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ - __I uint32_t USBHS_PHY_STATUS; /**< USB High Speed Phy Status, offset: 0x108 */ } ANACTRL_Type; /* ---------------------------------------------------------------------------- @@ -4328,6 +4789,7 @@ typedef struct { /*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ /*! @{ */ + #define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) #define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) /*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. @@ -4339,12 +4801,7 @@ typedef struct { /*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ /*! @{ */ -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK (0x3FU) -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT (0U) -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK (0xFC0U) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT (6U) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK) + #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) /*! FLASH_PWRDWN - Flash Power Down status. @@ -4352,6 +4809,7 @@ typedef struct { * 0b1..Flash is in power down mode. */ #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) + #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) /*! FLASH_INIT_ERROR - Flash initialization error status. @@ -4359,29 +4817,29 @@ typedef struct { * 0b1..At least one error occured during flash initialization.. */ #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK (0xF0000000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT (28U) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK) /*! @} */ /*! @name FREQ_ME_CTRL - Frequency Measure function control register */ /*! @{ */ + #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) +/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale + */ #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) + #define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) #define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) +/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit + * when the measurement cycle has completed and there is valid capture data in the CAPVAL field + * (bits 30:0). + */ #define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) /*! @} */ /*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ /*! @{ */ -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK (0x3FU) -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT (0U) -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK (0x3F80U) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT (7U) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK) + #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) /*! ENA_12MHZCLK - 12 MHz clock control. @@ -4389,25 +4847,35 @@ typedef struct { * 0b1..12 MHz clock is enabled. */ #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) + #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) /*! ENA_48MHZCLK - 48 MHz clock control. - * 0b0..48 MHz clock is disabled. + * 0b0..Reserved. * 0b1..48 MHz clock is enabled. */ #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) + #define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) #define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) +/*! DAC_TRIM - Frequency trim. + */ #define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) + #define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) #define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) +/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, + * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF + * packets. + */ #define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) + #define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) #define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) +/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. + */ #define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK (0x30000000U) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT (28U) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT)) & ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK) + #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) /*! ENA_96MHZCLK - 96 MHz clock control. @@ -4415,13 +4883,17 @@ typedef struct { * 0b1..96 MHz clock is enabled. */ #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) + #define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) #define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) +/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. + */ #define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) /*! @} */ /*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ /*! @{ */ + #define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) #define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) /*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. @@ -4430,13 +4902,19 @@ typedef struct { * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). */ #define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) + #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) +/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses + * the threshold voltage of a SLVT transistor, this output signal will go high. It is also + * possible to observe the clk_valid signal. + */ #define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) /*! @} */ /*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ /*! @{ */ + #define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) #define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) /*! VBATDIVENABLE - Switch On/Off VBAT divider branch. @@ -4446,23 +4924,27 @@ typedef struct { #define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) /*! @} */ -/*! @name XO32M_CTRL - 32 MHz Crystal Oscillator Control register */ +/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ /*! @{ */ -#define ANACTRL_XO32M_CTRL_GM_MASK (0xEU) -#define ANACTRL_XO32M_CTRL_GM_SHIFT (1U) -#define ANACTRL_XO32M_CTRL_GM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_GM_SHIFT)) & ANACTRL_XO32M_CTRL_GM_MASK) + #define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) #define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) +/*! SLAVE - Xo in slave mode. + */ #define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) -#define ANACTRL_XO32M_CTRL_AMP_MASK (0xE0U) -#define ANACTRL_XO32M_CTRL_AMP_SHIFT (5U) -#define ANACTRL_XO32M_CTRL_AMP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_AMP_SHIFT)) & ANACTRL_XO32M_CTRL_AMP_MASK) + #define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) #define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) +/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin + */ #define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) + #define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) #define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) +/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin + */ #define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) + #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) /*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. @@ -4470,48 +4952,27 @@ typedef struct { * 0b1..XO AC buffer bypass is enabled. */ #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) + #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) -/*! ENABLE_PLL_USB_OUT - Enable XO 32 MHz output to USB HS PLL. - * 0b0..XO 32 MHz output to USB HS PLL is disabled. - * 0b1..XO 32 MHz output to USB HS PLL is enabled. +/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. + * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. + * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. */ #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) + #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) -/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system. - * 0b0..XO 32 MHz output to CPU system is disabled. - * 0b1..XO 32 MHz output to CPU system is enabled. +/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. + * 0b0..High speed Crystal oscillator output to CPU system is disabled. + * 0b1..High speed Crystal oscillator output to CPU system is enabled. */ #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK (0x2000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT (25U) -/*! CAPTESTSTARTSRCSEL - Source selection for 'xo32k_captest_start' signal. - * 0b0..Sourced from CAPTESTSTART. - * 0b1..Sourced from calibration. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK (0x4000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT (26U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK (0x8000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT (27U) -/*! CAPTESTENABLE - Enable signal for captest. - * 0b0..Captest is disabled. - * 0b1..Captest is enabled. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK (0x10000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT (28U) -/*! CAPTESTOSCINSEL - Select the input for test. - * 0b0..osc_out (oscillator output) pin. - * 0b1..osc_in (oscillator) pin. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK) /*! @} */ -/*! @name XO32M_STATUS - 32 MHz Crystal Oscillator Status register */ +/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ /*! @{ */ + #define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) #define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) /*! XO_READY - Indicates XO out frequency statibilty. @@ -4523,6 +4984,7 @@ typedef struct { /*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ /*! @{ */ + #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) /*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. @@ -4530,9 +4992,13 @@ typedef struct { * 0b1..BOD VBAT interrupt is enabled. */ #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) + #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) +/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) + #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) /*! BODCORE_INT_ENABLE - BOD CORE interrupt control. @@ -4540,9 +5006,13 @@ typedef struct { * 0b1..BOD CORE interrupt is enabled. */ #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) + #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) +/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) + #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) /*! DCDC_INT_ENABLE - DCDC interrupt control. @@ -4550,13 +5020,17 @@ typedef struct { * 0b1..DCDC interrupt is enabled. */ #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) + #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) +/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) /*! @} */ /*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ /*! @{ */ + #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) /*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. @@ -4564,6 +5038,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) /*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. @@ -4571,6 +5046,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) /*! BODVBAT_VAL - Current value of BOD VBAT power status output. @@ -4578,6 +5054,7 @@ typedef struct { * 0b1..VBAT voltage level is above the threshold. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) /*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. @@ -4585,6 +5062,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) /*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. @@ -4592,6 +5070,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) /*! BODCORE_VAL - Current value of BOD CORE power status output. @@ -4599,6 +5078,7 @@ typedef struct { * 0b1..CORE voltage level is above the threshold. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) /*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. @@ -4606,6 +5086,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) /*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. @@ -4613,6 +5094,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) /*! DCDC_VAL - Current value of DCDC power status output. @@ -4624,6 +5106,7 @@ typedef struct { /*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ /*! @{ */ + #define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) #define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) /*! SL - Select short or long ringo (for all ringos types). @@ -4631,6 +5114,7 @@ typedef struct { * 0b1..Select long ringo (many elements). */ #define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) + #define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) #define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) /*! FS - Ringo frequency output divider. @@ -4638,6 +5122,7 @@ typedef struct { * 0b1..Low frequency output (frequency lower than 10 MHz). */ #define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) + #define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) #define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) /*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. @@ -4647,6 +5132,7 @@ typedef struct { * 0b11..Don't use. */ #define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) + #define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) #define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) /*! PD - Ringo module Power control. @@ -4654,6 +5140,7 @@ typedef struct { * 0b1..The Ringo module is disabled. */ #define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) + #define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) #define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) /*! E_ND0 - First NAND2-based ringo control. @@ -4661,6 +5148,7 @@ typedef struct { * 0b1..First NAND2-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) + #define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) #define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) /*! E_ND1 - Second NAND2-based ringo control. @@ -4668,6 +5156,7 @@ typedef struct { * 0b1..Second NAND2-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) + #define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) #define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) /*! E_NR0 - First NOR2-based ringo control. @@ -4675,6 +5164,7 @@ typedef struct { * 0b1..First NOR2-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) + #define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) #define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) /*! E_NR1 - Second NOR2-based ringo control. @@ -4682,6 +5172,7 @@ typedef struct { * 0b1..Second NORD2-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) + #define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) #define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) /*! E_IV0 - First Inverter-based ringo control. @@ -4689,6 +5180,7 @@ typedef struct { * 0b1..First INV-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) + #define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) #define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) /*! E_IV1 - Second Inverter-based ringo control. @@ -4696,6 +5188,7 @@ typedef struct { * 0b1..Second INV-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) + #define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) #define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) /*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. @@ -4703,6 +5196,7 @@ typedef struct { * 0b1..First PN-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) + #define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) #define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) /*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. @@ -4710,16 +5204,24 @@ typedef struct { * 0b1..Second PN-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) + #define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) #define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ #define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) + #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) /*! @} */ /*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ /*! @{ */ + #define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) #define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) /*! S - Select short or long ringo (for all ringos types). @@ -4727,6 +5229,7 @@ typedef struct { * 0b1..Select long ringo (many elements). */ #define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) + #define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) #define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) /*! FS - Ringo frequency output divider. @@ -4734,6 +5237,7 @@ typedef struct { * 0b1..Low frequency output (frequency lower than 10 MHz). */ #define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) + #define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) #define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) /*! PD - Ringo module Power control. @@ -4741,6 +5245,7 @@ typedef struct { * 0b1..The Ringo module is disabled. */ #define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) + #define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) #define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) /*! E_R24 - . @@ -4748,6 +5253,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) + #define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) #define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) /*! E_R35 - . @@ -4755,6 +5261,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) + #define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) #define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) /*! E_M2 - Metal 2 (M2) monitor control. @@ -4762,6 +5269,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) + #define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) #define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) /*! E_M3 - Metal 3 (M3) monitor control. @@ -4769,6 +5277,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) + #define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) #define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) /*! E_M4 - Metal 4 (M4) monitor control. @@ -4776,6 +5285,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) + #define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) #define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) /*! E_M5 - Metal 5 (M5) monitor control. @@ -4783,16 +5293,24 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) + #define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) #define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ #define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) + #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) /*! @} */ /*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ /*! @{ */ + #define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) #define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) /*! S - Select short or long ringo (for all ringos types). @@ -4800,6 +5318,7 @@ typedef struct { * 0b1..Select long ringo (many elements). */ #define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) + #define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) #define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) /*! FS - Ringo frequency output divider. @@ -4807,6 +5326,7 @@ typedef struct { * 0b1..Low frequency output (frequency lower than 10 MHz). */ #define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) + #define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) #define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) /*! PD - Ringo module Power control. @@ -4814,6 +5334,7 @@ typedef struct { * 0b1..The Ringo module is disabled. */ #define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) + #define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) #define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) /*! E_R24 - . @@ -4821,6 +5342,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) + #define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) #define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) /*! E_R35 - . @@ -4828,6 +5350,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) + #define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) #define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) /*! E_M2 - Metal 2 (M2) monitor control. @@ -4835,6 +5358,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) + #define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) #define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) /*! E_M3 - Metal 3 (M3) monitor control. @@ -4842,6 +5366,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) + #define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) #define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) /*! E_M4 - Metal 4 (M4) monitor control. @@ -4849,6 +5374,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) + #define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) #define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) /*! E_M5 - Metal 5 (M5) monitor control. @@ -4856,16 +5382,24 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) + #define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) #define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ #define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) + #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) /*! @} */ /*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ /*! @{ */ + #define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) #define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) /*! BYPASS - Activate LDO bypass. @@ -4873,6 +5407,7 @@ typedef struct { * 0b1..Activate LDO bypass. */ #define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) + #define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) #define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) /*! HIGHZ - . @@ -4880,6 +5415,7 @@ typedef struct { * 0b1..Output in High Impedance state. */ #define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) + #define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) #define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) /*! VOUT - Sets the LDO output level. @@ -4893,126 +5429,130 @@ typedef struct { * 0b111..0.925 V. */ #define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) + #define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) #define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) +/*! IBIAS - Adjust the biasing current. + */ #define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) + #define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) #define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) +/*! STABMODE - Stability configuration. + */ #define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) /*! @} */ -/*! @name XO_CAL_CFG - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register */ +/*! @name AUX_BIAS - AUX_BIAS */ /*! @{ */ -#define ANACTRL_XO_CAL_CFG_START_INV_MASK (0x1U) -#define ANACTRL_XO_CAL_CFG_START_INV_SHIFT (0U) -#define ANACTRL_XO_CAL_CFG_START_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_START_INV_MASK) -#define ANACTRL_XO_CAL_CFG_START_OVR_MASK (0x2U) -#define ANACTRL_XO_CAL_CFG_START_OVR_SHIFT (1U) -#define ANACTRL_XO_CAL_CFG_START_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_OVR_SHIFT)) & ANACTRL_XO_CAL_CFG_START_OVR_MASK) -#define ANACTRL_XO_CAL_CFG_START_MASK (0x4U) -#define ANACTRL_XO_CAL_CFG_START_SHIFT (2U) -#define ANACTRL_XO_CAL_CFG_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_SHIFT)) & ANACTRL_XO_CAL_CFG_START_MASK) -#define ANACTRL_XO_CAL_CFG_STOP_INV_MASK (0x8U) -#define ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT (3U) -#define ANACTRL_XO_CAL_CFG_STOP_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_INV_MASK) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK (0x10U) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT (4U) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK) -#define ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK (0x20U) -#define ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT (5U) -/*! XO32K_MODE - When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal oscillator calibration is used. - * 0b0..High speed crystal oscillator (12 MHz- 32 MHz) is used - * 0b1..32 kHz crystal oscillator calibration is used. + +#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK (0x2U) +#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT (1U) +/*! VREF1VENABLE - Control output of 1V reference voltage. + * 0b0..Output of 1V reference voltage buffer is bypassed. + * 0b1..Output of 1V reference voltage is enabled. */ -#define ANACTRL_XO_CAL_CFG_XO32K_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT)) & ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK) -/*! @} */ +#define ANACTRL_AUX_BIAS_VREF1VENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK) -/*! @name XO_CAL_CMD - All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register. */ -/*! @{ */ -#define ANACTRL_XO_CAL_CMD_START_MASK (0x1U) -#define ANACTRL_XO_CAL_CMD_START_SHIFT (0U) -#define ANACTRL_XO_CAL_CMD_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_START_SHIFT)) & ANACTRL_XO_CAL_CMD_START_MASK) -#define ANACTRL_XO_CAL_CMD_STOP_MASK (0x2U) -#define ANACTRL_XO_CAL_CMD_STOP_SHIFT (1U) -#define ANACTRL_XO_CAL_CMD_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_STOP_SHIFT)) & ANACTRL_XO_CAL_CMD_STOP_MASK) -#define ANACTRL_XO_CAL_CMD_OVR_MASK (0x4U) -#define ANACTRL_XO_CAL_CMD_OVR_SHIFT (2U) -#define ANACTRL_XO_CAL_CMD_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_OVR_SHIFT)) & ANACTRL_XO_CAL_CMD_OVR_MASK) -/*! @} */ +#define ANACTRL_AUX_BIAS_ITRIM_MASK (0x7CU) +#define ANACTRL_AUX_BIAS_ITRIM_SHIFT (2U) +/*! ITRIM - current trimming control word. + */ +#define ANACTRL_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK) -/*! @name XO_CAL_STATUS - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register. */ -/*! @{ */ -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK (0xFFFFU) -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT (0U) -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT)) & ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK) -#define ANACTRL_XO_CAL_STATUS_DONE_MASK (0x10000U) -#define ANACTRL_XO_CAL_STATUS_DONE_SHIFT (16U) -#define ANACTRL_XO_CAL_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_DONE_SHIFT)) & ANACTRL_XO_CAL_STATUS_DONE_MASK) +#define ANACTRL_AUX_BIAS_PTATITRIM_MASK (0xF80U) +#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT (7U) +/*! PTATITRIM - current trimming control word for ptat current. + */ +#define ANACTRL_AUX_BIAS_PTATITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK (0x1F000U) +#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT (12U) +/*! VREF1VTRIM - voltage trimming control word. + */ +#define ANACTRL_AUX_BIAS_VREF1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK (0xE0000U) +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT (17U) +/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK (0x100000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT (20U) +/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK (0x200000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT (21U) +/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK) /*! @} */ /*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ /*! @{ */ + #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) +/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors. + */ #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) + #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) +/*! usb_id_ext - Override value for ID if using external detectors. + */ #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK (0x8U) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT (3U) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK) /*! @} */ /*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ /*! @{ */ + #define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) #define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) +/*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) +/*! trim_usbphy_tx_d_cal - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) +/*! trim_usbphy_tx_cal45dp - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) +/*! trim_usbphy_tx_cal45dm - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) +/*! trim_usb2_refbias_tst - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) +/*! trim_usb2_refbias_vbgadj - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) #define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) +/*! trim_pll_ctrl0_div_sel - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) /*! @} */ -/*! @name USBHS_PHY_STATUS - USB High Speed Phy Status */ -/*! @{ */ -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK (0x1U) -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT (0U) -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK (0x2U) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT (1U) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK (0x4U) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT (2U) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK (0x8U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT (3U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK (0x10U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT (4U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK (0x20U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT (5U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK (0x40U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT (6U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK) -/*! @} */ - /*! * @} @@ -5020,7 +5560,7 @@ typedef struct { /* ANACTRL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral ANACTRL base address */ #define ANACTRL_BASE (0x50013000u) /** Peripheral ANACTRL base address */ @@ -5098,6 +5638,7 @@ typedef struct { /*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ /*! @{ */ + #define CASPER_CTRL0_ABBPAIR_MASK (0x1U) #define CASPER_CTRL0_ABBPAIR_SHIFT (0U) /*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up @@ -5105,9 +5646,15 @@ typedef struct { * 0b1..Bank-pair 1 (2nd) */ #define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) -#define CASPER_CTRL0_ABOFF_MASK (0x4U) + +#define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) #define CASPER_CTRL0_ABOFF_SHIFT (2U) +/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code + * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed + * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up + */ #define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) + #define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) #define CASPER_CTRL0_CDBPAIR_SHIFT (16U) /*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up @@ -5115,19 +5662,31 @@ typedef struct { * 0b1..Bank-pair 1 (2nd) */ #define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) + #define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) #define CASPER_CTRL0_CDOFF_SHIFT (18U) +/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees + * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 + * bit operation. Ideally not in the same RAM as the AB values + */ #define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) /*! @} */ /*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ /*! @{ */ + #define CASPER_CTRL1_ITER_MASK (0xFFU) #define CASPER_CTRL1_ITER_SHIFT (0U) +/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. + */ #define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) + #define CASPER_CTRL1_MODE_MASK (0xFF00U) #define CASPER_CTRL1_MODE_SHIFT (8U) +/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. + */ #define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) + #define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) #define CASPER_CTRL1_RESBPAIR_SHIFT (16U) /*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally @@ -5136,9 +5695,14 @@ typedef struct { * 0b1..Bank-pair 1 (2nd) */ #define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) + #define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) #define CASPER_CTRL1_RESOFF_SHIFT (18U) +/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally + * not in the same RAM as the AB and CD values + */ #define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) + #define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) #define CASPER_CTRL1_CSKIP_SHIFT (30U) /*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: @@ -5152,9 +5716,14 @@ typedef struct { /*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ /*! @{ */ + #define CASPER_LOADER_COUNT_MASK (0xFFU) #define CASPER_LOADER_COUNT_SHIFT (0U) +/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one + * op - does not iterate, write N means N control pairs to load + */ #define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) + #define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) #define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) /*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not @@ -5163,13 +5732,17 @@ typedef struct { * 0b1..Bank-pair 1 (2nd) */ #define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) + #define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) #define CASPER_LOADER_CTRLOFF_SHIFT (18U) +/*! CTRLOFF - DWord Offset of CTRL pair to load next. + */ #define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) /*! @} */ /*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ /*! @{ */ + #define CASPER_STATUS_DONE_MASK (0x1U) #define CASPER_STATUS_DONE_SHIFT (0U) /*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. @@ -5177,6 +5750,7 @@ typedef struct { * 0b1..Completed last operation */ #define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) + #define CASPER_STATUS_CARRY_MASK (0x10U) #define CASPER_STATUS_CARRY_SHIFT (4U) /*! CARRY - Last carry value if operation produced a carry bit @@ -5184,6 +5758,7 @@ typedef struct { * 0b1..Carry was 1 */ #define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) + #define CASPER_STATUS_BUSY_MASK (0x20U) #define CASPER_STATUS_BUSY_SHIFT (5U) /*! BUSY - Indicates if the accelerator is busy performing an operation @@ -5195,6 +5770,7 @@ typedef struct { /*! @name INTENSET - Sets interrupts */ /*! @{ */ + #define CASPER_INTENSET_DONE_MASK (0x1U) #define CASPER_INTENSET_DONE_SHIFT (0U) /*! DONE - Set if the accelerator should interrupt when done. @@ -5206,6 +5782,7 @@ typedef struct { /*! @name INTENCLR - Clears interrupts */ /*! @{ */ + #define CASPER_INTENCLR_DONE_MASK (0x1U) #define CASPER_INTENCLR_DONE_SHIFT (0U) /*! DONE - Written to clear an interrupt set with INTENSET. @@ -5217,6 +5794,7 @@ typedef struct { /*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ /*! @{ */ + #define CASPER_INTSTAT_DONE_MASK (0x1U) #define CASPER_INTSTAT_DONE_SHIFT (0U) /*! DONE - If set, interrupt is caused by accelerator being done. @@ -5228,76 +5806,115 @@ typedef struct { /*! @name AREG - A register */ /*! @{ */ + #define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_AREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ #define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) /*! @} */ /*! @name BREG - B register */ /*! @{ */ + #define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_BREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ #define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) /*! @} */ /*! @name CREG - C register */ /*! @{ */ + #define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_CREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ #define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) /*! @} */ /*! @name DREG - D register */ /*! @{ */ + #define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_DREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ #define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) /*! @} */ /*! @name RES0 - Result register 0 */ /*! @{ */ + #define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_RES0_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ #define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) /*! @} */ /*! @name RES1 - Result register 1 */ /*! @{ */ + #define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_RES1_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ #define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) /*! @} */ /*! @name RES2 - Result register 2 */ /*! @{ */ + #define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_RES2_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ #define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) /*! @} */ /*! @name RES3 - Result register 3 */ /*! @{ */ + #define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_RES3_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ #define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) /*! @} */ /*! @name MASK - Optional mask register */ /*! @{ */ + #define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) #define CASPER_MASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + */ #define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) /*! @} */ /*! @name REMASK - Optional re-mask register */ /*! @{ */ + #define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) #define CASPER_REMASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + */ #define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) /*! @} */ /*! @name LOCK - Security lock register */ /*! @{ */ + #define CASPER_LOCK_LOCK_MASK (0x1U) #define CASPER_LOCK_LOCK_SHIFT (0U) /*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. @@ -5305,6 +5922,7 @@ typedef struct { * 0b1..Lock to current security level */ #define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) + #define CASPER_LOCK_KEY_MASK (0x1FFF0U) #define CASPER_LOCK_KEY_SHIFT (4U) /*! KEY - Must be written as 0x73D to change the register. @@ -5320,7 +5938,7 @@ typedef struct { /* CASPER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral CASPER base address */ #define CASPER_BASE (0x500A5000u) /** Peripheral CASPER base address */ @@ -5347,6 +5965,8 @@ typedef struct { /** Array initializer of CASPER peripheral base pointers */ #define CASPER_BASE_PTRS { CASPER } #endif +/** Interrupt vectors for the CASPER peripheral type */ +#define CASPER_IRQS { CASER_IRQn } /*! * @} @@ -5383,41 +6003,69 @@ typedef struct { /*! @name MODE - CRC mode register */ /*! @{ */ + #define CRC_MODE_CRC_POLY_MASK (0x3U) #define CRC_MODE_CRC_POLY_SHIFT (0U) +/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial + */ #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) + #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) + */ #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) + #define CRC_MODE_CMPL_WR_MASK (0x8U) #define CRC_MODE_CMPL_WR_SHIFT (3U) +/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA + */ #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) + #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM + */ #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) + #define CRC_MODE_CMPL_SUM_MASK (0x20U) #define CRC_MODE_CMPL_SUM_SHIFT (5U) +/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM + */ #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) /*! @} */ /*! @name SEED - CRC seed register */ /*! @{ */ + #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) #define CRC_SEED_CRC_SEED_SHIFT (0U) +/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with + * selected bit order and 1's complement pre-processes. A write access to this register will + * overrule the CRC calculation in progresses. + */ #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) /*! @} */ /*! @name SUM - CRC checksum register */ /*! @{ */ + #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) #define CRC_SUM_CRC_SUM_SHIFT (0U) +/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. + */ #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) /*! @} */ /*! @name WR_DATA - CRC data register */ /*! @{ */ + #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with + * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and + * accept back-to-back transactions. + */ #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) /*! @} */ @@ -5428,7 +6076,7 @@ typedef struct { /* CRC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral CRC_ENGINE base address */ #define CRC_ENGINE_BASE (0x50095000u) /** Peripheral CRC_ENGINE base address */ @@ -5499,34 +6147,59 @@ typedef struct { /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ /*! @{ */ + #define CTIMER_IR_MR0INT_MASK (0x1U) #define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt flag for match channel 0. + */ #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + #define CTIMER_IR_MR1INT_MASK (0x2U) #define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt flag for match channel 1. + */ #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + #define CTIMER_IR_MR2INT_MASK (0x4U) #define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt flag for match channel 2. + */ #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + #define CTIMER_IR_MR3INT_MASK (0x8U) #define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt flag for match channel 3. + */ #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + #define CTIMER_IR_CR0INT_MASK (0x10U) #define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt flag for capture channel 0 event. + */ #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + #define CTIMER_IR_CR1INT_MASK (0x20U) #define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt flag for capture channel 1 event. + */ #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + #define CTIMER_IR_CR2INT_MASK (0x40U) #define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt flag for capture channel 2 event. + */ #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + #define CTIMER_IR_CR3INT_MASK (0x80U) #define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt flag for capture channel 3 event. + */ #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) /*! @} */ /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ /*! @{ */ + #define CTIMER_TCR_CEN_MASK (0x1U) #define CTIMER_TCR_CEN_SHIFT (0U) /*! CEN - Counter enable. @@ -5534,6 +6207,7 @@ typedef struct { * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. */ #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + #define CTIMER_TCR_CRST_MASK (0x2U) #define CTIMER_TCR_CRST_SHIFT (1U) /*! CRST - Counter reset. @@ -5546,81 +6220,145 @@ typedef struct { /*! @name TC - Timer Counter */ /*! @{ */ + #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) #define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer counter value. + */ #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) /*! @} */ /*! @name PR - Prescale Register */ /*! @{ */ + #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) #define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale counter value. + */ #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) /*! @} */ /*! @name PC - Prescale Counter */ /*! @{ */ + #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) #define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale counter value. + */ #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) /*! @} */ /*! @name MCR - Match Control Register */ /*! @{ */ + #define CTIMER_MCR_MR0I_MASK (0x1U) #define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + */ #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + #define CTIMER_MCR_MR0R_MASK (0x2U) #define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. + */ #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + #define CTIMER_MCR_MR0S_MASK (0x4U) #define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + */ #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + #define CTIMER_MCR_MR1I_MASK (0x8U) #define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + */ #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + #define CTIMER_MCR_MR1R_MASK (0x10U) #define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. + */ #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + #define CTIMER_MCR_MR1S_MASK (0x20U) #define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + */ #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + #define CTIMER_MCR_MR2I_MASK (0x40U) #define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + */ #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + #define CTIMER_MCR_MR2R_MASK (0x80U) #define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. + */ #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + #define CTIMER_MCR_MR2S_MASK (0x100U) #define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + */ #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + #define CTIMER_MCR_MR3I_MASK (0x200U) #define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + */ #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + #define CTIMER_MCR_MR3R_MASK (0x400U) #define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. + */ #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + #define CTIMER_MCR_MR3S_MASK (0x800U) #define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + */ #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + #define CTIMER_MCR_MR0RL_MASK (0x1000000U) #define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ #define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + #define CTIMER_MCR_MR1RL_MASK (0x2000000U) #define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ #define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + #define CTIMER_MCR_MR2RL_MASK (0x4000000U) #define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ #define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + #define CTIMER_MCR_MR3RL_MASK (0x8000000U) #define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ #define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) /*! @} */ /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ /*! @{ */ + #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) #define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer counter match value. + */ #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) /*! @} */ @@ -5629,48 +6367,95 @@ typedef struct { /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ /*! @{ */ + #define CTIMER_CCR_CAP0RE_MASK (0x1U) #define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + #define CTIMER_CCR_CAP0FE_MASK (0x2U) #define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + #define CTIMER_CCR_CAP0I_MASK (0x4U) #define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. + */ #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + #define CTIMER_CCR_CAP1RE_MASK (0x8U) #define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + #define CTIMER_CCR_CAP1FE_MASK (0x10U) #define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + #define CTIMER_CCR_CAP1I_MASK (0x20U) #define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. + */ #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + #define CTIMER_CCR_CAP2RE_MASK (0x40U) #define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + #define CTIMER_CCR_CAP2FE_MASK (0x80U) #define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + #define CTIMER_CCR_CAP2I_MASK (0x100U) #define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. + */ #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + #define CTIMER_CCR_CAP3RE_MASK (0x200U) #define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + #define CTIMER_CCR_CAP3FE_MASK (0x400U) #define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + #define CTIMER_CCR_CAP3I_MASK (0x800U) #define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. + */ #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) /*! @} */ /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ /*! @{ */ + #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) #define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer counter capture value. + */ #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) /*! @} */ @@ -5679,18 +6464,43 @@ typedef struct { /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ /*! @{ */ + #define CTIMER_EMR_EM0_MASK (0x1U) #define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + #define CTIMER_EMR_EM1_MASK (0x2U) #define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + #define CTIMER_EMR_EM2_MASK (0x4U) #define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + #define CTIMER_EMR_EM3_MASK (0x8U) #define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins + * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + #define CTIMER_EMR_EMC0_MASK (0x30U) #define CTIMER_EMR_EMC0_SHIFT (4U) /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. @@ -5700,6 +6510,7 @@ typedef struct { * 0b11..Toggle. Toggle the corresponding External Match bit/output. */ #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + #define CTIMER_EMR_EMC1_MASK (0xC0U) #define CTIMER_EMR_EMC1_SHIFT (6U) /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. @@ -5709,6 +6520,7 @@ typedef struct { * 0b11..Toggle. Toggle the corresponding External Match bit/output. */ #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + #define CTIMER_EMR_EMC2_MASK (0x300U) #define CTIMER_EMR_EMC2_SHIFT (8U) /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. @@ -5718,6 +6530,7 @@ typedef struct { * 0b11..Toggle. Toggle the corresponding External Match bit/output. */ #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + #define CTIMER_EMR_EMC3_MASK (0xC00U) #define CTIMER_EMR_EMC3_SHIFT (10U) /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. @@ -5731,6 +6544,7 @@ typedef struct { /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ /*! @{ */ + #define CTIMER_CTCR_CTMODE_MASK (0x3U) #define CTIMER_CTCR_CTMODE_SHIFT (0U) /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment @@ -5742,6 +6556,7 @@ typedef struct { * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. */ #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + #define CTIMER_CTCR_CINSEL_MASK (0xCU) #define CTIMER_CTCR_CINSEL_SHIFT (2U) /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which @@ -5755,9 +6570,14 @@ typedef struct { * 0b11..Channel 3. CAPn.3 for CTIMERn */ #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + #define CTIMER_CTCR_ENCC_MASK (0x10U) #define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the + * capture-edge event specified in bits 7:5 occurs. + */ #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + #define CTIMER_CTCR_SELCC_MASK (0xE0U) #define CTIMER_CTCR_SELCC_SHIFT (5U) /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the @@ -5775,6 +6595,7 @@ typedef struct { /*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ /*! @{ */ + #define CTIMER_PWMC_PWMEN0_MASK (0x1U) #define CTIMER_PWMC_PWMEN0_SHIFT (0U) /*! PWMEN0 - PWM mode enable for channel0. @@ -5782,6 +6603,7 @@ typedef struct { * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. */ #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + #define CTIMER_PWMC_PWMEN1_MASK (0x2U) #define CTIMER_PWMC_PWMEN1_SHIFT (1U) /*! PWMEN1 - PWM mode enable for channel1. @@ -5789,6 +6611,7 @@ typedef struct { * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. */ #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + #define CTIMER_PWMC_PWMEN2_MASK (0x4U) #define CTIMER_PWMC_PWMEN2_SHIFT (2U) /*! PWMEN2 - PWM mode enable for channel2. @@ -5796,6 +6619,7 @@ typedef struct { * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. */ #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + #define CTIMER_PWMC_PWMEN3_MASK (0x8U) #define CTIMER_PWMC_PWMEN3_SHIFT (3U) /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. @@ -5807,9 +6631,12 @@ typedef struct { /*! @name MSR - Match Shadow Register */ /*! @{ */ -#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU) -#define CTIMER_MSR_SHADOWW_SHIFT (0U) -#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK) + +#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_SHADOW_SHIFT (0U) +/*! SHADOW - Timer counter match shadow value. + */ +#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) /*! @} */ /* The count of CTIMER_MSR */ @@ -5822,7 +6649,7 @@ typedef struct { /* CTIMER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral CTIMER0 base address */ #define CTIMER0_BASE (0x50008000u) /** Peripheral CTIMER0 base address */ @@ -5906,113 +6733,142 @@ typedef struct { /* ---------------------------------------------------------------------------- - -- DGBMAILBOX Peripheral Access Layer + -- DBGMAILBOX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup DGBMAILBOX_Peripheral_Access_Layer DGBMAILBOX Peripheral Access Layer + * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer * @{ */ -/** DGBMAILBOX - Register Layout Typedef */ +/** DBGMAILBOX - Register Layout Typedef */ typedef struct { __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ uint8_t RESERVED_0[240]; __I uint32_t ID; /**< Identification register, offset: 0xFC */ -} DGBMAILBOX_Type; +} DBGMAILBOX_Type; /* ---------------------------------------------------------------------------- - -- DGBMAILBOX Register Masks + -- DBGMAILBOX Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup DGBMAILBOX_Register_Masks DGBMAILBOX Register Masks + * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks * @{ */ /*! @name CSW - CRC mode register */ /*! @{ */ -#define DGBMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) -#define DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) -#define DGBMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DGBMAILBOX_CSW_RESYNCH_REQ_MASK) -#define DGBMAILBOX_CSW_REQ_PENDING_MASK (0x2U) -#define DGBMAILBOX_CSW_REQ_PENDING_SHIFT (1U) -#define DGBMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_REQ_PENDING_SHIFT)) & DGBMAILBOX_CSW_REQ_PENDING_MASK) -#define DGBMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) -#define DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) -#define DGBMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_DBG_OR_ERR_MASK) -#define DGBMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) -#define DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) -#define DGBMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_AHB_OR_ERR_MASK) -#define DGBMAILBOX_CSW_SOFT_RESET_MASK (0x10U) -#define DGBMAILBOX_CSW_SOFT_RESET_SHIFT (4U) -#define DGBMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_SOFT_RESET_SHIFT)) & DGBMAILBOX_CSW_SOFT_RESET_MASK) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK) + +#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation + */ +#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) + +#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) + */ +#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) + +#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) + */ +#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) + */ +#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to + * this bit will cause a soft reset for DM. + */ +#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) + +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is + * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) + */ +#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) /*! @} */ /*! @name REQUEST - CRC seed register */ /*! @{ */ -#define DGBMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_REQUEST_REQ_SHIFT (0U) -#define DGBMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_REQUEST_REQ_SHIFT)) & DGBMAILBOX_REQUEST_REQ_MASK) + +#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) +/*! REQ - Request Value + */ +#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) /*! @} */ /*! @name RETURN - Return value from ROM. */ /*! @{ */ -#define DGBMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_RETURN_RET_SHIFT (0U) -#define DGBMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_RETURN_RET_SHIFT)) & DGBMAILBOX_RETURN_RET_MASK) + +#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_RETURN_RET_SHIFT (0U) +/*! RET - The Return value from ROM. + */ +#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) /*! @} */ /*! @name ID - Identification register */ /*! @{ */ -#define DGBMAILBOX_ID_ID_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_ID_ID_SHIFT (0U) -#define DGBMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_ID_ID_SHIFT)) & DGBMAILBOX_ID_ID_MASK) + +#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_ID_ID_SHIFT (0U) +/*! ID - Identification value. + */ +#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) /*! @} */ /*! * @} - */ /* end of group DGBMAILBOX_Register_Masks */ + */ /* end of group DBGMAILBOX_Register_Masks */ -/* DGBMAILBOX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE (0x5009C000u) - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE_NS (0x4009C000u) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX_NS ((DGBMAILBOX_Type *)DGBMAILBOX_BASE_NS) - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS_NS { DGBMAILBOX_BASE_NS } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS_NS { DGBMAILBOX_NS } +/* DBGMAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x5009C000u) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE_NS (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } #else - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE (0x4009C000u) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } #endif /*! * @} - */ /* end of group DGBMAILBOX_Peripheral_Access_Layer */ + */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- @@ -6061,7 +6917,7 @@ typedef struct { __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ uint8_t RESERVED_0[4]; - } CHANNEL[30]; + } CHANNEL[23]; } DMA_Type; /* ---------------------------------------------------------------------------- @@ -6075,6 +6931,7 @@ typedef struct { /*! @name CTRL - DMA control. */ /*! @{ */ + #define DMA_CTRL_ENABLE_MASK (0x1U) #define DMA_CTRL_ENABLE_SHIFT (0U) /*! ENABLE - DMA controller master enable. @@ -6087,6 +6944,7 @@ typedef struct { /*! @name INTSTAT - Interrupt status. */ /*! @{ */ + #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) /*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. @@ -6094,6 +6952,7 @@ typedef struct { * 0b1..Pending. At least one enabled interrupt is pending. */ #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) + #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) /*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. @@ -6105,15 +6964,23 @@ typedef struct { /*! @name SRAMBASE - SRAM address of the channel configuration table. */ /*! @{ */ + #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) #define DMA_SRAMBASE_OFFSET_SHIFT (9U) +/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the + * table must begin on a 512 byte boundary. + */ #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) /*! @} */ /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. + */ #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) /*! @} */ @@ -6122,8 +6989,13 @@ typedef struct { /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears + * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits + * are reserved. + */ #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) /*! @} */ @@ -6132,8 +7004,12 @@ typedef struct { /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. + */ #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) /*! @} */ @@ -6142,8 +7018,12 @@ typedef struct { /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) #define DMA_COMMON_BUSY_BSY_SHIFT (0U) +/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. + */ #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) /*! @} */ @@ -6152,8 +7032,13 @@ typedef struct { /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is + * not active. 1 = error interrupt is active. + */ #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) /*! @} */ @@ -6162,8 +7047,13 @@ typedef struct { /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The + * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = + * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. + */ #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) /*! @} */ @@ -6172,8 +7062,13 @@ typedef struct { /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n + * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are + * reserved. + */ #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) /*! @} */ @@ -6182,8 +7077,13 @@ typedef struct { /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTA_IA_SHIFT (0U) +/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt A is not active. 1 = the DMA channel interrupt A is active. + */ #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) /*! @} */ @@ -6192,8 +7092,13 @@ typedef struct { /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTB_IB_SHIFT (0U) +/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt B is not active. 1 = the DMA channel interrupt B is active. + */ #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) /*! @} */ @@ -6202,8 +7107,13 @@ typedef struct { /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) #define DMA_COMMON_SETVALID_SV_SHIFT (0U) +/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits + * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the + * VALIDPENDING control bit for DMA channel n + */ #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) /*! @} */ @@ -6212,8 +7122,13 @@ typedef struct { /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number + * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = + * sets the TRIG bit for DMA channel n. + */ #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) /*! @} */ @@ -6222,8 +7137,12 @@ typedef struct { /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. + * 1 = aborts DMA operations on channel n. + */ #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) /*! @} */ @@ -6232,6 +7151,7 @@ typedef struct { /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ /*! @{ */ + #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) /*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory @@ -6241,6 +7161,7 @@ typedef struct { * 0b1..Enabled. Peripheral DMA requests are enabled. */ #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) + #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) /*! HWTRIGEN - Hardware Triggering Enable for this channel. @@ -6248,6 +7169,7 @@ typedef struct { * 0b1..Enabled. Use hardware triggering. */ #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) + #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) /*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. @@ -6255,6 +7177,7 @@ typedef struct { * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. */ #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) + #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) /*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. @@ -6266,6 +7189,7 @@ typedef struct { * current BURSTPOWER length are completed. */ #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) + #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) /*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. @@ -6276,9 +7200,21 @@ typedef struct { * complete. */ #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) + #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when + * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). + * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many + * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that + * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: + * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = + * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The + * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even + * multiple of the burst size. + */ #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) + #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) /*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is @@ -6289,6 +7225,7 @@ typedef struct { * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. */ #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) + #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) /*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is @@ -6299,16 +7236,21 @@ typedef struct { * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. */ #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) + #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority + * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. + */ #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) /*! @} */ /* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (30U) +#define DMA_CHANNEL_CFG_COUNT (23U) /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ /*! @{ */ + #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) /*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the @@ -6317,6 +7259,7 @@ typedef struct { * 0b1..Valid pending. */ #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) + #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) /*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is @@ -6328,10 +7271,11 @@ typedef struct { /*! @} */ /* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (30U) +#define DMA_CHANNEL_CTLSTAT_COUNT (23U) /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ /*! @{ */ + #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) /*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor @@ -6340,6 +7284,7 @@ typedef struct { * 0b1..Valid. The current channel descriptor is considered valid. */ #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) + #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) /*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current @@ -6348,6 +7293,7 @@ typedef struct { * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. */ #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) + #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) /*! SWTRIG - Software Trigger. @@ -6357,6 +7303,7 @@ typedef struct { * be used with level triggering when TRIGBURST = 0. */ #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) + #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) /*! CLRTRIG - Clear Trigger. @@ -6364,6 +7311,7 @@ typedef struct { * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted */ #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) + #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) /*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between @@ -6373,6 +7321,7 @@ typedef struct { * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. */ #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) + #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) /*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between @@ -6382,6 +7331,7 @@ typedef struct { * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. */ #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) + #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) /*! WIDTH - Transfer width used for this DMA channel. @@ -6391,6 +7341,7 @@ typedef struct { * 0b11..Reserved. Reserved setting, do not use. */ #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) + #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) /*! SRCINC - Determines whether the source address is incremented for each DMA transfer. @@ -6401,6 +7352,7 @@ typedef struct { * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. */ #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) + #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) /*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. @@ -6412,13 +7364,21 @@ typedef struct { * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. */ #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) + #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes + * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller + * uses this bit field during transfer to count down. Hence, it cannot be used by software to read + * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 + * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of + * 1,024 transfers will be performed. + */ #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) /*! @} */ /* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (30U) +#define DMA_CHANNEL_XFERCFG_COUNT (23U) /*! @@ -6427,7 +7387,7 @@ typedef struct { /* DMA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral DMA0 base address */ #define DMA0_BASE (0x50082000u) /** Peripheral DMA0 base address */ @@ -6487,13 +7447,12 @@ typedef struct { typedef struct { __O uint32_t CMD; /**< command register, offset: 0x0 */ __O uint32_t EVENT; /**< event register, offset: 0x4 */ - __IO uint32_t BURST; /**< read burst register, offset: 0x8 */ - uint8_t RESERVED_0[4]; + uint8_t RESERVED_0[8]; __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ uint8_t RESERVED_1[104]; - __IO uint32_t DATAW[8]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[3896]; + __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[3912]; __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ @@ -6515,173 +7474,263 @@ typedef struct { /*! @name CMD - command register */ /*! @{ */ + #define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) #define FLASH_CMD_CMD_SHIFT (0U) +/*! CMD - command register. + */ #define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) /*! @} */ /*! @name EVENT - event register */ /*! @{ */ + #define FLASH_EVENT_RST_MASK (0x1U) #define FLASH_EVENT_RST_SHIFT (0U) +/*! RST - When bit is set, the controller and flash are reset. + */ #define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) + #define FLASH_EVENT_WAKEUP_MASK (0x2U) #define FLASH_EVENT_WAKEUP_SHIFT (1U) +/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. + */ #define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) + #define FLASH_EVENT_ABORT_MASK (0x4U) #define FLASH_EVENT_ABORT_SHIFT (2U) +/*! ABORT - When bit is set, a running program/erase command is aborted. + */ #define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) /*! @} */ -/*! @name BURST - read burst register */ -/*! @{ */ -#define FLASH_BURST_XOR_MASK_MASK (0xFFFFFU) -#define FLASH_BURST_XOR_MASK_SHIFT (0U) -#define FLASH_BURST_XOR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_XOR_MASK_SHIFT)) & FLASH_BURST_XOR_MASK_MASK) -#define FLASH_BURST_DESCR1_MASK (0xF00000U) -#define FLASH_BURST_DESCR1_SHIFT (20U) -#define FLASH_BURST_DESCR1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR1_SHIFT)) & FLASH_BURST_DESCR1_MASK) -#define FLASH_BURST_DESCR2_MASK (0xF000000U) -#define FLASH_BURST_DESCR2_SHIFT (24U) -#define FLASH_BURST_DESCR2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR2_SHIFT)) & FLASH_BURST_DESCR2_MASK) -#define FLASH_BURST_DESCR3_MASK (0xF0000000U) -#define FLASH_BURST_DESCR3_SHIFT (28U) -#define FLASH_BURST_DESCR3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR3_SHIFT)) & FLASH_BURST_DESCR3_MASK) -/*! @} */ - /*! @name STARTA - start (or only) address for next flash command */ /*! @{ */ + #define FLASH_STARTA_STARTA_MASK (0x3FFFFU) #define FLASH_STARTA_STARTA_SHIFT (0U) +/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. + */ #define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) /*! @} */ /*! @name STOPA - end address for next flash command, if command operates on address ranges */ /*! @{ */ + #define FLASH_STOPA_STOPA_MASK (0x3FFFFU) #define FLASH_STOPA_STOPA_SHIFT (0U) +/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified + * by STOPA is included in the address range). + */ #define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) /*! @} */ /*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ /*! @{ */ + #define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) #define FLASH_DATAW_DATAW_SHIFT (0U) #define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) /*! @} */ /* The count of FLASH_DATAW */ -#define FLASH_DATAW_COUNT (8U) +#define FLASH_DATAW_COUNT (4U) /*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ /*! @{ */ + #define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) #define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ #define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) + #define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) #define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ #define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) + #define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) #define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ #define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) + #define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) #define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ #define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) /*! @} */ /*! @name INT_SET_ENABLE - Set interrupt enable bits */ /*! @{ */ + #define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) #define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ #define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) + #define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) #define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ #define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) + #define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) #define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ #define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) + #define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) #define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ #define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt status bits */ /*! @{ */ + #define FLASH_INT_STATUS_FAIL_MASK (0x1U) #define FLASH_INT_STATUS_FAIL_SHIFT (0U) +/*! FAIL - This status bit is set if execution of a (legal) command failed. + */ #define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) + #define FLASH_INT_STATUS_ERR_MASK (0x2U) #define FLASH_INT_STATUS_ERR_SHIFT (1U) +/*! ERR - This status bit is set if execution of an illegal command is detected. + */ #define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) + #define FLASH_INT_STATUS_DONE_MASK (0x4U) #define FLASH_INT_STATUS_DONE_SHIFT (2U) +/*! DONE - This status bit is set at the end of command execution. + */ #define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) + #define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) #define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested + * read, or a speculative read, or reads performed by a controller command), a correctable or + * uncorrectable error is detected by ECC decoding logic. + */ #define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) /*! @} */ /*! @name INT_ENABLE - Interrupt enable bits */ /*! @{ */ + #define FLASH_INT_ENABLE_FAIL_MASK (0x1U) #define FLASH_INT_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ #define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) + #define FLASH_INT_ENABLE_ERR_MASK (0x2U) #define FLASH_INT_ENABLE_ERR_SHIFT (1U) +/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ #define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) + #define FLASH_INT_ENABLE_DONE_MASK (0x4U) #define FLASH_INT_ENABLE_DONE_SHIFT (2U) +/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ #define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) + #define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) #define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ #define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) /*! @} */ /*! @name INT_CLR_STATUS - Clear interrupt status bits */ /*! @{ */ + #define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) #define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ #define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) + #define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) #define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) +/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ #define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) + #define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) #define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) +/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ #define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) + #define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) #define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ #define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) /*! @} */ /*! @name INT_SET_STATUS - Set interrupt status bits */ /*! @{ */ + #define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) #define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ #define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) + #define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) #define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) +/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ #define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) + #define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) #define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) +/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ #define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) + #define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) #define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ #define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) /*! @} */ /*! @name MODULE_ID - Controller+Memory module identification */ /*! @{ */ + #define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) #define FLASH_MODULE_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. + */ #define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) + #define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) #define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision i. + */ #define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) + #define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) #define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision i. + */ #define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) + #define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) #define FLASH_MODULE_ID_ID_SHIFT (16U) +/*! ID - Identifier. + */ #define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) /*! @} */ @@ -6692,7 +7741,7 @@ typedef struct { /* FLASH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral FLASH base address */ #define FLASH_BASE (0x50034000u) /** Peripheral FLASH base address */ @@ -6736,45 +7785,45 @@ typedef struct { /** FLASH_CFPA - Register Layout Typedef */ typedef struct { - __IO uint32_t HEADER; /**< ., offset: 0x0 */ - __IO uint32_t VERSION; /**< ., offset: 0x4 */ + __IO uint32_t HEADER; /**< , offset: 0x0 */ + __IO uint32_t VERSION; /**< , offset: 0x4 */ __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ uint8_t RESERVED_0[4]; - __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */ - __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */ + __IO uint32_t ROTKH_REVOKE; /**< , offset: 0x18 */ + __IO uint32_t VENDOR_USAGE; /**< , offset: 0x1C */ __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ union { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */ + __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< , array offset: 0x30, array step: 0x4 */ struct { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */ - __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< , offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< , offset: 0x34 */ + __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< , array offset: 0x38, array step: 0x4 */ } PRINCE_REGION0_IV_CODE_CORE; }; union { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */ + __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< , array offset: 0x68, array step: 0x4 */ struct { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */ - __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< , offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< , offset: 0x6C */ + __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< , array offset: 0x70, array step: 0x4 */ } PRINCE_REGION1_IV_CODE_CORE; }; union { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */ + __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< , array offset: 0xA0, array step: 0x4 */ struct { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */ - __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< , offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< , offset: 0xA4 */ + __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< , array offset: 0xA8, array step: 0x4 */ } PRINCE_REGION2_IV_CODE_CORE; }; uint8_t RESERVED_1[40]; __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ } FLASH_CFPA_Type; /* ---------------------------------------------------------------------------- @@ -6786,15 +7835,17 @@ typedef struct { * @{ */ -/*! @name HEADER - . */ +/*! @name HEADER - */ /*! @{ */ + #define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) #define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) /*! @} */ -/*! @name VERSION - . */ +/*! @name VERSION - */ /*! @{ */ + #define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) #define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) @@ -6802,6 +7853,7 @@ typedef struct { /*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ /*! @{ */ + #define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) #define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) @@ -6809,6 +7861,7 @@ typedef struct { /*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ /*! @{ */ + #define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) #define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) @@ -6816,36 +7869,59 @@ typedef struct { /*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ /*! @{ */ + #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) /*! @} */ -/*! @name ROTKH_REVOKE - . */ +/*! @name ROTKH_REVOKE - */ /*! @{ */ + #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) +/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) + #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) +/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) + #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) +/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) +/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) /*! @} */ -/*! @name VENDOR_USAGE - . */ +/*! @name VENDOR_USAGE - */ /*! @{ */ + #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) +/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. + */ #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) + #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) /*! @} */ /*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ /*! @{ */ + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) /*! NIDEN - Non Secure non-invasive debug enable @@ -6853,6 +7929,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) /*! DBGEN - Non Secure debug enable @@ -6860,6 +7937,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) /*! SPNIDEN - Secure non-invasive debug enable @@ -6867,6 +7945,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) /*! SPIDEN - Secure invasive debug enable @@ -6874,6 +7953,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) /*! TAPEN - JTAG TAP enable @@ -6881,13 +7961,15 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug enable + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) /*! ISP_CMD_EN - ISP Boot Command enable @@ -6895,6 +7977,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) /*! FA_CMD_EN - FA Command enable @@ -6902,6 +7985,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) /*! ME_CMD_EN - Flash Mass Erase Command enable @@ -6909,23 +7993,31 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. + */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) /*! @} */ /*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ /*! @{ */ + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) /*! NIDEN - Non Secure non-invasive debug fixed state @@ -6933,6 +8025,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) /*! DBGEN - Non Secure debug fixed state @@ -6940,6 +8033,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) /*! SPNIDEN - Secure non-invasive debug fixed state @@ -6947,6 +8041,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) /*! SPIDEN - Secure invasive debug fixed state @@ -6954,6 +8049,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) /*! TAPEN - JTAG TAP fixed state @@ -6961,13 +8057,15 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) /*! ISP_CMD_EN - ISP Boot Command fixed state @@ -6975,6 +8073,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) /*! FA_CMD_EN - FA Command fixed state @@ -6982,6 +8081,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) /*! ME_CMD_EN - Flash Mass Erase Command fixed state @@ -6989,20 +8089,25 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) /*! @} */ /*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ /*! @{ */ + #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) #define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) @@ -7010,13 +8115,15 @@ typedef struct { /*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ /*! @{ */ + #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) /*! @} */ -/*! @name PRINCE_REGION0_IV_CODE - . */ +/*! @name PRINCE_REGION0_IV_CODE - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) @@ -7025,28 +8132,33 @@ typedef struct { /* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) -/*! @name PRINCE_REGION0_IV_HEADER0 - . */ +/*! @name PRINCE_REGION0_IV_HEADER0 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) /*! @} */ -/*! @name PRINCE_REGION0_IV_HEADER1 - . */ +/*! @name PRINCE_REGION0_IV_HEADER1 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) + #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) + #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) /*! @} */ -/*! @name PRINCE_REGION0_IV_BODY - . */ +/*! @name PRINCE_REGION0_IV_BODY - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) @@ -7055,8 +8167,9 @@ typedef struct { /* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) -/*! @name PRINCE_REGION1_IV_CODE - . */ +/*! @name PRINCE_REGION1_IV_CODE - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) @@ -7065,28 +8178,33 @@ typedef struct { /* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) -/*! @name PRINCE_REGION1_IV_HEADER0 - . */ +/*! @name PRINCE_REGION1_IV_HEADER0 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) /*! @} */ -/*! @name PRINCE_REGION1_IV_HEADER1 - . */ +/*! @name PRINCE_REGION1_IV_HEADER1 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) + #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) + #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) /*! @} */ -/*! @name PRINCE_REGION1_IV_BODY - . */ +/*! @name PRINCE_REGION1_IV_BODY - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) @@ -7095,8 +8213,9 @@ typedef struct { /* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) -/*! @name PRINCE_REGION2_IV_CODE - . */ +/*! @name PRINCE_REGION2_IV_CODE - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) @@ -7105,28 +8224,33 @@ typedef struct { /* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) -/*! @name PRINCE_REGION2_IV_HEADER0 - . */ +/*! @name PRINCE_REGION2_IV_HEADER0 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) /*! @} */ -/*! @name PRINCE_REGION2_IV_HEADER1 - . */ +/*! @name PRINCE_REGION2_IV_HEADER1 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) + #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) + #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) /*! @} */ -/*! @name PRINCE_REGION2_IV_BODY - . */ +/*! @name PRINCE_REGION2_IV_BODY - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) @@ -7137,6 +8261,7 @@ typedef struct { /*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ /*! @{ */ + #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) @@ -7145,8 +8270,9 @@ typedef struct { /* The count of FLASH_CFPA_CUSTOMER_DEFINED */ #define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ /*! @{ */ + #define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) #define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) @@ -7162,7 +8288,7 @@ typedef struct { /* FLASH_CFPA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral FLASH_CFPA0 base address */ #define FLASH_CFPA0_BASE (0x1009E000u) /** Peripheral FLASH_CFPA0 base address */ @@ -7230,23 +8356,25 @@ typedef struct { /** FLASH_CMPA - Register Layout Typedef */ typedef struct { - __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */ - __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */ - __IO uint32_t USB_ID; /**< ., offset: 0x8 */ - __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */ - __IO uint32_t DCFG_CC_SOCU_PIN; /**< ., offset: 0x10 */ - __IO uint32_t DCFG_CC_SOCU_DFLT; /**< ., offset: 0x14 */ - __IO uint32_t DAP_VENDOR_USAGE_FIXED; /**< ., offset: 0x18 */ - __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */ - __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */ + __IO uint32_t BOOT_CFG; /**< , offset: 0x0 */ + __IO uint32_t SPI_FLASH_CFG; /**< , offset: 0x4 */ + __IO uint32_t USB_ID; /**< , offset: 0x8 */ + __IO uint32_t SDIO_CFG; /**< , offset: 0xC */ + __IO uint32_t CC_SOCU_PIN; /**< , offset: 0x10 */ + __IO uint32_t CC_SOCU_DFLT; /**< , offset: 0x14 */ + __IO uint32_t VENDOR_USAGE; /**< , offset: 0x18 */ + __IO uint32_t SECURE_BOOT_CFG; /**< Secure boot configuration flags., offset: 0x1C */ + __IO uint32_t PRINCE_BASE_ADDR; /**< , offset: 0x20 */ __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ - uint8_t RESERVED_0[32]; - __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ + __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ + __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ uint8_t RESERVED_1[144]; __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ } FLASH_CMPA_Type; /* ---------------------------------------------------------------------------- @@ -7258,280 +8386,430 @@ typedef struct { * @{ */ -/*! @name BOOT_CFG - . */ +/*! @name BOOT_CFG - */ /*! @{ */ + #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) /*! DEFAULT_ISP_MODE - Default ISP mode: * 0b000..Auto ISP - * 0b001..USB_HID_MSC - * 0b010..SPI Slave ISP - * 0b011..I2C Slave ISP + * 0b001..USB_HID_ISP + * 0b010..UART ISP + * 0b011..SPI Slave ISP + * 0b100..I2C Slave ISP * 0b111..Disable ISP fall through */ #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) + #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) /*! BOOT_SPEED - Core clock: * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE - * 0b01..48MHz FRO - * 0b10..96MHz FRO + * 0b01..96MHz FRO + * 0b10..48MHz FRO */ #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) + #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) +/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle + * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO + * pin + */ #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) /*! @} */ -/*! @name SPI_FLASH_CFG - . */ +/*! @name SPI_FLASH_CFG - */ /*! @{ */ -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT (0U) -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK) + +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) +/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. + */ +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) /*! @} */ -/*! @name USB_ID - . */ +/*! @name USB_ID - */ /*! @{ */ + #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) #define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) + #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) /*! @} */ -/*! @name SDIO_CFG - . */ +/*! @name SDIO_CFG - */ /*! @{ */ + #define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) #define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) /*! @} */ -/*! @name DCFG_CC_SOCU_PIN - . */ +/*! @name CC_SOCU_PIN - */ /*! @{ */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) + +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) /*! NIDEN - Non Secure non-invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) /*! DBGEN - Non Secure debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) /*! SPNIDEN - Secure non-invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) /*! SPIDEN - Secure invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) /*! TAPEN - JTAG TAP enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug enable +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) /*! ISP_CMD_EN - ISP Boot Command enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) /*! FA_CMD_EN - FA Command enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) /*! ME_CMD_EN - Flash Mass Erase Command enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. + */ +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) /*! @} */ -/*! @name DCFG_CC_SOCU_DFLT - . */ +/*! @name CC_SOCU_DFLT - */ /*! @{ */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) + +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) /*! NIDEN - Non Secure non-invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) /*! DBGEN - Non Secure debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) /*! SPNIDEN - Secure non-invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) /*! SPIDEN - Secure invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) /*! TAPEN - JTAG TAP fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) /*! ISP_CMD_EN - ISP Boot Command fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) /*! FA_CMD_EN - FA Command fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) /*! ME_CMD_EN - Flash Mass Erase Command fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) /*! @} */ -/*! @name DAP_VENDOR_USAGE_FIXED - . */ +/*! @name VENDOR_USAGE - */ /*! @{ */ -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT (16U) -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK) + +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) +/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. + */ +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) /*! @} */ -/*! @name SECURE_BOOT_CFG - . */ +/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */ /*! @{ */ + #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) +/*! RSA4K - Use RSA4096 keys only. + * 0b00..Allow RSA2048 and higher + * 0b01..RSA4096 only + * 0b10..RSA4096 only + * 0b11..RSA4096 only + */ #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U) +/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) +/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) +/*! SKIP_DICE - Skip DICE computation + * 0b00..Enable DICE + * 0b01..Disable DICE + * 0b10..Disable DICE + * 0b11..Disable DICE + */ #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) +/*! TZM_IMAGE_TYPE - TrustZone-M mode + * 0b00..TZ-M image mode is taken from application image header + * 0b01..TZ-M disabled image, boots to non-secure mode + * 0b10..TZ-M enabled image, boots to secure mode + * 0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header + */ #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) +/*! BLOCK_SET_KEY - Block PUF key code generation + * 0b00..Allow PUF Key Code generation + * 0b01..Disable PUF Key Code generation + * 0b10..Disable PUF Key Code generation + * 0b11..Disable PUF Key Code generation + */ #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) +/*! BLOCK_ENROLL - Block PUF enrollement + * 0b00..Allow PUF enroll operation + * 0b01..Disable PUF enroll operation + * 0b10..Disable PUF enroll operation + * 0b11..Disable PUF enroll operation + */ #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) +/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) +/*! SEC_BOOT_EN - Secure boot enable + * 0b00..Plain image (internal flash with or without CRC) + * 0b01..Boot signed images. (internal flash, RSA signed) + * 0b10..Boot signed images. (internal flash, RSA signed) + * 0b11..Boot signed images. (internal flash, RSA signed) + */ #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) /*! @} */ -/*! @name PRINCE_BASE_ADDR - . */ +/*! @name PRINCE_BASE_ADDR - */ /*! @{ */ + #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) +/*! ADDR0_PRG - Programmable portion of the base address of region 0 + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) + #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) +/*! ADDR1_PRG - Programmable portion of the base address of region 1 + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) + #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) +/*! ADDR2_PRG - Programmable portion of the base address of region 2 + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U) +/*! LOCK_REG0 - Lock PRINCE region0 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U) +/*! LOCK_REG1 - Lock PRINCE region1 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK) + #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) +/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) + #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) +/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) + #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) +/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) /*! @} */ /*! @name PRINCE_SR_0 - Region 0, sub-region enable */ /*! @{ */ + #define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) #define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) @@ -7539,6 +8817,7 @@ typedef struct { /*! @name PRINCE_SR_1 - Region 1, sub-region enable */ /*! @{ */ + #define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) #define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) @@ -7546,13 +8825,75 @@ typedef struct { /*! @name PRINCE_SR_2 - Region 2, sub-region enable */ /*! @{ */ + #define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) #define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) /*! @} */ -/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */ +/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ /*! @{ */ + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 32kHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ +/*! @{ */ + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 16MHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */ +/*! @{ */ + #define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) #define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) @@ -7563,6 +8904,7 @@ typedef struct { /*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ /*! @{ */ + #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) @@ -7571,8 +8913,9 @@ typedef struct { /* The count of FLASH_CMPA_CUSTOMER_DEFINED */ #define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ /*! @{ */ + #define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) #define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) @@ -7588,7 +8931,7 @@ typedef struct { /* FLASH_CMPA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral FLASH_CMPA base address */ #define FLASH_CMPA_BASE (0x1009E400u) /** Peripheral FLASH_CMPA base address */ @@ -7698,22 +9041,31 @@ typedef struct { /*! @name HEADER - Valid Key Sore Header : 0x95959595 */ /*! @{ */ + #define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) /*! @} */ /*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ /*! @{ */ + #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) /*! @} */ /*! @name ACTIVATION_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) /*! @} */ @@ -7722,8 +9074,11 @@ typedef struct { /*! @name SBKEY_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7732,28 +9087,43 @@ typedef struct { /*! @name SBKEY_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) /*! @} */ /*! @name SBKEY_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) /*! @} */ /*! @name SBKEY_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) /*! @} */ @@ -7762,8 +9132,11 @@ typedef struct { /*! @name USER_KEK_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7772,28 +9145,43 @@ typedef struct { /*! @name USER_KEK_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) /*! @} */ /*! @name USER_KEK_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) /*! @} */ /*! @name USER_KEK_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) /*! @} */ @@ -7802,8 +9190,11 @@ typedef struct { /*! @name UDS_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7812,28 +9203,43 @@ typedef struct { /*! @name UDS_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) /*! @} */ /*! @name UDS_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) /*! @} */ /*! @name UDS_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) /*! @} */ @@ -7842,8 +9248,11 @@ typedef struct { /*! @name PRINCE_REGION0_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7852,28 +9261,43 @@ typedef struct { /*! @name PRINCE_REGION0_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) /*! @} */ /*! @name PRINCE_REGION0_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) /*! @} */ /*! @name PRINCE_REGION0_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) /*! @} */ @@ -7882,8 +9306,11 @@ typedef struct { /*! @name PRINCE_REGION1_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7892,28 +9319,43 @@ typedef struct { /*! @name PRINCE_REGION1_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) /*! @} */ /*! @name PRINCE_REGION1_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) /*! @} */ /*! @name PRINCE_REGION1_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) /*! @} */ @@ -7922,8 +9364,11 @@ typedef struct { /*! @name PRINCE_REGION2_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7932,28 +9377,43 @@ typedef struct { /*! @name PRINCE_REGION2_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) /*! @} */ /*! @name PRINCE_REGION2_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) /*! @} */ /*! @name PRINCE_REGION2_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) /*! @} */ @@ -7967,7 +9427,7 @@ typedef struct { /* FLASH_KEY_STORE - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral FLASH_KEY_STORE base address */ #define FLASH_KEY_STORE_BASE (0x1009E600u) /** Peripheral FLASH_KEY_STORE base address */ @@ -8027,6 +9487,7 @@ typedef struct { /*! @name PSELID - Peripheral Select and Flexcomm ID register. */ /*! @{ */ + #define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) #define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) /*! PERSEL - Peripheral Select. This field is writable by software. @@ -8040,6 +9501,7 @@ typedef struct { * 0b111..Reserved */ #define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) + #define FLEXCOMM_PSELID_LOCK_MASK (0x8U) #define FLEXCOMM_PSELID_LOCK_SHIFT (3U) /*! LOCK - Lock the peripheral select. This field is writable by software. @@ -8047,6 +9509,7 @@ typedef struct { * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. */ #define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) + #define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) #define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) /*! USARTPRESENT - USART present indicator. This field is Read-only. @@ -8054,6 +9517,7 @@ typedef struct { * 0b1..This Flexcomm includes the USART function. */ #define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) + #define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) #define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) /*! SPIPRESENT - SPI present indicator. This field is Read-only. @@ -8061,6 +9525,7 @@ typedef struct { * 0b1..This Flexcomm includes the SPI function. */ #define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) + #define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) #define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) /*! I2CPRESENT - I2C present indicator. This field is Read-only. @@ -8068,6 +9533,7 @@ typedef struct { * 0b1..This Flexcomm includes the I2C function. */ #define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) + #define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) #define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) /*! I2SPRESENT - I 2S present indicator. This field is Read-only. @@ -8075,24 +9541,39 @@ typedef struct { * 0b1..This Flexcomm includes the I2S function. */ #define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) + #define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) #define FLEXCOMM_PSELID_ID_SHIFT (12U) +/*! ID - Flexcomm ID. + */ #define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) /*! @} */ /*! @name PID - Peripheral identification register. */ /*! @{ */ -#define FLEXCOMM_PID_Aperture_MASK (0xFFU) -#define FLEXCOMM_PID_Aperture_SHIFT (0U) -#define FLEXCOMM_PID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Aperture_SHIFT)) & FLEXCOMM_PID_Aperture_MASK) -#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) -#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) -#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) -#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) -#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) -#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) + +#define FLEXCOMM_PID_APERTURE_MASK (0xFFU) +#define FLEXCOMM_PID_APERTURE_SHIFT (0U) +/*! APERTURE - size aperture for the register port on the bus (APB or AHB). + */ +#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) + +#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) +#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) + +#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) +#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) + #define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) #define FLEXCOMM_PID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ #define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) /*! @} */ @@ -8103,7 +9584,7 @@ typedef struct { /* FLEXCOMM - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral FLEXCOMM0 base address */ #define FLEXCOMM0_BASE (0x50086000u) /** Peripheral FLEXCOMM0 base address */ @@ -8263,6 +9744,7 @@ typedef struct { /*! @name CTRL - GPIO grouped interrupt control register */ /*! @{ */ + #define GINT_CTRL_INT_MASK (0x1U) #define GINT_CTRL_INT_SHIFT (0U) /*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. @@ -8270,6 +9752,7 @@ typedef struct { * 0b1..Request active. Interrupt request is active. */ #define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) + #define GINT_CTRL_COMB_MASK (0x2U) #define GINT_CTRL_COMB_SHIFT (1U) /*! COMB - Combine enabled inputs for group interrupt @@ -8277,6 +9760,7 @@ typedef struct { * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). */ #define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) + #define GINT_CTRL_TRIG_MASK (0x4U) #define GINT_CTRL_TRIG_SHIFT (2U) /*! TRIG - Group interrupt trigger @@ -8288,8 +9772,14 @@ typedef struct { /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ /*! @{ */ + #define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) #define GINT_PORT_POL_POL_SHIFT (0U) +/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n + * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to + * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin + * contributes to the group interrupt. + */ #define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) /*! @} */ @@ -8298,8 +9788,13 @@ typedef struct { /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ /*! @{ */ + #define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) #define GINT_PORT_ENA_ENA_SHIFT (0U) +/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the + * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is + * enabled and contributes to the grouped interrupt. + */ #define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) /*! @} */ @@ -8313,7 +9808,7 @@ typedef struct { /* GINT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral GINT0 base address */ #define GINT0_BASE (0x50002000u) /** Peripheral GINT0 base address */ @@ -8371,29 +9866,29 @@ typedef struct { /** GPIO - Register Layout Typedef */ typedef struct { - __IO uint8_t B[4][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[3968]; - __IO uint32_t W[4][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3584]; - __IO uint32_t DIR[4]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[112]; - __IO uint32_t MASK[4]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[112]; - __IO uint32_t PIN[4]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[112]; - __IO uint32_t MPIN[4]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[112]; - __IO uint32_t SET[4]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[112]; - __O uint32_t CLR[4]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[112]; - __O uint32_t NOT[4]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[112]; - __O uint32_t DIRSET[4]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[112]; - __O uint32_t DIRCLR[4]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[112]; - __O uint32_t DIRNOT[4]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ + __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[4032]; + __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3840]; + __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[120]; + __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[120]; + __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[120]; + __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[120]; + __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[120]; + __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[120]; + __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[120]; + __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ } GPIO_Type; /* ---------------------------------------------------------------------------- @@ -8407,129 +9902,188 @@ typedef struct { /*! @name B - Byte pin registers for all port GPIO pins */ /*! @{ */ + #define GPIO_B_PBYTE_MASK (0x1U) #define GPIO_B_PBYTE_SHIFT (0U) +/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, + * except that pins configured as analog I/O always read as 0. One register for each port pin. + * Supported pins depends on the specific device and package. Write: loads the pin's output bit. + * One register for each port pin. Supported pins depends on the specific device and package. + */ #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) /*! @} */ /* The count of GPIO_B */ -#define GPIO_B_COUNT (4U) +#define GPIO_B_COUNT (2U) /* The count of GPIO_B */ #define GPIO_B_COUNT2 (32U) /*! @name W - Word pin registers for all port GPIO pins */ /*! @{ */ + #define GPIO_W_PWORD_MASK (0xFFFFFFFFU) #define GPIO_W_PWORD_SHIFT (0U) +/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is + * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be + * read. Writing any value other than 0 will set the output bit. One register for each port pin. + * Supported pins depends on the specific device and package. + */ #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) /*! @} */ /* The count of GPIO_W */ -#define GPIO_W_COUNT (4U) +#define GPIO_W_COUNT (2U) /* The count of GPIO_W */ #define GPIO_W_COUNT2 (32U) /*! @name DIR - Direction registers for all port GPIO pins */ /*! @{ */ + #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) #define GPIO_DIR_DIRP_SHIFT (0U) +/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = input. 1 = output. + */ #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) /*! @} */ /* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (4U) +#define GPIO_DIR_COUNT (2U) /*! @name MASK - Mask register for all port GPIO pins */ /*! @{ */ + #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) #define GPIO_MASK_MASKP_SHIFT (0U) +/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = + * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = + * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit + * not affected. + */ #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) /*! @} */ /* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (4U) +#define GPIO_MASK_COUNT (2U) /*! @name PIN - Port pin register for all port GPIO pins */ /*! @{ */ + #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) #define GPIO_PIN_PORT_SHIFT (0U) +/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. + * 1 = Read: pin is high; write: set output bit. + */ #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) /*! @} */ /* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (4U) +#define GPIO_PIN_COUNT (2U) /*! @name MPIN - Masked port register for all port GPIO pins */ /*! @{ */ + #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) #define GPIO_MPIN_MPORTP_SHIFT (0U) +/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK + * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 + * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit + * if the corresponding bit in the MASK register is 0. + */ #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) /*! @} */ /* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (4U) +#define GPIO_MPIN_COUNT (2U) /*! @name SET - Write: Set register for port. Read: output bits for port */ /*! @{ */ + #define GPIO_SET_SETP_MASK (0xFFFFFFFFU) #define GPIO_SET_SETP_SHIFT (0U) +/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output + * bit; write: set output bit. + */ #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) /*! @} */ /* The count of GPIO_SET */ -#define GPIO_SET_COUNT (4U) +#define GPIO_SET_COUNT (2U) /*! @name CLR - Clear port for all port GPIO pins */ /*! @{ */ + #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) #define GPIO_CLR_CLRP_SHIFT (0U) +/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = No operation. 1 = Clear output bit. + */ #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) /*! @} */ /* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (4U) +#define GPIO_CLR_COUNT (2U) /*! @name NOT - Toggle port for all port GPIO pins */ /*! @{ */ + #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) #define GPIO_NOT_NOTP_SHIFT (0U) +/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = no operation. 1 = Toggle output bit. + */ #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) /*! @} */ /* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (4U) +#define GPIO_NOT_COUNT (2U) /*! @name DIRSET - Set pin direction bits for port */ /*! @{ */ -#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) + +#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) #define GPIO_DIRSET_DIRSETP_SHIFT (0U) +/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Set direction bit. + */ #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) /*! @} */ /* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (4U) +#define GPIO_DIRSET_COUNT (2U) /*! @name DIRCLR - Clear pin direction bits for port */ /*! @{ */ -#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) + +#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Clear direction bit. + */ #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) /*! @} */ /* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (4U) +#define GPIO_DIRCLR_COUNT (2U) /*! @name DIRNOT - Toggle pin direction bits for port */ /*! @{ */ -#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) + +#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends + * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + */ #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) /*! @} */ /* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (4U) +#define GPIO_DIRNOT_COUNT (2U) /*! @@ -8538,7 +10092,7 @@ typedef struct { /* GPIO - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral GPIO base address */ #define GPIO_BASE (0x5008C000u) /** Peripheral GPIO base address */ @@ -8594,7 +10148,7 @@ typedef struct { /** HASHCRYPT - Register Layout Typedef */ typedef struct { - __IO uint32_t CTRL; /**< Is control register to enable and operate Hash and Crypto, offset: 0x0 */ + __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ @@ -8603,11 +10157,11 @@ typedef struct { uint8_t RESERVED_0[8]; __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ - __I uint32_t OUTDATA0[8]; /**< , array offset: 0x40, array step: 0x4 */ - __I uint32_t OUTDATA1[8]; /**< , array offset: 0x60, array step: 0x4 */ + __I uint32_t DIGEST0[8]; /**< , array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ - uint8_t RESERVED_1[4]; + uint8_t RESERVED_2[4]; __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ } HASHCRYPT_Type; @@ -8621,8 +10175,9 @@ typedef struct { * @{ */ -/*! @name CTRL - Is control register to enable and operate Hash and Crypto */ +/*! @name CTRL - Control register to enable and operate Hash and Crypto */ /*! @{ */ + #define HASHCRYPT_CTRL_MODE_MASK (0x7U) #define HASHCRYPT_CTRL_MODE_SHIFT (0U) /*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if @@ -8630,13 +10185,11 @@ typedef struct { * 0b000..Disabled * 0b001..SHA1 is enabled * 0b010..SHA2-256 is enabled - * 0b011..SHA2-512 is enabled (if available) * 0b100..AES if available (see also CRYPTCFG register for more controls) * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) - * 0b110..Salsa20/20 if available (including XSalsa - see also CRYPTCFG register) - * 0b111..ChaCha20 if available (see also CRYPTCFG register for more controls) */ #define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) + #define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) #define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) /*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING @@ -8644,6 +10197,7 @@ typedef struct { * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. */ #define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) + #define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) #define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) /*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words @@ -8656,6 +10210,7 @@ typedef struct { * 0b1..DMA will push in the data. */ #define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) + #define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) #define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) /*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the @@ -8663,13 +10218,19 @@ typedef struct { * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. */ #define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) + #define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) #define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) +/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB + * is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For + * cryptographic swapping, see the CRYPTCFG register. + */ #define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) /*! @} */ /*! @name STATUS - Indicates status of Hash peripheral. */ /*! @{ */ + #define HASHCRYPT_STATUS_WAITING_MASK (0x1U) #define HASHCRYPT_STATUS_WAITING_SHIFT (0U) /*! WAITING - If 1, the block is waiting for more data to process. @@ -8678,17 +10239,19 @@ typedef struct { * 0b1..Waiting for data to be written in (16 words) */ #define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK (0x2U) -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT (1U) -/*! DIGEST_aka_OUTDATA - For Hash, if 1 then a DIGEST is ready and waiting and there is no active - * next block already started. For Cryptographic uses, this will be set for each block processed, - * indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is - * cleared when any data is written, when New is written, for Cryptographic uses when the last - * word is read out, or when the block is disabled. + +#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) +#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) +/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block + * already started. For Cryptographic uses, this will be set for each block processed, indicating + * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared + * when any data is written, when New is written, for Cryptographic uses when the last word is read + * out, or when the block is disabled. * 0b0..No Digest is ready * 0b1..Digest is ready. Application may read it or may write more data */ -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT)) & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK) +#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) + #define HASHCRYPT_STATUS_ERROR_MASK (0x4U) #define HASHCRYPT_STATUS_ERROR_SHIFT (2U) /*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA @@ -8698,6 +10261,7 @@ typedef struct { * 0b1..An error occurred since last cleared (written 1 to clear). */ #define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) + #define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) #define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) /*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) @@ -8705,6 +10269,7 @@ typedef struct { * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. */ #define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) + #define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) #define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) /*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) @@ -8712,13 +10277,19 @@ typedef struct { * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. */ #define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) + #define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) #define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) +/*! ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from + * CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, + * it has to compute the full ICB, quicker when not 0. + */ #define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) /*! @} */ /*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ /*! @{ */ + #define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) #define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) /*! WAITING - Indicates if should interrupt when waiting for data input. @@ -8726,6 +10297,7 @@ typedef struct { * 0b1..Will interrupt when waiting */ #define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) + #define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) #define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) /*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). @@ -8733,6 +10305,7 @@ typedef struct { * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). */ #define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) + #define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) #define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) /*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) @@ -8744,89 +10317,133 @@ typedef struct { /*! @name INTENCLR - Write 1 to clear interrupts. */ /*! @{ */ + #define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) #define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) +/*! WAITING - Write 1 to clear mask. + */ #define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) + #define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) #define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) +/*! DIGEST - Write 1 to clear mask. + */ #define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) + #define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) #define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) +/*! ERROR - Write 1 to clear mask. + */ #define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) /*! @} */ /*! @name MEMCTRL - Setup Master to access memory (if available) */ /*! @{ */ + #define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) #define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) -/*! MASTER +/*! MASTER - Enables mastering. * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. * 0b1..Mastering is enabled and DMA and INDATA should not be used. */ #define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) + #define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) #define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) +/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks + * to copy starting at MEMADDR. This register will decrement after each block is copied, ending + * in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA + * interrupt will occur on ever block. If a bus error occurs, it will stop with this field set + * to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) + * blocks to hash. + */ #define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) /*! @} */ /*! @name MEMADDR - Address to start memory access from (if available). */ /*! @{ */ + #define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) #define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) +/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will + * advance as it processes the words. If it fails with a bus error, the register will contain + * the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be + * able to address SPIFI. + */ #define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) /*! @} */ /*! @name INDATA - Input of 16 words at a time to load up buffer. */ /*! @{ */ + #define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) #define HASHCRYPT_INDATA_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ #define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) /*! @} */ /*! @name ALIAS - */ /*! @{ */ + #define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) #define HASHCRYPT_ALIAS_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ #define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) /*! @} */ /* The count of HASHCRYPT_ALIAS */ #define HASHCRYPT_ALIAS_COUNT (7U) -/*! @name OUTDATA0 - */ +/*! @name DIGEST0 - */ /*! @{ */ -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK (0xFFFFFFFFU) -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT (0U) -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK) + +#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) +#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) +/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. + */ +#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) /*! @} */ -/* The count of HASHCRYPT_OUTDATA0 */ -#define HASHCRYPT_OUTDATA0_COUNT (8U) - -/*! @name OUTDATA1 - */ -/*! @{ */ -#define HASHCRYPT_OUTDATA1_OUTPUT_MASK (0xFFFFFFFFU) -#define HASHCRYPT_OUTDATA1_OUTPUT_SHIFT (0U) -#define HASHCRYPT_OUTDATA1_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA1_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA1_OUTPUT_MASK) -/*! @} */ - -/* The count of HASHCRYPT_OUTDATA1 */ -#define HASHCRYPT_OUTDATA1_COUNT (8U) +/* The count of HASHCRYPT_DIGEST0 */ +#define HASHCRYPT_DIGEST0_COUNT (8U) /*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ /*! @{ */ + #define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) #define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) +/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read + * in normal little endian - Least significant word 1st. Note: only if allowed by configuration. + */ #define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) + #define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) #define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) +/*! SWAPKEY - If 1, will Swap the key input (bytes in each word). + */ #define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) + #define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) #define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) +/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). + */ #define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) + #define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) #define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) +/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. + * Note: only if allowed by configuration. + */ #define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) + #define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) #define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) /*! AESMODE - AES Cipher mode to use if plain AES @@ -8836,6 +10453,7 @@ typedef struct { * 0b11..reserved */ #define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) + #define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) #define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) /*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB @@ -8843,6 +10461,7 @@ typedef struct { * 0b1..Decrypt */ #define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) + #define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) #define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) /*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are @@ -8851,6 +10470,7 @@ typedef struct { * 0b1..Secret key provided in hidden way by HW */ #define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) + #define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) #define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) /*! AESKEYSZ - Sets the AES key size @@ -8860,15 +10480,22 @@ typedef struct { * 0b11..reserved */ #define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) + #define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) #define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) +/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for + * Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if + * using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other + * use CTR should use ECB directly and do its own XOR and so on. + */ #define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) + #define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) #define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) +/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". + */ #define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) -#define HASHCRYPT_CRYPTCFG_XSALSA_MASK (0x20000U) -#define HASHCRYPT_CRYPTCFG_XSALSA_SHIFT (17U) -#define HASHCRYPT_CRYPTCFG_XSALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_XSALSA_SHIFT)) & HASHCRYPT_CRYPTCFG_XSALSA_MASK) + #define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) #define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) /*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the @@ -8879,6 +10506,7 @@ typedef struct { * 0b11..All 128 bits of the IV/ctr are used */ #define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) + #define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) #define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) /*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new @@ -8893,40 +10521,53 @@ typedef struct { /*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ /*! @{ */ + #define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) #define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) +/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit + */ #define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) + #define HASHCRYPT_CONFIG_DMA_MASK (0x2U) #define HASHCRYPT_CONFIG_DMA_SHIFT (1U) +/*! DMA - 1 if DMA is connected + */ #define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) + #define HASHCRYPT_CONFIG_AHB_MASK (0x8U) #define HASHCRYPT_CONFIG_AHB_SHIFT (3U) +/*! AHB - 1 if AHB Master is enabled + */ #define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) -#define HASHCRYPT_CONFIG_SHA512_MASK (0x20U) -#define HASHCRYPT_CONFIG_SHA512_SHIFT (5U) -#define HASHCRYPT_CONFIG_SHA512(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SHA512_SHIFT)) & HASHCRYPT_CONFIG_SHA512_MASK) + #define HASHCRYPT_CONFIG_AES_MASK (0x40U) #define HASHCRYPT_CONFIG_AES_SHIFT (6U) +/*! AES - 1 if AES 128 included + */ #define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) + #define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) #define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) +/*! AESKEY - 1 if AES 192 and 256 also included + */ #define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) + #define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) #define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) +/*! SECRET - 1 if AES Secret key available + */ #define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) -#define HASHCRYPT_CONFIG_SALSA_MASK (0x200U) -#define HASHCRYPT_CONFIG_SALSA_SHIFT (9U) -#define HASHCRYPT_CONFIG_SALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SALSA_SHIFT)) & HASHCRYPT_CONFIG_SALSA_MASK) -#define HASHCRYPT_CONFIG_CHACHA_MASK (0x400U) -#define HASHCRYPT_CONFIG_CHACHA_SHIFT (10U) -#define HASHCRYPT_CONFIG_CHACHA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_CHACHA_SHIFT)) & HASHCRYPT_CONFIG_CHACHA_MASK) + #define HASHCRYPT_CONFIG_ICB_MASK (0x800U) #define HASHCRYPT_CONFIG_ICB_SHIFT (11U) +/*! ICB - 1 if ICB over AES included + */ #define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) /*! @} */ /*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ /*! @{ */ + #define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) #define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) /*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. @@ -8937,15 +10578,21 @@ typedef struct { * 0b01..Locks to the current security level. AHB Master will issue requests at this level. */ #define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) + #define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) #define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 + */ #define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) /*! @} */ /*! @name MASK - */ /*! @{ */ + #define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) #define HASHCRYPT_MASK_MASK_SHIFT (0U) +/*! MASK - A random word. + */ #define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) /*! @} */ @@ -8959,7 +10606,7 @@ typedef struct { /* HASHCRYPT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral HASHCRYPT base address */ #define HASHCRYPT_BASE (0x500A4000u) /** Peripheral HASHCRYPT base address */ @@ -9037,6 +10684,7 @@ typedef struct { /*! @name CFG - Configuration for shared functions. */ /*! @{ */ + #define I2C_CFG_MSTEN_MASK (0x1U) #define I2C_CFG_MSTEN_SHIFT (0U) /*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not @@ -9045,6 +10693,7 @@ typedef struct { * 0b1..Enabled. The I2C Master function is enabled. */ #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) + #define I2C_CFG_SLVEN_MASK (0x2U) #define I2C_CFG_SLVEN_SHIFT (1U) /*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not @@ -9053,6 +10702,7 @@ typedef struct { * 0b1..Enabled. The I2C slave function is enabled. */ #define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) + #define I2C_CFG_MONEN_MASK (0x4U) #define I2C_CFG_MONEN_SHIFT (2U) /*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not @@ -9061,6 +10711,7 @@ typedef struct { * 0b1..Enabled. The I2C Monitor function is enabled. */ #define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) + #define I2C_CFG_TIMEOUTEN_MASK (0x8U) #define I2C_CFG_TIMEOUTEN_SHIFT (3U) /*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. @@ -9069,6 +10720,7 @@ typedef struct { * interrupts if they are enabled. Typically, only one time-out will be used in a system. */ #define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) + #define I2C_CFG_MONCLKSTR_MASK (0x10U) #define I2C_CFG_MONCLKSTR_SHIFT (4U) /*! MONCLKSTR - Monitor function Clock Stretching. @@ -9079,6 +10731,7 @@ typedef struct { * read all incoming data supplied by the Monitor function. */ #define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) + #define I2C_CFG_HSCAPABLE_MASK (0x20U) #define I2C_CFG_HSCAPABLE_SHIFT (5U) /*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive @@ -9097,6 +10750,7 @@ typedef struct { /*! @name STAT - Status register for Master, Slave, and Monitor functions. */ /*! @{ */ + #define I2C_STAT_MSTPENDING_MASK (0x1U) #define I2C_STAT_MSTPENDING_SHIFT (0U) /*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on @@ -9110,6 +10764,7 @@ typedef struct { * idle state, it is waiting to receive or transmit data or the NACK bit. */ #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) + #define I2C_STAT_MSTSTATE_MASK (0xEU) #define I2C_STAT_MSTSTATE_SHIFT (1U) /*! MSTSTATE - Master State code. The master state code reflects the master state when the @@ -9123,6 +10778,7 @@ typedef struct { * 0b100..NACK Data. Slave NACKed transmitted data. */ #define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) + #define I2C_STAT_MSTARBLOSS_MASK (0x10U) #define I2C_STAT_MSTARBLOSS_SHIFT (4U) /*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to @@ -9133,6 +10789,7 @@ typedef struct { * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. */ #define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) + #define I2C_STAT_MSTSTSTPERR_MASK (0x40U) #define I2C_STAT_MSTSTSTPERR_SHIFT (6U) /*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to @@ -9144,6 +10801,7 @@ typedef struct { * that the bus has not stalled. */ #define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) + #define I2C_STAT_SLVPENDING_MASK (0x100U) #define I2C_STAT_SLVPENDING_SHIFT (8U) /*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue @@ -9160,6 +10818,7 @@ typedef struct { * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. */ #define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) + #define I2C_STAT_SLVSTATE_MASK (0x600U) #define I2C_STAT_SLVSTATE_SHIFT (9U) /*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for @@ -9171,6 +10830,7 @@ typedef struct { * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). */ #define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) + #define I2C_STAT_SLVNOTSTR_MASK (0x800U) #define I2C_STAT_SLVNOTSTR_SHIFT (11U) /*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. @@ -9181,6 +10841,7 @@ typedef struct { * Power-down mode could be entered at this time. */ #define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) + #define I2C_STAT_SLVIDX_MASK (0x3000U) #define I2C_STAT_SLVIDX_SHIFT (12U) /*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been @@ -9193,6 +10854,7 @@ typedef struct { * 0b11..Address 3. Slave address 3 was matched. */ #define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) + #define I2C_STAT_SLVSEL_MASK (0x4000U) #define I2C_STAT_SLVSEL_SHIFT (14U) /*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave @@ -9205,6 +10867,7 @@ typedef struct { * 0b1..Selected. The Slave function is currently selected. */ #define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) + #define I2C_STAT_SLVDESEL_MASK (0x8000U) #define I2C_STAT_SLVDESEL_SHIFT (15U) /*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via @@ -9215,6 +10878,7 @@ typedef struct { * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. */ #define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) + #define I2C_STAT_MONRDY_MASK (0x10000U) #define I2C_STAT_MONRDY_SHIFT (16U) /*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. @@ -9222,6 +10886,7 @@ typedef struct { * 0b1..Data waiting. The Monitor function has data waiting to be read. */ #define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) + #define I2C_STAT_MONOV_MASK (0x20000U) #define I2C_STAT_MONOV_SHIFT (17U) /*! MONOV - Monitor Overflow flag. @@ -9230,6 +10895,7 @@ typedef struct { * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. */ #define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) + #define I2C_STAT_MONACTIVE_MASK (0x40000U) #define I2C_STAT_MONACTIVE_SHIFT (18U) /*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to @@ -9239,6 +10905,7 @@ typedef struct { * 0b1..Active. The Monitor function considers the I2C bus to be active. */ #define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) + #define I2C_STAT_MONIDLE_MASK (0x80000U) #define I2C_STAT_MONIDLE_SHIFT (19U) /*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change @@ -9249,6 +10916,7 @@ typedef struct { * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. */ #define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) + #define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) #define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) /*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been @@ -9259,6 +10927,7 @@ typedef struct { * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. */ #define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) + #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) #define I2C_STAT_SCLTIMEOUT_SHIFT (25U) /*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the @@ -9271,6 +10940,7 @@ typedef struct { /*! @name INTENSET - Interrupt Enable Set and read register. */ /*! @{ */ + #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) /*! MSTPENDINGEN - Master Pending interrupt Enable. @@ -9278,6 +10948,7 @@ typedef struct { * 0b1..Enabled. The MstPending interrupt is enabled. */ #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) + #define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) #define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) /*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. @@ -9285,6 +10956,7 @@ typedef struct { * 0b1..Enabled. The MstArbLoss interrupt is enabled. */ #define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) + #define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) #define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) /*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. @@ -9292,6 +10964,7 @@ typedef struct { * 0b1..Enabled. The MstStStpErr interrupt is enabled. */ #define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) + #define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) #define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) /*! SLVPENDINGEN - Slave Pending interrupt Enable. @@ -9299,6 +10972,7 @@ typedef struct { * 0b1..Enabled. The SlvPending interrupt is enabled. */ #define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) + #define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) #define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) /*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. @@ -9306,6 +10980,7 @@ typedef struct { * 0b1..Enabled. The SlvNotStr interrupt is enabled. */ #define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) + #define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) #define I2C_INTENSET_SLVDESELEN_SHIFT (15U) /*! SLVDESELEN - Slave Deselect interrupt Enable. @@ -9313,6 +10988,7 @@ typedef struct { * 0b1..Enabled. The SlvDeSel interrupt is enabled. */ #define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) + #define I2C_INTENSET_MONRDYEN_MASK (0x10000U) #define I2C_INTENSET_MONRDYEN_SHIFT (16U) /*! MONRDYEN - Monitor data Ready interrupt Enable. @@ -9320,6 +10996,7 @@ typedef struct { * 0b1..Enabled. The MonRdy interrupt is enabled. */ #define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) + #define I2C_INTENSET_MONOVEN_MASK (0x20000U) #define I2C_INTENSET_MONOVEN_SHIFT (17U) /*! MONOVEN - Monitor Overrun interrupt Enable. @@ -9327,6 +11004,7 @@ typedef struct { * 0b1..Enabled. The MonOv interrupt is enabled. */ #define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) + #define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) #define I2C_INTENSET_MONIDLEEN_SHIFT (19U) /*! MONIDLEEN - Monitor Idle interrupt Enable. @@ -9334,6 +11012,7 @@ typedef struct { * 0b1..Enabled. The MonIdle interrupt is enabled. */ #define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) + #define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) /*! EVENTTIMEOUTEN - Event time-out interrupt Enable. @@ -9341,6 +11020,7 @@ typedef struct { * 0b1..Enabled. The Event time-out interrupt is enabled. */ #define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) + #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) /*! SCLTIMEOUTEN - SCL time-out interrupt Enable. @@ -9352,97 +11032,183 @@ typedef struct { /*! @name INTENCLR - Interrupt Enable Clear register. */ /*! @{ */ + #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding + * bit in the INTENSET register if implemented. + */ #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) + #define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. + */ #define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) + #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. + */ #define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) + #define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +/*! SLVPENDINGCLR - Slave Pending interrupt clear. + */ #define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) + #define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. + */ #define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) + #define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) #define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +/*! SLVDESELCLR - Slave Deselect interrupt clear. + */ #define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) + #define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) #define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +/*! MONRDYCLR - Monitor data Ready interrupt clear. + */ #define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) + #define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) #define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +/*! MONOVCLR - Monitor Overrun interrupt clear. + */ #define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) + #define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) #define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +/*! MONIDLECLR - Monitor Idle interrupt clear. + */ #define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) + #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +/*! EVENTTIMEOUTCLR - Event time-out interrupt clear. + */ #define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) + #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +/*! SCLTIMEOUTCLR - SCL time-out interrupt clear. + */ #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) /*! @} */ /*! @name TIMEOUT - Time-out value register. */ /*! @{ */ + #define I2C_TIMEOUT_TOMIN_MASK (0xFU) #define I2C_TIMEOUT_TOMIN_SHIFT (0U) +/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum + * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. + */ #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) + #define I2C_TIMEOUT_TO_MASK (0xFFF0U) #define I2C_TIMEOUT_TO_SHIFT (4U) +/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C + * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, + * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A + * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after + * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the + * I2C function clock. + */ #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) /*! @} */ /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ /*! @{ */ + #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) #define I2C_CLKDIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that + * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = + * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is + * divided by 65,536 before use. + */ #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) /*! @} */ /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ /*! @{ */ + #define I2C_INTSTAT_MSTPENDING_MASK (0x1U) #define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. + */ #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) + #define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) #define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. + */ #define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) + #define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) #define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. + */ #define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) + #define I2C_INTSTAT_SLVPENDING_MASK (0x100U) #define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. + */ #define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) + #define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) #define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching status. + */ #define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) + #define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) #define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. + */ #define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) + #define I2C_INTSTAT_MONRDY_MASK (0x10000U) #define I2C_INTSTAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. + */ #define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) + #define I2C_INTSTAT_MONOV_MASK (0x20000U) #define I2C_INTSTAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + */ #define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) + #define I2C_INTSTAT_MONIDLE_MASK (0x80000U) #define I2C_INTSTAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. + */ #define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) + #define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event time-out Interrupt flag. + */ #define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) + #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL time-out Interrupt flag. + */ #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) /*! @} */ /*! @name MSTCTL - Master control register. */ /*! @{ */ + #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) /*! MSTCONTINUE - Master Continue. This bit is write-only. @@ -9451,6 +11217,7 @@ typedef struct { * transmit data, reading received data, or any other housekeeping related to the next bus operation. */ #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) + #define I2C_MSTCTL_MSTSTART_MASK (0x2U) #define I2C_MSTCTL_MSTSTART_SHIFT (1U) /*! MSTSTART - Master Start control. This bit is write-only. @@ -9458,6 +11225,7 @@ typedef struct { * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. */ #define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) + #define I2C_MSTCTL_MSTSTOP_MASK (0x4U) #define I2C_MSTCTL_MSTSTOP_SHIFT (2U) /*! MSTSTOP - Master Stop control. This bit is write-only. @@ -9466,6 +11234,7 @@ typedef struct { * if the master is receiving data from the slave (Master Receiver mode). */ #define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) + #define I2C_MSTCTL_MSTDMA_MASK (0x8U) #define I2C_MSTCTL_MSTDMA_SHIFT (3U) /*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type @@ -9484,6 +11253,7 @@ typedef struct { /*! @name MSTTIME - Master timing configuration. */ /*! @{ */ + #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) /*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this @@ -9500,6 +11270,7 @@ typedef struct { * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. */ #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) + #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) /*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this @@ -9520,13 +11291,18 @@ typedef struct { /*! @name MSTDAT - Combined Master receiver and transmitter data register. */ /*! @{ */ + #define I2C_MSTDAT_DATA_MASK (0xFFU) #define I2C_MSTDAT_DATA_SHIFT (0U) +/*! DATA - Master function data register. Read: read the most recently received data for the Master + * function. Write: transmit data using the Master function. + */ #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) /*! @} */ /*! @name SLVCTL - Slave control register. */ /*! @{ */ + #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) /*! SLVCONTINUE - Slave Continue. @@ -9537,6 +11313,7 @@ typedef struct { * should not be set unless SLVPENDING = 1. */ #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) + #define I2C_SLVCTL_SLVNACK_MASK (0x2U) #define I2C_SLVCTL_SLVNACK_SHIFT (1U) /*! SLVNACK - Slave NACK. @@ -9544,6 +11321,7 @@ typedef struct { * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). */ #define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) + #define I2C_SLVCTL_SLVDMA_MASK (0x8U) #define I2C_SLVCTL_SLVDMA_SHIFT (3U) /*! SLVDMA - Slave DMA enable. @@ -9551,6 +11329,7 @@ typedef struct { * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. */ #define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) + #define I2C_SLVCTL_AUTOACK_MASK (0x100U) #define I2C_SLVCTL_AUTOACK_SHIFT (8U) /*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches @@ -9566,6 +11345,7 @@ typedef struct { * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. */ #define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) + #define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) #define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) /*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write @@ -9580,13 +11360,18 @@ typedef struct { /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ /*! @{ */ + #define I2C_SLVDAT_DATA_MASK (0xFFU) #define I2C_SLVDAT_DATA_SHIFT (0U) +/*! DATA - Slave function data register. Read: read the most recently received data for the Slave + * function. Write: transmit data using the Slave function. + */ #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) /*! @} */ /*! @name SLVADR - Slave address register. */ /*! @{ */ + #define I2C_SLVADR_SADISABLE_MASK (0x1U) #define I2C_SLVADR_SADISABLE_SHIFT (0U) /*! SADISABLE - Slave Address n Disable. @@ -9594,9 +11379,13 @@ typedef struct { * 0b1..Ignored Slave Address n is ignored. */ #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) + #define I2C_SLVADR_SLVADR_MASK (0xFEU) #define I2C_SLVADR_SLVADR_SHIFT (1U) +/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. + */ #define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) + #define I2C_SLVADR_AUTONACK_MASK (0x8000U) #define I2C_SLVADR_AUTONACK_SHIFT (15U) /*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows @@ -9613,6 +11402,7 @@ typedef struct { /*! @name SLVQUAL0 - Slave Qualification for address 0. */ /*! @{ */ + #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) /*! QUALMODE0 - Qualify mode for slave address 0. @@ -9620,16 +11410,28 @@ typedef struct { * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. */ #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) + #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to + * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is + * set to 1 will cause an automatic match of the corresponding bit of the received address when it + * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for + * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 + * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). + */ #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) /*! @} */ /*! @name MONRXDAT - Monitor receiver data register. */ /*! @{ */ + #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. + */ #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) + #define I2C_MONRXDAT_MONSTART_MASK (0x100U) #define I2C_MONRXDAT_MONSTART_SHIFT (8U) /*! MONSTART - Monitor Received Start. @@ -9637,6 +11439,7 @@ typedef struct { * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. */ #define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) + #define I2C_MONRXDAT_MONRESTART_MASK (0x200U) #define I2C_MONRXDAT_MONRESTART_SHIFT (9U) /*! MONRESTART - Monitor Received Repeated Start. @@ -9644,6 +11447,7 @@ typedef struct { * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. */ #define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) + #define I2C_MONRXDAT_MONNACK_MASK (0x400U) #define I2C_MONRXDAT_MONNACK_SHIFT (10U) /*! MONNACK - Monitor Received NACK. @@ -9655,17 +11459,29 @@ typedef struct { /*! @name ID - Peripheral identification register. */ /*! @{ */ + #define I2C_ID_APERTURE_MASK (0xFFU) #define I2C_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ #define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) + #define I2C_ID_MINOR_REV_MASK (0xF00U) #define I2C_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ #define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) + #define I2C_ID_MAJOR_REV_MASK (0xF000U) #define I2C_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ #define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) + #define I2C_ID_ID_MASK (0xFFFF0000U) #define I2C_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ #define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) /*! @} */ @@ -9676,7 +11492,7 @@ typedef struct { /* I2C - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral I2C0 base address */ #define I2C0_BASE (0x50086000u) /** Peripheral I2C0 base address */ @@ -9812,13 +11628,7 @@ typedef struct { __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ uint8_t RESERVED_1[16]; __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - struct { /* offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */ - __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */ - uint8_t RESERVED_0[20]; - } SECCHANNEL[3]; - uint8_t RESERVED_2[384]; + uint8_t RESERVED_2[480]; __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ @@ -9835,7 +11645,8 @@ typedef struct { uint8_t RESERVED_6[8]; __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ - uint8_t RESERVED_7[436]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ } I2S_Type; @@ -9850,6 +11661,7 @@ typedef struct { /*! @name CFG1 - Configuration register 1 for the primary channel pair. */ /*! @{ */ + #define I2S_CFG1_MAINENABLE_MASK (0x1U) #define I2S_CFG1_MAINENABLE_SHIFT (0U) /*! MAINENABLE - Main enable for I 2S function in this Flexcomm @@ -9858,6 +11670,7 @@ typedef struct { * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. */ #define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) + #define I2S_CFG1_DATAPAUSE_MASK (0x2U) #define I2S_CFG1_DATAPAUSE_SHIFT (1U) /*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer @@ -9872,6 +11685,7 @@ typedef struct { * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. */ #define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) + #define I2S_CFG1_PAIRCOUNT_MASK (0xCU) #define I2S_CFG1_PAIRCOUNT_SHIFT (2U) /*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field @@ -9884,6 +11698,7 @@ typedef struct { * 0b11..4 I2S channel pairs in this flexcomm */ #define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) + #define I2S_CFG1_MSTSLVCFG_MASK (0x30U) #define I2S_CFG1_MSTSLVCFG_SHIFT (4U) /*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. @@ -9894,6 +11709,7 @@ typedef struct { * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. */ #define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) + #define I2S_CFG1_MODE_MASK (0xC0U) #define I2S_CFG1_MODE_SHIFT (6U) /*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all @@ -9908,6 +11724,7 @@ typedef struct { * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. */ #define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) + #define I2S_CFG1_RIGHTLOW_MASK (0x100U) #define I2S_CFG1_RIGHTLOW_SHIFT (8U) /*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left @@ -9922,6 +11739,7 @@ typedef struct { * bits 15:0 are used for the right channel. */ #define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) + #define I2S_CFG1_LEFTJUST_MASK (0x200U) #define I2S_CFG1_LEFTJUST_SHIFT (9U) /*! LEFTJUST - Left Justify data. @@ -9933,6 +11751,7 @@ typedef struct { * correspond to left justified data in the stream on the data bus. */ #define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) + #define I2S_CFG1_ONECHANNEL_MASK (0x400U) #define I2S_CFG1_ONECHANNEL_SHIFT (10U) /*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit @@ -9947,17 +11766,7 @@ typedef struct { * for the single channel of data is placed at the clock defined by POSITION. */ #define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) -#define I2S_CFG1_PDMDATA_MASK (0x800U) -#define I2S_CFG1_PDMDATA_SHIFT (11U) -/*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be - * set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a - * D-Mic subsystem. For the LPC55xx, this bit applies only to Flexcomm 6,7. - * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO. - * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in - * this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample - * rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. - */ -#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) + #define I2S_CFG1_SCK_POL_MASK (0x1000U) #define I2S_CFG1_SCK_POL_SHIFT (12U) /*! SCK_POL - SCK polarity. @@ -9965,6 +11774,7 @@ typedef struct { * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. */ #define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) + #define I2S_CFG1_WS_POL_MASK (0x2000U) #define I2S_CFG1_WS_POL_SHIFT (13U) /*! WS_POL - WS polarity. @@ -9972,23 +11782,54 @@ typedef struct { * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). */ #define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) + #define I2S_CFG1_DATALEN_MASK (0x1F0000U) #define I2S_CFG1_DATALEN_SHIFT (16U) +/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or + * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received + * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the + * I2S: Determines the size of data transfers between the FIFO and the I2S + * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of + * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse + * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to + * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = + * data is 32 bits in length + */ #define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) /*! @} */ /*! @name CFG2 - Configuration register 2 for the primary channel pair. */ /*! @{ */ + #define I2S_CFG2_FRAMELEN_MASK (0x1FFU) #define I2S_CFG2_FRAMELEN_SHIFT (0U) +/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the + * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported + * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is + * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in + * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger + * than DATALEN in order for the WS pulse to be generated correctly. + */ #define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) + #define I2S_CFG2_POSITION_MASK (0x1FF0000U) #define I2S_CFG2_POSITION_SHIFT (16U) +/*! POSITION - Data Position. Defines the location within the frame of the data for this channel + * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION + * defines the location of data in both the left phase and right phase, starting one clock after + * the WS edge. In other modes, POSITION defines the location of data within the entire frame. + * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The + * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels + * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit + * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS + * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. + */ #define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) /*! @} */ /*! @name STAT - Status register for the primary channel pair. */ /*! @{ */ + #define I2S_STAT_BUSY_MASK (0x1U) #define I2S_STAT_BUSY_SHIFT (0U) /*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. @@ -9996,6 +11837,7 @@ typedef struct { * 0b1..The transmitter/receiver for channel pair is currently processing data. */ #define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) + #define I2S_STAT_SLVFRMERR_MASK (0x2U) #define I2S_STAT_SLVFRMERR_SHIFT (1U) /*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as @@ -10005,6 +11847,7 @@ typedef struct { * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. */ #define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) + #define I2S_STAT_LR_MASK (0x4U) #define I2S_STAT_LR_SHIFT (2U) /*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to @@ -10014,6 +11857,7 @@ typedef struct { * 0b1..Right channel. */ #define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) + #define I2S_STAT_DATAPAUSED_MASK (0x8U) #define I2S_STAT_DATAPAUSED_SHIFT (3U) /*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels @@ -10026,55 +11870,20 @@ typedef struct { /*! @name DIV - Clock divider, used by all channel pairs. */ /*! @{ */ + #define I2S_DIV_DIV_MASK (0xFFFU) #define I2S_DIV_DIV_SHIFT (0U) +/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The + * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. + * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is + * divided by 4,096. + */ #define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) /*! @} */ -/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG1 */ -#define I2S_SECCHANNEL_PCFG1_COUNT (3U) - -/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) -#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) -#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG2 */ -#define I2S_SECCHANNEL_PCFG2_COUNT (3U) - -/*! @name SECCHANNEL_PSTAT - Status register for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) -#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) -#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) -#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) -#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) -#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PSTAT */ -#define I2S_SECCHANNEL_PSTAT_COUNT (3U) - /*! @name FIFOCFG - FIFO configuration and enable register. */ /*! @{ */ + #define I2S_FIFOCFG_ENABLETX_MASK (0x1U) #define I2S_FIFOCFG_ENABLETX_SHIFT (0U) /*! ENABLETX - Enable the transmit FIFO. @@ -10082,6 +11891,7 @@ typedef struct { * 0b1..The transmit FIFO is enabled. */ #define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) + #define I2S_FIFOCFG_ENABLERX_MASK (0x2U) #define I2S_FIFOCFG_ENABLERX_SHIFT (1U) /*! ENABLERX - Enable the receive FIFO. @@ -10089,6 +11899,7 @@ typedef struct { * 0b1..The receive FIFO is enabled. */ #define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) + #define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) #define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) /*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX @@ -10099,6 +11910,7 @@ typedef struct { * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. */ #define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) + #define I2S_FIFOCFG_PACK48_MASK (0x8U) #define I2S_FIFOCFG_PACK48_SHIFT (3U) /*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. @@ -10106,9 +11918,14 @@ typedef struct { * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. */ #define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) + #define I2S_FIFOCFG_SIZE_MASK (0x30U) #define I2S_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ #define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) + #define I2S_FIFOCFG_DMATX_MASK (0x1000U) #define I2S_FIFOCFG_DMATX_SHIFT (12U) /*! DMATX - DMA configuration for transmit. @@ -10116,6 +11933,7 @@ typedef struct { * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. */ #define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) + #define I2S_FIFOCFG_DMARX_MASK (0x2000U) #define I2S_FIFOCFG_DMARX_SHIFT (13U) /*! DMARX - DMA configuration for receive. @@ -10123,6 +11941,7 @@ typedef struct { * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. */ #define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) + #define I2S_FIFOCFG_WAKETX_MASK (0x4000U) #define I2S_FIFOCFG_WAKETX_SHIFT (14U) /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power @@ -10135,6 +11954,7 @@ typedef struct { * FIFOTRIG, even when the TXLVL interrupt is not enabled. */ #define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) + #define I2S_FIFOCFG_WAKERX_MASK (0x8000U) #define I2S_FIFOCFG_WAKERX_SHIFT (15U) /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power @@ -10147,54 +11967,93 @@ typedef struct { * FIFOTRIG, even when the RXLVL interrupt is not enabled. */ #define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) + #define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) #define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ #define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) + #define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) #define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) -#define I2S_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. */ -#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) /*! @} */ /*! @name FIFOSTAT - FIFO status register. */ /*! @{ */ + #define I2S_FIFOSTAT_TXERR_MASK (0x1U) #define I2S_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ #define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) + #define I2S_FIFOSTAT_RXERR_MASK (0x2U) #define I2S_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ #define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) + #define I2S_FIFOSTAT_PERINT_MASK (0x8U) #define I2S_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ #define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) + #define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) #define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ #define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) + #define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) #define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ #define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) + #define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) #define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ #define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) + #define I2S_FIFOSTAT_RXFULL_MASK (0x80U) #define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ #define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) + #define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) #define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ #define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) + #define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ #define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) /*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ /*! @{ */ + #define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) #define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -10203,6 +12062,7 @@ typedef struct { * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. */ #define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) + #define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) #define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -10211,16 +12071,32 @@ typedef struct { * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. */ #define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) + #define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) #define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ #define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) + #define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) #define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ #define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) /*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ /*! @{ */ + #define I2S_FIFOINTENSET_TXERR_MASK (0x1U) #define I2S_FIFOINTENSET_TXERR_SHIFT (0U) /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. @@ -10228,6 +12104,7 @@ typedef struct { * 0b1..An interrupt will be generated when a transmit error occurs. */ #define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) + #define I2S_FIFOINTENSET_RXERR_MASK (0x2U) #define I2S_FIFOINTENSET_RXERR_SHIFT (1U) /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. @@ -10235,6 +12112,7 @@ typedef struct { * 0b1..An interrupt will be generated when a receive error occurs. */ #define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) + #define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) #define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level @@ -10244,6 +12122,7 @@ typedef struct { * to the level specified by TXLVL in the FIFOTRIG register. */ #define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) + #define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) #define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level @@ -10257,94 +12136,161 @@ typedef struct { /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ /*! @{ */ + #define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) #define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) + #define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) #define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) + #define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) #define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) + #define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) #define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) /*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ /*! @{ */ + #define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) #define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ #define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) + #define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) #define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ #define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) + #define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) #define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ #define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) + #define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) #define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ #define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) + #define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) #define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ #define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) /*! @} */ /*! @name FIFOWR - FIFO write data. */ /*! @{ */ + #define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. + */ #define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) /*! @} */ /*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ /*! @{ */ + #define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) #define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ #define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) /*! @} */ /*! @name FIFORD - FIFO read data. */ /*! @{ */ + #define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. + */ #define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) /*! @} */ /*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ /*! @{ */ + #define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) #define I2S_FIFORD48H_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ #define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) /*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ /*! @{ */ + #define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ #define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) /*! @} */ /*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ /*! @{ */ + #define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) #define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ #define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) /*! @} */ +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + /*! @name ID - I2S Module identification */ /*! @{ */ -#define I2S_ID_Aperture_MASK (0xFFU) -#define I2S_ID_Aperture_SHIFT (0U) -#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK) -#define I2S_ID_Minor_Rev_MASK (0xF00U) -#define I2S_ID_Minor_Rev_SHIFT (8U) -#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK) -#define I2S_ID_Major_Rev_MASK (0xF000U) -#define I2S_ID_Major_Rev_SHIFT (12U) -#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK) + +#define I2S_ID_APERTURE_MASK (0xFFU) +#define I2S_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) + +#define I2S_ID_MINOR_REV_MASK (0xF00U) +#define I2S_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation, starting at 0. + */ +#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) + +#define I2S_ID_MAJOR_REV_MASK (0xF000U) +#define I2S_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation, starting at 0. + */ +#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) + #define I2S_ID_ID_MASK (0xFFFF0000U) #define I2S_ID_ID_SHIFT (16U) +/*! ID - Unique module identifier for this IP block. + */ #define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) /*! @} */ @@ -10355,7 +12301,7 @@ typedef struct { /* I2S - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral I2S0 base address */ #define I2S0_BASE (0x50086000u) /** Peripheral I2S0 base address */ @@ -10547,6 +12493,7 @@ typedef struct { /*! @name SCT0_INMUX - Input mux register for SCT0 input */ /*! @{ */ + #define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) #define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) /*! INP_N - Input number to SCT0 inputs 0 to 6.. @@ -10584,6 +12531,7 @@ typedef struct { /*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ /*! @{ */ + #define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) #define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) /*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 @@ -10604,9 +12552,9 @@ typedef struct { * 0b01110..CT_INP14 function selected from IOCON register * 0b01111..CT_INP15 function selected from IOCON register * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None * 0b10100..USB0_FRAME_TOGGLE * 0b10101..USB1_FRAME_TOGGLE * 0b10110..COMP_OUTPUT output from analog comparator @@ -10622,6 +12570,7 @@ typedef struct { /*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ /*! @{ */ + #define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) #define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) /*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 @@ -10642,9 +12591,9 @@ typedef struct { * 0b01110..CT_INP14 function selected from IOCON register * 0b01111..CT_INP15 function selected from IOCON register * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None * 0b10100..USB0_FRAME_TOGGLE * 0b10101..USB1_FRAME_TOGGLE * 0b10110..COMP_OUTPUT output from analog comparator @@ -10660,6 +12609,7 @@ typedef struct { /*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ /*! @{ */ + #define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) #define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) /*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 @@ -10680,9 +12630,9 @@ typedef struct { * 0b01110..CT_INP14 function selected from IOCON register * 0b01111..CT_INP15 function selected from IOCON register * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None * 0b10100..USB0_FRAME_TOGGLE * 0b10101..USB1_FRAME_TOGGLE * 0b10110..COMP_OUTPUT output from analog comparator @@ -10698,8 +12648,12 @@ typedef struct { /*! @name PINTSEL - Pin interrupt select register */ /*! @{ */ + #define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) #define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = + * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + */ #define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) /*! @} */ @@ -10708,6 +12662,7 @@ typedef struct { /*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ /*! @{ */ + #define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) #define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). @@ -10743,8 +12698,11 @@ typedef struct { /*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ /*! @{ */ + #define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) #define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). + */ #define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) /*! @} */ @@ -10753,20 +12711,43 @@ typedef struct { /*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ /*! @{ */ + #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ #define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) /*! @} */ /*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ /*! @{ */ + #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) /*! @} */ /*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ /*! @{ */ + #define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) #define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) /*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 @@ -10805,6 +12786,7 @@ typedef struct { /*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ /*! @{ */ + #define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) #define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) /*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 @@ -10843,8 +12825,12 @@ typedef struct { /*! @name PINTSECSEL - Pin interrupt secure select register */ /*! @{ */ + #define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) #define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: + * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. + */ #define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) /*! @} */ @@ -10853,6 +12839,7 @@ typedef struct { /*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ /*! @{ */ + #define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) #define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). @@ -10881,8 +12868,11 @@ typedef struct { /*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ /*! @{ */ + #define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) #define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). + */ #define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) /*! @} */ @@ -10891,85 +12881,125 @@ typedef struct { /*! @name DMA0_REQ_ENA - Enable DMA0 requests */ /*! @{ */ + #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) /*! @} */ /*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ /*! @{ */ + #define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) #define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register + */ #define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) /*! @} */ /*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ /*! @{ */ + #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register + */ #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) /*! @} */ /*! @name DMA1_REQ_ENA - Enable DMA1 requests */ /*! @{ */ + #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) /*! @} */ /*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ /*! @{ */ + #define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) #define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register + */ #define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) /*! @} */ /*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ /*! @{ */ + #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register + */ #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) /*! @} */ /*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ /*! @{ */ + #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) /*! @} */ /*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ /*! @{ */ + #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) /*! @} */ /*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ /*! @{ */ + #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) /*! @} */ /*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ /*! @{ */ + #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) /*! @} */ /*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ /*! @{ */ + #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) /*! @} */ /*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ /*! @{ */ + #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) /*! @} */ @@ -10980,7 +13010,7 @@ typedef struct { /* INPUTMUX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral INPUTMUX base address */ #define INPUTMUX_BASE (0x50006000u) /** Peripheral INPUTMUX base address */ @@ -11038,6 +13068,7 @@ typedef struct { /*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ /*! @{ */ + #define IOCON_PIO_FUNC_MASK (0xFU) #define IOCON_PIO_FUNC_SHIFT (0U) /*! FUNC - Selects pin function. @@ -11051,6 +13082,7 @@ typedef struct { * 0b0111..Alternative connection 7. */ #define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) + #define IOCON_PIO_MODE_MASK (0x30U) #define IOCON_PIO_MODE_SHIFT (4U) /*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). @@ -11060,13 +13092,15 @@ typedef struct { * 0b11..Repeater. Repeater mode. */ #define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) + #define IOCON_PIO_SLEW_MASK (0x40U) #define IOCON_PIO_SLEW_SHIFT (6U) /*! SLEW - Driver slew rate. - * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. - * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. */ #define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) + #define IOCON_PIO_INVERT_MASK (0x80U) #define IOCON_PIO_INVERT_SHIFT (7U) /*! INVERT - Input polarity. @@ -11074,27 +13108,32 @@ typedef struct { * 0b1..Enabled. Input is function inverted. */ #define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) + #define IOCON_PIO_DIGIMODE_MASK (0x100U) #define IOCON_PIO_DIGIMODE_SHIFT (8U) /*! DIGIMODE - Select Digital mode. - * 0b0..Analog mode, digital input is disabled. - * 0b1..Digital mode, digital input is enabled. + * 0b0..Disable digital mode. Digital input set to 0. + * 0b1..Enable Digital mode. Digital input is enabled. */ #define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) + #define IOCON_PIO_OD_MASK (0x200U) #define IOCON_PIO_OD_SHIFT (9U) -/*! OD - Controls open-drain mode. +/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). * 0b0..Normal. Normal push-pull output * 0b1..Open-drain. Simulated open-drain output (high drive disabled). */ #define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) + #define IOCON_PIO_ASW_MASK (0x400U) #define IOCON_PIO_ASW_SHIFT (10U) -/*! ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 - * 0b0..Analog switch is open. - * 0b1..Analog switch is closed. +/*! ASW - Analog switch input control. + * 0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed + * (enabled). For the other pins, analog switch is open (disabled). + * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) */ #define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) + #define IOCON_PIO_SSEL_MASK (0x800U) #define IOCON_PIO_SSEL_SHIFT (11U) /*! SSEL - Supply Selection bit. @@ -11102,32 +13141,36 @@ typedef struct { * 0b1..1V8 Signaling in I2C Mode. */ #define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) + #define IOCON_PIO_FILTEROFF_MASK (0x1000U) #define IOCON_PIO_FILTEROFF_SHIFT (12U) /*! FILTEROFF - Controls input glitch filter. - * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out. - * 0b1..Filter disabled. No input filtering is done. + * 0b0..Filter enabled. + * 0b1..Filter disabled. */ #define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) + #define IOCON_PIO_ECS_MASK (0x2000U) #define IOCON_PIO_ECS_SHIFT (13U) -/*! ECS - Pull-up current source enable in IIC mode. +/*! ECS - Pull-up current source enable in I2C mode. * 0b1..Enabled. Pull resistor is conencted. - * 0b0..Disabled. IO is in open drain. + * 0b0..Disabled. IO is in open drain cell. */ #define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) + #define IOCON_PIO_EGP_MASK (0x4000U) #define IOCON_PIO_EGP_SHIFT (14U) -/*! EGP - Controls slew rate of I2C pad. +/*! EGP - Switch between GPIO mode and I2C mode. * 0b0..I2C mode. * 0b1..GPIO mode. */ #define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) + #define IOCON_PIO_I2CFILTER_MASK (0x8000U) #define IOCON_PIO_I2CFILTER_SHIFT (15U) -/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - * 0b0..I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. - * 0b1..I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. +/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. + * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. + * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. */ #define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) /*! @} */ @@ -11145,7 +13188,7 @@ typedef struct { /* IOCON - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral IOCON base address */ #define IOCON_BASE (0x50001000u) /** Peripheral IOCON base address */ @@ -11210,8 +13253,11 @@ typedef struct { /*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ /*! @{ */ + #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) +/*! INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. + */ #define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) /*! @} */ @@ -11220,8 +13266,11 @@ typedef struct { /*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ /*! @{ */ + #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) +/*! INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register. + */ #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) /*! @} */ @@ -11230,8 +13279,11 @@ typedef struct { /*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ /*! @{ */ + #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) +/*! INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register. + */ #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) /*! @} */ @@ -11240,8 +13292,11 @@ typedef struct { /*! @name MUTEX - Mutual exclusion register[1] */ /*! @{ */ + #define MAILBOX_MUTEX_EX_MASK (0x1U) #define MAILBOX_MUTEX_EX_SHIFT (0U) +/*! EX - Cleared when read, set when written. See usage description above. + */ #define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) /*! @} */ @@ -11252,7 +13307,7 @@ typedef struct { /* MAILBOX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral MAILBOX base address */ #define MAILBOX_BASE (0x5008B000u) /** Peripheral MAILBOX base address */ @@ -11321,9 +13376,17 @@ typedef struct { /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ /*! @{ */ + #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT + * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to + * this bit field starts the timer immediately. If the timer is running, writing a zero to this + * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer + * stops at the end of the time interval. + */ #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) + #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) /*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. @@ -11340,8 +13403,15 @@ typedef struct { /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ /*! @{ */ + #define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn + * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval + * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn + * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields + * returns -1 (0x00FF FFFF). + */ #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) /*! @} */ @@ -11350,6 +13420,7 @@ typedef struct { /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ /*! @{ */ + #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) /*! INTEN - Enable the TIMERn interrupt. @@ -11357,6 +13428,7 @@ typedef struct { * 0b1..Enabled. TIMERn interrupt is enabled. */ #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) + #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) /*! MODE - Selects timer mode. @@ -11373,6 +13445,7 @@ typedef struct { /*! @name CHANNEL_STAT - MRT Status register. */ /*! @{ */ + #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) /*! INTFLAG - Monitors the interrupt flag. @@ -11382,6 +13455,7 @@ typedef struct { * are raised. Writing a 1 to this bit clears the interrupt request. */ #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) + #define MRT_CHANNEL_STAT_RUN_MASK (0x2U) #define MRT_CHANNEL_STAT_RUN_SHIFT (1U) /*! RUN - Indicates the state of TIMERn. This bit is read-only. @@ -11389,6 +13463,7 @@ typedef struct { * 0b1..Running. TIMERn is running. */ #define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) + #define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) #define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) /*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG @@ -11405,12 +13480,19 @@ typedef struct { /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ /*! @{ */ + #define MRT_MODCFG_NOC_MASK (0xFU) #define MRT_MODCFG_NOC_SHIFT (0U) +/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) + */ #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) + #define MRT_MODCFG_NOB_MASK (0x1F0U) #define MRT_MODCFG_NOB_SHIFT (4U) +/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) + */ #define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) + #define MRT_MODCFG_MULTITASK_MASK (0x80000000U) #define MRT_MODCFG_MULTITASK_SHIFT (31U) /*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. @@ -11422,13 +13504,20 @@ typedef struct { /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ /*! @{ */ + #define MRT_IDLE_CH_CHAN_MASK (0xF0U) #define MRT_IDLE_CH_CHAN_SHIFT (4U) +/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is + * positioned such that it can be used as an offset from the MRT base address in order to access + * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See + * text above for more details. + */ #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) /*! @} */ /*! @name IRQ_FLAG - Global interrupt flag register */ /*! @{ */ + #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) /*! GFLAG0 - Monitors the interrupt flag of TIMER0. @@ -11438,14 +13527,23 @@ typedef struct { * interrupt are raised. Writing a 1 to this bit clears the interrupt request. */ #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) + #define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) #define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. + */ #define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) + #define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) #define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. + */ #define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) + #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. + */ #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) /*! @} */ @@ -11456,7 +13554,7 @@ typedef struct { /* MRT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral MRT0 base address */ #define MRT0_BASE (0x5000D000u) /** Peripheral MRT0 base address */ @@ -11504,12 +13602,12 @@ typedef struct { typedef struct { __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ - __I uint32_t CAPTUREN_L; /**< Local Capture Low Register for CPUn, offset: 0x8 */ - __I uint32_t CAPTUREN_H; /**< Local Capture High Register for CPUn, offset: 0xC */ - __IO uint32_t MATCHN_L; /**< Local Match Low Register for CPUn, offset: 0x10 */ - __IO uint32_t MATCHN_H; /**< Match High Register for CPUn, offset: 0x14 */ + __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ uint8_t RESERVED_0[4]; - __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register for CPUn, offset: 0x1C */ + __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ } OSTIMER_Type; /* ---------------------------------------------------------------------------- @@ -11523,54 +13621,96 @@ typedef struct { /*! @name EVTIMERL - EVTIMER Low Register */ /*! @{ */ + #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits + * EVTIMER. Note: There is only one EVTIMER, readable from all domains. + */ #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) /*! @} */ /*! @name EVTIMERH - EVTIMER High Register */ /*! @{ */ -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits + * EVTIMER. Note there is only one EVTIMER, readable from all domains. + */ #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) /*! @} */ -/*! @name CAPTUREN_L - Local Capture Low Register for CPUn */ +/*! @name CAPTURE_L - Capture Low Register */ /*! @{ */ -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT (0U) -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK) + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) /*! @} */ -/*! @name CAPTUREN_H - Local Capture High Register for CPUn */ +/*! @name CAPTURE_H - Capture High Register */ /*! @{ */ -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT (0U) -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK) + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) /*! @} */ -/*! @name MATCHN_L - Local Match Low Register for CPUn */ +/*! @name MATCH_L - Match Low Register */ /*! @{ */ -#define OSTIMER_MATCHN_L_MATCHn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT (0U) -#define OSTIMER_MATCHN_L_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_L_MATCHn_VALUE_MASK) + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central + * EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) /*! @} */ -/*! @name MATCHN_H - Match High Register for CPUn */ +/*! @name MATCH_H - Match High Register */ /*! @{ */ -#define OSTIMER_MATCHN_H_MATCHn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT (0U) -#define OSTIMER_MATCHN_H_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_H_MATCHn_VALUE_MASK) + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared + * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) /*! @} */ -/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register for CPUn */ +/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ /*! @{ */ + #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and + * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes + * to clear this bit are asynchronous. It should be done before a new match value is written into + * the MATCH_L/H registers. + */ #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will + * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests + * due to the OSTIMER_INTR flag are blocked. + */ #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In + * typical applications it should not be necessary to test this bit. [1] + */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) /*! @} */ @@ -11580,7 +13720,7 @@ typedef struct { /* OSTIMER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral OSTIMER base address */ #define OSTIMER_BASE (0x5002D000u) /** Peripheral OSTIMER base address */ @@ -11652,76 +13792,131 @@ typedef struct { /*! @name ISEL - Pin Interrupt Mode register */ /*! @{ */ + #define PINT_ISEL_PMODE_MASK (0xFFU) #define PINT_ISEL_PMODE_SHIFT (0U) +/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt + * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive + */ #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) /*! @} */ /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ /*! @{ */ + #define PINT_IENR_ENRL_MASK (0xFFU) #define PINT_IENR_ENRL_SHIFT (0U) +/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the + * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable + * rising edge or level interrupt. + */ #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) /*! @} */ /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ /*! @{ */ + #define PINT_SIENR_SETENRL_MASK (0xFFU) #define PINT_SIENR_SETENRL_SHIFT (0U) +/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n + * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. + */ #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) /*! @} */ /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ /*! @{ */ + #define PINT_CIENR_CENRL_MASK (0xFFU) #define PINT_CIENR_CENRL_SHIFT (0U) +/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit + * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level + * interrupt. + */ #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) /*! @} */ /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ /*! @{ */ + #define PINT_IENF_ENAF_MASK (0xFFU) #define PINT_IENF_ENAF_SHIFT (0U) +/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. + * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt + * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active + * interrupt level HIGH. + */ #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) /*! @} */ /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ /*! @{ */ + #define PINT_SIENF_SETENAF_MASK (0xFFU) #define PINT_SIENF_SETENAF_SHIFT (0U) +/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n + * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable + * falling edge interrupt. + */ #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) /*! @} */ /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ /*! @{ */ + #define PINT_CIENF_CENAF_MASK (0xFFU) #define PINT_CIENF_CENAF_SHIFT (0U) +/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n + * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or + * falling edge interrupt disabled. + */ #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) /*! @} */ /*! @name RISE - Pin interrupt rising edge register */ /*! @{ */ + #define PINT_RISE_RDET_MASK (0xFFU) #define PINT_RISE_RDET_SHIFT (0U) +/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read + * 0: No rising edge has been detected on this pin since Reset or the last time a one was written + * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the + * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. + */ #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) /*! @} */ /*! @name FALL - Pin interrupt falling edge register */ /*! @{ */ + #define PINT_FALL_FDET_MASK (0xFFU) #define PINT_FALL_FDET_SHIFT (0U) +/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read + * 0: No falling edge has been detected on this pin since Reset or the last time a one was + * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or + * the last time a one was written to this bit. Write 1: clear falling edge detection for this + * pin. + */ #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) /*! @} */ /*! @name IST - Pin interrupt status register */ /*! @{ */ + #define PINT_IST_PSTAT_MASK (0xFFU) #define PINT_IST_PSTAT_SHIFT (0U) +/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts + * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for + * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this + * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. + * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). + */ #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) /*! @} */ /*! @name PMCTRL - Pattern match interrupt control register */ /*! @{ */ + #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) /*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. @@ -11729,6 +13924,7 @@ typedef struct { * 0b1..Pattern match. Interrupts are driven in response to pattern matches. */ #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) + #define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) #define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) /*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. @@ -11736,13 +13932,19 @@ typedef struct { * 0b1..Enabled. RXEV output to the CPU is enabled. */ #define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) + #define PINT_PMCTRL_PMAT_MASK (0xFF000000U) #define PINT_PMCTRL_PMAT_SHIFT (24U) +/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field + * indicates that the corresponding product term is matched by the current state of the appropriate + * inputs. + */ #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) /*! @} */ /*! @name PMSRC - Pattern match interrupt bit-slice source register */ /*! @{ */ + #define PINT_PMSRC_SRC0_MASK (0x700U) #define PINT_PMSRC_SRC0_SHIFT (8U) /*! SRC0 - Selects the input source for bit slice 0 @@ -11756,6 +13958,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. */ #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) + #define PINT_PMSRC_SRC1_MASK (0x3800U) #define PINT_PMSRC_SRC1_SHIFT (11U) /*! SRC1 - Selects the input source for bit slice 1 @@ -11769,6 +13972,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. */ #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) + #define PINT_PMSRC_SRC2_MASK (0x1C000U) #define PINT_PMSRC_SRC2_SHIFT (14U) /*! SRC2 - Selects the input source for bit slice 2 @@ -11782,6 +13986,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. */ #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) + #define PINT_PMSRC_SRC3_MASK (0xE0000U) #define PINT_PMSRC_SRC3_SHIFT (17U) /*! SRC3 - Selects the input source for bit slice 3 @@ -11795,6 +14000,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. */ #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) + #define PINT_PMSRC_SRC4_MASK (0x700000U) #define PINT_PMSRC_SRC4_SHIFT (20U) /*! SRC4 - Selects the input source for bit slice 4 @@ -11808,6 +14014,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. */ #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) + #define PINT_PMSRC_SRC5_MASK (0x3800000U) #define PINT_PMSRC_SRC5_SHIFT (23U) /*! SRC5 - Selects the input source for bit slice 5 @@ -11821,6 +14028,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. */ #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) + #define PINT_PMSRC_SRC6_MASK (0x1C000000U) #define PINT_PMSRC_SRC6_SHIFT (26U) /*! SRC6 - Selects the input source for bit slice 6 @@ -11834,6 +14042,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. */ #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) + #define PINT_PMSRC_SRC7_MASK (0xE0000000U) #define PINT_PMSRC_SRC7_SHIFT (29U) /*! SRC7 - Selects the input source for bit slice 7 @@ -11851,6 +14060,7 @@ typedef struct { /*! @name PMCFG - Pattern match interrupt bit slice configuration register */ /*! @{ */ + #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) /*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. @@ -11858,6 +14068,7 @@ typedef struct { * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) + #define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) #define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) /*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. @@ -11865,6 +14076,7 @@ typedef struct { * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) + #define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) #define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) /*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. @@ -11872,6 +14084,7 @@ typedef struct { * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) + #define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) #define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) /*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. @@ -11879,6 +14092,7 @@ typedef struct { * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) + #define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) #define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) /*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. @@ -11886,6 +14100,7 @@ typedef struct { * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) + #define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) #define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) /*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. @@ -11893,6 +14108,7 @@ typedef struct { * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) + #define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) #define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) /*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. @@ -11900,6 +14116,7 @@ typedef struct { * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) + #define PINT_PMCFG_CFG0_MASK (0x700U) #define PINT_PMCFG_CFG0_SHIFT (8U) /*! CFG0 - Specifies the match contribution condition for bit slice 0. @@ -11921,6 +14138,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) + #define PINT_PMCFG_CFG1_MASK (0x3800U) #define PINT_PMCFG_CFG1_SHIFT (11U) /*! CFG1 - Specifies the match contribution condition for bit slice 1. @@ -11942,6 +14160,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) + #define PINT_PMCFG_CFG2_MASK (0x1C000U) #define PINT_PMCFG_CFG2_SHIFT (14U) /*! CFG2 - Specifies the match contribution condition for bit slice 2. @@ -11963,6 +14182,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) + #define PINT_PMCFG_CFG3_MASK (0xE0000U) #define PINT_PMCFG_CFG3_SHIFT (17U) /*! CFG3 - Specifies the match contribution condition for bit slice 3. @@ -11984,6 +14204,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) + #define PINT_PMCFG_CFG4_MASK (0x700000U) #define PINT_PMCFG_CFG4_SHIFT (20U) /*! CFG4 - Specifies the match contribution condition for bit slice 4. @@ -12005,6 +14226,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) + #define PINT_PMCFG_CFG5_MASK (0x3800000U) #define PINT_PMCFG_CFG5_SHIFT (23U) /*! CFG5 - Specifies the match contribution condition for bit slice 5. @@ -12026,6 +14248,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) + #define PINT_PMCFG_CFG6_MASK (0x1C000000U) #define PINT_PMCFG_CFG6_SHIFT (26U) /*! CFG6 - Specifies the match contribution condition for bit slice 6. @@ -12047,6 +14270,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) + #define PINT_PMCFG_CFG7_MASK (0xE0000000U) #define PINT_PMCFG_CFG7_SHIFT (29U) /*! CFG7 - Specifies the match contribution condition for bit slice 7. @@ -12077,7 +14301,7 @@ typedef struct { /* PINT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral PINT base address */ #define PINT_BASE (0x50004000u) /** Peripheral PINT base address */ @@ -12136,14 +14360,14 @@ typedef struct { /** PLU - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x20 */ - __IO uint32_t INP[5]; /**< LUT0 input 0 MUX..LUT25 input 4 MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ + __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ uint8_t RESERVED_0[12]; } LUT[26]; uint8_t RESERVED_0[1216]; __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ uint8_t RESERVED_1[152]; __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ - __IO uint32_t WAKEINT; /**< Wakeup interrupt control for PLU, offset: 0x904 */ + __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ uint8_t RESERVED_2[760]; __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ } PLU_Type; @@ -12157,18 +14381,20 @@ typedef struct { * @{ */ -/*! @name LUT_INP - LUT0 input 0 MUX..LUT25 input 4 MUX */ +/*! @name LUT_INP_MUX - LUTn input x MUX */ /*! @{ */ -#define PLU_LUT_INP_LUT_INP_MASK (0x3FU) -#define PLU_LUT_INP_LUT_INP_SHIFT (0U) -/*! LUT_INP - Selects the input source to be connected to LUT25 input4. + +#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) +#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) +/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot + * associated with the output from LUTn itself is tied low. * 0b000000..The PLU primary inputs 0. * 0b000001..The PLU primary inputs 1. * 0b000010..The PLU primary inputs 2. * 0b000011..The PLU primary inputs 3. * 0b000100..The PLU primary inputs 4. * 0b000101..The PLU primary inputs 5. - * 0b000110..Tie low. + * 0b000110..The output of LUT0. * 0b000111..The output of LUT1. * 0b001000..The output of LUT2. * 0b001001..The output of LUT3. @@ -12199,59 +14425,83 @@ typedef struct { * 0b100010..state(2). * 0b100011..state(3). */ -#define PLU_LUT_INP_LUT_INP(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_LUT_INP_SHIFT)) & PLU_LUT_INP_LUT_INP_MASK) +#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) /*! @} */ -/* The count of PLU_LUT_INP */ -#define PLU_LUT_INP_COUNT (26U) +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT (26U) -/* The count of PLU_LUT_INP */ -#define PLU_LUT_INP_COUNT2 (5U) +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT2 (5U) -/*! @name LUT_T_LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ +/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ /*! @{ */ -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK (0xFFFFFFFFU) -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT (0U) -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT)) & PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK) + +#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) +#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) +/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. + */ +#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) /*! @} */ -/* The count of PLU_LUT_T_LUT_TRUTH */ -#define PLU_LUT_T_LUT_TRUTH_COUNT (26U) +/* The count of PLU_LUT_TRUTH */ +#define PLU_LUT_TRUTH_COUNT (26U) /*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ /*! @{ */ + #define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) #define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) +/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. + */ #define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) /*! @} */ -/*! @name WAKEINT - Wakeup interrupt control for PLU */ +/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ /*! @{ */ -#define PLU_WAKEINT_MASK_MASK (0xFFU) -#define PLU_WAKEINT_MASK_SHIFT (0U) -#define PLU_WAKEINT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_MASK_SHIFT)) & PLU_WAKEINT_MASK_MASK) -#define PLU_WAKEINT_FILTER_MODE_MASK (0x300U) -#define PLU_WAKEINT_FILTER_MODE_SHIFT (8U) -/*! FILTER_MODE - control input of the PLU, add filtering for glitch + +#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) +#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) +/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) + */ +#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) +#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) +/*! FILTER_MODE - control input of the PLU, add filtering for glitch. * 0b00..Bypass mode. * 0b01..Filter 1 clock period. * 0b10..Filter 2 clock period. * 0b11..Filter 3 clock period. */ -#define PLU_WAKEINT_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_MODE_SHIFT)) & PLU_WAKEINT_FILTER_MODE_MASK) -#define PLU_WAKEINT_FILTER_CLKSEL_MASK (0xC00U) -#define PLU_WAKEINT_FILTER_CLKSEL_SHIFT (10U) -#define PLU_WAKEINT_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_FILTER_CLKSEL_MASK) -#define PLU_WAKEINT_LATCH_ENABLE_MASK (0x1000U) -#define PLU_WAKEINT_LATCH_ENABLE_SHIFT (12U) -#define PLU_WAKEINT_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_LATCH_ENABLE_MASK) -#define PLU_WAKEINT_INTR_CLEAR_MASK (0x2000U) -#define PLU_WAKEINT_INTR_CLEAR_SHIFT (13U) -#define PLU_WAKEINT_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_INTR_CLEAR_MASK) +#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) +/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. + * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. + * 0b01..Selects the 12 Mhz FRO as the filter clock. + * 0b10..Selects a third filter clock source, if provided. + * 0b11..Reserved. + */ +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) + +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) +/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR + */ +#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) + +#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) +#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) +/*! INTR_CLEAR - Write to clear wakeint_latched + */ +#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) /*! @} */ /*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ /*! @{ */ + #define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) #define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) /*! OUTPUTn - Selects the source to be connected to PLU Output 7. @@ -12299,7 +14549,7 @@ typedef struct { /* PLU - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral PLU base address */ #define PLU_BASE (0x5003D000u) /** Peripheral PLU base address */ @@ -12343,35 +14593,41 @@ typedef struct { /** PMC - Register Layout Typedef */ typedef struct { - uint8_t RESERVED_0[8]; + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ - __IO uint32_t RESETCAUSE; /**< Reset Cause register [Reset by: PoR], offset: 0xC */ - uint8_t RESERVED_1[32]; - __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DCDC0; /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */ + __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ uint8_t RESERVED_2[4]; - __IO uint32_t BODCORE; /**< Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x38 */ - uint8_t RESERVED_3[8]; - __IO uint32_t FRO1M; /**< 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x44 */ - __IO uint32_t FRO32K; /**< 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x48 */ + __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ + uint8_t RESERVED_3[16]; + __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ + uint8_t RESERVED_4[12]; + __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ + uint8_t RESERVED_5[8]; __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ - uint8_t RESERVED_4[20]; + uint8_t RESERVED_6[16]; + __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ - uint8_t RESERVED_5[8]; + uint8_t RESERVED_7[8]; __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ - uint8_t RESERVED_6[12]; + uint8_t RESERVED_8[12]; __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ - uint8_t RESERVED_7[16]; + uint8_t RESERVED_9[8]; + __IO uint32_t MISCCTRL; /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ + uint8_t RESERVED_10[4]; __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ - uint8_t RESERVED_8[16]; - __IO uint32_t PDSLEEPCFG0; /**< Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB0 */ - uint8_t RESERVED_9[4]; + uint8_t RESERVED_11[24]; __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ - uint8_t RESERVED_10[4]; + uint8_t RESERVED_12[4]; __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ - uint8_t RESERVED_11[4]; + uint8_t RESERVED_13[4]; __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ + uint8_t RESERVED_14[8]; + __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ } PMC_Type; /* ---------------------------------------------------------------------------- @@ -12383,8 +14639,23 @@ typedef struct { * @{ */ +/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ +/*! @{ */ + +#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) +#define PMC_STATUS_BOOTMODE_SHIFT (18U) +/*! BOOTMODE - Latest IC Boot cause:. + * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). + * 0b01..Latest IC boot was from DEEP SLEEP low power mode. + * 0b10..Latest IC boot was from POWER DOWN low power mode. + * 0b11..Latest IC boot was from DEEP POWER DOWN low power mode. + */ +#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) +/*! @} */ + /*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ + #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) /*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). @@ -12392,6 +14663,7 @@ typedef struct { * 0b1..Reset event from DEEP POWER DOWN mode is enable. */ #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) + #define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) #define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) /*! BODVBATRESETENABLE - BOD VBAT reset enable. @@ -12399,6 +14671,7 @@ typedef struct { * 0b1..BOD VBAT reset is enable. */ #define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) + #define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) #define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) /*! BODCORERESETENABLE - BOD CORE reset enable. @@ -12406,6 +14679,7 @@ typedef struct { * 0b1..BOD CORE reset is enable. */ #define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) + #define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) #define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) /*! SWRRESETENABLE - Software reset enable. @@ -12415,39 +14689,242 @@ typedef struct { #define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) /*! @} */ -/*! @name RESETCAUSE - Reset Cause register [Reset by: PoR] */ +/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ -#define PMC_RESETCAUSE_POR_MASK (0x1U) -#define PMC_RESETCAUSE_POR_SHIFT (0U) -#define PMC_RESETCAUSE_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_POR_SHIFT)) & PMC_RESETCAUSE_POR_MASK) -#define PMC_RESETCAUSE_PADRESET_MASK (0x2U) -#define PMC_RESETCAUSE_PADRESET_SHIFT (1U) -#define PMC_RESETCAUSE_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_PADRESET_SHIFT)) & PMC_RESETCAUSE_PADRESET_MASK) -#define PMC_RESETCAUSE_BODRESET_MASK (0x4U) -#define PMC_RESETCAUSE_BODRESET_SHIFT (2U) -#define PMC_RESETCAUSE_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_BODRESET_SHIFT)) & PMC_RESETCAUSE_BODRESET_MASK) -#define PMC_RESETCAUSE_SYSTEMRESET_MASK (0x8U) -#define PMC_RESETCAUSE_SYSTEMRESET_SHIFT (3U) -#define PMC_RESETCAUSE_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SYSTEMRESET_SHIFT)) & PMC_RESETCAUSE_SYSTEMRESET_MASK) -#define PMC_RESETCAUSE_WDTRESET_MASK (0x10U) -#define PMC_RESETCAUSE_WDTRESET_SHIFT (4U) -#define PMC_RESETCAUSE_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_WDTRESET_SHIFT)) & PMC_RESETCAUSE_WDTRESET_MASK) -#define PMC_RESETCAUSE_SWRRESET_MASK (0x20U) -#define PMC_RESETCAUSE_SWRRESET_SHIFT (5U) -#define PMC_RESETCAUSE_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SWRRESET_SHIFT)) & PMC_RESETCAUSE_SWRRESET_MASK) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK (0x40U) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT (6U) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT)) & PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK) -#define PMC_RESETCAUSE_DPDRESET_RTC_MASK (0x80U) -#define PMC_RESETCAUSE_DPDRESET_RTC_SHIFT (7U) -#define PMC_RESETCAUSE_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_RTC_SHIFT)) & PMC_RESETCAUSE_DPDRESET_RTC_MASK) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK (0x100U) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT (8U) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT)) & PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK) + +#define PMC_DCDC0_RC_MASK (0x3FU) +#define PMC_DCDC0_RC_SHIFT (0U) +/*! RC - Constant On-Time calibration. + */ +#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) + +#define PMC_DCDC0_ICOMP_MASK (0xC0U) +#define PMC_DCDC0_ICOMP_SHIFT (6U) +/*! ICOMP - Select the type of ZCD comparator. + */ +#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) + +#define PMC_DCDC0_ISEL_MASK (0x300U) +#define PMC_DCDC0_ISEL_SHIFT (8U) +/*! ISEL - Alter Internal biasing currents. + */ +#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) + +#define PMC_DCDC0_ICENABLE_MASK (0x400U) +#define PMC_DCDC0_ICENABLE_SHIFT (10U) +/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. + */ +#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) + +#define PMC_DCDC0_TMOS_MASK (0xF800U) +#define PMC_DCDC0_TMOS_SHIFT (11U) +/*! TMOS - One-shot generator reference current trimming signal. + */ +#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) + +#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) +#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) +/*! DISABLEISENSE - Disable Current sensing. + */ +#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) + +#define PMC_DCDC0_VOUT_MASK (0x1E0000U) +#define PMC_DCDC0_VOUT_SHIFT (17U) +/*! VOUT - Set output regulation voltage. + * 0b0000..0.95 V. + * 0b0001..0.975 V. + * 0b0010..1 V. + * 0b0011..1.025 V. + * 0b0100..1.05 V. + * 0b0101..1.075 V. + * 0b0110..1.1 V. + * 0b0111..1.125 V. + * 0b1000..1.15 V. + * 0b1001..1.175 V. + * 0b1010..1.2 V. + */ +#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) + +#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) +#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) +/*! SLICINGENABLE - Enable staggered switching of power switches. + */ +#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) + +#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) +#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) +/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. + */ +#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) + +#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) +#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) +/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. + */ +#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) +/*! @} */ + +/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) +#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) +/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. + */ +#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) + +#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) +#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) +/*! RSENSETRIM - Adjust Max inductor peak current limiting. + */ +#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) + +#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) +#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) +/*! DTESTENABLE - Enable Digital test signals. + */ +#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) + +#define PMC_DCDC1_SETCURVE_MASK (0x600U) +#define PMC_DCDC1_SETCURVE_SHIFT (9U) +/*! SETCURVE - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) + +#define PMC_DCDC1_SETDC_MASK (0x7800U) +#define PMC_DCDC1_SETDC_SHIFT (11U) +/*! SETDC - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) + +#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) +#define PMC_DCDC1_DTESTSEL_SHIFT (15U) +/*! DTESTSEL - Select the output signal for test. + */ +#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) + +#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) +#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) +/*! ISCALEENABLE - Modify COT behavior. + */ +#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) + +#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) +#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) +/*! FORCEBYPASS - Force bypass mode. + */ +#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) + +#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) +#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) +/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. + */ +#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) + +#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) +#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) +/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. + */ +#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) + +#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) +#define PMC_DCDC1_LCENABLE_SHIFT (25U) +/*! LCENABLE - Change the range of the peak detector of current inside the inductor. + */ +#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) + +#define PMC_DCDC1_TOFF_MASK (0x7C000000U) +#define PMC_DCDC1_TOFF_SHIFT (26U) +/*! TOFF - Constant Off-Time calibration input. + */ +#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) + +#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) +#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) +/*! TOFFENABLE - Enable Constant Off-Time feature. + */ +#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) +/*! @} */ + +/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_LDOPMU_VADJ_MASK (0x1FU) +#define PMC_LDOPMU_VADJ_SHIFT (0U) +/*! VADJ - Sets the Always-On domain LDO output level. + * 0b00000..1.22 V. + * 0b00001..0.7 V. + * 0b00010..0.725 V. + * 0b00011..0.75 V. + * 0b00100..0.775 V. + * 0b00101..0.8 V. + * 0b00110..0.825 V. + * 0b00111..0.85 V. + * 0b01000..0.875 V. + * 0b01001..0.9 V. + * 0b01010..0.96 V. + * 0b01011..0.97 V. + * 0b01100..0.98 V. + * 0b01101..0.99 V. + * 0b01110..1 V. + * 0b01111..1.01 V. + * 0b10000..1.02 V. + * 0b10001..1.03 V. + * 0b10010..1.04 V. + * 0b10011..1.05 V. + * 0b10100..1.06 V. + * 0b10101..1.07 V. + * 0b10110..1.08 V. + * 0b10111..1.09 V. + * 0b11000..1.1 V. + * 0b11001..1.11 V. + * 0b11010..1.12 V. + * 0b11011..1.13 V. + * 0b11100..1.14 V. + * 0b11101..1.15 V. + * 0b11110..1.16 V. + * 0b11111..1.22 V. + */ +#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) + +#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) +#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) +/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) +#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) +/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. + */ +#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) +#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) +/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) + +#define PMC_LDOPMU_BOOST_ENA_MASK (0x1000000U) +#define PMC_LDOPMU_BOOST_ENA_SHIFT (24U) +/*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK) + +#define PMC_LDOPMU_BOOST_ENA_PWD_MASK (0x2000000U) +#define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT (25U) +/*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK) /*! @} */ /*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ /*! @{ */ + #define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) #define PMC_BODVBAT_TRIGLVL_SHIFT (0U) /*! TRIGLVL - BoD trigger level. @@ -12485,6 +14962,7 @@ typedef struct { * 0b11111..3.30 V. */ #define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) + #define PMC_BODVBAT_HYST_MASK (0x60U) #define PMC_BODVBAT_HYST_SHIFT (5U) /*! HYST - BoD Hysteresis control. @@ -12496,115 +14974,65 @@ typedef struct { #define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) /*! @} */ -/*! @name BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ /*! @{ */ -#define PMC_BODCORE_TRIGLVL_MASK (0x7U) -#define PMC_BODCORE_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b000..0.60 V. - * 0b001..0.65 V. - * 0b010..0.70 V. - * 0b011..0.75 V. - * 0b100..0.80 V. - * 0b101..0.85 V. - * 0b110..0.90 V. - * 0b111..0.95 V. - */ -#define PMC_BODCORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_TRIGLVL_SHIFT)) & PMC_BODCORE_TRIGLVL_MASK) -#define PMC_BODCORE_HYST_MASK (0x30U) -#define PMC_BODCORE_HYST_SHIFT (4U) -/*! HYST - BoD Core Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODCORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_HYST_SHIFT)) & PMC_BODCORE_HYST_MASK) -/*! @} */ -/*! @name FRO1M - 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_FRO1M_FREQSEL_MASK (0x7FU) -#define PMC_FRO1M_FREQSEL_SHIFT (0U) -#define PMC_FRO1M_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_FREQSEL_SHIFT)) & PMC_FRO1M_FREQSEL_MASK) -#define PMC_FRO1M_ATBCTRL_MASK (0x180U) -#define PMC_FRO1M_ATBCTRL_SHIFT (7U) -#define PMC_FRO1M_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_ATBCTRL_SHIFT)) & PMC_FRO1M_ATBCTRL_MASK) -#define PMC_FRO1M_DIVSEL_MASK (0x3E00U) -#define PMC_FRO1M_DIVSEL_SHIFT (9U) -/*! DIVSEL - Divider selection bits. - * 0b00000..2.0. - * 0b00001..4.0. - * 0b00010..6.0. - * 0b00011..8.0. - * 0b00100..10.0. - * 0b00101..12.0. - * 0b00110..14.0. - * 0b00111..16.0. - * 0b01000..18.0. - * 0b01001..20.0. - * 0b01010..22.0. - * 0b01011..24.0. - * 0b01100..26.0. - * 0b01101..28.0. - * 0b01110..30.0. - * 0b01111..32.0. - * 0b10000..34.0. - * 0b10001..36.0. - * 0b10010..38.0. - * 0b10011..40.0. - * 0b10100..42.0. - * 0b10101..44.0. - * 0b10110..46.0. - * 0b10111..48.0. - * 0b11000..50.0. - * 0b11001..52.0. - * 0b11010..54.0. - * 0b11011..56.0. - * 0b11100..58.0. - * 0b11101..60.0. - * 0b11110..62.0. - * 0b11111..1.0. +#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) +#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) +/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . + * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. + * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. */ -#define PMC_FRO1M_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_DIVSEL_SHIFT)) & PMC_FRO1M_DIVSEL_MASK) -/*! @} */ +#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) -/*! @name FRO32K - 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_FRO32K_NTAT_MASK (0xEU) -#define PMC_FRO32K_NTAT_SHIFT (1U) -#define PMC_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_NTAT_SHIFT)) & PMC_FRO32K_NTAT_MASK) -#define PMC_FRO32K_PTAT_MASK (0x70U) -#define PMC_FRO32K_PTAT_SHIFT (4U) -#define PMC_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_PTAT_SHIFT)) & PMC_FRO32K_PTAT_MASK) -#define PMC_FRO32K_CAPCAL_MASK (0xFF80U) -#define PMC_FRO32K_CAPCAL_SHIFT (7U) -#define PMC_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_CAPCAL_SHIFT)) & PMC_FRO32K_CAPCAL_MASK) -#define PMC_FRO32K_ATBCTRL_MASK (0x30000U) -#define PMC_FRO32K_ATBCTRL_SHIFT (16U) -#define PMC_FRO32K_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_ATBCTRL_SHIFT)) & PMC_FRO32K_ATBCTRL_MASK) +#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) +#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) +/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . + * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. + * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. + */ +#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) /*! @} */ /*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ /*! @{ */ + #define PMC_XTAL32K_IREF_MASK (0x6U) #define PMC_XTAL32K_IREF_SHIFT (1U) +/*! IREF - reference output current selection inputs. + */ #define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) + #define PMC_XTAL32K_TEST_MASK (0x8U) #define PMC_XTAL32K_TEST_SHIFT (3U) +/*! TEST - Oscillator Test Mode. + */ #define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) + #define PMC_XTAL32K_IBIAS_MASK (0x30U) #define PMC_XTAL32K_IBIAS_SHIFT (4U) +/*! IBIAS - bias current selection inputs. + */ #define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) + #define PMC_XTAL32K_AMPL_MASK (0xC0U) #define PMC_XTAL32K_AMPL_SHIFT (6U) +/*! AMPL - oscillator amplitude selection inputs. + */ #define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) + #define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) #define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) +/*! CAPBANKIN - Capa bank setting input. + */ #define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) + #define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) #define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) +/*! CAPBANKOUT - Capa bank setting output. + */ #define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) + #define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) #define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) /*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. @@ -12612,12 +15040,19 @@ typedef struct { * 0b1..Sourced from calibration. */ #define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) + #define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) #define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) +/*! CAPTESTSTART - Start test. + */ #define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) + #define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) #define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) +/*! CAPTESTENABLE - Enable signal for cap test. + */ #define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) + #define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) #define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) /*! CAPTESTOSCINSEL - Select the input for test. @@ -12629,6 +15064,7 @@ typedef struct { /*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ + #define PMC_COMP_HYST_MASK (0x2U) #define PMC_COMP_HYST_SHIFT (1U) /*! HYST - Hysteris when hyst = '1'. @@ -12636,6 +15072,7 @@ typedef struct { * 0b1..Hysteresis is enable. */ #define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) + #define PMC_COMP_VREFINPUT_MASK (0x4U) #define PMC_COMP_VREFINPUT_SHIFT (2U) /*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). @@ -12643,6 +15080,7 @@ typedef struct { * 0b1..Select VDDA. */ #define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) + #define PMC_COMP_LOWPOWER_MASK (0x8U) #define PMC_COMP_LOWPOWER_SHIFT (3U) /*! LOWPOWER - Low power mode. @@ -12650,6 +15088,7 @@ typedef struct { * 0b1..Low power mode (Low speed). */ #define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) + #define PMC_COMP_PMUX_MASK (0x70U) #define PMC_COMP_PMUX_SHIFT (4U) /*! PMUX - Control word for P multiplexer:. @@ -12661,6 +15100,7 @@ typedef struct { * 0b101..Pin P2_23. */ #define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) + #define PMC_COMP_NMUX_MASK (0x380U) #define PMC_COMP_NMUX_SHIFT (7U) /*! NMUX - Control word for N multiplexer:. @@ -12672,22 +15112,133 @@ typedef struct { * 0b101..Pin P2_23. */ #define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) + #define PMC_COMP_VREF_MASK (0x7C00U) #define PMC_COMP_VREF_SHIFT (10U) +/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). + */ #define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) + #define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) #define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) +/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ #define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) + #define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) #define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) +/*! FILTERCGF_CLKDIV - Filter Clock divider. + * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. + * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. + * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. + * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. + * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. + * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. + * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. + * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. + */ #define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) -#define PMC_COMP_PMUXCAPT_MASK (0xE00000U) -#define PMC_COMP_PMUXCAPT_SHIFT (21U) -#define PMC_COMP_PMUXCAPT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUXCAPT_SHIFT)) & PMC_COMP_PMUXCAPT_MASK) +/*! @} */ + +/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) +/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) +/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) +/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) +/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) +/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) +/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) +/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) +/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK (0x100U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT (8U) +/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK (0x200U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT (9U) +/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK (0x400U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT (10U) +/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK (0x800U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT (11U) +/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK) /*! @} */ /*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ /*! @{ */ + #define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) #define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) /*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. @@ -12695,6 +15246,7 @@ typedef struct { * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. */ #define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) + #define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) #define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) /*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. @@ -12702,6 +15254,7 @@ typedef struct { * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. */ #define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) + #define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) #define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) /*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. @@ -12709,6 +15262,7 @@ typedef struct { * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. */ #define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) + #define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) #define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) /*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. @@ -12720,30 +15274,167 @@ typedef struct { /*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ /*! @{ */ + #define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) #define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) +/*! XTAL32KOK - XTAL oscillator 32 K OK signal. + */ #define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) -#define PMC_STATUSCLK_FRO1MCLKVALID_MASK (0x2U) -#define PMC_STATUSCLK_FRO1MCLKVALID_SHIFT (1U) -#define PMC_STATUSCLK_FRO1MCLKVALID(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_FRO1MCLKVALID_SHIFT)) & PMC_STATUSCLK_FRO1MCLKVALID_MASK) + #define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) #define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) /*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared.. - * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared.. + * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. + * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. */ #define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) /*! @} */ /*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ /*! @{ */ -#define PMC_AOREG1_DATA31_0_MASK (0xFFFFFFFFU) -#define PMC_AOREG1_DATA31_0_SHIFT (0U) -#define PMC_AOREG1_DATA31_0(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DATA31_0_SHIFT)) & PMC_AOREG1_DATA31_0_MASK) + +#define PMC_AOREG1_POR_MASK (0x10U) +#define PMC_AOREG1_POR_SHIFT (4U) +/*! POR - The last chip reset was caused by a Power On Reset. + */ +#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) + +#define PMC_AOREG1_PADRESET_MASK (0x20U) +#define PMC_AOREG1_PADRESET_SHIFT (5U) +/*! PADRESET - The last chip reset was caused by a Pin Reset. + */ +#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) + +#define PMC_AOREG1_BODRESET_MASK (0x40U) +#define PMC_AOREG1_BODRESET_SHIFT (6U) +/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. + */ +#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) + +#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) +#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) +/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. + */ +#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) + +#define PMC_AOREG1_WDTRESET_MASK (0x100U) +#define PMC_AOREG1_WDTRESET_SHIFT (8U) +/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. + */ +#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) + +#define PMC_AOREG1_SWRRESET_MASK (0x200U) +#define PMC_AOREG1_SWRRESET_SHIFT (9U) +/*! SWRRESET - The last chip reset was caused by a Software event. + */ +#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) + +#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) +#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) +/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) + +#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) +#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) +/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) + +#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) +#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) +/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) + +#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) +#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) +/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. + */ +#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) +/*! @} */ + +/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK (0x1U) +#define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT (0U) +/*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. + * 0b0..LDO DEEP Sleep uses Flash buffer biasing as reference. + * 0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference. + */ +#define PMC_MISCCTRL_LDODEEPSLEEPREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK) + +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK (0x2U) +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT (1U) +/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. + * 0b0..LDO MEM High Z mode is disabled. + * 0b1..LDO MEM High Z mode is enabled. + */ +#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK) + +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK (0x4U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT (2U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) + +#define PMC_MISCCTRL_MISCCTRL_3_8_MASK (0xF8U) +#define PMC_MISCCTRL_MISCCTRL_3_8_SHIFT (3U) +/*! MISCCTRL_3_8 - Reserved. + */ +#define PMC_MISCCTRL_MISCCTRL_3_8(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_8_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_8_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP0_MASK (0x100U) +#define PMC_MISCCTRL_MODEWAKEUP0_SHIFT (8U) +/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP0_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP0_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP1_MASK (0x200U) +#define PMC_MISCCTRL_MODEWAKEUP1_SHIFT (9U) +/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP1_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP1_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP2_MASK (0x400U) +#define PMC_MISCCTRL_MODEWAKEUP2_SHIFT (10U) +/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP2_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP2_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP3_MASK (0x800U) +#define PMC_MISCCTRL_MODEWAKEUP3_SHIFT (11U) +/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP3_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP3_MASK) + +#define PMC_MISCCTRL_DISABLE_BLEED_MASK (0x1000U) +#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT (12U) +/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the + * Low Power Software only in DEEP SLEEP low power mode. + * 0b0..LDO_MEM bleed current is enabled. + * 0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared + * after wake up from Deep SLeep low power mode. + */ +#define PMC_MISCCTRL_DISABLE_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK) + +#define PMC_MISCCTRL_MISCCTRL_13_14_MASK (0x6000U) +#define PMC_MISCCTRL_MISCCTRL_13_14_SHIFT (13U) +/*! MISCCTRL_13_14 - Reserved. + */ +#define PMC_MISCCTRL_MISCCTRL_13_14(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_14_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_14_MASK) + +#define PMC_MISCCTRL_WAKUPIO_RST_MASK (0x8000U) +#define PMC_MISCCTRL_WAKUPIO_RST_SHIFT (15U) +/*! WAKUPIO_RST - WAKEUP IO event detector reset control. + * 0b1..Wakeup IO is reset. + * 0b0..Wakeup IO is not reset. + */ +#define PMC_MISCCTRL_WAKUPIO_RST(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_WAKUPIO_RST_SHIFT)) & PMC_MISCCTRL_WAKUPIO_RST_MASK) /*! @} */ /*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ /*! @{ */ + #define PMC_RTCOSC32K_SEL_MASK (0x1U) #define PMC_RTCOSC32K_SEL_SHIFT (0U) /*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . @@ -12751,246 +15442,69 @@ typedef struct { * 0b1..XTAL 32KHz. */ #define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) + #define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) #define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) +/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. + */ #define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) + #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) +/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. + */ #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) + #define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) #define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) +/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. + */ #define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) + #define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) #define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) +/*! CLK1HZDIVHALT - Halts the divider counter. + */ #define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) + #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) +/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. + */ #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) /*! @} */ /*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ /*! @{ */ + #define PMC_OSTIMER_SOFTRESET_MASK (0x1U) #define PMC_OSTIMER_SOFTRESET_SHIFT (0U) +/*! SOFTRESET - Active high reset. + */ #define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) + #define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) #define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) +/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock. + */ #define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) + #define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) #define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) +/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). + */ #define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) + #define PMC_OSTIMER_OSC32KPD_MASK (0x8U) #define PMC_OSTIMER_OSC32KPD_SHIFT (3U) +/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. + */ #define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) /*! @} */ -/*! @name PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ -#define PMC_PDSLEEPCFG0_PDEN_DCDC_MASK (0x1U) -#define PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT (0U) -/*! PDEN_DCDC - Controls DCDC power during DEEP SLEEP (DCDC is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..DCDC is powered on during low power mode.. - * 0b1..DCDC is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_DCDC_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BIAS_MASK (0x2U) -#define PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT (1U) -/*! PDEN_BIAS - Controls Analog Bias power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Analog Bias is powered on during low power mode.. - * 0b1..Analog Bias is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BIAS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK (0x4U) -#define PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT (2U) -/*! PDEN_BODCORE - Controls Core Logic BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..BOD CORE is powered on during low power mode.. - * 0b1..BOD CORE is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK (0x8U) -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT (3U) -/*! PDEN_BODVBAT - Controls VBAT BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..BOD VBAT is powered on during low power mode.. - * 0b1..BOD VBAT is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK (0x10U) -#define PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT (4U) -/*! PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..FRO 1MHz is powered on during low power mode.. - * 0b1..FRO 1MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO1M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK (0x20U) -#define PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT (5U) -/*! PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP SLEEP (always shut down - * during POWER DOWN and DEEP POWER DOWN). - * 0b0..FRO 192 MHz is powered on during low power mode.. - * 0b1..FRO 192 MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..FRO 32 KHz is powered on during low power mode.. - * 0b1..FRO 32 KHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..crystal 32 KHz is powered on during low power mode.. - * 0b1..crystal 32 KHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK (0x100U) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls crystal 32 MHz power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..crystal 32 MHz is powered on during low power mode.. - * 0b1..crystal 32 MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP SLEEP (always shut down - * during POWER DOWN and DEEP POWER DOWN). - * 0b0..System PLL (also refered as PLL0) is powered on during low power mode.. - * 0b1..System PLL (also refered as PLL0) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP SLEEP (always shut down - * during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB PLL (also refered as PLL1) is powered on during low power mode.. - * 0b1..USB PLL (also refered as PLL1) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL1_MASK) -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB Full Speed phy is powered on during low power mode.. - * 0b1..USB Full Speed phy is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK) -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK (0x1000U) -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT (12U) -/*! PDEN_USBHSPHY - Controls USB High Speed Phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB High Speed Phy is powered on during low power mode.. - * 0b1..USB High Speed Phy is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK) -#define PMC_PDSLEEPCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls Analog Comparator power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Analog Comparator is powered on during low power mode.. - * 0b1..Analog Comparator is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_COMP_MASK) -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK (0x4000U) -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT (14U) -/*! PDEN_TEMPSENS - Controls Temperature Sensor power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..Temperature Sensor is powered on during low power mode.. - * 0b1..Temperature Sensor is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_GPADC_MASK (0x8000U) -#define PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT (15U) -/*! PDEN_GPADC - Controls General Purpose ADC (GPADC) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..General Purpose ADC (GPADC) is powered on during low power mode.. - * 0b1..General Purpose ADC (GPADC) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_GPADC_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK (0x10000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT (16U) -/*! PDEN_LDOMEM - Controls Memories LDO power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..Memories LDO is powered on during low power mode.. - * 0b1..Memories LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) -/*! PDEN_LDODEEPSLEEP - Controls Deep Sleep LDO power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Deep Sleep LDO is powered on during low power mode.. - * 0b1..Deep Sleep LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK (0x40000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT (18U) -/*! PDEN_LDOUSBHS - Controls USB high speed LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB high speed LDO is powered on during low power mode.. - * 0b1..USB high speed LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK (0x80000U) -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT (19U) -/*! PDEN_AUXBIAS - during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..is powered on during low power mode.. - * 0b1..is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK (0x100000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls crystal 32 MHz LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..crystal 32 MHz LDO is powered on during low power mode.. - * 0b1..crystal 32 MHz LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT (21U) -/*! PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..Flash NV (high voltage) is powered on during low power mode.. - * 0b1..Flash NV (high voltage) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK) -#define PMC_PDSLEEPCFG0_PDEN_RNG_MASK (0x400000U) -#define PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT (22U) -/*! PDEN_RNG - Controls True Random Number Genetaor (TRNG) clock sources power during DEEP SLEEP - * (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..True Random Number Genetaor (TRNG) clock sources are powered on during low power mode.. - * 0b1..True Random Number Genetaor (TRNG) clock sources are powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_RNG_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP SLEEP (PLL0 Spread - * Spectrum is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..PLL0 Spread Sprectrum module is powered on during low power mode.. - * 0b1..PLL0 Spread Sprectrum module is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK) -#define PMC_PDSLEEPCFG0_PDEN_ROM_MASK (0x1000000U) -#define PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT (24U) -/*! PDEN_ROM - Controls ROM power during DEEP SLEEP (ROM is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..ROM is powered on during low power mode.. - * 0b1..ROM is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_ROM_MASK) -/*! @} */ - /*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ -#define PMC_PDRUNCFG0_PDEN_DCDC_MASK (0x1U) -#define PMC_PDRUNCFG0_PDEN_DCDC_SHIFT (0U) -/*! PDEN_DCDC - Controls power to Bulk DCDC Converter. - * 0b0..DCDC is powered. - * 0b1..DCDC is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_DCDC_SHIFT)) & PMC_PDRUNCFG0_PDEN_DCDC_MASK) -#define PMC_PDRUNCFG0_PDEN_BIAS_MASK (0x2U) -#define PMC_PDRUNCFG0_PDEN_BIAS_SHIFT (1U) -/*! PDEN_BIAS - Controls power to . - * 0b0..Analog Bias is powered. - * 0b1..Analog Bias is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_BIAS_MASK) -#define PMC_PDRUNCFG0_PDEN_BODCORE_MASK (0x4U) -#define PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT (2U) -/*! PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD). - * 0b0..BOD CORE is powered. - * 0b1..BOD CORE is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODCORE_MASK) + #define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) #define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) /*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). @@ -12998,14 +15512,7 @@ typedef struct { * 0b1..BOD VBAT is powered down. */ #define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) -#define PMC_PDRUNCFG0_PDEN_FRO192M_MASK (0x20U) -#define PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT (5U) -/*! PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz - * and 96 MHz clocks are derived from this FRO. - * 0b0..FRO 192MHz is powered. - * 0b1..FRO 192MHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) + #define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) #define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) /*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. @@ -13013,6 +15520,7 @@ typedef struct { * 0b1..FRO32KHz is powered down. */ #define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) + #define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) #define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) /*! PDEN_XTAL32K - Controls power to crystal 32 KHz. @@ -13020,13 +15528,15 @@ typedef struct { * 0b1..Crystal 32KHz is powered down. */ #define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) + #define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) #define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls power to crystal 32 MHz. - * 0b0..Crystal 32MHz is powered. - * 0b1..Crystal 32MHz is powered down. +/*! PDEN_XTAL32M - Controls power to high speed crystal. + * 0b0..High speed crystal is powered. + * 0b1..High speed crystal is powered down. */ #define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) + #define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) #define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) /*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). @@ -13034,6 +15544,7 @@ typedef struct { * 0b1..PLL0 is powered down. */ #define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) + #define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) #define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) /*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). @@ -13041,6 +15552,7 @@ typedef struct { * 0b1..PLL1 is powered down. */ #define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) + #define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) #define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) /*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. @@ -13048,6 +15560,7 @@ typedef struct { * 0b1..USB Full Speed phy is powered down. */ #define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) + #define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) #define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) /*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. @@ -13055,6 +15568,7 @@ typedef struct { * 0b1..USB HS phy is powered down. */ #define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) + #define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) #define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) /*! PDEN_COMP - Controls power to Analog Comparator. @@ -13062,34 +15576,7 @@ typedef struct { * 0b1..Analog Comparator is powered down. */ #define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) -#define PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK (0x4000U) -#define PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT (14U) -/*! PDEN_TEMPSENS - Controls power to Temperature Sensor. - * 0b0..Temperature Sensor is powered. - * 0b1..Temperature Sensor is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK) -#define PMC_PDRUNCFG0_PDEN_GPADC_MASK (0x8000U) -#define PMC_PDRUNCFG0_PDEN_GPADC_SHIFT (15U) -/*! PDEN_GPADC - Controls power to General Purpose ADC (GPADC). - * 0b0..GPADC is powered. - * 0b1..GPADC is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_GPADC_SHIFT)) & PMC_PDRUNCFG0_PDEN_GPADC_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOMEM_MASK (0x10000U) -#define PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT (16U) -/*! PDEN_LDOMEM - Controls power to Memories LDO. - * 0b0..Memories LDO is powered. - * 0b1..Memories LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOMEM_MASK) -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) -/*! PDEN_LDODEEPSLEEP - Controls power to Deep Sleep LDO. - * 0b0..Deep Sleep LDO is powered. - * 0b1..Deep Sleep LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK) + #define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) #define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) /*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. @@ -13097,6 +15584,7 @@ typedef struct { * 0b1..USB high speed LDO is powered down. */ #define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) + #define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) #define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) /*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) @@ -13104,20 +15592,15 @@ typedef struct { * 0b1..auxiliary biasing is powered down. */ #define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) + #define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) #define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO. - * 0b0..crystal 32 MHz LDO is powered. - * 0b1..crystal 32 MHz LDO is powered down. +/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO. + * 0b0..High speed crystal LDO is powered. + * 0b1..High speed crystal LDO is powered down. */ #define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT (21U) -/*! PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO. - * 0b0..Flash NV LDO is powered. - * 0b1..Flash NV LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK) + #define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) #define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) /*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. @@ -13125,6 +15608,7 @@ typedef struct { * 0b1..TRNG clocks are powered down. */ #define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) + #define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) #define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) /*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. @@ -13136,18 +15620,56 @@ typedef struct { /*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ + #define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) #define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) +/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ #define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) /*! @} */ /*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ + #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) +/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) /*! @} */ +/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ + +#define PMC_SRAMCTRL_SMB_MASK (0x3U) +#define PMC_SRAMCTRL_SMB_SHIFT (0U) +/*! SMB - Source Biasing voltage. + * 0b00..Low leakage. + * 0b01..Medium leakage. + * 0b10..Highest leakage. + * 0b11..Disable. + */ +#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) + +#define PMC_SRAMCTRL_RM_MASK (0x1CU) +#define PMC_SRAMCTRL_RM_SHIFT (2U) +/*! RM - Read Margin control settings. + */ +#define PMC_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK) + +#define PMC_SRAMCTRL_WM_MASK (0xE0U) +#define PMC_SRAMCTRL_WM_SHIFT (5U) +/*! WM - Write Margin control settings. + */ +#define PMC_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK) + +#define PMC_SRAMCTRL_WRME_MASK (0x100U) +#define PMC_SRAMCTRL_WRME_SHIFT (8U) +/*! WRME - Write read margin enable. + */ +#define PMC_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK) +/*! @} */ + /*! * @} @@ -13155,7 +15677,7 @@ typedef struct { /* PMC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral PMC base address */ #define PMC_BASE (0x50020000u) /** Peripheral PMC base address */ @@ -13237,229 +15759,375 @@ typedef struct { /*! @name OUTBASE - Base address register for output region */ /*! @{ */ + #define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) +/*! outbase - Base address register for the output region + */ #define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) /*! @} */ /*! @name OUTFORMAT - Output format */ /*! @{ */ + #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) +/*! out_formatint - Output Internal format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) + #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) +/*! out_formatext - Output External format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) + #define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) #define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) +/*! out_scaler - Output Scaler value (for scaled 'q31' formats) + */ #define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) /*! @} */ /*! @name TMPBASE - Base address register for temp region */ /*! @{ */ + #define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) +/*! tmpbase - Base address register for the temporary region + */ #define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) /*! @} */ /*! @name TMPFORMAT - Temp format */ /*! @{ */ + #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) +/*! tmp_formatint - Temp Internal format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) + #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) +/*! tmp_formatext - Temp External format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) + #define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) #define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) +/*! tmp_scaler - Temp Scaler value (for scaled 'q31' formats) + */ #define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) /*! @} */ /*! @name INABASE - Base address register for input A region */ /*! @{ */ + #define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) #define POWERQUAD_INABASE_INABASE_SHIFT (0U) +/*! inabase - Base address register for the input A region + */ #define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) /*! @} */ /*! @name INAFORMAT - Input A format */ /*! @{ */ + #define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) #define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) +/*! ina_formatint - Input A Internal format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) + #define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) #define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) +/*! ina_formatext - Input A External format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) + #define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) #define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) +/*! ina_scaler - Input A Scaler value (for scaled 'q31' formats) + */ #define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) /*! @} */ /*! @name INBBASE - Base address register for input B region */ /*! @{ */ + #define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) +/*! inbbase - Base address register for the input B region + */ #define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) /*! @} */ /*! @name INBFORMAT - Input B format */ /*! @{ */ + #define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) #define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) +/*! inb_formatint - Input B Internal format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) + #define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) #define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) +/*! inb_formatext - Input B External format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) + #define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) #define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) +/*! inb_scaler - Input B Scaler value (for scaled 'q31' formats) + */ #define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) /*! @} */ /*! @name CONTROL - PowerQuad Control register */ /*! @{ */ + #define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) #define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) +/*! decode_opcode - opcode specific to decode_machine + */ #define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) + #define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) #define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) +/*! decode_machine - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA + */ #define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) + #define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) #define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) +/*! inst_busy - Instruction busy signal when high indicates processing is on + */ #define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) /*! @} */ /*! @name LENGTH - Length register */ /*! @{ */ + #define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) #define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) +/*! inst_length - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = + * inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = + * inst_length[20:16] + */ #define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) /*! @} */ /*! @name CPPRE - Pre-scale register */ /*! @{ */ + #define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) #define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) +/*! cppre_in - co-processor scaling of input + */ #define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) + #define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) #define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) +/*! cppre_out - co-processor fixed point output + */ #define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) + #define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) #define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) +/*! cppre_sat - 1 : forces sub-32 bit saturation + */ #define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) + #define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) #define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) +/*! cppre_sat8 - 0 = 8bits, 1 = 16bits + */ #define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) /*! @} */ /*! @name MISC - Misc register */ /*! @{ */ + #define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) #define POWERQUAD_MISC_INST_MISC_SHIFT (0U) +/*! inst_misc - Misc register. For Matrix : Used for scale factor + */ #define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) /*! @} */ /*! @name CURSORY - Cursory register */ /*! @{ */ + #define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) #define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) +/*! cursory - 1 : Enable cursory mode + */ #define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) /*! @} */ /*! @name CORDIC_X - Cordic input X register */ /*! @{ */ + #define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) +/*! cordic_x - Cordic input x + */ #define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) /*! @} */ /*! @name CORDIC_Y - Cordic input Y register */ /*! @{ */ + #define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) +/*! cordic_y - Cordic input y + */ #define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) /*! @} */ /*! @name CORDIC_Z - Cordic input Z register */ /*! @{ */ + #define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) +/*! cordic_z - Cordic input z + */ #define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) /*! @} */ /*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ /*! @{ */ + #define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) #define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) +/*! OVERFLOW - overflow + */ #define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) + #define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) #define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) +/*! NAN - nan + */ #define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) + #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) +/*! FIXEDOVERFLOW - fixed_pt_overflow + */ #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) + #define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) #define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) +/*! UNDERFLOW - underflow + */ #define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) + #define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) #define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) +/*! BUSERROR - bus_error + */ #define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) /*! @} */ /*! @name INTREN - INTERRUPT enable register */ /*! @{ */ + #define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) #define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) +/*! intr_oflow - 1 : Enable interrupt on Floating point overflow + */ #define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) + #define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) #define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) +/*! intr_nan - 1 : Enable interrupt on Floating point NaN + */ #define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) + #define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) #define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) +/*! intr_fixed - 1: Enable interrupt on Fixed point Overflow + */ #define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) + #define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) #define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) +/*! intr_uflow - 1 : Enable interrupt on Subnormal truncation + */ #define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) + #define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) #define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) +/*! intr_berr - 1: Enable interrupt on AHBM Buss Error + */ #define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) + #define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) #define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) +/*! intr_comp - 1: Enable interrupt on instruction completion + */ #define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) /*! @} */ /*! @name EVENTEN - Event Enable register */ /*! @{ */ + #define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) #define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) +/*! event_oflow - 1 : Enable event trigger on Floating point overflow + */ #define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) + #define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) #define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) +/*! event_nan - 1 : Enable event trigger on Floating point NaN + */ #define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) + #define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) #define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) +/*! event_fixed - 1: Enable event trigger on Fixed point Overflow + */ #define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) + #define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) #define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) +/*! event_uflow - 1 : Enable event trigger on Subnormal truncation + */ #define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) + #define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) #define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) +/*! event_berr - 1: Enable event trigger on AHBM Buss Error + */ #define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) + #define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) #define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) +/*! event_comp - 1: Enable event trigger on instruction completion + */ #define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) /*! @} */ /*! @name INTRSTAT - INTERRUPT STATUS register */ /*! @{ */ + #define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) #define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) +/*! intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit + */ #define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) /*! @} */ /*! @name GPREG - General purpose register bank N. */ /*! @{ */ + #define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) #define POWERQUAD_GPREG_GPREG_SHIFT (0U) +/*! gpreg - General purpose register bank + */ #define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) /*! @} */ @@ -13468,8 +16136,11 @@ typedef struct { /*! @name COMPREGS_COMPREG - Compute register bank */ /*! @{ */ + #define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) #define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) +/*! compreg - Compute register bank + */ #define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) /*! @} */ @@ -13483,7 +16154,7 @@ typedef struct { /* POWERQUAD - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral POWERQUAD base address */ #define POWERQUAD_BASE (0x500A6000u) /** Peripheral POWERQUAD base address */ @@ -13556,31 +16227,39 @@ typedef struct { /*! @name ENC_ENABLE - Encryption Enable register */ /*! @{ */ + #define PRINCE_ENC_ENABLE_EN_MASK (0x1U) #define PRINCE_ENC_ENABLE_EN_SHIFT (0U) /*! EN - Encryption Enable. - * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled.. - * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled.. + * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. + * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. */ #define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) /*! @} */ /*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ /*! @{ */ + #define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) #define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. + */ #define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) /*! @} */ /*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ /*! @{ */ + #define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) #define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. + */ #define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) /*! @} */ /*! @name LOCK - Lock register */ /*! @{ */ + #define PRINCE_LOCK_LOCKREG0_MASK (0x1U) #define PRINCE_LOCK_LOCKREG0_SHIFT (0U) /*! LOCKREG0 - Lock Region 0 registers. @@ -13588,6 +16267,7 @@ typedef struct { * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. */ #define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) + #define PRINCE_LOCK_LOCKREG1_MASK (0x2U) #define PRINCE_LOCK_LOCKREG1_SHIFT (1U) /*! LOCKREG1 - Lock Region 1 registers. @@ -13595,6 +16275,7 @@ typedef struct { * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. */ #define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) + #define PRINCE_LOCK_LOCKREG2_MASK (0x4U) #define PRINCE_LOCK_LOCKREG2_SHIFT (2U) /*! LOCKREG2 - Lock Region 2 registers. @@ -13602,6 +16283,7 @@ typedef struct { * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. */ #define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) + #define PRINCE_LOCK_LOCKMASK_MASK (0x100U) #define PRINCE_LOCK_LOCKMASK_SHIFT (8U) /*! LOCKMASK - Lock the Mask registers. @@ -13613,94 +16295,139 @@ typedef struct { /*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ /*! @{ */ + #define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) /*! @} */ /*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ /*! @{ */ + #define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) /*! @} */ /*! @name BASE_ADDR0 - Base Address for region 0 register */ /*! @{ */ + #define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) #define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 0. + */ #define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) + #define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) #define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 0. + */ #define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) /*! @} */ /*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ /*! @{ */ + #define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) #define PRINCE_SR_ENABLE0_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. + */ #define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) /*! @} */ /*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ /*! @{ */ + #define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) /*! @} */ /*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ /*! @{ */ + #define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) /*! @} */ /*! @name BASE_ADDR1 - Base Address for region 1 register */ /*! @{ */ + #define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) #define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 1. + */ #define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) + #define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) #define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 1. + */ #define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) /*! @} */ /*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ /*! @{ */ + #define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) #define PRINCE_SR_ENABLE1_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. + */ #define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) /*! @} */ /*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ /*! @{ */ + #define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) /*! @} */ /*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ /*! @{ */ + #define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) /*! @} */ /*! @name BASE_ADDR2 - Base Address for region 2 register */ /*! @{ */ + #define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) #define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 2. + */ #define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) + #define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) #define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 2. + */ #define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) /*! @} */ /*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ /*! @{ */ + #define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) #define PRINCE_SR_ENABLE2_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. + */ #define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) /*! @} */ @@ -13711,7 +16438,7 @@ typedef struct { /* PRINCE - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral PRINCE base address */ #define PRINCE_BASE (0x50035000u) /** Peripheral PRINCE base address */ @@ -13801,309 +16528,539 @@ typedef struct { /*! @name CTRL - PUF Control register */ /*! @{ */ + #define PUF_CTRL_ZEROIZE_MASK (0x1U) #define PUF_CTRL_ZEROIZE_SHIFT (0U) +/*! zeroize - Begin Zeroize operation for PUF and go to Error state + */ #define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) + #define PUF_CTRL_ENROLL_MASK (0x2U) #define PUF_CTRL_ENROLL_SHIFT (1U) +/*! enroll - Begin Enroll operation + */ #define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) + #define PUF_CTRL_START_MASK (0x4U) #define PUF_CTRL_START_SHIFT (2U) +/*! start - Begin Start operation + */ #define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) + #define PUF_CTRL_GENERATEKEY_MASK (0x8U) #define PUF_CTRL_GENERATEKEY_SHIFT (3U) +/*! GENERATEKEY - Begin Set Intrinsic Key operation + */ #define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) + #define PUF_CTRL_SETKEY_MASK (0x10U) #define PUF_CTRL_SETKEY_SHIFT (4U) +/*! SETKEY - Begin Set User Key operation + */ #define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) + #define PUF_CTRL_GETKEY_MASK (0x40U) #define PUF_CTRL_GETKEY_SHIFT (6U) +/*! GETKEY - Begin Get Key operation + */ #define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) /*! @} */ /*! @name KEYINDEX - PUF Key Index register */ /*! @{ */ + #define PUF_KEYINDEX_KEYIDX_MASK (0xFU) #define PUF_KEYINDEX_KEYIDX_SHIFT (0U) +/*! KEYIDX - Key index for Set Key operations + */ #define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) /*! @} */ /*! @name KEYSIZE - PUF Key Size register */ /*! @{ */ + #define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) #define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) +/*! KEYSIZE - Key size for Set Key operations + */ #define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) /*! @} */ /*! @name STAT - PUF Status register */ /*! @{ */ + #define PUF_STAT_BUSY_MASK (0x1U) #define PUF_STAT_BUSY_SHIFT (0U) +/*! busy - Indicates that operation is in progress + */ #define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) + #define PUF_STAT_SUCCESS_MASK (0x2U) #define PUF_STAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Last operation was successful + */ #define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) + #define PUF_STAT_ERROR_MASK (0x4U) #define PUF_STAT_ERROR_SHIFT (2U) +/*! error - PUF is in the Error state and no operations can be performed + */ #define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) + #define PUF_STAT_KEYINREQ_MASK (0x10U) #define PUF_STAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Request for next part of key + */ #define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) + #define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) #define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Next part of key is available + */ #define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) + #define PUF_STAT_CODEINREQ_MASK (0x40U) #define PUF_STAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Request for next part of AC/KC + */ #define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) + #define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) #define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Next part of AC/KC is available + */ #define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) /*! @} */ /*! @name ALLOW - PUF Allow register */ /*! @{ */ + #define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) #define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) +/*! ALLOWENROLL - Enroll operation is allowed + */ #define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) + #define PUF_ALLOW_ALLOWSTART_MASK (0x2U) #define PUF_ALLOW_ALLOWSTART_SHIFT (1U) +/*! ALLOWSTART - Start operation is allowed + */ #define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) + #define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) #define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) +/*! ALLOWSETKEY - Set Key operations are allowed + */ #define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) + #define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) #define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) +/*! ALLOWGETKEY - Get Key operation is allowed + */ #define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) /*! @} */ /*! @name KEYINPUT - PUF Key Input register */ /*! @{ */ + #define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) #define PUF_KEYINPUT_KEYIN_SHIFT (0U) +/*! KEYIN - Key input data + */ #define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) /*! @} */ /*! @name CODEINPUT - PUF Code Input register */ /*! @{ */ + #define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) #define PUF_CODEINPUT_CODEIN_SHIFT (0U) +/*! CODEIN - AC/KC input data + */ #define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) /*! @} */ /*! @name CODEOUTPUT - PUF Code Output register */ /*! @{ */ + #define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) #define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) +/*! CODEOUT - AC/KC output data + */ #define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) /*! @} */ /*! @name KEYOUTINDEX - PUF Key Output Index register */ /*! @{ */ + #define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) #define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) +/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register + */ #define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) /*! @} */ /*! @name KEYOUTPUT - PUF Key Output register */ /*! @{ */ + #define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) #define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) +/*! KEYOUT - Key output data + */ #define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) /*! @} */ /*! @name IFSTAT - PUF Interface Status and clear register */ /*! @{ */ + #define PUF_IFSTAT_ERROR_MASK (0x1U) #define PUF_IFSTAT_ERROR_SHIFT (0U) +/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit + */ #define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) /*! @} */ /*! @name VERSION - PUF version register. */ /*! @{ */ -#define PUF_VERSION_KEYOUT_MASK (0xFFFFFFFFU) -#define PUF_VERSION_KEYOUT_SHIFT (0U) -#define PUF_VERSION_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_KEYOUT_SHIFT)) & PUF_VERSION_KEYOUT_MASK) + +#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU) +#define PUF_VERSION_VERSION_SHIFT (0U) +/*! VERSION - Version of the PUF module. + */ +#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK) /*! @} */ /*! @name INTEN - PUF Interrupt Enable */ /*! @{ */ + #define PUF_INTEN_READYEN_MASK (0x1U) #define PUF_INTEN_READYEN_SHIFT (0U) +/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) + #define PUF_INTEN_SUCCESEN_MASK (0x2U) #define PUF_INTEN_SUCCESEN_SHIFT (1U) +/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) + #define PUF_INTEN_ERROREN_MASK (0x4U) #define PUF_INTEN_ERROREN_SHIFT (2U) +/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) + #define PUF_INTEN_KEYINREQEN_MASK (0x10U) #define PUF_INTEN_KEYINREQEN_SHIFT (4U) +/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) + #define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) #define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) +/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) + #define PUF_INTEN_CODEINREQEN_MASK (0x40U) #define PUF_INTEN_CODEINREQEN_SHIFT (6U) +/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) + #define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) #define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) +/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) /*! @} */ /*! @name INTSTAT - PUF interrupt status */ /*! @{ */ + #define PUF_INTSTAT_READY_MASK (0x1U) #define PUF_INTSTAT_READY_SHIFT (0U) +/*! READY - Triggers on falling edge of busy, write 1 to clear + */ #define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) + #define PUF_INTSTAT_SUCCESS_MASK (0x2U) #define PUF_INTSTAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) + #define PUF_INTSTAT_ERROR_MASK (0x4U) #define PUF_INTSTAT_ERROR_SHIFT (2U) +/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) + #define PUF_INTSTAT_KEYINREQ_MASK (0x10U) #define PUF_INTSTAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) + #define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) #define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) + #define PUF_INTSTAT_CODEINREQ_MASK (0x40U) #define PUF_INTSTAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) + #define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) #define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) /*! @} */ /*! @name PWRCTRL - PUF RAM Power Control */ /*! @{ */ + #define PUF_PWRCTRL_RAMON_MASK (0x1U) #define PUF_PWRCTRL_RAMON_SHIFT (0U) +/*! RAMON - Power on the PUF RAM. + */ #define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) + #define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) #define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) +/*! RAMSTAT - PUF RAM status. + */ #define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) /*! @} */ /*! @name CFG - PUF config register for block bits */ /*! @{ */ + #define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) #define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) +/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. + */ #define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) + #define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) #define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) +/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. + */ #define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) /*! @} */ /*! @name KEYLOCK - Only reset in case of full IC reset */ /*! @{ */ + #define PUF_KEYLOCK_KEY0_MASK (0x3U) #define PUF_KEYLOCK_KEY0_SHIFT (0U) +/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, + * 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ #define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) + #define PUF_KEYLOCK_KEY1_MASK (0xCU) #define PUF_KEYLOCK_KEY1_SHIFT (2U) +/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, + * 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ #define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) + #define PUF_KEYLOCK_KEY2_MASK (0x30U) #define PUF_KEYLOCK_KEY2_SHIFT (4U) +/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, + * 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ #define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) + #define PUF_KEYLOCK_KEY3_MASK (0xC0U) #define PUF_KEYLOCK_KEY3_SHIFT (6U) +/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, + * 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ #define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) /*! @} */ /*! @name KEYENABLE - */ /*! @{ */ + #define PUF_KEYENABLE_KEY0_MASK (0x3U) #define PUF_KEYENABLE_KEY0_SHIFT (0U) +/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." + */ #define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) + #define PUF_KEYENABLE_KEY1_MASK (0xCU) #define PUF_KEYENABLE_KEY1_SHIFT (2U) +/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." + */ #define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) + #define PUF_KEYENABLE_KEY2_MASK (0x30U) #define PUF_KEYENABLE_KEY2_SHIFT (4U) +/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." + */ #define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) + #define PUF_KEYENABLE_KEY3_MASK (0xC0U) #define PUF_KEYENABLE_KEY3_SHIFT (6U) +/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." + */ #define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) /*! @} */ /*! @name KEYRESET - Reinitialize Keys shift registers counters */ /*! @{ */ + #define PUF_KEYRESET_KEY0_MASK (0x3U) #define PUF_KEYRESET_KEY0_SHIFT (0U) +/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. + */ #define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) + #define PUF_KEYRESET_KEY1_MASK (0xCU) #define PUF_KEYRESET_KEY1_SHIFT (2U) +/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. + */ #define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) + #define PUF_KEYRESET_KEY2_MASK (0x30U) #define PUF_KEYRESET_KEY2_SHIFT (4U) +/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. + */ #define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) + #define PUF_KEYRESET_KEY3_MASK (0xC0U) #define PUF_KEYRESET_KEY3_SHIFT (6U) +/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. + */ #define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) /*! @} */ /*! @name IDXBLK_L - */ /*! @{ */ -#define PUF_IDXBLK_L_IDX0_MASK (0x3U) -#define PUF_IDXBLK_L_IDX0_SHIFT (0U) -#define PUF_IDXBLK_L_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX0_SHIFT)) & PUF_IDXBLK_L_IDX0_MASK) + #define PUF_IDXBLK_L_IDX1_MASK (0xCU) #define PUF_IDXBLK_L_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 + */ #define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) + #define PUF_IDXBLK_L_IDX2_MASK (0x30U) #define PUF_IDXBLK_L_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 + */ #define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) + #define PUF_IDXBLK_L_IDX3_MASK (0xC0U) #define PUF_IDXBLK_L_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 + */ #define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) + #define PUF_IDXBLK_L_IDX4_MASK (0x300U) #define PUF_IDXBLK_L_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 + */ #define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) + #define PUF_IDXBLK_L_IDX5_MASK (0xC00U) #define PUF_IDXBLK_L_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 + */ #define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) + #define PUF_IDXBLK_L_IDX6_MASK (0x3000U) #define PUF_IDXBLK_L_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 + */ #define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) + #define PUF_IDXBLK_L_IDX7_MASK (0xC000U) #define PUF_IDXBLK_L_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 + */ #define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) + #define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) #define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) +/*! LOCK_IDX - Lock 0 to 7 PUF key indexes + */ #define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) /*! @} */ /*! @name IDXBLK_H_DP - */ /*! @{ */ + #define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) #define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) +/*! IDX8 - Use to block PUF index 8 + */ #define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) + #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) #define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) +/*! IDX9 - Use to block PUF index 9 + */ #define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) + #define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) #define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) +/*! IDX10 - Use to block PUF index 10 + */ #define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) + #define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) #define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) +/*! IDX11 - Use to block PUF index 11 + */ #define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) + #define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) #define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) +/*! IDX12 - Use to block PUF index 12 + */ #define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) + #define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) #define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) +/*! IDX13 - Use to block PUF index 13 + */ #define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) + #define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) #define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) +/*! IDX14 - Use to block PUF index 14 + */ #define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) + #define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) #define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) +/*! IDX15 - Use to block PUF index 15 + */ #define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) /*! @} */ /*! @name KEYMASK - Only reset in case of full IC reset */ /*! @{ */ + #define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) #define PUF_KEYMASK_KEYMASK_SHIFT (0U) #define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) @@ -14114,76 +17071,133 @@ typedef struct { /*! @name IDXBLK_H - */ /*! @{ */ + #define PUF_IDXBLK_H_IDX8_MASK (0x3U) #define PUF_IDXBLK_H_IDX8_SHIFT (0U) +/*! IDX8 - Use to block PUF index 8 + */ #define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) + #define PUF_IDXBLK_H_IDX9_MASK (0xCU) #define PUF_IDXBLK_H_IDX9_SHIFT (2U) +/*! IDX9 - Use to block PUF index 9 + */ #define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) + #define PUF_IDXBLK_H_IDX10_MASK (0x30U) #define PUF_IDXBLK_H_IDX10_SHIFT (4U) +/*! IDX10 - Use to block PUF index 10 + */ #define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) + #define PUF_IDXBLK_H_IDX11_MASK (0xC0U) #define PUF_IDXBLK_H_IDX11_SHIFT (6U) +/*! IDX11 - Use to block PUF index 11 + */ #define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) + #define PUF_IDXBLK_H_IDX12_MASK (0x300U) #define PUF_IDXBLK_H_IDX12_SHIFT (8U) +/*! IDX12 - Use to block PUF index 12 + */ #define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) + #define PUF_IDXBLK_H_IDX13_MASK (0xC00U) #define PUF_IDXBLK_H_IDX13_SHIFT (10U) +/*! IDX13 - Use to block PUF index 13 + */ #define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) + #define PUF_IDXBLK_H_IDX14_MASK (0x3000U) #define PUF_IDXBLK_H_IDX14_SHIFT (12U) +/*! IDX14 - Use to block PUF index 14 + */ #define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) + #define PUF_IDXBLK_H_IDX15_MASK (0xC000U) #define PUF_IDXBLK_H_IDX15_SHIFT (14U) +/*! IDX15 - Use to block PUF index 15 + */ #define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) + #define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) #define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) +/*! LOCK_IDX - Lock 8 to 15 PUF key indexes + */ #define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) /*! @} */ /*! @name IDXBLK_L_DP - */ /*! @{ */ -#define PUF_IDXBLK_L_DP_IDX0_MASK (0x3U) -#define PUF_IDXBLK_L_DP_IDX0_SHIFT (0U) -#define PUF_IDXBLK_L_DP_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX0_SHIFT)) & PUF_IDXBLK_L_DP_IDX0_MASK) + #define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) #define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 + */ #define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) + #define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) #define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 + */ #define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) + #define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) #define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 + */ #define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) + #define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) #define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 + */ #define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) + #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) #define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 + */ #define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) + #define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) #define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 + */ #define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) + #define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) #define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 + */ #define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) /*! @} */ /*! @name SHIFT_STATUS - */ /*! @{ */ + #define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) #define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) +/*! KEY0 - Index counter from key 0 shift register + */ #define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) + #define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) #define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) +/*! KEY1 - Index counter from key 1 shift register + */ #define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) + #define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) #define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) +/*! KEY2 - Index counter from key 2 shift register + */ #define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) + #define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) #define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) +/*! KEY3 - Index counter from key 3 shift register + */ #define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) /*! @} */ @@ -14194,7 +17208,7 @@ typedef struct { /* PUF - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral PUF base address */ #define PUF_BASE (0x5003B000u) /** Peripheral PUF base address */ @@ -14241,15 +17255,12 @@ typedef struct { /** RNG - Register Layout Typedef */ typedef struct { __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ - __I uint32_t ENCRYPTED_NUMBER; /**< This register contains a random 32 bit number which is pre-computed, offset: 0x4 */ + uint8_t RESERVED_0[4]; __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ - __IO uint32_t MISC_CFG; /**< , offset: 0x18 */ - uint8_t RESERVED_0[4056]; - __IO uint32_t POWERDOWN; /**< Powerdown mode (standard but certainly useless here), offset: 0xFF4 */ - uint8_t RESERVED_1[4]; + uint8_t RESERVED_1[4068]; __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ } RNG_Type; @@ -14264,106 +17275,119 @@ typedef struct { /*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ /*! @{ */ + #define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) #define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) +/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. + */ #define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) /*! @} */ -/*! @name ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed */ -/*! @{ */ -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT (0U) -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT)) & RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK) -/*! @} */ - /*! @name COUNTER_VAL - */ /*! @{ */ + #define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) #define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) +/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock + * frequency for evaluation and certification purposes. + */ #define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) + #define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) #define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) +/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. + */ #define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) /*! @} */ /*! @name COUNTER_CFG - */ /*! @{ */ + #define RNG_COUNTER_CFG_MODE_MASK (0x3U) #define RNG_COUNTER_CFG_MODE_SHIFT (0U) +/*! MODE - 00: disabled 01: update once. + */ #define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) + #define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) #define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) +/*! CLOCK_SEL - Selects the internal clock on which to compute statistics. + */ #define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) + #define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) #define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) +/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. + */ #define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK (0x100U) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT (8U) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT)) & RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK (0x200U) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT (9U) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT)) & RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK) /*! @} */ /*! @name ONLINE_TEST_CFG - */ /*! @{ */ + #define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) #define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) +/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. + */ #define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) + #define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) #define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) +/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one + * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: + * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this + * field. + */ #define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) /*! @} */ /*! @name ONLINE_TEST_VAL - */ /*! @{ */ + #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) +/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. + */ #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) + #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) +/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. + */ #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) + #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) +/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. + */ #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) /*! @} */ -/*! @name MISC_CFG - */ -/*! @{ */ -#define RNG_MISC_CFG_AES_RESEED_MASK (0x1U) -#define RNG_MISC_CFG_AES_RESEED_SHIFT (0U) -#define RNG_MISC_CFG_AES_RESEED(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_RESEED_SHIFT)) & RNG_MISC_CFG_AES_RESEED_MASK) -#define RNG_MISC_CFG_AES_DT_CFG_MASK (0x2U) -#define RNG_MISC_CFG_AES_DT_CFG_SHIFT (1U) -#define RNG_MISC_CFG_AES_DT_CFG(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_DT_CFG_SHIFT)) & RNG_MISC_CFG_AES_DT_CFG_MASK) -/*! @} */ - -/*! @name POWERDOWN - Powerdown mode (standard but certainly useless here) */ -/*! @{ */ -#define RNG_POWERDOWN_SOFT_RESET_MASK (0x1U) -#define RNG_POWERDOWN_SOFT_RESET_SHIFT (0U) -#define RNG_POWERDOWN_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_SOFT_RESET_MASK) -#define RNG_POWERDOWN_FORCE_SOFT_RESET_MASK (0x2U) -#define RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT (1U) -#define RNG_POWERDOWN_FORCE_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_FORCE_SOFT_RESET_MASK) -#define RNG_POWERDOWN_POWERDOWN_MASK (0x80000000U) -#define RNG_POWERDOWN_POWERDOWN_SHIFT (31U) -#define RNG_POWERDOWN_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_POWERDOWN_SHIFT)) & RNG_POWERDOWN_POWERDOWN_MASK) -/*! @} */ - /*! @name MODULEID - IP identifier */ /*! @{ */ + #define RNG_MODULEID_APERTURE_MASK (0xFFU) #define RNG_MODULEID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. + */ #define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) + #define RNG_MODULEID_MIN_REV_MASK (0xF00U) #define RNG_MODULEID_MIN_REV_SHIFT (8U) +/*! MIN_REV - Minor revision i. + */ #define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) + #define RNG_MODULEID_MAJ_REV_MASK (0xF000U) #define RNG_MODULEID_MAJ_REV_SHIFT (12U) +/*! MAJ_REV - Major revision i. + */ #define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) + #define RNG_MODULEID_ID_MASK (0xFFFF0000U) #define RNG_MODULEID_ID_SHIFT (16U) +/*! ID - Identifier. + */ #define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) /*! @} */ @@ -14374,7 +17398,7 @@ typedef struct { /* RNG - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral RNG base address */ #define RNG_BASE (0x5003A000u) /** Peripheral RNG base address */ @@ -14422,7 +17446,7 @@ typedef struct { __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ - __I uint32_t SUBSEC; /**< RTC Sub-second Counter register, offset: 0x10 */ + __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ uint8_t RESERVED_0[44]; __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ } RTC_Type; @@ -14438,6 +17462,7 @@ typedef struct { /*! @name CTRL - RTC control register */ /*! @{ */ + #define RTC_CTRL_SWRESET_MASK (0x1U) #define RTC_CTRL_SWRESET_SHIFT (0U) /*! SWRESET - Software reset control @@ -14448,6 +17473,7 @@ typedef struct { * the same time that the reset bit is being cleared. */ #define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) + #define RTC_CTRL_ALARM1HZ_MASK (0x4U) #define RTC_CTRL_ALARM1HZ_SHIFT (2U) /*! ALARM1HZ - RTC 1 Hz timer alarm flag status. @@ -14456,6 +17482,7 @@ typedef struct { * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. */ #define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) + #define RTC_CTRL_WAKE1KHZ_MASK (0x8U) #define RTC_CTRL_WAKE1KHZ_SHIFT (3U) /*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. @@ -14464,6 +17491,7 @@ typedef struct { * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. */ #define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) + #define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) #define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) /*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. @@ -14471,6 +17499,7 @@ typedef struct { * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. */ #define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) + #define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) #define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) /*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. @@ -14478,6 +17507,7 @@ typedef struct { * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. */ #define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) + #define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) #define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) /*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz @@ -14486,6 +17516,7 @@ typedef struct { * 0b1..Enable. The 1 kHz RTC timer is enabled. */ #define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) + #define RTC_CTRL_RTC_EN_MASK (0x80U) #define RTC_CTRL_RTC_EN_SHIFT (7U) /*! RTC_EN - RTC enable. @@ -14496,6 +17527,7 @@ typedef struct { * high-resolution, 1 kHz clock, set bit 6 in this register. */ #define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) + #define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) #define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) /*! RTC_OSC_PD - RTC oscillator power-down control. @@ -14503,6 +17535,7 @@ typedef struct { * 0b1..RTC oscillator is powered-down. */ #define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) + #define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) #define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) /*! RTC_OSC_BYPASS - RTC oscillator bypass control. @@ -14510,6 +17543,7 @@ typedef struct { * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. */ #define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) + #define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) #define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) /*! RTC_SUBSEC_ENA - RTC Sub-second counter control. @@ -14526,36 +17560,63 @@ typedef struct { /*! @name MATCH - RTC match register */ /*! @{ */ + #define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) #define RTC_MATCH_MATVAL_SHIFT (0U) +/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the + * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. + */ #define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) /*! @} */ /*! @name COUNT - RTC counter register */ /*! @{ */ + #define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) #define RTC_COUNT_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial + * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC + * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this + * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after + * the RTC_EN bit is set. + */ #define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) /*! @} */ /*! @name WAKE - High-resolution/wake-up timer control register */ /*! @{ */ + #define RTC_WAKE_VAL_MASK (0xFFFFU) #define RTC_WAKE_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads + * a start count value into the wake-up timer and initializes a count-down sequence. Do not write + * to this register while counting is in progress. + */ #define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) /*! @} */ -/*! @name SUBSEC - RTC Sub-second Counter register */ +/*! @name SUBSEC - Sub-second counter register */ /*! @{ */ + #define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) #define RTC_SUBSEC_SUBSEC_SHIFT (0U) +/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is + * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz + * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This + * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is + * disabled and re-enabled. On modules not equipped with a sub-second counter, this register + * will read-back as all zeroes. + */ #define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) /*! @} */ /*! @name GPREG - General Purpose register */ /*! @{ */ + #define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) #define RTC_GPREG_GPDATA_SHIFT (0U) +/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. + */ #define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) /*! @} */ @@ -14569,7 +17630,7 @@ typedef struct { /* RTC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral RTC base address */ #define RTC_BASE (0x5002C000u) /** Peripheral RTC base address */ @@ -14616,40 +17677,112 @@ typedef struct { /** SCT - Register Layout Typedef */ typedef struct { __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ + __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ + } CTRL_ACCESS16BIT; + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ + __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ + } LIMIT_ACCESS16BIT; + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + }; + union { /* offset: 0xC */ + struct { /* offset: 0xC */ + __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ + __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ + } HALT_ACCESS16BIT; + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + }; + union { /* offset: 0x10 */ + struct { /* offset: 0x10 */ + __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ + __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ + } STOP_ACCESS16BIT; + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + }; + union { /* offset: 0x14 */ + struct { /* offset: 0x14 */ + __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ + __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ + } START_ACCESS16BIT; + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + }; uint8_t RESERVED_0[40]; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + union { /* offset: 0x40 */ + struct { /* offset: 0x40 */ + __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ + __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ + } COUNT_ACCESS16BIT; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + }; + union { /* offset: 0x44 */ + struct { /* offset: 0x44 */ + __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ + __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ + } STATE_ACCESS16BIT; + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + }; __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + union { /* offset: 0x4C */ + struct { /* offset: 0x4C */ + __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ + __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ + } REGMODE_ACCESS16BIT; + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + }; __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ + __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ uint8_t RESERVED_1[140]; __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ union { /* offset: 0x100 */ - __IO uint32_t SCTCAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - __IO uint32_t SCTMATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ + } CAP_ACCESS16BIT[16]; + __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + }; + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ + } MATCH_ACCESS16BIT[16]; + __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; }; uint8_t RESERVED_2[192]; union { /* offset: 0x200 */ - __IO uint32_t SCTCAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - __IO uint32_t SCTMATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ + } CAPCTRL_ACCESS16BIT[16]; + __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + }; + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ + } MATCHREL_ACCESS16BIT[16]; + __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; }; uint8_t RESERVED_3[192]; struct { /* offset: 0x300, array step: 0x8 */ __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EVENT[16]; + } EV[16]; uint8_t RESERVED_4[384]; struct { /* offset: 0x500, array step: 0x8 */ __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ @@ -14668,6 +17801,7 @@ typedef struct { /*! @name CONFIG - SCT configuration register */ /*! @{ */ + #define SCT_CONFIG_UNIFY_MASK (0x1U) #define SCT_CONFIG_UNIFY_SHIFT (0U) /*! UNIFY - SCT operation @@ -14675,6 +17809,7 @@ typedef struct { * 0b1..The SCT operates as a unified 32-bit counter. */ #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) + #define SCT_CONFIG_CLKMODE_MASK (0x6U) #define SCT_CONFIG_CLKMODE_SHIFT (1U) /*! CLKMODE - SCT clock mode @@ -14692,6 +17827,7 @@ typedef struct { * the system clock. */ #define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) + #define SCT_CONFIG_CKSEL_MASK (0x78U) #define SCT_CONFIG_CKSEL_SHIFT (3U) /*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent @@ -14704,39 +17840,207 @@ typedef struct { * 0b0101..Falling edges on input 2. * 0b0110..Rising edges on input 3. * 0b0111..Falling edges on input 3. + * 0b1000..Rising edges on input 4. + * 0b1001..Falling edges on input 4. + * 0b1010..Rising edges on input 5. + * 0b1011..Falling edges on input 5. + * 0b1100..Rising edges on input 6. + * 0b1101..Falling edges on input 6. + * 0b1110..Rising edges on input 7. + * 0b1111..Falling edges on input 7. */ #define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) -#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) -#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) -#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) + +#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) +#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) +/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any + * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ +#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) + #define SCT_CONFIG_NORELOAD_H_MASK (0x100U) #define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at + * any time. This bit is not used when the UNIFY bit is set. + */ #define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) + #define SCT_CONFIG_INSYNC_MASK (0x1E00U) #define SCT_CONFIG_INSYNC_SHIFT (9U) +/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all + * other bits are reserved. A 1 in one of these bits subjects the corresponding input to + * synchronization to the SCT clock, before it is used to create an event. If an input is known to + * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: + * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input + * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. + * It does not apply to the clock input specified in the CKSEL field. + */ #define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) + #define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) #define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto + * LIMIT condition without the need to define an associated event. As with any LIMIT event, this + * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change + * the direction of count in bi-directional mode. Software can write to set or clear this bit at + * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ #define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) + #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a + * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, + * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to + * change the direction of count in bi-directional mode. Software can write to set or clear this bit + * at any time. This bit is not used when the UNIFY bit is set. + */ #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) /*! @} */ +/*! @name CTRLL - SCT_CTRLL register */ +/*! @{ */ + +#define SCT_CTRLL_DOWN_L_MASK (0x1U) +#define SCT_CTRLL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) + +#define SCT_CTRLL_STOP_L_MASK (0x2U) +#define SCT_CTRLL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ +#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) + +#define SCT_CTRLL_HALT_L_MASK (0x4U) +#define SCT_CTRLL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) + +#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + */ +#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) + +#define SCT_CTRLL_BIDIR_L_MASK (0x10U) +#define SCT_CTRLL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) + +#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRLL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) +/*! @} */ + +/*! @name CTRLH - SCT_CTRLH register */ +/*! @{ */ + +#define SCT_CTRLH_DOWN_H_MASK (0x1U) +#define SCT_CTRLH_DOWN_H_SHIFT (0U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) + +#define SCT_CTRLH_STOP_H_MASK (0x2U) +#define SCT_CTRLH_STOP_H_SHIFT (1U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ +#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) + +#define SCT_CTRLH_HALT_H_MASK (0x4U) +#define SCT_CTRLH_HALT_H_SHIFT (2U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) + +#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) +#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. + */ +#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) + +#define SCT_CTRLH_BIDIR_H_MASK (0x10U) +#define SCT_CTRLH_BIDIR_H_SHIFT (4U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) + +#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) +#define SCT_CTRLH_PRE_H_SHIFT (5U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) +/*! @} */ + /*! @name CTRL - SCT control register */ /*! @{ */ + #define SCT_CTRL_DOWN_L_MASK (0x1U) #define SCT_CTRL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) + #define SCT_CTRL_STOP_L_MASK (0x2U) #define SCT_CTRL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ #define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) + #define SCT_CTRL_HALT_L_MASK (0x4U) #define SCT_CTRL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ #define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) + #define SCT_CTRL_CLRCTR_L_MASK (0x8U) #define SCT_CTRL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + */ #define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) + #define SCT_CTRL_BIDIR_L_MASK (0x10U) #define SCT_CTRL_BIDIR_L_SHIFT (4U) /*! BIDIR_L - L or unified counter direction select @@ -14744,21 +18048,47 @@ typedef struct { * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. */ #define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) + #define SCT_CTRL_PRE_L_MASK (0x1FE0U) #define SCT_CTRL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ #define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) + #define SCT_CTRL_DOWN_H_MASK (0x10000U) #define SCT_CTRL_DOWN_H_SHIFT (16U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ #define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) + #define SCT_CTRL_STOP_H_MASK (0x20000U) #define SCT_CTRL_STOP_H_SHIFT (17U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ #define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) + #define SCT_CTRL_HALT_H_MASK (0x40000U) #define SCT_CTRL_HALT_H_SHIFT (18U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ #define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) + #define SCT_CTRL_CLRCTR_H_MASK (0x80000U) #define SCT_CTRL_CLRCTR_H_SHIFT (19U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. + */ #define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) + #define SCT_CTRL_BIDIR_H_MASK (0x100000U) #define SCT_CTRL_BIDIR_H_SHIFT (20U) /*! BIDIR_H - Direction select @@ -14766,190 +18096,465 @@ typedef struct { * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. */ #define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) + #define SCT_CTRL_PRE_H_MASK (0x1FE00000U) #define SCT_CTRL_PRE_H_SHIFT (21U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) /*! @} */ +/*! @name LIMITL - SCT_LIMITL register */ +/*! @{ */ + +#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) +#define SCT_LIMITL_LIMITL_SHIFT (0U) +#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) +/*! @} */ + +/*! @name LIMITH - SCT_LIMITH register */ +/*! @{ */ + +#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) +#define SCT_LIMITH_LIMITH_SHIFT (0U) +#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) +/*! @} */ + /*! @name LIMIT - SCT limit event select register */ /*! @{ */ + #define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) #define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) + #define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) #define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) /*! @} */ +/*! @name HALTL - SCT_HALTL register */ +/*! @{ */ + +#define SCT_HALTL_HALTL_MASK (0xFFFFU) +#define SCT_HALTL_HALTL_SHIFT (0U) +#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) +/*! @} */ + +/*! @name HALTH - SCT_HALTH register */ +/*! @{ */ + +#define SCT_HALTH_HALTH_MASK (0xFFFFU) +#define SCT_HALTH_HALTH_SHIFT (0U) +#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) +/*! @} */ + /*! @name HALT - SCT halt event select register */ /*! @{ */ + #define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) #define SCT_HALT_HALTMSK_L_SHIFT (0U) +/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) + #define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) #define SCT_HALT_HALTMSK_H_SHIFT (16U) +/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) /*! @} */ +/*! @name STOPL - SCT_STOPL register */ +/*! @{ */ + +#define SCT_STOPL_STOPL_MASK (0xFFFFU) +#define SCT_STOPL_STOPL_SHIFT (0U) +#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) +/*! @} */ + +/*! @name STOPH - SCT_STOPH register */ +/*! @{ */ + +#define SCT_STOPH_STOPH_MASK (0xFFFFU) +#define SCT_STOPH_STOPH_SHIFT (0U) +#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) +/*! @} */ + /*! @name STOP - SCT stop event select register */ /*! @{ */ + #define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) #define SCT_STOP_STOPMSK_L_SHIFT (0U) +/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) + #define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) #define SCT_STOP_STOPMSK_H_SHIFT (16U) +/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) /*! @} */ +/*! @name STARTL - SCT_STARTL register */ +/*! @{ */ + +#define SCT_STARTL_STARTL_MASK (0xFFFFU) +#define SCT_STARTL_STARTL_SHIFT (0U) +#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) +/*! @} */ + +/*! @name STARTH - SCT_STARTH register */ +/*! @{ */ + +#define SCT_STARTH_STARTH_MASK (0xFFFFU) +#define SCT_STARTH_STARTH_SHIFT (0U) +#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) +/*! @} */ + /*! @name START - SCT start event select register */ /*! @{ */ + #define SCT_START_STARTMSK_L_MASK (0xFFFFU) #define SCT_START_STARTMSK_L_SHIFT (0U) +/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit + * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) + #define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) #define SCT_START_STARTMSK_H_SHIFT (16U) +/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) /*! @} */ +/*! @name COUNTL - SCT_COUNTL register */ +/*! @{ */ + +#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) +#define SCT_COUNTL_COUNTL_SHIFT (0U) +#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) +/*! @} */ + +/*! @name COUNTH - SCT_COUNTH register */ +/*! @{ */ + +#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) +#define SCT_COUNTH_COUNTH_SHIFT (0U) +#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) +/*! @} */ + /*! @name COUNT - SCT counter register */ /*! @{ */ + #define SCT_COUNT_CTR_L_MASK (0xFFFFU) #define SCT_COUNT_CTR_L_SHIFT (0U) +/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write + * the lower 16 bits of the 32-bit unified counter. + */ #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) + #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) #define SCT_COUNT_CTR_H_SHIFT (16U) +/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write + * the upper 16 bits of the 32-bit unified counter. + */ #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) /*! @} */ +/*! @name STATEL - SCT_STATEL register */ +/*! @{ */ + +#define SCT_STATEL_STATEL_MASK (0xFFFFU) +#define SCT_STATEL_STATEL_SHIFT (0U) +#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) +/*! @} */ + +/*! @name STATEH - SCT_STATEH register */ +/*! @{ */ + +#define SCT_STATEH_STATEH_MASK (0xFFFFU) +#define SCT_STATEH_STATEH_SHIFT (0U) +#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) +/*! @} */ + /*! @name STATE - SCT state register */ /*! @{ */ + #define SCT_STATE_STATE_L_MASK (0x1FU) #define SCT_STATE_STATE_L_SHIFT (0U) +/*! STATE_L - State variable. + */ #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) + #define SCT_STATE_STATE_H_MASK (0x1F0000U) #define SCT_STATE_STATE_H_SHIFT (16U) +/*! STATE_H - State variable. + */ #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) /*! @} */ /*! @name INPUT - SCT input register */ /*! @{ */ + #define SCT_INPUT_AIN0_MASK (0x1U) #define SCT_INPUT_AIN0_SHIFT (0U) +/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) + #define SCT_INPUT_AIN1_MASK (0x2U) #define SCT_INPUT_AIN1_SHIFT (1U) +/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) + #define SCT_INPUT_AIN2_MASK (0x4U) #define SCT_INPUT_AIN2_SHIFT (2U) +/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) + #define SCT_INPUT_AIN3_MASK (0x8U) #define SCT_INPUT_AIN3_SHIFT (3U) +/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) + #define SCT_INPUT_AIN4_MASK (0x10U) #define SCT_INPUT_AIN4_SHIFT (4U) +/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) + #define SCT_INPUT_AIN5_MASK (0x20U) #define SCT_INPUT_AIN5_SHIFT (5U) +/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) + #define SCT_INPUT_AIN6_MASK (0x40U) #define SCT_INPUT_AIN6_SHIFT (6U) +/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) + #define SCT_INPUT_AIN7_MASK (0x80U) #define SCT_INPUT_AIN7_SHIFT (7U) +/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) + #define SCT_INPUT_AIN8_MASK (0x100U) #define SCT_INPUT_AIN8_SHIFT (8U) +/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) + #define SCT_INPUT_AIN9_MASK (0x200U) #define SCT_INPUT_AIN9_SHIFT (9U) +/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) + #define SCT_INPUT_AIN10_MASK (0x400U) #define SCT_INPUT_AIN10_SHIFT (10U) +/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) + #define SCT_INPUT_AIN11_MASK (0x800U) #define SCT_INPUT_AIN11_SHIFT (11U) +/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) + #define SCT_INPUT_AIN12_MASK (0x1000U) #define SCT_INPUT_AIN12_SHIFT (12U) +/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) + #define SCT_INPUT_AIN13_MASK (0x2000U) #define SCT_INPUT_AIN13_SHIFT (13U) +/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) + #define SCT_INPUT_AIN14_MASK (0x4000U) #define SCT_INPUT_AIN14_SHIFT (14U) +/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) + #define SCT_INPUT_AIN15_MASK (0x8000U) #define SCT_INPUT_AIN15_SHIFT (15U) +/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) + #define SCT_INPUT_SIN0_MASK (0x10000U) #define SCT_INPUT_SIN0_SHIFT (16U) +/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) + #define SCT_INPUT_SIN1_MASK (0x20000U) #define SCT_INPUT_SIN1_SHIFT (17U) +/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) + #define SCT_INPUT_SIN2_MASK (0x40000U) #define SCT_INPUT_SIN2_SHIFT (18U) +/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) + #define SCT_INPUT_SIN3_MASK (0x80000U) #define SCT_INPUT_SIN3_SHIFT (19U) +/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) + #define SCT_INPUT_SIN4_MASK (0x100000U) #define SCT_INPUT_SIN4_SHIFT (20U) +/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) + #define SCT_INPUT_SIN5_MASK (0x200000U) #define SCT_INPUT_SIN5_SHIFT (21U) +/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) + #define SCT_INPUT_SIN6_MASK (0x400000U) #define SCT_INPUT_SIN6_SHIFT (22U) +/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) + #define SCT_INPUT_SIN7_MASK (0x800000U) #define SCT_INPUT_SIN7_SHIFT (23U) +/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) + #define SCT_INPUT_SIN8_MASK (0x1000000U) #define SCT_INPUT_SIN8_SHIFT (24U) +/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) + #define SCT_INPUT_SIN9_MASK (0x2000000U) #define SCT_INPUT_SIN9_SHIFT (25U) +/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) + #define SCT_INPUT_SIN10_MASK (0x4000000U) #define SCT_INPUT_SIN10_SHIFT (26U) +/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) + #define SCT_INPUT_SIN11_MASK (0x8000000U) #define SCT_INPUT_SIN11_SHIFT (27U) +/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) + #define SCT_INPUT_SIN12_MASK (0x10000000U) #define SCT_INPUT_SIN12_SHIFT (28U) +/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) + #define SCT_INPUT_SIN13_MASK (0x20000000U) #define SCT_INPUT_SIN13_SHIFT (29U) +/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) + #define SCT_INPUT_SIN14_MASK (0x40000000U) #define SCT_INPUT_SIN14_SHIFT (30U) +/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) + #define SCT_INPUT_SIN15_MASK (0x80000000U) #define SCT_INPUT_SIN15_SHIFT (31U) +/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) /*! @} */ +/*! @name REGMODEL - SCT_REGMODEL register */ +/*! @{ */ + +#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) +#define SCT_REGMODEL_REGMODEL_SHIFT (0U) +#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) +/*! @} */ + +/*! @name REGMODEH - SCT_REGMODEH register */ +/*! @{ */ + +#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) +#define SCT_REGMODEH_REGMODEH_SHIFT (0U) +#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) +/*! @} */ + /*! @name REGMODE - SCT match/capture mode register */ /*! @{ */ + #define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) #define SCT_REGMODE_REGMOD_L_SHIFT (0U) +/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, + * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match register. 1 = register operates as capture register. + */ #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) + #define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) #define SCT_REGMODE_REGMOD_H_SHIFT (16U) +/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit + * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match registers. 1 = register operates as capture registers. + */ #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) /*! @} */ /*! @name OUTPUT - SCT output register */ /*! @{ */ + #define SCT_OUTPUT_OUT_MASK (0xFFFFU) #define SCT_OUTPUT_OUT_SHIFT (0U) +/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the + * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ #define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) /*! @} */ /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ /*! @{ */ + #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) /*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. @@ -14958,6 +18563,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) /*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. @@ -14966,6 +18572,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) /*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. @@ -14974,6 +18581,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) /*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. @@ -14982,6 +18590,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) /*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. @@ -14990,6 +18599,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) /*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. @@ -14998,6 +18608,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) /*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. @@ -15006,6 +18617,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) #define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) /*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. @@ -15014,6 +18626,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) #define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) /*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. @@ -15022,6 +18635,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) #define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) /*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. @@ -15030,6 +18644,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) #define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) /*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. @@ -15038,6 +18653,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) #define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) /*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. @@ -15046,6 +18662,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) #define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) /*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. @@ -15054,6 +18671,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) #define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) /*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. @@ -15062,6 +18680,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) #define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) /*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. @@ -15070,6 +18689,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) #define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) /*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. @@ -15082,6 +18702,7 @@ typedef struct { /*! @name RES - SCT conflict resolution register */ /*! @{ */ + #define SCT_RES_O0RES_MASK (0x3U) #define SCT_RES_O0RES_SHIFT (0U) /*! O0RES - Effect of simultaneous set and clear on output 0. @@ -15091,6 +18712,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) + #define SCT_RES_O1RES_MASK (0xCU) #define SCT_RES_O1RES_SHIFT (2U) /*! O1RES - Effect of simultaneous set and clear on output 1. @@ -15100,6 +18722,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) + #define SCT_RES_O2RES_MASK (0x30U) #define SCT_RES_O2RES_SHIFT (4U) /*! O2RES - Effect of simultaneous set and clear on output 2. @@ -15109,6 +18732,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) + #define SCT_RES_O3RES_MASK (0xC0U) #define SCT_RES_O3RES_SHIFT (6U) /*! O3RES - Effect of simultaneous set and clear on output 3. @@ -15118,6 +18742,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) + #define SCT_RES_O4RES_MASK (0x300U) #define SCT_RES_O4RES_SHIFT (8U) /*! O4RES - Effect of simultaneous set and clear on output 4. @@ -15127,6 +18752,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) + #define SCT_RES_O5RES_MASK (0xC00U) #define SCT_RES_O5RES_SHIFT (10U) /*! O5RES - Effect of simultaneous set and clear on output 5. @@ -15136,6 +18762,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) + #define SCT_RES_O6RES_MASK (0x3000U) #define SCT_RES_O6RES_SHIFT (12U) /*! O6RES - Effect of simultaneous set and clear on output 6. @@ -15145,6 +18772,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) + #define SCT_RES_O7RES_MASK (0xC000U) #define SCT_RES_O7RES_SHIFT (14U) /*! O7RES - Effect of simultaneous set and clear on output 7. @@ -15154,6 +18782,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) + #define SCT_RES_O8RES_MASK (0x30000U) #define SCT_RES_O8RES_SHIFT (16U) /*! O8RES - Effect of simultaneous set and clear on output 8. @@ -15163,6 +18792,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) + #define SCT_RES_O9RES_MASK (0xC0000U) #define SCT_RES_O9RES_SHIFT (18U) /*! O9RES - Effect of simultaneous set and clear on output 9. @@ -15172,6 +18802,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) + #define SCT_RES_O10RES_MASK (0x300000U) #define SCT_RES_O10RES_SHIFT (20U) /*! O10RES - Effect of simultaneous set and clear on output 10. @@ -15181,6 +18812,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) + #define SCT_RES_O11RES_MASK (0xC00000U) #define SCT_RES_O11RES_SHIFT (22U) /*! O11RES - Effect of simultaneous set and clear on output 11. @@ -15190,6 +18822,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) + #define SCT_RES_O12RES_MASK (0x3000000U) #define SCT_RES_O12RES_SHIFT (24U) /*! O12RES - Effect of simultaneous set and clear on output 12. @@ -15199,6 +18832,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) + #define SCT_RES_O13RES_MASK (0xC000000U) #define SCT_RES_O13RES_SHIFT (26U) /*! O13RES - Effect of simultaneous set and clear on output 13. @@ -15208,6 +18842,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) + #define SCT_RES_O14RES_MASK (0x30000000U) #define SCT_RES_O14RES_SHIFT (28U) /*! O14RES - Effect of simultaneous set and clear on output 14. @@ -15217,6 +18852,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) + #define SCT_RES_O15RES_MASK (0xC0000000U) #define SCT_RES_O15RES_SHIFT (30U) /*! O15RES - Effect of simultaneous set and clear on output 15. @@ -15228,152 +18864,350 @@ typedef struct { #define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) /*! @} */ -/*! @name DMA0REQUEST - SCT DMA request 0 register */ +/*! @name DMAREQ0 - SCT DMA request 0 register */ /*! @{ */ -#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) -#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) -#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) -#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) -#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) -#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) -#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) -#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) -#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) + +#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) +#define SCT_DMAREQ0_DEV_0_SHIFT (0U) +/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) + +#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) +#define SCT_DMAREQ0_DRL0_SHIFT (30U) +/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. + */ +#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) + +#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) +#define SCT_DMAREQ0_DRQ0_SHIFT (31U) +/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) /*! @} */ -/*! @name DMA1REQUEST - SCT DMA request 1 register */ +/*! @name DMAREQ1 - SCT DMA request 1 register */ /*! @{ */ -#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) -#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) -#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) -#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) -#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) -#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) -#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) -#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) -#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) + +#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) +#define SCT_DMAREQ1_DEV_1_SHIFT (0U) +/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) + +#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) +#define SCT_DMAREQ1_DRL1_SHIFT (30U) +/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. + */ +#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) + +#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) +#define SCT_DMAREQ1_DRQ1_SHIFT (31U) +/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) /*! @} */ /*! @name EVEN - SCT event interrupt enable register */ /*! @{ */ + #define SCT_EVEN_IEN_MASK (0xFFFFU) #define SCT_EVEN_IEN_SHIFT (0U) +/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are + * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in + * this SCT. + */ #define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) /*! @} */ /*! @name EVFLAG - SCT event flag register */ /*! @{ */ + #define SCT_EVFLAG_FLAG_MASK (0xFFFFU) #define SCT_EVFLAG_FLAG_SHIFT (0U) +/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ #define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) /*! @} */ /*! @name CONEN - SCT conflict interrupt enable register */ /*! @{ */ + #define SCT_CONEN_NCEN_MASK (0xFFFFU) #define SCT_CONEN_NCEN_SHIFT (0U) +/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag + * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ #define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) /*! @} */ /*! @name CONFLAG - SCT conflict flag register */ /*! @{ */ + #define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) #define SCT_CONFLAG_NCFLAG_SHIFT (0U) +/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was + * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = + * number of outputs in this SCT. + */ #define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) + #define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) #define SCT_CONFLAG_BUSERRL_SHIFT (30U) +/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE + * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write + * to certain L and H registers can be half successful and half unsuccessful. + */ #define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) + #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) #define SCT_CONFLAG_BUSERRH_SHIFT (31U) +/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or + * the Output register when the H counter was not halted. + */ #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) /*! @} */ -/*! @name SCTCAP - SCT capture register of capture channel */ +/*! @name CAPL - SCT_CAPL register */ /*! @{ */ -#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) -#define SCT_SCTCAP_CAPn_L_SHIFT (0U) -#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) -#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAP_CAPn_H_SHIFT (16U) -#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) + +#define SCT_CAPL_CAPL_MASK (0xFFFFU) +#define SCT_CAPL_CAPL_SHIFT (0U) +#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) /*! @} */ -/* The count of SCT_SCTCAP */ -#define SCT_SCTCAP_COUNT (16U) +/* The count of SCT_CAPL */ +#define SCT_CAPL_COUNT (16U) -/*! @name SCTMATCH - SCT match value register of match channels */ +/*! @name CAPH - SCT_CAPH register */ /*! @{ */ -#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) -#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) -#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) -#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) + +#define SCT_CAPH_CAPH_MASK (0xFFFFU) +#define SCT_CAPH_CAPH_SHIFT (0U) +#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) /*! @} */ -/* The count of SCT_SCTMATCH */ -#define SCT_SCTMATCH_COUNT (16U) +/* The count of SCT_CAPH */ +#define SCT_CAPH_COUNT (16U) -/*! @name SCTCAPCTRL - SCT capture control register */ +/*! @name CAP - SCT capture register of capture channel */ /*! @{ */ -#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) -#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) -#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) -#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) + +#define SCT_CAP_CAPn_L_MASK (0xFFFFU) +#define SCT_CAP_CAPn_L_SHIFT (0U) +/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) + +#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_CAP_CAPn_H_SHIFT (16U) +/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) /*! @} */ -/* The count of SCT_SCTCAPCTRL */ -#define SCT_SCTCAPCTRL_COUNT (16U) +/* The count of SCT_CAP */ +#define SCT_CAP_COUNT (16U) -/*! @name SCTMATCHREL - SCT match reload value register */ +/*! @name MATCHL - SCT_MATCHL register */ /*! @{ */ -#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) -#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) -#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) -#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) + +#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) +#define SCT_MATCHL_MATCHL_SHIFT (0U) +#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) /*! @} */ -/* The count of SCT_SCTMATCHREL */ -#define SCT_SCTMATCHREL_COUNT (16U) +/* The count of SCT_MATCHL */ +#define SCT_MATCHL_COUNT (16U) -/*! @name EVENT_STATE - SCT event state register 0 */ +/*! @name MATCHH - SCT_MATCHH register */ /*! @{ */ -#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) -#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) + +#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) +#define SCT_MATCHH_MATCHH_SHIFT (0U) +#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) /*! @} */ -/* The count of SCT_EVENT_STATE */ -#define SCT_EVENT_STATE_COUNT (16U) +/* The count of SCT_MATCHH */ +#define SCT_MATCHH_COUNT (16U) -/*! @name EVENT_CTRL - SCT event control register 0 */ +/*! @name MATCH - SCT match value register of match channels */ /*! @{ */ -#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) -#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) -#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) -#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) + +#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_MATCH_MATCHn_L_SHIFT (0U) +/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When + * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) + +#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_MATCH_MATCHn_H_SHIFT (16U) +/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When + * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCH */ +#define SCT_MATCH_COUNT (16U) + +/*! @name CAPCTRLL - SCT_CAPCTRLL register */ +/*! @{ */ + +#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) +#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) +#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLL */ +#define SCT_CAPCTRLL_COUNT (16U) + +/*! @name CAPCTRLH - SCT_CAPCTRLH register */ +/*! @{ */ + +#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) +#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) +#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLH */ +#define SCT_CAPCTRLH_COUNT (16U) + +/*! @name CAPCTRL - SCT capture control register */ +/*! @{ */ + +#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) +/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) + * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of + * match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) + +#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) +/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event + * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRL */ +#define SCT_CAPCTRL_COUNT (16U) + +/*! @name MATCHRELL - SCT_MATCHRELL register */ +/*! @{ */ + +#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) +#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) +#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELL */ +#define SCT_MATCHRELL_COUNT (16U) + +/*! @name MATCHRELH - SCT_MATCHRELH register */ +/*! @{ */ + +#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) +#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) +#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELH */ +#define SCT_MATCHRELH_COUNT (16U) + +/*! @name MATCHREL - SCT match reload value register */ +/*! @{ */ + +#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) +/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. + * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) + +#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) +/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When + * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCHREL */ +#define SCT_MATCHREL_COUNT (16U) + +/*! @name EV_STATE - SCT event state register 0 */ +/*! @{ */ + +#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) +/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT + * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of + * bits = number of states in this SCT. + */ +#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EV_STATE */ +#define SCT_EV_STATE_COUNT (16U) + +/*! @name EV_CTRL - SCT event control register 0 */ +/*! @{ */ + +#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) +/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur + * only when the counter selected by the HEVENT bit is running. + */ +#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) + +#define SCT_EV_CTRL_HEVENT_MASK (0x10U) +#define SCT_EV_CTRL_HEVENT_SHIFT (4U) /*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. * 0b0..Selects the L state and the L match register selected by MATCHSEL. * 0b1..Selects the H state and the H match register selected by MATCHSEL. */ -#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) -#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) +#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) + +#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) /*! OUTSEL - Input/output select * 0b0..Selects the inputs selected by IOSEL. * 0b1..Selects the outputs selected by IOSEL. */ -#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) -#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) -#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) -#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) +#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) + +#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EV_CTRL_IOSEL_SHIFT (6U) +/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not + * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit + * ingredient of every event. + */ +#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) + +#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EV_CTRL_IOCOND_SHIFT (10U) /*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state * detection, an input must have a minimum pulse width of at least one SCT clock period . @@ -15382,48 +19216,69 @@ typedef struct { * 0b10..Fall * 0b11..HIGH */ -#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) -#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) +#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) + +#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) /*! COMBMODE - Selects how the specified match and I/O condition are used and combined. * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. * 0b01..MATCH. Uses the specified match only. * 0b10..IO. Uses the specified I/O condition only. * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. */ -#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) -#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) -#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) +#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) + +#define SCT_EV_CTRL_STATELD_MASK (0x4000U) +#define SCT_EV_CTRL_STATELD_SHIFT (14U) /*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this * event is the highest-numbered event occurring for that state. * 0b0..STATEV value is added into STATE (the carry-out is ignored). * 0b1..STATEV value is loaded into STATE. */ -#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) -#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) -#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) -#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) -#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) -#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) +#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) + +#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EV_CTRL_STATEV_SHIFT (15U) +/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on + * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and + * STATEV are both zero, there is no change to the STATE value. + */ +#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) + +#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) +/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the + * triggering of this event, then a match is considered to be active whenever the counter value is + * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR + * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active + * during the cycle when the counter is equal to the match value. + */ +#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) + +#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) /*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. * 0b00..Direction independent. This event is triggered regardless of the count direction. * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. */ -#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) +#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) /*! @} */ -/* The count of SCT_EVENT_CTRL */ -#define SCT_EVENT_CTRL_COUNT (16U) +/* The count of SCT_EV_CTRL */ +#define SCT_EV_CTRL_COUNT (16U) /*! @name OUT_SET - SCT output 0 set register */ /*! @{ */ + #define SCT_OUT_SET_SET_MASK (0xFFFFU) #define SCT_OUT_SET_SET_SHIFT (0U) +/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output + * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) /*! @} */ @@ -15432,8 +19287,14 @@ typedef struct { /*! @name OUT_CLR - SCT output 0 clear register */ /*! @{ */ + #define SCT_OUT_CLR_CLR_MASK (0xFFFFU) #define SCT_OUT_CLR_CLR_SHIFT (0U) +/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 + * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) /*! @} */ @@ -15447,7 +19308,7 @@ typedef struct { /* SCT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral SCT0 base address */ #define SCT0_BASE (0x50085000u) /** Peripheral SCT0 base address */ @@ -15544,220 +19405,401 @@ typedef struct { /*! @name CTRL - Control register */ /*! @{ */ + #define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) #define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) +/*! CONTROLLER_RESET - Controller reset. + */ #define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) + #define SDIF_CTRL_FIFO_RESET_MASK (0x2U) #define SDIF_CTRL_FIFO_RESET_SHIFT (1U) +/*! FIFO_RESET - Fifo reset. + */ #define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) + #define SDIF_CTRL_DMA_RESET_MASK (0x4U) #define SDIF_CTRL_DMA_RESET_SHIFT (2U) +/*! DMA_RESET - DMA reset. + */ #define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) + #define SDIF_CTRL_INT_ENABLE_MASK (0x10U) #define SDIF_CTRL_INT_ENABLE_SHIFT (4U) +/*! INT_ENABLE - Global interrupt enable/disable bit. + */ #define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) + #define SDIF_CTRL_READ_WAIT_MASK (0x40U) #define SDIF_CTRL_READ_WAIT_SHIFT (6U) +/*! READ_WAIT - Read/wait. + */ #define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) + #define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) #define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) +/*! SEND_IRQ_RESPONSE - Send irq response. + */ #define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) + #define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) #define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) +/*! ABORT_READ_DATA - Abort read data. + */ #define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) + #define SDIF_CTRL_SEND_CCSD_MASK (0x200U) #define SDIF_CTRL_SEND_CCSD_SHIFT (9U) +/*! SEND_CCSD - Send ccsd. + */ #define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) + #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) +/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd. + */ #define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) + #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) +/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. + */ #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) + #define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) #define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) +/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. + */ #define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) + #define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) #define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) +/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. + */ #define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) + #define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) #define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) +/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. + */ #define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) + #define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) #define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) +/*! USE_INTERNAL_DMAC - SD/MMC DMA use. + */ #define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) /*! @} */ /*! @name PWREN - Power Enable register */ /*! @{ */ + #define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) #define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) +/*! POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait + * for regulator/switch ramp-up time before trying to initialize card 0. + */ #define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) + #define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) #define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) +/*! POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait + * for regulator/switch ramp-up time before trying to initialize card 1. + */ #define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) /*! @} */ /*! @name CLKDIV - Clock Divider register */ /*! @{ */ + #define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) #define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) +/*! CLK_DIVIDER0 - Clock divider-0 value. + */ #define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) /*! @} */ /*! @name CLKENA - Clock Enable register */ /*! @{ */ + #define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) #define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) +/*! CCLK0_ENABLE - Clock-enable control for SD card 0 clock. + */ #define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) + #define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) #define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) +/*! CCLK1_ENABLE - Clock-enable control for SD card 1 clock. + */ #define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) + #define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) #define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) +/*! CCLK0_LOW_POWER - Low-power control for SD card 0 clock. + */ #define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) + #define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) #define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) +/*! CCLK1_LOW_POWER - Low-power control for SD card 1 clock. + */ #define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) /*! @} */ /*! @name TMOUT - Time-out register */ /*! @{ */ + #define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) #define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) +/*! RESPONSE_TIMEOUT - Response time-out value. + */ #define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) + #define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) #define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) +/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. + */ #define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) /*! @} */ /*! @name CTYPE - Card Type register */ /*! @{ */ + #define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) #define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) +/*! CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit + * modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set + * to 0). + */ #define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) + #define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) #define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) +/*! CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit + * modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set + * to 0). + */ #define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) + #define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) #define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) +/*! CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + */ #define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) + #define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) #define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) +/*! CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + */ #define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) /*! @} */ /*! @name BLKSIZ - Block Size register */ /*! @{ */ + #define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) #define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) +/*! BLOCK_SIZE - Block size. + */ #define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) /*! @} */ /*! @name BYTCNT - Byte Count register */ /*! @{ */ + #define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) #define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) +/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. + */ #define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) /*! @} */ /*! @name INTMASK - Interrupt Mask register */ /*! @{ */ + #define SDIF_INTMASK_CDET_MASK (0x1U) #define SDIF_INTMASK_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ #define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) + #define SDIF_INTMASK_RE_MASK (0x2U) #define SDIF_INTMASK_RE_SHIFT (1U) +/*! RE - Response error. + */ #define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) + #define SDIF_INTMASK_CDONE_MASK (0x4U) #define SDIF_INTMASK_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ #define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) + #define SDIF_INTMASK_DTO_MASK (0x8U) #define SDIF_INTMASK_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ #define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) + #define SDIF_INTMASK_TXDR_MASK (0x10U) #define SDIF_INTMASK_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ #define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) + #define SDIF_INTMASK_RXDR_MASK (0x20U) #define SDIF_INTMASK_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ #define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) + #define SDIF_INTMASK_RCRC_MASK (0x40U) #define SDIF_INTMASK_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ #define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) + #define SDIF_INTMASK_DCRC_MASK (0x80U) #define SDIF_INTMASK_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ #define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) + #define SDIF_INTMASK_RTO_MASK (0x100U) #define SDIF_INTMASK_RTO_SHIFT (8U) +/*! RTO - Response time-out. + */ #define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) + #define SDIF_INTMASK_DRTO_MASK (0x200U) #define SDIF_INTMASK_DRTO_SHIFT (9U) +/*! DRTO - Data read time-out. + */ #define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) + #define SDIF_INTMASK_HTO_MASK (0x400U) #define SDIF_INTMASK_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ #define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) + #define SDIF_INTMASK_FRUN_MASK (0x800U) #define SDIF_INTMASK_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ #define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) + #define SDIF_INTMASK_HLE_MASK (0x1000U) #define SDIF_INTMASK_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ #define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) + #define SDIF_INTMASK_SBE_MASK (0x2000U) #define SDIF_INTMASK_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ #define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) + #define SDIF_INTMASK_ACD_MASK (0x4000U) #define SDIF_INTMASK_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ #define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) + #define SDIF_INTMASK_EBE_MASK (0x8000U) #define SDIF_INTMASK_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/Write no CRC. + */ #define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) + #define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) #define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) +/*! SDIO_INT_MASK - Mask SDIO interrupt. + */ #define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) /*! @} */ /*! @name CMDARG - Command Argument register */ /*! @{ */ + #define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) #define SDIF_CMDARG_CMD_ARG_SHIFT (0U) +/*! CMD_ARG - Value indicates command argument to be passed to card. + */ #define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) /*! @} */ /*! @name CMD - Command register */ /*! @{ */ + #define SDIF_CMD_CMD_INDEX_MASK (0x3FU) #define SDIF_CMD_CMD_INDEX_SHIFT (0U) +/*! CMD_INDEX - Command index. + */ #define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) + #define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) #define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) +/*! RESPONSE_EXPECT - Response expect. + */ #define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) + #define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) #define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) +/*! RESPONSE_LENGTH - Response length. + */ #define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) + #define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) #define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) +/*! CHECK_RESPONSE_CRC - Check response CRC. + */ #define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) + #define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) #define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) +/*! DATA_EXPECTED - Data expected. + */ #define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) + #define SDIF_CMD_READ_WRITE_MASK (0x400U) #define SDIF_CMD_READ_WRITE_SHIFT (10U) +/*! READ_WRITE - read/write. + */ #define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) + #define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) #define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) +/*! TRANSFER_MODE - Transfer mode. + */ #define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) + #define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) #define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) +/*! SEND_AUTO_STOP - Send auto stop. + */ #define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) + #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) +/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete. + */ #define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) + #define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) #define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) +/*! STOP_ABORT_CMD - Stop abort command. + */ #define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) + #define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) #define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) +/*! SEND_INITIALIZATION - Send initialization. + */ #define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) + #define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) #define SDIF_CMD_CARD_NUMBER_SHIFT (16U) /*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed @@ -15765,42 +19807,75 @@ typedef struct { * 0b00001..Command will be execute on SDCARD 1 */ #define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) + #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) +/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. + */ #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) + #define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) #define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) +/*! READ_CEATA_DEVICE - Read ceata device. + */ #define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) + #define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) #define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) +/*! CCS_EXPECTED - CCS expected. + */ #define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) + #define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) #define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) +/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. + */ #define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) + #define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) #define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) +/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge. + */ #define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) + #define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) #define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) +/*! DISABLE_BOOT - Disable Boot. + */ #define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) + #define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) #define SDIF_CMD_BOOT_MODE_SHIFT (27U) +/*! BOOT_MODE - Boot Mode. + */ #define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) + #define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) #define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) +/*! VOLT_SWITCH - Voltage switch bit. + */ #define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) + #define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) #define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) +/*! USE_HOLD_REG - Use Hold Register. + */ #define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) + #define SDIF_CMD_START_CMD_MASK (0x80000000U) #define SDIF_CMD_START_CMD_SHIFT (31U) +/*! START_CMD - Start command. + */ #define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) /*! @} */ /*! @name RESP - Response register */ /*! @{ */ + #define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) #define SDIF_RESP_RESPONSE_SHIFT (0U) +/*! RESPONSE - Bits of response. + */ #define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) /*! @} */ @@ -15809,339 +19884,602 @@ typedef struct { /*! @name MINTSTS - Masked Interrupt Status register */ /*! @{ */ + #define SDIF_MINTSTS_CDET_MASK (0x1U) #define SDIF_MINTSTS_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ #define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) + #define SDIF_MINTSTS_RE_MASK (0x2U) #define SDIF_MINTSTS_RE_SHIFT (1U) +/*! RE - Response error. + */ #define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) + #define SDIF_MINTSTS_CDONE_MASK (0x4U) #define SDIF_MINTSTS_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ #define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) + #define SDIF_MINTSTS_DTO_MASK (0x8U) #define SDIF_MINTSTS_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ #define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) + #define SDIF_MINTSTS_TXDR_MASK (0x10U) #define SDIF_MINTSTS_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ #define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) + #define SDIF_MINTSTS_RXDR_MASK (0x20U) #define SDIF_MINTSTS_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ #define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) + #define SDIF_MINTSTS_RCRC_MASK (0x40U) #define SDIF_MINTSTS_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ #define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) + #define SDIF_MINTSTS_DCRC_MASK (0x80U) #define SDIF_MINTSTS_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ #define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) + #define SDIF_MINTSTS_RTO_MASK (0x100U) #define SDIF_MINTSTS_RTO_SHIFT (8U) +/*! RTO - Response time-out. + */ #define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) + #define SDIF_MINTSTS_DRTO_MASK (0x200U) #define SDIF_MINTSTS_DRTO_SHIFT (9U) +/*! DRTO - Data read time-out. + */ #define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) + #define SDIF_MINTSTS_HTO_MASK (0x400U) #define SDIF_MINTSTS_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ #define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) + #define SDIF_MINTSTS_FRUN_MASK (0x800U) #define SDIF_MINTSTS_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ #define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) + #define SDIF_MINTSTS_HLE_MASK (0x1000U) #define SDIF_MINTSTS_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ #define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) + #define SDIF_MINTSTS_SBE_MASK (0x2000U) #define SDIF_MINTSTS_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ #define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) + #define SDIF_MINTSTS_ACD_MASK (0x4000U) #define SDIF_MINTSTS_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ #define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) + #define SDIF_MINTSTS_EBE_MASK (0x8000U) #define SDIF_MINTSTS_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/write no CRC. + */ #define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) + #define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) #define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) +/*! SDIO_INTERRUPT - Interrupt from SDIO card. + */ #define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) /*! @} */ /*! @name RINTSTS - Raw Interrupt Status register */ /*! @{ */ + #define SDIF_RINTSTS_CDET_MASK (0x1U) #define SDIF_RINTSTS_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ #define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) + #define SDIF_RINTSTS_RE_MASK (0x2U) #define SDIF_RINTSTS_RE_SHIFT (1U) +/*! RE - Response error. + */ #define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) + #define SDIF_RINTSTS_CDONE_MASK (0x4U) #define SDIF_RINTSTS_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ #define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) + #define SDIF_RINTSTS_DTO_MASK (0x8U) #define SDIF_RINTSTS_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ #define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) + #define SDIF_RINTSTS_TXDR_MASK (0x10U) #define SDIF_RINTSTS_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ #define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) + #define SDIF_RINTSTS_RXDR_MASK (0x20U) #define SDIF_RINTSTS_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ #define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) + #define SDIF_RINTSTS_RCRC_MASK (0x40U) #define SDIF_RINTSTS_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ #define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) + #define SDIF_RINTSTS_DCRC_MASK (0x80U) #define SDIF_RINTSTS_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ #define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) + #define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) #define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) +/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). + */ #define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) + #define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) #define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) +/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). + */ #define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) + #define SDIF_RINTSTS_HTO_MASK (0x400U) #define SDIF_RINTSTS_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ #define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) + #define SDIF_RINTSTS_FRUN_MASK (0x800U) #define SDIF_RINTSTS_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ #define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) + #define SDIF_RINTSTS_HLE_MASK (0x1000U) #define SDIF_RINTSTS_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ #define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) + #define SDIF_RINTSTS_SBE_MASK (0x2000U) #define SDIF_RINTSTS_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ #define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) + #define SDIF_RINTSTS_ACD_MASK (0x4000U) #define SDIF_RINTSTS_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ #define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) + #define SDIF_RINTSTS_EBE_MASK (0x8000U) #define SDIF_RINTSTS_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/write no CRC. + */ #define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) + #define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) #define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) +/*! SDIO_INTERRUPT - Interrupt from SDIO card. + */ #define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) /*! @} */ /*! @name STATUS - Status register */ /*! @{ */ + #define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) #define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) +/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. + */ #define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) + #define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) #define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) +/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. + */ #define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) + #define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) #define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) +/*! FIFO_EMPTY - FIFO is empty status. + */ #define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) + #define SDIF_STATUS_FIFO_FULL_MASK (0x8U) #define SDIF_STATUS_FIFO_FULL_SHIFT (3U) +/*! FIFO_FULL - FIFO is full status. + */ #define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) + #define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) #define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) +/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx + * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - + * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp + * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The + * command FSM state is represented using 19 bits. + */ #define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) + #define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) #define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) +/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. + */ #define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) + #define SDIF_STATUS_DATA_BUSY_MASK (0x200U) #define SDIF_STATUS_DATA_BUSY_SHIFT (9U) +/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. + */ #define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) + #define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) #define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) +/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. + */ #define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) + #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) #define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) +/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. + */ #define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) + #define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) #define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) +/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO. + */ #define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) + #define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) #define SDIF_STATUS_DMA_ACK_SHIFT (30U) +/*! DMA_ACK - DMA acknowledge signal state. + */ #define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) + #define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) #define SDIF_STATUS_DMA_REQ_SHIFT (31U) +/*! DMA_REQ - DMA request signal state. + */ #define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) /*! @} */ /*! @name FIFOTH - FIFO Threshold Watermark register */ /*! @{ */ + #define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) #define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) +/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card. + */ #define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) + #define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) #define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) +/*! RX_WMARK - FIFO threshold watermark level when receiving data to card. + */ #define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) + #define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) #define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) +/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller + * multiple-transaction-size SRC/DEST_MSIZE. + */ #define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) /*! @} */ /*! @name CDETECT - Card Detect register */ /*! @{ */ + #define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) #define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) +/*! CARD0_DETECT - Card 0 detect + */ #define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) + #define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) #define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) +/*! CARD1_DETECT - Card 1 detect + */ #define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) /*! @} */ /*! @name WRTPRT - Write Protect register */ /*! @{ */ + #define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) #define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) +/*! WRITE_PROTECT - Write protect. + */ #define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) /*! @} */ /*! @name TCBCNT - Transferred CIU Card Byte Count register */ /*! @{ */ + #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) +/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. + */ #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) /*! @} */ /*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ /*! @{ */ + #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) +/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. + */ #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) /*! @} */ /*! @name DEBNCE - Debounce Count register */ /*! @{ */ + #define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) #define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) +/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. + */ #define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) /*! @} */ /*! @name RST_N - Hardware Reset */ /*! @{ */ + #define SDIF_RST_N_CARD_RESET_MASK (0x1U) #define SDIF_RST_N_CARD_RESET_SHIFT (0U) +/*! CARD_RESET - Hardware reset. + */ #define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) /*! @} */ /*! @name BMOD - Bus Mode register */ /*! @{ */ + #define SDIF_BMOD_SWR_MASK (0x1U) #define SDIF_BMOD_SWR_SHIFT (0U) +/*! SWR - Software Reset. + */ #define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) + #define SDIF_BMOD_FB_MASK (0x2U) #define SDIF_BMOD_FB_SHIFT (1U) +/*! FB - Fixed Burst. + */ #define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) + #define SDIF_BMOD_DSL_MASK (0x7CU) #define SDIF_BMOD_DSL_SHIFT (2U) +/*! DSL - Descriptor Skip Length. + */ #define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) + #define SDIF_BMOD_DE_MASK (0x80U) #define SDIF_BMOD_DE_SHIFT (7U) +/*! DE - SD/MMC DMA Enable. + */ #define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) + #define SDIF_BMOD_PBL_MASK (0x700U) #define SDIF_BMOD_PBL_SHIFT (8U) +/*! PBL - Programmable Burst Length. + */ #define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) /*! @} */ /*! @name PLDMND - Poll Demand register */ /*! @{ */ + #define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) #define SDIF_PLDMND_PD_SHIFT (0U) +/*! PD - Poll Demand. + */ #define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) /*! @} */ /*! @name DBADDR - Descriptor List Base Address register */ /*! @{ */ + #define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) #define SDIF_DBADDR_SDL_SHIFT (0U) +/*! SDL - Start of Descriptor List. + */ #define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) /*! @} */ /*! @name IDSTS - Internal DMAC Status register */ /*! @{ */ + #define SDIF_IDSTS_TI_MASK (0x1U) #define SDIF_IDSTS_TI_SHIFT (0U) +/*! TI - Transmit Interrupt. + */ #define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) + #define SDIF_IDSTS_RI_MASK (0x2U) #define SDIF_IDSTS_RI_SHIFT (1U) +/*! RI - Receive Interrupt. + */ #define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) + #define SDIF_IDSTS_FBE_MASK (0x4U) #define SDIF_IDSTS_FBE_SHIFT (2U) +/*! FBE - Fatal Bus Error Interrupt. + */ #define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) + #define SDIF_IDSTS_DU_MASK (0x10U) #define SDIF_IDSTS_DU_SHIFT (4U) +/*! DU - Descriptor Unavailable Interrupt. + */ #define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) + #define SDIF_IDSTS_CES_MASK (0x20U) #define SDIF_IDSTS_CES_SHIFT (5U) +/*! CES - Card Error Summary. + */ #define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) + #define SDIF_IDSTS_NIS_MASK (0x100U) #define SDIF_IDSTS_NIS_SHIFT (8U) +/*! NIS - Normal Interrupt Summary. + */ #define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) + #define SDIF_IDSTS_AIS_MASK (0x200U) #define SDIF_IDSTS_AIS_SHIFT (9U) +/*! AIS - Abnormal Interrupt Summary. + */ #define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) + #define SDIF_IDSTS_EB_MASK (0x1C00U) #define SDIF_IDSTS_EB_SHIFT (10U) +/*! EB - Error Bits. + */ #define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) + #define SDIF_IDSTS_FSM_MASK (0x1E000U) #define SDIF_IDSTS_FSM_SHIFT (13U) +/*! FSM - DMAC state machine present state. + */ #define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) /*! @} */ /*! @name IDINTEN - Internal DMAC Interrupt Enable register */ /*! @{ */ + #define SDIF_IDINTEN_TI_MASK (0x1U) #define SDIF_IDINTEN_TI_SHIFT (0U) +/*! TI - Transmit Interrupt Enable. + */ #define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) + #define SDIF_IDINTEN_RI_MASK (0x2U) #define SDIF_IDINTEN_RI_SHIFT (1U) +/*! RI - Receive Interrupt Enable. + */ #define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) + #define SDIF_IDINTEN_FBE_MASK (0x4U) #define SDIF_IDINTEN_FBE_SHIFT (2U) +/*! FBE - Fatal Bus Error Enable. + */ #define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) + #define SDIF_IDINTEN_DU_MASK (0x10U) #define SDIF_IDINTEN_DU_SHIFT (4U) +/*! DU - Descriptor Unavailable Interrupt. + */ #define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) + #define SDIF_IDINTEN_CES_MASK (0x20U) #define SDIF_IDINTEN_CES_SHIFT (5U) +/*! CES - Card Error summary Interrupt Enable. + */ #define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) + #define SDIF_IDINTEN_NIS_MASK (0x100U) #define SDIF_IDINTEN_NIS_SHIFT (8U) +/*! NIS - Normal Interrupt Summary Enable. + */ #define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) + #define SDIF_IDINTEN_AIS_MASK (0x200U) #define SDIF_IDINTEN_AIS_SHIFT (9U) +/*! AIS - Abnormal Interrupt Summary Enable. + */ #define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) /*! @} */ /*! @name DSCADDR - Current Host Descriptor Address register */ /*! @{ */ + #define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) #define SDIF_DSCADDR_HDA_SHIFT (0U) +/*! HDA - Host Descriptor Address Pointer. + */ #define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) /*! @} */ /*! @name BUFADDR - Current Buffer Descriptor Address register */ /*! @{ */ + #define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) #define SDIF_BUFADDR_HBA_SHIFT (0U) +/*! HBA - Host Buffer Address Pointer. + */ #define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) /*! @} */ /*! @name CARDTHRCTL - Card Threshold Control */ /*! @{ */ + #define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) #define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) +/*! CARDRDTHREN - Card Read Threshold Enable. + */ #define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) + #define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) #define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) +/*! BSYCLRINTEN - Busy Clear Interrupt Enable. + */ #define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) + #define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) #define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) +/*! CARDTHRESHOLD - Card Threshold size. + */ #define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) /*! @} */ /*! @name BACKENDPWR - Power control */ /*! @{ */ + #define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) #define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) +/*! BACKENDPWR - Back-end Power control for card application. + */ #define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) /*! @} */ /*! @name FIFO - SDIF FIFO */ /*! @{ */ + #define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) #define SDIF_FIFO_DATA_SHIFT (0U) +/*! DATA - SDIF FIFO. + */ #define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) /*! @} */ @@ -16155,7 +20493,7 @@ typedef struct { /* SDIF - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral SDIF base address */ #define SDIF_BASE (0x5009B000u) /** Peripheral SDIF base address */ @@ -16224,7 +20562,9 @@ typedef struct { __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ uint8_t RESERVED_6[12]; __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_7[440]; + uint8_t RESERVED_7[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_8[432]; __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ } SPI_Type; @@ -16239,6 +20579,7 @@ typedef struct { /*! @name CFG - SPI Configuration register */ /*! @{ */ + #define SPI_CFG_ENABLE_MASK (0x1U) #define SPI_CFG_ENABLE_SHIFT (0U) /*! ENABLE - SPI enable. @@ -16246,6 +20587,7 @@ typedef struct { * 0b1..Enabled. The SPI is enabled for operation. */ #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) + #define SPI_CFG_MASTER_MASK (0x4U) #define SPI_CFG_MASTER_SHIFT (2U) /*! MASTER - Master mode select. @@ -16253,6 +20595,7 @@ typedef struct { * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. */ #define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) + #define SPI_CFG_LSBF_MASK (0x8U) #define SPI_CFG_LSBF_SHIFT (3U) /*! LSBF - LSB First mode enable. @@ -16260,6 +20603,7 @@ typedef struct { * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). */ #define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) + #define SPI_CFG_CPHA_MASK (0x10U) #define SPI_CFG_CPHA_SHIFT (4U) /*! CPHA - Clock Phase select. @@ -16269,6 +20613,7 @@ typedef struct { * changes away from the rest state). Data is captured on the following edge. */ #define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) + #define SPI_CFG_CPOL_MASK (0x20U) #define SPI_CFG_CPOL_SHIFT (5U) /*! CPOL - Clock Polarity select. @@ -16276,6 +20621,7 @@ typedef struct { * 0b1..High. The rest state of the clock (between transfers) is high. */ #define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) + #define SPI_CFG_LOOP_MASK (0x80U) #define SPI_CFG_LOOP_SHIFT (7U) /*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit @@ -16284,6 +20630,7 @@ typedef struct { * 0b1..Enabled. */ #define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) + #define SPI_CFG_SPOL0_MASK (0x100U) #define SPI_CFG_SPOL0_SHIFT (8U) /*! SPOL0 - SSEL0 Polarity select. @@ -16291,6 +20638,7 @@ typedef struct { * 0b1..High. The SSEL0 pin is active high. */ #define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) + #define SPI_CFG_SPOL1_MASK (0x200U) #define SPI_CFG_SPOL1_SHIFT (9U) /*! SPOL1 - SSEL1 Polarity select. @@ -16298,6 +20646,7 @@ typedef struct { * 0b1..High. The SSEL1 pin is active high. */ #define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) + #define SPI_CFG_SPOL2_MASK (0x400U) #define SPI_CFG_SPOL2_SHIFT (10U) /*! SPOL2 - SSEL2 Polarity select. @@ -16305,6 +20654,7 @@ typedef struct { * 0b1..High. The SSEL2 pin is active high. */ #define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) + #define SPI_CFG_SPOL3_MASK (0x800U) #define SPI_CFG_SPOL3_SHIFT (11U) /*! SPOL3 - SSEL3 Polarity select. @@ -16316,41 +20666,94 @@ typedef struct { /*! @name DLY - SPI Delay register */ /*! @{ */ + #define SPI_DLY_PRE_DELAY_MASK (0xFU) #define SPI_DLY_PRE_DELAY_SHIFT (0U) +/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data + * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This + * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI + * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are + * inserted. + */ #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) + #define SPI_DLY_POST_DELAY_MASK (0xF0U) #define SPI_DLY_POST_DELAY_SHIFT (4U) +/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL + * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock + * times are inserted. 0xF = 15 SPI clock times are inserted. + */ #define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) + #define SPI_DLY_FRAME_DELAY_MASK (0xF00U) #define SPI_DLY_FRAME_DELAY_SHIFT (8U) +/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current + * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 + * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock + * times are inserted. + */ #define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) + #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between + * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 + * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that + * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 + * SPI clock times. + */ #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) /*! @} */ /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ /*! @{ */ + #define SPI_STAT_SSA_MASK (0x10U) #define SPI_STAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from + * deasserted to asserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a + * slave mode access begins. This flag is cleared by software. + */ #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) + #define SPI_STAT_SSD_MASK (0x20U) #define SPI_STAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to + * deasserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become idle. This flag is cleared by software. + */ #define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) + #define SPI_STAT_STALLED_MASK (0x40U) #define SPI_STAT_STALLED_SHIFT (6U) +/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. + */ #define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) + #define SPI_STAT_ENDTRANSFER_MASK (0x80U) #define SPI_STAT_ENDTRANSFER_SHIFT (7U) +/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current + * transfer when the transmitter finishes any activity already in progress, as if the EOT flag + * had been set prior to the last transmission. This capability is included to support cases where + * it is not known when transmit data is written that it will be the end of a transfer. The bit + * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end + * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. + */ #define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) + #define SPI_STAT_MSTIDLE_MASK (0x100U) #define SPI_STAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. + * This means that the transmit holding register is empty and the transmitter is not in the + * process of sending data. + */ #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) /*! @} */ /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ /*! @{ */ + #define SPI_INTENSET_SSAEN_MASK (0x10U) #define SPI_INTENSET_SSAEN_SHIFT (4U) /*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. @@ -16358,6 +20761,7 @@ typedef struct { * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. */ #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) + #define SPI_INTENSET_SSDEN_MASK (0x20U) #define SPI_INTENSET_SSDEN_SHIFT (5U) /*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. @@ -16365,6 +20769,7 @@ typedef struct { * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. */ #define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) + #define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) #define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) /*! MSTIDLEEN - Master idle interrupt enable. @@ -16376,39 +20781,64 @@ typedef struct { /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ /*! @{ */ + #define SPI_INTENCLR_SSAEN_MASK (0x10U) #define SPI_INTENCLR_SSAEN_SHIFT (4U) +/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) + #define SPI_INTENCLR_SSDEN_MASK (0x20U) #define SPI_INTENCLR_SSDEN_SHIFT (5U) +/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) + #define SPI_INTENCLR_MSTIDLE_MASK (0x100U) #define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) /*! @} */ /*! @name DIV - SPI clock Divider */ /*! @{ */ + #define SPI_DIV_DIVVAL_MASK (0xFFFFU) #define SPI_DIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the + * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, + * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results + * in FCLK/65536. + */ #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) /*! @} */ /*! @name INTSTAT - SPI Interrupt Status */ /*! @{ */ + #define SPI_INTSTAT_SSA_MASK (0x10U) #define SPI_INTSTAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. + */ #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) + #define SPI_INTSTAT_SSD_MASK (0x20U) #define SPI_INTSTAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. + */ #define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) + #define SPI_INTSTAT_MSTIDLE_MASK (0x100U) #define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master Idle status flag. + */ #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) /*! @} */ /*! @name FIFOCFG - FIFO configuration and enable register. */ /*! @{ */ + #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) #define SPI_FIFOCFG_ENABLETX_SHIFT (0U) /*! ENABLETX - Enable the transmit FIFO. @@ -16416,6 +20846,7 @@ typedef struct { * 0b1..The transmit FIFO is enabled. */ #define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) + #define SPI_FIFOCFG_ENABLERX_MASK (0x2U) #define SPI_FIFOCFG_ENABLERX_SHIFT (1U) /*! ENABLERX - Enable the receive FIFO. @@ -16423,9 +20854,14 @@ typedef struct { * 0b1..The receive FIFO is enabled. */ #define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) + #define SPI_FIFOCFG_SIZE_MASK (0x30U) #define SPI_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ #define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) + #define SPI_FIFOCFG_DMATX_MASK (0x1000U) #define SPI_FIFOCFG_DMATX_SHIFT (12U) /*! DMATX - DMA configuration for transmit. @@ -16433,6 +20869,7 @@ typedef struct { * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. */ #define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) + #define SPI_FIFOCFG_DMARX_MASK (0x2000U) #define SPI_FIFOCFG_DMARX_SHIFT (13U) /*! DMARX - DMA configuration for receive. @@ -16440,6 +20877,7 @@ typedef struct { * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. */ #define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) + #define SPI_FIFOCFG_WAKETX_MASK (0x4000U) #define SPI_FIFOCFG_WAKETX_SHIFT (14U) /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power @@ -16452,6 +20890,7 @@ typedef struct { * FIFOTRIG, even when the TXLVL interrupt is not enabled. */ #define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) + #define SPI_FIFOCFG_WAKERX_MASK (0x8000U) #define SPI_FIFOCFG_WAKERX_SHIFT (15U) /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power @@ -16464,54 +20903,93 @@ typedef struct { * FIFOTRIG, even when the RXLVL interrupt is not enabled. */ #define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) + #define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) #define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ #define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) + #define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) #define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -#define SPI_FIFOCFG_POPDBG_MASK (0x40000U) -#define SPI_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. */ -#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK) +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) /*! @} */ /*! @name FIFOSTAT - FIFO status register. */ /*! @{ */ + #define SPI_FIFOSTAT_TXERR_MASK (0x1U) #define SPI_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ #define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) + #define SPI_FIFOSTAT_RXERR_MASK (0x2U) #define SPI_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ #define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) + #define SPI_FIFOSTAT_PERINT_MASK (0x8U) #define SPI_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ #define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) + #define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) #define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ #define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) + #define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) #define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ #define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) + #define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) #define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ #define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + #define SPI_FIFOSTAT_RXFULL_MASK (0x80U) #define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ #define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) + #define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) #define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ #define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) + #define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ #define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) /*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ /*! @{ */ + #define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) #define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -16520,6 +20998,7 @@ typedef struct { * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. */ #define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) + #define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) #define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -16528,16 +21007,32 @@ typedef struct { * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. */ #define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) + #define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) #define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ #define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) + #define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) #define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ #define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) /*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ /*! @{ */ + #define SPI_FIFOINTENSET_TXERR_MASK (0x1U) #define SPI_FIFOINTENSET_TXERR_SHIFT (0U) /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. @@ -16545,6 +21040,7 @@ typedef struct { * 0b1..An interrupt will be generated when a transmit error occurs. */ #define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) + #define SPI_FIFOINTENSET_RXERR_MASK (0x2U) #define SPI_FIFOINTENSET_RXERR_SHIFT (1U) /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. @@ -16552,6 +21048,7 @@ typedef struct { * 0b1..An interrupt will be generated when a receive error occurs. */ #define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) + #define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) #define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level @@ -16561,6 +21058,7 @@ typedef struct { * to the level specified by TXLVL in the FIFOTRIG register. */ #define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) + #define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) #define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level @@ -16574,44 +21072,75 @@ typedef struct { /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ /*! @{ */ + #define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) #define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) + #define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) #define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) + #define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) #define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) + #define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) #define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) /*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ /*! @{ */ + #define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) #define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ #define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) + #define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) #define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ #define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) + #define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) #define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ #define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) + #define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) #define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ #define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) + #define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) #define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ #define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) /*! @} */ /*! @name FIFOWR - FIFO write data. */ /*! @{ */ + #define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) #define SPI_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. + */ #define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) + #define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) #define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) /*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. @@ -16619,6 +21148,7 @@ typedef struct { * 0b1..SSEL0 not asserted. */ #define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) + #define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) #define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) /*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. @@ -16626,6 +21156,7 @@ typedef struct { * 0b1..SSEL1 not asserted. */ #define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) + #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) #define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) /*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. @@ -16633,6 +21164,7 @@ typedef struct { * 0b1..SSEL2 not asserted. */ #define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) + #define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) #define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) /*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. @@ -16640,6 +21172,7 @@ typedef struct { * 0b1..SSEL3 not asserted. */ #define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) + #define SPI_FIFOWR_EOT_MASK (0x100000U) #define SPI_FIFOWR_EOT_SHIFT (20U) /*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain @@ -16648,6 +21181,7 @@ typedef struct { * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. */ #define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) + #define SPI_FIFOWR_EOF_MASK (0x200000U) #define SPI_FIFOWR_EOF_SHIFT (21U) /*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value @@ -16659,6 +21193,7 @@ typedef struct { * inserted before subsequent data is transmitted. */ #define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) + #define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) #define SPI_FIFOWR_RXIGNORE_SHIFT (22U) /*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to @@ -16671,68 +21206,147 @@ typedef struct { * data. No receiver flags are generated. */ #define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) + #define SPI_FIFOWR_LEN_MASK (0xF000000U) #define SPI_FIFOWR_LEN_SHIFT (24U) +/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths + * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. + * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data + * transfer is 16 bits in length. + */ #define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) /*! @} */ /*! @name FIFORD - FIFO read data. */ /*! @{ */ + #define SPI_FIFORD_RXDATA_MASK (0xFFFFU) #define SPI_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ #define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) + #define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) #define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved + * along with received data. The value will reflect the SSEL0 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ #define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) + #define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) #define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved + * along with received data. The value will reflect the SSEL1 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ #define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) + #define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) #define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved + * along with received data. The value will reflect the SSEL2 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ #define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) + #define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) #define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved + * along with received data. The value will reflect the SSEL3 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ #define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) + #define SPI_FIFORD_SOT_MASK (0x100000U) #define SPI_FIFORD_SOT_SHIFT (20U) +/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went + * from deasserted to asserted (i.e., any previous transfer has ended). This information can be + * used to identify the first piece of data in cases where the transfer length is greater than 16 + * bits. + */ #define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) /*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ /*! @{ */ + #define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) #define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ #define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) + #define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) #define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. + */ #define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) + #define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) #define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. + */ #define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) + #define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) #define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. + */ #define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) + #define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) #define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. + */ #define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) + #define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) #define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +/*! SOT - Start of transfer flag. + */ #define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) /*! @} */ +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + /*! @name ID - Peripheral identification register. */ /*! @{ */ + #define SPI_ID_APERTURE_MASK (0xFFU) #define SPI_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ #define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) + #define SPI_ID_MINOR_REV_MASK (0xF00U) #define SPI_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ #define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) + #define SPI_ID_MAJOR_REV_MASK (0xF000U) #define SPI_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ #define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) + #define SPI_ID_ID_MASK (0xFFFF0000U) #define SPI_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ #define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) /*! @} */ @@ -16743,7 +21357,7 @@ typedef struct { /* SPI - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral SPI0 base address */ #define SPI0_BASE (0x50086000u) /** Peripheral SPI0 base address */ @@ -16891,7 +21505,7 @@ typedef struct { uint8_t RESERVED_1[36]; __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ - __IO uint32_t CPU1TCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ + __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ uint8_t RESERVED_2[4]; __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ uint8_t RESERVED_3[180]; @@ -16906,7 +21520,7 @@ typedef struct { uint8_t RESERVED_4[20]; __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ uint8_t RESERVED_5[20]; - __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset contro clearl register, array offset: 0x140, array step: 0x4 */ + __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ uint8_t RESERVED_6[20]; __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ uint8_t RESERVED_7[156]; @@ -16950,7 +21564,7 @@ typedef struct { uint8_t RESERVED_12[12]; __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ - __IO uint32_t USB1CLKSEL; /**< HS USB clock source select - NOT USED, offset: 0x2AC */ + uint8_t RESERVED_13[4]; union { /* offset: 0x2B0 */ struct { /* offset: 0x2B0 */ __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ @@ -16965,17 +21579,17 @@ typedef struct { __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ }; __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ - uint8_t RESERVED_13[12]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ uint8_t RESERVED_14[12]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_15[12]; __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ - uint8_t RESERVED_15[4]; - __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ uint8_t RESERVED_16[4]; + __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ + uint8_t RESERVED_17[4]; __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ - uint8_t RESERVED_17[20]; + uint8_t RESERVED_18[20]; union { /* offset: 0x320 */ struct { /* offset: 0x320 */ __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ @@ -16989,36 +21603,34 @@ typedef struct { } FLEXFRGCTRL; __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ }; - uint8_t RESERVED_18[64]; + uint8_t RESERVED_19[64]; __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ - uint8_t RESERVED_19[4]; + uint8_t RESERVED_20[4]; __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ - uint8_t RESERVED_20[16]; + uint8_t RESERVED_21[16]; __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_21[4]; - __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ uint8_t RESERVED_22[4]; - __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ + __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ uint8_t RESERVED_23[4]; + __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ + uint8_t RESERVED_24[4]; __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ - uint8_t RESERVED_24[52]; + uint8_t RESERVED_25[52]; __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ - __IO uint32_t FMCCR; /**< FMC configuration register - INTERNAL USE ONLY, offset: 0x400 */ - uint8_t RESERVED_25[8]; - __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */ - __I uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */ + __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ uint8_t RESERVED_26[8]; + __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */ + __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */ + uint8_t RESERVED_27[8]; __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ - __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */ - __I uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */ - uint8_t RESERVED_27[36]; - __IO uint32_t FLASHBANKENABLE; /**< Flash Banks control, offset: 0x450 */ - uint8_t RESERVED_28[12]; + __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */ + __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */ + uint8_t RESERVED_28[52]; __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ uint8_t RESERVED_29[252]; __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ @@ -17033,53 +21645,31 @@ typedef struct { __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ - uint8_t RESERVED_31[52]; - __IO uint32_t EFUSECLKCTRL; /**< eFUSE controller clock enable, offset: 0x5CC */ - uint8_t RESERVED_32[176]; - __IO uint32_t STARTER[2]; /**< Start logic wake-up enable register, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_33[24]; - __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */ - uint8_t RESERVED_34[24]; - __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER, array offset: 0x6C0, array step: 0x4 */ - uint8_t RESERVED_35[184]; - __IO uint32_t HARDWARESLEEP; /**< Hardware Sleep control, offset: 0x780 */ - uint8_t RESERVED_36[124]; + uint8_t RESERVED_31[364]; + __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control register, offset: 0x704 */ + uint8_t RESERVED_32[248]; __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ - __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ + uint8_t RESERVED_33[4]; __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ - uint8_t RESERVED_37[240]; - __IO uint32_t DICE_REG0; /**< Composite Device Identifier, offset: 0x900 */ - __IO uint32_t DICE_REG1; /**< Composite Device Identifier, offset: 0x904 */ - __IO uint32_t DICE_REG2; /**< Composite Device Identifier, offset: 0x908 */ - __IO uint32_t DICE_REG3; /**< Composite Device Identifier, offset: 0x90C */ - __IO uint32_t DICE_REG4; /**< Composite Device Identifier, offset: 0x910 */ - __IO uint32_t DICE_REG5; /**< Composite Device Identifier, offset: 0x914 */ - __IO uint32_t DICE_REG6; /**< Composite Device Identifier, offset: 0x918 */ - __IO uint32_t DICE_REG7; /**< Composite Device Identifier, offset: 0x91C */ - uint8_t RESERVED_38[248]; + uint8_t RESERVED_34[520]; __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ - uint8_t RESERVED_39[244]; + uint8_t RESERVED_35[244]; __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ - uint8_t RESERVED_40[748]; + uint8_t RESERVED_36[748]; __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ - uint8_t RESERVED_41[404]; - __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers -- FOR INTERNAl USE ONLY, offset: 0xFA0 */ - __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY, offset: 0xFA4 */ - __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY, offset: 0xFA8 */ - uint8_t RESERVED_42[4]; - __O uint32_t CODESECURITYPROTTEST; /**< Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY, offset: 0xFB0 */ - __O uint32_t CODESECURITYPROTCPU0; /**< Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB4 */ - __O uint32_t CODESECURITYPROTCPU1; /**< Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB8 */ - __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY, offset: 0xFBC */ - __IO uint32_t DEBUG_AUTH_SCRATCH; /**< Debug authentication scratch registers -- FOR INTERNAL USE ONLY, offset: 0xFC0 */ - uint8_t RESERVED_43[16]; + uint8_t RESERVED_37[404]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */ + uint8_t RESERVED_38[16]; + __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ + uint8_t RESERVED_39[16]; __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */ - uint8_t RESERVED_44[20]; - __IO uint32_t PERIPHENCFG; /**< peripheral enable configuration -- FOR INTERNAL USE ONLY, offset: 0xFEC */ - uint8_t RESERVED_45[8]; + uint8_t RESERVED_40[32]; __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ } SYSCON_Type; @@ -17095,6 +21685,7 @@ typedef struct { /*! @name MEMORYREMAP - Memory Remap control register */ /*! @{ */ + #define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) #define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) /*! MAP - Select the location of the vector table :. @@ -17108,104 +21699,176 @@ typedef struct { /*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ /*! @{ */ -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT (0U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT (2U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT (4U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT (6U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) +/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) +/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U) +/*! PRI_CPU1_CBUS - CPU1 C-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U) +/*! PRI_CPU1_SBUS - CPU1 S-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK) + #define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) #define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) +/*! PRI_USB_FS - USB-FS.(USB0) + */ #define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) + #define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) #define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) +/*! PRI_SDMA0 - DMA0 controller priority. + */ #define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK (0x3000U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT (12U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK (0xC000U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT (14U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK) + #define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) #define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) +/*! PRI_SDIO - SDIO. + */ #define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) + #define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) #define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) +/*! PRI_PQ - PQ (HW Accelerator). + */ #define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) -#define SYSCON_AHBMATPRIO_PRI_SHA2_MASK (0x300000U) -#define SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT (20U) -#define SYSCON_AHBMATPRIO_PRI_SHA2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA2_MASK) + +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U) +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U) +/*! PRI_HASH_AES - HASH_AES. + */ +#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) + #define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) #define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) +/*! PRI_USB_HS - USB-HS.(USB1) + */ #define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) + #define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) #define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) +/*! PRI_SDMA1 - DMA1 controller priority. + */ #define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) /*! @} */ /*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ /*! @{ */ -#define SYSCON_CPU0STCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU0STCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU0STCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_CAL_SHIFT)) & SYSCON_CPU0STCKCAL_CAL_MASK) + +#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) + #define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) #define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Initial value for the Systick timer. + */ #define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) + #define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) #define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference + * clock provided; 1 = no reference clock provided. + */ #define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) /*! @} */ /*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ /*! @{ */ -#define SYSCON_CPU0NSTCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU0NSTCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU0NSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_CAL_SHIFT)) & SYSCON_CPU0NSTCKCAL_CAL_MASK) + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + #define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) #define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. + */ #define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + #define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) #define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Initial value for the Systick timer. + */ #define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) /*! @} */ -/*! @name CPU1TCKCAL - System tick calibration for CPU1 */ +/*! @name CPU1STCKCAL - System tick calibration for CPU1 */ /*! @{ */ -#define SYSCON_CPU1TCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU1TCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU1TCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_CAL_SHIFT)) & SYSCON_CPU1TCKCAL_CAL_MASK) -#define SYSCON_CPU1TCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU1TCKCAL_SKEW_SHIFT (24U) -#define SYSCON_CPU1TCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_SKEW_SHIFT)) & SYSCON_CPU1TCKCAL_SKEW_MASK) -#define SYSCON_CPU1TCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU1TCKCAL_NOREF_SHIFT (25U) -#define SYSCON_CPU1TCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_NOREF_SHIFT)) & SYSCON_CPU1TCKCAL_NOREF_MASK) + +#define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK) + +#define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. + */ +#define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) + +#define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference + * clock provided; 1 = no reference clock provided. + */ +#define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) /*! @} */ /*! @name NMISRC - NMI Source Select */ /*! @{ */ + #define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) #define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. + */ #define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + #define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) #define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) +/*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. + */ #define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) + #define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) #define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) +/*! NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. + */ #define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) + #define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) #define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + */ #define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) /*! @} */ /*! @name PRESETCTRL0 - Peripheral reset control 0 */ /*! @{ */ + #define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) #define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) /*! ROM_RST - ROM reset control. @@ -17213,6 +21876,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) + #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) /*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. @@ -17220,6 +21884,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) + #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) /*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. @@ -17227,6 +21892,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) + #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) /*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. @@ -17234,6 +21900,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) + #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) /*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. @@ -17241,6 +21908,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) + #define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) #define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) /*! FLASH_RST - Flash controller reset control. @@ -17248,6 +21916,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) + #define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) #define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) /*! FMC_RST - FMC controller reset control. @@ -17255,13 +21924,15 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) -#define SYSCON_PRESETCTRL0_MUX0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL0_MUX0_RST_SHIFT (11U) -/*! MUX0_RST - Input Mux 0 reset control. + +#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) +/*! MUX_RST - Input Mux reset control. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL0_MUX0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX0_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX0_RST_MASK) +#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) + #define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) #define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) /*! IOCON_RST - I/O controller reset control. @@ -17269,6 +21940,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) + #define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) #define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) /*! GPIO0_RST - GPIO0 reset control. @@ -17276,6 +21948,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) + #define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) #define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) /*! GPIO1_RST - GPIO1 reset control. @@ -17283,6 +21956,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) + #define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) #define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) /*! GPIO2_RST - GPIO2 reset control. @@ -17290,6 +21964,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) + #define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) #define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) /*! GPIO3_RST - GPIO3 reset control. @@ -17297,6 +21972,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) + #define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) #define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) /*! PINT_RST - Pin interrupt (PINT) reset control. @@ -17304,6 +21980,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) + #define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) #define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) /*! GINT_RST - Group interrupt (GINT) reset control. @@ -17311,6 +21988,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) + #define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) #define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) /*! DMA0_RST - DMA0 reset control. @@ -17318,6 +21996,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) + #define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) #define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) /*! CRCGEN_RST - CRCGEN reset control. @@ -17325,6 +22004,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) + #define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) #define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) /*! WWDT_RST - Watchdog Timer reset control. @@ -17332,6 +22012,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) + #define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) #define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) /*! RTC_RST - Real Time Clock (RTC) reset control. @@ -17339,6 +22020,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) + #define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) #define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) /*! MAILBOX_RST - Inter CPU communication Mailbox reset control. @@ -17346,6 +22028,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) + #define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) #define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) /*! ADC_RST - ADC reset control. @@ -17357,6 +22040,7 @@ typedef struct { /*! @name PRESETCTRL1 - Peripheral reset control 1 */ /*! @{ */ + #define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) #define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) /*! MRT_RST - MRT reset control. @@ -17364,20 +22048,23 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) -#define SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT (1U) -/*! OSTIMER0_RST - OS Timer 0 reset control. + +#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) +/*! OSTIMER_RST - OS Event Timer reset control. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL1_OSTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK) -#define SYSCON_PRESETCTRL1_SCT0_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL1_SCT0_RST_SHIFT (2U) -/*! SCT0_RST - SCT0 reset control. +#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) + +#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) +/*! SCT_RST - SCT reset control. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL1_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT0_RST_MASK) +#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) + #define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) #define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) /*! SCTIPU_RST - SCTIPU reset control. @@ -17385,13 +22072,15 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) -#define SYSCON_PRESETCTRL1_UTICK0_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT (10U) -/*! UTICK0_RST - UTICK0 reset control. + +#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) +/*! UTICK_RST - UTICK reset control. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL1_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK0_RST_MASK) +#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) + #define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) #define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) /*! FC0_RST - FC0 reset control. @@ -17399,6 +22088,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) + #define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) #define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) /*! FC1_RST - FC1 reset control. @@ -17406,6 +22096,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) + #define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) #define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) /*! FC2_RST - FC2 reset control. @@ -17413,6 +22104,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) + #define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) #define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) /*! FC3_RST - FC3 reset control. @@ -17420,6 +22112,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) + #define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) #define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) /*! FC4_RST - FC4 reset control. @@ -17427,6 +22120,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) + #define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) #define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) /*! FC5_RST - FC5 reset control. @@ -17434,6 +22128,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) + #define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) #define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) /*! FC6_RST - FC6 reset control. @@ -17441,6 +22136,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) + #define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) #define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) /*! FC7_RST - FC7 reset control. @@ -17448,6 +22144,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) + #define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) #define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) /*! TIMER2_RST - Timer 2 reset control. @@ -17455,6 +22152,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) + #define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) #define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) /*! USB0_DEV_RST - USB0 DEV reset control. @@ -17462,6 +22160,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) + #define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) #define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) /*! TIMER0_RST - Timer 0 reset control. @@ -17469,6 +22168,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) + #define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) #define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) /*! TIMER1_RST - Timer 1 reset control. @@ -17476,31 +22176,11 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) -#define SYSCON_PRESETCTRL1_PVT_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL1_PVT_RST_SHIFT (28U) -/*! PVT_RST - PVT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_PVT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_PVT_RST_SHIFT)) & SYSCON_PRESETCTRL1_PVT_RST_MASK) -#define SYSCON_PRESETCTRL1_EZHA_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL1_EZHA_RST_SHIFT (30U) -/*! EZHA_RST - EZH a reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_EZHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHA_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHA_RST_MASK) -#define SYSCON_PRESETCTRL1_EZHB_RST_MASK (0x80000000U) -#define SYSCON_PRESETCTRL1_EZHB_RST_SHIFT (31U) -/*! EZHB_RST - EZH b reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_EZHB_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHB_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHB_RST_MASK) /*! @} */ /*! @name PRESETCTRL2 - Peripheral reset control 2 */ /*! @{ */ + #define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) #define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) /*! DMA1_RST - DMA1 reset control. @@ -17508,6 +22188,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) + #define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) #define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) /*! COMP_RST - Comparator reset control. @@ -17515,6 +22196,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) + #define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) #define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) /*! SDIO_RST - SDIO reset control. @@ -17522,6 +22204,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) + #define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) #define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) /*! USB1_HOST_RST - USB1 Host reset control. @@ -17529,6 +22212,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) + #define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) #define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) /*! USB1_DEV_RST - USB1 dev reset control. @@ -17536,6 +22220,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) + #define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) #define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) /*! USB1_RAM_RST - USB1 RAM reset control. @@ -17543,6 +22228,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) + #define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) #define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) /*! USB1_PHY_RST - USB1 PHY reset control. @@ -17550,6 +22236,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) + #define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) #define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) /*! FREQME_RST - Frequency meter reset control. @@ -17557,27 +22244,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO4_RST_MASK (0x200U) -#define SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT (9U) -/*! GPIO4_RST - GPIO4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO4_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO5_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT (10U) -/*! GPIO5_RST - GPIO5 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO5_RST_MASK) -#define SYSCON_PRESETCTRL2_OTP_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL2_OTP_RST_SHIFT (12U) -/*! OTP_RST - OTP reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL2_OTP_RST_MASK) + #define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) #define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) /*! RNG_RST - RNG reset control. @@ -17585,13 +22252,15 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) -#define SYSCON_PRESETCTRL2_MUX1_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL2_MUX1_RST_SHIFT (14U) -/*! MUX1_RST - Peripheral Input Mux 1 reset control. + +#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) +/*! SYSCTL_RST - SYSCTL Block reset. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL2_MUX1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_MUX1_RST_SHIFT)) & SYSCON_PRESETCTRL2_MUX1_RST_MASK) +#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) + #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) /*! USB0_HOSTM_RST - USB0 Host Master reset control. @@ -17599,6 +22268,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) + #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) /*! USB0_HOSTS_RST - USB0 Host Slave reset control. @@ -17606,13 +22276,15 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) -#define SYSCON_PRESETCTRL2_HASH0_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL2_HASH0_RST_SHIFT (18U) -/*! HASH0_RST - HASH0 reset control. + +#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) +/*! HASH_AES_RST - HASH_AES reset control. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL2_HASH0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH0_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH0_RST_MASK) +#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) + #define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) #define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) /*! PQ_RST - Power Quad reset control. @@ -17620,6 +22292,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) + #define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) #define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) /*! PLULUT_RST - PLU LUT reset control. @@ -17627,6 +22300,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) + #define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) #define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) /*! TIMER3_RST - Timer 3 reset control. @@ -17634,6 +22308,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) + #define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) #define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) /*! TIMER4_RST - Timer 4 reset control. @@ -17641,6 +22316,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) + #define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) #define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) /*! PUF_RST - PUF reset control reset control. @@ -17648,6 +22324,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) + #define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) #define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) /*! CASPER_RST - Casper reset control. @@ -17655,13 +22332,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) -#define SYSCON_PRESETCTRL2_CAPT0_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT (25U) -/*! CAPT0_RST - CAPT0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CAPT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT)) & SYSCON_PRESETCTRL2_CAPT0_RST_MASK) + #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) /*! ANALOG_CTRL_RST - analog control reset control. @@ -17669,6 +22340,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) + #define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) #define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) /*! HS_LSPI_RST - HS LSPI reset control. @@ -17676,6 +22348,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) + #define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) #define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) /*! GPIO_SEC_RST - GPIO secure reset control. @@ -17683,6 +22356,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) + #define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) #define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) /*! GPIO_SEC_INT_RST - GPIO secure int reset control. @@ -17694,8 +22368,11 @@ typedef struct { /*! @name PRESETCTRLX - Peripheral reset control register */ /*! @{ */ + #define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) /*! @} */ @@ -17704,18 +22381,24 @@ typedef struct { /*! @name PRESETCTRLSET - Peripheral reset control set register */ /*! @{ */ + #define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) /*! @} */ /* The count of SYSCON_PRESETCTRLSET */ #define SYSCON_PRESETCTRLSET_COUNT (3U) -/*! @name PRESETCTRLCLR - Peripheral reset contro clearl register */ +/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ /*! @{ */ + #define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) /*! @} */ @@ -17724,6 +22407,7 @@ typedef struct { /*! @name SWR_RESET - generate a software_reset */ /*! @{ */ + #define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) #define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) /*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. @@ -17735,6 +22419,7 @@ typedef struct { /*! @name AHBCLKCTRL0 - AHB Clock control 0 */ /*! @{ */ + #define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) #define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) /*! ROM - Enables the clock for the ROM. @@ -17742,6 +22427,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) + #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) /*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. @@ -17749,6 +22435,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) + #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) /*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. @@ -17756,6 +22443,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) + #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) /*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. @@ -17763,6 +22451,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) + #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) /*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. @@ -17770,6 +22459,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) + #define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) #define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) /*! FLASH - Enables the clock for the Flash controller. @@ -17777,6 +22467,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) + #define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) #define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) /*! FMC - Enables the clock for the FMC controller. @@ -17784,13 +22475,15 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) -#define SYSCON_AHBCLKCTRL0_MUX0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL0_MUX0_SHIFT (11U) -/*! MUX0 - Enables the clock for the Input Mux 0. + +#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) +/*! MUX - Enables the clock for the Input Mux. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX0_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX0_MASK) +#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) + #define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) #define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) /*! IOCON - Enables the clock for the I/O controller. @@ -17798,6 +22491,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) + #define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) #define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) /*! GPIO0 - Enables the clock for the GPIO0. @@ -17805,6 +22499,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) + #define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) #define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) /*! GPIO1 - Enables the clock for the GPIO1. @@ -17812,6 +22507,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) + #define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) #define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) /*! GPIO2 - Enables the clock for the GPIO2. @@ -17819,6 +22515,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) + #define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) #define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) /*! GPIO3 - Enables the clock for the GPIO3. @@ -17826,6 +22523,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) + #define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) #define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) /*! PINT - Enables the clock for the Pin interrupt (PINT). @@ -17833,6 +22531,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) + #define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) #define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) /*! GINT - Enables the clock for the Group interrupt (GINT). @@ -17840,6 +22539,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) + #define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) #define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) /*! DMA0 - Enables the clock for the DMA0. @@ -17847,6 +22547,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) + #define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) #define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) /*! CRCGEN - Enables the clock for the CRCGEN. @@ -17854,6 +22555,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) + #define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) #define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) /*! WWDT - Enables the clock for the Watchdog Timer. @@ -17861,6 +22563,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) + #define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) #define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) /*! RTC - Enables the clock for the Real Time Clock (RTC). @@ -17868,6 +22571,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) + #define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) #define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) /*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. @@ -17875,6 +22579,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) + #define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) #define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) /*! ADC - Enables the clock for the ADC. @@ -17886,6 +22591,7 @@ typedef struct { /*! @name AHBCLKCTRL1 - AHB Clock control 1 */ /*! @{ */ + #define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) #define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) /*! MRT - Enables the clock for the MRT. @@ -17893,34 +22599,31 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) -#define SYSCON_AHBCLKCTRL1_OSTIMER0_MASK (0x2U) -#define SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT (1U) -/*! OSTIMER0 - Enables the clock for the OS Timer 0. + +#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) +/*! OSTIMER - Enables the clock for the OS Event Timer. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER0_MASK) -#define SYSCON_AHBCLKCTRL1_SCT0_MASK (0x4U) -#define SYSCON_AHBCLKCTRL1_SCT0_SHIFT (2U) -/*! SCT0 - Enables the clock for the SCT0. +#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) + +#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) +#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) +/*! SCT - Enables the clock for the SCT. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL1_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT0_MASK) -#define SYSCON_AHBCLKCTRL1_SCTIPU_MASK (0x40U) -#define SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT (6U) -/*! SCTIPU - Enables the clock for the SCTIPU. +#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) + +#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) +/*! UTICK - Enables the clock for the UTICK. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL1_SCTIPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT)) & SYSCON_AHBCLKCTRL1_SCTIPU_MASK) -#define SYSCON_AHBCLKCTRL1_UTICK0_MASK (0x400U) -#define SYSCON_AHBCLKCTRL1_UTICK0_SHIFT (10U) -/*! UTICK0 - Enables the clock for the UTICK0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK0_MASK) +#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) + #define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) #define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) /*! FC0 - Enables the clock for the FC0. @@ -17928,6 +22631,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) + #define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) #define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) /*! FC1 - Enables the clock for the FC1. @@ -17935,6 +22639,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) + #define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) #define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) /*! FC2 - Enables the clock for the FC2. @@ -17942,6 +22647,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) + #define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) #define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) /*! FC3 - Enables the clock for the FC3. @@ -17949,6 +22655,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) + #define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) #define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) /*! FC4 - Enables the clock for the FC4. @@ -17956,6 +22663,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) + #define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) #define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) /*! FC5 - Enables the clock for the FC5. @@ -17963,6 +22671,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) + #define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) #define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) /*! FC6 - Enables the clock for the FC6. @@ -17970,6 +22679,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) + #define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) #define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) /*! FC7 - Enables the clock for the FC7. @@ -17977,6 +22687,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) + #define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) #define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) /*! TIMER2 - Enables the clock for the Timer 2. @@ -17984,6 +22695,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) + #define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) #define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) /*! USB0_DEV - Enables the clock for the USB0 DEV. @@ -17991,6 +22703,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) + #define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) #define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) /*! TIMER0 - Enables the clock for the Timer 0. @@ -17998,6 +22711,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) + #define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) #define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) /*! TIMER1 - Enables the clock for the Timer 1. @@ -18005,31 +22719,11 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) -#define SYSCON_AHBCLKCTRL1_PVT_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL1_PVT_SHIFT (28U) -/*! PVT - Enables the clock for the PVT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_PVT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PVT_SHIFT)) & SYSCON_AHBCLKCTRL1_PVT_MASK) -#define SYSCON_AHBCLKCTRL1_EZHA_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL1_EZHA_SHIFT (30U) -/*! EZHA - Enables the clock for the EZH a. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_EZHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHA_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHA_MASK) -#define SYSCON_AHBCLKCTRL1_EZHB_MASK (0x80000000U) -#define SYSCON_AHBCLKCTRL1_EZHB_SHIFT (31U) -/*! EZHB - Enables the clock for the EZH b. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_EZHB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHB_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHB_MASK) /*! @} */ /*! @name AHBCLKCTRL2 - AHB Clock control 2 */ /*! @{ */ + #define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) #define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) /*! DMA1 - Enables the clock for the DMA1. @@ -18037,6 +22731,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) + #define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) #define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) /*! COMP - Enables the clock for the Comparator. @@ -18044,6 +22739,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) + #define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) #define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) /*! SDIO - Enables the clock for the SDIO. @@ -18051,6 +22747,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) + #define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) #define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) /*! USB1_HOST - Enables the clock for the USB1 Host. @@ -18058,6 +22755,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) + #define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) #define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) /*! USB1_DEV - Enables the clock for the USB1 dev. @@ -18065,6 +22763,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) + #define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) #define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) /*! USB1_RAM - Enables the clock for the USB1 RAM. @@ -18072,6 +22771,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) + #define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) #define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) /*! USB1_PHY - Enables the clock for the USB1 PHY. @@ -18079,6 +22779,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) + #define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) #define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) /*! FREQME - Enables the clock for the Frequency meter. @@ -18086,27 +22787,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO4_MASK (0x200U) -#define SYSCON_AHBCLKCTRL2_GPIO4_SHIFT (9U) -/*! GPIO4 - Enables the clock for the GPIO4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO4_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO5_MASK (0x400U) -#define SYSCON_AHBCLKCTRL2_GPIO5_SHIFT (10U) -/*! GPIO5 - Enables the clock for the GPIO5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO5_MASK) -#define SYSCON_AHBCLKCTRL2_OTP_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL2_OTP_SHIFT (12U) -/*! OTP - Enables the clock for the OTP. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_OTP_SHIFT)) & SYSCON_AHBCLKCTRL2_OTP_MASK) + #define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) #define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) /*! RNG - Enables the clock for the RNG. @@ -18114,13 +22795,15 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) -#define SYSCON_AHBCLKCTRL2_MUX1_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL2_MUX1_SHIFT (14U) -/*! MUX1 - Enables the clock for the Peripheral Input Mux 1. + +#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) +/*! SYSCTL - SYSCTL block clock. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL2_MUX1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_MUX1_SHIFT)) & SYSCON_AHBCLKCTRL2_MUX1_MASK) +#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) + #define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) #define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) /*! USB0_HOSTM - Enables the clock for the USB0 Host Master. @@ -18128,6 +22811,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) + #define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) #define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) /*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. @@ -18135,13 +22819,15 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) -#define SYSCON_AHBCLKCTRL2_HASH0_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL2_HASH0_SHIFT (18U) -/*! HASH0 - Enables the clock for the HASH0. + +#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) +/*! HASH_AES - Enables the clock for the HASH_AES. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL2_HASH0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH0_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH0_MASK) +#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) + #define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) #define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) /*! PQ - Enables the clock for the Power Quad. @@ -18149,6 +22835,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) + #define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) #define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) /*! PLULUT - Enables the clock for the PLU LUT. @@ -18156,6 +22843,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) + #define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) #define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) /*! TIMER3 - Enables the clock for the Timer 3. @@ -18163,6 +22851,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) + #define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) #define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) /*! TIMER4 - Enables the clock for the Timer 4. @@ -18170,6 +22859,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) + #define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) #define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) /*! PUF - Enables the clock for the PUF reset control. @@ -18177,6 +22867,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) + #define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) #define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) /*! CASPER - Enables the clock for the Casper. @@ -18184,13 +22875,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) -#define SYSCON_AHBCLKCTRL2_CAPT0_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL2_CAPT0_SHIFT (25U) -/*! CAPT0 - Enables the clock for the CAPT0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CAPT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CAPT0_SHIFT)) & SYSCON_AHBCLKCTRL2_CAPT0_MASK) + #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) /*! ANALOG_CTRL - Enables the clock for the analog control. @@ -18198,6 +22883,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) + #define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) #define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) /*! HS_LSPI - Enables the clock for the HS LSPI. @@ -18205,6 +22891,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) + #define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) #define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) /*! GPIO_SEC - Enables the clock for the GPIO secure. @@ -18212,6 +22899,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) + #define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) #define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) /*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. @@ -18223,8 +22911,11 @@ typedef struct { /*! @name AHBCLKCTRLX - Peripheral reset control register */ /*! @{ */ + #define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) /*! @} */ @@ -18233,8 +22924,11 @@ typedef struct { /*! @name AHBCLKCTRLSET - Peripheral reset control register */ /*! @{ */ + #define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) /*! @} */ @@ -18243,8 +22937,11 @@ typedef struct { /*! @name AHBCLKCTRLCLR - Peripheral reset control register */ /*! @{ */ + #define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) /*! @} */ @@ -18253,6 +22950,7 @@ typedef struct { /*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ /*! @{ */ + #define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) #define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) /*! SEL - System Tick Timer for CPU0 source select. @@ -18270,6 +22968,7 @@ typedef struct { /*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ /*! @{ */ + #define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) #define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) /*! SEL - System Tick Timer for CPU1 source select. @@ -18287,8 +22986,11 @@ typedef struct { /*! @name SYSTICKCLKSELX - Peripheral reset control register */ /*! @{ */ + #define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) #define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) /*! @} */ @@ -18297,6 +22999,7 @@ typedef struct { /*! @name TRACECLKSEL - Trace clock source select */ /*! @{ */ + #define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) #define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) /*! SEL - Trace clock source select. @@ -18314,6 +23017,7 @@ typedef struct { /*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ /*! @{ */ + #define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) #define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) /*! SEL - CTimer 0 clock source select. @@ -18331,6 +23035,7 @@ typedef struct { /*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ /*! @{ */ + #define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) #define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) /*! SEL - CTimer 1 clock source select. @@ -18348,6 +23053,7 @@ typedef struct { /*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ /*! @{ */ + #define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) #define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) /*! SEL - CTimer 2 clock source select. @@ -18365,6 +23071,7 @@ typedef struct { /*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ /*! @{ */ + #define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) #define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) /*! SEL - CTimer 3 clock source select. @@ -18382,6 +23089,7 @@ typedef struct { /*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ /*! @{ */ + #define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) #define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) /*! SEL - CTimer 4 clock source select. @@ -18399,8 +23107,11 @@ typedef struct { /*! @name CTIMERCLKSELX - Peripheral reset control register */ /*! @{ */ + #define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) #define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) /*! @} */ @@ -18409,6 +23120,7 @@ typedef struct { /*! @name MAINCLKSELA - Main clock A source select */ /*! @{ */ + #define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) #define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) /*! SEL - Main clock A source select. @@ -18416,16 +23128,17 @@ typedef struct { * 0b001..CLKIN clock. * 0b010..FRO 1MHz clock. * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. */ #define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) /*! @} */ /*! @name MAINCLKSELB - Main clock source select */ /*! @{ */ + #define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) #define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) /*! SEL - Main clock source select. @@ -18433,16 +23146,17 @@ typedef struct { * 0b001..PLL0 clock. * 0b010..PLL1 clock. * 0b011..Oscillator 32 kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. */ #define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) /*! @} */ /*! @name CLKOUTSEL - CLKOUT clock source select */ /*! @{ */ + #define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) #define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) /*! SEL - CLKOUT clock source select. @@ -18460,6 +23174,7 @@ typedef struct { /*! @name PLL0CLKSEL - PLL0 clock source select */ /*! @{ */ + #define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) #define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) /*! SEL - PLL0 clock source select. @@ -18477,6 +23192,7 @@ typedef struct { /*! @name PLL1CLKSEL - PLL1 clock source select */ /*! @{ */ + #define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) #define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) /*! SEL - PLL1 clock source select. @@ -18494,13 +23210,14 @@ typedef struct { /*! @name ADCCLKSEL - ADC clock source select */ /*! @{ */ + #define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) /*! SEL - ADC clock source select. * 0b000..Main clock. * 0b001..PLL0 clock. * 0b010..FRO 96 MHz clock. - * 0b011..No clock. + * 0b011..Reserved. * 0b100..No clock. * 0b101..No clock. * 0b110..No clock. @@ -18511,6 +23228,7 @@ typedef struct { /*! @name USB0CLKSEL - FS USB clock source select */ /*! @{ */ + #define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) #define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) /*! SEL - FS USB clock source select. @@ -18526,25 +23244,9 @@ typedef struct { #define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) /*! @} */ -/*! @name USB1CLKSEL - HS USB clock source select - NOT USED */ -/*! @{ */ -#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U) -/*! SEL - HS USB clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK) -/*! @} */ - /*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. @@ -18562,6 +23264,7 @@ typedef struct { /*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. @@ -18579,6 +23282,7 @@ typedef struct { /*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. @@ -18596,6 +23300,7 @@ typedef struct { /*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. @@ -18613,6 +23318,7 @@ typedef struct { /*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. @@ -18630,6 +23336,7 @@ typedef struct { /*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. @@ -18647,6 +23354,7 @@ typedef struct { /*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. @@ -18664,6 +23372,7 @@ typedef struct { /*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. @@ -18681,8 +23390,11 @@ typedef struct { /*! @name FCCLKSELX - Peripheral reset control register */ /*! @{ */ + #define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) #define SYSCON_FCCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) /*! @} */ @@ -18691,6 +23403,7 @@ typedef struct { /*! @name HSLSPICLKSEL - HS LSPI clock source select */ /*! @{ */ + #define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) #define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) /*! SEL - HS LSPI clock source select. @@ -18708,13 +23421,14 @@ typedef struct { /*! @name MCLKCLKSEL - MCLK clock source select */ /*! @{ */ + #define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) #define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) /*! SEL - MCLK clock source select. * 0b000..FRO 96 MHz clock. * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..No clock. + * 0b010..Reserved. + * 0b011..Reserved. * 0b100..No clock. * 0b101..No clock. * 0b110..No clock. @@ -18725,6 +23439,7 @@ typedef struct { /*! @name SCTCLKSEL - SCTimer/PWM clock source select */ /*! @{ */ + #define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) #define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) /*! SEL - SCTimer/PWM clock source select. @@ -18742,6 +23457,7 @@ typedef struct { /*! @name SDIOCLKSEL - SDIO clock source select */ /*! @{ */ + #define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) #define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) /*! SEL - SDIO clock source select. @@ -18759,9 +23475,13 @@ typedef struct { /*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ /*! @{ */ + #define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) #define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) + #define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) #define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18769,6 +23489,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) + #define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) #define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -18776,6 +23497,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) + #define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) #define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -18787,9 +23509,13 @@ typedef struct { /*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ /*! @{ */ + #define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) #define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) + #define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) #define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18797,6 +23523,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) + #define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) #define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -18804,6 +23531,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) + #define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) #define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -18815,9 +23543,13 @@ typedef struct { /*! @name TRACECLKDIV - TRACE clock divider */ /*! @{ */ + #define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) #define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) + #define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) #define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18825,6 +23557,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) + #define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) #define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -18832,6 +23565,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) + #define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -18843,88 +23577,139 @@ typedef struct { /*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ /*! @{ */ + #define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) + #define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ /*! @{ */ + #define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) + #define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ /*! @{ */ + #define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) + #define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ /*! @{ */ + #define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) + #define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ /*! @{ */ + #define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) + #define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ /*! @{ */ + #define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) + #define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ /*! @{ */ + #define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) + #define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ /*! @{ */ + #define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) + #define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRGXCTRL - Peripheral reset control register */ /*! @{ */ + #define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) #define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) /*! @} */ @@ -18933,9 +23718,13 @@ typedef struct { /*! @name AHBCLKDIV - System clock divider */ /*! @{ */ + #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) #define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + #define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18943,6 +23732,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) + #define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -18950,6 +23740,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) + #define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -18961,9 +23752,13 @@ typedef struct { /*! @name CLKOUTDIV - CLKOUT clock divider */ /*! @{ */ + #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) + #define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) #define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18971,6 +23766,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) + #define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) #define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -18978,6 +23774,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) + #define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -18989,9 +23786,13 @@ typedef struct { /*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ /*! @{ */ + #define SYSCON_FROHFDIV_DIV_MASK (0xFFU) #define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + #define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) #define SYSCON_FROHFDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18999,6 +23800,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) + #define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) #define SYSCON_FROHFDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19006,6 +23808,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + #define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19017,9 +23820,13 @@ typedef struct { /*! @name WDTCLKDIV - WDT clock divider */ /*! @{ */ + #define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) #define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) + #define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19027,6 +23834,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) + #define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19034,6 +23842,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) + #define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19045,9 +23854,13 @@ typedef struct { /*! @name ADCCLKDIV - ADC clock divider */ /*! @{ */ + #define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) + #define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19055,6 +23868,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) + #define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19062,6 +23876,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) + #define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19073,9 +23888,13 @@ typedef struct { /*! @name USB0CLKDIV - USB0 Clock divider */ /*! @{ */ + #define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) #define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) + #define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19083,6 +23902,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) + #define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19090,6 +23910,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) + #define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19101,9 +23922,13 @@ typedef struct { /*! @name MCLKDIV - I2S MCLK clock divider */ /*! @{ */ + #define SYSCON_MCLKDIV_DIV_MASK (0xFFU) #define SYSCON_MCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) + #define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_MCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19111,6 +23936,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) + #define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_MCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19118,6 +23944,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) + #define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19129,9 +23956,13 @@ typedef struct { /*! @name SCTCLKDIV - SCT/PWM clock divider */ /*! @{ */ + #define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) #define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) + #define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19139,6 +23970,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) + #define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19146,6 +23978,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) + #define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19157,9 +23990,13 @@ typedef struct { /*! @name SDIOCLKDIV - SDIO clock divider */ /*! @{ */ + #define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) #define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) + #define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19167,6 +24004,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) + #define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19174,6 +24012,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) + #define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19185,9 +24024,13 @@ typedef struct { /*! @name PLL0CLKDIV - PLL0 clock divider */ /*! @{ */ + #define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) #define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) + #define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19195,6 +24038,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) + #define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19202,6 +24046,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) + #define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19213,6 +24058,7 @@ typedef struct { /*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ /*! @{ */ + #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) /*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). @@ -19222,211 +24068,218 @@ typedef struct { #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) /*! @} */ -/*! @name FMCCR - FMC configuration register - INTERNAL USE ONLY */ +/*! @name FMCCR - FMC configuration register */ /*! @{ */ -#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) -#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) -#define SYSCON_FMCCR_FETCHCTL_MASK (0x3U) -#define SYSCON_FMCCR_FETCHCTL_SHIFT (0U) -/*! FETCHCTL - Fetch control - * 0b00..No buffering (bypass always used) for Fetch cycles - * 0b01..One buffer is used for all Fetch cycles - * 0b10..All buffers can be used for Fetch cycles +#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) +#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) +/*! FETCHCFG - Instruction fetch configuration. + * 0b00..Instruction fetches from flash are not buffered. + * 0b01..One buffer is used for all instruction fetches. + * 0b10..All buffers may be used for instruction fetches. */ -#define SYSCON_FMCCR_FETCHCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCTL_SHIFT)) & SYSCON_FMCCR_FETCHCTL_MASK) -#define SYSCON_FMCCR_DATACTL_MASK (0xCU) -#define SYSCON_FMCCR_DATACTL_SHIFT (2U) -/*! DATACTL - Data control - * 0b00..No buffering (bypass always used) for Data cycles - * 0b01..One buffer is used for all Data cycles - * 0b10..All buffers can be used for Data cycles +#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) + +#define SYSCON_FMCCR_DATACFG_MASK (0xCU) +#define SYSCON_FMCCR_DATACFG_SHIFT (2U) +/*! DATACFG - Data read configuration. + * 0b00..Data accesses from flash are not buffered. + * 0b01..One buffer is used for all data accesses. + * 0b10..All buffers can be used for data accesses. */ -#define SYSCON_FMCCR_DATACTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACTL_SHIFT)) & SYSCON_FMCCR_DATACTL_MASK) +#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) + #define SYSCON_FMCCR_ACCEL_MASK (0x10U) #define SYSCON_FMCCR_ACCEL_SHIFT (4U) +/*! ACCEL - Acceleration enable. + * 0b0..Flash acceleration is disabled. + * 0b1..Flash acceleration is enabled. + */ #define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) + #define SYSCON_FMCCR_PREFEN_MASK (0x20U) #define SYSCON_FMCCR_PREFEN_SHIFT (5U) +/*! PREFEN - Prefetch enable. + * 0b0..No instruction prefetch is performed. + * 0b1..Instruction prefetch is enabled. + */ #define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) + #define SYSCON_FMCCR_PREFOVR_MASK (0x40U) #define SYSCON_FMCCR_PREFOVR_SHIFT (6U) +/*! PREFOVR - Prefetch override. + * 0b0..Any previously initiated prefetch will be completed. + * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current + * execution address will be prefetched if not already buffered. + */ #define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) -#define SYSCON_FMCCR_PREFCRI_MASK (0x700U) -#define SYSCON_FMCCR_PREFCRI_SHIFT (8U) -#define SYSCON_FMCCR_PREFCRI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFCRI_SHIFT)) & SYSCON_FMCCR_PREFCRI_MASK) -#define SYSCON_FMCCR_FMCTIM_MASK (0x1F000U) -#define SYSCON_FMCCR_FMCTIM_SHIFT (12U) -#define SYSCON_FMCCR_FMCTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FMCTIM_SHIFT)) & SYSCON_FMCCR_FMCTIM_MASK) -#define SYSCON_FMCCR_PFISLRU_MASK (0x20000U) -#define SYSCON_FMCCR_PFISLRU_SHIFT (17U) -#define SYSCON_FMCCR_PFISLRU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFISLRU_SHIFT)) & SYSCON_FMCCR_PFISLRU_MASK) -#define SYSCON_FMCCR_PFADAP_MASK (0x40000U) -#define SYSCON_FMCCR_PFADAP_SHIFT (18U) -#define SYSCON_FMCCR_PFADAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFADAP_SHIFT)) & SYSCON_FMCCR_PFADAP_MASK) + +#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) +#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) +/*! FLASHTIM - Flash memory access time. + * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). + * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). + * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). + * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). + * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). + * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). + * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). + * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). + * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). + * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz). + * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz). + * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). + */ +#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) /*! @} */ -/*! @name USB0CLKCTRL - USB0 clock control */ +/*! @name USB0NEEDCLKCTRL - USB0 need clock control */ /*! @{ */ -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) -/*! AP_FS_DEV_CLK - USB0 Device USB0_NEEDCLK signal control:. + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. * 0b0..Under hardware control. * 0b1..Forced high. */ -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK) -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) -/*! POL_FS_DEV_CLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. */ -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK) -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) -/*! AP_FS_HOST_CLK - USB0 Host USB0_NEEDCLK signal control:. +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. * 0b0..Under hardware control. * 0b1..Forced high. */ -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK) -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) -/*! POL_FS_HOST_CLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. */ -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK) -#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U) -#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U) -/*! PU_DISABLE - Internal pull-up disable control. - * 0b1..Internal pull-up disable. - * 0b0..Internal pull-up enable. - */ -#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) /*! @} */ -/*! @name USB0CLKSTAT - USB0 clock status */ +/*! @name USB0NEEDCLKSTAT - USB0 need clock status */ /*! @{ */ -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) -/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status:. + +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. * 0b1..USB0 Device clock is high. * 0b0..USB0 Device clock is low. */ -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK) -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) -/*! HOST_NEED_CLKST - USB0 Host USB0_NEEDCLK signal status:. +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. * 0b1..USB0 Host clock is high. * 0b0..USB0 Host clock is low. */ -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK) +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) /*! @} */ /*! @name FMCFLUSH - FMCflush control */ /*! @{ */ + #define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) #define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) +/*! FLUSH - Flush control + * 0b1..Flush the FMC buffer contents. + * 0b0..No action is performed. + */ #define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) /*! @} */ /*! @name MCLKIO - MCLK control */ /*! @{ */ -#define SYSCON_MCLKIO_MCLKIO_MASK (0xFFFFFFFFU) + +#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) #define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) /*! MCLKIO - MCLK control. - * 0b00000000000000000000000000000000..input mode. - * 0b00000000000000000000000000000001..output mode. + * 0b0..input mode. + * 0b1..output mode. */ #define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) /*! @} */ -/*! @name USB1CLKCTRL - USB1 clock control */ +/*! @name USB1NEEDCLKCTRL - USB1 need clock control */ /*! @{ */ -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK (0x1U) -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT (0U) -/*! AP_HS_DEV_CLK - USB1 Device need_clock signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. */ -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK) -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK (0x2U) -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT (1U) -/*! POL_HS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt:. - * 0b0..Falling edge of device need_clock triggers wake-up. - * 0b1..Rising edge of device need_clock triggers wake-up. +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: + * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. + * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. */ -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK) -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK (0x4U) -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT (2U) -/*! AP_HS_HOST_CLK - USB1 Host need_clock signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. */ -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK) -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK (0x8U) -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT (3U) -/*! POL_HS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt: 0 - * Falling edge of device need_clock triggers wake-up. - * 0b0..Falling edge of device need_clock triggers wake-up. - * 0b1..Rising edge of device need_clock triggers wake-up. +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. + * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. + * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. */ -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK) -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) -/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active - * low) will result in exiting the low power mode; input to synchronous control logic:. - * 0b0..Forces USB1 PHY to wake-up. - * 0b1..Normal USB1 PHY behavior. +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) +/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. + * 0b0..Forces USB1_PHY to wake-up. + * 0b1..Normal USB1_PHY behavior. */ -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK) +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) /*! @} */ -/*! @name USB1CLKSTAT - USB1 clock status */ +/*! @name USB1NEEDCLKSTAT - USB1 need clock status */ /*! @{ */ -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) -/*! DEV_NEED_CLKST - USB1 Device need_clock signal status:. - * 0b1..USB1 Device clock is high. - * 0b0..USB1 Device clock is low. - */ -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK) -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) -/*! HOST_NEED_CLKST - USB1 Host need_clock signal status:. - * 0b1..USB1 Host clock is high. - * 0b0..USB1 Host clock is low. - */ -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK) -/*! @} */ -/*! @name FLASHBANKENABLE - Flash Banks control */ -/*! @{ */ -#define SYSCON_FLASHBANKENABLE_BANK0_MASK (0xFU) -#define SYSCON_FLASHBANKENABLE_BANK0_SHIFT (0U) -/*! BANK0 - Flash Bank0 control. - * 0b0000..Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased and programmed). +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB1 Device need_clock signal status:. + * 0b1..DEV_NEEDCLK is high. + * 0b0..DEV_NEEDCLK is low. */ -#define SYSCON_FLASHBANKENABLE_BANK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK0_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK0_MASK) -#define SYSCON_FLASHBANKENABLE_BANK1_MASK (0xF0U) -#define SYSCON_FLASHBANKENABLE_BANK1_SHIFT (4U) -/*! BANK1 - Flash Bank1 control. - * 0b0000..Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased and programmed). +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB1 Host need_clock signal status:. + * 0b1..HOST_NEEDCLK is high. + * 0b0..HOST_NEEDCLK is low. */ -#define SYSCON_FLASHBANKENABLE_BANK1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK1_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK1_MASK) -#define SYSCON_FLASHBANKENABLE_BANK2_MASK (0xF00U) -#define SYSCON_FLASHBANKENABLE_BANK2_SHIFT (8U) -/*! BANK2 - Flash Bank2 control. - * 0b0000..Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased and programmed). - */ -#define SYSCON_FLASHBANKENABLE_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK2_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK2_MASK) +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) /*! @} */ /*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ /*! @{ */ + #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) /*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. @@ -19436,6 +24289,7 @@ typedef struct { * 0b11..270 degree shift. */ #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) + #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) /*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. @@ -19445,6 +24299,7 @@ typedef struct { * 0b11..270 degree shift. */ #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) + #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) /*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. @@ -19452,9 +24307,13 @@ typedef struct { * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. */ #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) + #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) +/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. + */ #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) + #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) /*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. @@ -19462,9 +24321,13 @@ typedef struct { * 0b0..Disable drive delay. */ #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) + #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) +/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + */ #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) + #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) /*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. @@ -19476,15 +24339,25 @@ typedef struct { /*! @name PLL1CTRL - PLL1 550m control */ /*! @{ */ + #define SYSCON_PLL1CTRL_SELR_MASK (0xFU) #define SYSCON_PLL1CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ #define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) + #define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) #define SYSCON_PLL1CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ #define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) + #define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) #define SYSCON_PLL1CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ #define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) + #define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) #define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) /*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). @@ -19492,6 +24365,7 @@ typedef struct { * 0b0..use PLL. */ #define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) + #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) /*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. @@ -19499,9 +24373,13 @@ typedef struct { * 0b0..use the divide-by-2 divider in the post-divider. */ #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) + #define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) #define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ #define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) + #define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) #define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) /*! BWDIRECT - control of the bandwidth of the PLL. @@ -19509,6 +24387,7 @@ typedef struct { * 0b0..the bandwidth is changed synchronously with the feedback-divider. */ #define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) + #define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) #define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) /*! BYPASSPREDIV - bypass of the pre-divider. @@ -19516,6 +24395,7 @@ typedef struct { * 0b0..use the pre-divider. */ #define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) + #define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) #define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) /*! BYPASSPOSTDIV - bypass of the post-divider. @@ -19523,6 +24403,7 @@ typedef struct { * 0b0..use the post-divider. */ #define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) + #define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) #define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) /*! CLKEN - enable the output clock. @@ -19530,12 +24411,19 @@ typedef struct { * 0b0..Disable the output clock. */ #define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) + #define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) #define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - 1: free running mode. + */ #define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) + #define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) #define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. + */ #define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) + #define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) #define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) /*! SKEWEN - Skew mode. @@ -19547,64 +24435,107 @@ typedef struct { /*! @name PLL1STAT - PLL1 550m status */ /*! @{ */ + #define SYSCON_PLL1STAT_LOCK_MASK (0x1U) #define SYSCON_PLL1STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ #define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) + #define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) #define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ #define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) + #define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) #define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ #define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) + #define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) #define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ #define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) + #define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) #define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ #define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) /*! @} */ /*! @name PLL1NDEC - PLL1 550m N divider */ /*! @{ */ + #define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) #define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ #define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) + #define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) #define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ #define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) /*! @} */ /*! @name PLL1MDEC - PLL1 550m M divider */ /*! @{ */ + #define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) #define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) +/*! MDIV - feedback divider divider ratio (M-divider). + */ #define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) + #define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) #define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) +/*! MREQ - feedback ratio change request. + */ #define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) /*! @} */ /*! @name PLL1PDEC - PLL1 550m P divider */ /*! @{ */ + #define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) #define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ #define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) + #define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) #define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ #define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) /*! @} */ /*! @name PLL0CTRL - PLL0 550m control */ /*! @{ */ + #define SYSCON_PLL0CTRL_SELR_MASK (0xFU) #define SYSCON_PLL0CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ #define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) + #define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) #define SYSCON_PLL0CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ #define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) + #define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) #define SYSCON_PLL0CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ #define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) + #define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) #define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) /*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). @@ -19612,6 +24543,7 @@ typedef struct { * 0b0..use PLL. */ #define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) + #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) /*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. @@ -19619,9 +24551,13 @@ typedef struct { * 0b0..use the divide-by-2 divider in the post-divider. */ #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + #define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) #define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ #define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) + #define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) #define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) /*! BWDIRECT - Control of the bandwidth of the PLL. @@ -19629,6 +24565,7 @@ typedef struct { * 0b0..the bandwidth is changed synchronously with the feedback-divider. */ #define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) + #define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) #define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) /*! BYPASSPREDIV - bypass of the pre-divider. @@ -19636,6 +24573,7 @@ typedef struct { * 0b0..use the pre-divider. */ #define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) + #define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) #define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) /*! BYPASSPOSTDIV - bypass of the post-divider. @@ -19643,6 +24581,7 @@ typedef struct { * 0b0..use the post-divider. */ #define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) + #define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) #define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) /*! CLKEN - enable the output clock. @@ -19650,6 +24589,7 @@ typedef struct { * 0b0..disable the output clock. */ #define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) + #define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) #define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) /*! FRMEN - free running mode. @@ -19657,9 +24597,13 @@ typedef struct { * 0b0..free running mode is disable. */ #define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) + #define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) #define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. + */ #define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) + #define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) #define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) /*! SKEWEN - skew mode. @@ -19671,786 +24615,169 @@ typedef struct { /*! @name PLL0STAT - PLL0 550m status */ /*! @{ */ + #define SYSCON_PLL0STAT_LOCK_MASK (0x1U) #define SYSCON_PLL0STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ #define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) + #define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) #define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ #define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) + #define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) #define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ #define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) + #define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) #define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ #define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) + #define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) #define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ #define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) /*! @} */ /*! @name PLL0NDEC - PLL0 550m N divider */ /*! @{ */ + #define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) #define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ #define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) + #define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) #define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ #define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) /*! @} */ /*! @name PLL0PDEC - PLL0 550m P divider */ /*! @{ */ + #define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) #define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ #define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) + #define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) #define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ #define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) /*! @} */ /*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ /*! @{ */ + #define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) #define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) +/*! MD_LBS - input word of the wrapper bit 31 to 0. + */ #define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) /*! @} */ /*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ /*! @{ */ + #define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) #define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) +/*! MD_MBS - input word of the wrapper bit 32. + */ #define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) + #define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) #define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) +/*! MD_REQ - md change request. + */ #define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) + #define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) #define SYSCON_PLL0SSCG1_MF_SHIFT (2U) +/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. + */ #define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) + #define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) #define SYSCON_PLL0SSCG1_MR_SHIFT (5U) +/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) + * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. + */ #define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) + #define SYSCON_PLL0SSCG1_MC_MASK (0x300U) #define SYSCON_PLL0SSCG1_MC_SHIFT (8U) +/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a + * triangular modulation at the output of the PLL, giving a flat frequency spectrum. + */ #define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) + #define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) #define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) +/*! MDIV_EXT - to select an external mdiv value. + */ #define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) + #define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) #define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) +/*! MREQ - to select an external mreq value. + */ #define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) + #define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) #define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) +/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way + * (white noise), in order to decrease the probability that the modulated waveform will occur + * with the same phase on a particular point on the screen. + */ #define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) + #define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) #define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) +/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. + */ #define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) /*! @} */ -/*! @name EFUSECLKCTRL - eFUSE controller clock enable */ +/*! @name FUNCRETENTIONCTRL - Functional retention control register */ /*! @{ */ -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK (0x1U) -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT (0U) -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT)) & SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK) -/*! @} */ -/*! @name STARTER - Start logic wake-up enable register */ -/*! @{ */ -#define SYSCON_STARTER_GPIO_INT04_MASK (0x1U) -#define SYSCON_STARTER_GPIO_INT04_SHIFT (0U) -/*! GPIO_INT04 - GPIO_INT04 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) +/*! FUNCRETENA - functional retention in power down only. + * 0b1..enable functional retention. + * 0b0..disable functional retention. */ -#define SYSCON_STARTER_GPIO_INT04(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT04_SHIFT)) & SYSCON_STARTER_GPIO_INT04_MASK) -#define SYSCON_STARTER_SYS_MASK (0x1U) -#define SYSCON_STARTER_SYS_SHIFT (0U) -/*! SYS - SYS interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SYS_SHIFT)) & SYSCON_STARTER_SYS_MASK) -#define SYSCON_STARTER_GPIO_INT05_MASK (0x2U) -#define SYSCON_STARTER_GPIO_INT05_SHIFT (1U) -/*! GPIO_INT05 - GPIO_INT05 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT05(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT05_SHIFT)) & SYSCON_STARTER_GPIO_INT05_MASK) -#define SYSCON_STARTER_SDMA0_MASK (0x2U) -#define SYSCON_STARTER_SDMA0_SHIFT (1U) -/*! SDMA0 - SDMA0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA0_SHIFT)) & SYSCON_STARTER_SDMA0_MASK) -#define SYSCON_STARTER_GINT0_MASK (0x4U) -#define SYSCON_STARTER_GINT0_SHIFT (2U) -/*! GINT0 - GINT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) -#define SYSCON_STARTER_GPIO_INT06_MASK (0x4U) -#define SYSCON_STARTER_GPIO_INT06_SHIFT (2U) -/*! GPIO_INT06 - GPIO_INT06 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT06(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT06_SHIFT)) & SYSCON_STARTER_GPIO_INT06_MASK) -#define SYSCON_STARTER_GINT1_MASK (0x8U) -#define SYSCON_STARTER_GINT1_SHIFT (3U) -/*! GINT1 - GINT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) -#define SYSCON_STARTER_GPIO_INT07_MASK (0x8U) -#define SYSCON_STARTER_GPIO_INT07_SHIFT (3U) -/*! GPIO_INT07 - GPIO_INT07 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT07(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT07_SHIFT)) & SYSCON_STARTER_GPIO_INT07_MASK) -#define SYSCON_STARTER_CTIMER2_MASK (0x10U) -#define SYSCON_STARTER_CTIMER2_SHIFT (4U) -/*! CTIMER2 - CTIMER2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK) -#define SYSCON_STARTER_PIO_INT0_MASK (0x10U) -#define SYSCON_STARTER_PIO_INT0_SHIFT (4U) -/*! PIO_INT0 - PIO_INT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT0_SHIFT)) & SYSCON_STARTER_PIO_INT0_MASK) -#define SYSCON_STARTER_CTIMER4_MASK (0x20U) -#define SYSCON_STARTER_CTIMER4_SHIFT (5U) -/*! CTIMER4 - CTIMER4 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK) -#define SYSCON_STARTER_PIO_INT1_MASK (0x20U) -#define SYSCON_STARTER_PIO_INT1_SHIFT (5U) -/*! PIO_INT1 - PIO_INT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT1_SHIFT)) & SYSCON_STARTER_PIO_INT1_MASK) -#define SYSCON_STARTER_OS_EVENT_MASK (0x40U) -#define SYSCON_STARTER_OS_EVENT_SHIFT (6U) -/*! OS_EVENT - OS_EVENT interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_OS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_OS_EVENT_SHIFT)) & SYSCON_STARTER_OS_EVENT_MASK) -#define SYSCON_STARTER_PIO_INT2_MASK (0x40U) -#define SYSCON_STARTER_PIO_INT2_SHIFT (6U) -/*! PIO_INT2 - PIO_INT2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT2_SHIFT)) & SYSCON_STARTER_PIO_INT2_MASK) -#define SYSCON_STARTER_PIO_INT3_MASK (0x80U) -#define SYSCON_STARTER_PIO_INT3_SHIFT (7U) -/*! PIO_INT3 - PIO_INT3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT3_SHIFT)) & SYSCON_STARTER_PIO_INT3_MASK) -#define SYSCON_STARTER_UTICK0_MASK (0x100U) -#define SYSCON_STARTER_UTICK0_SHIFT (8U) -/*! UTICK0 - UTICK0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK) -#define SYSCON_STARTER_MRT0_MASK (0x200U) -#define SYSCON_STARTER_MRT0_SHIFT (9U) -/*! MRT0 - MRT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK) -#define SYSCON_STARTER_CTIMER0_MASK (0x400U) -#define SYSCON_STARTER_CTIMER0_SHIFT (10U) -/*! CTIMER0 - CTIMER0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) -#define SYSCON_STARTER_SDIO_MASK (0x400U) -#define SYSCON_STARTER_SDIO_SHIFT (10U) -/*! SDIO - SDIO interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDIO_SHIFT)) & SYSCON_STARTER_SDIO_MASK) -#define SYSCON_STARTER_CTIMER1_MASK (0x800U) -#define SYSCON_STARTER_CTIMER1_SHIFT (11U) -/*! CTIMER1 - CTIMER1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) -#define SYSCON_STARTER_SCT0_MASK (0x1000U) -#define SYSCON_STARTER_SCT0_SHIFT (12U) -/*! SCT0 - SCT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) -#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) -#define SYSCON_STARTER_CTIMER3_SHIFT (13U) -/*! CTIMER3 - CTIMER3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) -#define SYSCON_STARTER_FLEXINT0_MASK (0x4000U) -#define SYSCON_STARTER_FLEXINT0_SHIFT (14U) -/*! FLEXINT0 - FLEXINT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT0_SHIFT)) & SYSCON_STARTER_FLEXINT0_MASK) -#define SYSCON_STARTER_FLEXINT1_MASK (0x8000U) -#define SYSCON_STARTER_FLEXINT1_SHIFT (15U) -/*! FLEXINT1 - FLEXINT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT1_SHIFT)) & SYSCON_STARTER_FLEXINT1_MASK) -#define SYSCON_STARTER_USB1_MASK (0x8000U) -#define SYSCON_STARTER_USB1_SHIFT (15U) -/*! USB1 - USB1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK) -#define SYSCON_STARTER_FLEXINT2_MASK (0x10000U) -#define SYSCON_STARTER_FLEXINT2_SHIFT (16U) -/*! FLEXINT2 - FLEXINT2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT2_SHIFT)) & SYSCON_STARTER_FLEXINT2_MASK) -#define SYSCON_STARTER_USB1_NEEDCLK_MASK (0x10000U) -#define SYSCON_STARTER_USB1_NEEDCLK_SHIFT (16U) -/*! USB1_NEEDCLK - USB1_NEEDCLK interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB1_NEEDCLK_MASK) -#define SYSCON_STARTER_FLEXINT3_MASK (0x20000U) -#define SYSCON_STARTER_FLEXINT3_SHIFT (17U) -/*! FLEXINT3 - FLEXINT3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT3_SHIFT)) & SYSCON_STARTER_FLEXINT3_MASK) -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK (0x20000U) -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT (17U) -/*! SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT)) & SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK) -#define SYSCON_STARTER_FLEXINT4_MASK (0x40000U) -#define SYSCON_STARTER_FLEXINT4_SHIFT (18U) -/*! FLEXINT4 - FLEXINT4 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT4_SHIFT)) & SYSCON_STARTER_FLEXINT4_MASK) -#define SYSCON_STARTER_SEC_GPIO_INT00_MASK (0x40000U) -#define SYSCON_STARTER_SEC_GPIO_INT00_SHIFT (18U) -/*! SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_GPIO_INT00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT00_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT00_MASK) -#define SYSCON_STARTER_FLEXINT5_MASK (0x80000U) -#define SYSCON_STARTER_FLEXINT5_SHIFT (19U) -/*! FLEXINT5 - FLEXINT5 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT5_SHIFT)) & SYSCON_STARTER_FLEXINT5_MASK) -#define SYSCON_STARTER_SEC_GPIO_INT01_MASK (0x80000U) -#define SYSCON_STARTER_SEC_GPIO_INT01_SHIFT (19U) -/*! SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_GPIO_INT01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT01_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT01_MASK) -#define SYSCON_STARTER_FLEXINT6_MASK (0x100000U) -#define SYSCON_STARTER_FLEXINT6_SHIFT (20U) -/*! FLEXINT6 - FLEXINT6 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT6_SHIFT)) & SYSCON_STARTER_FLEXINT6_MASK) -#define SYSCON_STARTER_PLU_MASK (0x100000U) -#define SYSCON_STARTER_PLU_SHIFT (20U) -/*! PLU - PLU interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PLU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PLU_SHIFT)) & SYSCON_STARTER_PLU_MASK) -#define SYSCON_STARTER_FLEXINT7_MASK (0x200000U) -#define SYSCON_STARTER_FLEXINT7_SHIFT (21U) -/*! FLEXINT7 - FLEXINT7 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT7_SHIFT)) & SYSCON_STARTER_FLEXINT7_MASK) -#define SYSCON_STARTER_SEC_VIO_MASK (0x200000U) -#define SYSCON_STARTER_SEC_VIO_SHIFT (21U) -/*! SEC_VIO - SEC_VIO interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_VIO_SHIFT)) & SYSCON_STARTER_SEC_VIO_MASK) -#define SYSCON_STARTER_ADC0_MASK (0x400000U) -#define SYSCON_STARTER_ADC0_SHIFT (22U) -/*! ADC0 - ADC0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SHIFT)) & SYSCON_STARTER_ADC0_MASK) -#define SYSCON_STARTER_SHA_MASK (0x400000U) -#define SYSCON_STARTER_SHA_SHIFT (22U) -/*! SHA - SHA interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SHA_SHIFT)) & SYSCON_STARTER_SHA_MASK) -#define SYSCON_STARTER_CASER_MASK (0x800000U) -#define SYSCON_STARTER_CASER_SHIFT (23U) -/*! CASER - CASER interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CASER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CASER_SHIFT)) & SYSCON_STARTER_CASER_MASK) -#define SYSCON_STARTER_ADC0_THCMP_OVR_MASK (0x1000000U) -#define SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT (24U) -/*! ADC0_THCMP_OVR - ADC0_THCMP_OVR interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ADC0_THCMP_OVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_OVR_MASK) -#define SYSCON_STARTER_QDDKEY_MASK (0x1000000U) -#define SYSCON_STARTER_QDDKEY_SHIFT (24U) -/*! QDDKEY - QDDKEY interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_QDDKEY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_QDDKEY_SHIFT)) & SYSCON_STARTER_QDDKEY_MASK) -#define SYSCON_STARTER_PQ_MASK (0x2000000U) -#define SYSCON_STARTER_PQ_SHIFT (25U) -/*! PQ - PQ interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PQ_SHIFT)) & SYSCON_STARTER_PQ_MASK) -#define SYSCON_STARTER_SDMA1_MASK (0x4000000U) -#define SYSCON_STARTER_SDMA1_SHIFT (26U) -/*! SDMA1 - SDMA1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA1_SHIFT)) & SYSCON_STARTER_SDMA1_MASK) -#define SYSCON_STARTER_LSPI_HS_MASK (0x8000000U) -#define SYSCON_STARTER_LSPI_HS_SHIFT (27U) -/*! LSPI_HS - LSPI_HS interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_LSPI_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_LSPI_HS_SHIFT)) & SYSCON_STARTER_LSPI_HS_MASK) -#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) -#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) -/*! USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) -#define SYSCON_STARTER_USB0_MASK (0x10000000U) -#define SYSCON_STARTER_USB0_SHIFT (28U) -/*! USB0 - USB0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) -#define SYSCON_STARTER_RTC_LITE0_MASK (0x20000000U) -#define SYSCON_STARTER_RTC_LITE0_SHIFT (29U) -/*! RTC_LITE0 - RTC_LITE0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_RTC_LITE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_LITE0_SHIFT)) & SYSCON_STARTER_RTC_LITE0_MASK) -#define SYSCON_STARTER_EZH_ARCH_B0_MASK (0x40000000U) -#define SYSCON_STARTER_EZH_ARCH_B0_SHIFT (30U) -/*! EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_EZH_ARCH_B0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_EZH_ARCH_B0_SHIFT)) & SYSCON_STARTER_EZH_ARCH_B0_MASK) -#define SYSCON_STARTER_WAKEUPPADS_MASK (0x80000000U) -#define SYSCON_STARTER_WAKEUPPADS_SHIFT (31U) -#define SYSCON_STARTER_WAKEUPPADS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUPPADS_SHIFT)) & SYSCON_STARTER_WAKEUPPADS_MASK) -#define SYSCON_STARTER_WAKEUP_MAILBOX0_MASK (0x80000000U) -#define SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT (31U) -/*! WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_WAKEUP_MAILBOX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT)) & SYSCON_STARTER_WAKEUP_MAILBOX0_MASK) -/*! @} */ +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) -/* The count of SYSCON_STARTER */ -#define SYSCON_STARTER_COUNT (2U) +#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) +#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) +/*! RET_START - Start address divided by 4 inside SRAMX bank. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) -/*! @name STARTERSET - Set bits in STARTER */ -/*! @{ */ -#define SYSCON_STARTERSET_GPIO_INT04_SET_MASK (0x1U) -#define SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT (0U) -#define SYSCON_STARTERSET_GPIO_INT04_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT04_SET_MASK) -#define SYSCON_STARTERSET_SYS_SET_MASK (0x1U) -#define SYSCON_STARTERSET_SYS_SET_SHIFT (0U) -#define SYSCON_STARTERSET_SYS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SYS_SET_SHIFT)) & SYSCON_STARTERSET_SYS_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT05_SET_MASK (0x2U) -#define SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT (1U) -#define SYSCON_STARTERSET_GPIO_INT05_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT05_SET_MASK) -#define SYSCON_STARTERSET_SDMA0_SET_MASK (0x2U) -#define SYSCON_STARTERSET_SDMA0_SET_SHIFT (1U) -#define SYSCON_STARTERSET_SDMA0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA0_SET_SHIFT)) & SYSCON_STARTERSET_SDMA0_SET_MASK) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK (0x4U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT (2U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT06_SET_MASK (0x4U) -#define SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT (2U) -#define SYSCON_STARTERSET_GPIO_INT06_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT06_SET_MASK) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK (0x8U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT (3U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT07_SET_MASK (0x8U) -#define SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT (3U) -#define SYSCON_STARTERSET_GPIO_INT07_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT07_SET_MASK) -#define SYSCON_STARTERSET_CTIMER2_SET_MASK (0x10U) -#define SYSCON_STARTERSET_CTIMER2_SET_SHIFT (4U) -#define SYSCON_STARTERSET_CTIMER2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER2_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER2_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT00_SET_MASK (0x10U) -#define SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT (4U) -#define SYSCON_STARTERSET_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT00_SET_MASK) -#define SYSCON_STARTERSET_CTIMER4_SET_MASK (0x20U) -#define SYSCON_STARTERSET_CTIMER4_SET_SHIFT (5U) -#define SYSCON_STARTERSET_CTIMER4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER4_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER4_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT01_SET_MASK (0x20U) -#define SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT (5U) -#define SYSCON_STARTERSET_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT01_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT02_SET_MASK (0x40U) -#define SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT (6U) -#define SYSCON_STARTERSET_GPIO_INT02_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT02_SET_MASK) -#define SYSCON_STARTERSET_OS_EVENT_SET_MASK (0x40U) -#define SYSCON_STARTERSET_OS_EVENT_SET_SHIFT (6U) -#define SYSCON_STARTERSET_OS_EVENT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_OS_EVENT_SET_SHIFT)) & SYSCON_STARTERSET_OS_EVENT_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT03_SET_MASK (0x80U) -#define SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT (7U) -#define SYSCON_STARTERSET_GPIO_INT03_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT03_SET_MASK) -#define SYSCON_STARTERSET_UTICK0_SET_MASK (0x100U) -#define SYSCON_STARTERSET_UTICK0_SET_SHIFT (8U) -#define SYSCON_STARTERSET_UTICK0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_UTICK0_SET_SHIFT)) & SYSCON_STARTERSET_UTICK0_SET_MASK) -#define SYSCON_STARTERSET_MRT0_SET_MASK (0x200U) -#define SYSCON_STARTERSET_MRT0_SET_SHIFT (9U) -#define SYSCON_STARTERSET_MRT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_MRT0_SET_SHIFT)) & SYSCON_STARTERSET_MRT0_SET_MASK) -#define SYSCON_STARTERSET_CTIMER0_SET_MASK (0x400U) -#define SYSCON_STARTERSET_CTIMER0_SET_SHIFT (10U) -#define SYSCON_STARTERSET_CTIMER0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER0_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER0_SET_MASK) -#define SYSCON_STARTERSET_SDIO_SET_MASK (0x400U) -#define SYSCON_STARTERSET_SDIO_SET_SHIFT (10U) -#define SYSCON_STARTERSET_SDIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDIO_SET_SHIFT)) & SYSCON_STARTERSET_SDIO_SET_MASK) -#define SYSCON_STARTERSET_CTIMER1_SET_MASK (0x800U) -#define SYSCON_STARTERSET_CTIMER1_SET_SHIFT (11U) -#define SYSCON_STARTERSET_CTIMER1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER1_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER1_SET_MASK) -#define SYSCON_STARTERSET_SCT0_SET_MASK (0x1000U) -#define SYSCON_STARTERSET_SCT0_SET_SHIFT (12U) -#define SYSCON_STARTERSET_SCT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SCT0_SET_SHIFT)) & SYSCON_STARTERSET_SCT0_SET_MASK) -#define SYSCON_STARTERSET_CTIMER3_SET_MASK (0x2000U) -#define SYSCON_STARTERSET_CTIMER3_SET_SHIFT (13U) -#define SYSCON_STARTERSET_CTIMER3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER3_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER3_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT0_SET_MASK (0x4000U) -#define SYSCON_STARTERSET_FLEXINT0_SET_SHIFT (14U) -#define SYSCON_STARTERSET_FLEXINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT0_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT1_SET_MASK (0x8000U) -#define SYSCON_STARTERSET_FLEXINT1_SET_SHIFT (15U) -#define SYSCON_STARTERSET_FLEXINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT1_SET_MASK) -#define SYSCON_STARTERSET_USB1_SET_MASK (0x8000U) -#define SYSCON_STARTERSET_USB1_SET_SHIFT (15U) -#define SYSCON_STARTERSET_USB1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_SET_SHIFT)) & SYSCON_STARTERSET_USB1_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT2_SET_MASK (0x10000U) -#define SYSCON_STARTERSET_FLEXINT2_SET_SHIFT (16U) -#define SYSCON_STARTERSET_FLEXINT2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT2_SET_MASK) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK (0x10000U) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT (16U) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT3_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_FLEXINT3_SET_SHIFT (17U) -#define SYSCON_STARTERSET_FLEXINT3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT3_SET_MASK) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT (17U) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT)) & SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT4_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_FLEXINT4_SET_SHIFT (18U) -#define SYSCON_STARTERSET_FLEXINT4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT4_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT4_SET_MASK) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT (18U) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT5_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_FLEXINT5_SET_SHIFT (19U) -#define SYSCON_STARTERSET_FLEXINT5_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT5_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT5_SET_MASK) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT (19U) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT6_SET_MASK (0x100000U) -#define SYSCON_STARTERSET_FLEXINT6_SET_SHIFT (20U) -#define SYSCON_STARTERSET_FLEXINT6_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT6_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT6_SET_MASK) -#define SYSCON_STARTERSET_PLU_SET_MASK (0x100000U) -#define SYSCON_STARTERSET_PLU_SET_SHIFT (20U) -#define SYSCON_STARTERSET_PLU_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PLU_SET_SHIFT)) & SYSCON_STARTERSET_PLU_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT7_SET_MASK (0x200000U) -#define SYSCON_STARTERSET_FLEXINT7_SET_SHIFT (21U) -#define SYSCON_STARTERSET_FLEXINT7_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT7_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT7_SET_MASK) -#define SYSCON_STARTERSET_SEC_VIO_SET_MASK (0x200000U) -#define SYSCON_STARTERSET_SEC_VIO_SET_SHIFT (21U) -#define SYSCON_STARTERSET_SEC_VIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_VIO_SET_SHIFT)) & SYSCON_STARTERSET_SEC_VIO_SET_MASK) -#define SYSCON_STARTERSET_ADC0_SET_MASK (0x400000U) -#define SYSCON_STARTERSET_ADC0_SET_SHIFT (22U) -#define SYSCON_STARTERSET_ADC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_SET_MASK) -#define SYSCON_STARTERSET_SHA_SET_MASK (0x400000U) -#define SYSCON_STARTERSET_SHA_SET_SHIFT (22U) -#define SYSCON_STARTERSET_SHA_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SHA_SET_SHIFT)) & SYSCON_STARTERSET_SHA_SET_MASK) -#define SYSCON_STARTERSET_CASER_SET_MASK (0x800000U) -#define SYSCON_STARTERSET_CASER_SET_SHIFT (23U) -#define SYSCON_STARTERSET_CASER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CASER_SET_SHIFT)) & SYSCON_STARTERSET_CASER_SET_MASK) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK (0x1000000U) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT (24U) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK) -#define SYSCON_STARTERSET_QDDKEY_SET_MASK (0x1000000U) -#define SYSCON_STARTERSET_QDDKEY_SET_SHIFT (24U) -#define SYSCON_STARTERSET_QDDKEY_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_QDDKEY_SET_SHIFT)) & SYSCON_STARTERSET_QDDKEY_SET_MASK) -#define SYSCON_STARTERSET_PQ_SET_MASK (0x2000000U) -#define SYSCON_STARTERSET_PQ_SET_SHIFT (25U) -#define SYSCON_STARTERSET_PQ_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PQ_SET_SHIFT)) & SYSCON_STARTERSET_PQ_SET_MASK) -#define SYSCON_STARTERSET_SDMA1_SET_MASK (0x4000000U) -#define SYSCON_STARTERSET_SDMA1_SET_SHIFT (26U) -#define SYSCON_STARTERSET_SDMA1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA1_SET_SHIFT)) & SYSCON_STARTERSET_SDMA1_SET_MASK) -#define SYSCON_STARTERSET_LSPI_HS_SET_MASK (0x8000000U) -#define SYSCON_STARTERSET_LSPI_HS_SET_SHIFT (27U) -#define SYSCON_STARTERSET_LSPI_HS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_LSPI_HS_SET_SHIFT)) & SYSCON_STARTERSET_LSPI_HS_SET_MASK) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK (0x8000000U) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT (27U) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK) -#define SYSCON_STARTERSET_USB0_SET_MASK (0x10000000U) -#define SYSCON_STARTERSET_USB0_SET_SHIFT (28U) -#define SYSCON_STARTERSET_USB0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_SET_SHIFT)) & SYSCON_STARTERSET_USB0_SET_MASK) -#define SYSCON_STARTERSET_RTC_LITE0_SET_MASK (0x20000000U) -#define SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT (29U) -#define SYSCON_STARTERSET_RTC_LITE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT)) & SYSCON_STARTERSET_RTC_LITE0_SET_MASK) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK (0x40000000U) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT (30U) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT)) & SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK) -#define SYSCON_STARTERSET_WAKEUPPADS_SET_MASK (0x80000000U) -#define SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT (31U) -#define SYSCON_STARTERSET_WAKEUPPADS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUPPADS_SET_MASK) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK (0x80000000U) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT (31U) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERSET */ -#define SYSCON_STARTERSET_COUNT (2U) - -/*! @name STARTERCLR - Clear bits in STARTER */ -/*! @{ */ -#define SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK (0x1U) -#define SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_GPIO_INT04_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK) -#define SYSCON_STARTERCLR_SYS_CLR_MASK (0x1U) -#define SYSCON_STARTERCLR_SYS_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_SYS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SYS_CLR_SHIFT)) & SYSCON_STARTERCLR_SYS_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK (0x2U) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT (1U) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK) -#define SYSCON_STARTERCLR_SDMA0_CLR_MASK (0x2U) -#define SYSCON_STARTERCLR_SDMA0_CLR_SHIFT (1U) -#define SYSCON_STARTERCLR_SDMA0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA0_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA0_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK (0x4U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT (2U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK (0x4U) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT (2U) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK (0x8U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT (3U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK (0x8U) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT (3U) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER2_CLR_MASK (0x10U) -#define SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT (4U) -#define SYSCON_STARTERCLR_CTIMER2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER2_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK (0x10U) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT (4U) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER4_CLR_MASK (0x20U) -#define SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT (5U) -#define SYSCON_STARTERCLR_CTIMER4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER4_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK (0x20U) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT (5U) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK (0x40U) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT (6U) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK) -#define SYSCON_STARTERCLR_OS_EVENT_CLR_MASK (0x40U) -#define SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT (6U) -#define SYSCON_STARTERCLR_OS_EVENT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT)) & SYSCON_STARTERCLR_OS_EVENT_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK (0x80U) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT (7U) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK) -#define SYSCON_STARTERCLR_UTICK0_CLR_MASK (0x100U) -#define SYSCON_STARTERCLR_UTICK0_CLR_SHIFT (8U) -#define SYSCON_STARTERCLR_UTICK0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_UTICK0_CLR_SHIFT)) & SYSCON_STARTERCLR_UTICK0_CLR_MASK) -#define SYSCON_STARTERCLR_MRT0_CLR_MASK (0x200U) -#define SYSCON_STARTERCLR_MRT0_CLR_SHIFT (9U) -#define SYSCON_STARTERCLR_MRT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_MRT0_CLR_SHIFT)) & SYSCON_STARTERCLR_MRT0_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER0_CLR_MASK (0x400U) -#define SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT (10U) -#define SYSCON_STARTERCLR_CTIMER0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER0_CLR_MASK) -#define SYSCON_STARTERCLR_SDIO_CLR_MASK (0x400U) -#define SYSCON_STARTERCLR_SDIO_CLR_SHIFT (10U) -#define SYSCON_STARTERCLR_SDIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SDIO_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER1_CLR_MASK (0x800U) -#define SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT (11U) -#define SYSCON_STARTERCLR_CTIMER1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER1_CLR_MASK) -#define SYSCON_STARTERCLR_SCT0_CLR_MASK (0x1000U) -#define SYSCON_STARTERCLR_SCT0_CLR_SHIFT (12U) -#define SYSCON_STARTERCLR_SCT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SCT0_CLR_SHIFT)) & SYSCON_STARTERCLR_SCT0_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER3_CLR_MASK (0x2000U) -#define SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT (13U) -#define SYSCON_STARTERCLR_CTIMER3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER3_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT0_CLR_MASK (0x4000U) -#define SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT (14U) -#define SYSCON_STARTERCLR_FLEXINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT0_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT1_CLR_MASK (0x8000U) -#define SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT (15U) -#define SYSCON_STARTERCLR_FLEXINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT1_CLR_MASK) -#define SYSCON_STARTERCLR_USB1_CLR_MASK (0x8000U) -#define SYSCON_STARTERCLR_USB1_CLR_SHIFT (15U) -#define SYSCON_STARTERCLR_USB1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT2_CLR_MASK (0x10000U) -#define SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT (16U) -#define SYSCON_STARTERCLR_FLEXINT2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT2_CLR_MASK) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK (0x10000U) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT (16U) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT3_CLR_MASK (0x20000U) -#define SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT (17U) -#define SYSCON_STARTERCLR_FLEXINT3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT3_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK (0x20000U) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT (17U) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT4_CLR_MASK (0x40000U) -#define SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT (18U) -#define SYSCON_STARTERCLR_FLEXINT4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT4_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK (0x40000U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT (18U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT5_CLR_MASK (0x80000U) -#define SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT (19U) -#define SYSCON_STARTERCLR_FLEXINT5_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT5_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK (0x80000U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT (19U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT6_CLR_MASK (0x100000U) -#define SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT (20U) -#define SYSCON_STARTERCLR_FLEXINT6_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT6_CLR_MASK) -#define SYSCON_STARTERCLR_PLU_CLR_MASK (0x100000U) -#define SYSCON_STARTERCLR_PLU_CLR_SHIFT (20U) -#define SYSCON_STARTERCLR_PLU_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PLU_CLR_SHIFT)) & SYSCON_STARTERCLR_PLU_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT7_CLR_MASK (0x200000U) -#define SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT (21U) -#define SYSCON_STARTERCLR_FLEXINT7_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT7_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_VIO_CLR_MASK (0x200000U) -#define SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT (21U) -#define SYSCON_STARTERCLR_SEC_VIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_VIO_CLR_MASK) -#define SYSCON_STARTERCLR_ADC0_CLR_MASK (0x400000U) -#define SYSCON_STARTERCLR_ADC0_CLR_SHIFT (22U) -#define SYSCON_STARTERCLR_ADC0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_CLR_MASK) -#define SYSCON_STARTERCLR_SHA_CLR_MASK (0x400000U) -#define SYSCON_STARTERCLR_SHA_CLR_SHIFT (22U) -#define SYSCON_STARTERCLR_SHA_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SHA_CLR_SHIFT)) & SYSCON_STARTERCLR_SHA_CLR_MASK) -#define SYSCON_STARTERCLR_CASER_CLR_MASK (0x800000U) -#define SYSCON_STARTERCLR_CASER_CLR_SHIFT (23U) -#define SYSCON_STARTERCLR_CASER_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CASER_CLR_SHIFT)) & SYSCON_STARTERCLR_CASER_CLR_MASK) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK (0x1000000U) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT (24U) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK) -#define SYSCON_STARTERCLR_QDDKEY_CLR_MASK (0x1000000U) -#define SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT (24U) -#define SYSCON_STARTERCLR_QDDKEY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT)) & SYSCON_STARTERCLR_QDDKEY_CLR_MASK) -#define SYSCON_STARTERCLR_PQ_CLR_MASK (0x2000000U) -#define SYSCON_STARTERCLR_PQ_CLR_SHIFT (25U) -#define SYSCON_STARTERCLR_PQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PQ_CLR_SHIFT)) & SYSCON_STARTERCLR_PQ_CLR_MASK) -#define SYSCON_STARTERCLR_SDMA1_CLR_MASK (0x4000000U) -#define SYSCON_STARTERCLR_SDMA1_CLR_SHIFT (26U) -#define SYSCON_STARTERCLR_SDMA1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA1_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA1_CLR_MASK) -#define SYSCON_STARTERCLR_LSPI_HS_CLR_MASK (0x8000000U) -#define SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT (27U) -#define SYSCON_STARTERCLR_LSPI_HS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT)) & SYSCON_STARTERCLR_LSPI_HS_CLR_MASK) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK (0x8000000U) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT (27U) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK) -#define SYSCON_STARTERCLR_USB0_CLR_MASK (0x10000000U) -#define SYSCON_STARTERCLR_USB0_CLR_SHIFT (28U) -#define SYSCON_STARTERCLR_USB0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_CLR_MASK) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK (0x20000000U) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT (29U) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT)) & SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK (0x40000000U) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT (30U) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT)) & SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK (0x80000000U) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT (31U) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK (0x80000000U) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT (31U) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERCLR */ -#define SYSCON_STARTERCLR_COUNT (2U) - -/*! @name HARDWARESLEEP - Hardware Sleep control */ -/*! @{ */ -#define SYSCON_HARDWARESLEEP_FORCED_MASK (0x1U) -#define SYSCON_HARDWARESLEEP_FORCED_SHIFT (0U) -#define SYSCON_HARDWARESLEEP_FORCED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_FORCED_SHIFT)) & SYSCON_HARDWARESLEEP_FORCED_MASK) -#define SYSCON_HARDWARESLEEP_PERIPHERALS_MASK (0x2U) -#define SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT (1U) -#define SYSCON_HARDWARESLEEP_PERIPHERALS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT)) & SYSCON_HARDWARESLEEP_PERIPHERALS_MASK) -#define SYSCON_HARDWARESLEEP_SDMA0_MASK (0x8U) -#define SYSCON_HARDWARESLEEP_SDMA0_SHIFT (3U) -#define SYSCON_HARDWARESLEEP_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA0_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA0_MASK) -#define SYSCON_HARDWARESLEEP_SDMA1_MASK (0x20U) -#define SYSCON_HARDWARESLEEP_SDMA1_SHIFT (5U) -#define SYSCON_HARDWARESLEEP_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA1_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA1_MASK) +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) +/*! RET_LENTH - lenth of Scan chains to save. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) /*! @} */ /*! @name CPUCTRL - CPU Control for multiple processors */ /*! @{ */ + #define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) #define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) /*! CPU1CLKEN - CPU1 clock enable. @@ -20458,6 +24785,7 @@ typedef struct { * 0b0..The CPU1 clock is not enabled. */ #define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) + #define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) #define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) /*! CPU1RSTEN - CPU1 reset. @@ -20469,20 +24797,17 @@ typedef struct { /*! @name CPBOOT - Coprocessor Boot Address */ /*! @{ */ + #define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) #define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) +/*! CPBOOT - Coprocessor Boot Address for CPU1. + */ #define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) /*! @} */ -/*! @name CPSTACK - Coprocessor Stack Address */ -/*! @{ */ -#define SYSCON_CPSTACK_CPSTACK_MASK (0xFFFFFFFFU) -#define SYSCON_CPSTACK_CPSTACK_SHIFT (0U) -#define SYSCON_CPSTACK_CPSTACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_CPSTACK_SHIFT)) & SYSCON_CPSTACK_CPSTACK_MASK) -/*! @} */ - /*! @name CPSTAT - CPU Status */ /*! @{ */ + #define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) #define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) /*! CPU0SLEEPING - The CPU0 sleeping state. @@ -20490,6 +24815,7 @@ typedef struct { * 0b0..the CPU is not sleeping. */ #define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) + #define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) #define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) /*! CPU1SLEEPING - The CPU1 sleeping state. @@ -20497,6 +24823,7 @@ typedef struct { * 0b0..the CPU is not sleeping. */ #define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) + #define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) #define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) /*! CPU0LOCKUP - The CPU0 lockup state. @@ -20504,6 +24831,7 @@ typedef struct { * 0b0..the CPU is not in lockup. */ #define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) + #define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) #define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) /*! CPU1LOCKUP - The CPU1 lockup state. @@ -20513,71 +24841,9 @@ typedef struct { #define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) /*! @} */ -/*! @name DICE_REG0 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG0_DICE_REG0_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG0_DICE_REG0_SHIFT (0U) -#define SYSCON_DICE_REG0_DICE_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG0_DICE_REG0_SHIFT)) & SYSCON_DICE_REG0_DICE_REG0_MASK) -/*! @} */ - -/*! @name DICE_REG1 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG1_DICE_REG1_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG1_DICE_REG1_SHIFT (0U) -#define SYSCON_DICE_REG1_DICE_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG1_DICE_REG1_SHIFT)) & SYSCON_DICE_REG1_DICE_REG1_MASK) -/*! @} */ - -/*! @name DICE_REG2 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG2_DICE_REG2_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG2_DICE_REG2_SHIFT (0U) -#define SYSCON_DICE_REG2_DICE_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG2_DICE_REG2_SHIFT)) & SYSCON_DICE_REG2_DICE_REG2_MASK) -/*! @} */ - -/*! @name DICE_REG3 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG3_DICE_REG3_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG3_DICE_REG3_SHIFT (0U) -#define SYSCON_DICE_REG3_DICE_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG3_DICE_REG3_SHIFT)) & SYSCON_DICE_REG3_DICE_REG3_MASK) -/*! @} */ - -/*! @name DICE_REG4 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG4_DICE_REG4_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG4_DICE_REG4_SHIFT (0U) -#define SYSCON_DICE_REG4_DICE_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG4_DICE_REG4_SHIFT)) & SYSCON_DICE_REG4_DICE_REG4_MASK) -/*! @} */ - -/*! @name DICE_REG5 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG5_DICE_REG5_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG5_DICE_REG5_SHIFT (0U) -#define SYSCON_DICE_REG5_DICE_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG5_DICE_REG5_SHIFT)) & SYSCON_DICE_REG5_DICE_REG5_MASK) -/*! @} */ - -/*! @name DICE_REG6 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG6_DICE_REG6_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG6_DICE_REG6_SHIFT (0U) -#define SYSCON_DICE_REG6_DICE_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG6_DICE_REG6_SHIFT)) & SYSCON_DICE_REG6_DICE_REG6_MASK) -/*! @} */ - -/*! @name DICE_REG7 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG7_DICE_REG7_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG7_DICE_REG7_SHIFT (0U) -#define SYSCON_DICE_REG7_DICE_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG7_DICE_REG7_SHIFT)) & SYSCON_DICE_REG7_DICE_REG7_MASK) -/*! @} */ - /*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ /*! @{ */ -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK (0x1U) -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT (0U) -/*! FLASH48MHZ_ENA - Enable Flash 48 MHz clock. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK) + #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) /*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. @@ -20585,6 +24851,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) + #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) /*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. @@ -20592,6 +24859,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) + #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) /*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. @@ -20599,6 +24867,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) + #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) /*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. @@ -20606,6 +24875,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) + #define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) #define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) /*! CLKIN_ENA - Enable clock_in clock for clock module. @@ -20613,6 +24883,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) + #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) /*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. @@ -20620,6 +24891,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) + #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) /*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. @@ -20627,6 +24899,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) + #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) /*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. @@ -20634,6 +24907,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) + #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) /*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. @@ -20645,6 +24919,7 @@ typedef struct { /*! @name COMP_INT_CTRL - Comparator Interrupt control */ /*! @{ */ + #define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) #define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) /*! INT_ENABLE - Analog Comparator interrupt enable control:. @@ -20652,6 +24927,7 @@ typedef struct { * 0b0..interrupt disable. */ #define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) + #define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) #define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) /*! INT_CLEAR - Analog Comparator interrupt clear. @@ -20659,6 +24935,7 @@ typedef struct { * 0b1..Clear the interrupt. Self-cleared bit. */ #define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) + #define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) #define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) /*! INT_CTRL - Comparator interrupt type selector:. @@ -20672,6 +24949,7 @@ typedef struct { * 0b111..The analog comparator interrupt level sensitive is disabled. */ #define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) + #define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) #define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) /*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. @@ -20684,6 +24962,7 @@ typedef struct { /*! @name COMP_INT_STATUS - Comparator Interrupt status */ /*! @{ */ + #define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) #define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) /*! STATUS - Interrupt status BEFORE Interrupt Enable. @@ -20691,6 +24970,7 @@ typedef struct { * 0b1..interrupt pending. */ #define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) + #define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) #define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) /*! INT_STATUS - Interrupt status AFTER Interrupt Enable. @@ -20698,6 +24978,7 @@ typedef struct { * 0b1..interrupt pending. */ #define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) + #define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) #define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) /*! VAL - comparator analog output. @@ -20709,6 +24990,7 @@ typedef struct { /*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ /*! @{ */ + #define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) #define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) /*! ROM - Control automatic clock gating of ROM controller. @@ -20716,6 +24998,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) /*! RAMX_CTRL - Control automatic clock gating of RAMX controller. @@ -20723,6 +25006,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) /*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. @@ -20730,6 +25014,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) /*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. @@ -20737,6 +25022,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) /*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. @@ -20744,6 +25030,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) /*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. @@ -20751,6 +25038,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) /*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. @@ -20758,6 +25046,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) /*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. @@ -20765,6 +25054,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) /*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. @@ -20772,20 +25062,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK (0x200U) -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT (9U) -/*! FLASH - Control automatic clock gating of FLASH controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK (0x400U) -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT (10U) -/*! FMC - Control automatic clock gating of FMC controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) /*! CRCGEN - Control automatic clock gating of CRCGEN controller. @@ -20793,6 +25070,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) /*! SDMA0 - Control automatic clock gating of DMA0 controller. @@ -20800,6 +25078,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) /*! SDMA1 - Control automatic clock gating of DMA1 controller. @@ -20807,13 +25086,15 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK (0x4000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT (14U) -/*! USB - Control automatic clock gating of USB controller. + +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) +/*! USB0 - Control automatic clock gating of USB controller. * 0b1..Automatic clock gating is overridden (Clock gating is disabled). * 0b0..Automatic clock gating is not overridden. */ -#define SYSCON_AUTOCLKGATEOVERRIDE_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) /*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. @@ -20821,17 +25102,19 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) /*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - * 0b1100000011011110..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0000000000000000..Automatic clock gating is not overridden. + * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated + * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated */ #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) /*! @} */ /*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ /*! @{ */ + #define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) #define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) /*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. @@ -20841,159 +25124,147 @@ typedef struct { #define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) /*! @} */ -/*! @name DEBUG_LOCK_EN - Control write access to security registers -- FOR INTERNAl USE ONLY */ +/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ /*! @{ */ + #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) /*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, - * CODESECURITYPROTCPU1, CM33_DEBUG_FEATURES, MCM33_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + * CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. * 0b1010..1010: Enable write access to all 6 registers. * 0b0000..Any other value than b1010: disable write access to all 6 registers. */ #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) /*! @} */ -/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY */ +/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */ /*! @{ */ -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT (0U) -/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT (2U) -/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT (4U) -/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT (6U) -/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT (8U) -/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT (10U) -/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK) /*! @} */ -/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY */ +/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */ /*! @{ */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT (0U) -/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT (2U) -/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT (4U) -/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT (6U) -/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT (8U) -/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT (10U) -/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK) /*! @} */ -/*! @name CODESECURITYPROTTEST - Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY */ +/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ /*! @{ */ -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow test access : 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow test access. - * 0b00000000000000000000000000000000..test access is not allowed. - */ -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK) -/*! @} */ -/*! @name CODESECURITYPROTCPU0 - Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow CPU0 DAP: 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow CPU0 DAP. - * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. - */ -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK) -/*! @} */ - -/*! @name CODESECURITYPROTCPU1 - Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow CPU1 DAP: 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow CPU1 DAP. - * 0b00000000000000000000000000000000..CPU1 DAP is not allowed. - */ -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK) -/*! @} */ - -/*! @name KEY_BLOCK - block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY */ -/*! @{ */ #define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) #define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) +/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. + */ #define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) /*! @} */ -/*! @name DEBUG_AUTH_SCRATCH - Debug authentication scratch registers -- FOR INTERNAL USE ONLY */ +/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ /*! @{ */ -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK (0xFFFFFFFFU) -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT (0U) -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT)) & SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK) + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) /*! @} */ /*! @name CPUCFG - CPUs configuration register */ /*! @{ */ + #define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) #define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) /*! CPU1ENABLE - Enable CPU1. @@ -21003,92 +25274,29 @@ typedef struct { #define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) /*! @} */ -/*! @name PERIPHENCFG - peripheral enable configuration -- FOR INTERNAL USE ONLY */ -/*! @{ */ -#define SYSCON_PERIPHENCFG_SCTEN_MASK (0x1U) -#define SYSCON_PERIPHENCFG_SCTEN_SHIFT (0U) -/*! SCTEN - SCT enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_SCTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SCTEN_SHIFT)) & SYSCON_PERIPHENCFG_SCTEN_MASK) -#define SYSCON_PERIPHENCFG_ADCEN_MASK (0x2U) -#define SYSCON_PERIPHENCFG_ADCEN_SHIFT (1U) -/*! ADCEN - ADC enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_ADCEN_SHIFT)) & SYSCON_PERIPHENCFG_ADCEN_MASK) -#define SYSCON_PERIPHENCFG_USB0EN_MASK (0x4U) -#define SYSCON_PERIPHENCFG_USB0EN_SHIFT (2U) -/*! USB0EN - USB0 enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_USB0EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB0EN_SHIFT)) & SYSCON_PERIPHENCFG_USB0EN_MASK) -#define SYSCON_PERIPHENCFG_PUFFEN_MASK (0x40U) -#define SYSCON_PERIPHENCFG_PUFFEN_SHIFT (6U) -/*! PUFFEN - Puff enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_PUFFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PUFFEN_SHIFT)) & SYSCON_PERIPHENCFG_PUFFEN_MASK) -#define SYSCON_PERIPHENCFG_USB1EN_MASK (0x400U) -#define SYSCON_PERIPHENCFG_USB1EN_SHIFT (10U) -/*! USB1EN - USB1 enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_USB1EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB1EN_SHIFT)) & SYSCON_PERIPHENCFG_USB1EN_MASK) -#define SYSCON_PERIPHENCFG_SDIOEN_MASK (0x800U) -#define SYSCON_PERIPHENCFG_SDIOEN_SHIFT (11U) -/*! SDIOEN - SDIO enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_SDIOEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SDIOEN_SHIFT)) & SYSCON_PERIPHENCFG_SDIOEN_MASK) -#define SYSCON_PERIPHENCFG_HASHEN_MASK (0x1000U) -#define SYSCON_PERIPHENCFG_HASHEN_SHIFT (12U) -/*! HASHEN - HASH enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_HASHEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_HASHEN_SHIFT)) & SYSCON_PERIPHENCFG_HASHEN_MASK) -#define SYSCON_PERIPHENCFG_PRINCEEN_MASK (0x4000U) -#define SYSCON_PERIPHENCFG_PRINCEEN_SHIFT (14U) -/*! PRINCEEN - PRINCE enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_PRINCEEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PRINCEEN_SHIFT)) & SYSCON_PERIPHENCFG_PRINCEEN_MASK) -/*! @} */ - /*! @name DEVICE_ID0 - Device ID */ /*! @{ */ -#define SYSCON_DEVICE_ID0_PARTCONFIG_MASK (0xFFU) -#define SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT (0U) -#define SYSCON_DEVICE_ID0_PARTCONFIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT)) & SYSCON_DEVICE_ID0_PARTCONFIG_MASK) -#define SYSCON_DEVICE_ID0_SRAM_SIZE_MASK (0xF00U) -#define SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT (8U) -#define SYSCON_DEVICE_ID0_SRAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_SRAM_SIZE_MASK) -#define SYSCON_DEVICE_ID0_FLASH_SIZE_MASK (0x7000U) -#define SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT (12U) -#define SYSCON_DEVICE_ID0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_FLASH_SIZE_MASK) + #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - ROM revision. + */ #define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK (0x7000000U) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT (24U) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT)) & SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK) /*! @} */ /*! @name DIEID - Chip revision ID and Number */ /*! @{ */ + #define SYSCON_DIEID_REV_ID_MASK (0xFU) #define SYSCON_DIEID_REV_ID_SHIFT (0U) +/*! REV_ID - Chip Metal Revision ID. + */ #define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) + #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) +/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. + */ #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) /*! @} */ @@ -21099,7 +25307,7 @@ typedef struct { /* SYSCON - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral SYSCON base address */ #define SYSCON_BASE (0x50000000u) /** Peripheral SYSCON base address */ @@ -21163,6 +25371,7 @@ typedef struct { /*! @name UPDATELCKOUT - update lock out control */ /*! @{ */ + #define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) #define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) /*! UPDATELCKOUT - All Registers @@ -21174,6 +25383,7 @@ typedef struct { /*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ /*! @{ */ + #define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) #define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) /*! SCKINSEL - Selects the source for SCK going into this Flexcomm. @@ -21183,6 +25393,7 @@ typedef struct { * 0b11..Reserved. */ #define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) + #define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) #define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) /*! WSINSEL - Selects the source for WS going into this Flexcomm. @@ -21192,6 +25403,7 @@ typedef struct { * 0b11..Reserved. */ #define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) + #define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) #define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) /*! DATAINSEL - Selects the source for DATA input to this Flexcomm. @@ -21201,6 +25413,7 @@ typedef struct { * 0b11..Reserved. */ #define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) + #define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) #define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) /*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. @@ -21215,10 +25428,11 @@ typedef struct { /* The count of SYSCTL_FCCTRLSEL */ #define SYSCTL_FCCTRLSEL_COUNT (8U) -/*! @name SHARECTRLSET_SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ +/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ /*! @{ */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) + +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) /*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. * 0b000..SCK for this shared signal set comes from Flexcomm 0. * 0b001..SCK for this shared signal set comes from Flexcomm 1. @@ -21229,9 +25443,10 @@ typedef struct { * 0b110..SCK for this shared signal set comes from Flexcomm 6. * 0b111..SCK for this shared signal set comes from Flexcomm 7. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) /*! SHAREDWSSEL - Selects the source for WS of this shared signal set. * 0b000..WS for this shared signal set comes from Flexcomm 0. * 0b001..WS for this shared signal set comes from Flexcomm 1. @@ -21242,9 +25457,10 @@ typedef struct { * 0b110..WS for this shared signal set comes from Flexcomm 6. * 0b111..WS for this shared signal set comes from Flexcomm 7. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) /*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. * 0b000..DATA input for this shared signal set comes from Flexcomm 0. * 0b001..DATA input for this shared signal set comes from Flexcomm 1. @@ -21255,70 +25471,71 @@ typedef struct { * 0b110..DATA input for this shared signal set comes from Flexcomm 6. * 0b111..DATA input for this shared signal set comes from Flexcomm 7. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) /*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC0 does not contribute to this shared set. * 0b1..Data output from FC0 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) /*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC1 does not contribute to this shared set. * 0b1..Data output from FC1 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK (0x40000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT (18U) -/*! F20DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) +/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC2 does not contribute to this shared set. * 0b1..Data output from FC2 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK (0x80000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT (19U) -/*! FC3DATAOUTEN - Controls FC3 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC3 does not contribute to this shared set. - * 0b1..Data output from FC3 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) /*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC4 does not contribute to this shared set. * 0b1..Data output from FC4 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) /*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC5 does not contribute to this shared set. * 0b1..Data output from FC5 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) /*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC6 does not contribute to this shared set. * 0b1..Data output from FC6 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) /*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC7 does not contribute to this shared set. * 0b1..Data output from FC7 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK) +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) /*! @} */ -/* The count of SYSCTL_SHARECTRLSET_SHAREDCTRLSET */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_COUNT (2U) +/* The count of SYSCTL_SHAREDCTRLSET */ +#define SYSCTL_SHAREDCTRLSET_COUNT (2U) /*! @name USB_HS_STATUS - Status register for USB HS */ /*! @{ */ + #define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) #define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) /*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. @@ -21335,7 +25552,7 @@ typedef struct { /* SYSCTL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral SYSCTL base address */ #define SYSCTL_BASE (0x50023000u) /** Peripheral SYSCTL base address */ @@ -21403,7 +25620,9 @@ typedef struct { __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ uint8_t RESERVED_5[12]; __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_6[440]; + uint8_t RESERVED_6[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ } USART_Type; @@ -21418,6 +25637,7 @@ typedef struct { /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ /*! @{ */ + #define USART_CFG_ENABLE_MASK (0x1U) #define USART_CFG_ENABLE_SHIFT (0U) /*! ENABLE - USART Enable. @@ -21428,6 +25648,7 @@ typedef struct { * 0b1..Enabled. The USART is enabled for operation. */ #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) + #define USART_CFG_DATALEN_MASK (0xCU) #define USART_CFG_DATALEN_SHIFT (2U) /*! DATALEN - Selects the data size for the USART. @@ -21437,6 +25658,7 @@ typedef struct { * 0b11..Reserved. */ #define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) + #define USART_CFG_PARITYSEL_MASK (0x30U) #define USART_CFG_PARITYSEL_SHIFT (4U) /*! PARITYSEL - Selects what type of parity is used by the USART. @@ -21448,6 +25670,7 @@ typedef struct { * and the number of 1s in a received character is expected to be odd. */ #define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) + #define USART_CFG_STOPLEN_MASK (0x40U) #define USART_CFG_STOPLEN_SHIFT (6U) /*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. @@ -21455,6 +25678,7 @@ typedef struct { * 0b1..2 stop bits. This setting should only be used for asynchronous communication. */ #define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) + #define USART_CFG_MODE32K_MASK (0x80U) #define USART_CFG_MODE32K_SHIFT (7U) /*! MODE32K - Selects standard or 32 kHz clocking mode. @@ -21462,6 +25686,7 @@ typedef struct { * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. */ #define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) + #define USART_CFG_LINMODE_MASK (0x100U) #define USART_CFG_LINMODE_SHIFT (8U) /*! LINMODE - LIN break mode enable. @@ -21469,6 +25694,7 @@ typedef struct { * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. */ #define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) + #define USART_CFG_CTSEN_MASK (0x200U) #define USART_CFG_CTSEN_SHIFT (9U) /*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input @@ -21477,6 +25703,7 @@ typedef struct { * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. */ #define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) + #define USART_CFG_SYNCEN_MASK (0x800U) #define USART_CFG_SYNCEN_SHIFT (11U) /*! SYNCEN - Selects synchronous or asynchronous operation. @@ -21484,6 +25711,7 @@ typedef struct { * 0b1..Synchronous mode. */ #define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) + #define USART_CFG_CLKPOL_MASK (0x1000U) #define USART_CFG_CLKPOL_SHIFT (12U) /*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. @@ -21491,6 +25719,7 @@ typedef struct { * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. */ #define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) + #define USART_CFG_SYNCMST_MASK (0x4000U) #define USART_CFG_SYNCMST_SHIFT (14U) /*! SYNCMST - Synchronous mode Master select. @@ -21498,6 +25727,7 @@ typedef struct { * 0b1..Master. When synchronous mode is enabled, the USART is a master. */ #define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) + #define USART_CFG_LOOP_MASK (0x8000U) #define USART_CFG_LOOP_SHIFT (15U) /*! LOOP - Selects data loopback mode. @@ -21508,6 +25738,7 @@ typedef struct { * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. */ #define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) + #define USART_CFG_OETA_MASK (0x40000U) #define USART_CFG_OETA_SHIFT (18U) /*! OETA - Output Enable Turnaround time enable for RS-485 operation. @@ -21517,6 +25748,7 @@ typedef struct { * before it is deasserted. */ #define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) + #define USART_CFG_AUTOADDR_MASK (0x80000U) #define USART_CFG_AUTOADDR_SHIFT (19U) /*! AUTOADDR - Automatic Address matching enable. @@ -21526,6 +25758,7 @@ typedef struct { * the ADDR register as the address to match. */ #define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) + #define USART_CFG_OESEL_MASK (0x100000U) #define USART_CFG_OESEL_SHIFT (20U) /*! OESEL - Output Enable Select. @@ -21533,6 +25766,7 @@ typedef struct { * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. */ #define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) + #define USART_CFG_OEPOL_MASK (0x200000U) #define USART_CFG_OEPOL_SHIFT (21U) /*! OEPOL - Output Enable Polarity. @@ -21540,6 +25774,7 @@ typedef struct { * 0b1..High. If selected by OESEL, the output enable is active high. */ #define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) + #define USART_CFG_RXPOL_MASK (0x400000U) #define USART_CFG_RXPOL_SHIFT (22U) /*! RXPOL - Receive data polarity. @@ -21549,6 +25784,7 @@ typedef struct { * 0, start bit is 1, data is inverted, and the stop bit is 0. */ #define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) + #define USART_CFG_TXPOL_MASK (0x800000U) #define USART_CFG_TXPOL_SHIFT (23U) /*! TXPOL - Transmit data polarity. @@ -21562,6 +25798,7 @@ typedef struct { /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ /*! @{ */ + #define USART_CTL_TXBRKEN_MASK (0x2U) #define USART_CTL_TXBRKEN_SHIFT (1U) /*! TXBRKEN - Break Enable. @@ -21572,6 +25809,7 @@ typedef struct { * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. */ #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) + #define USART_CTL_ADDRDET_MASK (0x4U) #define USART_CTL_ADDRDET_SHIFT (2U) /*! ADDRDET - Enable address detect mode. @@ -21583,6 +25821,7 @@ typedef struct { * normally. */ #define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) + #define USART_CTL_TXDIS_MASK (0x40U) #define USART_CTL_TXDIS_SHIFT (6U) /*! TXDIS - Transmit Disable. @@ -21591,6 +25830,7 @@ typedef struct { * feature can be used to facilitate software flow control. */ #define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) + #define USART_CTL_CC_MASK (0x100U) #define USART_CTL_CC_SHIFT (8U) /*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. @@ -21600,6 +25840,7 @@ typedef struct { * Un_RxD independently from transmission on Un_TXD). */ #define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) + #define USART_CTL_CLRCCONRX_MASK (0x200U) #define USART_CTL_CLRCCONRX_SHIFT (9U) /*! CLRCCONRX - Clear Continuous Clock. @@ -21607,6 +25848,7 @@ typedef struct { * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. */ #define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) + #define USART_CTL_AUTOBAUD_MASK (0x10000U) #define USART_CTL_AUTOBAUD_SHIFT (16U) /*! AUTOBAUD - Autobaud enable. @@ -21620,160 +25862,314 @@ typedef struct { /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ /*! @{ */ + #define USART_STAT_RXIDLE_MASK (0x2U) #define USART_STAT_RXIDLE_SHIFT (1U) +/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of + * receiving data. When 1, indicates that the receiver is not currently in the process of receiving + * data. + */ #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) + #define USART_STAT_TXIDLE_MASK (0x8U) #define USART_STAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of + * sending data.When 1, indicate that the transmitter is not currently in the process of sending + * data. + */ #define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) + #define USART_STAT_CTS_MASK (0x10U) #define USART_STAT_CTS_SHIFT (4U) +/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the + * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode + * is enabled. + */ #define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) + #define USART_STAT_DELTACTS_MASK (0x20U) #define USART_STAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. + */ #define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) + #define USART_STAT_TXDISSTAT_MASK (0x40U) #define USART_STAT_TXDISSTAT_SHIFT (6U) +/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART + * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). + */ #define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) + #define USART_STAT_RXBRK_MASK (0x400U) #define USART_STAT_RXBRK_SHIFT (10U) +/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection + * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also + * be set when this condition occurs because the stop bit(s) for the character would be missing. + * RXBRK is cleared when the Un_RXD pin goes high. + */ #define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) + #define USART_STAT_DELTARXBRK_MASK (0x800U) #define USART_STAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. + */ #define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) + #define USART_STAT_START_MASK (0x1000U) #define USART_STAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily + * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. + * Cleared by software. + */ #define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) + #define USART_STAT_FRAMERRINT_MASK (0x2000U) #define USART_STAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a + * missing stop bit at the expected location. This could be an indication of a baud rate or + * configuration mismatch with the transmitting source. + */ #define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) + #define USART_STAT_PARITYERRINT_MASK (0x4000U) #define USART_STAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. + */ #define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) + #define USART_STAT_RXNOISEINT_MASK (0x8000U) #define USART_STAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to + * determine the value of each received data bit, except in synchronous mode. This acts as a + * noise filter if one sample disagrees. This flag is set when a received data bit contains one + * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or + * loss of synchronization during data reception. + */ #define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) + #define USART_STAT_ABERR_MASK (0x10000U) #define USART_STAT_ABERR_SHIFT (16U) +/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the + * end of the start bit that is being measured, essentially an auto baud time-out. + */ #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) /*! @} */ /*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ /*! @{ */ + #define USART_INTENSET_TXIDLEEN_MASK (0x8U) #define USART_INTENSET_TXIDLEEN_SHIFT (3U) +/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). + */ #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) + #define USART_INTENSET_DELTACTSEN_MASK (0x20U) #define USART_INTENSET_DELTACTSEN_SHIFT (5U) +/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. + */ #define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) + #define USART_INTENSET_TXDISEN_MASK (0x40U) #define USART_INTENSET_TXDISEN_SHIFT (6U) +/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by + * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. + */ #define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) + #define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) #define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection + * of a received break condition (break condition asserted or deasserted). + */ #define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) + #define USART_INTENSET_STARTEN_MASK (0x1000U) #define USART_INTENSET_STARTEN_SHIFT (12U) +/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. + */ #define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) + #define USART_INTENSET_FRAMERREN_MASK (0x2000U) #define USART_INTENSET_FRAMERREN_SHIFT (13U) +/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. + */ #define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) + #define USART_INTENSET_PARITYERREN_MASK (0x4000U) #define USART_INTENSET_PARITYERREN_SHIFT (14U) +/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. + */ #define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) + #define USART_INTENSET_RXNOISEEN_MASK (0x8000U) #define USART_INTENSET_RXNOISEEN_SHIFT (15U) +/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. + */ #define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) + #define USART_INTENSET_ABERREN_MASK (0x10000U) #define USART_INTENSET_ABERREN_SHIFT (16U) +/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. + */ #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) /*! @} */ /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ /*! @{ */ + #define USART_INTENCLR_TXIDLECLR_MASK (0x8U) #define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) + #define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) #define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) + #define USART_INTENCLR_TXDISCLR_MASK (0x40U) #define USART_INTENCLR_TXDISCLR_SHIFT (6U) +/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) + #define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) #define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) + #define USART_INTENCLR_STARTCLR_MASK (0x1000U) #define USART_INTENCLR_STARTCLR_SHIFT (12U) +/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) + #define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) #define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) + #define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) #define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) + #define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) #define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) + #define USART_INTENCLR_ABERRCLR_MASK (0x10000U) #define USART_INTENCLR_ABERRCLR_SHIFT (16U) +/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) /*! @} */ /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ /*! @{ */ + #define USART_BRG_BRGVAL_MASK (0xFFFFU) #define USART_BRG_BRGVAL_SHIFT (0U) +/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on + * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is + * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART + * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. + */ #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) /*! @} */ /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ /*! @{ */ + #define USART_INTSTAT_TXIDLE_MASK (0x8U) #define USART_INTSTAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle status. + */ #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) + #define USART_INTSTAT_DELTACTS_MASK (0x20U) #define USART_INTSTAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. + */ #define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) + #define USART_INTSTAT_TXDISINT_MASK (0x40U) #define USART_INTSTAT_TXDISINT_SHIFT (6U) +/*! TXDISINT - Transmitter Disabled Interrupt flag. + */ #define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) + #define USART_INTSTAT_DELTARXBRK_MASK (0x800U) #define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. + */ #define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) + #define USART_INTSTAT_START_MASK (0x1000U) #define USART_INTSTAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. + */ #define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) + #define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) #define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. + */ #define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) + #define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) #define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. + */ #define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) + #define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) #define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. + */ #define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) + #define USART_INTSTAT_ABERRINT_MASK (0x10000U) #define USART_INTSTAT_ABERRINT_SHIFT (16U) +/*! ABERRINT - Auto baud Error Interrupt flag. + */ #define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) /*! @} */ /*! @name OSR - Oversample selection register for asynchronous communication. */ /*! @{ */ + #define USART_OSR_OSRVAL_MASK (0xFU) #define USART_OSR_OSRVAL_SHIFT (0U) +/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to + * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive + * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. + */ #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) /*! @} */ /*! @name ADDR - Address register for automatic address matching. */ /*! @{ */ + #define USART_ADDR_ADDRESS_MASK (0xFFU) #define USART_ADDR_ADDRESS_SHIFT (0U) +/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is + * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). + */ #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) /*! @} */ /*! @name FIFOCFG - FIFO configuration and enable register. */ /*! @{ */ + #define USART_FIFOCFG_ENABLETX_MASK (0x1U) #define USART_FIFOCFG_ENABLETX_SHIFT (0U) /*! ENABLETX - Enable the transmit FIFO. @@ -21781,6 +26177,7 @@ typedef struct { * 0b1..The transmit FIFO is enabled. */ #define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) + #define USART_FIFOCFG_ENABLERX_MASK (0x2U) #define USART_FIFOCFG_ENABLERX_SHIFT (1U) /*! ENABLERX - Enable the receive FIFO. @@ -21788,9 +26185,14 @@ typedef struct { * 0b1..The receive FIFO is enabled. */ #define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) + #define USART_FIFOCFG_SIZE_MASK (0x30U) #define USART_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ #define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) + #define USART_FIFOCFG_DMATX_MASK (0x1000U) #define USART_FIFOCFG_DMATX_SHIFT (12U) /*! DMATX - DMA configuration for transmit. @@ -21798,6 +26200,7 @@ typedef struct { * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. */ #define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) + #define USART_FIFOCFG_DMARX_MASK (0x2000U) #define USART_FIFOCFG_DMARX_SHIFT (13U) /*! DMARX - DMA configuration for receive. @@ -21805,6 +26208,7 @@ typedef struct { * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. */ #define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) + #define USART_FIFOCFG_WAKETX_MASK (0x4000U) #define USART_FIFOCFG_WAKETX_SHIFT (14U) /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power @@ -21817,6 +26221,7 @@ typedef struct { * FIFOTRIG, even when the TXLVL interrupt is not enabled. */ #define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) + #define USART_FIFOCFG_WAKERX_MASK (0x8000U) #define USART_FIFOCFG_WAKERX_SHIFT (15U) /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power @@ -21829,54 +26234,93 @@ typedef struct { * FIFOTRIG, even when the RXLVL interrupt is not enabled. */ #define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) + #define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) #define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ #define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) + #define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) #define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -#define USART_FIFOCFG_POPDBG_MASK (0x40000U) -#define USART_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. */ -#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK) +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) /*! @} */ /*! @name FIFOSTAT - FIFO status register. */ /*! @{ */ + #define USART_FIFOSTAT_TXERR_MASK (0x1U) #define USART_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ #define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) + #define USART_FIFOSTAT_RXERR_MASK (0x2U) #define USART_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ #define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) + #define USART_FIFOSTAT_PERINT_MASK (0x8U) #define USART_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ #define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) + #define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) #define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ #define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) + #define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) #define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ #define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) + #define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) #define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ #define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) + #define USART_FIFOSTAT_RXFULL_MASK (0x80U) #define USART_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ #define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) + #define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) #define USART_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ #define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) + #define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define USART_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ #define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) /*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ /*! @{ */ + #define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) #define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -21885,6 +26329,7 @@ typedef struct { * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. */ #define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) + #define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) #define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -21893,16 +26338,32 @@ typedef struct { * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. */ #define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) + #define USART_FIFOTRIG_TXLVL_MASK (0xF00U) #define USART_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ #define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) + #define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) #define USART_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ #define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) /*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ /*! @{ */ + #define USART_FIFOINTENSET_TXERR_MASK (0x1U) #define USART_FIFOINTENSET_TXERR_SHIFT (0U) /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. @@ -21910,6 +26371,7 @@ typedef struct { * 0b1..An interrupt will be generated when a transmit error occurs. */ #define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) + #define USART_FIFOINTENSET_RXERR_MASK (0x2U) #define USART_FIFOINTENSET_RXERR_SHIFT (1U) /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. @@ -21917,6 +26379,7 @@ typedef struct { * 0b1..An interrupt will be generated when a receive error occurs. */ #define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) + #define USART_FIFOINTENSET_TXLVL_MASK (0x4U) #define USART_FIFOINTENSET_TXLVL_SHIFT (2U) /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level @@ -21926,6 +26389,7 @@ typedef struct { * to the level specified by TXLVL in the FIFOTRIG register. */ #define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) + #define USART_FIFOINTENSET_RXLVL_MASK (0x8U) #define USART_FIFOINTENSET_RXLVL_SHIFT (3U) /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level @@ -21939,91 +26403,177 @@ typedef struct { /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ /*! @{ */ + #define USART_FIFOINTENCLR_TXERR_MASK (0x1U) #define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) + #define USART_FIFOINTENCLR_RXERR_MASK (0x2U) #define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) + #define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) #define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) + #define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) #define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) /*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ /*! @{ */ + #define USART_FIFOINTSTAT_TXERR_MASK (0x1U) #define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ #define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) + #define USART_FIFOINTSTAT_RXERR_MASK (0x2U) #define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ #define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) + #define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) #define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ #define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) + #define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) #define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ #define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) + #define USART_FIFOINTSTAT_PERINT_MASK (0x10U) #define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ #define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) /*! @} */ /*! @name FIFOWR - FIFO write data. */ /*! @{ */ + #define USART_FIFOWR_TXDATA_MASK (0x1FFU) #define USART_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. + */ #define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) /*! @} */ /*! @name FIFORD - FIFO read data. */ /*! @{ */ + #define USART_FIFORD_RXDATA_MASK (0x1FFU) #define USART_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + */ #define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) + #define USART_FIFORD_FRAMERR_MASK (0x2000U) #define USART_FIFORD_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ #define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) + #define USART_FIFORD_PARITYERR_MASK (0x4000U) #define USART_FIFORD_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ #define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) + #define USART_FIFORD_RXNOISE_MASK (0x8000U) #define USART_FIFORD_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. + */ #define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) /*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ /*! @{ */ + #define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) #define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + */ #define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) + #define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) #define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ #define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) + #define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) #define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ #define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) + #define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) #define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. + */ #define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) /*! @} */ +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + /*! @name ID - Peripheral identification register. */ /*! @{ */ + #define USART_ID_APERTURE_MASK (0xFFU) #define USART_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ #define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) + #define USART_ID_MINOR_REV_MASK (0xF00U) #define USART_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ #define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) + #define USART_ID_MAJOR_REV_MASK (0xF000U) #define USART_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ #define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) + #define USART_ID_ID_MASK (0xFFFF0000U) #define USART_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ #define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) /*! @} */ @@ -22034,7 +26584,7 @@ typedef struct { /* USART - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USART0 base address */ #define USART0_BASE (0x50086000u) /** Peripheral USART0 base address */ @@ -22190,15 +26740,31 @@ typedef struct { /*! @name DEVCMDSTAT - USB Device Command/Status register */ /*! @{ */ + #define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) #define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit + * is set, the device will respond on packets for function address DEV_ADDR. When receiving a + * SetAddress Control Request from the USB host, software must program the new address before + * completing the status phase of the SetAddress Control Request. + */ #define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) + #define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) #define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. + */ #define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) + #define USB_DEVCMDSTAT_SETUP_MASK (0x100U) #define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this + * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW + * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the + * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. + */ #define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) + #define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) #define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) /*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: @@ -22206,6 +26772,7 @@ typedef struct { * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. */ #define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) + #define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) #define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) /*! LPM_SUP - LPM Supported: @@ -22213,6 +26780,7 @@ typedef struct { * 0b1..LPM supported. */ #define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) + #define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) #define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) /*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP @@ -22220,6 +26788,7 @@ typedef struct { * 0b1..Both acknowledged and NAKed packets generate interrupts. */ #define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) + #define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) #define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) /*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP @@ -22227,6 +26796,7 @@ typedef struct { * 0b1..Both acknowledged and NAKed packets generate interrupts. */ #define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) + #define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) #define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) /*! INTONNAK_CO - Interrupt on NAK for control OUT EP @@ -22234,6 +26804,7 @@ typedef struct { * 0b1..Both acknowledged and NAKed packets generate interrupts. */ #define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) + #define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) #define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) /*! INTONNAK_CI - Interrupt on NAK for control IN EP @@ -22241,37 +26812,93 @@ typedef struct { * 0b1..Both acknowledged and NAKed packets generate interrupts. */ #define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) + #define USB_DEVCMDSTAT_DCON_MASK (0x10000U) #define USB_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device + * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and + * the VBUSDEBOUNCED bit is one. + */ #define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) + #define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) #define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set + * to 1 when the device hasn't seen any activity on its upstream port for more than 3 + * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and + * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen + * when the device is connected (Connect bit = 1). When the device is not connected or not + * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. + */ #define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) + #define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) #define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is + * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the + * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend + * bit = 1) and the software writes a zero to this bit, the device will generate a remote + * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this + * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the + * LPM_SUPP bit is equal to one. + */ #define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) + #define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) #define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake + * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the + * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset + * is received. Software can use this bit to check if the remote wake-up feature is enabled by the + * host for the LPM transaction. + */ #define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) + #define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) #define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up + * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. + */ #define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) + #define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) #define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit + * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The + * device is disconnected - The device receives resume signaling on its upstream port. The bit is + * reset by writing a one to it. + */ #define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) + #define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) #define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On + * a bus reset the device will automatically go to the default state (unconfigured and responding + * to address 0). The bit is reset by writing a one to it. + */ #define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) + #define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) #define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when + * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and + * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. + */ #define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) /*! @} */ /*! @name INFO - USB Info register */ /*! @{ */ + #define USB_INFO_FRAME_NR_MASK (0x7FFU) #define USB_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. + * In case no SOF was received by the device at the beginning of a frame, the frame number + * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC + * error, the frame number returned will be the corrupted frame number as received by the device. + */ #define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) + #define USB_INFO_ERR_CODE_MASK (0x7800U) #define USB_INFO_ERR_CODE_SHIFT (11U) /*! ERR_CODE - The error code which last occurred: @@ -22293,132 +26920,285 @@ typedef struct { * 0b1111..Wrong data toggle */ #define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) + #define USB_INFO_MINREV_MASK (0xFF0000U) #define USB_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor Revision. + */ #define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) + #define USB_INFO_MAJREV_MASK (0xFF000000U) #define USB_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major Revision. + */ #define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) /*! @} */ /*! @name EPLISTSTART - USB EP Command/Status List start address */ /*! @{ */ + #define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) #define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +/*! EP_LIST - Start address of the USB EP Command/Status List. + */ #define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) /*! @} */ /*! @name DATABUFSTART - USB Data buffer start address */ /*! @{ */ + #define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) #define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. + */ #define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) /*! @} */ /*! @name LPM - USB Link Power Management register */ /*! @{ */ + #define USB_LPM_HIRD_HW_MASK (0xFU) #define USB_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token + */ #define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) + #define USB_LPM_HIRD_SW_MASK (0xF0U) #define USB_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB + * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. + */ #define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) + #define USB_LPM_DATA_PENDING_MASK (0x100U) #define USB_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and + * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has + * still data pending and LPM is supported, it must set this bit to 1. + */ #define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) /*! @} */ /*! @name EPSKIP - USB Endpoint skip */ /*! @{ */ + #define USB_EPSKIP_SKIP_MASK (0x3FFU) #define USB_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. When HW has + * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An + * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, + * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. + */ #define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) /*! @} */ /*! @name EPINUSE - USB Endpoint Buffer in use */ /*! @{ */ + #define USB_EPINUSE_BUF_MASK (0x3FCU) #define USB_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer + * 0. 1: HW is accessing buffer 1. + */ #define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) /*! @} */ /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ /*! @{ */ + #define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) #define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: + * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding + * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle + * the EPINUSE bit when it clears the Active bit for the buffer. + */ #define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) /*! @} */ /*! @name INTSTAT - USB interrupt status register */ /*! @{ */ + #define USB_INTSTAT_EP0OUT_MASK (0x1U) #define USB_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set + * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is + * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a + * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a + * one to it. + */ #define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) + #define USB_INTSTAT_EP0IN_MASK (0x2U) #define USB_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if + * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this + * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can + * clear this bit by writing a one to it. + */ #define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) + #define USB_INTSTAT_EP1OUT_MASK (0x4U) #define USB_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by + * writing a one to it. + */ #define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) + #define USB_INTSTAT_EP1IN_MASK (0x8U) #define USB_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing + * a one to it. + */ #define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) + #define USB_INTSTAT_EP2OUT_MASK (0x10U) #define USB_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by + * writing a one to it. + */ #define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) + #define USB_INTSTAT_EP2IN_MASK (0x20U) #define USB_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing + * a one to it. + */ #define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) + #define USB_INTSTAT_EP3OUT_MASK (0x40U) #define USB_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by + * writing a one to it. + */ #define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) + #define USB_INTSTAT_EP3IN_MASK (0x80U) #define USB_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing + * a one to it. + */ #define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) + #define USB_INTSTAT_EP4OUT_MASK (0x100U) #define USB_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by + * writing a one to it. + */ #define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) + #define USB_INTSTAT_EP4IN_MASK (0x200U) #define USB_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing + * a one to it. + */ #define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) + #define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) #define USB_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit + * and the DCON bit are set. This bit can be used by software when handling isochronous + * endpoints. Software can clear this bit by writing a one to it. + */ #define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) + #define USB_INTSTAT_DEV_INT_MASK (0x80000000U) #define USB_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device + * Status Change register are set. Software can clear this bit by writing a one to it. + */ #define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) /*! @} */ /*! @name INTEN - USB interrupt enable register */ /*! @{ */ + #define USB_INTEN_EP_INT_EN_MASK (0x3FFU) #define USB_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ #define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) + #define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) #define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt + * routing bit. + */ #define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) + #define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) #define USB_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ #define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) /*! @} */ /*! @name INTSETSTAT - USB set interrupt status register */ /*! @{ */ + #define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) #define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status register + * is returned. + */ #define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) + #define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) #define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ #define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) + #define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) #define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ #define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) /*! @} */ /*! @name EPTOGGLE - USB Endpoint toggle register */ /*! @{ */ + #define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) #define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + */ #define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) /*! @} */ @@ -22429,7 +27209,7 @@ typedef struct { /* USB - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USB0 base address */ #define USB0_BASE (0x50084000u) /** Peripheral USB0 base address */ @@ -22483,15 +27263,15 @@ typedef struct { __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ - __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ + __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ - __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ + __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ - __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ - __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ + __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ + __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ @@ -22513,351 +27293,625 @@ typedef struct { /*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ /*! @{ */ + #define USBFSH_HCREVISION_REV_MASK (0xFFU) #define USBFSH_HCREVISION_REV_SHIFT (0U) +/*! REV - Revision. + */ #define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) /*! @} */ /*! @name HCCONTROL - Defines the operating modes of the HC */ /*! @{ */ + #define USBFSH_HCCONTROL_CBSR_MASK (0x3U) #define USBFSH_HCCONTROL_CBSR_SHIFT (0U) +/*! CBSR - ControlBulkServiceRatio. + */ #define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) + #define USBFSH_HCCONTROL_PLE_MASK (0x4U) #define USBFSH_HCCONTROL_PLE_SHIFT (2U) +/*! PLE - PeriodicListEnable. + */ #define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) + #define USBFSH_HCCONTROL_IE_MASK (0x8U) #define USBFSH_HCCONTROL_IE_SHIFT (3U) +/*! IE - IsochronousEnable. + */ #define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) + #define USBFSH_HCCONTROL_CLE_MASK (0x10U) #define USBFSH_HCCONTROL_CLE_SHIFT (4U) +/*! CLE - ControlListEnable. + */ #define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) + #define USBFSH_HCCONTROL_BLE_MASK (0x20U) #define USBFSH_HCCONTROL_BLE_SHIFT (5U) +/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. + */ #define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) + #define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) #define USBFSH_HCCONTROL_HCFS_SHIFT (6U) +/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL + * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin + * 1 ms later. + */ #define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) + #define USBFSH_HCCONTROL_IR_MASK (0x100U) #define USBFSH_HCCONTROL_IR_SHIFT (8U) +/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. + */ #define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) + #define USBFSH_HCCONTROL_RWC_MASK (0x200U) #define USBFSH_HCCONTROL_RWC_SHIFT (9U) +/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. + */ #define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) + #define USBFSH_HCCONTROL_RWE_MASK (0x400U) #define USBFSH_HCCONTROL_RWE_SHIFT (10U) +/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature + * upon the detection of upstream resume signaling. + */ #define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) /*! @} */ /*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ /*! @{ */ + #define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) #define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) +/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. + */ #define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) + #define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) #define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) +/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. + */ #define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) + #define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) #define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) +/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. + */ #define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) + #define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) #define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) +/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. + */ #define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) + #define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) #define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) +/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. + */ #define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) /*! @} */ /*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ /*! @{ */ + #define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) #define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) +/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and + * after the update of HccaFrameNumber. + */ #define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) + #define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) #define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) +/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. + */ #define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) + #define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) #define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) +/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. + */ #define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) + #define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) #define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) +/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. + */ #define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) + #define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) #define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) +/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. + */ #define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) + #define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) #define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) +/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, + * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. + */ #define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) + #define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) #define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) +/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any + * of HcRhPortStatus[NumberofDownstreamPort] has changed. + */ #define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) + #define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) #define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) +/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. + */ #define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) /*! @} */ /*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ /*! @{ */ + #define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) #define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) + #define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) #define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) + #define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) #define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) + #define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) #define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) + #define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) #define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) + #define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) #define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) + #define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) #define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) + #define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) #define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) + #define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) #define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) +/*! MIE - Master Interrupt Enable. + */ #define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) /*! @} */ /*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ /*! @{ */ + #define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) #define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) + #define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) #define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) + #define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) #define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) + #define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) #define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) + #define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) #define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) + #define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) #define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) + #define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) #define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) + #define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) #define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) + #define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) #define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) +/*! MIE - A 0 written to this field is ignored by HC. + */ #define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) /*! @} */ /*! @name HCHCCA - Contains the physical address of the host controller communication area */ /*! @{ */ + #define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) #define USBFSH_HCHCCA_HCCA_SHIFT (8U) +/*! HCCA - Base address of the Host Controller Communication Area. + */ #define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) /*! @} */ /*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ /*! @{ */ + #define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) #define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) +/*! PCED - The content of this register is updated by HC after a periodic ED is processed. + */ #define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) /*! @} */ /*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ /*! @{ */ + #define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) #define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) +/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. + */ #define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) /*! @} */ /*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ /*! @{ */ + #define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) #define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) +/*! CCED - ControlCurrentED. + */ #define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) /*! @} */ /*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ /*! @{ */ + #define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) #define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) +/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. + */ #define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) /*! @} */ /*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ /*! @{ */ + #define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) #define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) +/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. + */ #define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) /*! @} */ /*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ /*! @{ */ + #define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) #define USBFSH_HCDONEHEAD_DH_SHIFT (4U) +/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. + */ #define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) /*! @} */ /*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ /*! @{ */ + #define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) #define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) +/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. + */ #define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) + #define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) #define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) +/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data + * Packet Counter at the beginning of each frame. + */ #define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) + #define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) #define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) +/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. + */ #define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) /*! @} */ /*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ /*! @{ */ + #define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) #define USBFSH_HCFMREMAINING_FR_SHIFT (0U) +/*! FR - FrameRemaining This counter is decremented at each bit time. + */ #define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) + #define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) #define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) +/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval + * whenever FrameRemaining reaches 0. + */ #define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) /*! @} */ /*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ /*! @{ */ + #define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) #define USBFSH_HCFMNUMBER_FN_SHIFT (0U) +/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. + */ #define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) /*! @} */ /*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ /*! @{ */ + #define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) #define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) +/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. + */ #define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) /*! @} */ /*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ /*! @{ */ + #define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) #define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) +/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field + * prior to initiating a Low Speed transaction. + */ #define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) /*! @} */ /*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ /*! @{ */ + #define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) #define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) +/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. + */ #define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) + #define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) #define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) +/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. + */ #define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) + #define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) #define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) +/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. + */ #define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) + #define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) #define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) +/*! DT - DeviceType This bit specifies that the root hub is not a compound device. + */ #define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) + #define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) #define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) +/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. + */ #define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) + #define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) #define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) +/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. + */ #define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) + #define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) #define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) +/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before + * accessing a powered-on port of the root hub. + */ #define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) /*! @} */ /*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ /*! @{ */ + #define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) #define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) +/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. + */ #define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) + #define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) #define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) +/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control + * command when PowerSwitchingMode is set. + */ #define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) /*! @} */ /*! @name HCRHSTATUS - This register is divided into two parts */ /*! @{ */ + #define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) #define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) +/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; + * thus, this bit is always read as 0. + */ #define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) + #define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) #define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) +/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. + */ #define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) + #define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) #define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) +/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume + * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected + * interrupt. + */ #define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) + #define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) #define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) +/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. + */ #define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) + #define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) #define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) +/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. + */ #define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) + #define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) #define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) +/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. + */ #define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) /*! @} */ /*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ /*! @{ */ + #define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) #define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) +/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. + */ #define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) + #define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) #define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) +/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. + */ #define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) + #define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) #define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) +/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. + */ #define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) + #define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) #define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) +/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in + * such a way that overcurrent conditions are reported on a per-port basis. + */ #define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) + #define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) #define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) +/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. + */ #define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) + #define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) #define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) +/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type + * of power switching implemented. + */ #define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) + #define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) #define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) +/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. + */ #define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) + #define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) #define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) +/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. + */ #define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) + #define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) #define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) +/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. + */ #define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) + #define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) #define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) +/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. + */ #define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) + #define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) #define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) +/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. + */ #define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) + #define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) #define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) +/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. + */ #define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) /*! @} */ /*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ /*! @{ */ + #define USBFSH_PORTMODE_ID_MASK (0x1U) #define USBFSH_PORTMODE_ID_SHIFT (0U) +/*! ID - Port ID pin value. + */ #define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) + #define USBFSH_PORTMODE_ID_EN_MASK (0x100U) #define USBFSH_PORTMODE_ID_EN_SHIFT (8U) +/*! ID_EN - Port ID pin pull-up enable. + */ #define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) + #define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) #define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - 1: device 0: host. + */ #define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) /*! @} */ @@ -22868,7 +27922,7 @@ typedef struct { /* USBFSH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USBFSH base address */ #define USBFSH_BASE (0x500A2000u) /** Peripheral USBFSH base address */ @@ -22928,8 +27982,6 @@ typedef struct { __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ uint8_t RESERVED_0[8]; __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ - uint8_t RESERVED_1[4]; - __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */ } USBHSD_Type; /* ---------------------------------------------------------------------------- @@ -22943,236 +27995,382 @@ typedef struct { /*! @name DEVCMDSTAT - USB Device Command/Status register */ /*! @{ */ + #define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) #define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. + */ #define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) + #define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) #define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. + */ #define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) + #define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) #define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. + */ #define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) + #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. + */ #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK) + #define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) #define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported:. + */ #define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) + #define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) #define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. + */ #define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) + #define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) #define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. + */ #define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) + #define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) #define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:. + */ #define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) + #define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) #define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP:. + */ #define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) + #define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) #define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. + */ #define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) + #define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) #define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. + */ #define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) + #define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) #define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. + */ #define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) + #define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) #define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. + */ #define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) + #define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) #define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) +/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: + * full-speed 10b: high-speed 11b: super-speed (reserved for future use). + */ #define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) + #define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) #define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. + */ #define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) + #define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) #define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. + */ #define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) + #define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) #define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. + */ #define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) + #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) +/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. + */ #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) + #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) +/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. + * 0b000..Test mode disabled. + * 0b001..Test_J. + * 0b010..Test_K. + * 0b011..Test_SE0_NAK. + * 0b100..Test_Packet. + * 0b101..Test_Force_Enable. + */ #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) /*! @} */ /*! @name INFO - USB Info register */ /*! @{ */ + #define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) #define USBHSD_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. + */ #define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) + #define USBHSD_INFO_ERR_CODE_MASK (0x7800U) #define USBHSD_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred:. + */ #define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) -#define USBHSD_INFO_Minrev_MASK (0xFF0000U) -#define USBHSD_INFO_Minrev_SHIFT (16U) -#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK) -#define USBHSD_INFO_Majrev_MASK (0xFF000000U) -#define USBHSD_INFO_Majrev_SHIFT (24U) -#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK) + +#define USBHSD_INFO_MINREV_MASK (0xFF0000U) +#define USBHSD_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor revision. + */ +#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK) + +#define USBHSD_INFO_MAJREV_MASK (0xFF000000U) +#define USBHSD_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major revision. + */ +#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK) /*! @} */ /*! @name EPLISTSTART - USB EP Command/Status List start address */ /*! @{ */ + #define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) #define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) +/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. + */ #define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) + #define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) #define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) +/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. + */ #define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) /*! @} */ /*! @name DATABUFSTART - USB Data buffer start address */ /*! @{ */ + #define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) #define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) +/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located. + */ #define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) /*! @} */ /*! @name LPM - USB Link Power Management register */ /*! @{ */ + #define USBHSD_LPM_HIRD_HW_MASK (0xFU) #define USBHSD_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. + */ #define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) + #define USBHSD_LPM_HIRD_SW_MASK (0xF0U) #define USBHSD_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. + */ #define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) + #define USBHSD_LPM_DATA_PENDING_MASK (0x100U) #define USBHSD_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. + */ #define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) /*! @} */ /*! @name EPSKIP - USB Endpoint skip */ /*! @{ */ + #define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) #define USBHSD_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. + */ #define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) /*! @} */ /*! @name EPINUSE - USB Endpoint Buffer in use */ /*! @{ */ + #define USBHSD_EPINUSE_BUF_MASK (0xFFCU) #define USBHSD_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. + */ #define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) /*! @} */ /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ /*! @{ */ + #define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) #define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. + */ #define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) /*! @} */ /*! @name INTSTAT - USB interrupt status register */ /*! @{ */ + #define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) #define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. + */ #define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) + #define USBHSD_INTSTAT_EP0IN_MASK (0x2U) #define USBHSD_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. + */ #define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) + #define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) #define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. + */ #define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) + #define USBHSD_INTSTAT_EP1IN_MASK (0x8U) #define USBHSD_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. + */ #define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) + #define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) #define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. + */ #define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) + #define USBHSD_INTSTAT_EP2IN_MASK (0x20U) #define USBHSD_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. + */ #define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) + #define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) #define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. + */ #define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) + #define USBHSD_INTSTAT_EP3IN_MASK (0x80U) #define USBHSD_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. + */ #define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) + #define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) #define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. + */ #define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) + #define USBHSD_INTSTAT_EP4IN_MASK (0x200U) #define USBHSD_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. + */ #define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) + #define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) #define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) +/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction. + */ #define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) + #define USBHSD_INTSTAT_EP5IN_MASK (0x800U) #define USBHSD_INTSTAT_EP5IN_SHIFT (11U) +/*! EP5IN - Interrupt status register bit for the EP5 IN direction. + */ #define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) + #define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) #define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. + */ #define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) + #define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) #define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. + */ #define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) /*! @} */ /*! @name INTEN - USB interrupt enable register */ /*! @{ */ + #define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) #define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ #define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) + #define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) #define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ #define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) + #define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) #define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ #define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) /*! @} */ /*! @name INTSETSTAT - USB set interrupt status register */ /*! @{ */ + #define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) #define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ #define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) + #define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) #define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ #define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) + #define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) #define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ #define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) /*! @} */ /*! @name EPTOGGLE - USB Endpoint toggle register */ /*! @{ */ + #define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) #define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + */ #define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) /*! @} */ -/*! @name ULPIDEBUG - UTMI/ULPI debug register */ -/*! @{ */ -#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU) -#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U) -#define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK) -#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U) -#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U) -#define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK) -#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U) -#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U) -#define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK) -#define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U) -#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U) -#define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK) -#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U) -#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U) -#define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK) -#define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U) -#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U) -#define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK) -/*! @} */ - /*! * @} @@ -23180,7 +28378,7 @@ typedef struct { /* USBHSD - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USBHSD base address */ #define USBHSD_BASE (0x50094000u) /** Peripheral USBHSD base address */ @@ -23229,24 +28427,24 @@ typedef struct { typedef struct { __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ - __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */ + uint8_t RESERVED_0[4]; __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ - __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ - __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ - __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ - __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ + __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ + __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ + __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ + __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ - __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */ - __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */ - __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */ - __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */ - __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */ - __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */ - __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ - __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */ + __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */ + __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */ + __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */ + __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */ + __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */ + __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */ + __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ + uint8_t RESERVED_1[4]; __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ } USBHSH_Type; @@ -23261,307 +28459,446 @@ typedef struct { /*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ /*! @{ */ + #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - Capability Length: This is used as an offset. + */ #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) + #define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) #define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) +/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major + * revision [23:16] = Minor revision Major revisions used: 0x01: USB2. + */ #define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) /*! @} */ /*! @name HCSPARAMS - Host Controller Structural Parameters */ /*! @{ */ + #define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) #define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. + */ #define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) + #define USBHSH_HCSPARAMS_PPC_MASK (0x10U) #define USBHSH_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - This field indicates whether the host controller implementation includes port power control. + */ #define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) + #define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) #define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) +/*! P_INDICATOR - This bit indicates whether the ports support port indicator control. + */ #define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) /*! @} */ -/*! @name HCCPARAMS - Host Controller Capability Parameters */ -/*! @{ */ -#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U) -#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U) -#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK) -/*! @} */ - /*! @name FLADJ_FRINDEX - Frame Length Adjustment */ /*! @{ */ + #define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) #define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) +/*! FLADJ - Frame Length Timing Value. + */ #define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) + #define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) #define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) +/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. + */ #define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) /*! @} */ -/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */ +/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */ /*! @{ */ -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK) + +#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U) +#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U) +/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. + */ +#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK) + +#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U) +#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U) +/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. + */ +#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK) /*! @} */ -/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */ +/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */ /*! @{ */ -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK) + +#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U) +#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U) +/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. + */ +#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK) + +#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U) +#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U) +/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. + */ +#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK) /*! @} */ -/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */ +/*! @name INTPTD - Memory base address where INT PTD0 is stored */ /*! @{ */ -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK) + +#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U) +#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U) +/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. + */ +#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK) + +#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U) +#define USBHSH_INTPTD_INT_BASE_SHIFT (10U) +/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list. + */ +#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK) /*! @} */ -/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */ +/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */ /*! @{ */ -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U) -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U) -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK) + +#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U) +#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U) +/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. + */ +#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK) /*! @} */ /*! @name USBCMD - USB Command register */ /*! @{ */ + #define USBHSH_USBCMD_RS_MASK (0x1U) #define USBHSH_USBCMD_RS_SHIFT (0U) +/*! RS - Run/Stop: 1b = Run. + */ #define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) + #define USBHSH_USBCMD_HCRESET_MASK (0x2U) #define USBHSH_USBCMD_HCRESET_SHIFT (1U) +/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. + */ #define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) + #define USBHSH_USBCMD_FLS_MASK (0xCU) #define USBHSH_USBCMD_FLS_SHIFT (2U) +/*! FLS - Frame List Size: This field specifies the size of the frame list. + */ #define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) + #define USBHSH_USBCMD_LHCR_MASK (0x80U) #define USBHSH_USBCMD_LHCR_SHIFT (7U) +/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host + * controller without affecting the state of the ports. + */ #define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) + #define USBHSH_USBCMD_ATL_EN_MASK (0x100U) #define USBHSH_USBCMD_ATL_EN_SHIFT (8U) +/*! ATL_EN - ATL List enabled. + */ #define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) + #define USBHSH_USBCMD_ISO_EN_MASK (0x200U) #define USBHSH_USBCMD_ISO_EN_SHIFT (9U) +/*! ISO_EN - ISO List enabled. + */ #define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) + #define USBHSH_USBCMD_INT_EN_MASK (0x400U) #define USBHSH_USBCMD_INT_EN_SHIFT (10U) +/*! INT_EN - INT List enabled. + */ #define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) -#define USBHSH_USBCMD_HIRD_MASK (0xF000000U) -#define USBHSH_USBCMD_HIRD_SHIFT (24U) -#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK) -#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U) -#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U) -#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK) /*! @} */ /*! @name USBSTS - USB Interrupt Status register */ /*! @{ */ + #define USBHSH_USBSTS_PCD_MASK (0x4U) #define USBHSH_USBSTS_PCD_SHIFT (2U) +/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a + * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a + * result of a J-K transition detected on a suspended port. + */ #define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) + #define USBHSH_USBSTS_FLR_MASK (0x8U) #define USBHSH_USBSTS_FLR_SHIFT (3U) +/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list + * index rolls over its maximum value to 0. + */ #define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) + #define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) #define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) +/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. + */ #define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) + #define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) #define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) +/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. + */ #define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) + #define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) #define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) +/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. + */ #define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) + #define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) #define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) +/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. + */ #define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) /*! @} */ /*! @name USBINTR - USB Interrupt Enable register */ /*! @{ */ + #define USBHSH_USBINTR_PCDE_MASK (0x4U) #define USBHSH_USBINTR_PCDE_SHIFT (2U) +/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. + */ #define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) + #define USBHSH_USBINTR_FLRE_MASK (0x8U) #define USBHSH_USBINTR_FLRE_SHIFT (3U) +/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. + */ #define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) + #define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) #define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) +/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. + */ #define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) + #define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) #define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) +/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. + */ #define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) + #define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) #define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) +/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. + */ #define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) + #define USBHSH_USBINTR_SOF_E_MASK (0x80000U) #define USBHSH_USBINTR_SOF_E_SHIFT (19U) +/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. + */ #define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) /*! @} */ /*! @name PORTSC1 - Port Status and Control register */ /*! @{ */ + #define USBHSH_PORTSC1_CCS_MASK (0x1U) #define USBHSH_PORTSC1_CCS_SHIFT (0U) +/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port. + */ #define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) + #define USBHSH_PORTSC1_CSC_MASK (0x2U) #define USBHSH_PORTSC1_CSC_SHIFT (1U) +/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. + */ #define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) + #define USBHSH_PORTSC1_PED_MASK (0x4U) #define USBHSH_PORTSC1_PED_SHIFT (2U) +/*! PED - Port Enabled/Disabled. + */ #define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) + #define USBHSH_PORTSC1_PEDC_MASK (0x8U) #define USBHSH_PORTSC1_PEDC_SHIFT (3U) +/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. + */ #define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) + #define USBHSH_PORTSC1_OCA_MASK (0x10U) #define USBHSH_PORTSC1_OCA_SHIFT (4U) +/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition. + */ #define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) + #define USBHSH_PORTSC1_OCC_MASK (0x20U) #define USBHSH_PORTSC1_OCC_SHIFT (5U) +/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed. + */ #define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) + #define USBHSH_PORTSC1_FPR_MASK (0x40U) #define USBHSH_PORTSC1_FPR_SHIFT (6U) +/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. + */ #define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) + #define USBHSH_PORTSC1_SUSP_MASK (0x80U) #define USBHSH_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - Suspend: Logic 1 means port is in the suspend state. + */ #define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) + #define USBHSH_PORTSC1_PR_MASK (0x100U) #define USBHSH_PORTSC1_PR_SHIFT (8U) +/*! PR - Port Reset: Logic 1 means the port is in the reset state. + */ #define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) -#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U) -#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U) -#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK) + #define USBHSH_PORTSC1_LS_MASK (0xC00U) #define USBHSH_PORTSC1_LS_SHIFT (10U) +/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. + */ #define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) + #define USBHSH_PORTSC1_PP_MASK (0x1000U) #define USBHSH_PORTSC1_PP_SHIFT (12U) +/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. + */ #define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) + #define USBHSH_PORTSC1_PIC_MASK (0xC000U) #define USBHSH_PORTSC1_PIC_SHIFT (14U) +/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the + * HCSPARAMS register is logic 0. + */ #define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) + #define USBHSH_PORTSC1_PTC_MASK (0xF0000U) #define USBHSH_PORTSC1_PTC_SHIFT (16U) +/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. + */ #define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) + #define USBHSH_PORTSC1_PSPD_MASK (0x300000U) #define USBHSH_PORTSC1_PSPD_SHIFT (20U) +/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. + */ #define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) + #define USBHSH_PORTSC1_WOO_MASK (0x400000U) #define USBHSH_PORTSC1_WOO_SHIFT (22U) +/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to + * overcurrent conditions as wake-up events. + */ #define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) -#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U) -#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U) -#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK) -#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U) -#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U) -#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK) /*! @} */ -/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */ +/*! @name ATLPTDD - Done map for each ATL PTD */ /*! @{ */ -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U) -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK) + +#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U) +/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK) /*! @} */ -/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */ +/*! @name ATLPTDS - Skip map for each ATL PTD */ /*! @{ */ -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U) -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK) + +#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U) +/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK) /*! @} */ -/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */ +/*! @name ISOPTDD - Done map for each ISO PTD */ /*! @{ */ -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U) -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK) + +#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U) +/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK) /*! @} */ -/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */ +/*! @name ISOPTDS - Skip map for each ISO PTD */ /*! @{ */ -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U) -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK) + +#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U) +/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK) /*! @} */ -/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */ +/*! @name INTPTDD - Done map for each INT PTD */ /*! @{ */ -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U) -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK) + +#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U) +/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK) /*! @} */ -/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */ +/*! @name INTPTDS - Skip map for each INT PTD */ /*! @{ */ -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U) -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK) + +#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U) +/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK) /*! @} */ -/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */ +/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */ /*! @{ */ -#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU) -#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U) -#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK) -#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U) -#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U) -#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK) -/*! @} */ -/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */ -/*! @{ */ -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK) +#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU) +#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U) +/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. + */ +#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK) + +#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U) +#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U) +/*! ISO_LAST - This indicates the last PTD in the ISO list. + */ +#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK) + +#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U) +#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U) +/*! INT_LAST - This indicates the last PTD in the INT list. + */ +#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK) /*! @} */ /*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ /*! @{ */ -#define USBHSH_PORTMODE_ID0_MASK (0x1U) -#define USBHSH_PORTMODE_ID0_SHIFT (0U) -#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK) -#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U) -#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U) -#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK) + #define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) #define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. + */ #define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) + #define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) #define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) +/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. + */ #define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) + #define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) #define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) +/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. + */ #define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) /*! @} */ @@ -23572,7 +28909,7 @@ typedef struct { /* USBHSH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USBHSH base address */ #define USBHSH_BASE (0x500A3000u) /** Peripheral USBHSH base address */ @@ -23635,36 +28972,18 @@ typedef struct { __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ - __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ - uint8_t RESERVED_0[12]; - __IO uint32_t DEBUG0; /**< USB PHY Debug Register 0, offset: 0x50 */ - __IO uint32_t DEBUG0_SET; /**< USB PHY Debug Register 0, offset: 0x54 */ - __IO uint32_t DEBUG0_CLR; /**< USB PHY Debug Register 0, offset: 0x58 */ - __IO uint32_t DEBUG0_TOG; /**< USB PHY Debug Register 0, offset: 0x5C */ - uint8_t RESERVED_1[16]; - __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ - __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ - __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ - __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ - __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ - uint8_t RESERVED_2[28]; + __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[92]; __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ - uint8_t RESERVED_3[16]; + uint8_t RESERVED_1[16]; __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ - __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */ - uint8_t RESERVED_4[12]; - __IO uint32_t USB1_CHRG_DETECT; /**< USB PHY Charger Detect Control Register, offset: 0xE0 */ - __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB PHY Charger Detect Control Register, offset: 0xE4 */ - __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB PHY Charger Detect Control Register, offset: 0xE8 */ - __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB PHY Charger Detect Control Register, offset: 0xEC */ - __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */ - uint8_t RESERVED_5[12]; + uint8_t RESERVED_2[48]; __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ @@ -23682,6 +29001,7 @@ typedef struct { /*! @name PWD - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TXPWDFS_SHIFT (10U) /*! TXPWDFS @@ -23689,6 +29009,7 @@ typedef struct { * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the */ #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) + #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS @@ -23696,6 +29017,7 @@ typedef struct { * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the */ #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) + #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I @@ -23703,6 +29025,7 @@ typedef struct { * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) + #define USBPHY_PWD_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_RXPWDENV_SHIFT (17U) /*! RXPWDENV @@ -23710,6 +29033,7 @@ typedef struct { * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) + #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 @@ -23717,6 +29041,7 @@ typedef struct { * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) + #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF @@ -23724,6 +29049,7 @@ typedef struct { * 0b1..Power-down the USB high-speed differential receive */ #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) + #define USBPHY_PWD_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_RXPWDRX_SHIFT (20U) /*! RXPWDRX @@ -23735,6 +29061,7 @@ typedef struct { /*! @name PWD_SET - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) /*! TXPWDFS @@ -23742,6 +29069,7 @@ typedef struct { * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the */ #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) + #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS @@ -23749,6 +29077,7 @@ typedef struct { * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the */ #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) + #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I @@ -23756,6 +29085,7 @@ typedef struct { * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) + #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) /*! RXPWDENV @@ -23763,6 +29093,7 @@ typedef struct { * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) + #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 @@ -23770,6 +29101,7 @@ typedef struct { * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) + #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF @@ -23777,6 +29109,7 @@ typedef struct { * 0b1..Power-down the USB high-speed differential receive */ #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) + #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) /*! RXPWDRX @@ -23788,6 +29121,7 @@ typedef struct { /*! @name PWD_CLR - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) /*! TXPWDFS @@ -23795,6 +29129,7 @@ typedef struct { * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the */ #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) + #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS @@ -23802,6 +29137,7 @@ typedef struct { * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the */ #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) + #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I @@ -23809,6 +29145,7 @@ typedef struct { * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) + #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) /*! RXPWDENV @@ -23816,6 +29153,7 @@ typedef struct { * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) + #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 @@ -23823,6 +29161,7 @@ typedef struct { * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) + #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF @@ -23830,6 +29169,7 @@ typedef struct { * 0b1..Power-down the USB high-speed differential receive */ #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) + #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) /*! RXPWDRX @@ -23841,6 +29181,7 @@ typedef struct { /*! @name PWD_TOG - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) /*! TXPWDFS @@ -23848,6 +29189,7 @@ typedef struct { * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the */ #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) + #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS @@ -23855,6 +29197,7 @@ typedef struct { * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the */ #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) + #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I @@ -23862,6 +29205,7 @@ typedef struct { * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) + #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) /*! RXPWDENV @@ -23869,6 +29213,7 @@ typedef struct { * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) + #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 @@ -23876,6 +29221,7 @@ typedef struct { * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) + #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF @@ -23883,6 +29229,7 @@ typedef struct { * 0b1..Power-down the USB high-speed differential receive */ #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) + #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) /*! RXPWDRX @@ -23894,6 +29241,7 @@ typedef struct { /*! @name TX - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_D_CAL_MASK (0xFU) #define USBPHY_TX_D_CAL_SHIFT (0U) /*! D_CAL @@ -23902,15 +29250,19 @@ typedef struct { * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) + #define USBPHY_TX_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) + #define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) + #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) + #define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) @@ -23918,6 +29270,7 @@ typedef struct { /*! @name TX_SET - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_SET_D_CAL_MASK (0xFU) #define USBPHY_TX_SET_D_CAL_SHIFT (0U) /*! D_CAL @@ -23926,15 +29279,19 @@ typedef struct { * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) + #define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) + #define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) + #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) + #define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) @@ -23942,6 +29299,7 @@ typedef struct { /*! @name TX_CLR - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_CLR_D_CAL_MASK (0xFU) #define USBPHY_TX_CLR_D_CAL_SHIFT (0U) /*! D_CAL @@ -23950,15 +29308,19 @@ typedef struct { * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) + #define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) + #define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) + #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) + #define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) @@ -23966,6 +29328,7 @@ typedef struct { /*! @name TX_TOG - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_TOG_D_CAL_MASK (0xFU) #define USBPHY_TX_TOG_D_CAL_SHIFT (0U) /*! D_CAL @@ -23974,15 +29337,19 @@ typedef struct { * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) + #define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) + #define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) + #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) + #define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) @@ -23990,6 +29357,7 @@ typedef struct { /*! @name RX - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_ENVADJ_MASK (0x7U) #define USBPHY_RX_ENVADJ_SHIFT (0U) /*! ENVADJ @@ -24003,6 +29371,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) + #define USBPHY_RX_DISCONADJ_MASK (0x70U) #define USBPHY_RX_DISCONADJ_SHIFT (4U) /*! DISCONADJ @@ -24016,6 +29385,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) + #define USBPHY_RX_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS @@ -24027,6 +29397,7 @@ typedef struct { /*! @name RX_SET - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_SET_ENVADJ_MASK (0x7U) #define USBPHY_RX_SET_ENVADJ_SHIFT (0U) /*! ENVADJ @@ -24040,6 +29411,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) + #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) /*! DISCONADJ @@ -24053,6 +29425,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) + #define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS @@ -24064,6 +29437,7 @@ typedef struct { /*! @name RX_CLR - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) /*! ENVADJ @@ -24077,6 +29451,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) + #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) /*! DISCONADJ @@ -24090,6 +29465,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) + #define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS @@ -24101,6 +29477,7 @@ typedef struct { /*! @name RX_TOG - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) /*! ENVADJ @@ -24114,6 +29491,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) + #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) /*! DISCONADJ @@ -24127,6 +29505,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) + #define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS @@ -24138,12 +29517,19 @@ typedef struct { /*! @name CTRL - USB PHY General Control Register */ /*! @{ */ + #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) + #define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET @@ -24151,42 +29537,83 @@ typedef struct { * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) + #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) -#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) -#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) + #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK) + #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) + #define USBPHY_CTRL_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) @@ -24194,12 +29621,19 @@ typedef struct { /*! @name CTRL_SET - USB PHY General Control Register */ /*! @{ */ + #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) + #define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET @@ -24207,39 +29641,83 @@ typedef struct { * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) + #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) + #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK) + #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) + #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) @@ -24247,12 +29725,19 @@ typedef struct { /*! @name CTRL_CLR - USB PHY General Control Register */ /*! @{ */ + #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) + #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET @@ -24260,39 +29745,83 @@ typedef struct { * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) + #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) + #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK) + #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) + #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) @@ -24300,12 +29829,19 @@ typedef struct { /*! @name CTRL_TOG - USB PHY General Control Register */ /*! @{ */ + #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) + #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET @@ -24313,39 +29849,83 @@ typedef struct { * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) + #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) + #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK) + #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) + #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) @@ -24353,6 +29933,11 @@ typedef struct { /*! @name STATUS - USB PHY Status Register */ /*! @{ */ + +#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) +#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) +#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) + #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) /*! HOSTDISCONDETECT_STATUS @@ -24360,6 +29945,7 @@ typedef struct { * 0b1..USB cable disconnect has been detected at the local host */ #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) + #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) /*! DEVPLUGIN_STATUS @@ -24367,268 +29953,27 @@ typedef struct { * 0b1..Cable attachment to a USB host is detected */ #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) -#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) -#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) -#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) + #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) /*! @} */ -/*! @name DEBUG0 - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_SET - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_SET_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_CLR - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_TOG - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG1 - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name VERSION - UTMI RTL Version */ -/*! @{ */ -#define USBPHY_VERSION_STEP_MASK (0xFFFFU) -#define USBPHY_VERSION_STEP_SHIFT (0U) -#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) -#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) -#define USBPHY_VERSION_MINOR_SHIFT (16U) -#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) -#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) -#define USBPHY_VERSION_MAJOR_SHIFT (24U) -#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) -/*! @} */ - /*! @name PLL_SIC - USB PHY PLL Control/Status Register */ /*! @{ */ -#define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) + #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL @@ -24636,12 +29981,15 @@ typedef struct { * 0b1..Selects REFBIAS_PWD to control the reference bias */ #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) #define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL @@ -24655,6 +30003,11 @@ typedef struct { * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK) + #define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK @@ -24666,21 +30019,19 @@ typedef struct { /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ /*! @{ */ -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) + #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL @@ -24688,12 +30039,15 @@ typedef struct { * 0b1..Selects REFBIAS_PWD to control the reference bias */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL @@ -24707,6 +30061,11 @@ typedef struct { * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK) + #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK @@ -24718,21 +30077,19 @@ typedef struct { /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ /*! @{ */ -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL @@ -24740,12 +30097,15 @@ typedef struct { * 0b1..Selects REFBIAS_PWD to control the reference bias */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL @@ -24759,6 +30119,11 @@ typedef struct { * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK @@ -24770,21 +30135,19 @@ typedef struct { /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ /*! @{ */ -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL @@ -24792,12 +30155,15 @@ typedef struct { * 0b1..Selects REFBIAS_PWD to control the reference bias */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL @@ -24811,6 +30177,11 @@ typedef struct { * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK @@ -24822,6 +30193,7 @@ typedef struct { /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH @@ -24835,6 +30207,7 @@ typedef struct { * 0b111..4.7V */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN @@ -24842,18 +30215,23 @@ typedef struct { * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL @@ -24861,6 +30239,7 @@ typedef struct { * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL @@ -24870,6 +30249,31 @@ typedef struct { * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID @@ -24877,13 +30281,19 @@ typedef struct { * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS @@ -24891,17 +30301,11 @@ typedef struct { * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH @@ -24915,6 +30319,7 @@ typedef struct { * 0b111..4.7V */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN @@ -24922,18 +30327,23 @@ typedef struct { * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL @@ -24941,6 +30351,7 @@ typedef struct { * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL @@ -24950,6 +30361,31 @@ typedef struct { * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID @@ -24957,13 +30393,19 @@ typedef struct { * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS @@ -24971,17 +30413,11 @@ typedef struct { * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH @@ -24995,6 +30431,7 @@ typedef struct { * 0b111..4.7V */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN @@ -25002,18 +30439,23 @@ typedef struct { * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL @@ -25021,6 +30463,7 @@ typedef struct { * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL @@ -25030,6 +30473,31 @@ typedef struct { * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID @@ -25037,13 +30505,19 @@ typedef struct { * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS @@ -25051,17 +30525,11 @@ typedef struct { * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH @@ -25075,6 +30543,7 @@ typedef struct { * 0b111..4.7V */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN @@ -25082,18 +30551,23 @@ typedef struct { * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL @@ -25101,6 +30575,7 @@ typedef struct { * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL @@ -25110,6 +30585,31 @@ typedef struct { * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID @@ -25117,13 +30617,19 @@ typedef struct { * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS @@ -25131,151 +30637,19 @@ typedef struct { * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) -/*! SESSEND - * 0b0..The VBUS voltage is above the Session Valid threshold - * 0b1..The VBUS voltage is below the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) -#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) -/*! BVALID - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) -#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) -/*! AVALID - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - * 0b0..VBUS is below the comparator threshold - * 0b1..VBUS is above the comparator threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - * 0b0..VBUS voltage is below VBUS_VALID_3V threshold - * 0b1..VBUS voltage is above VBUS_VALID_3V threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - * 0b0..No USB cable attachment has been detected - * 0b1..A USB cable attachment between the device and host has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - * 0b0..Standard Downstream Port (SDP) has been detected - * 0b1..Charging Port has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) -/*! DM_STATE - * 0b0..USB_DM pin voltage is < 0.8V - * 0b1..USB_DM pin voltage is > 2.0V - */ -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) -/*! DP_STATE - * 0b0..USB_DP pin voltage is < 0.8V - * 0b1..USB_DP pin voltage is > 2.0V - */ -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - * 0b0..Charging Downstream Port (CDP) has been detected - * 0b1..Downstream Charging Port (DCP) has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) /*! @} */ /*! @name ANACTRL - USB PHY Analog Control Register */ /*! @{ */ + +#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) + +#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) + #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN @@ -25287,6 +30661,15 @@ typedef struct { /*! @name ANACTRL_SET - USB PHY Analog Control Register */ /*! @{ */ + +#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) + +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) + #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN @@ -25298,6 +30681,15 @@ typedef struct { /*! @name ANACTRL_CLR - USB PHY Analog Control Register */ /*! @{ */ + +#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) + +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) + #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN @@ -25309,6 +30701,15 @@ typedef struct { /*! @name ANACTRL_TOG - USB PHY Analog Control Register */ /*! @{ */ + +#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) + +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) + #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN @@ -25325,7 +30726,7 @@ typedef struct { /* USBPHY - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USBPHY base address */ #define USBPHY_BASE (0x50038000u) /** Peripheral USBPHY base address */ @@ -25352,6 +30753,8 @@ typedef struct { /** Array initializer of USBPHY peripheral base pointers */ #define USBPHY_BASE_PTRS { USBPHY } #endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_PHY_IRQn } /*! * @} @@ -25387,75 +30790,133 @@ typedef struct { /*! @name CTRL - Control register. */ /*! @{ */ + #define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) #define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer + * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. + */ #define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + #define UTICK_CTRL_REPEAT_MASK (0x80000000U) #define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. + */ #define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) /*! @} */ /*! @name STAT - Status register. */ /*! @{ */ + #define UTICK_STAT_INTR_MASK (0x1U) #define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any + * value to this register clears this flag. + */ #define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + #define UTICK_STAT_ACTIVE_MASK (0x2U) #define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. + */ #define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) /*! @} */ /*! @name CFG - Capture configuration register. */ /*! @{ */ + #define UTICK_CFG_CAPEN0_MASK (0x1U) #define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. + */ #define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + #define UTICK_CFG_CAPEN1_MASK (0x2U) #define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. + */ #define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + #define UTICK_CFG_CAPEN2_MASK (0x4U) #define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. + */ #define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + #define UTICK_CFG_CAPEN3_MASK (0x8U) #define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. + */ #define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + #define UTICK_CFG_CAPPOL0_MASK (0x100U) #define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. + */ #define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + #define UTICK_CFG_CAPPOL1_MASK (0x200U) #define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. + */ #define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + #define UTICK_CFG_CAPPOL2_MASK (0x400U) #define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. + */ #define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + #define UTICK_CFG_CAPPOL3_MASK (0x800U) #define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. + */ #define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) /*! @} */ /*! @name CAPCLR - Capture clear register. */ /*! @{ */ + #define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) #define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. + */ #define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + #define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) #define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. + */ #define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + #define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) #define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. + */ #define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + #define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) #define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. + */ #define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) /*! @} */ /*! @name CAP - Capture register . */ /*! @{ */ + #define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) #define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower + * than the actual value of the Micro-tick Timer at the moment of the capture event. + */ #define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + #define UTICK_CAP_VALID_MASK (0x80000000U) #define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related + * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. + */ #define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) /*! @} */ @@ -25469,7 +30930,7 @@ typedef struct { /* UTICK - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral UTICK0 base address */ #define UTICK0_BASE (0x5000E000u) /** Peripheral UTICK0 base address */ @@ -25535,6 +30996,7 @@ typedef struct { /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ /*! @{ */ + #define WWDT_MOD_WDEN_MASK (0x1U) #define WWDT_MOD_WDEN_SHIFT (0U) /*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the @@ -25543,6 +31005,7 @@ typedef struct { * 0b1..Run. The watchdog timer is running. */ #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + #define WWDT_MOD_WDRESET_MASK (0x2U) #define WWDT_MOD_WDRESET_SHIFT (1U) /*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. @@ -25550,12 +31013,24 @@ typedef struct { * 0b1..Reset. A watchdog time-out will cause a chip reset. */ #define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + #define WWDT_MOD_WDTOF_MASK (0x4U) #define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by + * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a + * chip reset if WDRESET = 1. + */ #define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + #define WWDT_MOD_WDINT_MASK (0x8U) #define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. + * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the + * WARNINT value is equal to the value of the TV register. This can occur if the value of + * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. + */ #define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + #define WWDT_MOD_WDPROTECT_MASK (0x10U) #define WWDT_MOD_WDPROTECT_SHIFT (4U) /*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. @@ -25567,36 +31042,51 @@ typedef struct { /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ /*! @{ */ + #define WWDT_TC_COUNT_MASK (0xFFFFFFU) #define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog time-out value. + */ #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) /*! @} */ /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ /*! @{ */ + #define WWDT_FEED_FEED_MASK (0xFFU) #define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed value should be 0xAA followed by 0x55. + */ #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) /*! @} */ /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ /*! @{ */ + #define WWDT_TV_COUNT_MASK (0xFFFFFFU) #define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter timer value. + */ #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) /*! @} */ /*! @name WARNINT - Watchdog Warning Interrupt compare value. */ /*! @{ */ + #define WWDT_WARNINT_WARNINT_MASK (0x3FFU) #define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog warning interrupt compare value. + */ #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) /*! @} */ /*! @name WINDOW - Watchdog Window compare value. */ /*! @{ */ + #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) #define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog window value. + */ #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) /*! @} */ @@ -25607,7 +31097,7 @@ typedef struct { /* WWDT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral WWDT base address */ #define WWDT_BASE (0x5000C000u) /** Peripheral WWDT base address */ @@ -25714,48 +31204,31 @@ typedef struct { /** High Speed SPI (Flexcomm 8) interrupt name */ #define LSPI_HS_IRQn FLEXCOMM8_IRQn -/** EMC CS base address */ -#define EMC_CS0_BASE (0x80000000u) -#define EMC_CS1_BASE (0x90000000u) -#define EMC_CS2_BASE (0x98000000u) -#define EMC_CS3_BASE (0x9C000000u) -#define EMC_DYCS0_BASE (0xA0000000u) -#define EMC_DYCS1_BASE (0xB0000000u) -#define EMC_DYCS2_BASE (0xC0000000u) -#define EMC_DYCS3_BASE (0xD0000000u) -#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE} -#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE} +/*! + * @brief Get the chip value. + * + * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. + */ +static inline uint32_t Chip_GetVersion(void) +{ + uint32_t deviceRevision; -/** OTP API */ -typedef struct { - uint32_t (*otpInit)(void); /** Initializes OTP controller */ - uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */ - uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */ - uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, - uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */ - uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, - uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */ - uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */ - uint32_t RESERVED_0[5]; - uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */ - uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */ -} OTP_API_Type; + deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK; -/** ROM API */ -typedef struct { - __I uint32_t usbdApiBase; /** USB API Base */ - uint32_t RESERVED_0[13]; - __I OTP_API_Type *otpApiBase; /** OTP API Base */ - __I uint32_t aesApiBase; /** AES API Base */ - __I uint32_t secureApiBase; /** Secure API Base */ -} ROM_API_Type; + if(0UL == deviceRevision) /* A0 device revision is 0 */ + { + return 0x0; + } + else if(1UL == deviceRevision) /* A1 device revision is 1 */ + { + return 0x1; + } + else + { + return 0xFF; + } +} -/** ROM API base address */ -#define ROM_API_BASE (0x03000200u) -/** ROM API base pointer */ -#define ROM_API (*(ROM_API_Type**) ROM_API_BASE) -/** OTP API base pointer */ -#define OTP_API (ROM_API->otpApiBase) /*! * @} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml index 0d7fea3b1d..0353d8f92b 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0.xml @@ -3,9 +3,9 @@ nxp.com LPC55S69_cm33_core0 1.0 - LPC55S69JBD100,LPC55S69JBD64,LPC55S69JET98 + LPC55S69JBD100,LPC55S69JBD64,LPC55S69JEV98 -Copyright 2016-2019 NXP +Copyright 2016-2021 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -37,7 +37,7 @@ SPDX-License-Identifier: BSD-3-Clause HEADER - . + no description available 0 32 read-write @@ -46,7 +46,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -55,7 +55,7 @@ SPDX-License-Identifier: BSD-3-Clause VERSION - . + no description available 0x4 32 read-write @@ -64,7 +64,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -82,7 +82,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -100,7 +100,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -118,7 +118,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -127,7 +127,7 @@ SPDX-License-Identifier: BSD-3-Clause ROTKH_REVOKE - . + no description available 0x18 32 read-write @@ -155,11 +155,18 @@ SPDX-License-Identifier: BSD-3-Clause 2 read-write + + RoTK3_EN + RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 6 + 2 + read-write + VENDOR_USAGE - . + no description available 0x1C 32 read-write @@ -199,12 +206,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -218,12 +225,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -237,12 +244,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -256,12 +263,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -275,31 +282,31 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 - MCM33_DBGEN - Micro CM33 invasive debug enable + CPU1_DBGEN + CPU1 (Micro cortex M33) invasive debug enable 5 1 read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -313,12 +320,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -332,12 +339,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -351,31 +358,31 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 - MCM33_NIDEN - Micro CM33 non-invasive debug enable + CPU1_NIDEN + CPU1 (Micro cortex M33) non-invasive debug enable 9 1 read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -502,8 +509,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_DBGEN - Micro CM33 invasive debug fixed state + CPU1_DBGEN + CPU1 (Micro cortex M33) invasive debug fixed state 5 1 read-write @@ -578,8 +585,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_NIDEN - Micro CM33 non-invasive debug fixed state + CPU1_NIDEN + CPU1 (Micro cortex M33) non-invasive debug fixed state 9 1 read-write @@ -616,7 +623,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -634,7 +641,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -643,7 +650,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE0 - . + no description available PRINCE_REGION0_IV_CODE 0x30 32 @@ -653,7 +660,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -662,7 +669,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_HEADER0 - . + no description available PRINCE_REGION0_IV_CODE 0x30 32 @@ -672,7 +679,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -681,7 +688,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE1 - . + no description available PRINCE_REGION0_IV_CODE 0x34 32 @@ -691,7 +698,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -700,7 +707,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_HEADER1 - . + no description available PRINCE_REGION0_IV_CODE 0x34 32 @@ -710,21 +717,21 @@ SPDX-License-Identifier: BSD-3-Clause TYPE - . + no description available 0 2 read-write INDEX - . + no description available 8 4 read-write SIZE - . + no description available 24 6 read-write @@ -733,7 +740,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY0 - . + no description available PRINCE_REGION0_IV_CODE 0x38 32 @@ -743,7 +750,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -752,7 +759,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE2 - . + no description available PRINCE_REGION0_IV_CODE 0x38 32 @@ -762,7 +769,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -771,7 +778,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY1 - . + no description available PRINCE_REGION0_IV_CODE 0x3C 32 @@ -781,7 +788,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -790,7 +797,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE3 - . + no description available PRINCE_REGION0_IV_CODE 0x3C 32 @@ -800,7 +807,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -809,7 +816,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY2 - . + no description available PRINCE_REGION0_IV_CODE 0x40 32 @@ -819,7 +826,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -828,7 +835,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE4 - . + no description available PRINCE_REGION0_IV_CODE 0x40 32 @@ -838,7 +845,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -847,7 +854,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY3 - . + no description available PRINCE_REGION0_IV_CODE 0x44 32 @@ -857,7 +864,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -866,7 +873,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE5 - . + no description available PRINCE_REGION0_IV_CODE 0x44 32 @@ -876,7 +883,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -885,7 +892,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY4 - . + no description available PRINCE_REGION0_IV_CODE 0x48 32 @@ -895,7 +902,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -904,7 +911,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE6 - . + no description available PRINCE_REGION0_IV_CODE 0x48 32 @@ -914,7 +921,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -923,7 +930,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY5 - . + no description available PRINCE_REGION0_IV_CODE 0x4C 32 @@ -933,7 +940,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -942,7 +949,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE7 - . + no description available PRINCE_REGION0_IV_CODE 0x4C 32 @@ -952,7 +959,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -961,7 +968,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY6 - . + no description available PRINCE_REGION0_IV_CODE 0x50 32 @@ -971,7 +978,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -980,7 +987,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE8 - . + no description available PRINCE_REGION0_IV_CODE 0x50 32 @@ -990,7 +997,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -999,7 +1006,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY7 - . + no description available PRINCE_REGION0_IV_CODE 0x54 32 @@ -1009,7 +1016,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1018,7 +1025,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE9 - . + no description available PRINCE_REGION0_IV_CODE 0x54 32 @@ -1028,7 +1035,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1037,7 +1044,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY8 - . + no description available PRINCE_REGION0_IV_CODE 0x58 32 @@ -1047,7 +1054,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1056,7 +1063,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE10 - . + no description available PRINCE_REGION0_IV_CODE 0x58 32 @@ -1066,7 +1073,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1075,7 +1082,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY9 - . + no description available PRINCE_REGION0_IV_CODE 0x5C 32 @@ -1085,7 +1092,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1094,7 +1101,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE11 - . + no description available PRINCE_REGION0_IV_CODE 0x5C 32 @@ -1104,7 +1111,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1113,7 +1120,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY10 - . + no description available PRINCE_REGION0_IV_CODE 0x60 32 @@ -1123,7 +1130,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1132,7 +1139,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE12 - . + no description available PRINCE_REGION0_IV_CODE 0x60 32 @@ -1142,7 +1149,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1151,7 +1158,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY11 - . + no description available PRINCE_REGION0_IV_CODE 0x64 32 @@ -1161,7 +1168,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1170,7 +1177,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE13 - . + no description available PRINCE_REGION0_IV_CODE 0x64 32 @@ -1180,7 +1187,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1189,7 +1196,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE0 - . + no description available PRINCE_REGION1_IV_CODE 0x68 32 @@ -1199,7 +1206,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1208,7 +1215,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_HEADER0 - . + no description available PRINCE_REGION1_IV_CODE 0x68 32 @@ -1218,7 +1225,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1227,7 +1234,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE1 - . + no description available PRINCE_REGION1_IV_CODE 0x6C 32 @@ -1237,7 +1244,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1246,7 +1253,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_HEADER1 - . + no description available PRINCE_REGION1_IV_CODE 0x6C 32 @@ -1256,21 +1263,21 @@ SPDX-License-Identifier: BSD-3-Clause TYPE - . + no description available 0 2 read-write INDEX - . + no description available 8 4 read-write SIZE - . + no description available 24 6 read-write @@ -1279,7 +1286,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY0 - . + no description available PRINCE_REGION1_IV_CODE 0x70 32 @@ -1289,7 +1296,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1298,7 +1305,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE2 - . + no description available PRINCE_REGION1_IV_CODE 0x70 32 @@ -1308,7 +1315,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1317,7 +1324,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY1 - . + no description available PRINCE_REGION1_IV_CODE 0x74 32 @@ -1327,7 +1334,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1336,7 +1343,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE3 - . + no description available PRINCE_REGION1_IV_CODE 0x74 32 @@ -1346,7 +1353,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1355,7 +1362,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY2 - . + no description available PRINCE_REGION1_IV_CODE 0x78 32 @@ -1365,7 +1372,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1374,7 +1381,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE4 - . + no description available PRINCE_REGION1_IV_CODE 0x78 32 @@ -1384,7 +1391,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1393,7 +1400,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY3 - . + no description available PRINCE_REGION1_IV_CODE 0x7C 32 @@ -1403,7 +1410,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1412,7 +1419,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE5 - . + no description available PRINCE_REGION1_IV_CODE 0x7C 32 @@ -1422,7 +1429,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1431,7 +1438,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY4 - . + no description available PRINCE_REGION1_IV_CODE 0x80 32 @@ -1441,7 +1448,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1450,7 +1457,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE6 - . + no description available PRINCE_REGION1_IV_CODE 0x80 32 @@ -1460,7 +1467,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1469,7 +1476,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY5 - . + no description available PRINCE_REGION1_IV_CODE 0x84 32 @@ -1479,7 +1486,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1488,7 +1495,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE7 - . + no description available PRINCE_REGION1_IV_CODE 0x84 32 @@ -1498,7 +1505,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1507,7 +1514,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY6 - . + no description available PRINCE_REGION1_IV_CODE 0x88 32 @@ -1517,7 +1524,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1526,7 +1533,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE8 - . + no description available PRINCE_REGION1_IV_CODE 0x88 32 @@ -1536,7 +1543,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1545,7 +1552,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY7 - . + no description available PRINCE_REGION1_IV_CODE 0x8C 32 @@ -1555,7 +1562,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1564,7 +1571,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE9 - . + no description available PRINCE_REGION1_IV_CODE 0x8C 32 @@ -1574,7 +1581,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1583,7 +1590,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY8 - . + no description available PRINCE_REGION1_IV_CODE 0x90 32 @@ -1593,7 +1600,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1602,7 +1609,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE10 - . + no description available PRINCE_REGION1_IV_CODE 0x90 32 @@ -1612,7 +1619,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1621,7 +1628,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY9 - . + no description available PRINCE_REGION1_IV_CODE 0x94 32 @@ -1631,7 +1638,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1640,7 +1647,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE11 - . + no description available PRINCE_REGION1_IV_CODE 0x94 32 @@ -1650,7 +1657,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1659,7 +1666,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY10 - . + no description available PRINCE_REGION1_IV_CODE 0x98 32 @@ -1669,7 +1676,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1678,7 +1685,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE12 - . + no description available PRINCE_REGION1_IV_CODE 0x98 32 @@ -1688,7 +1695,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1697,7 +1704,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY11 - . + no description available PRINCE_REGION1_IV_CODE 0x9C 32 @@ -1707,7 +1714,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1716,7 +1723,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE13 - . + no description available PRINCE_REGION1_IV_CODE 0x9C 32 @@ -1726,7 +1733,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1735,7 +1742,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE0 - . + no description available PRINCE_REGION2_IV_CODE 0xA0 32 @@ -1745,7 +1752,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1754,7 +1761,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_HEADER0 - . + no description available PRINCE_REGION2_IV_CODE 0xA0 32 @@ -1764,7 +1771,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1773,7 +1780,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE1 - . + no description available PRINCE_REGION2_IV_CODE 0xA4 32 @@ -1783,7 +1790,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1792,7 +1799,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_HEADER1 - . + no description available PRINCE_REGION2_IV_CODE 0xA4 32 @@ -1802,21 +1809,21 @@ SPDX-License-Identifier: BSD-3-Clause TYPE - . + no description available 0 2 read-write INDEX - . + no description available 8 4 read-write SIZE - . + no description available 24 6 read-write @@ -1825,7 +1832,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY0 - . + no description available PRINCE_REGION2_IV_CODE 0xA8 32 @@ -1835,7 +1842,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1844,7 +1851,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE2 - . + no description available PRINCE_REGION2_IV_CODE 0xA8 32 @@ -1854,7 +1861,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1863,7 +1870,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY1 - . + no description available PRINCE_REGION2_IV_CODE 0xAC 32 @@ -1873,7 +1880,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1882,7 +1889,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE3 - . + no description available PRINCE_REGION2_IV_CODE 0xAC 32 @@ -1892,7 +1899,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1901,7 +1908,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY2 - . + no description available PRINCE_REGION2_IV_CODE 0xB0 32 @@ -1911,7 +1918,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1920,7 +1927,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE4 - . + no description available PRINCE_REGION2_IV_CODE 0xB0 32 @@ -1930,7 +1937,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1939,7 +1946,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY3 - . + no description available PRINCE_REGION2_IV_CODE 0xB4 32 @@ -1949,7 +1956,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1958,7 +1965,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE5 - . + no description available PRINCE_REGION2_IV_CODE 0xB4 32 @@ -1968,7 +1975,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1977,7 +1984,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY4 - . + no description available PRINCE_REGION2_IV_CODE 0xB8 32 @@ -1987,7 +1994,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1996,7 +2003,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE6 - . + no description available PRINCE_REGION2_IV_CODE 0xB8 32 @@ -2006,7 +2013,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2015,7 +2022,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY5 - . + no description available PRINCE_REGION2_IV_CODE 0xBC 32 @@ -2025,7 +2032,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2034,7 +2041,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE7 - . + no description available PRINCE_REGION2_IV_CODE 0xBC 32 @@ -2044,7 +2051,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2053,7 +2060,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY6 - . + no description available PRINCE_REGION2_IV_CODE 0xC0 32 @@ -2063,7 +2070,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2072,7 +2079,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE8 - . + no description available PRINCE_REGION2_IV_CODE 0xC0 32 @@ -2082,7 +2089,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2091,7 +2098,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY7 - . + no description available PRINCE_REGION2_IV_CODE 0xC4 32 @@ -2101,7 +2108,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2110,7 +2117,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE9 - . + no description available PRINCE_REGION2_IV_CODE 0xC4 32 @@ -2120,7 +2127,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2129,7 +2136,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY8 - . + no description available PRINCE_REGION2_IV_CODE 0xC8 32 @@ -2139,7 +2146,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2148,7 +2155,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE10 - . + no description available PRINCE_REGION2_IV_CODE 0xC8 32 @@ -2158,7 +2165,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2167,7 +2174,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY9 - . + no description available PRINCE_REGION2_IV_CODE 0xCC 32 @@ -2177,7 +2184,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2186,7 +2193,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE11 - . + no description available PRINCE_REGION2_IV_CODE 0xCC 32 @@ -2196,7 +2203,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2205,7 +2212,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY10 - . + no description available PRINCE_REGION2_IV_CODE 0xD0 32 @@ -2215,7 +2222,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2224,7 +2231,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE12 - . + no description available PRINCE_REGION2_IV_CODE 0xD0 32 @@ -2234,7 +2241,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2243,7 +2250,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY11 - . + no description available PRINCE_REGION2_IV_CODE 0xD4 32 @@ -2253,7 +2260,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2262,7 +2269,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE13 - . + no description available PRINCE_REGION2_IV_CODE 0xD4 32 @@ -2272,7 +2279,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2292,7 +2299,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2303,7 +2310,7 @@ SPDX-License-Identifier: BSD-3-Clause 8 0x4 SHA256_DIGEST[%s] - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] + SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] 0x1E0 32 read-write @@ -2312,7 +2319,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2356,7 +2363,7 @@ SPDX-License-Identifier: BSD-3-Clause BOOT_CFG - . + no description available 0 32 read-write @@ -2371,27 +2378,32 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + AUTO_ISP Auto ISP 0 - VALUE_1 - USB_HID_MSC + USB_HID_ISP + USB_HID_ISP 0x1 - VALUE_2 - SPI Slave ISP + UART_ISP + UART ISP 0x2 - VALUE_3 - I2C Slave ISP + SPI_ISP + SPI Slave ISP 0x3 - VALUE_7 + I2C_ISP + I2C Slave ISP + 0x4 + + + DISABLE Disable ISP fall through 0x7 @@ -2411,12 +2423,12 @@ SPDX-License-Identifier: BSD-3-Clause VALUE_1 - 48MHz FRO + 96MHz FRO 0x1 VALUE_2 - 96MHz FRO + 48MHz FRO 0x2 @@ -2432,7 +2444,7 @@ SPDX-License-Identifier: BSD-3-Clause SPI_FLASH_CFG - . + no description available 0x4 32 read-write @@ -2440,17 +2452,17 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - FIELD - . + SPI_RECOVERY_BOOT_EN + SPI flash recovery boot is enabled, if non-zero value is written to this field. 0 - 32 + 5 read-write USB_ID - . + no description available 0x8 32 read-write @@ -2459,14 +2471,14 @@ SPDX-License-Identifier: BSD-3-Clause USB_VENDOR_ID - . + no description available 0 16 read-write USB_PRODUCT_ID - . + no description available 16 16 read-write @@ -2475,7 +2487,7 @@ SPDX-License-Identifier: BSD-3-Clause SDIO_CFG - . + no description available 0xC 32 read-write @@ -2484,7 +2496,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2492,8 +2504,8 @@ SPDX-License-Identifier: BSD-3-Clause - DCFG_CC_SOCU_PIN - . + CC_SOCU_PIN + no description available 0x10 32 read-write @@ -2508,12 +2520,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2527,12 +2539,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2546,12 +2558,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2565,12 +2577,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2584,31 +2596,31 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 - MCM33_DBGEN - Micro CM33 invasive debug enable + CPU1_DBGEN + CPU1 (Micro cortex M33) invasive debug enable 5 1 read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2622,12 +2634,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2641,12 +2653,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2660,31 +2672,31 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 - MCM33_NIDEN - Micro CM33 non-invasive debug enable + CPU1_NIDEN + CPU1 (Micro cortex M33) non-invasive debug enable 9 1 read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2707,8 +2719,8 @@ SPDX-License-Identifier: BSD-3-Clause - DCFG_CC_SOCU_DFLT - . + CC_SOCU_DFLT + no description available 0x14 32 read-write @@ -2811,8 +2823,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_DBGEN - Micro CM33 invasive debug fixed state + CPU1_DBGEN + CPU1 (Micro cortex M33) invasive debug fixed state 5 1 read-write @@ -2887,8 +2899,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_NIDEN - Micro CM33 non-invasive debug fixed state + CPU1_NIDEN + CPU1 (Micro cortex M33) non-invasive debug fixed state 9 1 read-write @@ -2915,8 +2927,8 @@ SPDX-License-Identifier: BSD-3-Clause - DAP_VENDOR_USAGE_FIXED - . + VENDOR_USAGE + no description available 0x18 32 read-write @@ -2934,7 +2946,7 @@ SPDX-License-Identifier: BSD-3-Clause SECURE_BOOT_CFG - . + Secure boot configuration flags. 0x1C 32 read-write @@ -2943,65 +2955,248 @@ SPDX-License-Identifier: BSD-3-Clause RSA4K - Use RSA4096 keys only. 00- RSA2048 keys 01, 10, 11 - RSA4096 keys + Use RSA4096 keys only. 0 2 read-write + + + VALUE_0 + Allow RSA2048 and higher + 0 + + + VALUE_1 + RSA4096 only + 0x1 + + + VALUE_2 + RSA4096 only + 0x2 + + + VALUE_3 + RSA4096 only + 0x3 + + - DICE_ENC_NXP_CFG - Include NXP area in DICE computation. 00 - not included 01, 10, 11 - included + DICE_INC_NXP_CFG + Include NXP area in DICE computation. 2 2 read-write + + + NOT_INCLUD + not included + 0 + + + INCLUD + included + 0x1 + + + VALUE_2 + included + 0x2 + + + VALUE_3 + included + 0x3 + + DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 - included + Include Customer factory area (including keys) in DICE computation. 4 2 read-write + + + NOT_INCLUD + not included + 0 + + + UNCLUD + included + 0x1 + + + VALUE_2 + included + 0x2 + + + VALUE_3 + included + 0x3 + + SKIP_DICE - Skip DICE computation. 00 - Enable DICE 01,10,11 - Disable DICE + Skip DICE computation 6 2 read-write + + + ENABLE + Enable DICE + 0 + + + DISABLE + Disable DICE + 0x1 + + + VALUE_2 + Disable DICE + 0x2 + + + VALUE_3 + Disable DICE + 0x3 + + TZM_IMAGE_TYPE - TrustZone-M mode. 00 - TZM mode in image header. 01 - Disable TZ-M. Boots to NonSecure. 10 - TZ-M enable boots to secure mode. 11 - Preset TZM checker from image header. + TrustZone-M mode 8 2 read-write + + + VALUE_0 + TZ-M image mode is taken from application image header + 0 + + + VALUE_1 + TZ-M disabled image, boots to non-secure mode + 0x1 + + + VALUE_2 + TZ-M enabled image, boots to secure mode + 0x2 + + + VALUE_3 + TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header + 0x3 + + BLOCK_SET_KEY - Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code generation + Block PUF key code generation 10 2 read-write + + + ALLOW + Allow PUF Key Code generation + 0 + + + DISABLE + Disable PUF Key Code generation + 0x1 + + + VALUE_2 + Disable PUF Key Code generation + 0x2 + + + VALUE_3 + Disable PUF Key Code generation + 0x3 + + BLOCK_ENROLL - Block PUF enrollement. 00 - Enable enrollment mode 01, 10, 11 - Disable further enrollmnet + Block PUF enrollement 12 2 read-write + + + ALLOW + Allow PUF enroll operation + 0 + + + DISABLE + Disable PUF enroll operation + 0x1 + + + VALUE_2 + Disable PUF enroll operation + 0x2 + + + VALUE_3 + Disable PUF enroll operation + 0x3 + + + + + DICE_INC_SEC_EPOCH + Include security EPOCH in DICE + 14 + 2 + read-write SEC_BOOT_EN - Secure boot enable. 00 - Plain image (internal flash with or without CRC) 01, 10, 11 - Boot signed images. (internal flash, RSA signed) + Secure boot enable 30 2 read-write + + + DISABLE + Plain image (internal flash with or without CRC) + 0 + + + ENABLE + Boot signed images. (internal flash, RSA signed) + 0x1 + + + VALUE_2 + Boot signed images. (internal flash, RSA signed) + 0x2 + + + VALUE_3 + Boot signed images. (internal flash, RSA signed) + 0x3 + + PRINCE_BASE_ADDR - . + no description available 0x20 32 read-write @@ -3010,66 +3205,169 @@ SPDX-License-Identifier: BSD-3-Clause ADDR0_PRG - Programmable portion of the base address of region 0. + Programmable portion of the base address of region 0 0 4 read-write ADDR1_PRG - Programmable portion of the base address of region 1. + Programmable portion of the base address of region 1 4 4 read-write ADDR2_PRG - Programmable portion of the base address of region 2. + Programmable portion of the base address of region 2 8 4 read-write LOCK_REG0 - Lock PRINCE region0 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. - 16 - 2 - read-write - - - LOCK_REG1 - Lock PRINCE region1 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. + Lock PRINCE region0 settings 18 2 read-write + + + UNLOCK + Region is not locked + 0 + + + LOCK + Region is locked + 0x1 + + + VALUE_2 + Region is locked + 0x2 + + + VALUE_3 + Region is locked + 0x3 + + - LOCK_REG2 - Lock PRINCE region2 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. + LOCK_REG1 + Lock PRINCE region1 settings 20 2 read-write + + + UNLOCK + Region is not locked + 0 + + + LOCK + Region is locked + 0x1 + + + VALUE_2 + Region is locked + 0x2 + + + VALUE_3 + Region is locked + 0x3 + + REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + For PRINCE region0 enable checking whether all encrypted pages are erased together 24 2 read-write + + + DISABLE + Region is disabled + 0 + + + ENABLE + Region is enabled + 0x1 + + + VALUE_2 + Region is enabled + 0x2 + + + VALUE_3 + Region is enabled + 0x3 + + REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + For PRINCE region1 enable checking whether all encrypted pages are erased together 26 2 read-write + + + DISABLE + Region is disabled + 0 + + + ENABLE + Region is enabled + 0x1 + + + VALUE_2 + Region is enabled + 0x2 + + + VALUE_3 + Region is enabled + 0x3 + + REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + For PRINCE region2 enable checking whether all encrypted pages are erased together 28 2 read-write + + + DISABLE + Region is disabled + 0 + + + ENABLE + Region is enabled + 0x1 + + + VALUE_2 + Region is enabled + 0x2 + + + VALUE_3 + Region is enabled + 0x3 + + @@ -3084,7 +3382,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -3102,7 +3400,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -3120,18 +3418,120 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write + + XTAL_32KHZ_CAPABANK_TRIM + Xtal 32kHz capabank triming. + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIM_VALID + XTAL 32kHz capa bank trimmings + 0 + 1 + read-write + + + NOT_TRIM + Capa Bank trimmings not valid. Default trimmings value are used + 0 + + + VALID + Capa Bank trimmings valid + 0x1 + + + + + XTAL_LOAD_CAP_IEC_PF_X100 + Load capacitance, pF x 100. For example, 6pF becomes 600. + 1 + 10 + read-write + + + PCB_XIN_PARA_CAP_PF_X100 + PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 11 + 10 + read-write + + + PCB_XOUT_PARA_CAP_PF_X100 + PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 21 + 10 + read-write + + + + + XTAL_16MHZ_CAPABANK_TRIM + Xtal 16MHz capabank triming. + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIM_VALID + XTAL 16MHz capa bank trimmings + 0 + 1 + read-write + + + NOT_TRIM + Capa Bank trimmings not valid. Default trimmings value are used + 0 + + + VALID + Capa Bank trimmings valid + 0x1 + + + + + XTAL_LOAD_CAP_IEC_PF_X100 + Load capacitance, pF x 100. For example, 6pF becomes 600. + 1 + 10 + read-write + + + PCB_XIN_PARA_CAP_PF_X100 + PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 11 + 10 + read-write + + + PCB_XOUT_PARA_CAP_PF_X100 + PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 21 + 10 + read-write + + + 8 0x4 ROTKH[%s] - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] + ROTKHindex for Root of Trust Keys Table hash[(((7 - index) * 32) + 31):((7 - index) * 32)] 0x50 32 read-write @@ -3140,7 +3540,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -3160,7 +3560,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -3171,7 +3571,7 @@ SPDX-License-Identifier: BSD-3-Clause 8 0x4 SHA256_DIGEST[%s] - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] + SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] 0x1E0 32 read-write @@ -3180,7 +3580,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -6595,29 +6995,29 @@ SPDX-License-Identifier: BSD-3-Clause 0x3FFFFFF - PRI_TEAL_CBUS - Teal C-AHB bus. + PRI_CPU0_CBUS + CPU0 C-AHB bus. 0 2 read-write - PRI_TEAL_SBUS - Teal S-AHB bus. + PRI_CPU0_SBUS + CPU0 S-AHB bus. 2 2 read-write - PRI_UTEAL_CBUS - Micro Teal C-AHB bus. + PRI_CPU1_CBUS + CPU1 C-AHB bus. 4 2 read-write - PRI_UTEAL_SBUS - Micro Teal S-AHB bus. + PRI_CPU1_SBUS + CPU1 S-AHB bus. 6 2 read-write @@ -6636,20 +7036,6 @@ SPDX-License-Identifier: BSD-3-Clause 2 read-write - - PRI_EZH_B_D - EZH B data bus. - 12 - 2 - read-write - - - PRI_EZH_B_I - EZH B instruction bus. - 14 - 2 - read-write - PRI_SDIO SDIO. @@ -6659,14 +7045,14 @@ SPDX-License-Identifier: BSD-3-Clause PRI_PQ - PQ (Teal HW Accelerator). + PQ (HW Accelerator). 18 2 read-write - PRI_SHA2 - SHA-2. + PRI_HASH_AES + HASH_AES. 20 2 read-write @@ -6697,8 +7083,8 @@ SPDX-License-Identifier: BSD-3-Clause 0x3FFFFFF - CAL - System tick timer calibration value. + TENMS + Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. 0 24 read-write @@ -6712,7 +7098,7 @@ SPDX-License-Identifier: BSD-3-Clause NOREF - Initial value for the Systick timer. + Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. 25 1 read-write @@ -6729,15 +7115,15 @@ SPDX-License-Identifier: BSD-3-Clause 0x3FFFFFF - CAL - System tick timer calibration value. + TENMS + Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. 0 24 read-write SKEW - Initial value for the Systick timer. + Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. 24 1 read-write @@ -6752,7 +7138,7 @@ SPDX-License-Identifier: BSD-3-Clause - CPU1TCKCAL + CPU1STCKCAL System tick calibration for CPU1 0x40 32 @@ -6761,22 +7147,22 @@ SPDX-License-Identifier: BSD-3-Clause 0x3FFFFFF - CAL - System tick timer calibration value. + TENMS + Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. 0 24 read-write SKEW - Initial value for the Systick timer. + Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. 24 1 read-write NOREF - Initial value for the Systick timer. + Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. 25 1 read-write @@ -6966,8 +7352,8 @@ SPDX-License-Identifier: BSD-3-Clause - MUX0_RST - Input Mux 0 reset control. + MUX_RST + Input Mux reset control. 11 1 read-write @@ -7282,8 +7668,8 @@ SPDX-License-Identifier: BSD-3-Clause - OSTIMER0_RST - OS Timer 0 reset control. + OSTIMER_RST + OS Event Timer reset control. 1 1 read-write @@ -7301,8 +7687,8 @@ SPDX-License-Identifier: BSD-3-Clause - SCT0_RST - SCT0 reset control. + SCT_RST + SCT reset control. 2 1 read-write @@ -7339,8 +7725,8 @@ SPDX-License-Identifier: BSD-3-Clause - UTICK0_RST - UTICK0 reset control. + UTICK_RST + UTICK reset control. 10 1 read-write @@ -7585,63 +7971,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PVT_RST - PVT reset control. - 28 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - EZHA_RST - EZH a reset control. - 30 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - EZHB_RST - EZH b reset control. - 31 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - @@ -7825,63 +8154,6 @@ SPDX-License-Identifier: BSD-3-Clause - - GPIO4_RST - GPIO4 reset control. - 9 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO5_RST - GPIO5 reset control. - 10 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - OTP_RST - OTP reset control. - 12 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - RNG_RST RNG reset control. @@ -7902,9 +8174,9 @@ SPDX-License-Identifier: BSD-3-Clause - MUX1_RST - Peripheral Input Mux 1 reset control. - 14 + SYSCTL_RST + SYSCTL Block reset. + 15 1 read-write @@ -7959,8 +8231,8 @@ SPDX-License-Identifier: BSD-3-Clause - HASH0_RST - HASH0 reset control. + HASH_AES_RST + HASH_AES reset control. 18 1 read-write @@ -8091,25 +8363,6 @@ SPDX-License-Identifier: BSD-3-Clause - - CAPT0_RST - CAPT0 reset control. - 25 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - ANALOG_CTRL_RST analog control reset control. @@ -8231,7 +8484,7 @@ SPDX-License-Identifier: BSD-3-Clause 3 0x4 PRESETCTRLCLR[%s] - Peripheral reset contro clearl register + Peripheral reset control clear register 0x140 32 read-write @@ -8421,8 +8674,8 @@ SPDX-License-Identifier: BSD-3-Clause - MUX0 - Enables the clock for the Input Mux 0. + MUX + Enables the clock for the Input Mux. 11 1 read-write @@ -8737,8 +8990,8 @@ SPDX-License-Identifier: BSD-3-Clause - OSTIMER0 - Enables the clock for the OS Timer 0. + OSTIMER + Enables the clock for the OS Event Timer. 1 1 read-write @@ -8756,8 +9009,8 @@ SPDX-License-Identifier: BSD-3-Clause - SCT0 - Enables the clock for the SCT0. + SCT + Enables the clock for the SCT. 2 1 read-write @@ -8775,27 +9028,8 @@ SPDX-License-Identifier: BSD-3-Clause - SCTIPU - Enables the clock for the SCTIPU. - 6 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - UTICK0 - Enables the clock for the UTICK0. + UTICK + Enables the clock for the UTICK. 10 1 read-write @@ -9040,63 +9274,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PVT - Enables the clock for the PVT. - 28 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - EZHA - Enables the clock for the EZH a. - 30 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - EZHB - Enables the clock for the EZH b. - 31 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - @@ -9280,63 +9457,6 @@ SPDX-License-Identifier: BSD-3-Clause - - GPIO4 - Enables the clock for the GPIO4. - 9 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO5 - Enables the clock for the GPIO5. - 10 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - OTP - Enables the clock for the OTP. - 12 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - RNG Enables the clock for the RNG. @@ -9357,9 +9477,9 @@ SPDX-License-Identifier: BSD-3-Clause - MUX1 - Enables the clock for the Peripheral Input Mux 1. - 14 + SYSCTL + SYSCTL block clock. + 15 1 read-write @@ -9414,8 +9534,8 @@ SPDX-License-Identifier: BSD-3-Clause - HASH0 - Enables the clock for the HASH0. + HASH_AES + Enables the clock for the HASH_AES. 18 1 read-write @@ -9546,25 +9666,6 @@ SPDX-License-Identifier: BSD-3-Clause - - CAPT0 - Enables the clock for the CAPT0. - 25 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - ANALOG_CTRL Enables the clock for the analog control. @@ -10358,26 +10459,6 @@ SPDX-License-Identifier: BSD-3-Clause FRO 96 MHz clock. 0x3 - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - @@ -10418,26 +10499,6 @@ SPDX-License-Identifier: BSD-3-Clause Oscillator 32 kHz clock. 0x3 - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - @@ -10653,11 +10714,6 @@ SPDX-License-Identifier: BSD-3-Clause FRO 96 MHz clock. 0x2 - - ENUM_0x3 - No clock. - 0x3 - ENUM_0x4 No clock. @@ -10742,66 +10798,6 @@ SPDX-License-Identifier: BSD-3-Clause - - USB1CLKSEL - HS USB clock source select - NOT USED - 0x2AC - 32 - read-write - 0x7 - 0x7 - - - SEL - HS USB clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - CLKIN clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - PLL1 clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - FCCLKSEL0 Flexcomm Interface 0 clock source select for Fractional Rate Divider @@ -11528,16 +11524,6 @@ SPDX-License-Identifier: BSD-3-Clause PLL0 clock. 0x1 - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - ENUM_0x4 No clock. @@ -13049,115 +13035,192 @@ SPDX-License-Identifier: BSD-3-Clause FMCCR - FMC configuration register - INTERNAL USE ONLY + FMC configuration register 0x400 32 read-write - 0x3000 + 0x2000 0xFFFFFFFF - FETCHCTL - Fetch control + FETCHCFG + Instruction fetch configuration. 0 2 read-write NOBUF - No buffering (bypass always used) for Fetch cycles + Instruction fetches from flash are not buffered. 0 ONEBUF - One buffer is used for all Fetch cycles + One buffer is used for all instruction fetches. 0x1 ALLBUF - All buffers can be used for Fetch cycles + All buffers may be used for instruction fetches. 0x2 - DATACTL - Data control + DATACFG + Data read configuration. 2 2 read-write NOBUF - No buffering (bypass always used) for Data cycles + Data accesses from flash are not buffered. 0 ONEBUF - One buffer is used for all Data cycles + One buffer is used for all data accesses. 0x1 ALLBUF - All buffers can be used for Data cycles + All buffers can be used for data accesses. 0x2 ACCEL - ACCEL + Acceleration enable. 4 1 read-write + + + DISABLE + Flash acceleration is disabled. + 0 + + + ENABLE + Flash acceleration is enabled. + 0x1 + + PREFEN - Pref enable + Prefetch enable. 5 1 read-write + + + DISABLE + No instruction prefetch is performed. + 0 + + + ENABLE + Instruction prefetch is enabled. + 0x1 + + PREFOVR - Pref ovr + Prefetch override. 6 1 read-write + + + NORMAL + Any previously initiated prefetch will be completed. + 0 + + + OVERRIDE + Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered. + 0x1 + + - PREFCRI - Pref CRI - 8 - 3 - read-write - - - FMCTIM - TMC time + FLASHTIM + Flash memory access time. 12 - 5 - read-write - - - PFISLRU - When set, prefetch uses LRU buffer replacement policy - 17 - 1 - read-write - - - PFADAP - When set, prefetch will adaptively select between parent and LRU buffer replacement policies. - 18 - 1 + 4 read-write + + + FLASHTIM0 + 1 system clock flash access time (for system clock rates up to 11 MHz). + 0 + + + FLASHTIM1 + 2 system clocks flash access time (for system clock rates up to 22 MHz). + 0x1 + + + FLASHTIM2 + 3 system clocks flash access time (for system clock rates up to 33 MHz). + 0x2 + + + FLASHTIM3 + 4 system clocks flash access time (for system clock rates up to 44 MHz). + 0x3 + + + FLASHTIM4 + 5 system clocks flash access time (for system clock rates up to 55 MHz). + 0x4 + + + FLASHTIM5 + 6 system clocks flash access time (for system clock rates up to 66 MHz). + 0x5 + + + FLASHTIM6 + 7 system clocks flash access time (for system clock rates up to 77 MHz). + 0x6 + + + FLASHTIM7 + 8 system clocks flash access time (for system clock rates up to 88 MHz). + 0x7 + + + FLASHTIM8 + 9 system clocks flash access time (for system clock rates up to 100 MHz). + 0x8 + + + FLASHTIM9 + 10 system clocks flash access time (for system clock rates up to 115 MHz). + 0x9 + + + FLASHTIM10 + 11 system clocks flash access time (for system clock rates up to 130 MHz). + 0xA + + + FLASHTIM11 + 12 system clocks flash access time (for system clock rates up to 150 MHz). + 0xB + + - USB0CLKCTRL - USB0 clock control + USB0NEEDCLKCTRL + USB0 need clock control 0x40C 32 read-write @@ -13165,7 +13228,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x1F - AP_FS_DEV_CLK + AP_FS_DEV_NEEDCLK USB0 Device USB0_NEEDCLK signal control:. 0 1 @@ -13184,7 +13247,7 @@ SPDX-License-Identifier: BSD-3-Clause - POL_FS_DEV_CLK + POL_FS_DEV_NEEDCLK USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. 1 1 @@ -13203,7 +13266,7 @@ SPDX-License-Identifier: BSD-3-Clause - AP_FS_HOST_CLK + AP_FS_HOST_NEEDCLK USB0 Host USB0_NEEDCLK signal control:. 2 1 @@ -13222,7 +13285,7 @@ SPDX-License-Identifier: BSD-3-Clause - POL_FS_HOST_CLK + POL_FS_HOST_NEEDCLK USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. 3 1 @@ -13240,30 +13303,11 @@ SPDX-License-Identifier: BSD-3-Clause - - PU_DISABLE - Internal pull-up disable control. - 4 - 1 - read-write - - - ENABLE - Internal pull-up enable. - 0 - - - DISABLE - Internal pull-up disable. - 0x1 - - - - USB0CLKSTAT - USB0 clock status + USB0NEEDCLKSTAT + USB0 need clock status 0x410 32 read-write @@ -13271,7 +13315,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x3 - DEV_NEED_CLKST + DEV_NEEDCLK USB0 Device USB0_NEEDCLK signal status:. 0 1 @@ -13290,7 +13334,7 @@ SPDX-License-Identifier: BSD-3-Clause - HOST_NEED_CLKST + HOST_NEEDCLK USB0 Host USB0_NEEDCLK signal status:. 1 1 @@ -13321,10 +13365,22 @@ SPDX-License-Identifier: BSD-3-Clause FLUSH - no description available + Flush control 0 1 write-only + + + NO_FLUSH + No action is performed. + 0 + + + FLUSH + Flush the FMC buffer contents. + 0x1 + + @@ -13341,7 +13397,7 @@ SPDX-License-Identifier: BSD-3-Clause MCLKIO MCLK control. 0 - 32 + 1 read-write @@ -13359,8 +13415,8 @@ SPDX-License-Identifier: BSD-3-Clause - USB1CLKCTRL - USB1 clock control + USB1NEEDCLKCTRL + USB1 need clock control 0x424 32 read-write @@ -13368,96 +13424,96 @@ SPDX-License-Identifier: BSD-3-Clause 0x1F - AP_HS_DEV_CLK - USB1 Device need_clock signal control:. + AP_HS_DEV_NEEDCLK + USB1 Device need_clock signal control: 0 1 read-write HW_CTRL - Under hardware control. + HOST_NEEDCLK is under hardware control. 0 FORCED - Forced high. + HOST_NEEDCLK is forced high. 0x1 - POL_HS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt:. + POL_HS_DEV_NEEDCLK + USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: 1 1 read-write FALLING - Falling edge of device need_clock triggers wake-up. + Falling edge of DEV_NEEDCLK triggers wake-up. 0 RISING - Rising edge of device need_clock triggers wake-up. + Rising edge of DEV_NEEDCLK triggers wake-up. 0x1 - AP_HS_HOST_CLK - USB1 Host need_clock signal control:. + AP_HS_HOST_NEEDCLK + USB1 Host need clock signal control: 2 1 read-write HW_CTRL - Under hardware control. + HOST_NEEDCLK is under hardware control. 0 FORCED - Forced high. + HOST_NEEDCLK is forced high. 0x1 - POL_HS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt: 0 Falling edge of device need_clock triggers wake-up. + POL_HS_HOST_NEEDCLK + USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. 3 1 read-write FALLING - Falling edge of device need_clock triggers wake-up. + Falling edge of HOST_NEEDCLK triggers wake-up. 0 RISING - Rising edge of device need_clock triggers wake-up. + Rising edge of HOST_NEEDCLK triggers wake-up. 0x1 HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to synchronous control logic:. + Software override of device controller PHY wake up logic. 4 1 read-write FORCE_WUP - Forces USB1 PHY to wake-up. + Forces USB1_PHY to wake-up. 0 NORMAL_WUP - Normal USB1 PHY behavior. + Normal USB1_PHY behavior. 0x1 @@ -13465,8 +13521,8 @@ SPDX-License-Identifier: BSD-3-Clause - USB1CLKSTAT - USB1 clock status + USB1NEEDCLKSTAT + USB1 need clock status 0x428 32 read-write @@ -13474,7 +13530,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x3 - DEV_NEED_CLKST + DEV_NEEDCLK USB1 Device need_clock signal status:. 0 1 @@ -13482,18 +13538,18 @@ SPDX-License-Identifier: BSD-3-Clause LOW - USB1 Device clock is low. + DEV_NEEDCLK is low. 0 HIGH - USB1 Device clock is high. + DEV_NEEDCLK is high. 0x1 - HOST_NEED_CLKST + HOST_NEEDCLK USB1 Host need_clock signal status:. 1 1 @@ -13501,86 +13557,18 @@ SPDX-License-Identifier: BSD-3-Clause LOW - USB1 Host clock is low. + HOST_NEEDCLK is low. 0 HIGH - USB1 Host clock is high. + HOST_NEEDCLK is high. 0x1 - - FLASHBANKENABLE - Flash Banks control - 0x450 - 32 - read-write - 0 - 0xFFF - - - BANK0 - Flash Bank0 control. - 0 - 4 - read-write - - - ENABLE - Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - 0 - - - DISABLE - 1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased and programmed). - 0xA - - - - - BANK1 - Flash Bank1 control. - 4 - 4 - read-write - - - ENABLE - Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - 0 - - - DISABLE - 1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased and programmed). - 0xA - - - - - BANK2 - Flash Bank2 control. - 8 - 4 - read-write - - - ENABLE - Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - 0 - - - DISABLE - 1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased and programmed). - 0xA - - - - - SDIOCLKCTRL SDIO CCLKIN phase and delay control @@ -14415,1795 +14403,45 @@ SPDX-License-Identifier: BSD-3-Clause - EFUSECLKCTRL - eFUSE controller clock enable - 0x5CC + FUNCRETENTIONCTRL + Functional retention control register + 0x704 32 read-write - 0x1 - 0xFFFFFFFF + 0x50C000 + 0xFFFFFF - EFUSECLKENA - eFUSE controller clock enable. - 0 - 1 - read-write - - - - - STARTER0 - Start logic wake-up enable register - 0x680 - 32 - read-write - 0 - 0xF97FFFFF - - - SYS - SYS interrupt wake-up. + FUNCRETENA + functional retention in power down only. 0 1 read-write DISABLE - Wake-up disabled. + disable functional retention. 0 ENABLE - Wake-up enabled. + enable functional retention. 0x1 - SDMA0 - SDMA0 interrupt wake-up. + RET_START + Start address divided by 4 inside SRAMX bank. 1 - 1 + 13 read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - GINT0 - GINT0 interrupt wake-up. - 2 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - GINT1 - GINT1 interrupt wake-up. - 3 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PIO_INT0 - PIO_INT0 interrupt wake-up. - 4 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PIO_INT1 - PIO_INT1 interrupt wake-up. - 5 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PIO_INT2 - PIO_INT2 interrupt wake-up. - 6 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PIO_INT3 - PIO_INT3 interrupt wake-up. - 7 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - UTICK0 - UTICK0 interrupt wake-up. - 8 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - MRT0 - MRT0 interrupt wake-up. - 9 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CTIMER0 - CTIMER0 interrupt wake-up. - 10 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CTIMER1 - CTIMER1 interrupt wake-up. - 11 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SCT0 - SCT0 interrupt wake-up. - 12 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CTIMER3 - CTIMER3 interrupt wake-up. - 13 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT0 - FLEXINT0 interrupt wake-up. + RET_LENTH + lenth of Scan chains to save. 14 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT1 - FLEXINT1 interrupt wake-up. - 15 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT2 - FLEXINT2 interrupt wake-up. - 16 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT3 - FLEXINT3 interrupt wake-up. - 17 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT4 - FLEXINT4 interrupt wake-up. - 18 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT5 - FLEXINT5 interrupt wake-up. - 19 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT6 - FLEXINT6 interrupt wake-up. - 20 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT7 - FLEXINT7 interrupt wake-up. - 21 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - ADC0 - ADC0 interrupt wake-up. - 22 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - ADC0_THCMP_OVR - ADC0_THCMP_OVR interrupt wake-up. - 24 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up. - 27 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - USB0 - USB0 interrupt wake-up. - 28 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - RTC_LITE0 - RTC_LITE0 interrupt wake-up. - 29 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up. - 30 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up. - 31 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - - - STARTER1 - Start logic wake-up enable register - 0x684 - 32 - read-write - 0 - 0xFFFF847F - - - GPIO_INT04 - GPIO_INT04 interrupt wake-up. - 0 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - GPIO_INT05 - GPIO_INT05 interrupt wake-up. - 1 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - GPIO_INT06 - GPIO_INT06 interrupt wake-up. - 2 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - GPIO_INT07 - GPIO_INT07 interrupt wake-up. - 3 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CTIMER2 - CTIMER2 interrupt wake-up. - 4 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CTIMER4 - CTIMER4 interrupt wake-up. - 5 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - OS_EVENT - OS_EVENT interrupt wake-up. - 6 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SDIO - SDIO interrupt wake-up. - 10 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - USB1 - USB1 interrupt wake-up. - 15 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - USB1_NEEDCLK - USB1_NEEDCLK interrupt wake-up. - 16 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up. - 17 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up. - 18 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up. - 19 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PLU - PLU interrupt wake-up. - 20 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SEC_VIO - SEC_VIO interrupt wake-up. - 21 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SHA - SHA interrupt wake-up. - 22 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CASER - CASER interrupt wake-up. - 23 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - QDDKEY - QDDKEY interrupt wake-up. - 24 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PQ - PQ interrupt wake-up. - 25 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SDMA1 - SDMA1 interrupt wake-up. - 26 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - LSPI_HS - LSPI_HS interrupt wake-up. - 27 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - WAKEUPPADS - WAKEUPPADS interrupt wake-up. - 31 - 1 - read-write - - - - - STARTERSET0 - Set bits in STARTER - 0x6A0 - 32 - write-only - 0 - 0xF97FFFFF - - - SYS_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 0 - 1 - write-only - - - SDMA0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 1 - 1 - write-only - - - GPIO_GLOBALINT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 2 - 1 - write-only - - - GPIO_GLOBALINT1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 3 - 1 - write-only - - - GPIO_INT00_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 4 - 1 - write-only - - - GPIO_INT01_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 5 - 1 - write-only - - - GPIO_INT02_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 6 - 1 - write-only - - - GPIO_INT03_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 7 - 1 - write-only - - - UTICK0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 8 - 1 - write-only - - - MRT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 9 - 1 - write-only - - - CTIMER0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 10 - 1 - write-only - - - CTIMER1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 11 - 1 - write-only - - - SCT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 12 - 1 - write-only - - - CTIMER3_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 13 - 1 - write-only - - - FLEXINT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 14 - 1 - write-only - - - FLEXINT1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 15 - 1 - write-only - - - FLEXINT2_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 16 - 1 - write-only - - - FLEXINT3_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 17 - 1 - write-only - - - FLEXINT4_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 18 - 1 - write-only - - - FLEXINT5_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 19 - 1 - write-only - - - FLEXINT6_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 20 - 1 - write-only - - - FLEXINT7_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 21 - 1 - write-only - - - ADC0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 22 - 1 - write-only - - - ADC0_THCMP_OVR_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 24 - 1 - write-only - - - USB0_NEEDCLK_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 27 - 1 - write-only - - - USB0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 28 - 1 - write-only - - - RTC_LITE0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 29 - 1 - write-only - - - EZH_ARCH_B0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 30 - 1 - write-only - - - WAKEUP_MAILBOX0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 31 - 1 - write-only - - - - - STARTERSET1 - Set bits in STARTER - 0x6A4 - 32 - write-only - 0 - 0x8FFF847F - - - GPIO_INT04_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 0 - 1 - write-only - - - GPIO_INT05_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 1 - 1 - write-only - - - GPIO_INT06_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 2 - 1 - write-only - - - GPIO_INT07_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 3 - 1 - write-only - - - CTIMER2_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 4 - 1 - write-only - - - CTIMER4_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 5 - 1 - write-only - - - OS_EVENT_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 6 - 1 - write-only - - - SDIO_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 10 - 1 - write-only - - - USB1_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 15 - 1 - write-only - - - USB1_NEEDCLK_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 16 - 1 - write-only - - - SEC_HYPERVISOR_CALL_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 17 - 1 - write-only - - - SEC_GPIO_INT00_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 18 - 1 - write-only - - - SEC_GPIO_INT01_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 19 - 1 - write-only - - - PLU_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 20 - 1 - write-only - - - SEC_VIO_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 21 - 1 - write-only - - - SHA_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 22 - 1 - write-only - - - CASER_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 23 - 1 - write-only - - - QDDKEY_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 24 - 1 - write-only - - - PQ_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 25 - 1 - write-only - - - SDMA1_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 26 - 1 - write-only - - - LSPI_HS_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 27 - 1 - write-only - - - WAKEUPPADS_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 31 - 1 - write-only - - - - - STARTERCLR0 - Clear bits in STARTER - 0x6C0 - 32 - write-only - 0 - 0xF97FFFFF - - - SYS_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 0 - 1 - write-only - - - SDMA0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 1 - 1 - write-only - - - GPIO_GLOBALINT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 2 - 1 - write-only - - - GPIO_GLOBALINT1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 3 - 1 - write-only - - - GPIO_INT00_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 4 - 1 - write-only - - - GPIO_INT01_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 5 - 1 - write-only - - - GPIO_INT02_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 6 - 1 - write-only - - - GPIO_INT03_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 7 - 1 - write-only - - - UTICK0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 8 - 1 - write-only - - - MRT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 9 - 1 - write-only - - - CTIMER0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 10 - 1 - write-only - - - CTIMER1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 11 - 1 - write-only - - - SCT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 12 - 1 - write-only - - - CTIMER3_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 13 - 1 - write-only - - - FLEXINT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 14 - 1 - write-only - - - FLEXINT1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 15 - 1 - write-only - - - FLEXINT2_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 16 - 1 - write-only - - - FLEXINT3_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 17 - 1 - write-only - - - FLEXINT4_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 18 - 1 - write-only - - - FLEXINT5_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 19 - 1 - write-only - - - FLEXINT6_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 20 - 1 - write-only - - - FLEXINT7_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 21 - 1 - write-only - - - ADC0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 22 - 1 - write-only - - - ADC0_THCMP_OVR_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 24 - 1 - write-only - - - USB0_NEEDCLK_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 27 - 1 - write-only - - - USB0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 28 - 1 - write-only - - - RTC_LITE0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 29 - 1 - write-only - - - EZH_ARCH_B0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 30 - 1 - write-only - - - WAKEUP_MAILBOX0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 31 - 1 - write-only - - - - - STARTERCLR1 - Clear bits in STARTER - 0x6C4 - 32 - write-only - 0 - 0x8FFF847F - - - GPIO_INT04_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 0 - 1 - write-only - - - GPIO_INT05_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 1 - 1 - write-only - - - GPIO_INT06_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 2 - 1 - write-only - - - GPIO_INT07_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 3 - 1 - write-only - - - CTIMER2_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 4 - 1 - write-only - - - CTIMER4_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 5 - 1 - write-only - - - OS_EVENT_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 6 - 1 - write-only - - - SDIO_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 10 - 1 - write-only - - - USB1_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 15 - 1 - write-only - - - USB1_NEEDCLK_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 16 - 1 - write-only - - - SEC_HYPERVISOR_CALL_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 17 - 1 - write-only - - - SEC_GPIO_INT00_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 18 - 1 - write-only - - - SEC_GPIO_INT01_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 19 - 1 - write-only - - - PLU_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 20 - 1 - write-only - - - SEC_VIO_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 21 - 1 - write-only - - - SHA_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 22 - 1 - write-only - - - CASER_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 23 - 1 - write-only - - - QDDKEY_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 24 - 1 - write-only - - - PQ_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 25 - 1 - write-only - - - SDMA1_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 26 - 1 - write-only - - - LSPI_HS_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 27 - 1 - write-only - - - WAKEUPPADS_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 31 - 1 - write-only - - - - - HARDWARESLEEP - Hardware Sleep control - 0x780 - 32 - read-write - 0 - 0x2B - - - FORCED - Force peripheral clocking to stay on during Deep Sleep and Power-down modes. - 0 - 1 - read-write - - - PERIPHERALS - Wake for Flexcomms. - 1 - 1 - read-write - - - SDMA0 - Wake for DMA0. - 3 - 1 - read-write - - - SDMA1 - Wake for DMA1. - 5 - 1 + 10 read-write @@ -16275,24 +14513,6 @@ SPDX-License-Identifier: BSD-3-Clause - - CPSTACK - Coprocessor Stack Address - 0x808 - 32 - read-write - 0 - 0xFFFFFFFF - - - CPSTACK - Coprocessor Stack Address. -- NOT USED - 0 - 32 - read-write - - - CPSTAT CPU Status @@ -16380,150 +14600,6 @@ SPDX-License-Identifier: BSD-3-Clause - - DICE_REG0 - Composite Device Identifier - 0x900 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG0 - no description available - 0 - 32 - read-write - - - - - DICE_REG1 - Composite Device Identifier - 0x904 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG1 - no description available - 0 - 32 - read-write - - - - - DICE_REG2 - Composite Device Identifier - 0x908 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG2 - no description available - 0 - 32 - read-write - - - - - DICE_REG3 - Composite Device Identifier - 0x90C - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG3 - no description available - 0 - 32 - read-write - - - - - DICE_REG4 - Composite Device Identifier - 0x910 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG4 - no description available - 0 - 32 - read-write - - - - - DICE_REG5 - Composite Device Identifier - 0x914 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG5 - no description available - 0 - 32 - read-write - - - - - DICE_REG6 - Composite Device Identifier - 0x918 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG6 - no description available - 0 - 32 - read-write - - - - - DICE_REG7 - Composite Device Identifier - 0x91C - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG7 - no description available - 0 - 32 - read-write - - - CLOCK_CTRL Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures @@ -16531,27 +14607,8 @@ SPDX-License-Identifier: BSD-3-Clause 32 read-write 0x1 - 0x7F + 0x3FF - - FLASH48MHZ_ENA - Enable Flash 48 MHz clock. - 0 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - XTAL32MHZ_FREQM_ENA Enable XTAL32MHz clock for Frequency Measure module. @@ -17090,44 +15147,6 @@ SPDX-License-Identifier: BSD-3-Clause - - FLASH - Control automatic clock gating of FLASH controller. - 9 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - FMC - Control automatic clock gating of FMC controller. - 10 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - CRCGEN Control automatic clock gating of CRCGEN controller. @@ -17186,7 +15205,7 @@ SPDX-License-Identifier: BSD-3-Clause - USB + USB0 Control automatic clock gating of USB controller. 14 1 @@ -17232,12 +15251,12 @@ SPDX-License-Identifier: BSD-3-Clause DISABLE - Automatic clock gating is not overridden. + Bit Fields 0 - 15 of this register are not updated 0 ENABLE - Automatic clock gating is overridden (Clock gating is disabled). + Bit Fields 0 - 15 of this register are updated 0xC0DE @@ -17276,7 +15295,7 @@ SPDX-License-Identifier: BSD-3-Clause DEBUG_LOCK_EN - Control write access to security registers -- FOR INTERNAl USE ONLY + Control write access to security registers. 0xFA0 32 read-write @@ -17285,7 +15304,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CM33_DEBUG_FEATURES, MCM33_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. 0 4 read-write @@ -17306,7 +15325,7 @@ SPDX-License-Identifier: BSD-3-Clause DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY + Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. 0xFA4 32 read-write @@ -17314,8 +15333,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFF - CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + CPU0_DBGEN + CPU0 Invasive debug control:. 0 2 read-write @@ -17333,8 +15352,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. + CPU0_NIDEN + CPU0 Non Invasive debug control:. 2 2 read-write @@ -17352,8 +15371,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. + CPU0_SPIDEN + CPU0 Secure Invasive debug control:. 4 2 read-write @@ -17371,8 +15390,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. + CPU0_SPNIDEN + CPU0 Secure Non Invasive debug control:. 6 2 read-write @@ -17390,8 +15409,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. + CPU1_DBGEN + CPU1 Invasive debug control:. 8 2 read-write @@ -17409,8 +15428,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. + CPU1_NIDEN + CPU1 Non Invasive debug control:. 10 2 read-write @@ -17431,7 +15450,7 @@ SPDX-License-Identifier: BSD-3-Clause DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY + Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. 0xFA8 32 read-write @@ -17439,8 +15458,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFF - CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + CPU0_DBGEN + CPU0 (CPU0) Invasive debug control:. 0 2 read-write @@ -17458,8 +15477,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. + CPU0_NIDEN + CPU0 Non Invasive debug control:. 2 2 read-write @@ -17477,8 +15496,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. + CPU0_SPIDEN + CPU0 Secure Invasive debug control:. 4 2 read-write @@ -17496,8 +15515,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. + CPU0_SPNIDEN + CPU0 Secure Non Invasive debug control:. 6 2 read-write @@ -17515,8 +15534,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. + CPU1_DBGEN + CPU1 Invasive debug control:. 8 2 read-write @@ -17534,8 +15553,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. + CPU1_NIDEN + CPU1 Non Invasive debug control:. 10 2 read-write @@ -17554,99 +15573,9 @@ SPDX-License-Identifier: BSD-3-Clause - - CODESECURITYPROTTEST - Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY - 0xFB0 - 32 - write-only - 0 - 0xFFFFFFFF - - - SEC_CODE - Security code to allow test access : 0x12345678. - 0 - 32 - write-only - - - DISABLE - test access is not allowed. - 0 - - - ENABLE - Security code to allow test access. - 0x12345678 - - - - - - - CODESECURITYPROTCPU0 - Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY - 0xFB4 - 32 - write-only - 0 - 0xFFFFFFFF - - - SEC_CODE - Security code to allow CPU0 DAP: 0x12345678. - 0 - 32 - write-only - - - DISABLE - CPU0 DAP is not allowed. - 0 - - - ENABLE - Security code to allow CPU0 DAP. - 0x12345678 - - - - - - - CODESECURITYPROTCPU1 - Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY - 0xFB8 - 32 - write-only - 0 - 0xFFFFFFFF - - - SEC_CODE - Security code to allow CPU1 DAP: 0x12345678. - 0 - 32 - write-only - - - DISABLE - CPU1 DAP is not allowed. - 0 - - - ENABLE - Security code to allow CPU1 DAP. - 0x12345678 - - - - - KEY_BLOCK - block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY + block quiddikey/PUF all index. 0xFBC 32 write-only @@ -17663,8 +15592,8 @@ SPDX-License-Identifier: BSD-3-Clause - DEBUG_AUTH_SCRATCH - Debug authentication scratch registers -- FOR INTERNAL USE ONLY + DEBUG_AUTH_BEACON + Debug authentication BEACON register 0xFC0 32 read-write @@ -17672,7 +15601,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - SCRATCH + BEACON Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code. 0 32 @@ -17710,169 +15639,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PERIPHENCFG - peripheral enable configuration -- FOR INTERNAL USE ONLY - 0xFEC - 32 - read-write - 0x5C47 - 0x5C47 - - - SCTEN - SCT enable. - 0 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - ADCEN - ADC enable. - 1 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - USB0EN - USB0 enable. - 2 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - PUFFEN - Puff enable. - 6 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - USB1EN - USB1 enable. - 10 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - SDIOEN - SDIO enable. - 11 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - HASHEN - HASH enable. - 12 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - PRINCEEN - PRINCE enable. - 14 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - DEVICE_ID0 Device ID @@ -17882,41 +15648,13 @@ SPDX-License-Identifier: BSD-3-Clause 0 0xFFFFFFFF - - PARTCONFIG - no description available - 0 - 8 - read-only - - - SRAM_SIZE - no description available - 8 - 4 - read-only - - - FLASH_SIZE - no description available - 12 - 3 - read-only - ROM_REV_MINOR - no description available + ROM revision. 20 4 read-only - - MODELNUM_EXTENTION - no description available - 24 - 3 - read-only - @@ -17937,7 +15675,7 @@ SPDX-License-Identifier: BSD-3-Clause MCO_NUM_IN_DIE_ID - Chip Number. + Chip Number 0x426B. 4 20 read-only @@ -18053,12 +15791,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18091,12 +15829,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -18122,19 +15860,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -18237,12 +15975,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18275,12 +16013,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -18402,12 +16140,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18440,12 +16178,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -18567,12 +16305,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18605,12 +16343,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -18732,12 +16470,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18770,12 +16508,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -18897,12 +16635,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18935,12 +16673,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19062,12 +16800,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19100,12 +16838,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19227,12 +16965,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19265,12 +17003,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19392,12 +17130,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19430,12 +17168,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19557,12 +17295,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19595,12 +17333,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19626,19 +17364,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -19741,12 +17479,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19779,12 +17517,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19810,19 +17548,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -19925,12 +17663,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19963,12 +17701,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19994,19 +17732,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -20109,12 +17847,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -20147,12 +17885,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -20178,19 +17916,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -20293,12 +18031,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -20331,19 +18069,19 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 OD - Controls open-drain mode. + Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). 9 1 read-write @@ -20388,26 +18126,26 @@ SPDX-License-Identifier: BSD-3-Clause ENABLED - Filter enabled. Noise pulses below approximately 10 ns are filtered out. + Filter enabled. 0 DISABLED - Filter disabled. No input filtering is done. + Filter disabled. 0x1 ECS - Pull-up current source enable in IIC mode. + Pull-up current source enable in I2C mode. 13 1 read-write DISABLED - Disabled. IO is in open drain. + Disabled. IO is in open drain cell. 0 @@ -20419,7 +18157,7 @@ SPDX-License-Identifier: BSD-3-Clause EGP - Controls slew rate of I2C pad. + Switch between GPIO mode and I2C mode. 14 1 read-write @@ -20438,19 +18176,19 @@ SPDX-License-Identifier: BSD-3-Clause I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. + Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. 15 1 read-write FAST_MODE - I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. + I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. 0 STANDARD_MODE - I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. + I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. 0x1 @@ -20553,12 +18291,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -20591,19 +18329,19 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 OD - Controls open-drain mode. + Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). 9 1 read-write @@ -20648,26 +18386,26 @@ SPDX-License-Identifier: BSD-3-Clause ENABLED - Filter enabled. Noise pulses below approximately 10 ns are filtered out. + Filter enabled. 0 DISABLED - Filter disabled. No input filtering is done. + Filter disabled. 0x1 ECS - Pull-up current source enable in IIC mode. + Pull-up current source enable in I2C mode. 13 1 read-write DISABLED - Disabled. IO is in open drain. + Disabled. IO is in open drain cell. 0 @@ -20679,7 +18417,7 @@ SPDX-License-Identifier: BSD-3-Clause EGP - Controls slew rate of I2C pad. + Switch between GPIO mode and I2C mode. 14 1 read-write @@ -20698,19 +18436,19 @@ SPDX-License-Identifier: BSD-3-Clause I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. + Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. 15 1 read-write FAST_MODE - I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. + I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. 0 STANDARD_MODE - I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. + I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. 0x1 @@ -20813,12 +18551,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -20851,12 +18589,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -20882,19 +18620,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -20997,12 +18735,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21035,12 +18773,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -21066,19 +18804,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -21181,12 +18919,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21219,12 +18957,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -21346,12 +19084,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21384,12 +19122,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -21415,19 +19153,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -21530,12 +19268,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21568,12 +19306,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -21695,12 +19433,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21733,12 +19471,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -21860,12 +19598,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21898,12 +19636,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22025,12 +19763,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22063,12 +19801,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22190,12 +19928,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22228,12 +19966,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22259,19 +19997,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -22374,12 +20112,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22412,12 +20150,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22539,12 +20277,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22577,12 +20315,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22704,12 +20442,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22742,12 +20480,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22869,12 +20607,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22907,12 +20645,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23034,12 +20772,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23072,12 +20810,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23199,12 +20937,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23237,12 +20975,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23364,12 +21102,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23402,12 +21140,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23529,12 +21267,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23567,12 +21305,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23598,19 +21336,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -23713,12 +21451,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23751,12 +21489,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23782,19 +21520,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -23897,12 +21635,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23935,12 +21673,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24062,12 +21800,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24100,12 +21838,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24227,12 +21965,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24265,12 +22003,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24392,12 +22130,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24430,12 +22168,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24557,12 +22295,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24595,12 +22333,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24722,12 +22460,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24760,12 +22498,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24887,12 +22625,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24925,12 +22663,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25052,12 +22790,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25090,12 +22828,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25121,19 +22859,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -25236,12 +22974,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25274,12 +23012,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25305,19 +23043,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -25420,12 +23158,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25458,12 +23196,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25585,12 +23323,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25623,12 +23361,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25750,12 +23488,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25788,12 +23526,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25915,12 +23653,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25953,12 +23691,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26080,12 +23818,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26118,12 +23856,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26149,19 +23887,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -26264,12 +24002,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26302,12 +24040,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26429,12 +24167,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26467,12 +24205,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26594,12 +24332,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26632,12 +24370,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26759,12 +24497,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26797,12 +24535,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26924,12 +24662,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26962,12 +24700,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26993,19 +24731,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -27108,12 +24846,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27146,12 +24884,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -27273,12 +25011,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27311,12 +25049,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -27438,12 +25176,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27476,12 +25214,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -27603,12 +25341,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27641,12 +25379,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -27768,12 +25506,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27806,12 +25544,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -27933,12 +25671,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27971,12 +25709,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28098,12 +25836,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28136,12 +25874,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28263,12 +26001,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28301,12 +26039,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28428,12 +26166,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28466,12 +26204,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28593,12 +26331,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28631,12 +26369,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28758,12 +26496,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28796,12 +26534,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28923,12 +26661,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28961,12 +26699,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -30366,6 +28104,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x34 registers + + SEC_HYPERVISOR_CALL + 49 + SEC_GPIO_INT0_IRQ0 50 @@ -30374,6 +28116,10 @@ SPDX-License-Identifier: BSD-3-Clause SEC_GPIO_INT0_IRQ1 51 + + SEC_VIO + 53 + INPUTMUX @@ -30673,17 +28419,17 @@ SPDX-License-Identifier: BSD-3-Clause val17 - CT_INP17 function selected from IOCON register + None 0x11 val18 - CT_INP18 function selected from IOCON register + None 0x12 val19 - CT_INP19 function selected from IOCON register + None 0x13 @@ -30855,17 +28601,17 @@ SPDX-License-Identifier: BSD-3-Clause val17 - CT_INP17 function selected from IOCON register + None 0x11 val18 - CT_INP18 function selected from IOCON register + None 0x12 val19 - CT_INP19 function selected from IOCON register + None 0x13 @@ -31037,17 +28783,17 @@ SPDX-License-Identifier: BSD-3-Clause val17 - CT_INP17 function selected from IOCON register + None 0x11 val18 - CT_INP18 function selected from IOCON register + None 0x12 val19 - CT_INP19 function selected from IOCON register + None 0x13 @@ -31347,10 +29093,52 @@ SPDX-License-Identifier: BSD-3-Clause CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 + Clock source number (decimal value) for frequency measure function reference clock: 0 5 read-write + + + VALUE0 + External main crystal oscilator (Clock_in). + 0 + + + VALUE1 + FRO 12MHz clock. + 0x1 + + + VALUE2 + FRO 96MHz clock. + 0x2 + + + VALUE3 + Watchdog oscillator / FRO1MHz clock. + 0x3 + + + VALUE4 + 32 kHz oscillator (32k_clk) clock. + 0x4 + + + VALUE5 + main clock (main_clock). + 0x5 + + + VALUE6 + FREQME_GPIO_CLK_A. + 0x6 + + + VALUE7 + FREQME_GPIO_CLK_B. + 0x7 + + @@ -31365,10 +29153,52 @@ SPDX-License-Identifier: BSD-3-Clause CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 + Clock source number (decimal value) for frequency measure function target clock: 0 5 read-write + + + VALUE0 + External main crystal oscilator (Clock_in). + 0 + + + VALUE1 + FRO 12MHz clock. + 0x1 + + + VALUE2 + FRO 96MHz clock. + 0x2 + + + VALUE3 + Watchdog oscillator / FRO1MHz clock. + 0x3 + + + VALUE4 + 32 kHz oscillator (32k_clk) clock. + 0x4 + + + VALUE5 + main clock (main_clock). + 0x5 + + + VALUE6 + FREQME_GPIO_CLK_A. + 0x6 + + + VALUE7 + FREQME_GPIO_CLK_B. + 0x7 + + @@ -32909,7 +30739,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - SHADOWW + SHADOW Timer counter match shadow value. 0 32 @@ -33689,7 +31519,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x40013000 0 - 0x10C + 0x108 registers @@ -33732,20 +31562,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x50000000 0xF0003FFF - - PMU_ID - Power Management Unit (PMU) Analog macro-bloc identification number : . - 0 - 6 - read-only - - - OSC_ID - Oscillators Analog macro-bloc identification number : . - 6 - 6 - read-only - FLASH_PWRDWN Flash Power Down status. @@ -33784,13 +31600,6 @@ SPDX-License-Identifier: BSD-3-Clause - - FINAL_TEST_DONE_VECT - Indicates current status of Final Test. - 28 - 4 - read-only - @@ -33827,20 +31636,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x80D01A 0xF3FFFFBF - - BIAS_TRIM - Bias trimming bits (course frequency trimming). - 0 - 6 - read-write - - - TEMP_TRIM - Temperature coefficient trimming bits. - 7 - 7 - read-write - ENA_12MHZCLK 12 MHz clock control. @@ -33867,11 +31662,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - DISABLE - 48 MHz clock is disabled. - 0 - ENABLE 48 MHz clock is enabled. @@ -33881,7 +31671,7 @@ SPDX-License-Identifier: BSD-3-Clause DAC_TRIM - Curdac trimming bits (fine frequency trimming) This trim is used to adjust the frequency, given that the bias and temperature trim are set. + Frequency trim. 16 8 read-write @@ -33895,18 +31685,11 @@ SPDX-License-Identifier: BSD-3-Clause USBMODCHG - If this reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be reread until it is 0. + If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. 25 1 read-only - - ATB_CTRL - Analog Test Bus control. - 28 - 2 - read-write - ENA_96MHZCLK 96 MHz clock control. @@ -34004,20 +31787,13 @@ SPDX-License-Identifier: BSD-3-Clause XO32M_CTRL - 32 MHz Crystal Oscillator Control register + High speed Crystal Oscillator Control register 0x20 32 read-write 0x21428A 0x1FFFFFFE - - GM - Gm value for Xo. - 1 - 3 - read-write - SLAVE Xo in slave mode. @@ -34025,23 +31801,16 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - AMP - Amplitude selection , Min amp : 001, Max amp : 110. - 5 - 3 - read-write - OSC_CAP_IN - Tune capa banks of Crystal 32-MHz input pin + Tune capa banks of High speed Crystal Oscillator input pin 8 7 read-write OSC_CAP_OUT - Tune capa banks of Crystal 32-MHz output pin + Tune capa banks of High speed Crystal Oscillator output pin 15 7 read-write @@ -34067,102 +31836,38 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_PLL_USB_OUT - Enable XO 32 MHz output to USB HS PLL. + Enable High speed Crystal oscillator output to USB HS PLL. 23 1 read-write DISABLE - XO 32 MHz output to USB HS PLL is disabled. + High speed Crystal oscillator output to USB HS PLL is disabled. 0 ENABLE - XO 32 MHz output to USB HS PLL is enabled. + High speed Crystal oscillator output to USB HS PLL is enabled. 0x1 ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system. + Enable High speed Crystal oscillator output to CPU system. 24 1 read-write DISABLE - XO 32 MHz output to CPU system is disabled. + High speed Crystal oscillator output to CPU system is disabled. 0 ENABLE - XO 32 MHz output to CPU system is enabled. - 0x1 - - - - - CAPTESTSTARTSRCSEL - Source selection for 'xo32k_captest_start' signal. - 25 - 1 - read-write - - - CAPTEST - Sourced from CAPTESTSTART. - 0 - - - CALIB - Sourced from calibration. - 0x1 - - - - - CAPTESTSTART - 1: Start CapTest. - 26 - 1 - read-write - - - CAPTESTENABLE - Enable signal for captest. - 27 - 1 - read-write - - - DISABLE - Captest is disabled. - 0 - - - ENABLE - Captest is enabled. - 0x1 - - - - - CAPTESTOSCINSEL - Select the input for test. - 28 - 1 - read-write - - - OSCOUT - osc_out (oscillator output) pin. - 0 - - - OSCIN - osc_in (oscillator) pin. + High speed Crystal oscillator output to CPU system is enabled. 0x1 @@ -34171,7 +31876,7 @@ SPDX-License-Identifier: BSD-3-Clause XO32M_STATUS - 32 MHz Crystal Oscillator Status register + High speed Crystal Oscillator Status register 0x24 32 read-only @@ -35238,124 +32943,74 @@ SPDX-License-Identifier: BSD-3-Clause - XO_CAL_CFG - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register - 0xC0 + AUX_BIAS + AUX_BIAS + 0xB4 32 read-write - 0 - 0x3F + 0x703A0 + 0x3FFFFE - START_INV - Polarity of the externally applied START signal - 0 - 1 - read-write - - - START_OVR - Override of the START signal. + VREF1VENABLE + Control output of 1V reference voltage. 1 1 read-write - - - START - Override value of the START signal. - 2 - 1 - read-write - - - STOP_INV - Polarity of the STOP signal. - 3 - 1 - read-write - - - STOP_CNTR_END - Generate the external DONE signal when the counter reaches its end. - 4 - 1 - read-write - - - XO32K_MODE - When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal oscillator calibration is used. - 5 - 1 - read-write - XO32MHZ - High speed crystal oscillator (12 MHz- 32 MHz) is used + DISABLE + Output of 1V reference voltage buffer is bypassed. 0 - XO32KHZ - 32 kHz crystal oscillator calibration is used. + ENABLE + Output of 1V reference voltage is enabled. 0x1 - - - - XO_CAL_CMD - All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register. - 0xC4 - 32 - read-write - 0 - 0x7 - - START - START signal for testing the state machine. - 0 - 1 - read-write - - - STOP - STOP signal for testing the state machine. - 1 - 1 - read-write - - - OVR - Override instructing the state machine to use the START/STOP signals from this register. + ITRIM + current trimming control word. 2 + 5 + read-write + + + PTATITRIM + current trimming control word for ptat current. + 7 + 5 + read-write + + + VREF1VTRIM + voltage trimming control word. + 12 + 5 + read-write + + + VREF1VCURVETRIM + Control bit to configure trimming state of mirror. + 17 + 3 + read-write + + + ITRIMCTRL0 + Control bit to configure trimming state of mirror. + 20 1 read-write - - - - XO_CAL_STATUS - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register. - 0xC8 - 32 - read-only - 0 - 0x1FFFF - - CAL_CNTR - Value of the calibration counter (result of the calibration operation). - 0 - 16 - read-only - - - DONE - Status of the calibration run. 1: Calibration is completed. - 16 + ITRIMCTRL1 + Control bit to configure trimming state of mirror. + 21 1 - read-only + read-write @@ -35382,13 +33037,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - iso_atx - . - 3 - 1 - read-write - @@ -35451,66 +33099,6 @@ SPDX-License-Identifier: BSD-3-Clause - - USBHS_PHY_STATUS - USB High Speed Phy Status - 0x108 - 32 - read-only - 0 - 0x7F - - - pfd_stable - pfd output is stable. - 0 - 1 - read-only - - - vbusvalid_3vdetect_1p8v - Can be left disconnected if not using High volt interrupts. - 1 - 1 - read-only - - - sess_vld_1p8v - Same as utmi_sessend. - 2 - 1 - read-only - - - usb2_rx_vpin_fs_1p8v - Full speed single ended receiver for 1. - 3 - 1 - read-only - - - usb2_rx_vmin_fs_1p8v - Full speed single ended receiver for 1. - 4 - 1 - read-only - - - usb2_plugged_in_1p8v - this is a proprietary mode described in the reference manual. - 5 - 1 - read-only - - - usb2_iddig_1p8v - ID value in the 1. - 6 - 1 - read-only - - - @@ -35520,10 +33108,54 @@ SPDX-License-Identifier: BSD-3-Clause 0x40020000 0 - 0xCC + 0xD8 registers + + ACMP + 24 + + + STATUS + Power Management Controller FSM (Finite State Machines) status + 0x4 + 32 + read-only + 0 + 0xF00FFFFF + + + BOOTMODE + Latest IC Boot cause:. + 18 + 2 + read-only + + + POWERUP + Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). + 0 + + + DEEPSLEEP + Latest IC boot was from DEEP SLEEP low power mode. + 0x1 + + + POWERDOWN + Latest IC boot was from POWER DOWN low power mode. + 0x2 + + + DEEPPOWERDOWN + Latest IC boot was from DEEP POWER DOWN low power mode. + 0x3 + + + + + RESETCTRL Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] @@ -35612,78 +33244,482 @@ SPDX-License-Identifier: BSD-3-Clause - RESETCAUSE - Reset Cause register [Reset by: PoR] - 0xC + DCDC0 + DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x10 32 read-write - 0x1 - 0x1FF + 0x10C4E68 + 0x7FFFFFF - POR - 1 : The last chip reset was caused by a Power On Reset. Write '1' to clear this bit. + RC + Constant On-Time calibration. 0 - 1 - read-write - oneToClear - - - PADRESET - 1 : The last chip reset was caused by a Pin Reset. Write '1' to clear this bit. - 1 - 1 + 6 read-write - BODRESET - 1 : The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. Write '1' to clear this bit. - 2 - 1 - read-write - - - SYSTEMRESET - 1 : The last chip reset was caused by a System Reset requested by the ARM CPU. Write '1' to clear this bit. - 3 - 1 - read-write - - - WDTRESET - 1 : The last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit. - 4 - 1 - read-write - - - SWRRESET - 1 : The last chip reset was caused by a Software. Write '1' to clear this bit. - 5 - 1 - read-write - - - DPDRESET_WAKEUPIO - 1 : The last chip reset was caused by a Wake-up I/O reset event during DEEP POWER DOWN mode. Write '1' to clear this bit. + ICOMP + Select the type of ZCD comparator. 6 + 2 + read-write + + + ISEL + Alter Internal biasing currents. + 8 + 2 + read-write + + + ICENABLE + Selection of auto scaling of COT period with variations in VDD. + 10 1 read-write - DPDRESET_RTC - 1 : The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during DEEP POWER DOWN mode. Write '1' to clear this bit. - 7 + TMOS + One-shot generator reference current trimming signal. + 11 + 5 + read-write + + + DISABLEISENSE + Disable Current sensing. + 16 1 read-write - DPDRESET_OSTIMER - 1 : The last chip reset was caused by a OS Event Timer reset eventduring DEEP POWER DOWN mode. Write '1' to clear this bit. + VOUT + Set output regulation voltage. + 17 + 4 + read-write + + + V_DCDC_0P950 + 0.95 V. + 0 + + + V_DCDC_0P975 + 0.975 V. + 0x1 + + + V_DCDC_1P000 + 1 V. + 0x2 + + + V_DCDC_1P025 + 1.025 V. + 0x3 + + + V_DCDC_1P050 + 1.05 V. + 0x4 + + + V_DCDC_1P075 + 1.075 V. + 0x5 + + + V_DCDC_1P100 + 1.1 V. + 0x6 + + + V_DCDC_1P125 + 1.125 V. + 0x7 + + + V_DCDC_1P150 + 1.15 V. + 0x8 + + + V_DCDC_1P175 + 1.175 V. + 0x9 + + + V_DCDC_1P200 + 1.2 V. + 0xA + + + + + SLICINGENABLE + Enable staggered switching of power switches. + 21 + 1 + read-write + + + INDUCTORCLAMPENABLE + Enable shorting of Inductor during PFM idle time. + 22 + 1 + read-write + + + VOUT_PWD + Set output regulation voltage during Deep Sleep. + 23 + 4 + read-write + + + + + DCDC1 + DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x14 + 32 + read-write + 0x1803A98 + 0xFFFFFFFF + + + RTRIMOFFET + Adjust the offset voltage of BJT based comparator. + 0 + 4 + read-write + + + RSENSETRIM + Adjust Max inductor peak current limiting. + 4 + 4 + read-write + + + DTESTENABLE + Enable Digital test signals. 8 1 read-write + + SETCURVE + Bandgap calibration parameter. + 9 + 2 + read-write + + + SETDC + Bandgap calibration parameter. + 11 + 4 + read-write + + + DTESTSEL + Select the output signal for test. + 15 + 3 + read-write + + + ISCALEENABLE + Modify COT behavior. + 18 + 1 + read-write + + + FORCEBYPASS + Force bypass mode. + 19 + 1 + read-write + + + TRIMAUTOCOT + Change the scaling ratio of the feedforward compensation. + 20 + 4 + read-write + + + FORCEFULLCYCLE + Force full PFM PMOS and NMOS cycle. + 24 + 1 + read-write + + + LCENABLE + Change the range of the peak detector of current inside the inductor. + 25 + 1 + read-write + + + TOFF + Constant Off-Time calibration input. + 26 + 5 + read-write + + + TOFFENABLE + Enable Constant Off-Time feature. + 31 + 1 + read-write + + + + + LDOPMU + Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x1C + 32 + read-write + 0x10EF718 + 0x31FFFFF + + + VADJ + Sets the Always-On domain LDO output level. + 0 + 5 + read-write + + + V_1P220 + 1.22 V. + 0 + + + V_0P700 + 0.7 V. + 0x1 + + + V_0P725 + 0.725 V. + 0x2 + + + V_0P750 + 0.75 V. + 0x3 + + + V_0P775 + 0.775 V. + 0x4 + + + V_0P800 + 0.8 V. + 0x5 + + + V_0P825 + 0.825 V. + 0x6 + + + V_0P850 + 0.85 V. + 0x7 + + + V_0P875 + 0.875 V. + 0x8 + + + V_0P900 + 0.9 V. + 0x9 + + + V_0P960 + 0.96 V. + 0xA + + + V_0P970 + 0.97 V. + 0xB + + + V_0P980 + 0.98 V. + 0xC + + + V_0P990 + 0.99 V. + 0xD + + + V_1P000 + 1 V. + 0xE + + + V_1P010 + 1.01 V. + 0xF + + + V_1P020 + 1.02 V. + 0x10 + + + V_1P030 + 1.03 V. + 0x11 + + + V_1P040 + 1.04 V. + 0x12 + + + V_1P050 + 1.05 V. + 0x13 + + + V_1P060 + 1.06 V. + 0x14 + + + V_1P070 + 1.07 V. + 0x15 + + + V_1P080 + 1.08 V. + 0x16 + + + V_1P090 + 1.09 V. + 0x17 + + + V_1P100 + 1.1 V. + 0x18 + + + V_1P110 + 1.11 V. + 0x19 + + + V_1P120 + 1.12 V. + 0x1A + + + V_1P130 + 1.13 V. + 0x1B + + + V_1P140 + 1.14 V. + 0x1C + + + V_1P150 + 1.15 V. + 0x1D + + + V_1P160 + 1.16 V. + 0x1E + + + V_1P220_1 + 1.22 V. + 0x1F + + + + + VADJ_PWD + Sets the Always-On domain LDO output level in all power down modes. + 5 + 5 + read-write + + + VADJ_BOOST + Sets the Always-On domain LDO Boost output level. + 10 + 5 + read-write + + + VADJ_BOOST_PWD + Sets the Always-On domain LDO Boost output level in all power down modes. + 15 + 5 + read-write + + + BOOST_ENA + Control the LDO AO boost mode in ACTIVE mode. + 24 + 1 + read-write + + + DISABLE + LDO AO Boost Mode is disable. + 0 + + + ENABLE + LDO AO Boost Mode is enable. + 0x1 + + + + + BOOST_ENA_PWD + Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). + 25 + 1 + read-write + + + DISABLE + LDO AO Boost Mode is disable. + 0 + + + ENABLE + LDO AO Boost Mode is enable. + 0x1 + + + @@ -35692,7 +33728,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x30 32 read-write - 0x69 + 0x47 0x7F @@ -35896,324 +33932,51 @@ SPDX-License-Identifier: BSD-3-Clause - BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x38 + REFFASTWKUP + Analog References fast wake-up Control register [Reset by: PoR] + 0x40 32 read-write - 0x17 - 0x37 + 0x1 + 0x3 - TRIGLVL - BoD trigger level. + LPWKUP + Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . 0 - 3 + 1 read-write - V_0P60 - 0.60 V. + DISABLE + Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. 0 - V_0P65 - 0.65 V. + ENABLE + Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. 0x1 - - V_0P70 - 0.70 V. - 0x2 - - - V_0P75 - 0.75 V. - 0x3 - - - V_0P80 - 0.80 V. - 0x4 - - - V_0P85 - 0.85 V. - 0x5 - - - V_0P90 - 0.90 V. - 0x6 - - - V_0P95 - 0.95 V. - 0x7 - - HYST - BoD Core Hysteresis control. - 4 - 2 - read-write - - - HYST_25MV - 25 mV. - 0 - - - HYST_50MV - 50 mV. - 0x1 - - - HYST_75MV - 75 mV. - 0x2 - - - HYST_100MV - 100 mV. - 0x3 - - - - - - - FRO1M - 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x44 - 32 - read-write - 0x50 - 0x3FFF - - - FREQSEL - Frequency trimming bits. - 0 - 7 - read-write - - - ATBCTRL - Debug control bits to set the analog/digital test modes. - 7 - 2 - read-write - - - DIVSEL - Divider selection bits. - 9 - 5 - read-write - - - DIV_2 - 2.0. - 0 - - - DIV_4 - 4.0. - 0x1 - - - DIV_6 - 6.0. - 0x2 - - - DIV_8 - 8.0. - 0x3 - - - DIV_10 - 10.0. - 0x4 - - - DIV_12 - 12.0. - 0x5 - - - DIV_14 - 14.0. - 0x6 - - - DIV_16 - 16.0. - 0x7 - - - DIV_18 - 18.0. - 0x8 - - - DIV_20 - 20.0. - 0x9 - - - DIV_22 - 22.0. - 0xA - - - DIV_24 - 24.0. - 0xB - - - DIV_26 - 26.0. - 0xC - - - DIV_28 - 28.0. - 0xD - - - DIV_30 - 30.0. - 0xE - - - DIV_32 - 32.0. - 0xF - - - DIV_34 - 34.0. - 0x10 - - - DIV_36 - 36.0. - 0x11 - - - DIV_38 - 38.0. - 0x12 - - - DIV_40 - 40.0. - 0x13 - - - DIV_42 - 42.0. - 0x14 - - - DIV_44 - 44.0. - 0x15 - - - DIV_46 - 46.0. - 0x16 - - - DIV_48 - 48.0. - 0x17 - - - DIV_50 - 50.0. - 0x18 - - - DIV_52 - 52.0. - 0x19 - - - DIV_54 - 54.0. - 0x1A - - - DIV_56 - 56.0. - 0x1B - - - DIV_58 - 58.0. - 0x1C - - - DIV_60 - 60.0. - 0x1D - - - DIV_62 - 62.0. - 0x1E - - - DIV_1 - 1.0. - 0x1F - - - - - - - FRO32K - 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset] - 0x48 - 32 - read-write - 0x90B6 - 0x3FFFE - - - NTAT - Temperature coefficient trimming bits. + HWWKUP + Analog References fast wake-up in case of Hardware Pin reset: . 1 - 3 - read-write - - - PTAT - Bias trimming bits (course frequency trimming). - 4 - 3 - read-write - - - CAPCAL - Capacitive dac calibration bits (fine frequency trimming). - 7 - 9 - read-write - - - ATBCTRL - Debug control bits to set the analog/digital test modes. - 16 - 2 + 1 read-write + + + DISABLE + Analog References fast wake-up feature is disabled in case of Hardware Pin reset. + 0 + + + ENABLE + Analog References fast wake-up feature is enabled in case of Hardware Pin reset. + 0x1 + + @@ -36475,23 +34238,271 @@ SPDX-License-Identifier: BSD-3-Clause FILTERCGF_SAMPLEMODE - Filter Sample mode. + Control the filtering of the Analog Comparator output. 16 2 read-write + + + BYPASS + Bypass mode. + 0 + + + FILTER1CLK + Filter 1 clock period. + 0x1 + + + FILTER2CLK + Filter 2 clock period. + 0x2 + + + FILTER3CLK + Filter 3 clock period. + 0x3 + + FILTERCGF_CLKDIV - Filter Clock div . + Filter Clock divider. 18 3 read-write + + + FILTER_1CLK_PERIOD + Filter clock period duration equals 1 Analog Comparator clock period. + 0 + + + FILTER_2CLK_PERIOD + Filter clock period duration equals 2 Analog Comparator clock period. + 0x1 + + + FILTER_4CLK_PERIOD + Filter clock period duration equals 4 Analog Comparator clock period. + 0x2 + + + FILTER_8CLK_PERIOD + Filter clock period duration equals 8 Analog Comparator clock period. + 0x3 + + + FILTER_16CLK_PERIOD + Filter clock period duration equals 16 Analog Comparator clock period. + 0x4 + + + FILTER_32CLK_PERIOD + Filter clock period duration equals 32 Analog Comparator clock period. + 0x5 + + + FILTER_64CLK_PERIOD + Filter clock period duration equals 64 Analog Comparator clock period. + 0x6 + + + FILTER_128CLK_PERIOD + Filter clock period duration equals 128 Analog Comparator clock period. + 0x7 + + + + + + + WAKEUPIOCTRL + Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] + 0x64 + 32 + read-write + 0 + 0xFF + + + RISINGEDGEWAKEUP0 + Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. + 0 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + - PMUXCAPT - Control word for P multiplexer for Capacitive Touch Controller. - 21 - 3 + FALLINGEDGEWAKEUP0 + Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. + 1 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + RISINGEDGEWAKEUP1 + Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. + 2 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + + + + FALLINGEDGEWAKEUP1 + Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. + 3 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + RISINGEDGEWAKEUP2 + Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. + 4 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + + + + FALLINGEDGEWAKEUP2 + Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. + 5 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + RISINGEDGEWAKEUP3 + Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. + 6 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + + + + FALLINGEDGEWAKEUP3 + Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. + 7 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + MODEWAKEUP0 + Configure wake up I/O 0 in Deep Power Down mode + 8 + 1 + read-write + + + MODEWAKEUP1 + Configure wake up I/O 1 in Deep Power Down mode + 9 + 1 + read-write + + + MODEWAKEUP2 + Configure wake up I/O 2 in Deep Power Down mode + 10 + 1 + read-write + + + MODEWAKEUP3 + Configure wake up I/O 3 in Deep Power Down mode + 11 + 1 read-write @@ -36599,13 +34610,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-only - - FRO1MCLKVALID - FRO 1 MHz CCO voltage detector output. - 1 - 1 - read-only - XTAL32KOSCFAILURE XTAL32 KHZ oscillator oscillation failure detection indicator. @@ -36615,12 +34619,12 @@ SPDX-License-Identifier: BSD-3-Clause NOFAIL - No oscillation failure has been detetced since the last time this bit has been cleared.. + No oscillation failure has been detetced since the last time this bit has been cleared. 0 FAILURE - At least one oscillation failure has been detetced since the last time this bit has been cleared.. + At least one oscillation failure has been detetced since the last time this bit has been cleared. 0x1 @@ -36637,12 +34641,211 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - DATA31_0 - General purpose always on domain data storage. - 0 - 32 + POR + The last chip reset was caused by a Power On Reset. + 4 + 1 read-write + + PADRESET + The last chip reset was caused by a Pin Reset. + 5 + 1 + read-write + + + BODRESET + The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. + 6 + 1 + read-write + + + SYSTEMRESET + The last chip reset was caused by a System Reset requested by the ARM CPU. + 7 + 1 + read-write + + + WDTRESET + The last chip reset was caused by the Watchdog Timer. + 8 + 1 + read-write + + + SWRRESET + The last chip reset was caused by a Software event. + 9 + 1 + read-write + + + DPDRESET_WAKEUPIO + The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. + 10 + 1 + read-write + + + DPDRESET_RTC + The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. + 11 + 1 + read-write + + + DPDRESET_OSTIMER + The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. + 12 + 1 + read-write + + + BOOTERRORCOUNTER + ROM Boot Fatal Error Counter. + 16 + 4 + read-write + + + + + MISCCTRL + Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x90 + 32 + read-write + 0 + 0xFFFF + + + LDODEEPSLEEPREF + Select LDO Deep Sleep reference source. + 0 + 1 + read-write + + + FLASHBUFFER + LDO DEEP Sleep uses Flash buffer biasing as reference. + 0 + + + BGP0P8V + LDO DEEP Sleep uses Band Gap 0.8V as reference. + 0x1 + + + + + LDOMEMHIGHZMODE + Control the activation of LDO MEM High Z mode. + 1 + 1 + read-write + + + DISABLE + LDO MEM High Z mode is disabled. + 0 + + + ENABLE + LDO MEM High Z mode is enabled. + 0x1 + + + + + LOWPWR_FLASH_BUF + no description available + 2 + 1 + read-write + + + MISCCTRL_3_8 + Reserved. + 3 + 5 + read-write + + + MODEWAKEUP0 + Configure wake up I/O 0 in Deep Power Down mode + 8 + 1 + read-write + + + MODEWAKEUP1 + Configure wake up I/O 1 in Deep Power Down mode + 9 + 1 + read-write + + + MODEWAKEUP2 + Configure wake up I/O 2 in Deep Power Down mode + 10 + 1 + read-write + + + MODEWAKEUP3 + Configure wake up I/O 3 in Deep Power Down mode + 11 + 1 + read-write + + + DISABLE_BLEED + Controls LDO MEM bleed current. This field is expected to be controlled by the Low Power Software only in DEEP SLEEP low power mode. + 12 + 1 + read-write + + + BLEED_ENABLE + LDO_MEM bleed current is enabled. + 0 + + + BLEED_DISABLE + LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared after wake up from Deep SLeep low power mode. + 0x1 + + + + + MISCCTRL_13_14 + Reserved. + 13 + 2 + read-write + + + WAKUPIO_RST + WAKEUP IO event detector reset control. + 15 + 1 + read-write + + + RELEASED + Wakeup IO is not reset. + 0 + + + ASSERTED + Wakeup IO is reset. + 0x1 + + + @@ -36749,492 +34952,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] - 0xB0 - 32 - read-write - 0xC0 - 0x1FFFFFF - - - PDEN_DCDC - Controls DCDC power during DEEP SLEEP (DCDC is always shut down during POWER DOWN and DEEP POWER DOWN). - 0 - 1 - read-write - - - POWEREDON - DCDC is powered on during low power mode.. - 0 - - - POWEREDOFF - DCDC is powered off during low power mode.. - 0x1 - - - - - PDEN_BIAS - Controls Analog Bias power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 1 - 1 - read-write - - - POWEREDON - Analog Bias is powered on during low power mode.. - 0 - - - POWEREDOFF - Analog Bias is powered off during low power mode.. - 0x1 - - - - - PDEN_BODCORE - Controls Core Logic BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 2 - 1 - read-write - - - POWEREDON - BOD CORE is powered on during low power mode.. - 0 - - - POWEREDOFF - BOD CORE is powered off during low power mode.. - 0x1 - - - - - PDEN_BODVBAT - Controls VBAT BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 3 - 1 - read-write - - - POWEREDON - BOD VBAT is powered on during low power mode.. - 0 - - - POWEREDOFF - BOD VBAT is powered off during low power mode.. - 0x1 - - - - - PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - 4 - 1 - read-write - - - POWEREDON - FRO 1MHz is powered on during low power mode.. - 0 - - - POWEREDOFF - FRO 1MHz is powered off during low power mode.. - 0x1 - - - - - PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 5 - 1 - read-write - - - POWEREDON - FRO 192 MHz is powered on during low power mode.. - 0 - - - POWEREDOFF - FRO 192 MHz is powered off during low power mode.. - 0x1 - - - - - PDEN_FRO32K - Controls power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - 6 - 1 - read-write - - - POWEREDON - FRO 32 KHz is powered on during low power mode.. - 0 - - - POWEREDOFF - FRO 32 KHz is powered off during low power mode.. - 0x1 - - - - - PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - 7 - 1 - read-write - - - POWEREDON - crystal 32 KHz is powered on during low power mode.. - 0 - - - POWEREDOFF - crystal 32 KHz is powered off during low power mode.. - 0x1 - - - - - PDEN_XTAL32M - Controls crystal 32 MHz power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 8 - 1 - read-write - - - POWEREDON - crystal 32 MHz is powered on during low power mode.. - 0 - - - POWEREDOFF - crystal 32 MHz is powered off during low power mode.. - 0x1 - - - - - PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 9 - 1 - read-write - - - POWEREDON - System PLL (also refered as PLL0) is powered on during low power mode.. - 0 - - - POWEREDOFF - System PLL (also refered as PLL0) is powered off during low power mode.. - 0x1 - - - - - PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 10 - 1 - read-write - - - POWEREDON - USB PLL (also refered as PLL1) is powered on during low power mode.. - 0 - - - POWEREDOFF - USB PLL (also refered as PLL1) is powered off during low power mode.. - 0x1 - - - - - PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 11 - 1 - read-write - - - POWEREDON - USB Full Speed phy is powered on during low power mode.. - 0 - - - POWEREDOFF - USB Full Speed phy is powered off during low power mode.. - 0x1 - - - - - PDEN_USBHSPHY - Controls USB High Speed Phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 12 - 1 - read-write - - - POWEREDON - USB High Speed Phy is powered on during low power mode.. - 0 - - - POWEREDOFF - USB High Speed Phy is powered off during low power mode.. - 0x1 - - - - - PDEN_COMP - Controls Analog Comparator power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 13 - 1 - read-write - - - POWEREDON - Analog Comparator is powered on during low power mode.. - 0 - - - POWEREDOFF - Analog Comparator is powered off during low power mode.. - 0x1 - - - - - PDEN_TEMPSENS - Controls Temperature Sensor power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 14 - 1 - read-write - - - POWEREDON - Temperature Sensor is powered on during low power mode.. - 0 - - - POWEREDOFF - Temperature Sensor is powered off during low power mode.. - 0x1 - - - - - PDEN_GPADC - Controls General Purpose ADC (GPADC) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 15 - 1 - read-write - - - POWEREDON - General Purpose ADC (GPADC) is powered on during low power mode.. - 0 - - - POWEREDOFF - General Purpose ADC (GPADC) is powered off during low power mode.. - 0x1 - - - - - PDEN_LDOMEM - Controls Memories LDO power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - 16 - 1 - read-write - - - POWEREDON - Memories LDO is powered on during low power mode.. - 0 - - - POWEREDOFF - Memories LDO is powered off during low power mode.. - 0x1 - - - - - PDEN_LDODEEPSLEEP - Controls Deep Sleep LDO power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 17 - 1 - read-write - - - POWEREDON - Deep Sleep LDO is powered on during low power mode.. - 0 - - - POWEREDOFF - Deep Sleep LDO is powered off during low power mode.. - 0x1 - - - - - PDEN_LDOUSBHS - Controls USB high speed LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 18 - 1 - read-write - - - POWEREDON - USB high speed LDO is powered on during low power mode.. - 0 - - - POWEREDOFF - USB high speed LDO is powered off during low power mode.. - 0x1 - - - - - PDEN_AUXBIAS - during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 19 - 1 - read-write - - - POWEREDON - is powered on during low power mode.. - 0 - - - POWEREDOFF - is powered off during low power mode.. - 0x1 - - - - - PDEN_LDOXO32M - Controls crystal 32 MHz LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 20 - 1 - read-write - - - POWEREDON - crystal 32 MHz LDO is powered on during low power mode.. - 0 - - - POWEREDOFF - crystal 32 MHz LDO is powered off during low power mode.. - 0x1 - - - - - PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 21 - 1 - read-write - - - POWEREDON - Flash NV (high voltage) is powered on during low power mode.. - 0 - - - POWEREDOFF - Flash NV (high voltage) is powered off during low power mode.. - 0x1 - - - - - PDEN_RNG - Controls True Random Number Genetaor (TRNG) clock sources power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 22 - 1 - read-write - - - POWEREDON - True Random Number Genetaor (TRNG) clock sources are powered on during low power mode.. - 0 - - - POWEREDOFF - True Random Number Genetaor (TRNG) clock sources are powered off during low power mode.. - 0x1 - - - - - PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP SLEEP (PLL0 Spread Spectrum is always shut down during POWER DOWN and DEEP POWER DOWN). - 23 - 1 - read-write - - - POWEREDON - PLL0 Spread Sprectrum module is powered on during low power mode.. - 0 - - - POWEREDOFF - PLL0 Spread Sprectrum module is powered off during low power mode.. - 0x1 - - - - - PDEN_ROM - Controls ROM power during DEEP SLEEP (ROM is always shut down during POWER DOWN and DEEP POWER DOWN). - 24 - 1 - read-write - - - POWEREDON - ROM is powered on during low power mode.. - 0 - - - POWEREDOFF - ROM is powered off during low power mode.. - 0x1 - - - - - PDRUNCFG0 Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] @@ -37244,63 +34961,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xDEFFC4 0xFFFFEF - - PDEN_DCDC - Controls power to Bulk DCDC Converter. - 0 - 1 - read-write - - - POWEREDON - DCDC is powered. - 0 - - - POWEREDOFF - DCDC is powered down. - 0x1 - - - - - PDEN_BIAS - Controls power to . - 1 - 1 - read-write - - - POWEREDON - Analog Bias is powered. - 0 - - - POWEREDOFF - Analog Bias is powered down. - 0x1 - - - - - PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD). - 2 - 1 - read-write - - - POWEREDON - BOD CORE is powered. - 0 - - - POWEREDOFF - BOD CORE is powered down. - 0x1 - - - PDEN_BODVBAT Controls power to VBAT Brown Out Detector (BOD). @@ -37320,25 +34980,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz and 96 MHz clocks are derived from this FRO. - 5 - 1 - read-write - - - POWEREDON - FRO 192MHz is powered. - 0 - - - POWEREDOFF - FRO 192MHz is powered down. - 0x1 - - - PDEN_FRO32K Controls power to the Free Running Oscillator (FRO) 32 KHz. @@ -37379,19 +35020,19 @@ SPDX-License-Identifier: BSD-3-Clause PDEN_XTAL32M - Controls power to crystal 32 MHz. + Controls power to high speed crystal. 8 1 read-write POWEREDON - Crystal 32MHz is powered. + High speed crystal is powered. 0 POWEREDOFF - Crystal 32MHz is powered down. + High speed crystal is powered down. 0x1 @@ -37491,82 +35132,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PDEN_TEMPSENS - Controls power to Temperature Sensor. - 14 - 1 - read-write - - - POWEREDON - Temperature Sensor is powered. - 0 - - - POWEREDOFF - Temperature Sensor is powered down. - 0x1 - - - - - PDEN_GPADC - Controls power to General Purpose ADC (GPADC). - 15 - 1 - read-write - - - POWEREDON - GPADC is powered. - 0 - - - POWEREDOFF - GPADC is powered down. - 0x1 - - - - - PDEN_LDOMEM - Controls power to Memories LDO. - 16 - 1 - read-write - - - POWEREDON - Memories LDO is powered. - 0 - - - POWEREDOFF - Memories LDO is powered down. - 0x1 - - - - - PDEN_LDODEEPSLEEP - Controls power to Deep Sleep LDO. - 17 - 1 - read-write - - - POWEREDON - Deep Sleep LDO is powered. - 0 - - - POWEREDOFF - Deep Sleep LDO is powered down. - 0x1 - - - PDEN_LDOUSBHS Controls power to USB high speed LDO. @@ -37607,38 +35172,19 @@ SPDX-License-Identifier: BSD-3-Clause PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO. + Controls power to high speed crystal LDO. 20 1 read-write POWEREDON - crystal 32 MHz LDO is powered. + High speed crystal LDO is powered. 0 POWEREDOFF - crystal 32 MHz LDO is powered down. - 0x1 - - - - - PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO. - 21 - 1 - read-write - - - POWEREDON - Flash NV LDO is powered. - 0 - - - POWEREDOFF - Flash NV LDO is powered down. + High speed crystal LDO is powered down. 0x1 @@ -37719,6 +35265,67 @@ SPDX-License-Identifier: BSD-3-Clause + + SRAMCTRL + All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] + 0xD4 + 32 + read-write + 0x1 + 0x1FF + + + SMB + Source Biasing voltage. + 0 + 2 + read-write + + + LOW + Low leakage. + 0 + + + MEDIUM + Medium leakage. + 0x1 + + + HIGHEST + Highest leakage. + 0x2 + + + DISABLE + Disable. + 0x3 + + + + + RM + Read Margin control settings. + 2 + 3 + read-write + + + WM + Write Margin control settings. + 5 + 3 + read-write + + + WRME + Write read margin enable. + 8 + 1 + read-write + + + @@ -37767,7 +35374,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x4 0,1,2,3,4,5,6,7 FCCTRLSEL%s - Selects the source for SCK going into Flexcomm 0 + Selects the source for SCK going into Flexcomm index 0x40 32 read-write @@ -37877,7 +35484,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x4 0,1 SHAREDCTRLSET%s - Selects sources and data combinations for shared signal set 0. + Selects sources and data combinations for shared signal set index. 0x80 32 read-write @@ -38070,7 +35677,7 @@ SPDX-License-Identifier: BSD-3-Clause - F20DATAOUTEN + FC2DATAOUTEN Controls FC2 contribution to SHAREDDATAOUT for this shared set. 18 1 @@ -38088,25 +35695,6 @@ SPDX-License-Identifier: BSD-3-Clause - - FC3DATAOUTEN - Controls FC3 contribution to SHAREDDATAOUT for this shared set. - 19 - 1 - read-write - - - INPUT - Data output from FC3 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC3 does contribute to this shared set. - 0x1 - - - FC4DATAOUTEN Controls FC4 contribution to SHAREDDATAOUT for this shared set. @@ -38190,7 +35778,7 @@ SPDX-License-Identifier: BSD-3-Clause Status register for USB HS 0x100 32 - read-write + read-only 0 0x1C0FF00 @@ -38239,7 +35827,7 @@ SPDX-License-Identifier: BSD-3-Clause 32 read-write 0x1 - 0x3FD + 0x7FD SWRESET @@ -38489,16 +36077,16 @@ SPDX-License-Identifier: BSD-3-Clause SUBSEC - RTC Sub-second Counter register + Sub-second counter register 0x10 32 read-write 0 - 0xFFFFFFFF + 0xFFFF SUBSEC - A read reflects the current value of the 32Khz sub-second counter. This counter will be cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32 KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep_powerdown mode or after the main RTC module has been disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes. + A read reflects the current value of the 32KHz sub-second counter. This counter is cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep power-down mode or after the main RTC module is disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes. 0 15 read-only @@ -38553,7 +36141,7 @@ SPDX-License-Identifier: BSD-3-Clause EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the EVTIMER. Note there is physically only one EVTimer, readable from all domains. + A read reflects the current value of the lower 32 bits of the 42-bits EVTIMER. Note: There is only one EVTIMER, readable from all domains. 0 32 read-only @@ -38565,22 +36153,22 @@ SPDX-License-Identifier: BSD-3-Clause EVTIMER High Register 0x4 32 - read-only + read-write 0 0xFFFFFFFF EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 32 bits of the EVTIMER. Note there is physically only one EVTimer, readable from all domains. + A read reflects the current value of the upper 10 bits of the 42-bits EVTIMER. Note there is only one EVTIMER, readable from all domains. 0 - 32 + 10 read-only - CAPTUREn_L - Local Capture Low Register for CPUn + CAPTURE_L + Capture Low Register 0x8 32 read-only @@ -38588,8 +36176,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - CAPTUREn_VALUE - A read reflects the value of the lower 32 bits of the central EVTIMER at the time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses. + CAPTURE_VALUE + A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). 0 32 read-only @@ -38597,26 +36185,26 @@ SPDX-License-Identifier: BSD-3-Clause - CAPTUREn_H - Local Capture High Register for CPUn + CAPTURE_H + Capture High Register 0xC 32 - read-only + read-write 0 0xFFFFFFFF - CAPTUREn_VALUE - A read reflects the value of the upper 32 bits of the central EVTIMER at the time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses. + CAPTURE_VALUE + A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). 0 - 32 + 10 read-only - MATCHn_L - Local Match Low Register for CPUn + MATCH_L + Match Low Register 0x10 32 read-write @@ -38624,8 +36212,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - MATCHn_VALUE - The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses. + MATCH_VALUE + The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. 0 32 read-write @@ -38633,8 +36221,8 @@ SPDX-License-Identifier: BSD-3-Clause - MATCHn_H - Match High Register for CPUn + MATCH_H + Match High Register 0x14 32 read-write @@ -38642,37 +36230,44 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - MATCHn_VALUE - The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses. + MATCH_VALUE + The value written (upper 10 bits) to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. 0 - 32 + 10 read-write OSEVENT_CTRL - OS_EVENT TIMER Control Register for CPUn + OS_EVENT TIMER Control Register 0x1C 32 read-write 0 - 0x3 + 0x7 OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 64-bit EVTIMER and the value programmed in the Match-register pair for the associated CPU This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. This should be done before a new match value is written into the MATCH_L/H registers + This bit is set when a match occurs between the central 42-bits EVTIMER and the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. It should be done before a new match value is written into the MATCH_L/H registers. 0 1 read-write OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the Domainn processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked.A separate OSEVENT_CTRL register is implemented for each CPU. Each CPU reads its own local value at the same address. + When this bit is '1' an interrupt/wakeup request to the domain processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked. 1 1 read-write + + MATCH_WR_RDY + This bit will be low when it is safe to write to reload the Match Registers. In typical applications it should not be necessary to test this bit. [1] + 2 + 1 + read-only + @@ -38738,45 +36333,6 @@ SPDX-License-Identifier: BSD-3-Clause - - BURST - read burst register - 0x8 - 32 - read-write - 0x80000000 - 0xFFFFFFFF - - - XOR_MASK - burst 2 XOR mask. - 0 - 20 - read-write - - - DESCR1 - Burst 1 descriptor. - 20 - 4 - read-write - - - DESCR2 - Burst 2 descriptor. - 24 - 4 - read-write - - - DESCR3 - Burst 3 descriptor. - 28 - 4 - read-write - - - STARTA start (or only) address for next flash command @@ -38814,7 +36370,7 @@ SPDX-License-Identifier: BSD-3-Clause - 8 + 4 0x4 DATAW[%s] data register, word 0-7; Memory data, or command parameter, or command result. @@ -39137,12 +36693,12 @@ SPDX-License-Identifier: BSD-3-Clause DISABLED - Encryption of writes to the flash controller DATAW* registers is disabled.. + Encryption of writes to the flash controller DATAW* registers is disabled. 0 ENABLED - Encryption of writes to the flash controller DATAW* registers is enabled.. + Encryption of writes to the flash controller DATAW* registers is enabled. 0x1 @@ -39521,6 +37077,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x110 registers + + USB1_PHY + 46 + PWD @@ -40718,6 +38278,13 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode @@ -40745,16 +38312,37 @@ SPDX-License-Identifier: BSD-3-Clause - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 1 read-write - DATA_ON_LRADC - Data on LR ADC: Enables the LRADC to monitor USB_DP and USB_DM - 13 + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 1 read-write @@ -40772,6 +38360,20 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) @@ -40794,16 +38396,30 @@ SPDX-License-Identifier: BSD-3-Clause read-write - FSDLL_RST_EN - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. - 24 + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 1 read-write - OTG_ID_VALUE - Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle - 27 + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 1 read-write @@ -40853,6 +38469,13 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode @@ -40879,6 +38502,34 @@ SPDX-License-Identifier: BSD-3-Clause + + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + DEVPLUGIN_IRQ Indicates that the device is connected @@ -40900,6 +38551,20 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) @@ -40922,16 +38587,30 @@ SPDX-License-Identifier: BSD-3-Clause read-write - FSDLL_RST_EN - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. - 24 + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 1 read-write - OTG_ID_VALUE - Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle - 27 + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 1 read-write @@ -40947,7 +38626,7 @@ SPDX-License-Identifier: BSD-3-Clause Used by the PHY to indicate a powered-down state 29 1 - read-write + read-only CLKGATE @@ -40981,6 +38660,13 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode @@ -41007,6 +38693,34 @@ SPDX-License-Identifier: BSD-3-Clause + + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + DEVPLUGIN_IRQ Indicates that the device is connected @@ -41028,6 +38742,20 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) @@ -41050,16 +38778,30 @@ SPDX-License-Identifier: BSD-3-Clause read-write - FSDLL_RST_EN - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. - 24 + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 1 read-write - OTG_ID_VALUE - Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle - 27 + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 1 read-write @@ -41109,6 +38851,13 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode @@ -41135,6 +38884,34 @@ SPDX-License-Identifier: BSD-3-Clause + + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + DEVPLUGIN_IRQ Indicates that the device is connected @@ -41156,6 +38933,20 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) @@ -41178,16 +38969,30 @@ SPDX-License-Identifier: BSD-3-Clause read-write - FSDLL_RST_EN - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. - 24 + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 1 read-write - OTG_ID_VALUE - Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle - 27 + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 1 read-write @@ -41230,12 +39035,19 @@ SPDX-License-Identifier: BSD-3-Clause 0 0xFFFFFFFF + + OK_STATUS_3V + Indicates the USB 3v power rails are in range. + 0 + 1 + read-only + HOSTDISCONDETECT_STATUS Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode 3 1 - read-write + read-only value0 @@ -41254,7 +39066,7 @@ SPDX-License-Identifier: BSD-3-Clause Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4] 6 1 - read-write + read-only value0 @@ -41268,618 +39080,11 @@ SPDX-License-Identifier: BSD-3-Clause - - OTGID_STATUS - Indicates the results of USB_ID pin on the USB cable plugged into the local Micro- or Mini-AB receptacle - 8 - 1 - read-write - RESUME_STATUS Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt. 10 1 - read-write - - - - - DEBUG0 - USB PHY Debug Register 0 - 0x50 - 32 - read-write - 0x7F180000 - 0xFFFFFFFF - - - OTGIDPIOLOCK - Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value - 0 - 1 - read-write - - - DEBUG_INTERFACE_HOLD - Use holding registers to assist in timing for external UTMI interface. - 1 - 1 - read-write - - - HSTPULLDOWN - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line - 2 - 2 - read-write - - - ENHSTPULLDOWN - This bit field selects host pulldown overdrive mode - 4 - 2 - read-write - - - TX2RXCOUNT - Delay in between the end of transmit to the beginning of receive - 8 - 4 - read-write - - - ENTX2RXCOUNT - Set this bit to allow a countdown to transition in between TX and RX. - 12 - 1 - read-write - - - SQUELCHRESETCOUNT - Delay in between the detection of squelch to the reset of high-speed RX. - 16 - 5 - read-write - - - ENSQUELCHRESET - Set bit to allow squelch to reset high-speed receive. - 24 - 1 - read-write - - - SQUELCHRESETLENGTH - Duration of RESET in terms of the number of 480-MHz cycles. - 25 - 4 - read-write - - - HOST_RESUME_DEBUG - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. - 29 - 1 - read-write - - - CLKGATE - Gate Test Clocks - 30 - 1 - read-write - - - - - DEBUG0_SET - USB PHY Debug Register 0 - 0x54 - 32 - read-write - 0x7F180000 - 0xFFFFFFFF - - - OTGIDPIOLOCK - Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value - 0 - 1 - read-write - - - DEBUG_INTERFACE_HOLD - Use holding registers to assist in timing for external UTMI interface. - 1 - 1 - read-write - - - HSTPULLDOWN - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line - 2 - 2 - read-write - - - ENHSTPULLDOWN - This bit field selects host pulldown overdrive mode - 4 - 2 - read-write - - - TX2RXCOUNT - Delay in between the end of transmit to the beginning of receive - 8 - 4 - read-write - - - ENTX2RXCOUNT - Set this bit to allow a countdown to transition in between TX and RX. - 12 - 1 - read-write - - - SQUELCHRESETCOUNT - Delay in between the detection of squelch to the reset of high-speed RX. - 16 - 5 - read-write - - - ENSQUELCHRESET - Set bit to allow squelch to reset high-speed receive. - 24 - 1 - read-write - - - SQUELCHRESETLENGTH - Duration of RESET in terms of the number of 480-MHz cycles. - 25 - 4 - read-write - - - HOST_RESUME_DEBUG - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. - 29 - 1 - read-write - - - CLKGATE - Gate Test Clocks - 30 - 1 - read-write - - - - - DEBUG0_CLR - USB PHY Debug Register 0 - 0x58 - 32 - read-write - 0x7F180000 - 0xFFFFFFFF - - - OTGIDPIOLOCK - Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value - 0 - 1 - read-write - - - DEBUG_INTERFACE_HOLD - Use holding registers to assist in timing for external UTMI interface. - 1 - 1 - read-write - - - HSTPULLDOWN - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line - 2 - 2 - read-write - - - ENHSTPULLDOWN - This bit field selects host pulldown overdrive mode - 4 - 2 - read-write - - - TX2RXCOUNT - Delay in between the end of transmit to the beginning of receive - 8 - 4 - read-write - - - ENTX2RXCOUNT - Set this bit to allow a countdown to transition in between TX and RX. - 12 - 1 - read-write - - - SQUELCHRESETCOUNT - Delay in between the detection of squelch to the reset of high-speed RX. - 16 - 5 - read-write - - - ENSQUELCHRESET - Set bit to allow squelch to reset high-speed receive. - 24 - 1 - read-write - - - SQUELCHRESETLENGTH - Duration of RESET in terms of the number of 480-MHz cycles. - 25 - 4 - read-write - - - HOST_RESUME_DEBUG - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. - 29 - 1 - read-write - - - CLKGATE - Gate Test Clocks - 30 - 1 - read-write - - - - - DEBUG0_TOG - USB PHY Debug Register 0 - 0x5C - 32 - read-write - 0x7F180000 - 0xFFFFFFFF - - - OTGIDPIOLOCK - Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value - 0 - 1 - read-write - - - DEBUG_INTERFACE_HOLD - Use holding registers to assist in timing for external UTMI interface. - 1 - 1 - read-write - - - HSTPULLDOWN - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line - 2 - 2 - read-write - - - ENHSTPULLDOWN - This bit field selects host pulldown overdrive mode - 4 - 2 - read-write - - - TX2RXCOUNT - Delay in between the end of transmit to the beginning of receive - 8 - 4 - read-write - - - ENTX2RXCOUNT - Set this bit to allow a countdown to transition in between TX and RX. - 12 - 1 - read-write - - - SQUELCHRESETCOUNT - Delay in between the detection of squelch to the reset of high-speed RX. - 16 - 5 - read-write - - - ENSQUELCHRESET - Set bit to allow squelch to reset high-speed receive. - 24 - 1 - read-write - - - SQUELCHRESETLENGTH - Duration of RESET in terms of the number of 480-MHz cycles. - 25 - 4 - read-write - - - HOST_RESUME_DEBUG - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. - 29 - 1 - read-write - - - CLKGATE - Gate Test Clocks - 30 - 1 - read-write - - - - - DEBUG1 - UTMI Debug Status Register 1 - 0x70 - 32 - read-write - 0x1000 - 0xFFFFFFFF - - - ENTAILADJVD - Delay increment of the rise of squelch: - 13 - 2 - read-write - - - value0 - Delay is nominal - 0 - - - value1 - Delay is +20% - 0x1 - - - value2 - Delay is -20% - 0x2 - - - value3 - Delay is -40% - 0x3 - - - - - USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap - 18 - 3 - read-write - - - USB2_REFBIAS_TST - Bias current control for usb2_phy - 21 - 2 - read-write - - - - - DEBUG1_SET - UTMI Debug Status Register 1 - 0x74 - 32 - read-write - 0x1000 - 0xFFFFFFFF - - - ENTAILADJVD - Delay increment of the rise of squelch: - 13 - 2 - read-write - - - value0 - Delay is nominal - 0 - - - value1 - Delay is +20% - 0x1 - - - value2 - Delay is -20% - 0x2 - - - value3 - Delay is -40% - 0x3 - - - - - USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap - 18 - 3 - read-write - - - USB2_REFBIAS_TST - Bias current control for usb2_phy - 21 - 2 - read-write - - - - - DEBUG1_CLR - UTMI Debug Status Register 1 - 0x78 - 32 - read-write - 0x1000 - 0xFFFFFFFF - - - ENTAILADJVD - Delay increment of the rise of squelch: - 13 - 2 - read-write - - - value0 - Delay is nominal - 0 - - - value1 - Delay is +20% - 0x1 - - - value2 - Delay is -20% - 0x2 - - - value3 - Delay is -40% - 0x3 - - - - - USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap - 18 - 3 - read-write - - - USB2_REFBIAS_TST - Bias current control for usb2_phy - 21 - 2 - read-write - - - - - DEBUG1_TOG - UTMI Debug Status Register 1 - 0x7C - 32 - read-write - 0x1000 - 0xFFFFFFFF - - - ENTAILADJVD - Delay increment of the rise of squelch: - 13 - 2 - read-write - - - value0 - Delay is nominal - 0 - - - value1 - Delay is +20% - 0x1 - - - value2 - Delay is -20% - 0x2 - - - value3 - Delay is -40% - 0x3 - - - - - USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap - 18 - 3 - read-write - - - USB2_REFBIAS_TST - Bias current control for usb2_phy - 21 - 2 - read-write - - - - - VERSION - UTMI RTL Version - 0x80 - 32 - read-only - 0x5000000 - 0xFFFFFFFF - - - STEP - Fixed read-only value reflecting the stepping of the RTL version. - 0 - 16 - read-only - - - MINOR - Fixed read-only value reflecting the MINOR field of the RTL version - 16 - 8 - read-only - - - MAJOR - Fixed read-only value reflecting the MAJOR field of the RTL versio - 24 - 8 read-only @@ -41893,13 +39098,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xD12000 0xFFFFFFFF - - MISC2_CONTROL0 - Modifies the operation of the pll_sic_power_int signal - 5 - 1 - read-write - PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY @@ -41921,13 +39119,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - PLL_BYPASS - Bypass the USB PLL. - 16 - 1 - read-write - REFBIAS_PWD_SEL Reference bias power down select. @@ -42010,12 +39201,19 @@ SPDX-License-Identifier: BSD-3-Clause + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + PLL_LOCK USB PLL lock status indicator 31 1 - read-write + read-only value0 @@ -42040,13 +39238,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xD12000 0xFFFFFFFF - - MISC2_CONTROL0 - Modifies the operation of the pll_sic_power_int signal - 5 - 1 - read-write - PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY @@ -42068,13 +39259,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - PLL_BYPASS - Bypass the USB PLL. - 16 - 1 - read-write - REFBIAS_PWD_SEL Reference bias power down select. @@ -42157,12 +39341,19 @@ SPDX-License-Identifier: BSD-3-Clause + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + PLL_LOCK USB PLL lock status indicator 31 1 - read-write + read-only value0 @@ -42187,13 +39378,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xD12000 0xFFFFFFFF - - MISC2_CONTROL0 - Modifies the operation of the pll_sic_power_int signal - 5 - 1 - read-write - PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY @@ -42215,13 +39399,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - PLL_BYPASS - Bypass the USB PLL. - 16 - 1 - read-write - REFBIAS_PWD_SEL Reference bias power down select. @@ -42304,12 +39481,19 @@ SPDX-License-Identifier: BSD-3-Clause + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + PLL_LOCK USB PLL lock status indicator 31 1 - read-write + read-only value0 @@ -42334,13 +39518,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xD12000 0xFFFFFFFF - - MISC2_CONTROL0 - Modifies the operation of the pll_sic_power_int signal - 5 - 1 - read-write - PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY @@ -42362,13 +39539,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - PLL_BYPASS - Bypass the USB PLL. - 16 - 1 - read-write - REFBIAS_PWD_SEL Reference bias power down select. @@ -42451,12 +39621,19 @@ SPDX-License-Identifier: BSD-3-Clause + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + PLL_LOCK USB PLL lock status indicator 31 1 - read-write + read-only value0 @@ -42620,6 +39797,58 @@ SPDX-License-Identifier: BSD-3-Clause + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pinmuxed value: + 13 + 1 + read-write + + + value0 + Select the Muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pinmuxed value. + 14 + 1 + read-write + + + value0 + Select the Muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator @@ -42640,11 +39869,18 @@ SPDX-License-Identifier: BSD-3-Clause - PWRUP_CMPS - Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector - 20 + VBUSVALID_5VDETECT + no description available + 19 1 read-write + + + PWRUP_CMPS + Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector + 20 + 3 + read-write value0 @@ -42654,7 +39890,7 @@ SPDX-License-Identifier: BSD-3-Clause value1 Enables the VBUS_VALID comparator (default) - 0x1 + 0x7 @@ -42677,25 +39913,6 @@ SPDX-License-Identifier: BSD-3-Clause - - EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - 31 - 1 - read-write - - - value0 - Disable resistive charger detection resistors on USB_DP and USB_DP - 0 - - - value1 - Enable resistive charger detection resistors on USB_DP and USB_DP - 0x1 - - - @@ -42846,6 +40063,58 @@ SPDX-License-Identifier: BSD-3-Clause + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pinmuxed value: + 13 + 1 + read-write + + + value0 + Select the Muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pinmuxed value. + 14 + 1 + read-write + + + value0 + Select the Muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator @@ -42866,11 +40135,18 @@ SPDX-License-Identifier: BSD-3-Clause - PWRUP_CMPS - Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector - 20 + VBUSVALID_5VDETECT + no description available + 19 1 read-write + + + PWRUP_CMPS + Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector + 20 + 3 + read-write value0 @@ -42880,7 +40156,7 @@ SPDX-License-Identifier: BSD-3-Clause value1 Enables the VBUS_VALID comparator (default) - 0x1 + 0x7 @@ -42903,25 +40179,6 @@ SPDX-License-Identifier: BSD-3-Clause - - EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - 31 - 1 - read-write - - - value0 - Disable resistive charger detection resistors on USB_DP and USB_DP - 0 - - - value1 - Enable resistive charger detection resistors on USB_DP and USB_DP - 0x1 - - - @@ -43072,6 +40329,58 @@ SPDX-License-Identifier: BSD-3-Clause + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pinmuxed value: + 13 + 1 + read-write + + + value0 + Select the Muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pin muxed value. + 14 + 1 + read-write + + + value0 + Select the muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator @@ -43092,11 +40401,18 @@ SPDX-License-Identifier: BSD-3-Clause - PWRUP_CMPS - Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector - 20 + VBUSVALID_5VDETECT + no description available + 19 1 read-write + + + PWRUP_CMPS + Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector + 20 + 3 + read-write value0 @@ -43106,7 +40422,7 @@ SPDX-License-Identifier: BSD-3-Clause value1 Enables the VBUS_VALID comparator (default) - 0x1 + 0x7 @@ -43129,25 +40445,6 @@ SPDX-License-Identifier: BSD-3-Clause - - EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - 31 - 1 - read-write - - - value0 - Disable resistive charger detection resistors on USB_DP and USB_DP - 0 - - - value1 - Enable resistive charger detection resistors on USB_DP and USB_DP - 0x1 - - - @@ -43298,6 +40595,58 @@ SPDX-License-Identifier: BSD-3-Clause + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pin muxed value. + 13 + 1 + read-write + + + value0 + Select the muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pin muxed value. + 14 + 1 + read-write + + + value0 + Select the Muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator @@ -43317,11 +40666,18 @@ SPDX-License-Identifier: BSD-3-Clause + + VBUSVALID_5VDETECT + no description available + 19 + 1 + read-write + PWRUP_CMPS Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector 20 - 1 + 3 read-write @@ -43332,7 +40688,7 @@ SPDX-License-Identifier: BSD-3-Clause value1 Enables the VBUS_VALID comparator (default) - 0x1 + 0x7 @@ -43355,385 +40711,6 @@ SPDX-License-Identifier: BSD-3-Clause - - EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - 31 - 1 - read-write - - - value0 - Disable resistive charger detection resistors on USB_DP and USB_DP - 0 - - - value1 - Enable resistive charger detection resistors on USB_DP and USB_DP - 0x1 - - - - - - - USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register - 0xD0 - 32 - read-only - 0 - 0xFFFFFFFF - - - SESSEND - Session End indicator Session End status, value inverted from Session Valid comparator - 0 - 1 - read-only - - - value0 - The VBUS voltage is above the Session Valid threshold - 0 - - - value1 - The VBUS voltage is below the Session Valid threshold - 0x1 - - - - - BVALID - B-Device Session Valid status B-Device Session Valid status, determined by the Session Valid comparator - 1 - 1 - read-only - - - value0 - The VBUS voltage is below the Session Valid threshold - 0 - - - value1 - The VBUS voltage is above the Session Valid threshold - 0x1 - - - - - AVALID - A-Device Session Valid status A-Device Session Valid status, determined by the Session Valid comparator - 2 - 1 - read-only - - - value0 - The VBUS voltage is below the Session Valid threshold - 0 - - - value1 - The VBUS voltage is above the Session Valid threshold - 0x1 - - - - - VBUS_VALID - VBUS voltage status This bit field shows the result of VBUS_VALID detection for the USB1_VBUS pin - 3 - 1 - read-only - - - value0 - VBUS is below the comparator threshold - 0 - - - value1 - VBUS is above the comparator threshold - 0x1 - - - - - VBUS_VALID_3V - VBUS_VALID_3V detector status The VBUS_VALID_3V detector has a lower threshold for the voltage on the USB1_VBUS pin than either the Session Valid or VBUS_VALID comparators - 4 - 1 - read-only - - - value0 - VBUS voltage is below VBUS_VALID_3V threshold - 0 - - - value1 - VBUS voltage is above VBUS_VALID_3V threshold - 0x1 - - - - - - - USB1_CHRG_DETECT - USB PHY Charger Detect Control Register - 0xE0 - 32 - read-write - 0x80180000 - 0xFFFFFFFF - - - PULLUP_DP - This bit is used to pull up DP, for digital charge detect. - 2 - 1 - read-write - - - BGR_IBIAS - USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector - 23 - 1 - read-write - - - value0 - Bias current is derived from the USB PHY internal current generator. - 0 - - - value1 - Bias current is derived from the reference generator of the bandgap. - 0x1 - - - - - - - USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register - 0xE4 - 32 - read-write - 0x80180000 - 0xFFFFFFFF - - - PULLUP_DP - This bit is used to pull up DP, for digital charge detect. - 2 - 1 - read-write - - - BGR_IBIAS - USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector - 23 - 1 - read-write - - - value0 - Bias current is derived from the USB PHY internal current generator. - 0 - - - value1 - Bias current is derived from the reference generator of the bandgap. - 0x1 - - - - - - - USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register - 0xE8 - 32 - read-write - 0x80180000 - 0xFFFFFFFF - - - PULLUP_DP - This bit is used to pull up DP, for digital charge detect. - 2 - 1 - read-write - - - BGR_IBIAS - USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector - 23 - 1 - read-write - - - value0 - Bias current is derived from the USB PHY internal current generator. - 0 - - - value1 - Bias current is derived from the reference generator of the bandgap. - 0x1 - - - - - - - USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register - 0xEC - 32 - read-write - 0x80180000 - 0xFFFFFFFF - - - PULLUP_DP - This bit is used to pull up DP, for digital charge detect. - 2 - 1 - read-write - - - BGR_IBIAS - USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector - 23 - 1 - read-write - - - value0 - Bias current is derived from the USB PHY internal current generator. - 0 - - - value1 - Bias current is derived from the reference generator of the bandgap. - 0x1 - - - - - - - USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register - 0xF0 - 32 - read-only - 0 - 0xFFFFFFFF - - - PLUG_CONTACT - Battery Charging Data Contact Detection phase output During the Data Contact Detection phase per the USB Battery Charging Specification Revision 1 - 0 - 1 - read-only - - - value0 - No USB cable attachment has been detected - 0 - - - value1 - A USB cable attachment between the device and host has been detected - 0x1 - - - - - CHRG_DETECTED - Battery Charging Primary Detection phase output During the USB Battery Charging Primary Detection phase using the USBHSDCD module, this bit field indicates whether a Standard Downstream Port or Charging Port was detected - 1 - 1 - read-only - - - value0 - Standard Downstream Port (SDP) has been detected - 0 - - - value1 - Charging Port has been detected - 0x1 - - - - - DM_STATE - Single ended receiver output for the USB_DM pin, from charger detection circuits. - 2 - 1 - read-only - - - value0 - USB_DM pin voltage is < 0.8V - 0 - - - value1 - USB_DM pin voltage is > 2.0V - 0x1 - - - - - DP_STATE - Single ended receiver output for the USB_DP pin, from charger detection circuits. - 3 - 1 - read-only - - - value0 - USB_DP pin voltage is < 0.8V - 0 - - - value1 - USB_DP pin voltage is > 2.0V - 0x1 - - - - - SECDET_DCP - Battery Charging Secondary Detection phase output During the USB Battery Charging Secondary Detection phase using the USBHSDCD module, this bit field indicates which kind of Charging Port was detected - 4 - 1 - read-only - - - value0 - Charging Downstream Port (CDP) has been detected - 0 - - - value1 - Downstream Charging Port (DCP) has been detected - 0x1 - - - @@ -43745,6 +40722,20 @@ SPDX-License-Identifier: BSD-3-Clause 0xA000402 0xFFFFFFFF + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins @@ -43775,6 +40766,20 @@ SPDX-License-Identifier: BSD-3-Clause 0xA000402 0xFFFFFFFF + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins @@ -43805,6 +40810,20 @@ SPDX-License-Identifier: BSD-3-Clause 0xA000402 0xFFFFFFFF + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins @@ -43835,6 +40854,20 @@ SPDX-License-Identifier: BSD-3-Clause 0xA000402 0xFFFFFFFF + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins @@ -43887,24 +40920,6 @@ SPDX-License-Identifier: BSD-3-Clause - - ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed - 0x4 - 32 - read-only - 0 - 0xFFFFFFFF - - - ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed. - 0 - 32 - read-only - - - COUNTER_VAL no description available @@ -43960,20 +40975,6 @@ SPDX-License-Identifier: BSD-3-Clause 3 read-write - - DIS_ENH_ENTR_REFILL - Disable 'enhanced entropy refill' feature, which is enabled by default when 'mode' > 00. - 8 - 1 - read-write - - - FORCE_ENTR_SPREADING - Forces entropy spreading (interactions between RNGs) even when 'clock_sel'>0. - 9 - 1 - read-write - @@ -44033,63 +41034,6 @@ SPDX-License-Identifier: BSD-3-Clause - - MISC_CFG - no description available - 0x18 - 32 - read-write - 0 - 0x3 - - - AES_RESEED - If set, ENCRYPTED_NUMBER generation becomes predictable, provided all secrets and current internal state are known: independant from entropy source. - 0 - 1 - read-write - - - AES_DT_CFG - Set this bit to re-seed AES. - 1 - 1 - read-write - - - - - POWERDOWN - Powerdown mode (standard but certainly useless here) - 0xFF4 - 32 - read-write - 0 - 0x80000003 - - - SOFT_RESET - Request softreset that will go low automaticaly after acknowledge from CORE. - 0 - 1 - read-write - - - FORCE_SOFT_RESET - When used with softreset it forces CORE_RESETN to low on acknowledge from CORE. - 1 - 1 - read-write - - - POWERDOWN - When set all accesses to standard registers are blocked. - 31 - 1 - read-write - - - MODULEID IP identifier @@ -44260,7 +41204,7 @@ SPDX-License-Identifier: BSD-3-Clause error - Quiddikey is in the Error state and no operations can be performed + PUF is in the Error state and no operations can be performed 2 1 read-only @@ -44452,7 +41396,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - KEYOUT + VERSION Version of the PUF module. 0 32 @@ -44655,7 +41599,7 @@ SPDX-License-Identifier: BSD-3-Clause KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." 4 2 read-write @@ -44701,7 +41645,7 @@ SPDX-License-Identifier: BSD-3-Clause KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." + "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." 6 2 read-write @@ -44756,13 +41700,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x8000AAAA 0xC000FFFF - - IDX0 - Use to block PUF index 0 - 0 - 2 - read-write - IDX1 Use to block PUF index 1 @@ -44991,13 +41928,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xAAAA 0xFFFF - - IDX0 - Use to block PUF index 0 - 0 - 2 - read-write - IDX1 Use to block PUF index 1 @@ -45115,8 +42045,8 @@ SPDX-License-Identifier: BSD-3-Clause 5 0x4 0,1,2,3,4 - LUT_INP%s - LUT0 input 0 MUX + LUT_INP_MUX%s + LUTn input x MUX 0 32 read-write @@ -45124,8 +42054,8 @@ SPDX-License-Identifier: BSD-3-Clause 0x3F - LUT_INP - Selects the input source to be connected to LUT0 input0. + LUTn_INPx + Selects the input source to be connected to LUT0 input0. For each LUT, the slot associated with the output from LUTn itself is tied low. 0 6 read-write @@ -45319,7 +42249,7 @@ SPDX-License-Identifier: BSD-3-Clause 26 0x4 LUT_TRUTH[%s] - Specifies the Truth Table contents for LUT0 + Specifies the Truth Table contents for LUTLUTn 0x800 32 read-write @@ -45327,7 +42257,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - TRUTH_TABLE + LUTn_TRUTH Specifies the Truth Table contents for LUT0.. 0 32 @@ -45354,7 +42284,7 @@ SPDX-License-Identifier: BSD-3-Clause - WAKEINT + WAKEINT_CTRL Wakeup interrupt control for PLU 0x904 32 @@ -45371,7 +42301,7 @@ SPDX-License-Identifier: BSD-3-Clause FILTER_MODE - control input of the PLU, add filtering for glitch + control input of the PLU, add filtering for glitch. 8 2 read-write @@ -45400,10 +42330,27 @@ SPDX-License-Identifier: BSD-3-Clause FILTER_CLKSEL - hclk is divided by 2**filter_clksel + hclk is divided by 2**filter_clksel. 10 2 read-write + + + FRO1MHZ + Selects the 1 MHz low-power oscillator as the filter clock. + 0 + + + FRO12MHZ + Selects the 12 Mhz FRO as the filter clock. + 0x1 + + + OTHER_CLOCK + Selects a third filter clock source, if provided. + 0x2 + + LATCH_ENABLE @@ -45426,7 +42373,7 @@ SPDX-License-Identifier: BSD-3-Clause 8 0x4 OUTPUT_MUX[%s] - Selects the source to be connected to PLU Output 0 + Selects the source to be connected to PLU Output OUTPUT_n 0xC00 32 read-write @@ -45604,7 +42551,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x40082000 0 - 0x5DC + 0x56C registers @@ -45926,7 +42873,7 @@ SPDX-License-Identifier: BSD-3-Clause - 30 + 23 0x10 CHANNEL[%s] no description available @@ -46362,7 +43309,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x400A7000 0 - 0x5DC + 0x49C registers @@ -47132,10 +44079,50 @@ SPDX-License-Identifier: BSD-3-Clause Falling edges on input 3. 0x7 + + INPUT_4_RISING_EDGES + Rising edges on input 4. + 0x8 + + + INPUT_4_FALLING_EDGE + Falling edges on input 4. + 0x9 + + + INPUT_5_RISING_EDGES + Rising edges on input 5. + 0xA + + + INPUT_5_FALLING_EDGE + Falling edges on input 5. + 0xB + + + INPUT_6_RISING_EDGES + Rising edges on input 6. + 0xC + + + INPUT_6_FALLING_EDGE + Falling edges on input 6. + 0xD + + + INPUT_7_RISING_EDGES + Rising edges on input 7. + 0xE + + + INPUT_7_FALLING_EDGE + Falling edges on input 7. + 0xF + - NORELAOD_L + NORELOAD_L A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 7 1 @@ -48589,7 +45576,7 @@ SPDX-License-Identifier: BSD-3-Clause - DMA0REQUEST + DMAREQ0 SCT DMA request 0 register 0x5C 32 @@ -48621,7 +45608,7 @@ SPDX-License-Identifier: BSD-3-Clause - DMA1REQUEST + DMAREQ1 SCT DMA request 1 register 0x60 32 @@ -48739,7 +45726,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP0 + CAP0 SCT capture register of capture channel CAP_MATCH 0x100 @@ -48765,7 +45752,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH0 + MATCH0 SCT match value register of match channels CAP_MATCH 0x100 @@ -48791,7 +45778,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP1 + CAP1 SCT capture register of capture channel CAP_MATCH 0x104 @@ -48817,7 +45804,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH1 + MATCH1 SCT match value register of match channels CAP_MATCH 0x104 @@ -48843,7 +45830,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP2 + CAP2 SCT capture register of capture channel CAP_MATCH 0x108 @@ -48869,7 +45856,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH2 + MATCH2 SCT match value register of match channels CAP_MATCH 0x108 @@ -48895,7 +45882,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP3 + CAP3 SCT capture register of capture channel CAP_MATCH 0x10C @@ -48921,7 +45908,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH3 + MATCH3 SCT match value register of match channels CAP_MATCH 0x10C @@ -48947,7 +45934,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP4 + CAP4 SCT capture register of capture channel CAP_MATCH 0x110 @@ -48973,7 +45960,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH4 + MATCH4 SCT match value register of match channels CAP_MATCH 0x110 @@ -48999,7 +45986,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP5 + CAP5 SCT capture register of capture channel CAP_MATCH 0x114 @@ -49025,7 +46012,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH5 + MATCH5 SCT match value register of match channels CAP_MATCH 0x114 @@ -49051,7 +46038,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP6 + CAP6 SCT capture register of capture channel CAP_MATCH 0x118 @@ -49077,7 +46064,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH6 + MATCH6 SCT match value register of match channels CAP_MATCH 0x118 @@ -49103,7 +46090,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP7 + CAP7 SCT capture register of capture channel CAP_MATCH 0x11C @@ -49129,7 +46116,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH7 + MATCH7 SCT match value register of match channels CAP_MATCH 0x11C @@ -49155,7 +46142,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP8 + CAP8 SCT capture register of capture channel CAP_MATCH 0x120 @@ -49181,7 +46168,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH8 + MATCH8 SCT match value register of match channels CAP_MATCH 0x120 @@ -49207,7 +46194,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP9 + CAP9 SCT capture register of capture channel CAP_MATCH 0x124 @@ -49233,7 +46220,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH9 + MATCH9 SCT match value register of match channels CAP_MATCH 0x124 @@ -49259,7 +46246,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP10 + CAP10 SCT capture register of capture channel CAP_MATCH 0x128 @@ -49285,7 +46272,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH10 + MATCH10 SCT match value register of match channels CAP_MATCH 0x128 @@ -49311,7 +46298,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP11 + CAP11 SCT capture register of capture channel CAP_MATCH 0x12C @@ -49337,7 +46324,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH11 + MATCH11 SCT match value register of match channels CAP_MATCH 0x12C @@ -49363,7 +46350,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP12 + CAP12 SCT capture register of capture channel CAP_MATCH 0x130 @@ -49389,7 +46376,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH12 + MATCH12 SCT match value register of match channels CAP_MATCH 0x130 @@ -49415,7 +46402,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP13 + CAP13 SCT capture register of capture channel CAP_MATCH 0x134 @@ -49441,7 +46428,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH13 + MATCH13 SCT match value register of match channels CAP_MATCH 0x134 @@ -49467,7 +46454,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP14 + CAP14 SCT capture register of capture channel CAP_MATCH 0x138 @@ -49493,7 +46480,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH14 + MATCH14 SCT match value register of match channels CAP_MATCH 0x138 @@ -49519,7 +46506,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP15 + CAP15 SCT capture register of capture channel CAP_MATCH 0x13C @@ -49545,7 +46532,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH15 + MATCH15 SCT match value register of match channels CAP_MATCH 0x13C @@ -49571,7 +46558,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL0 + CAPCTRL0 SCT capture control register CAPCTRL_MATCHREL 0x200 @@ -49597,7 +46584,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL0 + MATCHREL0 SCT match reload value register CAPCTRL_MATCHREL 0x200 @@ -49623,7 +46610,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL1 + CAPCTRL1 SCT capture control register CAPCTRL_MATCHREL 0x204 @@ -49649,7 +46636,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL1 + MATCHREL1 SCT match reload value register CAPCTRL_MATCHREL 0x204 @@ -49675,7 +46662,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL2 + CAPCTRL2 SCT capture control register CAPCTRL_MATCHREL 0x208 @@ -49701,7 +46688,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL2 + MATCHREL2 SCT match reload value register CAPCTRL_MATCHREL 0x208 @@ -49727,7 +46714,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL3 + CAPCTRL3 SCT capture control register CAPCTRL_MATCHREL 0x20C @@ -49753,7 +46740,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL3 + MATCHREL3 SCT match reload value register CAPCTRL_MATCHREL 0x20C @@ -49779,7 +46766,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL4 + CAPCTRL4 SCT capture control register CAPCTRL_MATCHREL 0x210 @@ -49805,7 +46792,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL4 + MATCHREL4 SCT match reload value register CAPCTRL_MATCHREL 0x210 @@ -49831,7 +46818,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL5 + CAPCTRL5 SCT capture control register CAPCTRL_MATCHREL 0x214 @@ -49857,7 +46844,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL5 + MATCHREL5 SCT match reload value register CAPCTRL_MATCHREL 0x214 @@ -49883,7 +46870,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL6 + CAPCTRL6 SCT capture control register CAPCTRL_MATCHREL 0x218 @@ -49909,7 +46896,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL6 + MATCHREL6 SCT match reload value register CAPCTRL_MATCHREL 0x218 @@ -49935,7 +46922,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL7 + CAPCTRL7 SCT capture control register CAPCTRL_MATCHREL 0x21C @@ -49961,7 +46948,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL7 + MATCHREL7 SCT match reload value register CAPCTRL_MATCHREL 0x21C @@ -49987,7 +46974,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL8 + CAPCTRL8 SCT capture control register CAPCTRL_MATCHREL 0x220 @@ -50013,7 +47000,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL8 + MATCHREL8 SCT match reload value register CAPCTRL_MATCHREL 0x220 @@ -50039,7 +47026,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL9 + CAPCTRL9 SCT capture control register CAPCTRL_MATCHREL 0x224 @@ -50065,7 +47052,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL9 + MATCHREL9 SCT match reload value register CAPCTRL_MATCHREL 0x224 @@ -50091,7 +47078,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL10 + CAPCTRL10 SCT capture control register CAPCTRL_MATCHREL 0x228 @@ -50117,7 +47104,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL10 + MATCHREL10 SCT match reload value register CAPCTRL_MATCHREL 0x228 @@ -50143,7 +47130,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL11 + CAPCTRL11 SCT capture control register CAPCTRL_MATCHREL 0x22C @@ -50169,7 +47156,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL11 + MATCHREL11 SCT match reload value register CAPCTRL_MATCHREL 0x22C @@ -50195,7 +47182,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL12 + CAPCTRL12 SCT capture control register CAPCTRL_MATCHREL 0x230 @@ -50221,7 +47208,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL12 + MATCHREL12 SCT match reload value register CAPCTRL_MATCHREL 0x230 @@ -50247,7 +47234,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL13 + CAPCTRL13 SCT capture control register CAPCTRL_MATCHREL 0x234 @@ -50273,7 +47260,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL13 + MATCHREL13 SCT match reload value register CAPCTRL_MATCHREL 0x234 @@ -50299,7 +47286,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL14 + CAPCTRL14 SCT capture control register CAPCTRL_MATCHREL 0x238 @@ -50325,7 +47312,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL14 + MATCHREL14 SCT match reload value register CAPCTRL_MATCHREL 0x238 @@ -50351,7 +47338,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL15 + CAPCTRL15 SCT capture control register CAPCTRL_MATCHREL 0x23C @@ -50377,7 +47364,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL15 + MATCHREL15 SCT match reload value register CAPCTRL_MATCHREL 0x23C @@ -50405,11 +47392,11 @@ SPDX-License-Identifier: BSD-3-Clause 16 0x8 - EVENT[%s] + EV[%s] no description available 0x300 - STATE + EV_STATE SCT event state register 0 0 32 @@ -50427,7 +47414,7 @@ SPDX-License-Identifier: BSD-3-Clause - CTRL + EV_CTRL SCT event control register 0 0x4 32 @@ -50612,7 +47599,7 @@ SPDX-License-Identifier: BSD-3-Clause no description available 0x500 - SET + OUT_SET SCT output 0 set register 0 32 @@ -50630,7 +47617,7 @@ SPDX-License-Identifier: BSD-3-Clause - CLR + OUT_CLR SCT output 0 clear register 0x4 32 @@ -50828,21 +47815,21 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - Aperture - no description available + APERTURE + size aperture for the register port on the bus (APB or AHB). 0 8 read-only - Minor_Rev + MINOR_REV Minor revision of module implementation. 8 4 read-only - Major_Rev + MAJOR_REV Major revision of module implementation. 12 4 @@ -52244,9 +49231,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 - 0x4 - SLVADR[%s] + SLVADR0 Slave address register. 0x848 32 @@ -52301,6 +49286,117 @@ SPDX-License-Identifier: BSD-3-Clause + + SLVADR1 + Slave address register. + 0x84C + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + + + SLVADR2 + Slave address register. + 0x850 + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + + + SLVADR3 + Slave address register. + 0x854 + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + SLVQUAL0 Slave Qualification for address 0. @@ -52583,95 +49679,6 @@ SPDX-License-Identifier: BSD-3-Clause 14 - - 3 - 0x20 - SECCHANNEL[%s] - no description available - 0 - - PCFG1 - Configuration register 1 for channel pair - 0xC20 - 32 - read-write - 0 - 0x401 - - - PAIRENABLE - Enable for this channel pair.. - 0 - 1 - read-write - - - ONECHANNEL - Single channel mode. - 10 - 1 - read-write - - - - - PCFG2 - Configuration register 2 for channel pair - 0xC24 - 32 - read-write - 0 - 0x1FF0000 - - - POSITION - Data Position. - 16 - 9 - read-write - - - - - PSTAT - Status register for channel pair - 0xC28 - 32 - read-write - 0 - 0xF - - - BUSY - Busy status for this channel pair. - 0 - 1 - read-write - - - SLVFRMERR - Save Frame Error flag. - 1 - 1 - read-write - - - LR - Left/Right indication. - 2 - 1 - read-write - - - DATAPAUSED - Data Paused status flag. - 3 - 1 - read-only - - - - CFG1 Configuration register 1 for the primary channel pair. @@ -52863,25 +49870,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC55xx, this bit applies only to Flexcomm 6,7. - 11 - 1 - read-write - - - NORMAL - Normal operation, data is transferred to or from the Flexcomm FIFO. - 0 - - - DMIC_SUBSYSTEM - The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. - 0x1 - - - SCK_POL SCK polarity. @@ -53241,25 +50229,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - POPDBG - Pop FIFO for debug reads. - 18 - 1 - read-write - - - DO_NOT_POP - Debug reads of the FIFO do not pop the FIFO. - 0 - - - POP - A debug read will cause the FIFO to pop. - 0x1 - - - @@ -53679,6 +50648,24 @@ SPDX-License-Identifier: BSD-3-Clause + + FIFOSIZE + FIFO size register + 0xE48 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOSIZE + Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + 0 + 5 + read-only + + + ID I2S Module identification @@ -53689,21 +50676,21 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - Aperture + APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only - Minor_Rev + MINOR_REV Minor revision of module implementation, starting at 0. 8 4 read-only - Major_Rev + MAJOR_REV Major revision of module implementation, starting at 0. 12 4 @@ -54429,25 +51416,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - POPDBG - Pop FIFO for debug reads. - 18 - 1 - read-write - - - DO_NOT_POP - Debug reads of the FIFO do not pop the FIFO. - 0 - - - POP - A debug read will cause the FIFO to pop. - 0x1 - - - @@ -54764,7 +51732,7 @@ SPDX-License-Identifier: BSD-3-Clause FIFO write data. 0xE20 32 - read-write + write-only 0 0 @@ -55023,13 +51991,31 @@ SPDX-License-Identifier: BSD-3-Clause + + FIFOSIZE + FIFO size register + 0xE48 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOSIZE + Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + 0 + 5 + read-only + + + ID Peripheral identification register. 0xFFC 32 read-only - 0 + 0xE0201200 0xFFFFFFFF @@ -56193,25 +53179,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - POPDBG - Pop FIFO for debug reads. - 18 - 1 - read-write - - - DO_NOT_POP - Debug reads of the FIFO do not pop the FIFO. - 0 - - - POP - A debug read will cause the FIFO to pop. - 0x1 - - - @@ -56528,7 +53495,7 @@ SPDX-License-Identifier: BSD-3-Clause FIFO write data. 0xE20 32 - read-write + write-only 0 0 @@ -56619,6 +53586,24 @@ SPDX-License-Identifier: BSD-3-Clause + + FIFOSIZE + FIFO size register + 0xE48 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOSIZE + Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + 0 + 5 + read-only + + + ID Peripheral identification register. @@ -56872,16 +53857,15 @@ SPDX-License-Identifier: BSD-3-Clause GPIO General Purpose I/O (GPIO) GPIO - GPIO 0x4008C000 0 - 0x2490 + 0x2488 registers - 4 + 2 0x20 B[%s] no description available @@ -56908,7 +53892,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x80 W[%s] no description available @@ -56935,7 +53919,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 DIR[%s] Direction registers for all port GPIO pins @@ -56955,7 +53939,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 MASK[%s] Mask register for all port GPIO pins @@ -56975,7 +53959,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 PIN[%s] Port pin register for all port GPIO pins @@ -56995,7 +53979,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 MPIN[%s] Masked port register for all port GPIO pins @@ -57015,7 +53999,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 SET[%s] Write: Set register for port. Read: output bits for port @@ -57035,7 +54019,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 CLR[%s] Clear port for all port GPIO pins @@ -57055,7 +54039,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 NOT[%s] Toggle port for all port GPIO pins @@ -57075,7 +54059,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 DIRSET[%s] Set pin direction bits for port @@ -57089,13 +54073,13 @@ SPDX-License-Identifier: BSD-3-Clause DIRSETP Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. 0 - 29 + 32 write-only - 4 + 2 0x4 DIRCLR[%s] Clear pin direction bits for port @@ -57109,13 +54093,13 @@ SPDX-License-Identifier: BSD-3-Clause DIRCLRP Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. 0 - 29 + 32 write-only - 4 + 2 0x4 DIRNOT[%s] Toggle pin direction bits for port @@ -57129,24 +54113,13 @@ SPDX-License-Identifier: BSD-3-Clause DIRNOTP Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. 0 - 29 + 32 write-only - - SECGPIO - General Purpose I/O (GPIO) - GPIO - 0x400A8000 - - 0 - 0x2490 - registers - - USBHSD USB1 High-speed Device Controller @@ -57154,13 +54127,9 @@ SPDX-License-Identifier: BSD-3-Clause 0x40094000 0 - 0x40 + 0x38 registers - - USB1_UTMI - 46 - USB1 47 @@ -57207,13 +54176,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - FORCE_VBUS - If this bit is set to 1, the VBUS voltage indicators from the PHY are overruled. - 10 - 1 - read-write - LPM_SUP LPM Supported:. @@ -57314,10 +54276,42 @@ SPDX-License-Identifier: BSD-3-Clause PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2. + This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. 29 3 read-write + + + DISABLE + Test mode disabled. + 0 + + + TEST_J + Test_J. + 0x1 + + + TEST_K + Test_K. + 0x2 + + + TEST_SE0_NAK + Test_SE0_NAK. + 0x3 + + + TEST_PACKET + Test_Packet. + 0x4 + + + TEST_FORCE_ENABLE + Test_Force_Enable. + 0x5 + + @@ -57345,14 +54339,14 @@ SPDX-License-Identifier: BSD-3-Clause read-only - Minrev + MINREV Minor revision. 16 8 read-only - Majrev + MAJREV Major revision. 24 8 @@ -57680,59 +54674,6 @@ SPDX-License-Identifier: BSD-3-Clause - - ULPIDEBUG - UTMI/ULPI debug register - 0x3C - 32 - read-write - 0 - 0x83FFFFFF - - - PHY_ADDR - ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface. - 0 - 8 - read-write - - - PHY_WDATA - UTMI+ mode: Reserved. - 8 - 8 - read-write - - - PHY_RDATA - UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+. - 16 - 8 - read-write - - - PHY_RW - UTMI+ mode: Reserved. - 24 - 1 - read-write - - - PHY_ACCESS - Software writes this bit to one to start a read or write operation. - 25 - 1 - read-write - - - PHY_MODE - This bit indicates if the interface between the controller is UTMI+ or ULPI. - 31 - 1 - read-write - - - @@ -59328,9 +56269,9 @@ SPDX-License-Identifier: BSD-3-Clause - DGBMAILBOX + DBGMAILBOX MCU Debugger Mailbox - DGBMAILBOX + DBGMAILBOX 0x4009C000 0 @@ -68423,7 +65364,7 @@ SPDX-License-Identifier: BSD-3-Clause The content of this register is updated by HC after a periodic ED is processed. 4 28 - read-write + read-only @@ -68513,7 +65454,7 @@ SPDX-License-Identifier: BSD-3-Clause DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. 4 28 - read-write + read-only @@ -68563,14 +65504,14 @@ SPDX-License-Identifier: BSD-3-Clause FrameRemaining This counter is decremented at each bit time. 0 14 - read-write + read-only FRT FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. 31 1 - read-write + read-only @@ -68588,7 +65529,7 @@ SPDX-License-Identifier: BSD-3-Clause FrameNumber This is incremented when HcFmRemaining is re-loaded. 0 16 - read-write + read-only @@ -68905,10 +65846,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x54 registers - - USB1_UTMI - 46 - USB1 47 @@ -68975,24 +65912,6 @@ SPDX-License-Identifier: BSD-3-Clause - - HCCPARAMS - Host Controller Capability Parameters - 0x8 - 32 - read-only - 0x20006 - 0xFFFFFFFF - - - LPMC - Link Power Management Capability. - 17 - 1 - read-only - - - FLADJ_FRINDEX Frame Length Adjustment @@ -69019,7 +65938,7 @@ SPDX-License-Identifier: BSD-3-Clause - ATL_PTD_BASE_ADDR + ATLPTD Memory base address where ATL PTD0 is stored 0x10 32 @@ -69044,7 +65963,7 @@ SPDX-License-Identifier: BSD-3-Clause - ISO_PTD_BASE_ADDR + ISOPTD Memory base address where ISO PTD0 is stored 0x14 32 @@ -69069,7 +65988,7 @@ SPDX-License-Identifier: BSD-3-Clause - INT_PTD_BASE_ADDR + INTPTD Memory base address where INT PTD0 is stored 0x18 32 @@ -69094,7 +66013,7 @@ SPDX-License-Identifier: BSD-3-Clause - DATA_PAYLOAD_BASE_ADDR + DATAPAYLOAD Memory base address that indicates the start of the data payload buffers 0x1C 32 @@ -69169,20 +66088,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - HIRD - Host-Initiated Resume Duration. - 24 - 4 - read-write - - - LPM_RWU - bRemoteWake field. - 28 - 1 - read-write - @@ -69363,13 +66268,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - SUS_L1 - Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a 1 and a non-zero value is specified in the Device Address field, the host controller will generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as well as L1 exit timing during any device or host-initiated resume. - 9 - 1 - read-write - LS Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. @@ -69412,24 +66310,10 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - SUS_STAT - These two bits are used by software to determine whether the most recent L1 suspend request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet - Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred. - 23 - 2 - read-write - - - DEV_ADD - Device Address for LPM tokens. - 25 - 7 - read-write - - ATL_PTD_DONE_MAP + ATLPTDD Done map for each ATL PTD 0x30 32 @@ -69447,7 +66331,7 @@ SPDX-License-Identifier: BSD-3-Clause - ATL_PTD_SKIP_MAP + ATLPTDS Skip map for each ATL PTD 0x34 32 @@ -69465,7 +66349,7 @@ SPDX-License-Identifier: BSD-3-Clause - ISO_PTD_DONE_MAP + ISOPTDD Done map for each ISO PTD 0x38 32 @@ -69483,7 +66367,7 @@ SPDX-License-Identifier: BSD-3-Clause - ISO_PTD_SKIP_MAP + ISOPTDS Skip map for each ISO PTD 0x3C 32 @@ -69501,7 +66385,7 @@ SPDX-License-Identifier: BSD-3-Clause - INT_PTD_DONE_MAP + INTPTDD Done map for each INT PTD 0x40 32 @@ -69519,7 +66403,7 @@ SPDX-License-Identifier: BSD-3-Clause - INT_PTD_SKIP_MAP + INTPTDS Skip map for each INT PTD 0x44 32 @@ -69537,7 +66421,7 @@ SPDX-License-Identifier: BSD-3-Clause - LAST_PTD_INUSE + LASTPTD Marks the last PTD in the list for ISO, INT and ATL 0x48 32 @@ -69568,59 +66452,6 @@ SPDX-License-Identifier: BSD-3-Clause - - UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY - 0x4C - 32 - read-write - 0 - 0x83FFFFFF - - - PHY_ADDR - UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface. - 0 - 8 - read-write - - - PHY_WDATA - UTMI+ mode: Reserved. - 8 - 8 - read-write - - - PHY_RDATA - UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register. - 16 - 8 - read-write - - - PHY_RW - UTMI+ mode: Reserved. - 24 - 1 - read-write - - - PHY_ACCESS - Software writes this bit to one to start a read or write operation. - 25 - 1 - read-write - - - PHY_MODE - This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes, this bit is RW by SW. - 31 - 1 - read-write - - - PORTMODE Controls the port if it is attached to the host block or the device block @@ -69630,20 +66461,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x40000 0xD0101 - - ID0 - Port 0 ID pin value. - 0 - 1 - read-write - - - ID0_EN - Port 0 ID pin pull-up enable. - 8 - 1 - read-write - DEV_ENABLE If this bit is set to one, one of the ports will behave as a USB device. @@ -69686,12 +66503,12 @@ SPDX-License-Identifier: BSD-3-Clause CTRL - Is control register to enable and operate Hash and Crypto + Control register to enable and operate Hash and Crypto 0 32 read-write 0 - 0x1317 + 0x3317 Mode @@ -69715,11 +66532,6 @@ SPDX-License-Identifier: BSD-3-Clause SHA2-256 is enabled 0x2 - - SHA2_512 - SHA2-512 is enabled (if available) - 0x3 - AES AES if available (see also CRYPTCFG register for more controls) @@ -69730,16 +66542,6 @@ SPDX-License-Identifier: BSD-3-Clause ICB-AES if available (see also CRYPTCFG register for more controls) 0x5 - - SALSA20 - Salsa20/20 if available (including XSalsa - see also CRYPTCFG register) - 0x6 - - - CHACHA20 - ChaCha20 if available (see also CRYPTCFG register for more controls) - 0x7 - @@ -69747,7 +66549,7 @@ SPDX-License-Identifier: BSD-3-Clause Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. 4 1 - read-write + write-only START @@ -69827,7 +66629,7 @@ SPDX-License-Identifier: BSD-3-Clause - DIGEST_aka_OUTDATA + DIGEST For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled. 1 1 @@ -70026,7 +66828,7 @@ SPDX-License-Identifier: BSD-3-Clause MASTER - no description available + Enables mastering. 0 1 read-write @@ -70111,7 +66913,7 @@ SPDX-License-Identifier: BSD-3-Clause 8 0x4 - OUTDATA0[%s] + DIGEST0[%s] no description available 0x40 32 @@ -70120,7 +66922,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - DIGEST_OUTPUT + DIGEST One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. 0 32 @@ -70128,26 +66930,6 @@ SPDX-License-Identifier: BSD-3-Clause - - 8 - 0x4 - OUTDATA1[%s] - no description available - 0x60 - 32 - read-only - 0 - 0xFFFFFFFF - - - OUTPUT - One word of the 2nd half of the output when used. - 0 - 32 - read-only - - - CRYPTCFG Crypto settings for AES and Salsa and ChaCha @@ -70217,7 +66999,7 @@ SPDX-License-Identifier: BSD-3-Clause read-write - AESDECRYPT_0 + ENCRYPT Encrypt 0 @@ -70241,7 +67023,7 @@ SPDX-License-Identifier: BSD-3-Clause 0 - AESSECRET_1 + HIDDEN_WAY Secret key provided in hidden way by HW 0x1 @@ -70285,13 +67067,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - XSALSA - Is 1 if XSalsa 128b NONCE to be used vs. 64b - 17 - 1 - read-write - ICBSZ This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV. @@ -70382,13 +67157,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-only - - SHA512 - 1 if SHA2-512 included - 5 - 1 - read-only - AES 1 if AES 128 included @@ -70410,20 +67178,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-only - - SALSA - 1 if Salsa included - 9 - 1 - read-only - - - CHACHA - 1 if ChaCha included - 10 - 1 - read-only - ICB 1 if ICB over AES included @@ -70502,6 +67256,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x84 registers + + CASER + 55 + CTRL0 @@ -70535,7 +67293,7 @@ SPDX-License-Identifier: BSD-3-Clause ABOFF Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up 2 - 1 + 11 read-write @@ -71085,6 +67843,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x260 registers + + PQ + 57 + OUTBASE @@ -71677,6 +68439,1351 @@ SPDX-License-Identifier: BSD-3-Clause + + SECGPIO + General Purpose I/O (GPIO) + GPIO + 0x400A8000 + + 0 + 0x2484 + registers + + + + B0_0 + Byte pin registers for all port GPIO pins + 0 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_1 + Byte pin registers for all port GPIO pins + 0x1 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_2 + Byte pin registers for all port GPIO pins + 0x2 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_3 + Byte pin registers for all port GPIO pins + 0x3 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_4 + Byte pin registers for all port GPIO pins + 0x4 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_5 + Byte pin registers for all port GPIO pins + 0x5 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_6 + Byte pin registers for all port GPIO pins + 0x6 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_7 + Byte pin registers for all port GPIO pins + 0x7 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_8 + Byte pin registers for all port GPIO pins + 0x8 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_9 + Byte pin registers for all port GPIO pins + 0x9 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_10 + Byte pin registers for all port GPIO pins + 0xA + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_11 + Byte pin registers for all port GPIO pins + 0xB + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_12 + Byte pin registers for all port GPIO pins + 0xC + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_13 + Byte pin registers for all port GPIO pins + 0xD + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_14 + Byte pin registers for all port GPIO pins + 0xE + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_15 + Byte pin registers for all port GPIO pins + 0xF + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_16 + Byte pin registers for all port GPIO pins + 0x10 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_17 + Byte pin registers for all port GPIO pins + 0x11 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_18 + Byte pin registers for all port GPIO pins + 0x12 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_19 + Byte pin registers for all port GPIO pins + 0x13 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_20 + Byte pin registers for all port GPIO pins + 0x14 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_21 + Byte pin registers for all port GPIO pins + 0x15 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_22 + Byte pin registers for all port GPIO pins + 0x16 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_23 + Byte pin registers for all port GPIO pins + 0x17 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_24 + Byte pin registers for all port GPIO pins + 0x18 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_25 + Byte pin registers for all port GPIO pins + 0x19 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_26 + Byte pin registers for all port GPIO pins + 0x1A + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_27 + Byte pin registers for all port GPIO pins + 0x1B + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_28 + Byte pin registers for all port GPIO pins + 0x1C + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_29 + Byte pin registers for all port GPIO pins + 0x1D + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_30 + Byte pin registers for all port GPIO pins + 0x1E + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_31 + Byte pin registers for all port GPIO pins + 0x1F + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + W0_0 + Word pin registers for all port GPIO pins + 0x1000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_1 + Word pin registers for all port GPIO pins + 0x1004 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_2 + Word pin registers for all port GPIO pins + 0x1008 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_3 + Word pin registers for all port GPIO pins + 0x100C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_4 + Word pin registers for all port GPIO pins + 0x1010 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_5 + Word pin registers for all port GPIO pins + 0x1014 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_6 + Word pin registers for all port GPIO pins + 0x1018 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_7 + Word pin registers for all port GPIO pins + 0x101C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_8 + Word pin registers for all port GPIO pins + 0x1020 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_9 + Word pin registers for all port GPIO pins + 0x1024 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_10 + Word pin registers for all port GPIO pins + 0x1028 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_11 + Word pin registers for all port GPIO pins + 0x102C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_12 + Word pin registers for all port GPIO pins + 0x1030 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_13 + Word pin registers for all port GPIO pins + 0x1034 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_14 + Word pin registers for all port GPIO pins + 0x1038 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_15 + Word pin registers for all port GPIO pins + 0x103C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_16 + Word pin registers for all port GPIO pins + 0x1040 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_17 + Word pin registers for all port GPIO pins + 0x1044 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_18 + Word pin registers for all port GPIO pins + 0x1048 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_19 + Word pin registers for all port GPIO pins + 0x104C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_20 + Word pin registers for all port GPIO pins + 0x1050 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_21 + Word pin registers for all port GPIO pins + 0x1054 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_22 + Word pin registers for all port GPIO pins + 0x1058 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_23 + Word pin registers for all port GPIO pins + 0x105C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_24 + Word pin registers for all port GPIO pins + 0x1060 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_25 + Word pin registers for all port GPIO pins + 0x1064 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_26 + Word pin registers for all port GPIO pins + 0x1068 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_27 + Word pin registers for all port GPIO pins + 0x106C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_28 + Word pin registers for all port GPIO pins + 0x1070 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_29 + Word pin registers for all port GPIO pins + 0x1074 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_30 + Word pin registers for all port GPIO pins + 0x1078 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_31 + Word pin registers for all port GPIO pins + 0x107C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + DIR0 + Direction registers for all port GPIO pins + 0x2000 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIRP + Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. + 0 + 32 + read-write + + + + + MASK0 + Mask register for all port GPIO pins + 0x2080 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASKP + Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. + 0 + 32 + read-write + + + + + PIN0 + Port pin register for all port GPIO pins + 0x2100 + 32 + read-write + 0 + 0xFFFFFFFF + + + PORT + Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. + 0 + 32 + read-write + + + + + MPIN0 + Masked port register for all port GPIO pins + 0x2180 + 32 + read-write + 0 + 0xFFFFFFFF + + + MPORTP + Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. + 0 + 32 + read-write + + + + + SET0 + Write: Set register for port. Read: output bits for port + 0x2200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETP + Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. + 0 + 32 + read-write + + + + + CLR0 + Clear port for all port GPIO pins + 0x2280 + 32 + write-only + 0 + 0 + + + CLRP + Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. + 0 + 32 + write-only + + + + + NOT0 + Toggle port for all port GPIO pins + 0x2300 + 32 + write-only + 0 + 0 + + + NOTP + Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. + 0 + 32 + write-only + + + + + DIRSET0 + Set pin direction bits for port + 0x2380 + 32 + write-only + 0 + 0 + + + DIRSETP + Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. + 0 + 32 + write-only + + + + + DIRCLR0 + Clear pin direction bits for port + 0x2400 + 32 + write-only + 0 + 0 + + + DIRCLRP + Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. + 0 + 32 + write-only + + + + + DIRNOT0 + Toggle pin direction bits for port + 0x2480 + 32 + write-only + 0 + 0 + + + DIRNOTP + Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + 0 + 32 + write-only + + + + + AHB_SECURE_CTRL AHB secure controller @@ -74277,7 +72384,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - RAM0_RULE + RAM1_RULE Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 0 2 @@ -76265,8 +74372,8 @@ SPDX-License-Identifier: BSD-3-Clause - PMUX_RULE - Peripherals mux + INPUTMUX_RULE + Peripheral input multiplexing 24 2 read-write @@ -76489,46 +74596,8 @@ SPDX-License-Identifier: BSD-3-Clause - - EFUSE_RULE - eFUSE (One Time Programmable) memory controller - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. - 0x10C - 32 - write-only - 0 - 0xFFFFFFFF - SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. @@ -76891,7 +74960,7 @@ SPDX-License-Identifier: BSD-3-Clause - PUFF_RULE + PUF_RULE PUF 12 2 @@ -76951,7 +75020,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB0_0_SLAVE_RULE + SEC_CTRL_AHB_PORT8_SLAVE0_RULE Security access rules for AHB peripherals. 0x120 32 @@ -77107,7 +75176,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB0_1_SLAVE_RULE + SEC_CTRL_AHB_PORT8_SLAVE1_RULE Security access rules for AHB peripherals. 0x124 32 @@ -77263,7 +75332,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB1_0_SLAVE_RULE + SEC_CTRL_AHB_PORT9_SLAVE0_RULE Security access rules for AHB peripherals. 0x130 32 @@ -77390,7 +75459,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB1_1_SLAVE_RULE + SEC_CTRL_AHB_PORT9_SLAVE1_RULE Security access rules for AHB peripherals. 0x134 32 @@ -77517,7 +75586,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB2_0_SLAVE_RULE + SEC_CTRL_AHB_PORT10_SLAVE0_RULE Security access rules for AHB peripherals. 0x140 32 @@ -77672,7 +75741,7 @@ SPDX-License-Identifier: BSD-3-Clause PQ_RULE - Power Quad (CM33 processor hardware accelerator) + Power Quad (CPU0 processor hardware accelerator) 24 2 read-write @@ -77731,7 +75800,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB2_1_SLAVE_RULE + SEC_CTRL_AHB_PORT10_SLAVE1_RULE Security access rules for AHB peripherals. 0x144 32 @@ -77800,7 +75869,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB2_0_MEM_RULE + SEC_CTRL_AHB_SEC_CTRL_MEM_RULE Security access rules for AHB_SEC_CTRL_AHB. 0x150 32 @@ -78097,7 +76166,7 @@ SPDX-License-Identifier: BSD-3-Clause 12 0x4 sec_vio_addr[%s] - most recent security violation address for AHB layer n + most recent security violation address for AHB port n 0xE00 32 read-only @@ -78106,7 +76175,7 @@ SPDX-License-Identifier: BSD-3-Clause SEC_VIO_ADDR - security violation address for AHB layer + security violation address for AHB port 0 32 read-only @@ -78117,7 +76186,7 @@ SPDX-License-Identifier: BSD-3-Clause 12 0x4 sec_vio_misc_info[%s] - most recent security violation miscellaneous information for AHB layer n + most recent security violation miscellaneous information for AHB port n 0xE80 32 read-only @@ -78246,7 +76315,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID0 - violation information valid flag for AHB layer 0. Write 1 to clear. + violation information valid flag for AHB port 0. Write 1 to clear. 0 1 read-write @@ -78265,7 +76334,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID1 - violation information valid flag for AHB layer 1. Write 1 to clear. + violation information valid flag for AHB port 1. Write 1 to clear. 1 1 read-write @@ -78284,7 +76353,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID2 - violation information valid flag for AHB layer 2. Write 1 to clear. + violation information valid flag for AHB port 2. Write 1 to clear. 2 1 read-write @@ -78303,7 +76372,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID3 - violation information valid flag for AHB layer 3. Write 1 to clear. + violation information valid flag for AHB port 3. Write 1 to clear. 3 1 read-write @@ -78322,7 +76391,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID4 - violation information valid flag for AHB layer 4. Write 1 to clear. + violation information valid flag for AHB port 4. Write 1 to clear. 4 1 read-write @@ -78341,7 +76410,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID5 - violation information valid flag for AHB layer 5. Write 1 to clear. + violation information valid flag for AHB port 5. Write 1 to clear. 5 1 read-write @@ -78360,7 +76429,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID6 - violation information valid flag for AHB layer 6. Write 1 to clear. + violation information valid flag for AHB port 6. Write 1 to clear. 6 1 read-write @@ -78379,7 +76448,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID7 - violation information valid flag for AHB layer 7. Write 1 to clear. + violation information valid flag for AHB port 7. Write 1 to clear. 7 1 read-write @@ -78398,7 +76467,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID8 - violation information valid flag for AHB layer 8. Write 1 to clear. + violation information valid flag for AHB port 8. Write 1 to clear. 8 1 read-write @@ -78417,7 +76486,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID9 - violation information valid flag for AHB layer 9. Write 1 to clear. + violation information valid flag for AHB port 9. Write 1 to clear. 9 1 read-write @@ -78436,7 +76505,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID10 - violation information valid flag for AHB layer 10. Write 1 to clear. + violation information valid flag for AHB port 10. Write 1 to clear. 10 1 read-write @@ -78455,7 +76524,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID11 - violation information valid flag for AHB layer 11. Write 1 to clear. + violation information valid flag for AHB port 11. Write 1 to clear. 11 1 read-write @@ -80178,7 +78247,7 @@ SPDX-License-Identifier: BSD-3-Clause - ACMP_CAPT0_IRQ + ACMP_IRQ Analog Comparator interrupt. 24 1 @@ -80255,7 +78324,7 @@ SPDX-License-Identifier: BSD-3-Clause USB0_IRQ - USB High Speed Controller interrupt. + USB Full Speed Controller interrupt. 28 1 read-write @@ -80607,8 +78676,8 @@ SPDX-License-Identifier: BSD-3-Clause - USB1_UTMI_IRQ - USB High Speed Controller UTMI interrupt. + USB1_PHY_IRQ + USB High Speed PHY Controller interrupt. 14 1 read-write @@ -80797,7 +78866,7 @@ SPDX-License-Identifier: BSD-3-Clause - QDDKEY_IRQ + PUFKEY_IRQ PUF interrupt. 24 1 @@ -80971,8 +79040,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - MCM33C - Micro-CM33 (CPU1) Code bus. + CPU1C + Micro-Cortex M33 (CPU1) Code bus. 4 2 read-write @@ -81000,8 +79069,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33S - Micro-CM33 (CPU1) System bus. + CPU1S + Micro-Cortex M33 (CPU1) System bus. 6 2 read-write @@ -81262,8 +79331,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - MCM33C - Micro-CM33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33C) + CPU1C + Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) 4 2 read-write @@ -81291,8 +79360,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33S - Micro-CM33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33S) + CPU1S + Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) 6 2 read-write @@ -81544,8 +79613,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_LOCK_REG - Miscalleneous control signals for in CM33 (CPU0) + CPU0_LOCK_REG + Miscalleneous control signals for in Cortex M33 (CPU0) 0xFEC 32 read-write @@ -81554,7 +79623,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_NS_VTOR - CM33 (CPU0) VTOR_NS register write-lock. + Cortex M33 (CPU0) VTOR_NS register write-lock. 0 2 read-write @@ -81573,7 +79642,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_NS_MPU - CM33 (CPU0) non-secure MPU register write-lock. + Cortex M33 (CPU0) non-secure MPU register write-lock. 2 2 read-write @@ -81592,7 +79661,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_S_VTAIRCR - CM33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. 4 2 read-write @@ -81611,7 +79680,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_S_MPU - CM33 (CPU0) Secure MPU registers write-lock. + Cortex M33 (CPU0) Secure MPU registers write-lock. 6 2 read-write @@ -81630,7 +79699,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_SAU - CM33 (CPU0) SAU registers write-lock. + Cortex M33 (CPU0) SAU registers write-lock. 8 2 read-write @@ -81648,8 +79717,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_LOCK_REG_LOCK - CM33_LOCK_REG write-lock. + CPU0_LOCK_REG_LOCK + CPU0_LOCK_REG write-lock. 30 2 read-write @@ -81669,8 +79738,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_LOCK_REG - Miscalleneous control signals for in micro-CM33 (CPU1) + CPU1_LOCK_REG + Miscalleneous control signals for in micro-Cortex M33 (CPU1) 0xFF0 32 read-write @@ -81679,7 +79748,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_NS_VTOR - micro-CM33 (CPU1) VTOR_NS register write-lock. + micro-Cortex M33 (CPU1) VTOR_NS register write-lock. 0 2 read-write @@ -81698,7 +79767,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_NS_MPU - micro-CM33 (CPU1) non-secure MPU register write-lock. + micro-Cortex M33 (CPU1) non-secure MPU register write-lock. 2 2 read-write @@ -81716,8 +79785,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_LOCK_REG_LOCK - MCM33_LOCK_REG write-lock. + CPU1_LOCK_REG_LOCK + CPU1_LOCK_REG write-lock. 30 2 read-write @@ -81747,7 +79816,7 @@ SPDX-License-Identifier: BSD-3-Clause WRITE_LOCK - write lock. + Write lock. 0 2 read-write @@ -81766,7 +79835,7 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. + Enable secure check for AHB matrix. 2 2 read-write @@ -81785,7 +79854,7 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. + Enable secure privilege check for AHB matrix. 4 2 read-write @@ -81804,7 +79873,7 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. + Enable non-secure privilege check for AHB matrix. 6 2 read-write @@ -81910,7 +79979,7 @@ SPDX-License-Identifier: BSD-3-Clause WRITE_LOCK - write lock. + Write lock. 0 2 read-write @@ -81929,14 +79998,14 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. + Enable secure check for AHB matrix. 2 2 read-write ENABLE - Restricted mode. + Enabled (restricted mode) 0x1 @@ -81948,14 +80017,14 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. + Enable secure privilege check for AHB matrix. 4 2 read-write ENABLE - Restricted mode. + Enabled (restricted mode) 0x1 @@ -81967,14 +80036,14 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. + Enable non-secure privilege check for AHB matrix. 6 2 read-write ENABLE - Restricted mode. + Enabled (restricted mode) 0x1 @@ -86227,7 +84296,7 @@ SPDX-License-Identifier: BSD-3-Clause Software Trigger Interrupt Register 0xE00 32 - read-write + write-only 0 0xFFFFFFFF @@ -87061,7 +85130,7 @@ SPDX-License-Identifier: BSD-3-Clause - SAU_CTRL + CTRL Security Attribution Unit Control Register 0xD0 32 @@ -87110,7 +85179,7 @@ SPDX-License-Identifier: BSD-3-Clause - SAU_TYPE + TYPE Security Attribution Unit Type Register 0xD4 32 @@ -87128,7 +85197,7 @@ SPDX-License-Identifier: BSD-3-Clause - SAU_RNR + RNR Security Attribution Unit Region Number Register 0xD8 32 @@ -87146,7 +85215,7 @@ SPDX-License-Identifier: BSD-3-Clause - SAU_RBAR + RBAR Security Attribution Unit Region Base Address Register 0xDC 32 @@ -87164,7 +85233,7 @@ SPDX-License-Identifier: BSD-3-Clause - SAU_RLAR + RLAR Security Attribution Unit Region Limit Address Register 0xE0 32 diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h index f9c2d65e17..926c9857a0 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core0_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### -** Version: rev. 1.0, 2018-08-22 -** Build: b190418 +** Version: rev. 1.1, 2019-05-16 +** Build: b220303 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -18,6 +18,8 @@ ** Revisions: ** - rev. 1.0 (2018-08-22) ** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM ** ** ################################################################### */ @@ -73,7 +75,7 @@ #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) /* @brief PUF availability on the SoC. */ #define FSL_FEATURE_SOC_PUF_COUNT (1) -/* @brief RNG1 availability on the SoC. */ +/* @brief LPC_RNG1 availability on the SoC. */ #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) /* @brief RTC availability on the SoC. */ #define FSL_FEATURE_SOC_RTC_COUNT (1) @@ -136,18 +138,66 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f) +/* @brief the buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) + +/* ANALOGCTRL module features */ + +/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) +/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) +/* @brief Has auxiliary bias(register AUX_BIAS). */ +#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) /* CASPER module features */ /* @brief Base address of the CASPER dedicated RAM */ #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) -/* @brief Interleaving of the CASPER dedicated RAM */ +/* @brief SW interleaving of the CASPER dedicated RAM */ #define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) +/* @brief CASPER dedicated RAM offset */ +#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) /* DMA module features */ /* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) /* @brief Align size of DMA descriptor */ #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) /* @brief DMA head link descriptor table align size */ @@ -155,6 +205,72 @@ /* FLEXCOMM module features */ +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM0 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM1 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM2 I2S INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM3 I2S INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM4 I2S INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM5 I2S INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM6 I2S INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) +/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) /* @brief I2S has DMIC interconnection */ #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) @@ -166,9 +282,9 @@ /* I2S module features */ /* @brief I2S support dual channel transfer. */ -#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) -/* @brief I2S has DMIC interconnection. */ -#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) /* IOCON module features */ @@ -190,10 +306,22 @@ /* @brief Number of connected outputs */ #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PMC module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* @brief WDT OSC does not support PD configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + /* POWERLIB module features */ -/* @brief LPC55XX's Powerlib API is different with other LPC series devices. */ -#define FSL_FEATURE_POWERLIB_LPC55XX_EXTEND (1) +/* @brief Powerlib API is different with other LPC series devices. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) /* POWERQUAD module features */ @@ -207,6 +335,10 @@ /* @brief the shift status value */ #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) +/* RTC module features */ + +/* No feature definitions */ + /* SCT module features */ /* @brief Number of events */ @@ -221,13 +353,13 @@ /* SDIF module features */ /* @brief FIFO depth, every location is a WORD */ -#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) +#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) /* @brief Max DMA buffer size */ -#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) +#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) /* @brief Max source clock in HZ */ -#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) +#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) /* @brief support 2 cards */ -#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) +#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) /* SECPINT module features */ @@ -236,18 +368,22 @@ /* SYSCON module features */ -/* @brief Pointer to ROM IAP entry functions */ -#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) /* @brief Flash page size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) /* @brief Flash sector size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) /* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592) +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120) /* @brief Has Power Down mode */ #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) /* @brief CCM_ANALOG availability on the SoC. */ #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) + +/* SYSCTL1 module features */ + +/* No feature definitions */ /* USB module features */ @@ -289,17 +425,23 @@ /* @brief USBHSH version */ #define FSL_FEATURE_USBHSH_VERSION (300) -/* UTICK module features */ +/* USBPHY module features */ -/* @brief UTICK does not support PD configure. */ -#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBPHY_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBPHY_EP_NUM (6) /* WWDT module features */ +/* @brief Has no RESET register. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) -/* @brief WWDT does not support power down configure */ -#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) #endif /* _LPC55S69_cm33_core0_FEATURES_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h index 734057d56b..0c92b268aa 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.h @@ -2,22 +2,22 @@ ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 ** LPC55S69JBD64_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b190430 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b211009 ** ** Abstract: ** CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -28,14 +28,16 @@ ** Revisions: ** - rev. 1.0 (2018-08-22) ** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM ** ** ################################################################### */ /*! * @file LPC55S69_cm33_core1.h - * @version 1.0 - * @date 2018-08-22 + * @version 1.1 + * @date 2019-05-16 * @brief CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 * * CMSIS Peripheral Access Layer for LPC55S69_cm33_core1 @@ -48,7 +50,7 @@ * compatible) */ #define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0000U +#define MCU_MEM_MAP_VERSION_MINOR 0x0001U /* ---------------------------------------------------------------------------- @@ -126,7 +128,7 @@ typedef enum IRQn { Reserved59_IRQn = 43, /**< Reserved interrupt */ Reserved60_IRQn = 44, /**< Reserved interrupt */ Reserved61_IRQn = 45, /**< Reserved interrupt */ - USB1_UTMI_IRQn = 46, /**< USB1_UTMI */ + USB1_PHY_IRQn = 46, /**< USB1_PHY */ USB1_IRQn = 47, /**< USB1 interrupt */ USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */ SEC_HYPERVISOR_CALL_IRQn = 49, /**< SEC_HYPERVISOR_CALL interrupt */ @@ -216,9 +218,9 @@ typedef enum _dma_request_source kDma0RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ kDma1RequestFlexcomm1Tx = 7U, /**< Flexcomm Interface 1 TX/I2C Master */ kDma0RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ - kDma1RequestFlexcomm2Rx = 8U, /**< Flexcomm Interface 2 RX/I2C Slave */ + kDma1RequestFlexcomm3Rx = 8U, /**< Flexcomm Interface 3 RX/I2C Slave */ kDma0RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ - kDma1RequestFlexcomm2Tx = 9U, /**< Flexcomm Interface 2 TX/I2C Master */ + kDma1RequestFlexcomm3Tx = 9U, /**< Flexcomm Interface 3 TX/I2C Master */ kDma0RequestFlexcomm2Rx = 10U, /**< Flexcomm Interface 2 RX/I2C Slave */ kDma0RequestFlexcomm2Tx = 11U, /**< Flexcomm Interface 2 TX/I2C Master */ kDma0RequestFlexcomm4Rx = 12U, /**< Flexcomm Interface 4 RX/I2C Slave */ @@ -292,7 +294,7 @@ typedef struct { __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ uint8_t RESERVED_1[12]; - __IO uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ + __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ __IO uint32_t TSTAT; /**< Trigger Status Register, offset: 0x38 */ uint8_t RESERVED_2[4]; __IO uint32_t OFSTRIM; /**< ADC Offset Trim Register, offset: 0x40 */ @@ -329,6 +331,7 @@ typedef struct { /*! @name VERID - Version ID Register */ /*! @{ */ + #define ADC_VERID_RES_MASK (0x1U) #define ADC_VERID_RES_SHIFT (0U) /*! RES - Resolution @@ -336,6 +339,7 @@ typedef struct { * 0b1..Up to 16-bit differential/16-bit single ended resolution supported. */ #define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + #define ADC_VERID_DIFFEN_MASK (0x2U) #define ADC_VERID_DIFFEN_SHIFT (1U) /*! DIFFEN - Differential Supported @@ -343,6 +347,7 @@ typedef struct { * 0b1..Differential operation supported. CMDLa[CTYPE] controls fields implemented. */ #define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + #define ADC_VERID_MVI_MASK (0x8U) #define ADC_VERID_MVI_SHIFT (3U) /*! MVI - Multi Vref Implemented @@ -350,6 +355,7 @@ typedef struct { * 0b1..Multiple voltage reference high (VREFH) inputs supported. */ #define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + #define ADC_VERID_CSW_MASK (0x70U) #define ADC_VERID_CSW_SHIFT (4U) /*! CSW - Channel Scale Width @@ -358,6 +364,7 @@ typedef struct { * 0b110..Channel scaling supported. 6-bit CSCALE control field. */ #define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + #define ADC_VERID_VR1RNGI_MASK (0x100U) #define ADC_VERID_VR1RNGI_SHIFT (8U) /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented @@ -365,6 +372,7 @@ typedef struct { * 0b1..Range control required. CFG[VREF1RNG] is implemented. */ #define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + #define ADC_VERID_IADCKI_MASK (0x200U) #define ADC_VERID_IADCKI_SHIFT (9U) /*! IADCKI - Internal ADC Clock implemented @@ -372,6 +380,7 @@ typedef struct { * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. */ #define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + #define ADC_VERID_CALOFSI_MASK (0x400U) #define ADC_VERID_CALOFSI_SHIFT (10U) /*! CALOFSI - Calibration Function Implemented @@ -379,6 +388,7 @@ typedef struct { * 0b1..Calibration Implemented. */ #define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + #define ADC_VERID_NUM_SEC_MASK (0x800U) #define ADC_VERID_NUM_SEC_SHIFT (11U) /*! NUM_SEC - Number of Single Ended Outputs Supported @@ -386,6 +396,7 @@ typedef struct { * 0b1..This design supports two simultanious single ended conversions. */ #define ADC_VERID_NUM_SEC(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_SEC_SHIFT)) & ADC_VERID_NUM_SEC_MASK) + #define ADC_VERID_NUM_FIFO_MASK (0x7000U) #define ADC_VERID_NUM_FIFO_SHIFT (12U) /*! NUM_FIFO - Number of FIFOs @@ -396,19 +407,29 @@ typedef struct { * 0b100..This design supports four result FIFOs. */ #define ADC_VERID_NUM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_NUM_FIFO_SHIFT)) & ADC_VERID_NUM_FIFO_MASK) + #define ADC_VERID_MINOR_MASK (0xFF0000U) #define ADC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number + */ #define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + #define ADC_VERID_MAJOR_MASK (0xFF000000U) #define ADC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number + */ #define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK) /*! @} */ /*! @name PARAM - Parameter Register */ /*! @{ */ + #define ADC_PARAM_TRIG_NUM_MASK (0xFFU) #define ADC_PARAM_TRIG_NUM_SHIFT (0U) +/*! TRIG_NUM - Trigger Number + */ #define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + #define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) #define ADC_PARAM_FIFOSIZE_SHIFT (8U) /*! FIFOSIZE - Result FIFO Depth @@ -420,16 +441,23 @@ typedef struct { * 0b01000000..Result FIFO depth = 64 datawords. */ #define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + #define ADC_PARAM_CV_NUM_MASK (0xFF0000U) #define ADC_PARAM_CV_NUM_SHIFT (16U) +/*! CV_NUM - Compare Value Number + */ #define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + #define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) #define ADC_PARAM_CMD_NUM_SHIFT (24U) +/*! CMD_NUM - Command Buffer Number + */ #define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) /*! @} */ /*! @name CTRL - ADC Control Register */ /*! @{ */ + #define ADC_CTRL_ADCEN_MASK (0x1U) #define ADC_CTRL_ADCEN_SHIFT (0U) /*! ADCEN - ADC Enable @@ -437,6 +465,7 @@ typedef struct { * 0b1..ADC is enabled. */ #define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + #define ADC_CTRL_RST_MASK (0x2U) #define ADC_CTRL_RST_SHIFT (1U) /*! RST - Software Reset @@ -444,6 +473,7 @@ typedef struct { * 0b1..ADC logic is reset. */ #define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + #define ADC_CTRL_DOZEN_MASK (0x4U) #define ADC_CTRL_DOZEN_SHIFT (2U) /*! DOZEN - Doze Enable @@ -451,6 +481,7 @@ typedef struct { * 0b1..ADC is disabled in Doze mode. */ #define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + #define ADC_CTRL_CAL_REQ_MASK (0x8U) #define ADC_CTRL_CAL_REQ_SHIFT (3U) /*! CAL_REQ - Auto-Calibration Request @@ -458,6 +489,7 @@ typedef struct { * 0b1..A request for auto-calibration has been made */ #define ADC_CTRL_CAL_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CAL_REQ_SHIFT)) & ADC_CTRL_CAL_REQ_MASK) + #define ADC_CTRL_CALOFS_MASK (0x10U) #define ADC_CTRL_CALOFS_SHIFT (4U) /*! CALOFS - Configure for offset calibration function @@ -465,6 +497,7 @@ typedef struct { * 0b1..Request for offset calibration function */ #define ADC_CTRL_CALOFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CALOFS_SHIFT)) & ADC_CTRL_CALOFS_MASK) + #define ADC_CTRL_RSTFIFO0_MASK (0x100U) #define ADC_CTRL_RSTFIFO0_SHIFT (8U) /*! RSTFIFO0 - Reset FIFO 0 @@ -472,6 +505,7 @@ typedef struct { * 0b1..FIFO 0 is reset. */ #define ADC_CTRL_RSTFIFO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO0_SHIFT)) & ADC_CTRL_RSTFIFO0_MASK) + #define ADC_CTRL_RSTFIFO1_MASK (0x200U) #define ADC_CTRL_RSTFIFO1_SHIFT (9U) /*! RSTFIFO1 - Reset FIFO 1 @@ -479,6 +513,7 @@ typedef struct { * 0b1..FIFO 1 is reset. */ #define ADC_CTRL_RSTFIFO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO1_SHIFT)) & ADC_CTRL_RSTFIFO1_MASK) + #define ADC_CTRL_CAL_AVGS_MASK (0x70000U) #define ADC_CTRL_CAL_AVGS_SHIFT (16U) /*! CAL_AVGS - Auto-Calibration Averages @@ -496,6 +531,7 @@ typedef struct { /*! @name STAT - ADC Status Register */ /*! @{ */ + #define ADC_STAT_RDY0_MASK (0x1U) #define ADC_STAT_RDY0_SHIFT (0U) /*! RDY0 - Result FIFO 0 Ready Flag @@ -503,6 +539,7 @@ typedef struct { * 0b1..Result FIFO 0 holding data above watermark level. */ #define ADC_STAT_RDY0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY0_SHIFT)) & ADC_STAT_RDY0_MASK) + #define ADC_STAT_FOF0_MASK (0x2U) #define ADC_STAT_FOF0_SHIFT (1U) /*! FOF0 - Result FIFO 0 Overflow Flag @@ -510,6 +547,7 @@ typedef struct { * 0b1..At least one result FIFO 0 overflow has occurred since the last time the flag was cleared. */ #define ADC_STAT_FOF0(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF0_SHIFT)) & ADC_STAT_FOF0_MASK) + #define ADC_STAT_RDY1_MASK (0x4U) #define ADC_STAT_RDY1_SHIFT (2U) /*! RDY1 - Result FIFO1 Ready Flag @@ -517,6 +555,7 @@ typedef struct { * 0b1..Result FIFO1 holding data above watermark level. */ #define ADC_STAT_RDY1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY1_SHIFT)) & ADC_STAT_RDY1_MASK) + #define ADC_STAT_FOF1_MASK (0x8U) #define ADC_STAT_FOF1_SHIFT (3U) /*! FOF1 - Result FIFO1 Overflow Flag @@ -524,6 +563,7 @@ typedef struct { * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. */ #define ADC_STAT_FOF1(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF1_SHIFT)) & ADC_STAT_FOF1_MASK) + #define ADC_STAT_TEXC_INT_MASK (0x100U) #define ADC_STAT_TEXC_INT_SHIFT (8U) /*! TEXC_INT - Interrupt Flag For High Priority Trigger Exception @@ -531,6 +571,7 @@ typedef struct { * 0b1..A trigger exception has occurred and is pending acknowledgement. */ #define ADC_STAT_TEXC_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TEXC_INT_SHIFT)) & ADC_STAT_TEXC_INT_MASK) + #define ADC_STAT_TCOMP_INT_MASK (0x200U) #define ADC_STAT_TCOMP_INT_SHIFT (9U) /*! TCOMP_INT - Interrupt Flag For Trigger Completion @@ -538,6 +579,7 @@ typedef struct { * 0b1..Trigger sequence has been completed and all data is stored in the associated FIFO. */ #define ADC_STAT_TCOMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TCOMP_INT_SHIFT)) & ADC_STAT_TCOMP_INT_MASK) + #define ADC_STAT_CAL_RDY_MASK (0x400U) #define ADC_STAT_CAL_RDY_SHIFT (10U) /*! CAL_RDY - Calibration Ready @@ -545,6 +587,7 @@ typedef struct { * 0b1..The ADC is calibrated. */ #define ADC_STAT_CAL_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CAL_RDY_SHIFT)) & ADC_STAT_CAL_RDY_MASK) + #define ADC_STAT_ADC_ACTIVE_MASK (0x800U) #define ADC_STAT_ADC_ACTIVE_SHIFT (11U) /*! ADC_ACTIVE - ADC Active @@ -552,6 +595,7 @@ typedef struct { * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. */ #define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + #define ADC_STAT_TRGACT_MASK (0xF0000U) #define ADC_STAT_TRGACT_SHIFT (16U) /*! TRGACT - Trigger Active @@ -561,6 +605,7 @@ typedef struct { * 0b0011-0b1111..Command (sequence) from the associated Trigger number is currently being executed. */ #define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + #define ADC_STAT_CMDACT_MASK (0xF000000U) #define ADC_STAT_CMDACT_SHIFT (24U) /*! CMDACT - Command Active @@ -574,6 +619,7 @@ typedef struct { /*! @name IE - Interrupt Enable Register */ /*! @{ */ + #define ADC_IE_FWMIE0_MASK (0x1U) #define ADC_IE_FWMIE0_SHIFT (0U) /*! FWMIE0 - FIFO 0 Watermark Interrupt Enable @@ -581,6 +627,7 @@ typedef struct { * 0b1..FIFO 0 watermark interrupts are enabled. */ #define ADC_IE_FWMIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE0_SHIFT)) & ADC_IE_FWMIE0_MASK) + #define ADC_IE_FOFIE0_MASK (0x2U) #define ADC_IE_FOFIE0_SHIFT (1U) /*! FOFIE0 - Result FIFO 0 Overflow Interrupt Enable @@ -588,6 +635,7 @@ typedef struct { * 0b1..FIFO 0 overflow interrupts are enabled. */ #define ADC_IE_FOFIE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE0_SHIFT)) & ADC_IE_FOFIE0_MASK) + #define ADC_IE_FWMIE1_MASK (0x4U) #define ADC_IE_FWMIE1_SHIFT (2U) /*! FWMIE1 - FIFO1 Watermark Interrupt Enable @@ -595,6 +643,7 @@ typedef struct { * 0b1..FIFO1 watermark interrupts are enabled. */ #define ADC_IE_FWMIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE1_SHIFT)) & ADC_IE_FWMIE1_MASK) + #define ADC_IE_FOFIE1_MASK (0x8U) #define ADC_IE_FOFIE1_SHIFT (3U) /*! FOFIE1 - Result FIFO1 Overflow Interrupt Enable @@ -602,6 +651,7 @@ typedef struct { * 0b1..At least one result FIFO1 overflow has occurred since the last time the flag was cleared. */ #define ADC_IE_FOFIE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE1_SHIFT)) & ADC_IE_FOFIE1_MASK) + #define ADC_IE_TEXC_IE_MASK (0x100U) #define ADC_IE_TEXC_IE_SHIFT (8U) /*! TEXC_IE - Trigger Exception Interrupt Enable @@ -609,6 +659,7 @@ typedef struct { * 0b1..Trigger exception interrupts are enabled. */ #define ADC_IE_TEXC_IE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_TEXC_IE_SHIFT)) & ADC_IE_TEXC_IE_MASK) + #define ADC_IE_TCOMP_IE_MASK (0xFFFF0000U) #define ADC_IE_TCOMP_IE_SHIFT (16U) /*! TCOMP_IE - Trigger Completion Interrupt Enable @@ -623,6 +674,7 @@ typedef struct { /*! @name DE - DMA Enable Register */ /*! @{ */ + #define ADC_DE_FWMDE0_MASK (0x1U) #define ADC_DE_FWMDE0_SHIFT (0U) /*! FWMDE0 - FIFO 0 Watermark DMA Enable @@ -630,6 +682,7 @@ typedef struct { * 0b1..DMA request enabled. */ #define ADC_DE_FWMDE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE0_SHIFT)) & ADC_DE_FWMDE0_MASK) + #define ADC_DE_FWMDE1_MASK (0x2U) #define ADC_DE_FWMDE1_SHIFT (1U) /*! FWMDE1 - FIFO1 Watermark DMA Enable @@ -641,6 +694,7 @@ typedef struct { /*! @name CFG - ADC Configuration Register */ /*! @{ */ + #define ADC_CFG_TPRICTRL_MASK (0x3U) #define ADC_CFG_TPRICTRL_SHIFT (0U) /*! TPRICTRL - ADC trigger priority control @@ -654,6 +708,7 @@ typedef struct { * 0b11..RESERVED */ #define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + #define ADC_CFG_PWRSEL_MASK (0x30U) #define ADC_CFG_PWRSEL_SHIFT (4U) /*! PWRSEL - Power Configuration Select @@ -663,6 +718,7 @@ typedef struct { * 0b11..Highest power setting. */ #define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + #define ADC_CFG_REFSEL_MASK (0xC0U) #define ADC_CFG_REFSEL_SHIFT (6U) /*! REFSEL - Voltage Reference Selection @@ -672,6 +728,7 @@ typedef struct { * 0b11..Reserved */ #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + #define ADC_CFG_TRES_MASK (0x100U) #define ADC_CFG_TRES_SHIFT (8U) /*! TRES - Trigger Resume Enable @@ -679,6 +736,7 @@ typedef struct { * 0b1..Trigger sequences interrupted by a high priority trigger exception will be automatically resumed or restarted. */ #define ADC_CFG_TRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TRES_SHIFT)) & ADC_CFG_TRES_MASK) + #define ADC_CFG_TCMDRES_MASK (0x200U) #define ADC_CFG_TCMDRES_SHIFT (9U) /*! TCMDRES - Trigger Command Resume @@ -686,6 +744,7 @@ typedef struct { * 0b1..Trigger sequences interrupted by a high priority trigger exception will be resumed from the command executing before the exception. */ #define ADC_CFG_TCMDRES(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TCMDRES_SHIFT)) & ADC_CFG_TCMDRES_MASK) + #define ADC_CFG_HPT_EXDI_MASK (0x400U) #define ADC_CFG_HPT_EXDI_SHIFT (10U) /*! HPT_EXDI - High Priority Trigger Exception Disable @@ -693,9 +752,13 @@ typedef struct { * 0b1..High priority trigger exceptions are disabled. */ #define ADC_CFG_HPT_EXDI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_HPT_EXDI_SHIFT)) & ADC_CFG_HPT_EXDI_MASK) + #define ADC_CFG_PUDLY_MASK (0xFF0000U) #define ADC_CFG_PUDLY_SHIFT (16U) +/*! PUDLY - Power Up Delay + */ #define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + #define ADC_CFG_PWREN_MASK (0x10000000U) #define ADC_CFG_PWREN_SHIFT (28U) /*! PWREN - ADC Analog Pre-Enable @@ -711,9 +774,13 @@ typedef struct { /*! @name PAUSE - ADC Pause Register */ /*! @{ */ + #define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) #define ADC_PAUSE_PAUSEDLY_SHIFT (0U) +/*! PAUSEDLY - Pause Delay + */ #define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + #define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) #define ADC_PAUSE_PAUSEEN_SHIFT (31U) /*! PAUSEEN - PAUSE Option Enable @@ -725,6 +792,7 @@ typedef struct { /*! @name SWTRIG - Software Trigger Register */ /*! @{ */ + #define ADC_SWTRIG_SWT0_MASK (0x1U) #define ADC_SWTRIG_SWT0_SHIFT (0U) /*! SWT0 - Software trigger 0 event @@ -732,6 +800,7 @@ typedef struct { * 0b1..Trigger 0 event generated. */ #define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + #define ADC_SWTRIG_SWT1_MASK (0x2U) #define ADC_SWTRIG_SWT1_SHIFT (1U) /*! SWT1 - Software trigger 1 event @@ -739,6 +808,7 @@ typedef struct { * 0b1..Trigger 1 event generated. */ #define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + #define ADC_SWTRIG_SWT2_MASK (0x4U) #define ADC_SWTRIG_SWT2_SHIFT (2U) /*! SWT2 - Software trigger 2 event @@ -746,6 +816,7 @@ typedef struct { * 0b1..Trigger 2 event generated. */ #define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + #define ADC_SWTRIG_SWT3_MASK (0x8U) #define ADC_SWTRIG_SWT3_SHIFT (3U) /*! SWT3 - Software trigger 3 event @@ -753,6 +824,7 @@ typedef struct { * 0b1..Trigger 3 event generated. */ #define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) + #define ADC_SWTRIG_SWT4_MASK (0x10U) #define ADC_SWTRIG_SWT4_SHIFT (4U) /*! SWT4 - Software trigger 4 event @@ -760,6 +832,7 @@ typedef struct { * 0b1..Trigger 4 event generated. */ #define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) + #define ADC_SWTRIG_SWT5_MASK (0x20U) #define ADC_SWTRIG_SWT5_SHIFT (5U) /*! SWT5 - Software trigger 5 event @@ -767,6 +840,7 @@ typedef struct { * 0b1..Trigger 5 event generated. */ #define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) + #define ADC_SWTRIG_SWT6_MASK (0x40U) #define ADC_SWTRIG_SWT6_SHIFT (6U) /*! SWT6 - Software trigger 6 event @@ -774,6 +848,7 @@ typedef struct { * 0b1..Trigger 6 event generated. */ #define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) + #define ADC_SWTRIG_SWT7_MASK (0x80U) #define ADC_SWTRIG_SWT7_SHIFT (7U) /*! SWT7 - Software trigger 7 event @@ -781,6 +856,7 @@ typedef struct { * 0b1..Trigger 7 event generated. */ #define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK) + #define ADC_SWTRIG_SWT8_MASK (0x100U) #define ADC_SWTRIG_SWT8_SHIFT (8U) /*! SWT8 - Software trigger 8 event @@ -788,6 +864,7 @@ typedef struct { * 0b1..Trigger 8 event generated. */ #define ADC_SWTRIG_SWT8(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT8_SHIFT)) & ADC_SWTRIG_SWT8_MASK) + #define ADC_SWTRIG_SWT9_MASK (0x200U) #define ADC_SWTRIG_SWT9_SHIFT (9U) /*! SWT9 - Software trigger 9 event @@ -795,6 +872,7 @@ typedef struct { * 0b1..Trigger 9 event generated. */ #define ADC_SWTRIG_SWT9(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT9_SHIFT)) & ADC_SWTRIG_SWT9_MASK) + #define ADC_SWTRIG_SWT10_MASK (0x400U) #define ADC_SWTRIG_SWT10_SHIFT (10U) /*! SWT10 - Software trigger 10 event @@ -802,6 +880,7 @@ typedef struct { * 0b1..Trigger 10 event generated. */ #define ADC_SWTRIG_SWT10(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT10_SHIFT)) & ADC_SWTRIG_SWT10_MASK) + #define ADC_SWTRIG_SWT11_MASK (0x800U) #define ADC_SWTRIG_SWT11_SHIFT (11U) /*! SWT11 - Software trigger 11 event @@ -809,6 +888,7 @@ typedef struct { * 0b1..Trigger 11 event generated. */ #define ADC_SWTRIG_SWT11(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT11_SHIFT)) & ADC_SWTRIG_SWT11_MASK) + #define ADC_SWTRIG_SWT12_MASK (0x1000U) #define ADC_SWTRIG_SWT12_SHIFT (12U) /*! SWT12 - Software trigger 12 event @@ -816,6 +896,7 @@ typedef struct { * 0b1..Trigger 12 event generated. */ #define ADC_SWTRIG_SWT12(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT12_SHIFT)) & ADC_SWTRIG_SWT12_MASK) + #define ADC_SWTRIG_SWT13_MASK (0x2000U) #define ADC_SWTRIG_SWT13_SHIFT (13U) /*! SWT13 - Software trigger 13 event @@ -823,6 +904,7 @@ typedef struct { * 0b1..Trigger 13 event generated. */ #define ADC_SWTRIG_SWT13(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT13_SHIFT)) & ADC_SWTRIG_SWT13_MASK) + #define ADC_SWTRIG_SWT14_MASK (0x4000U) #define ADC_SWTRIG_SWT14_SHIFT (14U) /*! SWT14 - Software trigger 14 event @@ -830,6 +912,7 @@ typedef struct { * 0b1..Trigger 14 event generated. */ #define ADC_SWTRIG_SWT14(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT14_SHIFT)) & ADC_SWTRIG_SWT14_MASK) + #define ADC_SWTRIG_SWT15_MASK (0x8000U) #define ADC_SWTRIG_SWT15_SHIFT (15U) /*! SWT15 - Software trigger 15 event @@ -841,6 +924,7 @@ typedef struct { /*! @name TSTAT - Trigger Status Register */ /*! @{ */ + #define ADC_TSTAT_TEXC_NUM_MASK (0xFFFFU) #define ADC_TSTAT_TEXC_NUM_SHIFT (0U) /*! TEXC_NUM - Trigger Exception Number @@ -851,6 +935,7 @@ typedef struct { * 0b1111111111111111..Every trigger sequence has been interrupted by a high priority exception. */ #define ADC_TSTAT_TEXC_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TSTAT_TEXC_NUM_SHIFT)) & ADC_TSTAT_TEXC_NUM_MASK) + #define ADC_TSTAT_TCOMP_FLAG_MASK (0xFFFF0000U) #define ADC_TSTAT_TCOMP_FLAG_SHIFT (16U) /*! TCOMP_FLAG - Trigger Completion Flag @@ -865,16 +950,23 @@ typedef struct { /*! @name OFSTRIM - ADC Offset Trim Register */ /*! @{ */ + #define ADC_OFSTRIM_OFSTRIM_A_MASK (0x1FU) #define ADC_OFSTRIM_OFSTRIM_A_SHIFT (0U) +/*! OFSTRIM_A - Trim for offset + */ #define ADC_OFSTRIM_OFSTRIM_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_A_SHIFT)) & ADC_OFSTRIM_OFSTRIM_A_MASK) + #define ADC_OFSTRIM_OFSTRIM_B_MASK (0x1F0000U) #define ADC_OFSTRIM_OFSTRIM_B_SHIFT (16U) +/*! OFSTRIM_B - Trim for offset + */ #define ADC_OFSTRIM_OFSTRIM_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFSTRIM_OFSTRIM_B_SHIFT)) & ADC_OFSTRIM_OFSTRIM_B_MASK) /*! @} */ /*! @name TCTRL - Trigger Control Register */ /*! @{ */ + #define ADC_TCTRL_HTEN_MASK (0x1U) #define ADC_TCTRL_HTEN_SHIFT (0U) /*! HTEN - Trigger enable @@ -882,6 +974,7 @@ typedef struct { * 0b1..Hardware trigger source enabled */ #define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + #define ADC_TCTRL_FIFO_SEL_A_MASK (0x2U) #define ADC_TCTRL_FIFO_SEL_A_SHIFT (1U) /*! FIFO_SEL_A - SAR Result Destination For Channel A @@ -889,6 +982,7 @@ typedef struct { * 0b1..Result written to FIFO 1 */ #define ADC_TCTRL_FIFO_SEL_A(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_A_SHIFT)) & ADC_TCTRL_FIFO_SEL_A_MASK) + #define ADC_TCTRL_FIFO_SEL_B_MASK (0x4U) #define ADC_TCTRL_FIFO_SEL_B_SHIFT (2U) /*! FIFO_SEL_B - SAR Result Destination For Channel B @@ -896,6 +990,7 @@ typedef struct { * 0b1..Result written to FIFO 1 */ #define ADC_TCTRL_FIFO_SEL_B(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_FIFO_SEL_B_SHIFT)) & ADC_TCTRL_FIFO_SEL_B_MASK) + #define ADC_TCTRL_TPRI_MASK (0xF00U) #define ADC_TCTRL_TPRI_SHIFT (8U) /*! TPRI - Trigger priority setting @@ -904,12 +999,19 @@ typedef struct { * 0b1111..Set to lowest priority, Level 16 */ #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + #define ADC_TCTRL_RSYNC_MASK (0x8000U) #define ADC_TCTRL_RSYNC_SHIFT (15U) +/*! RSYNC - Trigger Resync + */ #define ADC_TCTRL_RSYNC(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_RSYNC_SHIFT)) & ADC_TCTRL_RSYNC_MASK) + #define ADC_TCTRL_TDLY_MASK (0xF0000U) #define ADC_TCTRL_TDLY_SHIFT (16U) +/*! TDLY - Trigger delay select + */ #define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + #define ADC_TCTRL_TCMD_MASK (0xF000000U) #define ADC_TCTRL_TCMD_SHIFT (24U) /*! TCMD - Trigger command select @@ -926,11 +1028,17 @@ typedef struct { /*! @name FCTRL - FIFO Control Register */ /*! @{ */ + #define ADC_FCTRL_FCOUNT_MASK (0x1FU) #define ADC_FCTRL_FCOUNT_SHIFT (0U) +/*! FCOUNT - Result FIFO counter + */ #define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + #define ADC_FCTRL_FWMARK_MASK (0xF0000U) #define ADC_FCTRL_FWMARK_SHIFT (16U) +/*! FWMARK - Watermark level selection + */ #define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) /*! @} */ @@ -939,9 +1047,13 @@ typedef struct { /*! @name GCC - Gain Calibration Control */ /*! @{ */ + #define ADC_GCC_GAIN_CAL_MASK (0xFFFFU) #define ADC_GCC_GAIN_CAL_SHIFT (0U) +/*! GAIN_CAL - Gain Calibration Value + */ #define ADC_GCC_GAIN_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCC_GAIN_CAL_SHIFT)) & ADC_GCC_GAIN_CAL_MASK) + #define ADC_GCC_RDY_MASK (0x1000000U) #define ADC_GCC_RDY_SHIFT (24U) /*! RDY - Gain Calibration Value Valid @@ -956,9 +1068,13 @@ typedef struct { /*! @name GCR - Gain Calculation Result */ /*! @{ */ + #define ADC_GCR_GCALR_MASK (0xFFFFU) #define ADC_GCR_GCALR_SHIFT (0U) +/*! GCALR - Gain Calculation Result + */ #define ADC_GCR_GCALR(x) (((uint32_t)(((uint32_t)(x)) << ADC_GCR_GCALR_SHIFT)) & ADC_GCR_GCALR_MASK) + #define ADC_GCR_RDY_MASK (0x1000000U) #define ADC_GCR_RDY_SHIFT (24U) /*! RDY - Gain Calculation Ready @@ -973,6 +1089,7 @@ typedef struct { /*! @name CMDL - ADC Command Low Buffer Register */ /*! @{ */ + #define ADC_CMDL_ADCH_MASK (0x1FU) #define ADC_CMDL_ADCH_SHIFT (0U) /*! ADCH - Input channel select @@ -985,6 +1102,7 @@ typedef struct { * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. */ #define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + #define ADC_CMDL_CTYPE_MASK (0x60U) #define ADC_CMDL_CTYPE_SHIFT (5U) /*! CTYPE - Conversion Type @@ -994,6 +1112,7 @@ typedef struct { * 0b11..Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */ #define ADC_CMDL_CTYPE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CTYPE_SHIFT)) & ADC_CMDL_CTYPE_MASK) + #define ADC_CMDL_MODE_MASK (0x80U) #define ADC_CMDL_MODE_SHIFT (7U) /*! MODE - Select resolution of conversions @@ -1008,6 +1127,7 @@ typedef struct { /*! @name CMDH - ADC Command High Buffer Register */ /*! @{ */ + #define ADC_CMDH_CMPEN_MASK (0x3U) #define ADC_CMDH_CMPEN_SHIFT (0U) /*! CMPEN - Compare Function Enable @@ -1017,6 +1137,7 @@ typedef struct { * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. */ #define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + #define ADC_CMDH_WAIT_TRIG_MASK (0x4U) #define ADC_CMDH_WAIT_TRIG_SHIFT (2U) /*! WAIT_TRIG - Wait for trigger assertion before execution. @@ -1024,6 +1145,7 @@ typedef struct { * 0b1..The active trigger must be asserted again before executing this command. */ #define ADC_CMDH_WAIT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_WAIT_TRIG_SHIFT)) & ADC_CMDH_WAIT_TRIG_MASK) + #define ADC_CMDH_LWI_MASK (0x80U) #define ADC_CMDH_LWI_SHIFT (7U) /*! LWI - Loop with Increment @@ -1031,6 +1153,7 @@ typedef struct { * 0b1..Auto channel increment enabled */ #define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + #define ADC_CMDH_STS_MASK (0x700U) #define ADC_CMDH_STS_SHIFT (8U) /*! STS - Sample Time Select @@ -1044,6 +1167,7 @@ typedef struct { * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. */ #define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + #define ADC_CMDH_AVGS_MASK (0x7000U) #define ADC_CMDH_AVGS_SHIFT (12U) /*! AVGS - Hardware Average Select @@ -1057,6 +1181,7 @@ typedef struct { * 0b111..128 conversions averaged. */ #define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + #define ADC_CMDH_LOOP_MASK (0xF0000U) #define ADC_CMDH_LOOP_SHIFT (16U) /*! LOOP - Loop Count Select @@ -1067,6 +1192,7 @@ typedef struct { * 0b1111..Loop 15 times. Command executes 16 times. */ #define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + #define ADC_CMDH_NEXT_MASK (0xF000000U) #define ADC_CMDH_NEXT_SHIFT (24U) /*! NEXT - Next Command Select @@ -1084,11 +1210,17 @@ typedef struct { /*! @name CV - Compare Value Register */ /*! @{ */ + #define ADC_CV_CVL_MASK (0xFFFFU) #define ADC_CV_CVL_SHIFT (0U) +/*! CVL - Compare Value Low. + */ #define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + #define ADC_CV_CVH_MASK (0xFFFF0000U) #define ADC_CV_CVH_SHIFT (16U) +/*! CVH - Compare Value High. + */ #define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK) /*! @} */ @@ -1097,9 +1229,13 @@ typedef struct { /*! @name RESFIFO - ADC Data Result FIFO Register */ /*! @{ */ + #define ADC_RESFIFO_D_MASK (0xFFFFU) #define ADC_RESFIFO_D_SHIFT (0U) +/*! D - Data result + */ #define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + #define ADC_RESFIFO_TSRC_MASK (0xF0000U) #define ADC_RESFIFO_TSRC_SHIFT (16U) /*! TSRC - Trigger Source @@ -1109,6 +1245,7 @@ typedef struct { * 0b1111..Trigger source 15 initiated this conversion. */ #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + #define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) #define ADC_RESFIFO_LOOPCNT_SHIFT (20U) /*! LOOPCNT - Loop count value @@ -1118,6 +1255,7 @@ typedef struct { * 0b1111..Result is from 16th conversion in command. */ #define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + #define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) #define ADC_RESFIFO_CMDSRC_SHIFT (24U) /*! CMDSRC - Command Buffer Source @@ -1128,6 +1266,7 @@ typedef struct { * 0b1111..CMD15 buffer used as control settings for this conversion. */ #define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + #define ADC_RESFIFO_VALID_MASK (0x80000000U) #define ADC_RESFIFO_VALID_SHIFT (31U) /*! VALID - FIFO entry is valid @@ -1142,8 +1281,11 @@ typedef struct { /*! @name CAL_GAR - Calibration General A-Side Registers */ /*! @{ */ + #define ADC_CAL_GAR_CAL_GAR_VAL_MASK (0xFFFFU) #define ADC_CAL_GAR_CAL_GAR_VAL_SHIFT (0U) +/*! CAL_GAR_VAL - Calibration General A Side Register Element + */ #define ADC_CAL_GAR_CAL_GAR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GAR_CAL_GAR_VAL_SHIFT)) & ADC_CAL_GAR_CAL_GAR_VAL_MASK) /*! @} */ @@ -1152,8 +1294,11 @@ typedef struct { /*! @name CAL_GBR - Calibration General B-Side Registers */ /*! @{ */ + #define ADC_CAL_GBR_CAL_GBR_VAL_MASK (0xFFFFU) #define ADC_CAL_GBR_CAL_GBR_VAL_SHIFT (0U) +/*! CAL_GBR_VAL - Calibration General B Side Register Element + */ #define ADC_CAL_GBR_CAL_GBR_VAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_GBR_CAL_GBR_VAL_SHIFT)) & ADC_CAL_GBR_CAL_GBR_VAL_MASK) /*! @} */ @@ -1162,6 +1307,7 @@ typedef struct { /*! @name TST - ADC Test Register */ /*! @{ */ + #define ADC_TST_CST_LONG_MASK (0x1U) #define ADC_TST_CST_LONG_SHIFT (0U) /*! CST_LONG - Calibration Sample Time Long @@ -1169,6 +1315,7 @@ typedef struct { * 0b1..Increased sample time. 67 ADCK cycles total sample time. */ #define ADC_TST_CST_LONG(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_CST_LONG_SHIFT)) & ADC_TST_CST_LONG_MASK) + #define ADC_TST_FOFFM_MASK (0x100U) #define ADC_TST_FOFFM_SHIFT (8U) /*! FOFFM - Force M-side positive offset @@ -1176,6 +1323,7 @@ typedef struct { * 0b1..Test configuration. Forced positive offset on MDAC. */ #define ADC_TST_FOFFM(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM_SHIFT)) & ADC_TST_FOFFM_MASK) + #define ADC_TST_FOFFP_MASK (0x200U) #define ADC_TST_FOFFP_SHIFT (9U) /*! FOFFP - Force P-side positive offset @@ -1183,6 +1331,7 @@ typedef struct { * 0b1..Test configuration. Forced positive offset on PDAC. */ #define ADC_TST_FOFFP(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP_SHIFT)) & ADC_TST_FOFFP_MASK) + #define ADC_TST_FOFFM2_MASK (0x400U) #define ADC_TST_FOFFM2_SHIFT (10U) /*! FOFFM2 - Force M-side negative offset @@ -1190,6 +1339,7 @@ typedef struct { * 0b1..Test configuration. Forced negative offset on MDAC. */ #define ADC_TST_FOFFM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFM2_SHIFT)) & ADC_TST_FOFFM2_MASK) + #define ADC_TST_FOFFP2_MASK (0x800U) #define ADC_TST_FOFFP2_SHIFT (11U) /*! FOFFP2 - Force P-side negative offset @@ -1197,6 +1347,7 @@ typedef struct { * 0b1..Test configuration. Forced negative offset on PDAC. */ #define ADC_TST_FOFFP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_TST_FOFFP2_SHIFT)) & ADC_TST_FOFFP2_MASK) + #define ADC_TST_TESTEN_MASK (0x800000U) #define ADC_TST_TESTEN_SHIFT (23U) /*! TESTEN - Enable test configuration @@ -1213,7 +1364,7 @@ typedef struct { /* ADC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral ADC0 base address */ #define ADC0_BASE (0x500A0000u) /** Peripheral ADC0 base address */ @@ -1308,24 +1459,24 @@ typedef struct { __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL0; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x100, array step: 0x30 */ __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL1; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x104, array step: 0x30 */ __IO uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL2; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x108, array step: 0x30 */ - uint32_t SEC_CTRL_APB_BRIDGE0_MEM_CTRL3; /**< Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total., array offset: 0x10C, array step: 0x30 */ + uint8_t RESERVED_1[4]; __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL0; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x110, array step: 0x30 */ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL1; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x114, array step: 0x30 */ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL2; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x118, array step: 0x30 */ __IO uint32_t SEC_CTRL_APB_BRIDGE1_MEM_CTRL3; /**< Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total., array offset: 0x11C, array step: 0x30 */ } SEC_CTRL_APB_BRIDGE[1]; - __IO uint32_t SEC_CTRL_AHB0_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ - __IO uint32_t SEC_CTRL_AHB0_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x120 */ + __IO uint32_t SEC_CTRL_AHB_PORT8_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x124 */ uint8_t RESERVED_6[8]; - __IO uint32_t SEC_CTRL_AHB1_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ - __IO uint32_t SEC_CTRL_AHB1_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE0_RULE; /**< Security access rules for AHB peripherals., offset: 0x130 */ + __IO uint32_t SEC_CTRL_AHB_PORT9_SLAVE1_RULE; /**< Security access rules for AHB peripherals., offset: 0x134 */ uint8_t RESERVED_7[8]; struct { /* offset: 0x140, array step: 0x14 */ - __IO uint32_t SEC_CTRL_AHB2_0_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ - __IO uint32_t SEC_CTRL_AHB2_1_SLAVE_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ + __IO uint32_t SLAVE0_RULE; /**< Security access rules for AHB peripherals., array offset: 0x140, array step: 0x14 */ + __IO uint32_t SLAVE1_RULE; /**< Security access rules for AHB peripherals., array offset: 0x144, array step: 0x14 */ uint8_t RESERVED_0[8]; - __IO uint32_t SEC_CTRL_AHB2_0_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ - } SEC_CTRL_AHB2[1]; + __IO uint32_t SEC_CTRL_AHB_SEC_CTRL_MEM_RULE[1]; /**< Security access rules for AHB_SEC_CTRL_AHB., array offset: 0x150, array step: index*0x14, index2*0x4 */ + } SEC_CTRL_AHB_PORT10[1]; uint8_t RESERVED_8[12]; struct { /* offset: 0x160, array step: 0x14 */ __IO uint32_t SLAVE_RULE; /**< Security access rules for USB High speed RAM slaves., array offset: 0x160, array step: 0x14 */ @@ -1333,9 +1484,9 @@ typedef struct { __IO uint32_t MEM_RULE[1]; /**< Security access rules for RAM_USB_HS., array offset: 0x170, array step: index*0x14, index2*0x4 */ } SEC_CTRL_USB_HS[1]; uint8_t RESERVED_9[3212]; - __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB layer n, array offset: 0xE00, array step: 0x4 */ + __I uint32_t SEC_VIO_ADDR[12]; /**< most recent security violation address for AHB port n, array offset: 0xE00, array step: 0x4 */ uint8_t RESERVED_10[80]; - __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB layer n, array offset: 0xE80, array step: 0x4 */ + __I uint32_t SEC_VIO_MISC_INFO[12]; /**< most recent security violation miscellaneous information for AHB port n, array offset: 0xE80, array step: 0x4 */ uint8_t RESERVED_11[80]; __IO uint32_t SEC_VIO_INFO_VALID; /**< security violation address/information registers valid flags, offset: 0xF00 */ uint8_t RESERVED_12[124]; @@ -1350,8 +1501,8 @@ typedef struct { __IO uint32_t MASTER_SEC_LEVEL; /**< master secure level register, offset: 0xFD0 */ __IO uint32_t MASTER_SEC_ANTI_POL_REG; /**< master secure level anti-pole register, offset: 0xFD4 */ uint8_t RESERVED_16[20]; - __IO uint32_t CM33_LOCK_REG; /**< Miscalleneous control signals for in CM33 (CPU0), offset: 0xFEC */ - __IO uint32_t MCM33_LOCK_REG; /**< Miscalleneous control signals for in micro-CM33 (CPU1), offset: 0xFF0 */ + __IO uint32_t CPU0_LOCK_REG; /**< Miscalleneous control signals for in Cortex M33 (CPU0), offset: 0xFEC */ + __IO uint32_t CPU1_LOCK_REG; /**< Miscalleneous control signals for in micro-Cortex M33 (CPU1), offset: 0xFF0 */ uint8_t RESERVED_17[4]; __IO uint32_t MISC_CTRL_DP_REG; /**< secure control duplicate register, offset: 0xFF8 */ __IO uint32_t MISC_CTRL_REG; /**< secure control register, offset: 0xFFC */ @@ -1368,6 +1519,7 @@ typedef struct { /*! @name SEC_CTRL_FLASH_ROM_SLAVE_RULE - Security access rules for Flash and ROM slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT (0U) /*! FLASH_RULE - Security access rules for the whole FLASH : 0x0000_0000 - 0x0009_FFFF @@ -1377,6 +1529,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_FLASH_RULE_MASK) + #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_MASK (0x30U) #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_ROM_RULE_SHIFT (4U) /*! ROM_RULE - Security access rules for the whole ROM : 0x0300_0000 - 0x0301_FFFF @@ -1391,172 +1544,189 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ +/*! @name SEC_CTRL_FLASH_MEM_RULE - Security access rules for FLASH sector 0 to sector 20. Each Flash sector is 32 Kbytes. There are 20 FLASH sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_MEM_RULE_COUNT2 (3U) -/*! @name SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ +/*! @name SEC_CTRL_ROM_MEM_RULE - Security access rules for ROM sector 0 to sector 31. Each ROM sector is 4 Kbytes. There are 32 ROM sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_FLASH_ROM_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_ROM_MEM_RULE_COUNT2 (4U) /*! @name SEC_CTRL_RAMX_SLAVE_RULE - Security access rules for RAMX slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_RAMX_RULE_SHIFT (0U) /*! RAMX_RULE - Security access rules for the whole RAMX : 0x0400_0000 - 0x0400_7FFF @@ -1571,90 +1741,99 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE - Security access rules for RAMX slaves. */ +/*! @name SEC_CTRL_RAMX_MEM_RULE - Security access rules for RAMX slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_SEC_CTRL_RAMX_MEM_RULE_MEM_RULE_COUNT2 (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAMX_MEM_RULE_COUNT2 (1U) /*! @name SEC_CTRL_RAM0_SLAVE_RULE - Security access rules for RAM0 slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_RAM0_RULE_SHIFT (0U) /*! RAM0_RULE - Security access rules for the whole RAM0 : 0x2000_0000 - 0x2000_FFFF @@ -1669,188 +1848,206 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE - Security access rules for RAM0 slaves. */ +/*! @name SEC_CTRL_RAM0_MEM_RULE - Security access rules for RAM0 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_SEC_CTRL_RAM0_MEM_RULE_MEM_RULE_COUNT2 (2U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM0_MEM_RULE_COUNT2 (2U) /*! @name SEC_CTRL_RAM1_SLAVE_RULE - Security access rules for RAM1 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT (0U) -/*! RAM0_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT (0U) +/*! RAM1_RULE - Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_RAM1_RULE_MASK) /*! @} */ /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE - Security access rules for RAM1 slaves. */ +/*! @name SEC_CTRL_RAM1_MEM_RULE - Security access rules for RAM1 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_SEC_CTRL_RAM1_MEM_RULE_MEM_RULE_COUNT2 (2U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM1_MEM_RULE_COUNT2 (2U) /*! @name SEC_CTRL_RAM2_SLAVE_RULE - Security access rules for RAM2 slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_RAM2_RULE_SHIFT (0U) /*! RAM2_RULE - Security access rules for the whole RAM2 : 0x2002_0000 - 0x2002_FFFF @@ -1865,90 +2062,99 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE - Security access rules for RAM2 slaves. */ +/*! @name SEC_CTRL_RAM2_MEM_RULE - Security access rules for RAM2 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_SEC_CTRL_RAM2_MEM_RULE_MEM_RULE_COUNT2 (2U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM2_MEM_RULE_COUNT2 (2U) /*! @name SEC_CTRL_RAM3_SLAVE_RULE - Security access rules for RAM3 slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_RAM3_RULE_SHIFT (0U) /*! RAM3_RULE - Security access rules for the whole RAM3: 0x2003_0000 - 0x2003_FFFF @@ -1963,90 +2169,99 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE - Security access rules for RAM3 slaves. */ +/*! @name SEC_CTRL_RAM3_MEM_RULE - Security access rules for RAM3 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE3_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE3_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT (16U) /*! RULE4 - secure control rule4. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE4_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE4_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT (20U) /*! RULE5 - secure control rule5. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE5_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE5_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT (24U) /*! RULE6 - secure control rule6. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE6_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE6_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT (28U) /*! RULE7 - secure control rule7. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_RULE7_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_RULE7_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_SEC_CTRL_RAM3_MEM_RULE_MEM_RULE_COUNT2 (2U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM3_MEM_RULE_COUNT2 (2U) /*! @name SEC_CTRL_RAM4_SLAVE_RULE - Security access rules for RAM4 slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_RAM4_RULE_SHIFT (0U) /*! RAM4_RULE - Security access rules for the whole RAM4 : 0x2004_0000 - 0x2004_3FFF @@ -2061,54 +2276,59 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE - Security access rules for RAM4 slaves. */ +/*! @name SEC_CTRL_RAM4_MEM_RULE - Security access rules for RAM4 slaves. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT (0U) /*! RULE0 - secure control rule0. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE0_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE0_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT (4U) /*! RULE1 - secure control rule1. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE1_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE1_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT (8U) /*! RULE2 - secure control rule2. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE2_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE2_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT (12U) /*! RULE3 - secure control rule3. it can be set when check_reg's write_lock is '0' * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_RULE3_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_RULE3_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_SEC_CTRL_RAM4_MEM_RULE_MEM_RULE_COUNT2 (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_RAM4_MEM_RULE_COUNT2 (1U) /*! @name SEC_CTRL_APB_BRIDGE_SLAVE_RULE - Security access rules for both APB Bridges slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT (0U) /*! APBBRIDGE0_RULE - Security access rules for the whole APB Bridge 0 @@ -2118,6 +2338,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE0_RULE_MASK) + #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_MASK (0x30U) #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_APBBRIDGE1_RULE_SHIFT (4U) /*! APBBRIDGE1_RULE - Security access rules for the whole APB Bridge 1 @@ -2132,622 +2353,668 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT (0U) /*! SYSCON_RULE - System Configuration * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SYSCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT (4U) /*! IOCON_RULE - I/O Configuration * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_IOCON_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT (8U) /*! GINT0_RULE - GPIO input Interrupt 0 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT (12U) /*! GINT1_RULE - GPIO input Interrupt 1 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_GINT1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT (16U) /*! PINT_RULE - Pin Interrupt and Pattern match * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT (20U) /*! SEC_PINT_RULE - Secure Pin Interrupt and Pattern match * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT (24U) -/*! PMUX_RULE - Peripherals mux +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_SEC_PINT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT (24U) +/*! INPUTMUX_RULE - Peripheral input multiplexing * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_PMUX_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_INPUTMUX_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL0_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT (0U) /*! CTIMER0_RULE - Standard counter/Timer 0 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT (4U) /*! CTIMER1_RULE - Standard counter/Timer 1 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_CTIMER1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT (16U) /*! WWDT_RULE - Windiwed wtachdog Timer * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_WWDT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT (20U) /*! MRT_RULE - Multi-rate Timer * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_MRT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT (24U) /*! UTICK_RULE - Micro-Timer * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_UTICK_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL1_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT (12U) /*! ANACTRL_RULE - Analog Modules controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT (20U) -/*! EFUSE_RULE - eFUSE (One Time Programmable) memory controller - * 0b00..Non-secure and Non-priviledge user access allowed. - * 0b01..Non-secure and Privilege access allowed. - * 0b10..Secure and Non-priviledge user access allowed. - * 0b11..Secure and Priviledge user access allowed. - */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_EFUSE_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_ANACTRL_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE0_MEM_CTRL2_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE0_MEM_CTRL3_COUNT (1U) - -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT (0U) /*! PMC_RULE - Power Management Controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_PMC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT (12U) /*! SYSCTRL_RULE - System Controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_SYSCTRL_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL0_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT (0U) /*! CTIMER2_RULE - Standard counter/Timer 2 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT (4U) /*! CTIMER3_RULE - Standard counter/Timer 3 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT (8U) /*! CTIMER4_RULE - Standard counter/Timer 4 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_CTIMER4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT (16U) /*! RTC_RULE - Real Time Counter * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_RTC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT (20U) /*! OSEVENT_RULE - OS Event Timer * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_OSEVENT_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL1_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT (16U) /*! FLASH_CTRL_RULE - Flash Controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_FLASH_CTRL_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT (20U) /*! PRINCE_RULE - Prince * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_PRINCE_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL2_COUNT (1U) -/*! @name SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ +/*! @name SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 - Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT (0U) /*! USBHPHY_RULE - USB High Speed Phy controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_USBHPHY_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT (8U) /*! RNG_RULE - True Random Number Generator * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT (12U) -/*! PUFF_RULE - PUF +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_RNG_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT (12U) +/*! PUF_RULE - PUF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUFF_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PUF_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT (20U) /*! PLU_RULE - Programmable Look-Up logic * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_PLU_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ -#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3 */ +#define AHB_SECURE_CTRL_SEC_CTRL_APB_BRIDGE1_MEM_CTRL3_COUNT (1U) -/*! @name SEC_CTRL_AHB0_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT8_SLAVE0_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT (8U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT (8U) /*! DMA0_RULE - DMA Controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_DMA0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_DMA0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT (16U) /*! FS_USB_DEV_RULE - USB Full-speed device * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FS_USB_DEV_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FS_USB_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT (20U) /*! SCT_RULE - SCTimer * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_SCT_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_SCT_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT (24U) /*! FLEXCOMM0_RULE - Flexcomm interface 0 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT (28U) /*! FLEXCOMM1_RULE - Flexcomm interface 1 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_0_SLAVE_RULE_FLEXCOMM1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE0_RULE_FLEXCOMM1_RULE_MASK) /*! @} */ -/*! @name SEC_CTRL_AHB0_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT8_SLAVE1_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT (0U) /*! FLEXCOMM2_RULE - Flexcomm interface 2 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT (4U) /*! FLEXCOMM3_RULE - Flexcomm interface 3 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM3_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM3_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT (8U) /*! FLEXCOMM4_RULE - Flexcomm interface 4 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_FLEXCOMM4_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_FLEXCOMM4_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT (12U) /*! MAILBOX_RULE - Inter CPU communication Mailbox * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_MAILBOX_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_MAILBOX_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT (16U) /*! GPIO0_RULE - High Speed GPIO * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB0_1_SLAVE_RULE_GPIO0_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT8_SLAVE1_RULE_GPIO0_RULE_MASK) /*! @} */ -/*! @name SEC_CTRL_AHB1_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT9_SLAVE0_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT (16U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT (16U) /*! USB_HS_DEV_RULE - USB high Speed device registers * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_USB_HS_DEV_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_USB_HS_DEV_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT (20U) /*! CRC_RULE - CRC engine * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_CRC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT (24U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_CRC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT (24U) /*! FLEXCOMM5_RULE - Flexcomm interface 5 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM5_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM5_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT (28U) /*! FLEXCOMM6_RULE - Flexcomm interface 6 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_0_SLAVE_RULE_FLEXCOMM6_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE0_RULE_FLEXCOMM6_RULE_MASK) /*! @} */ -/*! @name SEC_CTRL_AHB1_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT9_SLAVE1_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT (0U) /*! FLEXCOMM7_RULE - Flexcomm interface 7 * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_FLEXCOMM7_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_FLEXCOMM7_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT (12U) /*! SDIO_RULE - SDMMC card interface * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_SDIO_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_SDIO_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT (16U) /*! DBG_MAILBOX_RULE - Debug mailbox (aka ISP-AP) * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_DBG_MAILBOX_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_DBG_MAILBOX_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT (28U) /*! HS_LSPI_RULE - High Speed SPI * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB1_1_SLAVE_RULE_HS_LSPI_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT9_SLAVE1_RULE_HS_LSPI_RULE_MASK) /*! @} */ -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT10_SLAVE0_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT (0U) /*! ADC_RULE - ADC * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_ADC_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_ADC_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT (8U) /*! USB_FS_HOST_RULE - USB Full Speed Host registers. * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_FS_HOST_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_FS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT (12U) /*! USB_HS_HOST_RULE - USB High speed host registers * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_USB_HS_HOST_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK (0x30000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT (16U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_USB_HS_HOST_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK (0x30000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT (16U) /*! HASH_RULE - SHA-2 crypto registers * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_HASH_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK (0x300000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT (20U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_HASH_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK (0x300000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT (20U) /*! CASPER_RULE - RSA/ECC crypto accelerator * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_CASPER_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK (0x3000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT (24U) -/*! PQ_RULE - Power Quad (CM33 processor hardware accelerator) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_CASPER_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK (0x3000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT (24U) +/*! PQ_RULE - Power Quad (CPU0 processor hardware accelerator) * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_PQ_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK (0x30000000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT (28U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_PQ_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK (0x30000000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT (28U) /*! DMA1_RULE - DMA Controller (Secure) * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_DMA1_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_DMA1_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_0_SLAVE_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE0_RULE_COUNT (1U) -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE - Security access rules for AHB peripherals. */ +/*! @name SEC_CTRL_AHB_PORT10_SLAVE1_RULE - Security access rules for AHB peripherals. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT (0U) /*! GPIO1_RULE - Secure High Speed GPIO * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_GPIO1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_GPIO1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT (4U) /*! AHB_SEC_CTRL_RULE - AHB Secure Controller * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_AHB_SEC_CTRL_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_AHB_SEC_CTRL_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_1_SLAVE_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_PORT10_SLAVE1_RULE_COUNT (1U) -/*! @name SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ +/*! @name SEC_CTRL_AHB_SEC_CTRL_MEM_RULE - Security access rules for AHB_SEC_CTRL_AHB. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT (0U) /*! AHB_SEC_CTRL_SECT_0_RULE - Address space: 0x400A_0000 - 0x400A_CFFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT (4U) /*! AHB_SEC_CTRL_SECT_1_RULE - Address space: 0x400A_D000 - 0x400A_DFFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT (8U) /*! AHB_SEC_CTRL_SECT_2_RULE - Address space: 0x400A_E000 - 0x400A_EFFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT (12U) /*! AHB_SEC_CTRL_SECT_3_RULE - Address space: 0x400A_F000 - 0x400A_FFFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_AHB_SEC_CTRL_SECT_3_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_AHB2_SEC_CTRL_AHB2_MEM_RULE_SEC_CTRL_AHB2_0_MEM_RULE_COUNT2 (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_AHB_SEC_CTRL_MEM_RULE_COUNT2 (1U) /*! @name SEC_CTRL_USB_HS_SLAVE_RULE - Security access rules for USB High speed RAM slaves. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_RAM_USB_HS_RULE_SHIFT (0U) /*! RAM_USB_HS_RULE - Security access rules for the whole USB High Speed RAM : 0x4010_0000 - 0x4010_3FFF @@ -2762,64 +3029,72 @@ typedef struct { /* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE */ #define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SLAVE_RULE_COUNT (1U) -/*! @name SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE - Security access rules for RAM_USB_HS. */ +/*! @name SEC_CTRL_USB_HS_MEM_RULE - Security access rules for RAM_USB_HS. */ /*! @{ */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK (0x3U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT (0U) /*! SRAM_SECT_0_RULE - Address space: 0x4010_0000 - 0x4010_0FFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_0_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_0_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK (0x30U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT (4U) /*! SRAM_SECT_1_RULE - Address space: 0x4010_1000 - 0x4010_1FFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_1_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_1_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK (0x300U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT (8U) /*! SRAM_SECT_2_RULE - Address space: 0x4010_2000 - 0x4010_2FFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_2_RULE_MASK) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_2_RULE_MASK) + +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK (0x3000U) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT (12U) /*! SRAM_SECT_3_RULE - Address space: 0x4010_3000 - 0x4010_3FFF * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_SRAM_SECT_3_RULE_MASK) +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_SHIFT)) & AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_SRAM_SECT_3_RULE_MASK) /*! @} */ -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT (1U) -/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE */ -#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_SEC_CTRL_USB_HS_MEM_RULE_MEM_RULE_COUNT2 (1U) +/* The count of AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE */ +#define AHB_SECURE_CTRL_SEC_CTRL_USB_HS_MEM_RULE_COUNT2 (1U) -/*! @name SEC_VIO_ADDR - most recent security violation address for AHB layer n */ +/*! @name SEC_VIO_ADDR - most recent security violation address for AHB port n */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK (0xFFFFFFFFU) #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT (0U) +/*! SEC_VIO_ADDR - security violation address for AHB port + */ #define AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_ADDR_SEC_VIO_ADDR_MASK) /*! @} */ /* The count of AHB_SECURE_CTRL_SEC_VIO_ADDR */ #define AHB_SECURE_CTRL_SEC_VIO_ADDR_COUNT (12U) -/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB layer n */ +/*! @name SEC_VIO_MISC_INFO - most recent security violation miscellaneous information for AHB port n */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT (0U) /*! SEC_VIO_INFO_WRITE - security violation access read/write indicator. @@ -2827,6 +3102,7 @@ typedef struct { * 0b1..Write access. */ #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_WRITE_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT (1U) /*! SEC_VIO_INFO_DATA_ACCESS - security violation access data/code indicator. @@ -2834,9 +3110,13 @@ typedef struct { * 0b1..Data access. */ #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_DATA_ACCESS_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK (0xF0U) #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT (4U) +/*! SEC_VIO_INFO_MASTER_SEC_LEVEL - bit [5:4]: master sec level and privilege level bit [7:6]: anti-pol value for master sec level and privilege level + */ #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SEC_LEVEL_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_MASK (0xF00U) #define AHB_SECURE_CTRL_SEC_VIO_MISC_INFO_SEC_VIO_INFO_MASTER_SHIFT (8U) /*! SEC_VIO_INFO_MASTER - security violation master number @@ -2860,86 +3140,98 @@ typedef struct { /*! @name SEC_VIO_INFO_VALID - security violation address/information registers valid flags */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT (0U) -/*! VIO_INFO_VALID0 - violation information valid flag for AHB layer 0. Write 1 to clear. +/*! VIO_INFO_VALID0 - violation information valid flag for AHB port 0. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID0_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT (1U) -/*! VIO_INFO_VALID1 - violation information valid flag for AHB layer 1. Write 1 to clear. +/*! VIO_INFO_VALID1 - violation information valid flag for AHB port 1. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID1_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK (0x4U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT (2U) -/*! VIO_INFO_VALID2 - violation information valid flag for AHB layer 2. Write 1 to clear. +/*! VIO_INFO_VALID2 - violation information valid flag for AHB port 2. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID2_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK (0x8U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT (3U) -/*! VIO_INFO_VALID3 - violation information valid flag for AHB layer 3. Write 1 to clear. +/*! VIO_INFO_VALID3 - violation information valid flag for AHB port 3. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID3_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK (0x10U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT (4U) -/*! VIO_INFO_VALID4 - violation information valid flag for AHB layer 4. Write 1 to clear. +/*! VIO_INFO_VALID4 - violation information valid flag for AHB port 4. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID4_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK (0x20U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT (5U) -/*! VIO_INFO_VALID5 - violation information valid flag for AHB layer 5. Write 1 to clear. +/*! VIO_INFO_VALID5 - violation information valid flag for AHB port 5. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID5_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK (0x40U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT (6U) -/*! VIO_INFO_VALID6 - violation information valid flag for AHB layer 6. Write 1 to clear. +/*! VIO_INFO_VALID6 - violation information valid flag for AHB port 6. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID6_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK (0x80U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT (7U) -/*! VIO_INFO_VALID7 - violation information valid flag for AHB layer 7. Write 1 to clear. +/*! VIO_INFO_VALID7 - violation information valid flag for AHB port 7. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID7_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK (0x100U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT (8U) -/*! VIO_INFO_VALID8 - violation information valid flag for AHB layer 8. Write 1 to clear. +/*! VIO_INFO_VALID8 - violation information valid flag for AHB port 8. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID8_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK (0x200U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT (9U) -/*! VIO_INFO_VALID9 - violation information valid flag for AHB layer 9. Write 1 to clear. +/*! VIO_INFO_VALID9 - violation information valid flag for AHB port 9. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID9_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK (0x400U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT (10U) -/*! VIO_INFO_VALID10 - violation information valid flag for AHB layer 10. Write 1 to clear. +/*! VIO_INFO_VALID10 - violation information valid flag for AHB port 10. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_SHIFT)) & AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID10_MASK) + #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_MASK (0x800U) #define AHB_SECURE_CTRL_SEC_VIO_INFO_VALID_VIO_INFO_VALID11_SHIFT (11U) -/*! VIO_INFO_VALID11 - violation information valid flag for AHB layer 11. Write 1 to clear. +/*! VIO_INFO_VALID11 - violation information valid flag for AHB port 11. Write 1 to clear. * 0b0..Not valid. * 0b1..Valid (violation occurred). */ @@ -2948,6 +3240,7 @@ typedef struct { /*! @name SEC_GPIO_MASK0 - Secure GPIO mask for port 0 pins. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT (0U) /*! PIO0_PIN0_SEC_MASK - Secure mask for pin P0_0 @@ -2955,6 +3248,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN0_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT (1U) /*! PIO0_PIN1_SEC_MASK - Secure mask for pin P0_1 @@ -2962,6 +3256,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN1_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK (0x4U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT (2U) /*! PIO0_PIN2_SEC_MASK - Secure mask for pin P0_2 @@ -2969,6 +3264,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN2_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK (0x8U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT (3U) /*! PIO0_PIN3_SEC_MASK - Secure mask for pin P0_3 @@ -2976,6 +3272,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN3_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK (0x10U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT (4U) /*! PIO0_PIN4_SEC_MASK - Secure mask for pin P0_4 @@ -2983,6 +3280,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN4_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK (0x20U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT (5U) /*! PIO0_PIN5_SEC_MASK - Secure mask for pin P0_5 @@ -2990,6 +3288,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN5_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK (0x40U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT (6U) /*! PIO0_PIN6_SEC_MASK - Secure mask for pin P0_6 @@ -2997,6 +3296,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN6_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK (0x80U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT (7U) /*! PIO0_PIN7_SEC_MASK - Secure mask for pin P0_7 @@ -3004,6 +3304,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN7_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK (0x100U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT (8U) /*! PIO0_PIN8_SEC_MASK - Secure mask for pin P0_8 @@ -3011,6 +3312,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN8_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK (0x200U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT (9U) /*! PIO0_PIN9_SEC_MASK - Secure mask for pin P0_9 @@ -3018,6 +3320,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN9_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK (0x400U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT (10U) /*! PIO0_PIN10_SEC_MASK - Secure mask for pin P0_10 @@ -3025,6 +3328,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN10_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK (0x800U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT (11U) /*! PIO0_PIN11_SEC_MASK - Secure mask for pin P0_11 @@ -3032,6 +3336,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN11_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK (0x1000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT (12U) /*! PIO0_PIN12_SEC_MASK - Secure mask for pin P0_12 @@ -3039,6 +3344,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN12_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK (0x2000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT (13U) /*! PIO0_PIN13_SEC_MASK - Secure mask for pin P0_13 @@ -3046,6 +3352,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN13_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK (0x4000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT (14U) /*! PIO0_PIN14_SEC_MASK - Secure mask for pin P0_14 @@ -3053,6 +3360,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN14_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK (0x8000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT (15U) /*! PIO0_PIN15_SEC_MASK - Secure mask for pin P0_15 @@ -3060,6 +3368,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN15_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK (0x10000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT (16U) /*! PIO0_PIN16_SEC_MASK - Secure mask for pin P0_16 @@ -3067,6 +3376,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN16_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK (0x20000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT (17U) /*! PIO0_PIN17_SEC_MASK - Secure mask for pin P0_17 @@ -3074,6 +3384,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN17_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK (0x40000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT (18U) /*! PIO0_PIN18_SEC_MASK - Secure mask for pin P0_18 @@ -3081,6 +3392,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN18_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK (0x80000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT (19U) /*! PIO0_PIN19_SEC_MASK - Secure mask for pin P0_19 @@ -3088,6 +3400,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN19_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK (0x100000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT (20U) /*! PIO0_PIN20_SEC_MASK - Secure mask for pin P0_20 @@ -3095,6 +3408,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN20_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK (0x200000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT (21U) /*! PIO0_PIN21_SEC_MASK - Secure mask for pin P0_21 @@ -3102,6 +3416,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN21_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK (0x400000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT (22U) /*! PIO0_PIN22_SEC_MASK - Secure mask for pin P0_22 @@ -3109,6 +3424,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN22_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK (0x800000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT (23U) /*! PIO0_PIN23_SEC_MASK - Secure mask for pin P0_23 @@ -3116,6 +3432,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN23_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK (0x1000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT (24U) /*! PIO0_PIN24_SEC_MASK - Secure mask for pin P0_24 @@ -3123,6 +3440,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN24_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK (0x2000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT (25U) /*! PIO0_PIN25_SEC_MASK - Secure mask for pin P0_25 @@ -3130,6 +3448,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN25_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK (0x4000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT (26U) /*! PIO0_PIN26_SEC_MASK - Secure mask for pin P0_26 @@ -3137,6 +3456,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN26_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK (0x8000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT (27U) /*! PIO0_PIN27_SEC_MASK - Secure mask for pin P0_27 @@ -3144,6 +3464,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN27_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK (0x10000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT (28U) /*! PIO0_PIN28_SEC_MASK - Secure mask for pin P0_28 @@ -3151,6 +3472,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN28_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK (0x20000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT (29U) /*! PIO0_PIN29_SEC_MASK - Secure mask for pin P0_29 @@ -3158,6 +3480,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN29_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK (0x40000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT (30U) /*! PIO0_PIN30_SEC_MASK - Secure mask for pin P0_30 @@ -3165,6 +3488,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN30_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_MASK (0x80000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK0_PIO0_PIN31_SEC_MASK_SHIFT (31U) /*! PIO0_PIN31_SEC_MASK - Secure mask for pin P0_31 @@ -3176,6 +3500,7 @@ typedef struct { /*! @name SEC_GPIO_MASK1 - Secure GPIO mask for port 1 pins. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT (0U) /*! PIO1_PIN0_SEC_MASK - Secure mask for pin P1_0 @@ -3183,6 +3508,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN0_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT (1U) /*! PIO1_PIN1_SEC_MASK - Secure mask for pin P1_1 @@ -3190,6 +3516,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN1_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK (0x4U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT (2U) /*! PIO1_PIN2_SEC_MASK - Secure mask for pin P1_2 @@ -3197,6 +3524,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN2_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK (0x8U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT (3U) /*! PIO1_PIN3_SEC_MASK - Secure mask for pin P1_3 @@ -3204,6 +3532,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN3_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK (0x10U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT (4U) /*! PIO1_PIN4_SEC_MASK - Secure mask for pin P1_4 @@ -3211,6 +3540,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN4_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK (0x20U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT (5U) /*! PIO1_PIN5_SEC_MASK - Secure mask for pin P1_5 @@ -3218,6 +3548,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN5_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK (0x40U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT (6U) /*! PIO1_PIN6_SEC_MASK - Secure mask for pin P1_6 @@ -3225,6 +3556,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN6_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK (0x80U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT (7U) /*! PIO1_PIN7_SEC_MASK - Secure mask for pin P1_7 @@ -3232,6 +3564,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN7_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK (0x100U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT (8U) /*! PIO1_PIN8_SEC_MASK - Secure mask for pin P1_8 @@ -3239,6 +3572,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN8_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK (0x200U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT (9U) /*! PIO1_PIN9_SEC_MASK - Secure mask for pin P1_9 @@ -3246,6 +3580,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN9_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK (0x400U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT (10U) /*! PIO1_PIN10_SEC_MASK - Secure mask for pin P1_10 @@ -3253,6 +3588,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN10_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK (0x800U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT (11U) /*! PIO1_PIN11_SEC_MASK - Secure mask for pin P1_11 @@ -3260,6 +3596,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN11_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK (0x1000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT (12U) /*! PIO1_PIN12_SEC_MASK - Secure mask for pin P1_12 @@ -3267,6 +3604,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN12_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK (0x2000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT (13U) /*! PIO1_PIN13_SEC_MASK - Secure mask for pin P1_13 @@ -3274,6 +3612,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN13_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK (0x4000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT (14U) /*! PIO1_PIN14_SEC_MASK - Secure mask for pin P1_14 @@ -3281,6 +3620,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN14_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK (0x8000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT (15U) /*! PIO1_PIN15_SEC_MASK - Secure mask for pin P1_15 @@ -3288,6 +3628,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN15_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK (0x10000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT (16U) /*! PIO1_PIN16_SEC_MASK - Secure mask for pin P1_16 @@ -3295,6 +3636,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN16_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK (0x20000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT (17U) /*! PIO1_PIN17_SEC_MASK - Secure mask for pin P1_17 @@ -3302,6 +3644,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN17_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK (0x40000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT (18U) /*! PIO1_PIN18_SEC_MASK - Secure mask for pin P1_18 @@ -3309,6 +3652,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN18_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK (0x80000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT (19U) /*! PIO1_PIN19_SEC_MASK - Secure mask for pin P1_19 @@ -3316,6 +3660,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN19_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK (0x100000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT (20U) /*! PIO1_PIN20_SEC_MASK - Secure mask for pin P1_20 @@ -3323,6 +3668,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN20_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK (0x200000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT (21U) /*! PIO1_PIN21_SEC_MASK - Secure mask for pin P1_21 @@ -3330,6 +3676,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN21_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK (0x400000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT (22U) /*! PIO1_PIN22_SEC_MASK - Secure mask for pin P1_22 @@ -3337,6 +3684,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN22_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK (0x800000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT (23U) /*! PIO1_PIN23_SEC_MASK - Secure mask for pin P1_23 @@ -3344,6 +3692,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN23_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK (0x1000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT (24U) /*! PIO1_PIN24_SEC_MASK - Secure mask for pin P1_24 @@ -3351,6 +3700,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN24_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK (0x2000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT (25U) /*! PIO1_PIN25_SEC_MASK - Secure mask for pin P1_25 @@ -3358,6 +3708,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN25_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK (0x4000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT (26U) /*! PIO1_PIN26_SEC_MASK - Secure mask for pin P1_26 @@ -3365,6 +3716,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN26_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK (0x8000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT (27U) /*! PIO1_PIN27_SEC_MASK - Secure mask for pin P1_27 @@ -3372,6 +3724,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN27_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK (0x10000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT (28U) /*! PIO1_PIN28_SEC_MASK - Secure mask for pin P1_28 @@ -3379,6 +3732,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN28_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK (0x20000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT (29U) /*! PIO1_PIN29_SEC_MASK - Secure mask for pin P1_29 @@ -3386,6 +3740,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN29_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK (0x40000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT (30U) /*! PIO1_PIN30_SEC_MASK - Secure mask for pin P1_30 @@ -3393,6 +3748,7 @@ typedef struct { * 0b0..Pin state is blocked to non-secure world. */ #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_SHIFT)) & AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN30_SEC_MASK_MASK) + #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_MASK (0x80000000U) #define AHB_SECURE_CTRL_SEC_GPIO_MASK1_PIO1_PIN31_SEC_MASK_SHIFT (31U) /*! PIO1_PIN31_SEC_MASK - Secure mask for pin P1_31 @@ -3404,6 +3760,7 @@ typedef struct { /*! @name SEC_CPU_INT_MASK0 - Secure Interrupt mask for CPU1 */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT (0U) /*! SYS_IRQ - Watchdog Timer, Brown Out Detectors and Flash Controller interrupts @@ -3411,6 +3768,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SYS_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT (1U) /*! SDMA0_IRQ - System DMA 0 (non-secure) interrupt. @@ -3418,6 +3776,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SDMA0_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK (0x4U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT (2U) /*! GPIO_GLOBALINT0_IRQ - GPIO Group 0 interrupt. @@ -3425,6 +3784,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT0_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK (0x8U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT (3U) /*! GPIO_GLOBALINT1_IRQ - GPIO Group 1 interrupt. @@ -3432,6 +3792,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_GLOBALINT1_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK (0x10U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT (4U) /*! GPIO_INT0_IRQ0 - Pin interrupt 0 or pattern match engine slice 0 interrupt. @@ -3439,6 +3800,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ0_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK (0x20U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT (5U) /*! GPIO_INT0_IRQ1 - Pin interrupt 1 or pattern match engine slice 1 interrupt. @@ -3446,6 +3808,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ1_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK (0x40U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT (6U) /*! GPIO_INT0_IRQ2 - Pin interrupt 2 or pattern match engine slice 2 interrupt. @@ -3453,6 +3816,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ2_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK (0x80U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT (7U) /*! GPIO_INT0_IRQ3 - Pin interrupt 3 or pattern match engine slice 3 interrupt. @@ -3460,6 +3824,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_GPIO_INT0_IRQ3_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK (0x100U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT (8U) /*! UTICK_IRQ - Micro Tick Timer interrupt. @@ -3467,6 +3832,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_UTICK_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK (0x200U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT (9U) /*! MRT_IRQ - Multi-Rate Timer interrupt. @@ -3474,6 +3840,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MRT_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK (0x400U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT (10U) /*! CTIMER0_IRQ - Standard counter/timer 0 interrupt. @@ -3481,6 +3848,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER0_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK (0x800U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT (11U) /*! CTIMER1_IRQ - Standard counter/timer 1 interrupt. @@ -3488,6 +3856,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER1_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK (0x1000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT (12U) /*! SCT_IRQ - SCTimer/PWM interrupt. @@ -3495,6 +3864,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_SCT_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK (0x2000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT (13U) /*! CTIMER3_IRQ - Standard counter/timer 3 interrupt. @@ -3502,6 +3872,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_CTIMER3_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK (0x4000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT (14U) /*! FLEXCOMM0_IRQ - Flexcomm 0 interrupt (USART, SPI, I2C, I2S). @@ -3509,6 +3880,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM0_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK (0x8000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT (15U) /*! FLEXCOMM1_IRQ - Flexcomm 1 interrupt (USART, SPI, I2C, I2S). @@ -3516,6 +3888,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM1_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK (0x10000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT (16U) /*! FLEXCOMM2_IRQ - Flexcomm 2 interrupt (USART, SPI, I2C, I2S). @@ -3523,6 +3896,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM2_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK (0x20000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT (17U) /*! FLEXCOMM3_IRQ - Flexcomm 3 interrupt (USART, SPI, I2C, I2S). @@ -3530,6 +3904,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM3_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK (0x40000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT (18U) /*! FLEXCOMM4_IRQ - Flexcomm 4 interrupt (USART, SPI, I2C, I2S). @@ -3537,6 +3912,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM4_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK (0x80000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT (19U) /*! FLEXCOMM5_IRQ - Flexcomm 5 interrupt (USART, SPI, I2C, I2S). @@ -3544,6 +3920,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM5_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK (0x100000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT (20U) /*! FLEXCOMM6_IRQ - Flexcomm 6 interrupt (USART, SPI, I2C, I2S). @@ -3551,6 +3928,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM6_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK (0x200000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT (21U) /*! FLEXCOMM7_IRQ - Flexcomm 7 interrupt (USART, SPI, I2C, I2S). @@ -3558,6 +3936,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_FLEXCOMM7_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK (0x400000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT (22U) /*! ADC_IRQ - General Purpose ADC interrupt. @@ -3565,6 +3944,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ADC_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK (0x800000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT (23U) /*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. @@ -3572,13 +3952,15 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED0_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT (24U) -/*! ACMP_CAPT0_IRQ - Analog Comparator interrupt. + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT (24U) +/*! ACMP_IRQ - Analog Comparator interrupt. * 0b0.. * 0b1.. */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_CAPT0_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_ACMP_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK (0x2000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT (25U) /*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. @@ -3586,6 +3968,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED1_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK (0x4000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT (26U) /*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. @@ -3593,6 +3976,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED2_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK (0x8000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT (27U) /*! USB0_NEEDCLK - USB Full Speed Controller Clock request interrupt. @@ -3600,13 +3984,15 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_NEEDCLK_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK (0x10000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT (28U) -/*! USB0_IRQ - USB High Speed Controller interrupt. +/*! USB0_IRQ - USB Full Speed Controller interrupt. * 0b0.. * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_USB0_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK (0x20000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT (29U) /*! RTC_IRQ - RTC_LITE0_ALARM_IRQ, RTC_LITE0_WAKEUP_IRQ @@ -3614,6 +4000,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RTC_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK (0x40000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT (30U) /*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. @@ -3621,6 +4008,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_RESERVED3_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_MASK (0x80000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK0_MAILBOX_IRQ_SHIFT (31U) /*! MAILBOX_IRQ - Mailbox interrupt. @@ -3632,6 +4020,7 @@ typedef struct { /*! @name SEC_CPU_INT_MASK1 - Secure Interrupt mask for CPU1 */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK (0x1U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT (0U) /*! GPIO_INT0_IRQ4 - Pin interrupt 4 or pattern match engine slice 4 interrupt. @@ -3639,6 +4028,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ4_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK (0x2U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT (1U) /*! GPIO_INT0_IRQ5 - Pin interrupt 5 or pattern match engine slice 5 interrupt. @@ -3646,6 +4036,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ5_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK (0x4U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT (2U) /*! GPIO_INT0_IRQ6 - Pin interrupt 6 or pattern match engine slice 6 interrupt. @@ -3653,6 +4044,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ6_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK (0x8U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT (3U) /*! GPIO_INT0_IRQ7 - Pin interrupt 7 or pattern match engine slice 7 interrupt. @@ -3660,6 +4052,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_GPIO_INT0_IRQ7_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK (0x10U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT (4U) /*! CTIMER2_IRQ - Standard counter/timer 2 interrupt. @@ -3667,6 +4060,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER2_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK (0x20U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT (5U) /*! CTIMER4_IRQ - Standard counter/timer 4 interrupt. @@ -3674,6 +4068,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CTIMER4_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK (0x40U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT (6U) /*! OS_EVENT_TIMER_IRQ - OS Event Timer and OS Event Timer Wakeup interrupts @@ -3681,6 +4076,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_OS_EVENT_TIMER_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK (0x80U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT (7U) /*! RESERVED0 - Reserved. Read value is undefined, only zero should be written. @@ -3688,6 +4084,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED0_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK (0x100U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT (8U) /*! RESERVED1 - Reserved. Read value is undefined, only zero should be written. @@ -3695,6 +4092,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED1_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK (0x200U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT (9U) /*! RESERVED2 - Reserved. Read value is undefined, only zero should be written. @@ -3702,6 +4100,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED2_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK (0x400U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT (10U) /*! SDIO_IRQ - SDIO Controller interrupt. @@ -3709,6 +4108,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDIO_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK (0x800U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT (11U) /*! RESERVED3 - Reserved. Read value is undefined, only zero should be written. @@ -3716,6 +4116,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED3_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK (0x1000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT (12U) /*! RESERVED4 - Reserved. Read value is undefined, only zero should be written. @@ -3723,6 +4124,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED4_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK (0x2000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT (13U) /*! RESERVED5 - Reserved. Read value is undefined, only zero should be written. @@ -3730,13 +4132,15 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_RESERVED5_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK (0x4000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT (14U) -/*! USB1_UTMI_IRQ - USB High Speed Controller UTMI interrupt. + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK (0x4000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT (14U) +/*! USB1_PHY_IRQ - USB High Speed PHY Controller interrupt. * 0b0.. * 0b1.. */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_UTMI_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_PHY_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK (0x8000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT (15U) /*! USB1_IRQ - USB High Speed Controller interrupt. @@ -3744,6 +4148,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK (0x10000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT (16U) /*! USB1_NEEDCLK - USB High Speed Controller Clock request interrupt. @@ -3751,6 +4156,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_USB1_NEEDCLK_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK (0x20000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT (17U) /*! SEC_HYPERVISOR_CALL_IRQ - Secure fault Hyper Visor call interrupt. @@ -3758,6 +4164,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_HYPERVISOR_CALL_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK (0x40000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT (18U) /*! SEC_GPIO_INT0_IRQ0 - Secure Pin interrupt 0 or pattern match engine slice 0 interrupt. @@ -3765,6 +4172,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ0_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK (0x80000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT (19U) /*! SEC_GPIO_INT0_IRQ1 - Secure Pin interrupt 1 or pattern match engine slice 1 interrupt. @@ -3772,6 +4180,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_GPIO_INT0_IRQ1_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK (0x100000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT (20U) /*! PLU_IRQ - Programmable Look-Up Controller interrupt. @@ -3779,6 +4188,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PLU_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK (0x200000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT (21U) /*! SEC_VIO_IRQ - Security Violation interrupt. @@ -3786,6 +4196,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SEC_VIO_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK (0x400000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT (22U) /*! SHA_IRQ - HASH-AES interrupt. @@ -3793,6 +4204,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SHA_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK (0x800000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT (23U) /*! CASPER_IRQ - CASPER interrupt. @@ -3800,13 +4212,15 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_CASPER_IRQ_MASK) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK (0x1000000U) -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT (24U) -/*! QDDKEY_IRQ - PUF interrupt. + +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK (0x1000000U) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT (24U) +/*! PUFKEY_IRQ - PUF interrupt. * 0b0.. * 0b1.. */ -#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_QDDKEY_IRQ_MASK) +#define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PUFKEY_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK (0x2000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT (25U) /*! PQ_IRQ - Power Quad interrupt. @@ -3814,6 +4228,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_PQ_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK (0x4000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT (26U) /*! SDMA1_IRQ - System DMA 1 (Secure) interrupt @@ -3821,6 +4236,7 @@ typedef struct { * 0b1.. */ #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_SHIFT)) & AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_SDMA1_IRQ_MASK) + #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_MASK (0x8000000U) #define AHB_SECURE_CTRL_SEC_CPU_INT_MASK1_LSPI_HS_IRQ_SHIFT (27U) /*! LSPI_HS_IRQ - High Speed SPI interrupt @@ -3832,6 +4248,7 @@ typedef struct { /*! @name SEC_MASK_LOCK - Security General Purpose register access control. */ /*! @{ */ + #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK (0x3U) #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT (0U) /*! SEC_GPIO_MASK0_LOCK - SEC_GPIO_MASK0 register write-lock. @@ -3839,6 +4256,7 @@ typedef struct { * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK0_LOCK_MASK) + #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK (0xCU) #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT (2U) /*! SEC_GPIO_MASK1_LOCK - SEC_GPIO_MASK1 register write-lock. @@ -3846,6 +4264,7 @@ typedef struct { * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_GPIO_MASK1_LOCK_MASK) + #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK (0x300U) #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT (8U) /*! SEC_CPU1_INT_MASK0_LOCK - SEC_CPU_INT_MASK0 register write-lock. @@ -3853,6 +4272,7 @@ typedef struct { * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_SHIFT)) & AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK0_LOCK_MASK) + #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_MASK (0xC00U) #define AHB_SECURE_CTRL_SEC_MASK_LOCK_SEC_CPU1_INT_MASK1_LOCK_SHIFT (10U) /*! SEC_CPU1_INT_MASK1_LOCK - SEC_CPU_INT_MASK1 register write-lock. @@ -3864,24 +4284,27 @@ typedef struct { /*! @name MASTER_SEC_LEVEL - master secure level register */ /*! @{ */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT (4U) -/*! MCM33C - Micro-CM33 (CPU1) Code bus. + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33C_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT (6U) -/*! MCM33S - Micro-CM33 (CPU1) System bus. +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1C_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. * 0b00..Non-secure and Non-priviledge user access allowed. * 0b01..Non-secure and Privilege access allowed. * 0b10..Secure and Non-priviledge user access allowed. * 0b11..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MCM33S_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_CPU1S_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK (0x300U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT (8U) /*! USBFSD - USB Full Speed Device. @@ -3891,6 +4314,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSD_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK (0xC00U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT (10U) /*! SDMA0 - System DMA 0. @@ -3900,6 +4324,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA0_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK (0x30000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT (16U) /*! SDIO - SDIO. @@ -3909,6 +4334,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDIO_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK (0xC0000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT (18U) /*! PQ - Power Quad. @@ -3918,6 +4344,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_PQ_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK (0x300000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT (20U) /*! HASH - Hash. @@ -3927,6 +4354,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_HASH_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK (0xC00000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT (22U) /*! USBFSH - USB Full speed Host. @@ -3936,6 +4364,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_USBFSH_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK (0x3000000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT (24U) /*! SDMA1 - System DMA 1 security level. @@ -3945,6 +4374,7 @@ typedef struct { * 0b11..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_LEVEL_SDMA1_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_MASK (0xC0000000U) #define AHB_SECURE_CTRL_MASTER_SEC_LEVEL_MASTER_SEC_LEVEL_LOCK_SHIFT (30U) /*! MASTER_SEC_LEVEL_LOCK - MASTER_SEC_LEVEL write-lock. @@ -3956,24 +4386,27 @@ typedef struct { /*! @name MASTER_SEC_ANTI_POL_REG - master secure level anti-pole register */ /*! @{ */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK (0x30U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT (4U) -/*! MCM33C - Micro-CM33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33C) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK (0x30U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT (4U) +/*! CPU1C - Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) * 0b11..Non-secure and Non-priviledge user access allowed. * 0b10..Non-secure and Privilege access allowed. * 0b01..Secure and Non-priviledge user access allowed. * 0b00..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33C_MASK) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK (0xC0U) -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT (6U) -/*! MCM33S - Micro-CM33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33S) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1C_MASK) + +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK (0xC0U) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT (6U) +/*! CPU1S - Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) * 0b11..Non-secure and Non-priviledge user access allowed. * 0b10..Non-secure and Privilege access allowed. * 0b01..Secure and Non-priviledge user access allowed. * 0b00..Secure and Priviledge user access allowed. */ -#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MCM33S_MASK) +#define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_CPU1S_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK (0x300U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT (8U) /*! USBFSD - USB Full Speed Device. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSD) @@ -3983,6 +4416,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSD_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK (0xC00U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT (10U) /*! SDMA0 - System DMA 0. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA0) @@ -3992,6 +4426,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA0_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK (0x30000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT (16U) /*! SDIO - SDIO. Must be equal to NOT(MASTER_SEC_LEVEL.SDIO) @@ -4001,6 +4436,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDIO_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK (0xC0000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT (18U) /*! PQ - Power Quad. Must be equal to NOT(MASTER_SEC_LEVEL.PQ) @@ -4010,6 +4446,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_PQ_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK (0x300000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT (20U) /*! HASH - Hash. Must be equal to NOT(MASTER_SEC_LEVEL.HASH) @@ -4019,6 +4456,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_HASH_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK (0xC00000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT (22U) /*! USBFSH - USB Full speed Host. Must be equal to NOT(MASTER_SEC_LEVEL.USBFSH) @@ -4028,6 +4466,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_USBFSH_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK (0x3000000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT (24U) /*! SDMA1 - System DMA 1 security level. Must be equal to NOT(MASTER_SEC_LEVEL.SDMA1) @@ -4037,6 +4476,7 @@ typedef struct { * 0b00..Secure and Priviledge user access allowed. */ #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_SDMA1_MASK) + #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK (0xC0000000U) #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT (30U) /*! MASTER_SEC_LEVEL_ANTIPOL_LOCK - MASTER_SEC_ANTI_POL_REG register write-lock. @@ -4046,107 +4486,121 @@ typedef struct { #define AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_SHIFT)) & AHB_SECURE_CTRL_MASTER_SEC_ANTI_POL_REG_MASTER_SEC_LEVEL_ANTIPOL_LOCK_MASK) /*! @} */ -/*! @name CM33_LOCK_REG - Miscalleneous control signals for in CM33 (CPU0) */ +/*! @name CPU0_LOCK_REG - Miscalleneous control signals for in Cortex M33 (CPU0) */ /*! @{ */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - CM33 (CPU0) VTOR_NS register write-lock. + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - Cortex M33 (CPU0) VTOR_NS register write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_VTOR_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - CM33 (CPU0) non-secure MPU register write-lock. +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - Cortex M33 (CPU0) non-secure MPU register write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_NS_MPU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) -/*! LOCK_S_VTAIRCR - CM33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK (0x30U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT (4U) +/*! LOCK_S_VTAIRCR - Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_VTAIRCR_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT (6U) -/*! LOCK_S_MPU - CM33 (CPU0) Secure MPU registers write-lock. +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_VTAIRCR_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK (0xC0U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT (6U) +/*! LOCK_S_MPU - Cortex M33 (CPU0) Secure MPU registers write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_S_MPU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK (0x300U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT (8U) -/*! LOCK_SAU - CM33 (CPU0) SAU registers write-lock. +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_S_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK (0x300U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT (8U) +/*! LOCK_SAU - Cortex M33 (CPU0) SAU registers write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_LOCK_SAU_MASK) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT (30U) -/*! CM33_LOCK_REG_LOCK - CM33_LOCK_REG write-lock. +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_LOCK_SAU_MASK) + +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU0_LOCK_REG_LOCK - CPU0_LOCK_REG write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CM33_LOCK_REG_CM33_LOCK_REG_LOCK_MASK) +#define AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU0_LOCK_REG_CPU0_LOCK_REG_LOCK_MASK) /*! @} */ -/*! @name MCM33_LOCK_REG - Miscalleneous control signals for in micro-CM33 (CPU1) */ +/*! @name CPU1_LOCK_REG - Miscalleneous control signals for in micro-Cortex M33 (CPU1) */ /*! @{ */ -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) -/*! LOCK_NS_VTOR - micro-CM33 (CPU1) VTOR_NS register write-lock. + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK (0x3U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT (0U) +/*! LOCK_NS_VTOR - micro-Cortex M33 (CPU1) VTOR_NS register write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_VTOR_MASK) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) -/*! LOCK_NS_MPU - micro-CM33 (CPU1) non-secure MPU register write-lock. +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_VTOR_MASK) + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK (0xCU) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT (2U) +/*! LOCK_NS_MPU - micro-Cortex M33 (CPU1) non-secure MPU register write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_LOCK_NS_MPU_MASK) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK (0xC0000000U) -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT (30U) -/*! MCM33_LOCK_REG_LOCK - MCM33_LOCK_REG write-lock. +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_LOCK_NS_MPU_MASK) + +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK (0xC0000000U) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT (30U) +/*! CPU1_LOCK_REG_LOCK - CPU1_LOCK_REG write-lock. * 0b10..Writable. * 0b01..Restricted mode. */ -#define AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_MCM33_LOCK_REG_MCM33_LOCK_REG_LOCK_MASK) +#define AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_SHIFT)) & AHB_SECURE_CTRL_CPU1_LOCK_REG_CPU1_LOCK_REG_LOCK_MASK) /*! @} */ /*! @name MISC_CTRL_DP_REG - secure control duplicate register */ /*! @{ */ + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK (0x3U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - write lock. +/*! WRITE_LOCK - Write lock. * 0b10..Secure control registers can be written. * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_WRITE_LOCK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. * 0b10..Disable check. * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_SECURE_CHECKING_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. * 0b10..Disable check. * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_S_PRIV_CHECK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. * 0b10..Disable check. * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_ENABLE_NS_PRIV_CHECK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. @@ -4154,6 +4608,7 @@ typedef struct { * 0b01..Disable abort fort secure checker. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_VIOLATION_ABORT_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. @@ -4161,6 +4616,7 @@ typedef struct { * 0b01..Simple master in tier mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. @@ -4168,6 +4624,7 @@ typedef struct { * 0b01..Smart master in tier mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_DP_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_MASK (0xC000U) #define AHB_SECURE_CTRL_MISC_CTRL_DP_REG_IDAU_ALL_NS_SHIFT (14U) /*! IDAU_ALL_NS - Disable IDAU. @@ -4179,34 +4636,39 @@ typedef struct { /*! @name MISC_CTRL_REG - secure control register */ /*! @{ */ + #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK (0x3U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT (0U) -/*! WRITE_LOCK - write lock. +/*! WRITE_LOCK - Write lock. * 0b10..Secure control registers can be written. * 0b01..Restricted mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_WRITE_LOCK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK (0xCU) #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT (2U) -/*! ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. +/*! ENABLE_SECURE_CHECKING - Enable secure check for AHB matrix. * 0b10..Disable check. - * 0b01..Restricted mode. + * 0b01..Enabled (restricted mode) */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_SECURE_CHECKING_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK (0x30U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT (4U) -/*! ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. +/*! ENABLE_S_PRIV_CHECK - Enable secure privilege check for AHB matrix. * 0b10..Disable check. - * 0b01..Restricted mode. + * 0b01..Enabled (restricted mode) */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_S_PRIV_CHECK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK (0xC0U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT (6U) -/*! ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. +/*! ENABLE_NS_PRIV_CHECK - Enable non-secure privilege check for AHB matrix. * 0b10..Disable check. - * 0b01..Restricted mode. + * 0b01..Enabled (restricted mode) */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_ENABLE_NS_PRIV_CHECK_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK (0x300U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT (8U) /*! DISABLE_VIOLATION_ABORT - Disable secure violation abort. @@ -4214,6 +4676,7 @@ typedef struct { * 0b01..Disable abort fort secure checker. */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_VIOLATION_ABORT_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK (0xC00U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT (10U) /*! DISABLE_SIMPLE_MASTER_STRICT_MODE - Disable simple master strict mode. @@ -4221,6 +4684,7 @@ typedef struct { * 0b01..Simple master in tier mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SIMPLE_MASTER_STRICT_MODE_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK (0x3000U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT (12U) /*! DISABLE_SMART_MASTER_STRICT_MODE - Disable smart master strict mode. @@ -4228,6 +4692,7 @@ typedef struct { * 0b01..Smart master in tier mode. */ #define AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE(x) (((uint32_t)(((uint32_t)(x)) << AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_SHIFT)) & AHB_SECURE_CTRL_MISC_CTRL_REG_DISABLE_SMART_MASTER_STRICT_MODE_MASK) + #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_MASK (0xC000U) #define AHB_SECURE_CTRL_MISC_CTRL_REG_IDAU_ALL_NS_SHIFT (14U) /*! IDAU_ALL_NS - Disable IDAU. @@ -4244,7 +4709,7 @@ typedef struct { /* AHB_SECURE_CTRL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral AHB_SECURE_CTRL base address */ #define AHB_SECURE_CTRL_BASE (0x500AC000u) /** Peripheral AHB_SECURE_CTRL base address */ @@ -4296,8 +4761,8 @@ typedef struct { __I uint32_t FRO192M_STATUS; /**< 192MHz Free Running OScillator (FRO) Status register, offset: 0x14 */ __IO uint32_t ADC_CTRL; /**< General Purpose ADC VBAT Divider branch control, offset: 0x18 */ uint8_t RESERVED_1[4]; - __IO uint32_t XO32M_CTRL; /**< 32 MHz Crystal Oscillator Control register, offset: 0x20 */ - __I uint32_t XO32M_STATUS; /**< 32 MHz Crystal Oscillator Status register, offset: 0x24 */ + __IO uint32_t XO32M_CTRL; /**< High speed Crystal Oscillator Control register, offset: 0x20 */ + __I uint32_t XO32M_STATUS; /**< High speed Crystal Oscillator Status register, offset: 0x24 */ uint8_t RESERVED_2[8]; __IO uint32_t BOD_DCDC_INT_CTRL; /**< Brown Out Detectors (BoDs) & DCDC interrupts generation control register, offset: 0x30 */ __I uint32_t BOD_DCDC_INT_STATUS; /**< BoDs & DCDC interrupts status register, offset: 0x34 */ @@ -4307,14 +4772,10 @@ typedef struct { __IO uint32_t RINGO2_CTRL; /**< Third Ring Oscillator module control register., offset: 0x48 */ uint8_t RESERVED_4[100]; __IO uint32_t LDO_XO32M; /**< High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register, offset: 0xB0 */ - uint8_t RESERVED_5[12]; - __IO uint32_t XO_CAL_CFG; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register, offset: 0xC0 */ - __IO uint32_t XO_CAL_CMD; /**< All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register., offset: 0xC4 */ - __I uint32_t XO_CAL_STATUS; /**< All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register., offset: 0xC8 */ - uint8_t RESERVED_6[52]; + __IO uint32_t AUX_BIAS; /**< AUX_BIAS, offset: 0xB4 */ + uint8_t RESERVED_5[72]; __IO uint32_t USBHS_PHY_CTRL; /**< USB High Speed Phy Control, offset: 0x100 */ __IO uint32_t USBHS_PHY_TRIM; /**< USB High Speed Phy Trim values, offset: 0x104 */ - __I uint32_t USBHS_PHY_STATUS; /**< USB High Speed Phy Status, offset: 0x108 */ } ANACTRL_Type; /* ---------------------------------------------------------------------------- @@ -4328,6 +4789,7 @@ typedef struct { /*! @name ANALOG_CTRL_CFG - Various Analog blocks configuration (like FRO 192MHz trimmings source ...) */ /*! @{ */ + #define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_MASK (0x1U) #define ANACTRL_ANALOG_CTRL_CFG_FRO192M_TRIM_SRC_SHIFT (0U) /*! FRO192M_TRIM_SRC - FRO192M trimming and 'Enable' source. @@ -4339,12 +4801,7 @@ typedef struct { /*! @name ANALOG_CTRL_STATUS - Analog Macroblock Identity registers, Flash Status registers */ /*! @{ */ -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK (0x3FU) -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT (0U) -#define ANACTRL_ANALOG_CTRL_STATUS_PMU_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK (0xFC0U) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT (6U) -#define ANACTRL_ANALOG_CTRL_STATUS_OSC_ID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK) + #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK (0x1000U) #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT (12U) /*! FLASH_PWRDWN - Flash Power Down status. @@ -4352,6 +4809,7 @@ typedef struct { * 0b1..Flash is in power down mode. */ #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK) + #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK (0x2000U) #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT (13U) /*! FLASH_INIT_ERROR - Flash initialization error status. @@ -4359,29 +4817,29 @@ typedef struct { * 0b1..At least one error occured during flash initialization.. */ #define ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK (0xF0000000U) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT (28U) -#define ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_SHIFT)) & ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK) /*! @} */ /*! @name FREQ_ME_CTRL - Frequency Measure function control register */ /*! @{ */ + #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK (0x7FFFFFFFU) #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT (0U) +/*! CAPVAL_SCALE - Frequency measure result /Frequency measur scale + */ #define ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_SHIFT)) & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK) + #define ANACTRL_FREQ_ME_CTRL_PROG_MASK (0x80000000U) #define ANACTRL_FREQ_ME_CTRL_PROG_SHIFT (31U) +/*! PROG - Set this bit to one to initiate a frequency measurement cycle. Hardware clears this bit + * when the measurement cycle has completed and there is valid capture data in the CAPVAL field + * (bits 30:0). + */ #define ANACTRL_FREQ_ME_CTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FREQ_ME_CTRL_PROG_SHIFT)) & ANACTRL_FREQ_ME_CTRL_PROG_MASK) /*! @} */ /*! @name FRO192M_CTRL - 192MHz Free Running OScillator (FRO) Control register */ /*! @{ */ -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK (0x3FU) -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT (0U) -#define ANACTRL_FRO192M_CTRL_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_BIAS_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_BIAS_TRIM_MASK) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK (0x3F80U) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT (7U) -#define ANACTRL_FRO192M_CTRL_TEMP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_TEMP_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_TEMP_TRIM_MASK) + #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK (0x4000U) #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT (14U) /*! ENA_12MHZCLK - 12 MHz clock control. @@ -4389,25 +4847,35 @@ typedef struct { * 0b1..12 MHz clock is enabled. */ #define ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) + #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK (0x8000U) #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT (15U) /*! ENA_48MHZCLK - 48 MHz clock control. - * 0b0..48 MHz clock is disabled. + * 0b0..Reserved. * 0b1..48 MHz clock is enabled. */ #define ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK) + #define ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK (0xFF0000U) #define ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT (16U) +/*! DAC_TRIM - Frequency trim. + */ #define ANACTRL_FRO192M_CTRL_DAC_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_DAC_TRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_DAC_TRIM_MASK) + #define ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK (0x1000000U) #define ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT (24U) +/*! USBCLKADJ - If this bit is set and the USB peripheral is enabled into full speed device mode, + * the USB block will provide FRO clock adjustments to lock it to the host clock using the SOF + * packets. + */ #define ANACTRL_FRO192M_CTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBCLKADJ_SHIFT)) & ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK) + #define ANACTRL_FRO192M_CTRL_USBMODCHG_MASK (0x2000000U) #define ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT (25U) +/*! USBMODCHG - If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. + */ #define ANACTRL_FRO192M_CTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_USBMODCHG_SHIFT)) & ANACTRL_FRO192M_CTRL_USBMODCHG_MASK) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK (0x30000000U) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT (28U) -#define ANACTRL_FRO192M_CTRL_ATB_CTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ATB_CTRL_SHIFT)) & ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK) + #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK (0x40000000U) #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT (30U) /*! ENA_96MHZCLK - 96 MHz clock control. @@ -4415,13 +4883,17 @@ typedef struct { * 0b1..96 MHz clock is enabled. */ #define ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_SHIFT)) & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) + #define ANACTRL_FRO192M_CTRL_WRTRIM_MASK (0x80000000U) #define ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT (31U) +/*! WRTRIM - This must be written to 1 to modify the BIAS_TRIM and TEMP_TRIM fields. + */ #define ANACTRL_FRO192M_CTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_CTRL_WRTRIM_SHIFT)) & ANACTRL_FRO192M_CTRL_WRTRIM_MASK) /*! @} */ /*! @name FRO192M_STATUS - 192MHz Free Running OScillator (FRO) Status register */ /*! @{ */ + #define ANACTRL_FRO192M_STATUS_CLK_VALID_MASK (0x1U) #define ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT (0U) /*! CLK_VALID - Output clock valid signal. Indicates that CCO clock has settled. @@ -4430,13 +4902,19 @@ typedef struct { * FRO192M_CTRL.ENA_12MHZCLK/ENA_48MHZCLK/ENA_96MHZCLK). */ #define ANACTRL_FRO192M_STATUS_CLK_VALID(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_CLK_VALID_SHIFT)) & ANACTRL_FRO192M_STATUS_CLK_VALID_MASK) + #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK (0x2U) #define ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT (1U) +/*! ATB_VCTRL - CCO threshold voltage detector output (signal vcco_ok). Once the CCO voltage crosses + * the threshold voltage of a SLVT transistor, this output signal will go high. It is also + * possible to observe the clk_valid signal. + */ #define ANACTRL_FRO192M_STATUS_ATB_VCTRL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_FRO192M_STATUS_ATB_VCTRL_SHIFT)) & ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK) /*! @} */ /*! @name ADC_CTRL - General Purpose ADC VBAT Divider branch control */ /*! @{ */ + #define ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK (0x1U) #define ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT (0U) /*! VBATDIVENABLE - Switch On/Off VBAT divider branch. @@ -4446,23 +4924,27 @@ typedef struct { #define ANACTRL_ADC_CTRL_VBATDIVENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_ADC_CTRL_VBATDIVENABLE_SHIFT)) & ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK) /*! @} */ -/*! @name XO32M_CTRL - 32 MHz Crystal Oscillator Control register */ +/*! @name XO32M_CTRL - High speed Crystal Oscillator Control register */ /*! @{ */ -#define ANACTRL_XO32M_CTRL_GM_MASK (0xEU) -#define ANACTRL_XO32M_CTRL_GM_SHIFT (1U) -#define ANACTRL_XO32M_CTRL_GM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_GM_SHIFT)) & ANACTRL_XO32M_CTRL_GM_MASK) + #define ANACTRL_XO32M_CTRL_SLAVE_MASK (0x10U) #define ANACTRL_XO32M_CTRL_SLAVE_SHIFT (4U) +/*! SLAVE - Xo in slave mode. + */ #define ANACTRL_XO32M_CTRL_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_SLAVE_SHIFT)) & ANACTRL_XO32M_CTRL_SLAVE_MASK) -#define ANACTRL_XO32M_CTRL_AMP_MASK (0xE0U) -#define ANACTRL_XO32M_CTRL_AMP_SHIFT (5U) -#define ANACTRL_XO32M_CTRL_AMP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_AMP_SHIFT)) & ANACTRL_XO32M_CTRL_AMP_MASK) + #define ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK (0x7F00U) #define ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT (8U) +/*! OSC_CAP_IN - Tune capa banks of High speed Crystal Oscillator input pin + */ #define ANACTRL_XO32M_CTRL_OSC_CAP_IN(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK) + #define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK (0x3F8000U) #define ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT (15U) +/*! OSC_CAP_OUT - Tune capa banks of High speed Crystal Oscillator output pin + */ #define ANACTRL_XO32M_CTRL_OSC_CAP_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK) + #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK (0x400000U) #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT (22U) /*! ACBUF_PASS_ENABLE - Bypass enable of XO AC buffer enable in pll and top level. @@ -4470,48 +4952,27 @@ typedef struct { * 0b1..XO AC buffer bypass is enabled. */ #define ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK) + #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK (0x800000U) #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT (23U) -/*! ENABLE_PLL_USB_OUT - Enable XO 32 MHz output to USB HS PLL. - * 0b0..XO 32 MHz output to USB HS PLL is disabled. - * 0b1..XO 32 MHz output to USB HS PLL is enabled. +/*! ENABLE_PLL_USB_OUT - Enable High speed Crystal oscillator output to USB HS PLL. + * 0b0..High speed Crystal oscillator output to USB HS PLL is disabled. + * 0b1..High speed Crystal oscillator output to USB HS PLL is enabled. */ #define ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) + #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK (0x1000000U) #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT (24U) -/*! ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system. - * 0b0..XO 32 MHz output to CPU system is disabled. - * 0b1..XO 32 MHz output to CPU system is enabled. +/*! ENABLE_SYSTEM_CLK_OUT - Enable High speed Crystal oscillator output to CPU system. + * 0b0..High speed Crystal oscillator output to CPU system is disabled. + * 0b1..High speed Crystal oscillator output to CPU system is enabled. */ #define ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_SHIFT)) & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK (0x2000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT (25U) -/*! CAPTESTSTARTSRCSEL - Source selection for 'xo32k_captest_start' signal. - * 0b0..Sourced from CAPTESTSTART. - * 0b1..Sourced from calibration. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTARTSRCSEL_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK (0x4000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT (26U) -#define ANACTRL_XO32M_CTRL_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTSTART_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTSTART_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK (0x8000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT (27U) -/*! CAPTESTENABLE - Enable signal for captest. - * 0b0..Captest is disabled. - * 0b1..Captest is enabled. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTENABLE_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTENABLE_MASK) -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK (0x10000000U) -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT (28U) -/*! CAPTESTOSCINSEL - Select the input for test. - * 0b0..osc_out (oscillator output) pin. - * 0b1..osc_in (oscillator) pin. - */ -#define ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_SHIFT)) & ANACTRL_XO32M_CTRL_CAPTESTOSCINSEL_MASK) /*! @} */ -/*! @name XO32M_STATUS - 32 MHz Crystal Oscillator Status register */ +/*! @name XO32M_STATUS - High speed Crystal Oscillator Status register */ /*! @{ */ + #define ANACTRL_XO32M_STATUS_XO_READY_MASK (0x1U) #define ANACTRL_XO32M_STATUS_XO_READY_SHIFT (0U) /*! XO_READY - Indicates XO out frequency statibilty. @@ -4523,6 +4984,7 @@ typedef struct { /*! @name BOD_DCDC_INT_CTRL - Brown Out Detectors (BoDs) & DCDC interrupts generation control register */ /*! @{ */ + #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK (0x1U) #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT (0U) /*! BODVBAT_INT_ENABLE - BOD VBAT interrupt control. @@ -4530,9 +4992,13 @@ typedef struct { * 0b1..BOD VBAT interrupt is enabled. */ #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK) + #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK (0x2U) #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT (1U) +/*! BODVBAT_INT_CLEAR - BOD VBAT interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ #define ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK) + #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK (0x4U) #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT (2U) /*! BODCORE_INT_ENABLE - BOD CORE interrupt control. @@ -4540,9 +5006,13 @@ typedef struct { * 0b1..BOD CORE interrupt is enabled. */ #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK) + #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK (0x8U) #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT (3U) +/*! BODCORE_INT_CLEAR - BOD CORE interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ #define ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK) + #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK (0x10U) #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT (4U) /*! DCDC_INT_ENABLE - DCDC interrupt control. @@ -4550,13 +5020,17 @@ typedef struct { * 0b1..DCDC interrupt is enabled. */ #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK) + #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK (0x20U) #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT (5U) +/*! DCDC_INT_CLEAR - DCDC interrupt clear.1: Clear the interrupt. Self-cleared bit. + */ #define ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_SHIFT)) & ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK) /*! @} */ /*! @name BOD_DCDC_INT_STATUS - BoDs & DCDC interrupts status register */ /*! @{ */ + #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK (0x1U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT (0U) /*! BODVBAT_STATUS - BOD VBAT Interrupt status before Interrupt Enable. @@ -4564,6 +5038,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK (0x2U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT (1U) /*! BODVBAT_INT_STATUS - BOD VBAT Interrupt status after Interrupt Enable. @@ -4571,6 +5046,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK (0x4U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT (2U) /*! BODVBAT_VAL - Current value of BOD VBAT power status output. @@ -4578,6 +5054,7 @@ typedef struct { * 0b1..VBAT voltage level is above the threshold. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK (0x8U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT (3U) /*! BODCORE_STATUS - BOD CORE Interrupt status before Interrupt Enable. @@ -4585,6 +5062,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK (0x10U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT (4U) /*! BODCORE_INT_STATUS - BOD CORE Interrupt status after Interrupt Enable. @@ -4592,6 +5070,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK (0x20U) #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT (5U) /*! BODCORE_VAL - Current value of BOD CORE power status output. @@ -4599,6 +5078,7 @@ typedef struct { * 0b1..CORE voltage level is above the threshold. */ #define ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK (0x40U) #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT (6U) /*! DCDC_STATUS - DCDC Interrupt status before Interrupt Enable. @@ -4606,6 +5086,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK (0x80U) #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT (7U) /*! DCDC_INT_STATUS - DCDC Interrupt status after Interrupt Enable. @@ -4613,6 +5094,7 @@ typedef struct { * 0b1..Interrupt pending.. */ #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_SHIFT)) & ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK) + #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK (0x100U) #define ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_SHIFT (8U) /*! DCDC_VAL - Current value of DCDC power status output. @@ -4624,6 +5106,7 @@ typedef struct { /*! @name RINGO0_CTRL - First Ring Oscillator module control register. */ /*! @{ */ + #define ANACTRL_RINGO0_CTRL_SL_MASK (0x1U) #define ANACTRL_RINGO0_CTRL_SL_SHIFT (0U) /*! SL - Select short or long ringo (for all ringos types). @@ -4631,6 +5114,7 @@ typedef struct { * 0b1..Select long ringo (many elements). */ #define ANACTRL_RINGO0_CTRL_SL(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SL_SHIFT)) & ANACTRL_RINGO0_CTRL_SL_MASK) + #define ANACTRL_RINGO0_CTRL_FS_MASK (0x2U) #define ANACTRL_RINGO0_CTRL_FS_SHIFT (1U) /*! FS - Ringo frequency output divider. @@ -4638,6 +5122,7 @@ typedef struct { * 0b1..Low frequency output (frequency lower than 10 MHz). */ #define ANACTRL_RINGO0_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_FS_SHIFT)) & ANACTRL_RINGO0_CTRL_FS_MASK) + #define ANACTRL_RINGO0_CTRL_SWN_SWP_MASK (0xCU) #define ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT (2U) /*! SWN_SWP - PN-Ringos (P-Transistor and N-Transistor processing) control. @@ -4647,6 +5132,7 @@ typedef struct { * 0b11..Don't use. */ #define ANACTRL_RINGO0_CTRL_SWN_SWP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_SWN_SWP_SHIFT)) & ANACTRL_RINGO0_CTRL_SWN_SWP_MASK) + #define ANACTRL_RINGO0_CTRL_PD_MASK (0x10U) #define ANACTRL_RINGO0_CTRL_PD_SHIFT (4U) /*! PD - Ringo module Power control. @@ -4654,6 +5140,7 @@ typedef struct { * 0b1..The Ringo module is disabled. */ #define ANACTRL_RINGO0_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_PD_SHIFT)) & ANACTRL_RINGO0_CTRL_PD_MASK) + #define ANACTRL_RINGO0_CTRL_E_ND0_MASK (0x20U) #define ANACTRL_RINGO0_CTRL_E_ND0_SHIFT (5U) /*! E_ND0 - First NAND2-based ringo control. @@ -4661,6 +5148,7 @@ typedef struct { * 0b1..First NAND2-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_ND0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND0_MASK) + #define ANACTRL_RINGO0_CTRL_E_ND1_MASK (0x40U) #define ANACTRL_RINGO0_CTRL_E_ND1_SHIFT (6U) /*! E_ND1 - Second NAND2-based ringo control. @@ -4668,6 +5156,7 @@ typedef struct { * 0b1..Second NAND2-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_ND1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_ND1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_ND1_MASK) + #define ANACTRL_RINGO0_CTRL_E_NR0_MASK (0x80U) #define ANACTRL_RINGO0_CTRL_E_NR0_SHIFT (7U) /*! E_NR0 - First NOR2-based ringo control. @@ -4675,6 +5164,7 @@ typedef struct { * 0b1..First NOR2-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_NR0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR0_MASK) + #define ANACTRL_RINGO0_CTRL_E_NR1_MASK (0x100U) #define ANACTRL_RINGO0_CTRL_E_NR1_SHIFT (8U) /*! E_NR1 - Second NOR2-based ringo control. @@ -4682,6 +5172,7 @@ typedef struct { * 0b1..Second NORD2-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_NR1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_NR1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_NR1_MASK) + #define ANACTRL_RINGO0_CTRL_E_IV0_MASK (0x200U) #define ANACTRL_RINGO0_CTRL_E_IV0_SHIFT (9U) /*! E_IV0 - First Inverter-based ringo control. @@ -4689,6 +5180,7 @@ typedef struct { * 0b1..First INV-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_IV0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV0_MASK) + #define ANACTRL_RINGO0_CTRL_E_IV1_MASK (0x400U) #define ANACTRL_RINGO0_CTRL_E_IV1_SHIFT (10U) /*! E_IV1 - Second Inverter-based ringo control. @@ -4696,6 +5188,7 @@ typedef struct { * 0b1..Second INV-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_IV1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_IV1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_IV1_MASK) + #define ANACTRL_RINGO0_CTRL_E_PN0_MASK (0x800U) #define ANACTRL_RINGO0_CTRL_E_PN0_SHIFT (11U) /*! E_PN0 - First PN (P-Transistor and N-Transistor processing) monitor control. @@ -4703,6 +5196,7 @@ typedef struct { * 0b1..First PN-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_PN0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN0_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN0_MASK) + #define ANACTRL_RINGO0_CTRL_E_PN1_MASK (0x1000U) #define ANACTRL_RINGO0_CTRL_E_PN1_SHIFT (12U) /*! E_PN1 - Second PN (P-Transistor and N-Transistor processing) monitor control. @@ -4710,16 +5204,24 @@ typedef struct { * 0b1..Second PN-based ringo is enabled. */ #define ANACTRL_RINGO0_CTRL_E_PN1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_E_PN1_SHIFT)) & ANACTRL_RINGO0_CTRL_E_PN1_MASK) + #define ANACTRL_RINGO0_CTRL_DIVISOR_MASK (0xF0000U) #define ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ #define ANACTRL_RINGO0_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO0_CTRL_DIVISOR_MASK) + #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ #define ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK) /*! @} */ /*! @name RINGO1_CTRL - Second Ring Oscillator module control register. */ /*! @{ */ + #define ANACTRL_RINGO1_CTRL_S_MASK (0x1U) #define ANACTRL_RINGO1_CTRL_S_SHIFT (0U) /*! S - Select short or long ringo (for all ringos types). @@ -4727,6 +5229,7 @@ typedef struct { * 0b1..Select long ringo (many elements). */ #define ANACTRL_RINGO1_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_S_SHIFT)) & ANACTRL_RINGO1_CTRL_S_MASK) + #define ANACTRL_RINGO1_CTRL_FS_MASK (0x2U) #define ANACTRL_RINGO1_CTRL_FS_SHIFT (1U) /*! FS - Ringo frequency output divider. @@ -4734,6 +5237,7 @@ typedef struct { * 0b1..Low frequency output (frequency lower than 10 MHz). */ #define ANACTRL_RINGO1_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_FS_SHIFT)) & ANACTRL_RINGO1_CTRL_FS_MASK) + #define ANACTRL_RINGO1_CTRL_PD_MASK (0x4U) #define ANACTRL_RINGO1_CTRL_PD_SHIFT (2U) /*! PD - Ringo module Power control. @@ -4741,6 +5245,7 @@ typedef struct { * 0b1..The Ringo module is disabled. */ #define ANACTRL_RINGO1_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_PD_SHIFT)) & ANACTRL_RINGO1_CTRL_PD_MASK) + #define ANACTRL_RINGO1_CTRL_E_R24_MASK (0x8U) #define ANACTRL_RINGO1_CTRL_E_R24_SHIFT (3U) /*! E_R24 - . @@ -4748,6 +5253,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R24_MASK) + #define ANACTRL_RINGO1_CTRL_E_R35_MASK (0x10U) #define ANACTRL_RINGO1_CTRL_E_R35_SHIFT (4U) /*! E_R35 - . @@ -4755,6 +5261,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO1_CTRL_E_R35_MASK) + #define ANACTRL_RINGO1_CTRL_E_M2_MASK (0x20U) #define ANACTRL_RINGO1_CTRL_E_M2_SHIFT (5U) /*! E_M2 - Metal 2 (M2) monitor control. @@ -4762,6 +5269,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M2_MASK) + #define ANACTRL_RINGO1_CTRL_E_M3_MASK (0x40U) #define ANACTRL_RINGO1_CTRL_E_M3_SHIFT (6U) /*! E_M3 - Metal 3 (M3) monitor control. @@ -4769,6 +5277,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M3_MASK) + #define ANACTRL_RINGO1_CTRL_E_M4_MASK (0x80U) #define ANACTRL_RINGO1_CTRL_E_M4_SHIFT (7U) /*! E_M4 - Metal 4 (M4) monitor control. @@ -4776,6 +5285,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M4_MASK) + #define ANACTRL_RINGO1_CTRL_E_M5_MASK (0x100U) #define ANACTRL_RINGO1_CTRL_E_M5_SHIFT (8U) /*! E_M5 - Metal 5 (M5) monitor control. @@ -4783,16 +5293,24 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO1_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO1_CTRL_E_M5_MASK) + #define ANACTRL_RINGO1_CTRL_DIVISOR_MASK (0xF0000U) #define ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ #define ANACTRL_RINGO1_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO1_CTRL_DIVISOR_MASK) + #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ #define ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK) /*! @} */ /*! @name RINGO2_CTRL - Third Ring Oscillator module control register. */ /*! @{ */ + #define ANACTRL_RINGO2_CTRL_S_MASK (0x1U) #define ANACTRL_RINGO2_CTRL_S_SHIFT (0U) /*! S - Select short or long ringo (for all ringos types). @@ -4800,6 +5318,7 @@ typedef struct { * 0b1..Select long ringo (many elements). */ #define ANACTRL_RINGO2_CTRL_S(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_S_SHIFT)) & ANACTRL_RINGO2_CTRL_S_MASK) + #define ANACTRL_RINGO2_CTRL_FS_MASK (0x2U) #define ANACTRL_RINGO2_CTRL_FS_SHIFT (1U) /*! FS - Ringo frequency output divider. @@ -4807,6 +5326,7 @@ typedef struct { * 0b1..Low frequency output (frequency lower than 10 MHz). */ #define ANACTRL_RINGO2_CTRL_FS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_FS_SHIFT)) & ANACTRL_RINGO2_CTRL_FS_MASK) + #define ANACTRL_RINGO2_CTRL_PD_MASK (0x4U) #define ANACTRL_RINGO2_CTRL_PD_SHIFT (2U) /*! PD - Ringo module Power control. @@ -4814,6 +5334,7 @@ typedef struct { * 0b1..The Ringo module is disabled. */ #define ANACTRL_RINGO2_CTRL_PD(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_PD_SHIFT)) & ANACTRL_RINGO2_CTRL_PD_MASK) + #define ANACTRL_RINGO2_CTRL_E_R24_MASK (0x8U) #define ANACTRL_RINGO2_CTRL_E_R24_SHIFT (3U) /*! E_R24 - . @@ -4821,6 +5342,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_R24(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R24_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R24_MASK) + #define ANACTRL_RINGO2_CTRL_E_R35_MASK (0x10U) #define ANACTRL_RINGO2_CTRL_E_R35_SHIFT (4U) /*! E_R35 - . @@ -4828,6 +5350,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_R35(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_R35_SHIFT)) & ANACTRL_RINGO2_CTRL_E_R35_MASK) + #define ANACTRL_RINGO2_CTRL_E_M2_MASK (0x20U) #define ANACTRL_RINGO2_CTRL_E_M2_SHIFT (5U) /*! E_M2 - Metal 2 (M2) monitor control. @@ -4835,6 +5358,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_M2(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M2_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M2_MASK) + #define ANACTRL_RINGO2_CTRL_E_M3_MASK (0x40U) #define ANACTRL_RINGO2_CTRL_E_M3_SHIFT (6U) /*! E_M3 - Metal 3 (M3) monitor control. @@ -4842,6 +5366,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_M3(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M3_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M3_MASK) + #define ANACTRL_RINGO2_CTRL_E_M4_MASK (0x80U) #define ANACTRL_RINGO2_CTRL_E_M4_SHIFT (7U) /*! E_M4 - Metal 4 (M4) monitor control. @@ -4849,6 +5374,7 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_M4(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M4_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M4_MASK) + #define ANACTRL_RINGO2_CTRL_E_M5_MASK (0x100U) #define ANACTRL_RINGO2_CTRL_E_M5_SHIFT (8U) /*! E_M5 - Metal 5 (M5) monitor control. @@ -4856,16 +5382,24 @@ typedef struct { * 0b1..Ringo is enabled. */ #define ANACTRL_RINGO2_CTRL_E_M5(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_E_M5_SHIFT)) & ANACTRL_RINGO2_CTRL_E_M5_MASK) + #define ANACTRL_RINGO2_CTRL_DIVISOR_MASK (0xF0000U) #define ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT (16U) +/*! DIVISOR - Ringo out Clock divider value. Frequency Output = Frequency input / (DIViSOR+1). (minimum = Frequency input / 16) + */ #define ANACTRL_RINGO2_CTRL_DIVISOR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIVISOR_SHIFT)) & ANACTRL_RINGO2_CTRL_DIVISOR_MASK) + #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK (0x80000000U) #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT (31U) +/*! DIV_UPDATE_REQ - Ringo clock out Divider status flag. Set when a change is made to the divider + * value, cleared when the change is complete. + */ #define ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_SHIFT)) & ANACTRL_RINGO2_CTRL_DIV_UPDATE_REQ_MASK) /*! @} */ /*! @name LDO_XO32M - High Speed Crystal Oscillator (12 MHz - 32 MHz) Voltage Source Supply Control register */ /*! @{ */ + #define ANACTRL_LDO_XO32M_BYPASS_MASK (0x2U) #define ANACTRL_LDO_XO32M_BYPASS_SHIFT (1U) /*! BYPASS - Activate LDO bypass. @@ -4873,6 +5407,7 @@ typedef struct { * 0b1..Activate LDO bypass. */ #define ANACTRL_LDO_XO32M_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_BYPASS_SHIFT)) & ANACTRL_LDO_XO32M_BYPASS_MASK) + #define ANACTRL_LDO_XO32M_HIGHZ_MASK (0x4U) #define ANACTRL_LDO_XO32M_HIGHZ_SHIFT (2U) /*! HIGHZ - . @@ -4880,6 +5415,7 @@ typedef struct { * 0b1..Output in High Impedance state. */ #define ANACTRL_LDO_XO32M_HIGHZ(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_HIGHZ_SHIFT)) & ANACTRL_LDO_XO32M_HIGHZ_MASK) + #define ANACTRL_LDO_XO32M_VOUT_MASK (0x38U) #define ANACTRL_LDO_XO32M_VOUT_SHIFT (3U) /*! VOUT - Sets the LDO output level. @@ -4893,126 +5429,130 @@ typedef struct { * 0b111..0.925 V. */ #define ANACTRL_LDO_XO32M_VOUT(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_VOUT_SHIFT)) & ANACTRL_LDO_XO32M_VOUT_MASK) + #define ANACTRL_LDO_XO32M_IBIAS_MASK (0xC0U) #define ANACTRL_LDO_XO32M_IBIAS_SHIFT (6U) +/*! IBIAS - Adjust the biasing current. + */ #define ANACTRL_LDO_XO32M_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_IBIAS_SHIFT)) & ANACTRL_LDO_XO32M_IBIAS_MASK) + #define ANACTRL_LDO_XO32M_STABMODE_MASK (0x300U) #define ANACTRL_LDO_XO32M_STABMODE_SHIFT (8U) +/*! STABMODE - Stability configuration. + */ #define ANACTRL_LDO_XO32M_STABMODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_LDO_XO32M_STABMODE_SHIFT)) & ANACTRL_LDO_XO32M_STABMODE_MASK) /*! @} */ -/*! @name XO_CAL_CFG - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register */ +/*! @name AUX_BIAS - AUX_BIAS */ /*! @{ */ -#define ANACTRL_XO_CAL_CFG_START_INV_MASK (0x1U) -#define ANACTRL_XO_CAL_CFG_START_INV_SHIFT (0U) -#define ANACTRL_XO_CAL_CFG_START_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_START_INV_MASK) -#define ANACTRL_XO_CAL_CFG_START_OVR_MASK (0x2U) -#define ANACTRL_XO_CAL_CFG_START_OVR_SHIFT (1U) -#define ANACTRL_XO_CAL_CFG_START_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_OVR_SHIFT)) & ANACTRL_XO_CAL_CFG_START_OVR_MASK) -#define ANACTRL_XO_CAL_CFG_START_MASK (0x4U) -#define ANACTRL_XO_CAL_CFG_START_SHIFT (2U) -#define ANACTRL_XO_CAL_CFG_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_START_SHIFT)) & ANACTRL_XO_CAL_CFG_START_MASK) -#define ANACTRL_XO_CAL_CFG_STOP_INV_MASK (0x8U) -#define ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT (3U) -#define ANACTRL_XO_CAL_CFG_STOP_INV(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_INV_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_INV_MASK) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK (0x10U) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT (4U) -#define ANACTRL_XO_CAL_CFG_STOP_CNTR_END(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_STOP_CNTR_END_SHIFT)) & ANACTRL_XO_CAL_CFG_STOP_CNTR_END_MASK) -#define ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK (0x20U) -#define ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT (5U) -/*! XO32K_MODE - When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal oscillator calibration is used. - * 0b0..High speed crystal oscillator (12 MHz- 32 MHz) is used - * 0b1..32 kHz crystal oscillator calibration is used. + +#define ANACTRL_AUX_BIAS_VREF1VENABLE_MASK (0x2U) +#define ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT (1U) +/*! VREF1VENABLE - Control output of 1V reference voltage. + * 0b0..Output of 1V reference voltage buffer is bypassed. + * 0b1..Output of 1V reference voltage is enabled. */ -#define ANACTRL_XO_CAL_CFG_XO32K_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CFG_XO32K_MODE_SHIFT)) & ANACTRL_XO_CAL_CFG_XO32K_MODE_MASK) -/*! @} */ +#define ANACTRL_AUX_BIAS_VREF1VENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VENABLE_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VENABLE_MASK) -/*! @name XO_CAL_CMD - All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register. */ -/*! @{ */ -#define ANACTRL_XO_CAL_CMD_START_MASK (0x1U) -#define ANACTRL_XO_CAL_CMD_START_SHIFT (0U) -#define ANACTRL_XO_CAL_CMD_START(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_START_SHIFT)) & ANACTRL_XO_CAL_CMD_START_MASK) -#define ANACTRL_XO_CAL_CMD_STOP_MASK (0x2U) -#define ANACTRL_XO_CAL_CMD_STOP_SHIFT (1U) -#define ANACTRL_XO_CAL_CMD_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_STOP_SHIFT)) & ANACTRL_XO_CAL_CMD_STOP_MASK) -#define ANACTRL_XO_CAL_CMD_OVR_MASK (0x4U) -#define ANACTRL_XO_CAL_CMD_OVR_SHIFT (2U) -#define ANACTRL_XO_CAL_CMD_OVR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_CMD_OVR_SHIFT)) & ANACTRL_XO_CAL_CMD_OVR_MASK) -/*! @} */ +#define ANACTRL_AUX_BIAS_ITRIM_MASK (0x7CU) +#define ANACTRL_AUX_BIAS_ITRIM_SHIFT (2U) +/*! ITRIM - current trimming control word. + */ +#define ANACTRL_AUX_BIAS_ITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIM_SHIFT)) & ANACTRL_AUX_BIAS_ITRIM_MASK) -/*! @name XO_CAL_STATUS - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register. */ -/*! @{ */ -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK (0xFFFFU) -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT (0U) -#define ANACTRL_XO_CAL_STATUS_CAL_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_CAL_CNTR_SHIFT)) & ANACTRL_XO_CAL_STATUS_CAL_CNTR_MASK) -#define ANACTRL_XO_CAL_STATUS_DONE_MASK (0x10000U) -#define ANACTRL_XO_CAL_STATUS_DONE_SHIFT (16U) -#define ANACTRL_XO_CAL_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_XO_CAL_STATUS_DONE_SHIFT)) & ANACTRL_XO_CAL_STATUS_DONE_MASK) +#define ANACTRL_AUX_BIAS_PTATITRIM_MASK (0xF80U) +#define ANACTRL_AUX_BIAS_PTATITRIM_SHIFT (7U) +/*! PTATITRIM - current trimming control word for ptat current. + */ +#define ANACTRL_AUX_BIAS_PTATITRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_PTATITRIM_SHIFT)) & ANACTRL_AUX_BIAS_PTATITRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VTRIM_MASK (0x1F000U) +#define ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT (12U) +/*! VREF1VTRIM - voltage trimming control word. + */ +#define ANACTRL_AUX_BIAS_VREF1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VTRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VTRIM_MASK) + +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK (0xE0000U) +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT (17U) +/*! VREF1VCURVETRIM - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_VREF1VCURVETRIM(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_VREF1VCURVETRIM_SHIFT)) & ANACTRL_AUX_BIAS_VREF1VCURVETRIM_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK (0x100000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT (20U) +/*! ITRIMCTRL0 - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL0(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL0_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL0_MASK) + +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK (0x200000U) +#define ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT (21U) +/*! ITRIMCTRL1 - Control bit to configure trimming state of mirror. + */ +#define ANACTRL_AUX_BIAS_ITRIMCTRL1(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_AUX_BIAS_ITRIMCTRL1_SHIFT)) & ANACTRL_AUX_BIAS_ITRIMCTRL1_MASK) /*! @} */ /*! @name USBHS_PHY_CTRL - USB High Speed Phy Control */ /*! @{ */ + #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK (0x1U) #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT (0U) +/*! usb_vbusvalid_ext - Override value for Vbus if using external detectors. + */ #define ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_vbusvalid_ext_MASK) + #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK (0x2U) #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT (1U) +/*! usb_id_ext - Override value for ID if using external detectors. + */ #define ANACTRL_USBHS_PHY_CTRL_usb_id_ext(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_usb_id_ext_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_usb_id_ext_MASK) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK (0x8U) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT (3U) -#define ANACTRL_USBHS_PHY_CTRL_iso_atx(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_CTRL_iso_atx_SHIFT)) & ANACTRL_USBHS_PHY_CTRL_iso_atx_MASK) /*! @} */ /*! @name USBHS_PHY_TRIM - USB High Speed Phy Trim values */ /*! @{ */ + #define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK (0x3U) #define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT (0U) +/*! trim_usb_reg_env_tail_adj_vd - Adjusts time constant of HS RX squelch (envelope) comparator. + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb_reg_env_tail_adj_vd_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK (0x3CU) #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT (2U) +/*! trim_usbphy_tx_d_cal - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_d_cal_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK (0x7C0U) #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT (6U) +/*! trim_usbphy_tx_cal45dp - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dp_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK (0xF800U) #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT (11U) +/*! trim_usbphy_tx_cal45dm - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usbphy_tx_cal45dm_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK (0x30000U) #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT (16U) +/*! trim_usb2_refbias_tst - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_tst_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK (0x1C0000U) #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT (18U) +/*! trim_usb2_refbias_vbgadj - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_usb2_refbias_vbgadj_MASK) + #define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK (0xE00000U) #define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT (21U) +/*! trim_pll_ctrl0_div_sel - . + */ #define ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_SHIFT)) & ANACTRL_USBHS_PHY_TRIM_trim_pll_ctrl0_div_sel_MASK) /*! @} */ -/*! @name USBHS_PHY_STATUS - USB High Speed Phy Status */ -/*! @{ */ -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK (0x1U) -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT (0U) -#define ANACTRL_USBHS_PHY_STATUS_pfd_stable(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_pfd_stable_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_pfd_stable_MASK) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK (0x2U) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT (1U) -#define ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_vbusvalid_3vdetect_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK (0x4U) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT (2U) -#define ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_sess_vld_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK (0x8U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT (3U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vpin_fs_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK (0x10U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT (4U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_rx_vmin_fs_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK (0x20U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT (5U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_plugged_in_1p8v_MASK) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK (0x40U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT (6U) -#define ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v(x) (((uint32_t)(((uint32_t)(x)) << ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_SHIFT)) & ANACTRL_USBHS_PHY_STATUS_usb2_iddig_1p8v_MASK) -/*! @} */ - /*! * @} @@ -5020,7 +5560,7 @@ typedef struct { /* ANACTRL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral ANACTRL base address */ #define ANACTRL_BASE (0x50013000u) /** Peripheral ANACTRL base address */ @@ -5098,6 +5638,7 @@ typedef struct { /*! @name CTRL0 - Contains the offsets of AB and CD in the RAM. */ /*! @{ */ + #define CASPER_CTRL0_ABBPAIR_MASK (0x1U) #define CASPER_CTRL0_ABBPAIR_SHIFT (0U) /*! ABBPAIR - Which bank-pair the offset ABOFF is within. This must be 0 if only 2-up @@ -5105,9 +5646,15 @@ typedef struct { * 0b1..Bank-pair 1 (2nd) */ #define CASPER_CTRL0_ABBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABBPAIR_SHIFT)) & CASPER_CTRL0_ABBPAIR_MASK) -#define CASPER_CTRL0_ABOFF_MASK (0x4U) + +#define CASPER_CTRL0_ABOFF_MASK (0x1FFCU) #define CASPER_CTRL0_ABOFF_SHIFT (2U) +/*! ABOFF - Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code + * sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed + * if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up + */ #define CASPER_CTRL0_ABOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_ABOFF_SHIFT)) & CASPER_CTRL0_ABOFF_MASK) + #define CASPER_CTRL0_CDBPAIR_MASK (0x10000U) #define CASPER_CTRL0_CDBPAIR_SHIFT (16U) /*! CDBPAIR - Which bank-pair the offset CDOFF is within. This must be 0 if only 2-up @@ -5115,19 +5662,31 @@ typedef struct { * 0b1..Bank-pair 1 (2nd) */ #define CASPER_CTRL0_CDBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDBPAIR_SHIFT)) & CASPER_CTRL0_CDBPAIR_MASK) + #define CASPER_CTRL0_CDOFF_MASK (0x1FFC0000U) #define CASPER_CTRL0_CDOFF_SHIFT (18U) +/*! CDOFF - Word or DWord Offset of CD, with D at [2]=0 and C at [2]=1 as far as the code sees + * (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 + * bit operation. Ideally not in the same RAM as the AB values + */ #define CASPER_CTRL0_CDOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL0_CDOFF_SHIFT)) & CASPER_CTRL0_CDOFF_MASK) /*! @} */ /*! @name CTRL1 - Contains the opcode mode, iteration count, and result offset (in RAM) and also launches the accelerator. Note: with CP version: CTRL0 and CRTL1 can be written in one go with MCRR. */ /*! @{ */ + #define CASPER_CTRL1_ITER_MASK (0xFFU) #define CASPER_CTRL1_ITER_SHIFT (0U) +/*! ITER - Iteration counter. Is number_cycles - 1. write 0 means Does one cycle - does not iterate. + */ #define CASPER_CTRL1_ITER(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_ITER_SHIFT)) & CASPER_CTRL1_ITER_MASK) + #define CASPER_CTRL1_MODE_MASK (0xFF00U) #define CASPER_CTRL1_MODE_SHIFT (8U) +/*! MODE - Operation mode to perform. write 0 means Accelerator is inactive. write others means accelerator is active. + */ #define CASPER_CTRL1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_MODE_SHIFT)) & CASPER_CTRL1_MODE_MASK) + #define CASPER_CTRL1_RESBPAIR_MASK (0x10000U) #define CASPER_CTRL1_RESBPAIR_SHIFT (16U) /*! RESBPAIR - Which bank-pair the offset RESOFF is within. This must be 0 if only 2-up. Ideally @@ -5136,9 +5695,14 @@ typedef struct { * 0b1..Bank-pair 1 (2nd) */ #define CASPER_CTRL1_RESBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESBPAIR_SHIFT)) & CASPER_CTRL1_RESBPAIR_MASK) + #define CASPER_CTRL1_RESOFF_MASK (0x1FFC0000U) #define CASPER_CTRL1_RESOFF_SHIFT (18U) +/*! RESOFF - Word or DWord Offset of result. Word offset only allowed if 32 bit operation. Ideally + * not in the same RAM as the AB and CD values + */ #define CASPER_CTRL1_RESOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CTRL1_RESOFF_SHIFT)) & CASPER_CTRL1_RESOFF_MASK) + #define CASPER_CTRL1_CSKIP_MASK (0xC0000000U) #define CASPER_CTRL1_CSKIP_SHIFT (30U) /*! CSKIP - Skip rules on Carry if needed. This operation will be skipped based on Carry value (from previous operation) if not 0: @@ -5152,9 +5716,14 @@ typedef struct { /*! @name LOADER - Contains an optional loader to load into CTRL0/1 in steps to perform a set of operations. */ /*! @{ */ + #define CASPER_LOADER_COUNT_MASK (0xFFU) #define CASPER_LOADER_COUNT_SHIFT (0U) +/*! COUNT - Number of control pairs to load 0 relative (so 1 means load 1). write 1 means Does one + * op - does not iterate, write N means N control pairs to load + */ #define CASPER_LOADER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_COUNT_SHIFT)) & CASPER_LOADER_COUNT_MASK) + #define CASPER_LOADER_CTRLBPAIR_MASK (0x10000U) #define CASPER_LOADER_CTRLBPAIR_SHIFT (16U) /*! CTRLBPAIR - Which bank-pair the offset CTRLOFF is within. This must be 0 if only 2-up. Does not @@ -5163,13 +5732,17 @@ typedef struct { * 0b1..Bank-pair 1 (2nd) */ #define CASPER_LOADER_CTRLBPAIR(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLBPAIR_SHIFT)) & CASPER_LOADER_CTRLBPAIR_MASK) + #define CASPER_LOADER_CTRLOFF_MASK (0x1FFC0000U) #define CASPER_LOADER_CTRLOFF_SHIFT (18U) +/*! CTRLOFF - DWord Offset of CTRL pair to load next. + */ #define CASPER_LOADER_CTRLOFF(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOADER_CTRLOFF_SHIFT)) & CASPER_LOADER_CTRLOFF_MASK) /*! @} */ /*! @name STATUS - Indicates operational status and would contain the carry bit if used. */ /*! @{ */ + #define CASPER_STATUS_DONE_MASK (0x1U) #define CASPER_STATUS_DONE_SHIFT (0U) /*! DONE - Indicates if the accelerator has finished an operation. Write 1 to clear, or write CTRL1 to clear. @@ -5177,6 +5750,7 @@ typedef struct { * 0b1..Completed last operation */ #define CASPER_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_DONE_SHIFT)) & CASPER_STATUS_DONE_MASK) + #define CASPER_STATUS_CARRY_MASK (0x10U) #define CASPER_STATUS_CARRY_SHIFT (4U) /*! CARRY - Last carry value if operation produced a carry bit @@ -5184,6 +5758,7 @@ typedef struct { * 0b1..Carry was 1 */ #define CASPER_STATUS_CARRY(x) (((uint32_t)(((uint32_t)(x)) << CASPER_STATUS_CARRY_SHIFT)) & CASPER_STATUS_CARRY_MASK) + #define CASPER_STATUS_BUSY_MASK (0x20U) #define CASPER_STATUS_BUSY_SHIFT (5U) /*! BUSY - Indicates if the accelerator is busy performing an operation @@ -5195,6 +5770,7 @@ typedef struct { /*! @name INTENSET - Sets interrupts */ /*! @{ */ + #define CASPER_INTENSET_DONE_MASK (0x1U) #define CASPER_INTENSET_DONE_SHIFT (0U) /*! DONE - Set if the accelerator should interrupt when done. @@ -5206,6 +5782,7 @@ typedef struct { /*! @name INTENCLR - Clears interrupts */ /*! @{ */ + #define CASPER_INTENCLR_DONE_MASK (0x1U) #define CASPER_INTENCLR_DONE_SHIFT (0U) /*! DONE - Written to clear an interrupt set with INTENSET. @@ -5217,6 +5794,7 @@ typedef struct { /*! @name INTSTAT - Interrupt status bits (mask of INTENSET and STATUS) */ /*! @{ */ + #define CASPER_INTSTAT_DONE_MASK (0x1U) #define CASPER_INTSTAT_DONE_SHIFT (0U) /*! DONE - If set, interrupt is caused by accelerator being done. @@ -5228,76 +5806,115 @@ typedef struct { /*! @name AREG - A register */ /*! @{ */ + #define CASPER_AREG_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_AREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ #define CASPER_AREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_AREG_REG_VALUE_SHIFT)) & CASPER_AREG_REG_VALUE_MASK) /*! @} */ /*! @name BREG - B register */ /*! @{ */ + #define CASPER_BREG_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_BREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ #define CASPER_BREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_BREG_REG_VALUE_SHIFT)) & CASPER_BREG_REG_VALUE_MASK) /*! @} */ /*! @name CREG - C register */ /*! @{ */ + #define CASPER_CREG_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_CREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ #define CASPER_CREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_CREG_REG_VALUE_SHIFT)) & CASPER_CREG_REG_VALUE_MASK) /*! @} */ /*! @name DREG - D register */ /*! @{ */ + #define CASPER_DREG_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_DREG_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to be fed into Multiplier. Is not normally written or read by application, + * but is available when accelerator not busy. + */ #define CASPER_DREG_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_DREG_REG_VALUE_SHIFT)) & CASPER_DREG_REG_VALUE_MASK) /*! @} */ /*! @name RES0 - Result register 0 */ /*! @{ */ + #define CASPER_RES0_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_RES0_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ #define CASPER_RES0_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES0_REG_VALUE_SHIFT)) & CASPER_RES0_REG_VALUE_MASK) /*! @} */ /*! @name RES1 - Result register 1 */ /*! @{ */ + #define CASPER_RES1_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_RES1_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ #define CASPER_RES1_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES1_REG_VALUE_SHIFT)) & CASPER_RES1_REG_VALUE_MASK) /*! @} */ /*! @name RES2 - Result register 2 */ /*! @{ */ + #define CASPER_RES2_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_RES2_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ #define CASPER_RES2_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES2_REG_VALUE_SHIFT)) & CASPER_RES2_REG_VALUE_MASK) /*! @} */ /*! @name RES3 - Result register 3 */ /*! @{ */ + #define CASPER_RES3_REG_VALUE_MASK (0xFFFFFFFFU) #define CASPER_RES3_REG_VALUE_SHIFT (0U) +/*! REG_VALUE - Register to hold working result (from multiplier, adder/xor, etc). Is not normally + * written or read by application, but is available when accelerator not busy. + */ #define CASPER_RES3_REG_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CASPER_RES3_REG_VALUE_SHIFT)) & CASPER_RES3_REG_VALUE_MASK) /*! @} */ /*! @name MASK - Optional mask register */ /*! @{ */ + #define CASPER_MASK_MASK_MASK (0xFFFFFFFFU) #define CASPER_MASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + */ #define CASPER_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_MASK_MASK_SHIFT)) & CASPER_MASK_MASK_MASK) /*! @} */ /*! @name REMASK - Optional re-mask register */ /*! @{ */ + #define CASPER_REMASK_MASK_MASK (0xFFFFFFFFU) #define CASPER_REMASK_MASK_SHIFT (0U) +/*! MASK - Mask to apply as side channel countermeasure. 0: No mask to be used. N: Mask to XOR onto values + */ #define CASPER_REMASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_REMASK_MASK_SHIFT)) & CASPER_REMASK_MASK_MASK) /*! @} */ /*! @name LOCK - Security lock register */ /*! @{ */ + #define CASPER_LOCK_LOCK_MASK (0x1U) #define CASPER_LOCK_LOCK_SHIFT (0U) /*! LOCK - Reads back with security level locked to, or 0. Writes as 0 to unlock, 1 to lock. @@ -5305,6 +5922,7 @@ typedef struct { * 0b1..Lock to current security level */ #define CASPER_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CASPER_LOCK_LOCK_SHIFT)) & CASPER_LOCK_LOCK_MASK) + #define CASPER_LOCK_KEY_MASK (0x1FFF0U) #define CASPER_LOCK_KEY_SHIFT (4U) /*! KEY - Must be written as 0x73D to change the register. @@ -5320,7 +5938,7 @@ typedef struct { /* CASPER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral CASPER base address */ #define CASPER_BASE (0x500A5000u) /** Peripheral CASPER base address */ @@ -5347,6 +5965,8 @@ typedef struct { /** Array initializer of CASPER peripheral base pointers */ #define CASPER_BASE_PTRS { CASPER } #endif +/** Interrupt vectors for the CASPER peripheral type */ +#define CASPER_IRQS { CASER_IRQn } /*! * @} @@ -5383,41 +6003,69 @@ typedef struct { /*! @name MODE - CRC mode register */ /*! @{ */ + #define CRC_MODE_CRC_POLY_MASK (0x3U) #define CRC_MODE_CRC_POLY_SHIFT (0U) +/*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial + */ #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) + #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) +/*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) + */ #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) + #define CRC_MODE_CMPL_WR_MASK (0x8U) #define CRC_MODE_CMPL_WR_SHIFT (3U) +/*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA + */ #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) + #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) +/*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM + */ #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) + #define CRC_MODE_CMPL_SUM_MASK (0x20U) #define CRC_MODE_CMPL_SUM_SHIFT (5U) +/*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM + */ #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) /*! @} */ /*! @name SEED - CRC seed register */ /*! @{ */ + #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) #define CRC_SEED_CRC_SEED_SHIFT (0U) +/*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with + * selected bit order and 1's complement pre-processes. A write access to this register will + * overrule the CRC calculation in progresses. + */ #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) /*! @} */ /*! @name SUM - CRC checksum register */ /*! @{ */ + #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) #define CRC_SUM_CRC_SUM_SHIFT (0U) +/*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. + */ #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) /*! @} */ /*! @name WR_DATA - CRC data register */ /*! @{ */ + #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) +/*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with + * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and + * accept back-to-back transactions. + */ #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) /*! @} */ @@ -5428,7 +6076,7 @@ typedef struct { /* CRC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral CRC_ENGINE base address */ #define CRC_ENGINE_BASE (0x50095000u) /** Peripheral CRC_ENGINE base address */ @@ -5499,34 +6147,59 @@ typedef struct { /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ /*! @{ */ + #define CTIMER_IR_MR0INT_MASK (0x1U) #define CTIMER_IR_MR0INT_SHIFT (0U) +/*! MR0INT - Interrupt flag for match channel 0. + */ #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) + #define CTIMER_IR_MR1INT_MASK (0x2U) #define CTIMER_IR_MR1INT_SHIFT (1U) +/*! MR1INT - Interrupt flag for match channel 1. + */ #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) + #define CTIMER_IR_MR2INT_MASK (0x4U) #define CTIMER_IR_MR2INT_SHIFT (2U) +/*! MR2INT - Interrupt flag for match channel 2. + */ #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) + #define CTIMER_IR_MR3INT_MASK (0x8U) #define CTIMER_IR_MR3INT_SHIFT (3U) +/*! MR3INT - Interrupt flag for match channel 3. + */ #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) + #define CTIMER_IR_CR0INT_MASK (0x10U) #define CTIMER_IR_CR0INT_SHIFT (4U) +/*! CR0INT - Interrupt flag for capture channel 0 event. + */ #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) + #define CTIMER_IR_CR1INT_MASK (0x20U) #define CTIMER_IR_CR1INT_SHIFT (5U) +/*! CR1INT - Interrupt flag for capture channel 1 event. + */ #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) + #define CTIMER_IR_CR2INT_MASK (0x40U) #define CTIMER_IR_CR2INT_SHIFT (6U) +/*! CR2INT - Interrupt flag for capture channel 2 event. + */ #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) + #define CTIMER_IR_CR3INT_MASK (0x80U) #define CTIMER_IR_CR3INT_SHIFT (7U) +/*! CR3INT - Interrupt flag for capture channel 3 event. + */ #define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK) /*! @} */ /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ /*! @{ */ + #define CTIMER_TCR_CEN_MASK (0x1U) #define CTIMER_TCR_CEN_SHIFT (0U) /*! CEN - Counter enable. @@ -5534,6 +6207,7 @@ typedef struct { * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. */ #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) + #define CTIMER_TCR_CRST_MASK (0x2U) #define CTIMER_TCR_CRST_SHIFT (1U) /*! CRST - Counter reset. @@ -5546,81 +6220,145 @@ typedef struct { /*! @name TC - Timer Counter */ /*! @{ */ + #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) #define CTIMER_TC_TCVAL_SHIFT (0U) +/*! TCVAL - Timer counter value. + */ #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) /*! @} */ /*! @name PR - Prescale Register */ /*! @{ */ + #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) #define CTIMER_PR_PRVAL_SHIFT (0U) +/*! PRVAL - Prescale counter value. + */ #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) /*! @} */ /*! @name PC - Prescale Counter */ /*! @{ */ + #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) #define CTIMER_PC_PCVAL_SHIFT (0U) +/*! PCVAL - Prescale counter value. + */ #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) /*! @} */ /*! @name MCR - Match Control Register */ /*! @{ */ + #define CTIMER_MCR_MR0I_MASK (0x1U) #define CTIMER_MCR_MR0I_SHIFT (0U) +/*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. + */ #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) + #define CTIMER_MCR_MR0R_MASK (0x2U) #define CTIMER_MCR_MR0R_SHIFT (1U) +/*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. + */ #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) + #define CTIMER_MCR_MR0S_MASK (0x4U) #define CTIMER_MCR_MR0S_SHIFT (2U) +/*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. + */ #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) + #define CTIMER_MCR_MR1I_MASK (0x8U) #define CTIMER_MCR_MR1I_SHIFT (3U) +/*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. + */ #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) + #define CTIMER_MCR_MR1R_MASK (0x10U) #define CTIMER_MCR_MR1R_SHIFT (4U) +/*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. + */ #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) + #define CTIMER_MCR_MR1S_MASK (0x20U) #define CTIMER_MCR_MR1S_SHIFT (5U) +/*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. + */ #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) + #define CTIMER_MCR_MR2I_MASK (0x40U) #define CTIMER_MCR_MR2I_SHIFT (6U) +/*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. + */ #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) + #define CTIMER_MCR_MR2R_MASK (0x80U) #define CTIMER_MCR_MR2R_SHIFT (7U) +/*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. + */ #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) + #define CTIMER_MCR_MR2S_MASK (0x100U) #define CTIMER_MCR_MR2S_SHIFT (8U) +/*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. + */ #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) + #define CTIMER_MCR_MR3I_MASK (0x200U) #define CTIMER_MCR_MR3I_SHIFT (9U) +/*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. + */ #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) + #define CTIMER_MCR_MR3R_MASK (0x400U) #define CTIMER_MCR_MR3R_SHIFT (10U) +/*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. + */ #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) + #define CTIMER_MCR_MR3S_MASK (0x800U) #define CTIMER_MCR_MR3S_SHIFT (11U) +/*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. + */ #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) + #define CTIMER_MCR_MR0RL_MASK (0x1000000U) #define CTIMER_MCR_MR0RL_SHIFT (24U) +/*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ #define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) + #define CTIMER_MCR_MR1RL_MASK (0x2000000U) #define CTIMER_MCR_MR1RL_SHIFT (25U) +/*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ #define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) + #define CTIMER_MCR_MR2RL_MASK (0x4000000U) #define CTIMER_MCR_MR2RL_SHIFT (26U) +/*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ #define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) + #define CTIMER_MCR_MR3RL_MASK (0x8000000U) #define CTIMER_MCR_MR3RL_SHIFT (27U) +/*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero + * (either via a match event or a write to bit 1 of the TCR). + */ #define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) /*! @} */ /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ /*! @{ */ + #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) #define CTIMER_MR_MATCH_SHIFT (0U) +/*! MATCH - Timer counter match value. + */ #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) /*! @} */ @@ -5629,48 +6367,95 @@ typedef struct { /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ /*! @{ */ + #define CTIMER_CCR_CAP0RE_MASK (0x1U) #define CTIMER_CCR_CAP0RE_SHIFT (0U) +/*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) + #define CTIMER_CCR_CAP0FE_MASK (0x2U) #define CTIMER_CCR_CAP0FE_SHIFT (1U) +/*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) + #define CTIMER_CCR_CAP0I_MASK (0x4U) #define CTIMER_CCR_CAP0I_SHIFT (2U) +/*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. + */ #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) + #define CTIMER_CCR_CAP1RE_MASK (0x8U) #define CTIMER_CCR_CAP1RE_SHIFT (3U) +/*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) + #define CTIMER_CCR_CAP1FE_MASK (0x10U) #define CTIMER_CCR_CAP1FE_SHIFT (4U) +/*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) + #define CTIMER_CCR_CAP1I_MASK (0x20U) #define CTIMER_CCR_CAP1I_SHIFT (5U) +/*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. + */ #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) + #define CTIMER_CCR_CAP2RE_MASK (0x40U) #define CTIMER_CCR_CAP2RE_SHIFT (6U) +/*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) + #define CTIMER_CCR_CAP2FE_MASK (0x80U) #define CTIMER_CCR_CAP2FE_SHIFT (7U) +/*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) + #define CTIMER_CCR_CAP2I_MASK (0x100U) #define CTIMER_CCR_CAP2I_SHIFT (8U) +/*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. + */ #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) + #define CTIMER_CCR_CAP3RE_MASK (0x200U) #define CTIMER_CCR_CAP3RE_SHIFT (9U) +/*! CAP3RE - Rising edge of capture channel 3: a sequence of 0 then 1 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK) + #define CTIMER_CCR_CAP3FE_MASK (0x400U) #define CTIMER_CCR_CAP3FE_SHIFT (10U) +/*! CAP3FE - Falling edge of capture channel 3: a sequence of 1 then 0 causes CR3 to be loaded with + * the contents of TC. 0 = disabled. 1 = enabled. + */ #define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK) + #define CTIMER_CCR_CAP3I_MASK (0x800U) #define CTIMER_CCR_CAP3I_SHIFT (11U) +/*! CAP3I - Generate interrupt on channel 3 capture event: a CR3 load generates an interrupt. + */ #define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK) /*! @} */ /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ /*! @{ */ + #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) #define CTIMER_CR_CAP_SHIFT (0U) +/*! CAP - Timer counter capture value. + */ #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) /*! @} */ @@ -5679,18 +6464,43 @@ typedef struct { /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ /*! @{ */ + #define CTIMER_EMR_EM0_MASK (0x1U) #define CTIMER_EMR_EM0_SHIFT (0U) +/*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) + #define CTIMER_EMR_EM1_MASK (0x2U) #define CTIMER_EMR_EM1_SHIFT (1U) +/*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) + #define CTIMER_EMR_EM2_MASK (0x4U) #define CTIMER_EMR_EM2_SHIFT (2U) +/*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if + * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) + #define CTIMER_EMR_EM3_MASK (0x8U) #define CTIMER_EMR_EM3_SHIFT (3U) +/*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output + * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, + * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins + * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + */ #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) + #define CTIMER_EMR_EMC0_MASK (0x30U) #define CTIMER_EMR_EMC0_SHIFT (4U) /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. @@ -5700,6 +6510,7 @@ typedef struct { * 0b11..Toggle. Toggle the corresponding External Match bit/output. */ #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) + #define CTIMER_EMR_EMC1_MASK (0xC0U) #define CTIMER_EMR_EMC1_SHIFT (6U) /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. @@ -5709,6 +6520,7 @@ typedef struct { * 0b11..Toggle. Toggle the corresponding External Match bit/output. */ #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) + #define CTIMER_EMR_EMC2_MASK (0x300U) #define CTIMER_EMR_EMC2_SHIFT (8U) /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. @@ -5718,6 +6530,7 @@ typedef struct { * 0b11..Toggle. Toggle the corresponding External Match bit/output. */ #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) + #define CTIMER_EMR_EMC3_MASK (0xC00U) #define CTIMER_EMR_EMC3_SHIFT (10U) /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. @@ -5731,6 +6544,7 @@ typedef struct { /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ /*! @{ */ + #define CTIMER_CTCR_CTMODE_MASK (0x3U) #define CTIMER_CTCR_CTMODE_SHIFT (0U) /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment @@ -5742,6 +6556,7 @@ typedef struct { * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. */ #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) + #define CTIMER_CTCR_CINSEL_MASK (0xCU) #define CTIMER_CTCR_CINSEL_SHIFT (2U) /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which @@ -5755,9 +6570,14 @@ typedef struct { * 0b11..Channel 3. CAPn.3 for CTIMERn */ #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) + #define CTIMER_CTCR_ENCC_MASK (0x10U) #define CTIMER_CTCR_ENCC_SHIFT (4U) +/*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the + * capture-edge event specified in bits 7:5 occurs. + */ #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) + #define CTIMER_CTCR_SELCC_MASK (0xE0U) #define CTIMER_CTCR_SELCC_SHIFT (5U) /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the @@ -5775,6 +6595,7 @@ typedef struct { /*! @name PWMC - PWM Control Register. This register enables PWM mode for the external match pins. */ /*! @{ */ + #define CTIMER_PWMC_PWMEN0_MASK (0x1U) #define CTIMER_PWMC_PWMEN0_SHIFT (0U) /*! PWMEN0 - PWM mode enable for channel0. @@ -5782,6 +6603,7 @@ typedef struct { * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. */ #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) + #define CTIMER_PWMC_PWMEN1_MASK (0x2U) #define CTIMER_PWMC_PWMEN1_SHIFT (1U) /*! PWMEN1 - PWM mode enable for channel1. @@ -5789,6 +6611,7 @@ typedef struct { * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. */ #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) + #define CTIMER_PWMC_PWMEN2_MASK (0x4U) #define CTIMER_PWMC_PWMEN2_SHIFT (2U) /*! PWMEN2 - PWM mode enable for channel2. @@ -5796,6 +6619,7 @@ typedef struct { * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. */ #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) + #define CTIMER_PWMC_PWMEN3_MASK (0x8U) #define CTIMER_PWMC_PWMEN3_SHIFT (3U) /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. @@ -5807,9 +6631,12 @@ typedef struct { /*! @name MSR - Match Shadow Register */ /*! @{ */ -#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU) -#define CTIMER_MSR_SHADOWW_SHIFT (0U) -#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK) + +#define CTIMER_MSR_SHADOW_MASK (0xFFFFFFFFU) +#define CTIMER_MSR_SHADOW_SHIFT (0U) +/*! SHADOW - Timer counter match shadow value. + */ +#define CTIMER_MSR_SHADOW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOW_SHIFT)) & CTIMER_MSR_SHADOW_MASK) /*! @} */ /* The count of CTIMER_MSR */ @@ -5822,7 +6649,7 @@ typedef struct { /* CTIMER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral CTIMER0 base address */ #define CTIMER0_BASE (0x50008000u) /** Peripheral CTIMER0 base address */ @@ -5906,113 +6733,142 @@ typedef struct { /* ---------------------------------------------------------------------------- - -- DGBMAILBOX Peripheral Access Layer + -- DBGMAILBOX Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup DGBMAILBOX_Peripheral_Access_Layer DGBMAILBOX Peripheral Access Layer + * @addtogroup DBGMAILBOX_Peripheral_Access_Layer DBGMAILBOX Peripheral Access Layer * @{ */ -/** DGBMAILBOX - Register Layout Typedef */ +/** DBGMAILBOX - Register Layout Typedef */ typedef struct { __IO uint32_t CSW; /**< CRC mode register, offset: 0x0 */ __IO uint32_t REQUEST; /**< CRC seed register, offset: 0x4 */ __IO uint32_t RETURN; /**< Return value from ROM., offset: 0x8 */ uint8_t RESERVED_0[240]; __I uint32_t ID; /**< Identification register, offset: 0xFC */ -} DGBMAILBOX_Type; +} DBGMAILBOX_Type; /* ---------------------------------------------------------------------------- - -- DGBMAILBOX Register Masks + -- DBGMAILBOX Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup DGBMAILBOX_Register_Masks DGBMAILBOX Register Masks + * @addtogroup DBGMAILBOX_Register_Masks DBGMAILBOX Register Masks * @{ */ /*! @name CSW - CRC mode register */ /*! @{ */ -#define DGBMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) -#define DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) -#define DGBMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DGBMAILBOX_CSW_RESYNCH_REQ_MASK) -#define DGBMAILBOX_CSW_REQ_PENDING_MASK (0x2U) -#define DGBMAILBOX_CSW_REQ_PENDING_SHIFT (1U) -#define DGBMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_REQ_PENDING_SHIFT)) & DGBMAILBOX_CSW_REQ_PENDING_MASK) -#define DGBMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) -#define DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) -#define DGBMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_DBG_OR_ERR_MASK) -#define DGBMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) -#define DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) -#define DGBMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DGBMAILBOX_CSW_AHB_OR_ERR_MASK) -#define DGBMAILBOX_CSW_SOFT_RESET_MASK (0x10U) -#define DGBMAILBOX_CSW_SOFT_RESET_SHIFT (4U) -#define DGBMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_SOFT_RESET_SHIFT)) & DGBMAILBOX_CSW_SOFT_RESET_MASK) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) -#define DGBMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DGBMAILBOX_CSW_CHIP_RESET_REQ_MASK) + +#define DBGMAILBOX_CSW_RESYNCH_REQ_MASK (0x1U) +#define DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT (0U) +/*! RESYNCH_REQ - Debugger will set this bit to 1 to request a resynchronrisation + */ +#define DBGMAILBOX_CSW_RESYNCH_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_RESYNCH_REQ_SHIFT)) & DBGMAILBOX_CSW_RESYNCH_REQ_MASK) + +#define DBGMAILBOX_CSW_REQ_PENDING_MASK (0x2U) +#define DBGMAILBOX_CSW_REQ_PENDING_SHIFT (1U) +/*! REQ_PENDING - Request is pending from debugger (i.e unread value in REQUEST) + */ +#define DBGMAILBOX_CSW_REQ_PENDING(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_REQ_PENDING_SHIFT)) & DBGMAILBOX_CSW_REQ_PENDING_MASK) + +#define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) +#define DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT (2U) +/*! DBG_OR_ERR - Debugger overrun error (previous REQUEST overwritten before being picked up by ROM) + */ +#define DBGMAILBOX_CSW_DBG_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) +#define DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT (3U) +/*! AHB_OR_ERR - AHB overrun Error (Return value overwritten by ROM) + */ +#define DBGMAILBOX_CSW_AHB_OR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK) + +#define DBGMAILBOX_CSW_SOFT_RESET_MASK (0x10U) +#define DBGMAILBOX_CSW_SOFT_RESET_SHIFT (4U) +/*! SOFT_RESET - Soft Reset for DM (write-only from AHB, not readable and selfclearing). A write to + * this bit will cause a soft reset for DM. + */ +#define DBGMAILBOX_CSW_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_SOFT_RESET_SHIFT)) & DBGMAILBOX_CSW_SOFT_RESET_MASK) + +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK (0x20U) +#define DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT (5U) +/*! CHIP_RESET_REQ - Write only bit. Once written will cause the chip to reset (note that the DM is + * not reset by this reset as it is only resettable by a SOFT reset or a POR/BOD event) + */ +#define DBGMAILBOX_CSW_CHIP_RESET_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_CHIP_RESET_REQ_SHIFT)) & DBGMAILBOX_CSW_CHIP_RESET_REQ_MASK) /*! @} */ /*! @name REQUEST - CRC seed register */ /*! @{ */ -#define DGBMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_REQUEST_REQ_SHIFT (0U) -#define DGBMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_REQUEST_REQ_SHIFT)) & DGBMAILBOX_REQUEST_REQ_MASK) + +#define DBGMAILBOX_REQUEST_REQ_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_REQUEST_REQ_SHIFT (0U) +/*! REQ - Request Value + */ +#define DBGMAILBOX_REQUEST_REQ(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_REQUEST_REQ_SHIFT)) & DBGMAILBOX_REQUEST_REQ_MASK) /*! @} */ /*! @name RETURN - Return value from ROM. */ /*! @{ */ -#define DGBMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_RETURN_RET_SHIFT (0U) -#define DGBMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_RETURN_RET_SHIFT)) & DGBMAILBOX_RETURN_RET_MASK) + +#define DBGMAILBOX_RETURN_RET_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_RETURN_RET_SHIFT (0U) +/*! RET - The Return value from ROM. + */ +#define DBGMAILBOX_RETURN_RET(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_RETURN_RET_SHIFT)) & DBGMAILBOX_RETURN_RET_MASK) /*! @} */ /*! @name ID - Identification register */ /*! @{ */ -#define DGBMAILBOX_ID_ID_MASK (0xFFFFFFFFU) -#define DGBMAILBOX_ID_ID_SHIFT (0U) -#define DGBMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DGBMAILBOX_ID_ID_SHIFT)) & DGBMAILBOX_ID_ID_MASK) + +#define DBGMAILBOX_ID_ID_MASK (0xFFFFFFFFU) +#define DBGMAILBOX_ID_ID_SHIFT (0U) +/*! ID - Identification value. + */ +#define DBGMAILBOX_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_ID_ID_SHIFT)) & DBGMAILBOX_ID_ID_MASK) /*! @} */ /*! * @} - */ /* end of group DGBMAILBOX_Register_Masks */ + */ /* end of group DBGMAILBOX_Register_Masks */ -/* DGBMAILBOX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE (0x5009C000u) - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE_NS (0x4009C000u) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX_NS ((DGBMAILBOX_Type *)DGBMAILBOX_BASE_NS) - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS_NS { DGBMAILBOX_BASE_NS } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS_NS { DGBMAILBOX_NS } +/* DBGMAILBOX - Peripheral instance base addresses */ +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x5009C000u) + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE_NS (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX_NS ((DBGMAILBOX_Type *)DBGMAILBOX_BASE_NS) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS_NS { DBGMAILBOX_BASE_NS } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS_NS { DBGMAILBOX_NS } #else - /** Peripheral DGBMAILBOX base address */ - #define DGBMAILBOX_BASE (0x4009C000u) - /** Peripheral DGBMAILBOX base pointer */ - #define DGBMAILBOX ((DGBMAILBOX_Type *)DGBMAILBOX_BASE) - /** Array initializer of DGBMAILBOX peripheral base addresses */ - #define DGBMAILBOX_BASE_ADDRS { DGBMAILBOX_BASE } - /** Array initializer of DGBMAILBOX peripheral base pointers */ - #define DGBMAILBOX_BASE_PTRS { DGBMAILBOX } + /** Peripheral DBGMAILBOX base address */ + #define DBGMAILBOX_BASE (0x4009C000u) + /** Peripheral DBGMAILBOX base pointer */ + #define DBGMAILBOX ((DBGMAILBOX_Type *)DBGMAILBOX_BASE) + /** Array initializer of DBGMAILBOX peripheral base addresses */ + #define DBGMAILBOX_BASE_ADDRS { DBGMAILBOX_BASE } + /** Array initializer of DBGMAILBOX peripheral base pointers */ + #define DBGMAILBOX_BASE_PTRS { DBGMAILBOX } #endif /*! * @} - */ /* end of group DGBMAILBOX_Peripheral_Access_Layer */ + */ /* end of group DBGMAILBOX_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- @@ -6061,7 +6917,7 @@ typedef struct { __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */ __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */ uint8_t RESERVED_0[4]; - } CHANNEL[30]; + } CHANNEL[23]; } DMA_Type; /* ---------------------------------------------------------------------------- @@ -6075,6 +6931,7 @@ typedef struct { /*! @name CTRL - DMA control. */ /*! @{ */ + #define DMA_CTRL_ENABLE_MASK (0x1U) #define DMA_CTRL_ENABLE_SHIFT (0U) /*! ENABLE - DMA controller master enable. @@ -6087,6 +6944,7 @@ typedef struct { /*! @name INTSTAT - Interrupt status. */ /*! @{ */ + #define DMA_INTSTAT_ACTIVEINT_MASK (0x2U) #define DMA_INTSTAT_ACTIVEINT_SHIFT (1U) /*! ACTIVEINT - Summarizes whether any enabled interrupts (other than error interrupts) are pending. @@ -6094,6 +6952,7 @@ typedef struct { * 0b1..Pending. At least one enabled interrupt is pending. */ #define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK) + #define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U) #define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U) /*! ACTIVEERRINT - Summarizes whether any error interrupts are pending. @@ -6105,15 +6964,23 @@ typedef struct { /*! @name SRAMBASE - SRAM address of the channel configuration table. */ /*! @{ */ + #define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U) #define DMA_SRAMBASE_OFFSET_SHIFT (9U) +/*! OFFSET - Address bits 31:9 of the beginning of the DMA descriptor table. For 18 channels, the + * table must begin on a 512 byte boundary. + */ #define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK) /*! @} */ /*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU) #define DMA_COMMON_ENABLESET_ENA_SHIFT (0U) +/*! ENA - Enable for DMA channels. Bit n enables or disables DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = disabled. 1 = enabled. + */ #define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK) /*! @} */ @@ -6122,8 +6989,13 @@ typedef struct { /*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU) #define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears the corresponding bits in ENABLESET0. Bit n clears + * the channel enable bit n. The number of bits = number of DMA channels in this device. Other bits + * are reserved. + */ #define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK) /*! @} */ @@ -6132,8 +7004,12 @@ typedef struct { /*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU) #define DMA_COMMON_ACTIVE_ACT_SHIFT (0U) +/*! ACT - Active flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not active. 1 = active. + */ #define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK) /*! @} */ @@ -6142,8 +7018,12 @@ typedef struct { /*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU) #define DMA_COMMON_BUSY_BSY_SHIFT (0U) +/*! BSY - Busy flag for DMA channel n. Bit n corresponds to DMA channel n. The number of bits = + * number of DMA channels in this device. Other bits are reserved. 0 = not busy. 1 = busy. + */ #define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK) /*! @} */ @@ -6152,8 +7032,13 @@ typedef struct { /*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU) #define DMA_COMMON_ERRINT_ERR_SHIFT (0U) +/*! ERR - Error Interrupt flag for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = error interrupt is + * not active. 1 = error interrupt is active. + */ #define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK) /*! @} */ @@ -6162,8 +7047,13 @@ typedef struct { /*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTENSET_INTEN_SHIFT (0U) +/*! INTEN - Interrupt Enable read and set for DMA channel n. Bit n corresponds to DMA channel n. The + * number of bits = number of DMA channels in this device. Other bits are reserved. 0 = + * interrupt for DMA channel is disabled. 1 = interrupt for DMA channel is enabled. + */ #define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK) /*! @} */ @@ -6172,8 +7062,13 @@ typedef struct { /*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTENCLR_CLR_SHIFT (0U) +/*! CLR - Writing ones to this register clears corresponding bits in the INTENSET0. Bit n + * corresponds to DMA channel n. The number of bits = number of DMA channels in this device. Other bits are + * reserved. + */ #define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK) /*! @} */ @@ -6182,8 +7077,13 @@ typedef struct { /*! @name COMMON_INTA - Interrupt A status for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTA_IA_SHIFT (0U) +/*! IA - Interrupt A status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt A is not active. 1 = the DMA channel interrupt A is active. + */ #define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK) /*! @} */ @@ -6192,8 +7092,13 @@ typedef struct { /*! @name COMMON_INTB - Interrupt B status for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU) #define DMA_COMMON_INTB_IB_SHIFT (0U) +/*! IB - Interrupt B status for DMA channel n. Bit n corresponds to DMA channel n. The number of + * bits = number of DMA channels in this device. Other bits are reserved. 0 = the DMA channel + * interrupt B is not active. 1 = the DMA channel interrupt B is active. + */ #define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK) /*! @} */ @@ -6202,8 +7107,13 @@ typedef struct { /*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU) #define DMA_COMMON_SETVALID_SV_SHIFT (0U) +/*! SV - SETVALID control for DMA channel n. Bit n corresponds to DMA channel n. The number of bits + * = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = sets the + * VALIDPENDING control bit for DMA channel n + */ #define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK) /*! @} */ @@ -6212,8 +7122,13 @@ typedef struct { /*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU) #define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U) +/*! TRIG - Set Trigger control bit for DMA channel 0. Bit n corresponds to DMA channel n. The number + * of bits = number of DMA channels in this device. Other bits are reserved. 0 = no effect. 1 = + * sets the TRIG bit for DMA channel n. + */ #define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK) /*! @} */ @@ -6222,8 +7137,12 @@ typedef struct { /*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */ /*! @{ */ + #define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU) #define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U) +/*! ABORTCTRL - Abort control for DMA channel 0. Bit n corresponds to DMA channel n. 0 = no effect. + * 1 = aborts DMA operations on channel n. + */ #define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK) /*! @} */ @@ -6232,6 +7151,7 @@ typedef struct { /*! @name CHANNEL_CFG - Configuration register for DMA channel . */ /*! @{ */ + #define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U) #define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U) /*! PERIPHREQEN - Peripheral request Enable. If a DMA channel is used to perform a memory-to-memory @@ -6241,6 +7161,7 @@ typedef struct { * 0b1..Enabled. Peripheral DMA requests are enabled. */ #define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK) + #define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U) #define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U) /*! HWTRIGEN - Hardware Triggering Enable for this channel. @@ -6248,6 +7169,7 @@ typedef struct { * 0b1..Enabled. Use hardware triggering. */ #define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK) + #define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U) #define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U) /*! TRIGPOL - Trigger Polarity. Selects the polarity of a hardware trigger for this channel. @@ -6255,6 +7177,7 @@ typedef struct { * 0b1..Active high - rising edge. Hardware trigger is active high or rising edge triggered, based on TRIGTYPE. */ #define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK) + #define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U) #define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U) /*! TRIGTYPE - Trigger Type. Selects hardware trigger as edge triggered or level triggered. @@ -6266,6 +7189,7 @@ typedef struct { * current BURSTPOWER length are completed. */ #define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK) + #define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U) #define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U) /*! TRIGBURST - Trigger Burst. Selects whether hardware triggers cause a single or burst transfer. @@ -6276,9 +7200,21 @@ typedef struct { * complete. */ #define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK) + #define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U) #define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U) +/*! BURSTPOWER - Burst Power is used in two ways. It always selects the address wrap size when + * SRCBURSTWRAP and/or DSTBURSTWRAP modes are selected (see descriptions elsewhere in this register). + * When the TRIGBURST field elsewhere in this register = 1, Burst Power selects how many + * transfers are performed for each DMA trigger. This can be used, for example, with peripherals that + * contain a FIFO that can initiate a DMA operation when the FIFO reaches a certain level. 0000: + * Burst size = 1 (20). 0001: Burst size = 2 (21). 0010: Burst size = 4 (22). 1010: Burst size = + * 1024 (210). This corresponds to the maximum supported transfer count. others: not supported. The + * total transfer length as defined in the XFERCOUNT bits in the XFERCFG register must be an even + * multiple of the burst size. + */ #define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK) + #define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U) #define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U) /*! SRCBURSTWRAP - Source Burst Wrap. When enabled, the source data address for the DMA is @@ -6289,6 +7225,7 @@ typedef struct { * 0b1..Enabled. Source burst wrapping is enabled for this DMA channel. */ #define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK) + #define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U) #define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U) /*! DSTBURSTWRAP - Destination Burst Wrap. When enabled, the destination data address for the DMA is @@ -6299,16 +7236,21 @@ typedef struct { * 0b1..Enabled. Destination burst wrapping is enabled for this DMA channel. */ #define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK) + #define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U) #define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U) +/*! CHPRIORITY - Priority of this channel when multiple DMA requests are pending. Eight priority + * levels are supported: 0x0 = highest priority. 0x7 = lowest priority. + */ #define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK) /*! @} */ /* The count of DMA_CHANNEL_CFG */ -#define DMA_CHANNEL_CFG_COUNT (30U) +#define DMA_CHANNEL_CFG_COUNT (23U) /*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */ /*! @{ */ + #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U) #define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U) /*! VALIDPENDING - Valid pending flag for this channel. This bit is set when a 1 is written to the @@ -6317,6 +7259,7 @@ typedef struct { * 0b1..Valid pending. */ #define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK) + #define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U) #define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U) /*! TRIG - Trigger flag. Indicates that the trigger for this channel is currently set. This bit is @@ -6328,10 +7271,11 @@ typedef struct { /*! @} */ /* The count of DMA_CHANNEL_CTLSTAT */ -#define DMA_CHANNEL_CTLSTAT_COUNT (30U) +#define DMA_CHANNEL_CTLSTAT_COUNT (23U) /*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */ /*! @{ */ + #define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U) #define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U) /*! CFGVALID - Configuration Valid flag. This bit indicates whether the current channel descriptor @@ -6340,6 +7284,7 @@ typedef struct { * 0b1..Valid. The current channel descriptor is considered valid. */ #define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK) + #define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U) #define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U) /*! RELOAD - Indicates whether the channel's control structure will be reloaded when the current @@ -6348,6 +7293,7 @@ typedef struct { * 0b1..Enabled. Reload the channels' control structure when the current descriptor is exhausted. */ #define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK) + #define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U) #define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U) /*! SWTRIG - Software Trigger. @@ -6357,6 +7303,7 @@ typedef struct { * be used with level triggering when TRIGBURST = 0. */ #define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK) + #define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U) #define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U) /*! CLRTRIG - Clear Trigger. @@ -6364,6 +7311,7 @@ typedef struct { * 0b1..Cleared. The trigger is cleared when this descriptor is exhausted */ #define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK) + #define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U) #define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U) /*! SETINTA - Set Interrupt flag A for this channel. There is no hardware distinction between @@ -6373,6 +7321,7 @@ typedef struct { * 0b1..Set. The INTA flag for this channel will be set when the current descriptor is exhausted. */ #define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK) + #define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U) #define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U) /*! SETINTB - Set Interrupt flag B for this channel. There is no hardware distinction between @@ -6382,6 +7331,7 @@ typedef struct { * 0b1..Set. The INTB flag for this channel will be set when the current descriptor is exhausted. */ #define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK) + #define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U) #define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U) /*! WIDTH - Transfer width used for this DMA channel. @@ -6391,6 +7341,7 @@ typedef struct { * 0b11..Reserved. Reserved setting, do not use. */ #define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK) + #define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U) #define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U) /*! SRCINC - Determines whether the source address is incremented for each DMA transfer. @@ -6401,6 +7352,7 @@ typedef struct { * 0b11..4 x width. The source address is incremented by 4 times the amount specified by Width for each transfer. */ #define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK) + #define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U) #define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U) /*! DSTINC - Determines whether the destination address is incremented for each DMA transfer. @@ -6412,13 +7364,21 @@ typedef struct { * 0b11..4 x width. The destination address is incremented by 4 times the amount specified by Width for each transfer. */ #define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK) + #define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U) #define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U) +/*! XFERCOUNT - Total number of transfers to be performed, minus 1 encoded. The number of bytes + * transferred is: (XFERCOUNT + 1) x data width (as defined by the WIDTH field). The DMA controller + * uses this bit field during transfer to count down. Hence, it cannot be used by software to read + * back the size of the transfer, for instance, in an interrupt handler. 0x0 = a total of 1 + * transfer will be performed. 0x1 = a total of 2 transfers will be performed. 0x3FF = a total of + * 1,024 transfers will be performed. + */ #define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) /*! @} */ /* The count of DMA_CHANNEL_XFERCFG */ -#define DMA_CHANNEL_XFERCFG_COUNT (30U) +#define DMA_CHANNEL_XFERCFG_COUNT (23U) /*! @@ -6427,7 +7387,7 @@ typedef struct { /* DMA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral DMA0 base address */ #define DMA0_BASE (0x50082000u) /** Peripheral DMA0 base address */ @@ -6487,13 +7447,12 @@ typedef struct { typedef struct { __O uint32_t CMD; /**< command register, offset: 0x0 */ __O uint32_t EVENT; /**< event register, offset: 0x4 */ - __IO uint32_t BURST; /**< read burst register, offset: 0x8 */ - uint8_t RESERVED_0[4]; + uint8_t RESERVED_0[8]; __IO uint32_t STARTA; /**< start (or only) address for next flash command, offset: 0x10 */ __IO uint32_t STOPA; /**< end address for next flash command, if command operates on address ranges, offset: 0x14 */ uint8_t RESERVED_1[104]; - __IO uint32_t DATAW[8]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ - uint8_t RESERVED_2[3896]; + __IO uint32_t DATAW[4]; /**< data register, word 0-7; Memory data, or command parameter, or command result., array offset: 0x80, array step: 0x4 */ + uint8_t RESERVED_2[3912]; __O uint32_t INT_CLR_ENABLE; /**< Clear interrupt enable bits, offset: 0xFD8 */ __O uint32_t INT_SET_ENABLE; /**< Set interrupt enable bits, offset: 0xFDC */ __I uint32_t INT_STATUS; /**< Interrupt status bits, offset: 0xFE0 */ @@ -6515,173 +7474,263 @@ typedef struct { /*! @name CMD - command register */ /*! @{ */ + #define FLASH_CMD_CMD_MASK (0xFFFFFFFFU) #define FLASH_CMD_CMD_SHIFT (0U) +/*! CMD - command register. + */ #define FLASH_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMD_CMD_SHIFT)) & FLASH_CMD_CMD_MASK) /*! @} */ /*! @name EVENT - event register */ /*! @{ */ + #define FLASH_EVENT_RST_MASK (0x1U) #define FLASH_EVENT_RST_SHIFT (0U) +/*! RST - When bit is set, the controller and flash are reset. + */ #define FLASH_EVENT_RST(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_RST_SHIFT)) & FLASH_EVENT_RST_MASK) + #define FLASH_EVENT_WAKEUP_MASK (0x2U) #define FLASH_EVENT_WAKEUP_SHIFT (1U) +/*! WAKEUP - When bit is set, the controller wakes up from whatever low power or powerdown mode was active. + */ #define FLASH_EVENT_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_WAKEUP_SHIFT)) & FLASH_EVENT_WAKEUP_MASK) + #define FLASH_EVENT_ABORT_MASK (0x4U) #define FLASH_EVENT_ABORT_SHIFT (2U) +/*! ABORT - When bit is set, a running program/erase command is aborted. + */ #define FLASH_EVENT_ABORT(x) (((uint32_t)(((uint32_t)(x)) << FLASH_EVENT_ABORT_SHIFT)) & FLASH_EVENT_ABORT_MASK) /*! @} */ -/*! @name BURST - read burst register */ -/*! @{ */ -#define FLASH_BURST_XOR_MASK_MASK (0xFFFFFU) -#define FLASH_BURST_XOR_MASK_SHIFT (0U) -#define FLASH_BURST_XOR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_XOR_MASK_SHIFT)) & FLASH_BURST_XOR_MASK_MASK) -#define FLASH_BURST_DESCR1_MASK (0xF00000U) -#define FLASH_BURST_DESCR1_SHIFT (20U) -#define FLASH_BURST_DESCR1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR1_SHIFT)) & FLASH_BURST_DESCR1_MASK) -#define FLASH_BURST_DESCR2_MASK (0xF000000U) -#define FLASH_BURST_DESCR2_SHIFT (24U) -#define FLASH_BURST_DESCR2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR2_SHIFT)) & FLASH_BURST_DESCR2_MASK) -#define FLASH_BURST_DESCR3_MASK (0xF0000000U) -#define FLASH_BURST_DESCR3_SHIFT (28U) -#define FLASH_BURST_DESCR3(x) (((uint32_t)(((uint32_t)(x)) << FLASH_BURST_DESCR3_SHIFT)) & FLASH_BURST_DESCR3_MASK) -/*! @} */ - /*! @name STARTA - start (or only) address for next flash command */ /*! @{ */ + #define FLASH_STARTA_STARTA_MASK (0x3FFFFU) #define FLASH_STARTA_STARTA_SHIFT (0U) +/*! STARTA - Address / Start address for commands that take an address (range) as a parameter. + */ #define FLASH_STARTA_STARTA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STARTA_STARTA_SHIFT)) & FLASH_STARTA_STARTA_MASK) /*! @} */ /*! @name STOPA - end address for next flash command, if command operates on address ranges */ /*! @{ */ + #define FLASH_STOPA_STOPA_MASK (0x3FFFFU) #define FLASH_STOPA_STOPA_SHIFT (0U) +/*! STOPA - Stop address for commands that take an address range as a parameter (the word specified + * by STOPA is included in the address range). + */ #define FLASH_STOPA_STOPA(x) (((uint32_t)(((uint32_t)(x)) << FLASH_STOPA_STOPA_SHIFT)) & FLASH_STOPA_STOPA_MASK) /*! @} */ /*! @name DATAW - data register, word 0-7; Memory data, or command parameter, or command result. */ /*! @{ */ + #define FLASH_DATAW_DATAW_MASK (0xFFFFFFFFU) #define FLASH_DATAW_DATAW_SHIFT (0U) #define FLASH_DATAW_DATAW(x) (((uint32_t)(((uint32_t)(x)) << FLASH_DATAW_DATAW_SHIFT)) & FLASH_DATAW_DATAW_MASK) /*! @} */ /* The count of FLASH_DATAW */ -#define FLASH_DATAW_COUNT (8U) +#define FLASH_DATAW_COUNT (4U) /*! @name INT_CLR_ENABLE - Clear interrupt enable bits */ /*! @{ */ + #define FLASH_INT_CLR_ENABLE_FAIL_MASK (0x1U) #define FLASH_INT_CLR_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ #define FLASH_INT_CLR_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_FAIL_SHIFT)) & FLASH_INT_CLR_ENABLE_FAIL_MASK) + #define FLASH_INT_CLR_ENABLE_ERR_MASK (0x2U) #define FLASH_INT_CLR_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ #define FLASH_INT_CLR_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ERR_MASK) + #define FLASH_INT_CLR_ENABLE_DONE_MASK (0x4U) #define FLASH_INT_CLR_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ #define FLASH_INT_CLR_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_DONE_SHIFT)) & FLASH_INT_CLR_ENABLE_DONE_MASK) + #define FLASH_INT_CLR_ENABLE_ECC_ERR_MASK (0x8U) #define FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is cleared. + */ #define FLASH_INT_CLR_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_CLR_ENABLE_ECC_ERR_MASK) /*! @} */ /*! @name INT_SET_ENABLE - Set interrupt enable bits */ /*! @{ */ + #define FLASH_INT_SET_ENABLE_FAIL_MASK (0x1U) #define FLASH_INT_SET_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ #define FLASH_INT_SET_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_FAIL_SHIFT)) & FLASH_INT_SET_ENABLE_FAIL_MASK) + #define FLASH_INT_SET_ENABLE_ERR_MASK (0x2U) #define FLASH_INT_SET_ENABLE_ERR_SHIFT (1U) +/*! ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ #define FLASH_INT_SET_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ERR_MASK) + #define FLASH_INT_SET_ENABLE_DONE_MASK (0x4U) #define FLASH_INT_SET_ENABLE_DONE_SHIFT (2U) +/*! DONE - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ #define FLASH_INT_SET_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_DONE_SHIFT)) & FLASH_INT_SET_ENABLE_DONE_MASK) + #define FLASH_INT_SET_ENABLE_ECC_ERR_MASK (0x8U) #define FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_ENABLE bit is written to 1, the corresponding INT_ENABLE bit is set. + */ #define FLASH_INT_SET_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_SET_ENABLE_ECC_ERR_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt status bits */ /*! @{ */ + #define FLASH_INT_STATUS_FAIL_MASK (0x1U) #define FLASH_INT_STATUS_FAIL_SHIFT (0U) +/*! FAIL - This status bit is set if execution of a (legal) command failed. + */ #define FLASH_INT_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_FAIL_SHIFT)) & FLASH_INT_STATUS_FAIL_MASK) + #define FLASH_INT_STATUS_ERR_MASK (0x2U) #define FLASH_INT_STATUS_ERR_SHIFT (1U) +/*! ERR - This status bit is set if execution of an illegal command is detected. + */ #define FLASH_INT_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ERR_SHIFT)) & FLASH_INT_STATUS_ERR_MASK) + #define FLASH_INT_STATUS_DONE_MASK (0x4U) #define FLASH_INT_STATUS_DONE_SHIFT (2U) +/*! DONE - This status bit is set at the end of command execution. + */ #define FLASH_INT_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_DONE_SHIFT)) & FLASH_INT_STATUS_DONE_MASK) + #define FLASH_INT_STATUS_ECC_ERR_MASK (0x8U) #define FLASH_INT_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - This status bit is set if, during a memory read operation (either a user-requested + * read, or a speculative read, or reads performed by a controller command), a correctable or + * uncorrectable error is detected by ECC decoding logic. + */ #define FLASH_INT_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_STATUS_ECC_ERR_MASK) /*! @} */ /*! @name INT_ENABLE - Interrupt enable bits */ /*! @{ */ + #define FLASH_INT_ENABLE_FAIL_MASK (0x1U) #define FLASH_INT_ENABLE_FAIL_SHIFT (0U) +/*! FAIL - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ #define FLASH_INT_ENABLE_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_FAIL_SHIFT)) & FLASH_INT_ENABLE_FAIL_MASK) + #define FLASH_INT_ENABLE_ERR_MASK (0x2U) #define FLASH_INT_ENABLE_ERR_SHIFT (1U) +/*! ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ #define FLASH_INT_ENABLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ERR_SHIFT)) & FLASH_INT_ENABLE_ERR_MASK) + #define FLASH_INT_ENABLE_DONE_MASK (0x4U) #define FLASH_INT_ENABLE_DONE_SHIFT (2U) +/*! DONE - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ #define FLASH_INT_ENABLE_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_DONE_SHIFT)) & FLASH_INT_ENABLE_DONE_MASK) + #define FLASH_INT_ENABLE_ECC_ERR_MASK (0x8U) #define FLASH_INT_ENABLE_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - If an INT_ENABLE bit is set, an interrupt request will be generated if the corresponding INT_STATUS bit is high. + */ #define FLASH_INT_ENABLE_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_ENABLE_ECC_ERR_SHIFT)) & FLASH_INT_ENABLE_ECC_ERR_MASK) /*! @} */ /*! @name INT_CLR_STATUS - Clear interrupt status bits */ /*! @{ */ + #define FLASH_INT_CLR_STATUS_FAIL_MASK (0x1U) #define FLASH_INT_CLR_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ #define FLASH_INT_CLR_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_FAIL_SHIFT)) & FLASH_INT_CLR_STATUS_FAIL_MASK) + #define FLASH_INT_CLR_STATUS_ERR_MASK (0x2U) #define FLASH_INT_CLR_STATUS_ERR_SHIFT (1U) +/*! ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ #define FLASH_INT_CLR_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ERR_MASK) + #define FLASH_INT_CLR_STATUS_DONE_MASK (0x4U) #define FLASH_INT_CLR_STATUS_DONE_SHIFT (2U) +/*! DONE - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ #define FLASH_INT_CLR_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_DONE_SHIFT)) & FLASH_INT_CLR_STATUS_DONE_MASK) + #define FLASH_INT_CLR_STATUS_ECC_ERR_MASK (0x8U) #define FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a CLR_STATUS bit is written to 1, the corresponding INT_STATUS bit is cleared. + */ #define FLASH_INT_CLR_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_CLR_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_CLR_STATUS_ECC_ERR_MASK) /*! @} */ /*! @name INT_SET_STATUS - Set interrupt status bits */ /*! @{ */ + #define FLASH_INT_SET_STATUS_FAIL_MASK (0x1U) #define FLASH_INT_SET_STATUS_FAIL_SHIFT (0U) +/*! FAIL - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ #define FLASH_INT_SET_STATUS_FAIL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_FAIL_SHIFT)) & FLASH_INT_SET_STATUS_FAIL_MASK) + #define FLASH_INT_SET_STATUS_ERR_MASK (0x2U) #define FLASH_INT_SET_STATUS_ERR_SHIFT (1U) +/*! ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ #define FLASH_INT_SET_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ERR_MASK) + #define FLASH_INT_SET_STATUS_DONE_MASK (0x4U) #define FLASH_INT_SET_STATUS_DONE_SHIFT (2U) +/*! DONE - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ #define FLASH_INT_SET_STATUS_DONE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_DONE_SHIFT)) & FLASH_INT_SET_STATUS_DONE_MASK) + #define FLASH_INT_SET_STATUS_ECC_ERR_MASK (0x8U) #define FLASH_INT_SET_STATUS_ECC_ERR_SHIFT (3U) +/*! ECC_ERR - When a SET_STATUS bit is written to 1, the corresponding INT_STATUS bit is set. + */ #define FLASH_INT_SET_STATUS_ECC_ERR(x) (((uint32_t)(((uint32_t)(x)) << FLASH_INT_SET_STATUS_ECC_ERR_SHIFT)) & FLASH_INT_SET_STATUS_ECC_ERR_MASK) /*! @} */ /*! @name MODULE_ID - Controller+Memory module identification */ /*! @{ */ + #define FLASH_MODULE_ID_APERTURE_MASK (0xFFU) #define FLASH_MODULE_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. + */ #define FLASH_MODULE_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_APERTURE_SHIFT)) & FLASH_MODULE_ID_APERTURE_MASK) + #define FLASH_MODULE_ID_MINOR_REV_MASK (0xF00U) #define FLASH_MODULE_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision i. + */ #define FLASH_MODULE_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MINOR_REV_SHIFT)) & FLASH_MODULE_ID_MINOR_REV_MASK) + #define FLASH_MODULE_ID_MAJOR_REV_MASK (0xF000U) #define FLASH_MODULE_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision i. + */ #define FLASH_MODULE_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_MAJOR_REV_SHIFT)) & FLASH_MODULE_ID_MAJOR_REV_MASK) + #define FLASH_MODULE_ID_ID_MASK (0xFFFF0000U) #define FLASH_MODULE_ID_ID_SHIFT (16U) +/*! ID - Identifier. + */ #define FLASH_MODULE_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_MODULE_ID_ID_SHIFT)) & FLASH_MODULE_ID_ID_MASK) /*! @} */ @@ -6692,7 +7741,7 @@ typedef struct { /* FLASH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral FLASH base address */ #define FLASH_BASE (0x50034000u) /** Peripheral FLASH base address */ @@ -6736,45 +7785,45 @@ typedef struct { /** FLASH_CFPA - Register Layout Typedef */ typedef struct { - __IO uint32_t HEADER; /**< ., offset: 0x0 */ - __IO uint32_t VERSION; /**< ., offset: 0x4 */ + __IO uint32_t HEADER; /**< , offset: 0x0 */ + __IO uint32_t VERSION; /**< , offset: 0x4 */ __IO uint32_t S_FW_VERSION; /**< Secure firmware version (Monotonic counter), offset: 0x8 */ __IO uint32_t NS_FW_VERSION; /**< Non-Secure firmware version (Monotonic counter), offset: 0xC */ __IO uint32_t IMAGE_KEY_REVOKE; /**< Image key revocation ID (Monotonic counter), offset: 0x10 */ uint8_t RESERVED_0[4]; - __IO uint32_t ROTKH_REVOKE; /**< ., offset: 0x18 */ - __IO uint32_t VENDOR_USAGE; /**< ., offset: 0x1C */ + __IO uint32_t ROTKH_REVOKE; /**< , offset: 0x18 */ + __IO uint32_t VENDOR_USAGE; /**< , offset: 0x1C */ __IO uint32_t DCFG_CC_SOCU_PIN; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x20 */ __IO uint32_t DCFG_CC_SOCU_DFLT; /**< With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access., offset: 0x24 */ __IO uint32_t ENABLE_FA_MODE; /**< Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode., offset: 0x28 */ __IO uint32_t CMPA_PROG_IN_PROGRESS; /**< CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area., offset: 0x2C */ union { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< ., array offset: 0x30, array step: 0x4 */ + __IO uint32_t PRINCE_REGION0_IV_CODE[14]; /**< , array offset: 0x30, array step: 0x4 */ struct { /* offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< ., offset: 0x30 */ - __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< ., offset: 0x34 */ - __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< ., array offset: 0x38, array step: 0x4 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER0; /**< , offset: 0x30 */ + __IO uint32_t PRINCE_REGION0_IV_HEADER1; /**< , offset: 0x34 */ + __IO uint32_t PRINCE_REGION0_IV_BODY[12]; /**< , array offset: 0x38, array step: 0x4 */ } PRINCE_REGION0_IV_CODE_CORE; }; union { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< ., array offset: 0x68, array step: 0x4 */ + __IO uint32_t PRINCE_REGION1_IV_CODE[14]; /**< , array offset: 0x68, array step: 0x4 */ struct { /* offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< ., offset: 0x68 */ - __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< ., offset: 0x6C */ - __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< ., array offset: 0x70, array step: 0x4 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER0; /**< , offset: 0x68 */ + __IO uint32_t PRINCE_REGION1_IV_HEADER1; /**< , offset: 0x6C */ + __IO uint32_t PRINCE_REGION1_IV_BODY[12]; /**< , array offset: 0x70, array step: 0x4 */ } PRINCE_REGION1_IV_CODE_CORE; }; union { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< ., array offset: 0xA0, array step: 0x4 */ + __IO uint32_t PRINCE_REGION2_IV_CODE[14]; /**< , array offset: 0xA0, array step: 0x4 */ struct { /* offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< ., offset: 0xA0 */ - __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< ., offset: 0xA4 */ - __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< ., array offset: 0xA8, array step: 0x4 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER0; /**< , offset: 0xA0 */ + __IO uint32_t PRINCE_REGION2_IV_HEADER1; /**< , offset: 0xA4 */ + __IO uint32_t PRINCE_REGION2_IV_BODY[12]; /**< , array offset: 0xA8, array step: 0x4 */ } PRINCE_REGION2_IV_CODE_CORE; }; uint8_t RESERVED_1[40]; __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ } FLASH_CFPA_Type; /* ---------------------------------------------------------------------------- @@ -6786,15 +7835,17 @@ typedef struct { * @{ */ -/*! @name HEADER - . */ +/*! @name HEADER - */ /*! @{ */ + #define FLASH_CFPA_HEADER_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_HEADER_FIELD_SHIFT (0U) #define FLASH_CFPA_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_HEADER_FIELD_SHIFT)) & FLASH_CFPA_HEADER_FIELD_MASK) /*! @} */ -/*! @name VERSION - . */ +/*! @name VERSION - */ /*! @{ */ + #define FLASH_CFPA_VERSION_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_VERSION_FIELD_SHIFT (0U) #define FLASH_CFPA_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VERSION_FIELD_SHIFT)) & FLASH_CFPA_VERSION_FIELD_MASK) @@ -6802,6 +7853,7 @@ typedef struct { /*! @name S_FW_VERSION - Secure firmware version (Monotonic counter) */ /*! @{ */ + #define FLASH_CFPA_S_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT (0U) #define FLASH_CFPA_S_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_S_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_S_FW_VERSION_FIELD_MASK) @@ -6809,6 +7861,7 @@ typedef struct { /*! @name NS_FW_VERSION - Non-Secure firmware version (Monotonic counter) */ /*! @{ */ + #define FLASH_CFPA_NS_FW_VERSION_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT (0U) #define FLASH_CFPA_NS_FW_VERSION_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_NS_FW_VERSION_FIELD_SHIFT)) & FLASH_CFPA_NS_FW_VERSION_FIELD_MASK) @@ -6816,36 +7869,59 @@ typedef struct { /*! @name IMAGE_KEY_REVOKE - Image key revocation ID (Monotonic counter) */ /*! @{ */ + #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT (0U) #define FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_SHIFT)) & FLASH_CFPA_IMAGE_KEY_REVOKE_FIELD_MASK) /*! @} */ -/*! @name ROTKH_REVOKE - . */ +/*! @name ROTKH_REVOKE - */ /*! @{ */ + #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK (0x3U) #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT (0U) +/*! RoTK0_EN - RoT Key 0 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ #define FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK0_EN_MASK) + #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK (0xCU) #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT (2U) +/*! RoTK1_EN - RoT Key 1 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ #define FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK1_EN_MASK) + #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK (0x30U) #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT (4U) +/*! RoTK2_EN - RoT Key 2 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ #define FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK2_EN_MASK) + +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK (0xC0U) +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT (6U) +/*! RoTK3_EN - RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + */ +#define FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_SHIFT)) & FLASH_CFPA_ROTKH_REVOKE_RoTK3_EN_MASK) /*! @} */ -/*! @name VENDOR_USAGE - . */ +/*! @name VENDOR_USAGE - */ /*! @{ */ + #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK (0xFFFFU) #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT (0U) +/*! DBG_VENDOR_USAGE - DBG_VENDOR_USAGE. + */ #define FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_DBG_VENDOR_USAGE_MASK) + #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK (0xFFFF0000U) #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ #define FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_VENDOR_USAGE_INVERSE_VALUE_MASK) /*! @} */ /*! @name DCFG_CC_SOCU_PIN - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ /*! @{ */ + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) /*! NIDEN - Non Secure non-invasive debug enable @@ -6853,6 +7929,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) /*! DBGEN - Non Secure debug enable @@ -6860,6 +7937,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) /*! SPNIDEN - Secure non-invasive debug enable @@ -6867,6 +7945,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) /*! SPIDEN - Secure invasive debug enable @@ -6874,6 +7953,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) /*! TAPEN - JTAG TAP enable @@ -6881,13 +7961,15 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug enable + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_DBGEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) /*! ISP_CMD_EN - ISP Boot Command enable @@ -6895,6 +7977,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) /*! FA_CMD_EN - FA Command enable @@ -6902,6 +7985,7 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) /*! ME_CMD_EN - Flash Mass Erase Command enable @@ -6909,23 +7993,31 @@ typedef struct { * 0b1..Fixed state */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable + +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_CPU1_NIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. + */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ #define FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) /*! @} */ /*! @name DCFG_CC_SOCU_DFLT - With TZ-M, the part can be sold by level 1 customers (secure code developer) to level-2 customers who develops non-secure code only. - In this scenario, or easy of development, Level-I customer releases the part to always allow non-secure debug. - To allow level-2 customers to further seal the part DCFG_CC_SOCU_NS is used. - ROM will use this word to further restrict the debug access. */ /*! @{ */ + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) /*! NIDEN - Non Secure non-invasive debug fixed state @@ -6933,6 +8025,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) /*! DBGEN - Non Secure debug fixed state @@ -6940,6 +8033,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) /*! SPNIDEN - Secure non-invasive debug fixed state @@ -6947,6 +8041,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) /*! SPIDEN - Secure invasive debug fixed state @@ -6954,6 +8049,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) /*! TAPEN - JTAG TAP fixed state @@ -6961,13 +8057,15 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_DBGEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) /*! ISP_CMD_EN - ISP Boot Command fixed state @@ -6975,6 +8073,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) /*! FA_CMD_EN - FA Command fixed state @@ -6982,6 +8081,7 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) /*! ME_CMD_EN - Flash Mass Erase Command fixed state @@ -6989,20 +8089,25 @@ typedef struct { * 0b1..Enable */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state + +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) +#define FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_CPU1_NIDEN_MASK) + #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ #define FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CFPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) /*! @} */ /*! @name ENABLE_FA_MODE - Enable FA mode. SET_FA_MODE Command should write 0xC33CA55A to this word to indicate boot ROM to enter FA mode. */ /*! @{ */ + #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT (0U) #define FLASH_CFPA_ENABLE_FA_MODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_ENABLE_FA_MODE_FIELD_SHIFT)) & FLASH_CFPA_ENABLE_FA_MODE_FIELD_MASK) @@ -7010,13 +8115,15 @@ typedef struct { /*! @name CMPA_PROG_IN_PROGRESS - CMPA Page programming on going. This field shall be set to 0x5CC55AA5 in the active CFPA page each time CMPA page programming is going on. It shall always be set to 0x00000000 in the CFPA scratch area. */ /*! @{ */ + #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT (0U) #define FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_SHIFT)) & FLASH_CFPA_CMPA_PROG_IN_PROGRESS_FIELD_MASK) /*! @} */ -/*! @name PRINCE_REGION0_IV_CODE - . */ +/*! @name PRINCE_REGION0_IV_CODE - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_CODE_FIELD_MASK) @@ -7025,28 +8132,33 @@ typedef struct { /* The count of FLASH_CFPA_PRINCE_REGION0_IV_CODE */ #define FLASH_CFPA_PRINCE_REGION0_IV_CODE_COUNT (14U) -/*! @name PRINCE_REGION0_IV_HEADER0 - . */ +/*! @name PRINCE_REGION0_IV_HEADER0 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER0_FIELD_MASK) /*! @} */ -/*! @name PRINCE_REGION0_IV_HEADER1 - . */ +/*! @name PRINCE_REGION0_IV_HEADER1 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK (0x3U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_TYPE_MASK) + #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK (0xF00U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT (8U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_INDEX_MASK) + #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT (24U) #define FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_HEADER1_SIZE_MASK) /*! @} */ -/*! @name PRINCE_REGION0_IV_BODY - . */ +/*! @name PRINCE_REGION0_IV_BODY - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION0_IV_BODY_FIELD_MASK) @@ -7055,8 +8167,9 @@ typedef struct { /* The count of FLASH_CFPA_PRINCE_REGION0_IV_BODY */ #define FLASH_CFPA_PRINCE_REGION0_IV_BODY_COUNT (12U) -/*! @name PRINCE_REGION1_IV_CODE - . */ +/*! @name PRINCE_REGION1_IV_CODE - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_CODE_FIELD_MASK) @@ -7065,28 +8178,33 @@ typedef struct { /* The count of FLASH_CFPA_PRINCE_REGION1_IV_CODE */ #define FLASH_CFPA_PRINCE_REGION1_IV_CODE_COUNT (14U) -/*! @name PRINCE_REGION1_IV_HEADER0 - . */ +/*! @name PRINCE_REGION1_IV_HEADER0 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER0_FIELD_MASK) /*! @} */ -/*! @name PRINCE_REGION1_IV_HEADER1 - . */ +/*! @name PRINCE_REGION1_IV_HEADER1 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK (0x3U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_TYPE_MASK) + #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK (0xF00U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT (8U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_INDEX_MASK) + #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT (24U) #define FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_HEADER1_SIZE_MASK) /*! @} */ -/*! @name PRINCE_REGION1_IV_BODY - . */ +/*! @name PRINCE_REGION1_IV_BODY - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION1_IV_BODY_FIELD_MASK) @@ -7095,8 +8213,9 @@ typedef struct { /* The count of FLASH_CFPA_PRINCE_REGION1_IV_BODY */ #define FLASH_CFPA_PRINCE_REGION1_IV_BODY_COUNT (12U) -/*! @name PRINCE_REGION2_IV_CODE - . */ +/*! @name PRINCE_REGION2_IV_CODE - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_CODE_FIELD_MASK) @@ -7105,28 +8224,33 @@ typedef struct { /* The count of FLASH_CFPA_PRINCE_REGION2_IV_CODE */ #define FLASH_CFPA_PRINCE_REGION2_IV_CODE_COUNT (14U) -/*! @name PRINCE_REGION2_IV_HEADER0 - . */ +/*! @name PRINCE_REGION2_IV_HEADER0 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER0_FIELD_MASK) /*! @} */ -/*! @name PRINCE_REGION2_IV_HEADER1 - . */ +/*! @name PRINCE_REGION2_IV_HEADER1 - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK (0x3U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_TYPE_MASK) + #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK (0xF00U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT (8U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_INDEX_MASK) + #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT (24U) #define FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_HEADER1_SIZE_MASK) /*! @} */ -/*! @name PRINCE_REGION2_IV_BODY - . */ +/*! @name PRINCE_REGION2_IV_BODY - */ /*! @{ */ + #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT (0U) #define FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_SHIFT)) & FLASH_CFPA_PRINCE_REGION2_IV_BODY_FIELD_MASK) @@ -7137,6 +8261,7 @@ typedef struct { /*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ /*! @{ */ + #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) #define FLASH_CFPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CFPA_CUSTOMER_DEFINED_FIELD_MASK) @@ -7145,8 +8270,9 @@ typedef struct { /* The count of FLASH_CFPA_CUSTOMER_DEFINED */ #define FLASH_CFPA_CUSTOMER_DEFINED_COUNT (56U) -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ /*! @{ */ + #define FLASH_CFPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT (0U) #define FLASH_CFPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CFPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CFPA_SHA256_DIGEST_FIELD_MASK) @@ -7162,7 +8288,7 @@ typedef struct { /* FLASH_CFPA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral FLASH_CFPA0 base address */ #define FLASH_CFPA0_BASE (0x1009E000u) /** Peripheral FLASH_CFPA0 base address */ @@ -7230,23 +8356,25 @@ typedef struct { /** FLASH_CMPA - Register Layout Typedef */ typedef struct { - __IO uint32_t BOOT_CFG; /**< ., offset: 0x0 */ - __IO uint32_t SPI_FLASH_CFG; /**< ., offset: 0x4 */ - __IO uint32_t USB_ID; /**< ., offset: 0x8 */ - __IO uint32_t SDIO_CFG; /**< ., offset: 0xC */ - __IO uint32_t DCFG_CC_SOCU_PIN; /**< ., offset: 0x10 */ - __IO uint32_t DCFG_CC_SOCU_DFLT; /**< ., offset: 0x14 */ - __IO uint32_t DAP_VENDOR_USAGE_FIXED; /**< ., offset: 0x18 */ - __IO uint32_t SECURE_BOOT_CFG; /**< ., offset: 0x1C */ - __IO uint32_t PRINCE_BASE_ADDR; /**< ., offset: 0x20 */ + __IO uint32_t BOOT_CFG; /**< , offset: 0x0 */ + __IO uint32_t SPI_FLASH_CFG; /**< , offset: 0x4 */ + __IO uint32_t USB_ID; /**< , offset: 0x8 */ + __IO uint32_t SDIO_CFG; /**< , offset: 0xC */ + __IO uint32_t CC_SOCU_PIN; /**< , offset: 0x10 */ + __IO uint32_t CC_SOCU_DFLT; /**< , offset: 0x14 */ + __IO uint32_t VENDOR_USAGE; /**< , offset: 0x18 */ + __IO uint32_t SECURE_BOOT_CFG; /**< Secure boot configuration flags., offset: 0x1C */ + __IO uint32_t PRINCE_BASE_ADDR; /**< , offset: 0x20 */ __IO uint32_t PRINCE_SR_0; /**< Region 0, sub-region enable, offset: 0x24 */ __IO uint32_t PRINCE_SR_1; /**< Region 1, sub-region enable, offset: 0x28 */ __IO uint32_t PRINCE_SR_2; /**< Region 2, sub-region enable, offset: 0x2C */ - uint8_t RESERVED_0[32]; - __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ + __IO uint32_t XTAL_32KHZ_CAPABANK_TRIM; /**< Xtal 32kHz capabank triming., offset: 0x30 */ + __IO uint32_t XTAL_16MHZ_CAPABANK_TRIM; /**< Xtal 16MHz capabank triming., offset: 0x34 */ + uint8_t RESERVED_0[24]; + __IO uint32_t ROTKH[8]; /**< ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0], array offset: 0x50, array step: 0x4 */ uint8_t RESERVED_1[144]; __IO uint32_t CUSTOMER_DEFINED[56]; /**< Customer Defined (Programable through ROM API), array offset: 0x100, array step: 0x4 */ - __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ + __IO uint32_t SHA256_DIGEST[8]; /**< SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224], array offset: 0x1E0, array step: 0x4 */ } FLASH_CMPA_Type; /* ---------------------------------------------------------------------------- @@ -7258,280 +8386,430 @@ typedef struct { * @{ */ -/*! @name BOOT_CFG - . */ +/*! @name BOOT_CFG - */ /*! @{ */ + #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK (0x70U) #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT (4U) /*! DEFAULT_ISP_MODE - Default ISP mode: * 0b000..Auto ISP - * 0b001..USB_HID_MSC - * 0b010..SPI Slave ISP - * 0b011..I2C Slave ISP + * 0b001..USB_HID_ISP + * 0b010..UART ISP + * 0b011..SPI Slave ISP + * 0b100..I2C Slave ISP * 0b111..Disable ISP fall through */ #define FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_SHIFT)) & FLASH_CMPA_BOOT_CFG_DEFAULT_ISP_MODE_MASK) + #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK (0x180U) #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT (7U) /*! BOOT_SPEED - Core clock: * 0b00..Defined by NMPA.SYSTEM_SPEED_CODE - * 0b01..48MHz FRO - * 0b10..96MHz FRO + * 0b01..96MHz FRO + * 0b10..48MHz FRO */ #define FLASH_CMPA_BOOT_CFG_BOOT_SPEED(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_SPEED_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_SPEED_MASK) + #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK (0xFF000000U) #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT (24U) +/*! BOOT_FAILURE_PIN - GPIO port and pin number to use for indicating failure reason. The toggle + * rate of the pin is used to decode the error type. [2:0] - Defines GPIO port [7:3] - Defines GPIO + * pin + */ #define FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_SHIFT)) & FLASH_CMPA_BOOT_CFG_BOOT_FAILURE_PIN_MASK) /*! @} */ -/*! @name SPI_FLASH_CFG - . */ +/*! @name SPI_FLASH_CFG - */ /*! @{ */ -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK (0xFFFFFFFFU) -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT (0U) -#define FLASH_CMPA_SPI_FLASH_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_FIELD_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_FIELD_MASK) + +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK (0x1FU) +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT (0U) +/*! SPI_RECOVERY_BOOT_EN - SPI flash recovery boot is enabled, if non-zero value is written to this field. + */ +#define FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_SHIFT)) & FLASH_CMPA_SPI_FLASH_CFG_SPI_RECOVERY_BOOT_EN_MASK) /*! @} */ -/*! @name USB_ID - . */ +/*! @name USB_ID - */ /*! @{ */ + #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK (0xFFFFU) #define FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT (0U) #define FLASH_CMPA_USB_ID_USB_VENDOR_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_VENDOR_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_VENDOR_ID_MASK) + #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK (0xFFFF0000U) #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT (16U) #define FLASH_CMPA_USB_ID_USB_PRODUCT_ID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_USB_ID_USB_PRODUCT_ID_SHIFT)) & FLASH_CMPA_USB_ID_USB_PRODUCT_ID_MASK) /*! @} */ -/*! @name SDIO_CFG - . */ +/*! @name SDIO_CFG - */ /*! @{ */ + #define FLASH_CMPA_SDIO_CFG_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_SDIO_CFG_FIELD_SHIFT (0U) #define FLASH_CMPA_SDIO_CFG_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SDIO_CFG_FIELD_SHIFT)) & FLASH_CMPA_SDIO_CFG_FIELD_MASK) /*! @} */ -/*! @name DCFG_CC_SOCU_PIN - . */ +/*! @name CC_SOCU_PIN - */ /*! @{ */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK (0x1U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT (0U) + +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT (0U) /*! NIDEN - Non Secure non-invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK (0x2U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT (1U) +#define FLASH_CMPA_CC_SOCU_PIN_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT (1U) /*! DBGEN - Non Secure debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) +#define FLASH_CMPA_CC_SOCU_PIN_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT (2U) /*! SPNIDEN - Secure non-invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPNIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT (3U) +#define FLASH_CMPA_CC_SOCU_PIN_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT (3U) /*! SPIDEN - Secure invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_SPIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK (0x10U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT (4U) +#define FLASH_CMPA_CC_SOCU_PIN_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT (4U) /*! TAPEN - JTAG TAP enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_TAPEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug enable +#define FLASH_CMPA_CC_SOCU_PIN_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT (6U) /*! ISP_CMD_EN - ISP Boot Command enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ISP_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) +#define FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT (7U) /*! FA_CMD_EN - FA Command enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_FA_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) +#define FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_FA_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT (8U) /*! ME_CMD_EN - Flash Mass Erase Command enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_ME_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug enable +#define FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug enable * 0b0..Use DAP to enable * 0b1..Fixed state */ -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_MCM33_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_UUID_CHECK_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_PIN_INVERSE_VALUE_MASK) +#define FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_CPU1_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK (0x8000U) +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT (15U) +/*! UUID_CHECK - Enforce UUID match during Debug authentication. + */ +#define FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_UUID_CHECK_MASK) + +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_PIN_INVERSE_VALUE_MASK) /*! @} */ -/*! @name DCFG_CC_SOCU_DFLT - . */ +/*! @name CC_SOCU_DFLT - */ /*! @{ */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK (0x1U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT (0U) + +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK (0x1U) +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT (0U) /*! NIDEN - Non Secure non-invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK (0x2U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT (1U) +#define FLASH_CMPA_CC_SOCU_DFLT_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK (0x2U) +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT (1U) /*! DBGEN - Non Secure debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) +#define FLASH_CMPA_CC_SOCU_DFLT_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK (0x4U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT (2U) /*! SPNIDEN - Secure non-invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPNIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPNIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK (0x8U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT (3U) /*! SPIDEN - Secure invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_SPIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK (0x10U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT (4U) +#define FLASH_CMPA_CC_SOCU_DFLT_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_SPIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK (0x10U) +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT (4U) /*! TAPEN - JTAG TAP fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_TAPEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK (0x20U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT (5U) -/*! MCM33_DBGEN - Micro CM33 invasive debug fixed state +#define FLASH_CMPA_CC_SOCU_DFLT_TAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_TAPEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_TAPEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK (0x20U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT (5U) +/*! CPU1_DBGEN - CPU1 (Micro cortex M33) invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_DBGEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_DBGEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK (0x40U) +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT (6U) /*! ISP_CMD_EN - ISP Boot Command fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ISP_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) +#define FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ISP_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK (0x80U) +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT (7U) /*! FA_CMD_EN - FA Command fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_FA_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) +#define FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_FA_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK (0x100U) +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT (8U) /*! ME_CMD_EN - Flash Mass Erase Command fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_ME_CMD_EN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK (0x200U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT (9U) -/*! MCM33_NIDEN - Micro CM33 non-invasive debug fixed state +#define FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_ME_CMD_EN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK (0x200U) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT (9U) +/*! CPU1_NIDEN - CPU1 (Micro cortex M33) non-invasive debug fixed state * 0b0..Disable * 0b1..Enable */ -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_MCM33_NIDEN_MASK) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) -#define FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_DCFG_CC_SOCU_DFLT_INVERSE_VALUE_MASK) +#define FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_CPU1_NIDEN_MASK) + +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK (0xFFFF0000U) +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT (16U) +/*! INVERSE_VALUE - inverse value of bits [15:0] + */ +#define FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_SHIFT)) & FLASH_CMPA_CC_SOCU_DFLT_INVERSE_VALUE_MASK) /*! @} */ -/*! @name DAP_VENDOR_USAGE_FIXED - . */ +/*! @name VENDOR_USAGE - */ /*! @{ */ -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK (0xFFFF0000U) -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT (16U) -#define FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_DAP_VENDOR_USAGE_FIXED_VENDOR_USAGE_MASK) + +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK (0xFFFF0000U) +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT (16U) +/*! VENDOR_USAGE - Upper 16 bits of vendor usage field defined in DAP. Lower 16-bits come from customer field area. + */ +#define FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_SHIFT)) & FLASH_CMPA_VENDOR_USAGE_VENDOR_USAGE_MASK) /*! @} */ -/*! @name SECURE_BOOT_CFG - . */ +/*! @name SECURE_BOOT_CFG - Secure boot configuration flags. */ /*! @{ */ + #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK (0x3U) #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT (0U) +/*! RSA4K - Use RSA4096 keys only. + * 0b00..Allow RSA2048 and higher + * 0b01..RSA4096 only + * 0b10..RSA4096 only + * 0b11..RSA4096 only + */ #define FLASH_CMPA_SECURE_BOOT_CFG_RSA4K(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_RSA4K_MASK) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK (0xCU) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT (2U) -#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_ENC_NXP_CFG_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK (0xCU) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT (2U) +/*! DICE_INC_NXP_CFG - Include NXP area in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_NXP_CFG_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK (0x30U) #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT (4U) +/*! DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. + * 0b00..not included + * 0b01..included + * 0b10..included + * 0b11..included + */ #define FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_CUST_CFG_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK (0xC0U) #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT (6U) +/*! SKIP_DICE - Skip DICE computation + * 0b00..Enable DICE + * 0b01..Disable DICE + * 0b10..Disable DICE + * 0b11..Disable DICE + */ #define FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SKIP_DICE_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK (0x300U) #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT (8U) +/*! TZM_IMAGE_TYPE - TrustZone-M mode + * 0b00..TZ-M image mode is taken from application image header + * 0b01..TZ-M disabled image, boots to non-secure mode + * 0b10..TZ-M enabled image, boots to secure mode + * 0b11..TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header + */ #define FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_TZM_IMAGE_TYPE_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK (0xC00U) #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT (10U) +/*! BLOCK_SET_KEY - Block PUF key code generation + * 0b00..Allow PUF Key Code generation + * 0b01..Disable PUF Key Code generation + * 0b10..Disable PUF Key Code generation + * 0b11..Disable PUF Key Code generation + */ #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_SET_KEY_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK (0x3000U) #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT (12U) +/*! BLOCK_ENROLL - Block PUF enrollement + * 0b00..Allow PUF enroll operation + * 0b01..Disable PUF enroll operation + * 0b10..Disable PUF enroll operation + * 0b11..Disable PUF enroll operation + */ #define FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_BLOCK_ENROLL_MASK) + +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK (0xC000U) +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT (14U) +/*! DICE_INC_SEC_EPOCH - Include security EPOCH in DICE + */ +#define FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_DICE_INC_SEC_EPOCH_MASK) + #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK (0xC0000000U) #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT (30U) +/*! SEC_BOOT_EN - Secure boot enable + * 0b00..Plain image (internal flash with or without CRC) + * 0b01..Boot signed images. (internal flash, RSA signed) + * 0b10..Boot signed images. (internal flash, RSA signed) + * 0b11..Boot signed images. (internal flash, RSA signed) + */ #define FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_SHIFT)) & FLASH_CMPA_SECURE_BOOT_CFG_SEC_BOOT_EN_MASK) /*! @} */ -/*! @name PRINCE_BASE_ADDR - . */ +/*! @name PRINCE_BASE_ADDR - */ /*! @{ */ + #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK (0xFU) #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT (0U) +/*! ADDR0_PRG - Programmable portion of the base address of region 0 + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) + #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK (0xF0U) #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT (4U) +/*! ADDR1_PRG - Programmable portion of the base address of region 1 + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR1_PRG_MASK) + #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK (0xF00U) #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT (8U) +/*! ADDR2_PRG - Programmable portion of the base address of region 2 + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR2_PRG_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x30000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16U) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK (0xC0000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (18U) +/*! LOCK_REG0 - Lock PRINCE region0 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG0_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0xC0000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18U) + +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x300000U) +#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (20U) +/*! LOCK_REG1 - Lock PRINCE region1 settings + * 0b00..Region is not locked + * 0b01..Region is locked + * 0b10..Region is locked + * 0b11..Region is locked + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG1_MASK) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x300000U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20U) -#define FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_LOCK_REG2_MASK) + #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK (0x3000000U) #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT (24U) +/*! REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG0_ERASE_CHECK_EN_MASK) + #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK (0xC000000U) #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT (26U) +/*! REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG1_ERASE_CHECK_EN_MASK) + #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK (0x30000000U) #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT (28U) +/*! REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together + * 0b00..Region is disabled + * 0b01..Region is enabled + * 0b10..Region is enabled + * 0b11..Region is enabled + */ #define FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_SHIFT)) & FLASH_CMPA_PRINCE_BASE_ADDR_REG2_ERASE_CHECK_EN_MASK) /*! @} */ /*! @name PRINCE_SR_0 - Region 0, sub-region enable */ /*! @{ */ + #define FLASH_CMPA_PRINCE_SR_0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT (0U) #define FLASH_CMPA_PRINCE_SR_0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_0_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_0_FIELD_MASK) @@ -7539,6 +8817,7 @@ typedef struct { /*! @name PRINCE_SR_1 - Region 1, sub-region enable */ /*! @{ */ + #define FLASH_CMPA_PRINCE_SR_1_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT (0U) #define FLASH_CMPA_PRINCE_SR_1_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_1_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_1_FIELD_MASK) @@ -7546,13 +8825,75 @@ typedef struct { /*! @name PRINCE_SR_2 - Region 2, sub-region enable */ /*! @{ */ + #define FLASH_CMPA_PRINCE_SR_2_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT (0U) #define FLASH_CMPA_PRINCE_SR_2_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_PRINCE_SR_2_FIELD_SHIFT)) & FLASH_CMPA_PRINCE_SR_2_FIELD_MASK) /*! @} */ -/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] */ +/*! @name XTAL_32KHZ_CAPABANK_TRIM - Xtal 32kHz capabank triming. */ /*! @{ */ + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 32kHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_32KHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name XTAL_16MHZ_CAPABANK_TRIM - Xtal 16MHz capabank triming. */ +/*! @{ */ + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK (0x1U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT (0U) +/*! TRIM_VALID - XTAL 16MHz capa bank trimmings + * 0b0..Capa Bank trimmings not valid. Default trimmings value are used + * 0b1..Capa Bank trimmings valid + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_TRIM_VALID_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK (0x7FEU) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT (1U) +/*! XTAL_LOAD_CAP_IEC_PF_X100 - Load capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_XTAL_LOAD_CAP_IEC_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK (0x1FF800U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT (11U) +/*! PCB_XIN_PARA_CAP_PF_X100 - PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XIN_PARA_CAP_PF_X100_MASK) + +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK (0x7FE00000U) +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT (21U) +/*! PCB_XOUT_PARA_CAP_PF_X100 - PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + */ +#define FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_SHIFT)) & FLASH_CMPA_XTAL_16MHZ_CAPABANK_TRIM_PCB_XOUT_PARA_CAP_PF_X100_MASK) +/*! @} */ + +/*! @name ROTKH - ROTKH0 for Root of Trust Keys Table hash[255:224]..ROTKH7 for Root of Trust Keys Table hash[31:0] */ +/*! @{ */ + #define FLASH_CMPA_ROTKH_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_ROTKH_FIELD_SHIFT (0U) #define FLASH_CMPA_ROTKH_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_ROTKH_FIELD_SHIFT)) & FLASH_CMPA_ROTKH_FIELD_MASK) @@ -7563,6 +8904,7 @@ typedef struct { /*! @name CUSTOMER_DEFINED - Customer Defined (Programable through ROM API) */ /*! @{ */ + #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT (0U) #define FLASH_CMPA_CUSTOMER_DEFINED_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_CUSTOMER_DEFINED_FIELD_SHIFT)) & FLASH_CMPA_CUSTOMER_DEFINED_FIELD_MASK) @@ -7571,8 +8913,9 @@ typedef struct { /* The count of FLASH_CMPA_CUSTOMER_DEFINED */ #define FLASH_CMPA_CUSTOMER_DEFINED_COUNT (56U) -/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] */ +/*! @name SHA256_DIGEST - SHA256_DIGEST0 for DIGEST[31:0]..SHA256_DIGEST7 for DIGEST[255:224] */ /*! @{ */ + #define FLASH_CMPA_SHA256_DIGEST_FIELD_MASK (0xFFFFFFFFU) #define FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT (0U) #define FLASH_CMPA_SHA256_DIGEST_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_CMPA_SHA256_DIGEST_FIELD_SHIFT)) & FLASH_CMPA_SHA256_DIGEST_FIELD_MASK) @@ -7588,7 +8931,7 @@ typedef struct { /* FLASH_CMPA - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral FLASH_CMPA base address */ #define FLASH_CMPA_BASE (0x1009E400u) /** Peripheral FLASH_CMPA base address */ @@ -7698,22 +9041,31 @@ typedef struct { /*! @name HEADER - Valid Key Sore Header : 0x95959595 */ /*! @{ */ + #define FLASH_KEY_STORE_HEADER_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_HEADER_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_HEADER_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_HEADER_FIELD_SHIFT)) & FLASH_KEY_STORE_HEADER_FIELD_MASK) /*! @} */ /*! @name PUF_DISCHARGE_TIME_IN_MS - puf discharge time in ms. */ /*! @{ */ + #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_SHIFT)) & FLASH_KEY_STORE_PUF_DISCHARGE_TIME_IN_MS_FIELD_MASK) /*! @} */ /*! @name ACTIVATION_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_ACTIVATION_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_ACTIVATION_CODE_FIELD_MASK) /*! @} */ @@ -7722,8 +9074,11 @@ typedef struct { /*! @name SBKEY_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7732,28 +9087,43 @@ typedef struct { /*! @name SBKEY_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_SBKEY_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER0_FIELD_MASK) /*! @} */ /*! @name SBKEY_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_SBKEY_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_SBKEY_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_SBKEY_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_SBKEY_HEADER1_SIZE_MASK) /*! @} */ /*! @name SBKEY_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_SBKEY_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_SBKEY_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_SBKEY_BODY_FIELD_MASK) /*! @} */ @@ -7762,8 +9132,11 @@ typedef struct { /*! @name USER_KEK_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7772,28 +9145,43 @@ typedef struct { /*! @name USER_KEK_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER0_FIELD_MASK) /*! @} */ /*! @name USER_KEK_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_USER_KEK_HEADER1_SIZE_MASK) /*! @} */ /*! @name USER_KEK_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_USER_KEK_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_USER_KEK_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_USER_KEK_BODY_FIELD_MASK) /*! @} */ @@ -7802,8 +9190,11 @@ typedef struct { /*! @name UDS_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_UDS_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7812,28 +9203,43 @@ typedef struct { /*! @name UDS_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_UDS_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER0_FIELD_MASK) /*! @} */ /*! @name UDS_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_UDS_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_UDS_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_UDS_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_UDS_HEADER1_SIZE_MASK) /*! @} */ /*! @name UDS_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_UDS_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_UDS_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_UDS_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_UDS_BODY_FIELD_MASK) /*! @} */ @@ -7842,8 +9248,11 @@ typedef struct { /*! @name PRINCE_REGION0_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7852,28 +9261,43 @@ typedef struct { /*! @name PRINCE_REGION0_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER0_FIELD_MASK) /*! @} */ /*! @name PRINCE_REGION0_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_HEADER1_SIZE_MASK) /*! @} */ /*! @name PRINCE_REGION0_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION0_BODY_FIELD_MASK) /*! @} */ @@ -7882,8 +9306,11 @@ typedef struct { /*! @name PRINCE_REGION1_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7892,28 +9319,43 @@ typedef struct { /*! @name PRINCE_REGION1_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER0_FIELD_MASK) /*! @} */ /*! @name PRINCE_REGION1_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_HEADER1_SIZE_MASK) /*! @} */ /*! @name PRINCE_REGION1_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION1_BODY_FIELD_MASK) /*! @} */ @@ -7922,8 +9364,11 @@ typedef struct { /*! @name PRINCE_REGION2_KEY_CODE - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_KEY_CODE_FIELD_MASK) /*! @} */ @@ -7932,28 +9377,43 @@ typedef struct { /*! @name PRINCE_REGION2_HEADER0 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER0_FIELD_MASK) /*! @} */ /*! @name PRINCE_REGION2_HEADER1 - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK (0x3U) #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT (0U) +/*! TYPE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_TYPE_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK (0xF00U) #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT (8U) +/*! INDEX - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_INDEX_MASK) + #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK (0x3F000000U) #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT (24U) +/*! SIZE - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_HEADER1_SIZE_MASK) /*! @} */ /*! @name PRINCE_REGION2_BODY - . */ /*! @{ */ + #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK (0xFFFFFFFFU) #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT (0U) +/*! FIELD - . + */ #define FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD(x) (((uint32_t)(((uint32_t)(x)) << FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_SHIFT)) & FLASH_KEY_STORE_PRINCE_REGION2_BODY_FIELD_MASK) /*! @} */ @@ -7967,7 +9427,7 @@ typedef struct { /* FLASH_KEY_STORE - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral FLASH_KEY_STORE base address */ #define FLASH_KEY_STORE_BASE (0x1009E600u) /** Peripheral FLASH_KEY_STORE base address */ @@ -8027,6 +9487,7 @@ typedef struct { /*! @name PSELID - Peripheral Select and Flexcomm ID register. */ /*! @{ */ + #define FLEXCOMM_PSELID_PERSEL_MASK (0x7U) #define FLEXCOMM_PSELID_PERSEL_SHIFT (0U) /*! PERSEL - Peripheral Select. This field is writable by software. @@ -8040,6 +9501,7 @@ typedef struct { * 0b111..Reserved */ #define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK) + #define FLEXCOMM_PSELID_LOCK_MASK (0x8U) #define FLEXCOMM_PSELID_LOCK_SHIFT (3U) /*! LOCK - Lock the peripheral select. This field is writable by software. @@ -8047,6 +9509,7 @@ typedef struct { * 0b1..Peripheral select is locked and cannot be changed until this Flexcomm or the entire device is reset. */ #define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK) + #define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U) #define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U) /*! USARTPRESENT - USART present indicator. This field is Read-only. @@ -8054,6 +9517,7 @@ typedef struct { * 0b1..This Flexcomm includes the USART function. */ #define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK) + #define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U) #define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U) /*! SPIPRESENT - SPI present indicator. This field is Read-only. @@ -8061,6 +9525,7 @@ typedef struct { * 0b1..This Flexcomm includes the SPI function. */ #define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK) + #define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U) #define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U) /*! I2CPRESENT - I2C present indicator. This field is Read-only. @@ -8068,6 +9533,7 @@ typedef struct { * 0b1..This Flexcomm includes the I2C function. */ #define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK) + #define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U) #define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U) /*! I2SPRESENT - I 2S present indicator. This field is Read-only. @@ -8075,24 +9541,39 @@ typedef struct { * 0b1..This Flexcomm includes the I2S function. */ #define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK) + #define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U) #define FLEXCOMM_PSELID_ID_SHIFT (12U) +/*! ID - Flexcomm ID. + */ #define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK) /*! @} */ /*! @name PID - Peripheral identification register. */ /*! @{ */ -#define FLEXCOMM_PID_Aperture_MASK (0xFFU) -#define FLEXCOMM_PID_Aperture_SHIFT (0U) -#define FLEXCOMM_PID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Aperture_SHIFT)) & FLEXCOMM_PID_Aperture_MASK) -#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U) -#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U) -#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK) -#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U) -#define FLEXCOMM_PID_Major_Rev_SHIFT (12U) -#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK) + +#define FLEXCOMM_PID_APERTURE_MASK (0xFFU) +#define FLEXCOMM_PID_APERTURE_SHIFT (0U) +/*! APERTURE - size aperture for the register port on the bus (APB or AHB). + */ +#define FLEXCOMM_PID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_APERTURE_SHIFT)) & FLEXCOMM_PID_APERTURE_MASK) + +#define FLEXCOMM_PID_MINOR_REV_MASK (0xF00U) +#define FLEXCOMM_PID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ +#define FLEXCOMM_PID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MINOR_REV_SHIFT)) & FLEXCOMM_PID_MINOR_REV_MASK) + +#define FLEXCOMM_PID_MAJOR_REV_MASK (0xF000U) +#define FLEXCOMM_PID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ +#define FLEXCOMM_PID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_MAJOR_REV_SHIFT)) & FLEXCOMM_PID_MAJOR_REV_MASK) + #define FLEXCOMM_PID_ID_MASK (0xFFFF0000U) #define FLEXCOMM_PID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ #define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK) /*! @} */ @@ -8103,7 +9584,7 @@ typedef struct { /* FLEXCOMM - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral FLEXCOMM0 base address */ #define FLEXCOMM0_BASE (0x50086000u) /** Peripheral FLEXCOMM0 base address */ @@ -8263,6 +9744,7 @@ typedef struct { /*! @name CTRL - GPIO grouped interrupt control register */ /*! @{ */ + #define GINT_CTRL_INT_MASK (0x1U) #define GINT_CTRL_INT_SHIFT (0U) /*! INT - Group interrupt status. This bit is cleared by writing a one to it. Writing zero has no effect. @@ -8270,6 +9752,7 @@ typedef struct { * 0b1..Request active. Interrupt request is active. */ #define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK) + #define GINT_CTRL_COMB_MASK (0x2U) #define GINT_CTRL_COMB_SHIFT (1U) /*! COMB - Combine enabled inputs for group interrupt @@ -8277,6 +9760,7 @@ typedef struct { * 0b1..And. AND functionality: An interrupt is generated when all enabled bits are active (based on their programmed polarity). */ #define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK) + #define GINT_CTRL_TRIG_MASK (0x4U) #define GINT_CTRL_TRIG_SHIFT (2U) /*! TRIG - Group interrupt trigger @@ -8288,8 +9772,14 @@ typedef struct { /*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */ /*! @{ */ + #define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU) #define GINT_PORT_POL_POL_SHIFT (0U) +/*! POL - Configure pin polarity of port m pins for group interrupt. Bit n corresponds to pin PIOm_n + * of port m. 0 = the pin is active LOW. If the level on this pin is LOW, the pin contributes to + * the group interrupt. 1 = the pin is active HIGH. If the level on this pin is HIGH, the pin + * contributes to the group interrupt. + */ #define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK) /*! @} */ @@ -8298,8 +9788,13 @@ typedef struct { /*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */ /*! @{ */ + #define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU) #define GINT_PORT_ENA_ENA_SHIFT (0U) +/*! ENA - Enable port 0 pin for group interrupt. Bit n corresponds to pin Pm_n of port m. 0 = the + * port 0 pin is disabled and does not contribute to the grouped interrupt. 1 = the port 0 pin is + * enabled and contributes to the grouped interrupt. + */ #define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK) /*! @} */ @@ -8313,7 +9808,7 @@ typedef struct { /* GINT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral GINT0 base address */ #define GINT0_BASE (0x50002000u) /** Peripheral GINT0 base address */ @@ -8371,29 +9866,29 @@ typedef struct { /** GPIO - Register Layout Typedef */ typedef struct { - __IO uint8_t B[4][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ - uint8_t RESERVED_0[3968]; - __IO uint32_t W[4][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ - uint8_t RESERVED_1[3584]; - __IO uint32_t DIR[4]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ - uint8_t RESERVED_2[112]; - __IO uint32_t MASK[4]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ - uint8_t RESERVED_3[112]; - __IO uint32_t PIN[4]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ - uint8_t RESERVED_4[112]; - __IO uint32_t MPIN[4]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ - uint8_t RESERVED_5[112]; - __IO uint32_t SET[4]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ - uint8_t RESERVED_6[112]; - __O uint32_t CLR[4]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ - uint8_t RESERVED_7[112]; - __O uint32_t NOT[4]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ - uint8_t RESERVED_8[112]; - __O uint32_t DIRSET[4]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ - uint8_t RESERVED_9[112]; - __O uint32_t DIRCLR[4]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ - uint8_t RESERVED_10[112]; - __O uint32_t DIRNOT[4]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ + __IO uint8_t B[2][32]; /**< Byte pin registers for all port GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */ + uint8_t RESERVED_0[4032]; + __IO uint32_t W[2][32]; /**< Word pin registers for all port GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */ + uint8_t RESERVED_1[3840]; + __IO uint32_t DIR[2]; /**< Direction registers for all port GPIO pins, array offset: 0x2000, array step: 0x4 */ + uint8_t RESERVED_2[120]; + __IO uint32_t MASK[2]; /**< Mask register for all port GPIO pins, array offset: 0x2080, array step: 0x4 */ + uint8_t RESERVED_3[120]; + __IO uint32_t PIN[2]; /**< Port pin register for all port GPIO pins, array offset: 0x2100, array step: 0x4 */ + uint8_t RESERVED_4[120]; + __IO uint32_t MPIN[2]; /**< Masked port register for all port GPIO pins, array offset: 0x2180, array step: 0x4 */ + uint8_t RESERVED_5[120]; + __IO uint32_t SET[2]; /**< Write: Set register for port. Read: output bits for port, array offset: 0x2200, array step: 0x4 */ + uint8_t RESERVED_6[120]; + __O uint32_t CLR[2]; /**< Clear port for all port GPIO pins, array offset: 0x2280, array step: 0x4 */ + uint8_t RESERVED_7[120]; + __O uint32_t NOT[2]; /**< Toggle port for all port GPIO pins, array offset: 0x2300, array step: 0x4 */ + uint8_t RESERVED_8[120]; + __O uint32_t DIRSET[2]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ + uint8_t RESERVED_9[120]; + __O uint32_t DIRCLR[2]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ + uint8_t RESERVED_10[120]; + __O uint32_t DIRNOT[2]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ } GPIO_Type; /* ---------------------------------------------------------------------------- @@ -8407,129 +9902,188 @@ typedef struct { /*! @name B - Byte pin registers for all port GPIO pins */ /*! @{ */ + #define GPIO_B_PBYTE_MASK (0x1U) #define GPIO_B_PBYTE_SHIFT (0U) +/*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, + * except that pins configured as analog I/O always read as 0. One register for each port pin. + * Supported pins depends on the specific device and package. Write: loads the pin's output bit. + * One register for each port pin. Supported pins depends on the specific device and package. + */ #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) /*! @} */ /* The count of GPIO_B */ -#define GPIO_B_COUNT (4U) +#define GPIO_B_COUNT (2U) /* The count of GPIO_B */ #define GPIO_B_COUNT2 (32U) /*! @name W - Word pin registers for all port GPIO pins */ /*! @{ */ + #define GPIO_W_PWORD_MASK (0xFFFFFFFFU) #define GPIO_W_PWORD_SHIFT (0U) +/*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is + * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be + * read. Writing any value other than 0 will set the output bit. One register for each port pin. + * Supported pins depends on the specific device and package. + */ #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) /*! @} */ /* The count of GPIO_W */ -#define GPIO_W_COUNT (4U) +#define GPIO_W_COUNT (2U) /* The count of GPIO_W */ #define GPIO_W_COUNT2 (32U) /*! @name DIR - Direction registers for all port GPIO pins */ /*! @{ */ + #define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU) #define GPIO_DIR_DIRP_SHIFT (0U) +/*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = input. 1 = output. + */ #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) /*! @} */ /* The count of GPIO_DIR */ -#define GPIO_DIR_COUNT (4U) +#define GPIO_DIR_COUNT (2U) /*! @name MASK - Mask register for all port GPIO pins */ /*! @{ */ + #define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU) #define GPIO_MASK_MASKP_SHIFT (0U) +/*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = + * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = + * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit + * not affected. + */ #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) /*! @} */ /* The count of GPIO_MASK */ -#define GPIO_MASK_COUNT (4U) +#define GPIO_MASK_COUNT (2U) /*! @name PIN - Port pin register for all port GPIO pins */ /*! @{ */ + #define GPIO_PIN_PORT_MASK (0xFFFFFFFFU) #define GPIO_PIN_PORT_SHIFT (0U) +/*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported + * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. + * 1 = Read: pin is high; write: set output bit. + */ #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) /*! @} */ /* The count of GPIO_PIN */ -#define GPIO_PIN_COUNT (4U) +#define GPIO_PIN_COUNT (2U) /*! @name MPIN - Masked port register for all port GPIO pins */ /*! @{ */ + #define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU) #define GPIO_MPIN_MPORTP_SHIFT (0U) +/*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK + * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 + * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit + * if the corresponding bit in the MASK register is 0. + */ #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) /*! @} */ /* The count of GPIO_MPIN */ -#define GPIO_MPIN_COUNT (4U) +#define GPIO_MPIN_COUNT (2U) /*! @name SET - Write: Set register for port. Read: output bits for port */ /*! @{ */ + #define GPIO_SET_SETP_MASK (0xFFFFFFFFU) #define GPIO_SET_SETP_SHIFT (0U) +/*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output + * bit; write: set output bit. + */ #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) /*! @} */ /* The count of GPIO_SET */ -#define GPIO_SET_COUNT (4U) +#define GPIO_SET_COUNT (2U) /*! @name CLR - Clear port for all port GPIO pins */ /*! @{ */ + #define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU) #define GPIO_CLR_CLRP_SHIFT (0U) +/*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = No operation. 1 = Clear output bit. + */ #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) /*! @} */ /* The count of GPIO_CLR */ -#define GPIO_CLR_COUNT (4U) +#define GPIO_CLR_COUNT (2U) /*! @name NOT - Toggle port for all port GPIO pins */ /*! @{ */ + #define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU) #define GPIO_NOT_NOTP_SHIFT (0U) +/*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the + * specific device and package. 0 = no operation. 1 = Toggle output bit. + */ #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) /*! @} */ /* The count of GPIO_NOT */ -#define GPIO_NOT_COUNT (4U) +#define GPIO_NOT_COUNT (2U) /*! @name DIRSET - Set pin direction bits for port */ /*! @{ */ -#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU) + +#define GPIO_DIRSET_DIRSETP_MASK (0xFFFFFFFFU) #define GPIO_DIRSET_DIRSETP_SHIFT (0U) +/*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Set direction bit. + */ #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) /*! @} */ /* The count of GPIO_DIRSET */ -#define GPIO_DIRSET_COUNT (4U) +#define GPIO_DIRSET_COUNT (2U) /*! @name DIRCLR - Clear pin direction bits for port */ /*! @{ */ -#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU) + +#define GPIO_DIRCLR_DIRCLRP_MASK (0xFFFFFFFFU) #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) +/*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on + * the specific device and package. 0 = No operation. 1 = Clear direction bit. + */ #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) /*! @} */ /* The count of GPIO_DIRCLR */ -#define GPIO_DIRCLR_COUNT (4U) +#define GPIO_DIRCLR_COUNT (2U) /*! @name DIRNOT - Toggle pin direction bits for port */ /*! @{ */ -#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU) + +#define GPIO_DIRNOT_DIRNOTP_MASK (0xFFFFFFFFU) #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) +/*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends + * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + */ #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) /*! @} */ /* The count of GPIO_DIRNOT */ -#define GPIO_DIRNOT_COUNT (4U) +#define GPIO_DIRNOT_COUNT (2U) /*! @@ -8538,7 +10092,7 @@ typedef struct { /* GPIO - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral GPIO base address */ #define GPIO_BASE (0x5008C000u) /** Peripheral GPIO base address */ @@ -8594,7 +10148,7 @@ typedef struct { /** HASHCRYPT - Register Layout Typedef */ typedef struct { - __IO uint32_t CTRL; /**< Is control register to enable and operate Hash and Crypto, offset: 0x0 */ + __IO uint32_t CTRL; /**< Control register to enable and operate Hash and Crypto, offset: 0x0 */ __IO uint32_t STATUS; /**< Indicates status of Hash peripheral., offset: 0x4 */ __IO uint32_t INTENSET; /**< Write 1 to enable interrupts; reads back with which are set., offset: 0x8 */ __IO uint32_t INTENCLR; /**< Write 1 to clear interrupts., offset: 0xC */ @@ -8603,11 +10157,11 @@ typedef struct { uint8_t RESERVED_0[8]; __O uint32_t INDATA; /**< Input of 16 words at a time to load up buffer., offset: 0x20 */ __O uint32_t ALIAS[7]; /**< , array offset: 0x24, array step: 0x4 */ - __I uint32_t OUTDATA0[8]; /**< , array offset: 0x40, array step: 0x4 */ - __I uint32_t OUTDATA1[8]; /**< , array offset: 0x60, array step: 0x4 */ + __I uint32_t DIGEST0[8]; /**< , array offset: 0x40, array step: 0x4 */ + uint8_t RESERVED_1[32]; __IO uint32_t CRYPTCFG; /**< Crypto settings for AES and Salsa and ChaCha, offset: 0x80 */ __I uint32_t CONFIG; /**< Returns the configuration of this block in this chip - indicates what services are available., offset: 0x84 */ - uint8_t RESERVED_1[4]; + uint8_t RESERVED_2[4]; __IO uint32_t LOCK; /**< Lock register allows locking to the current security level or unlocking by the lock holding level., offset: 0x8C */ __O uint32_t MASK[4]; /**< , array offset: 0x90, array step: 0x4 */ } HASHCRYPT_Type; @@ -8621,8 +10175,9 @@ typedef struct { * @{ */ -/*! @name CTRL - Is control register to enable and operate Hash and Crypto */ +/*! @name CTRL - Control register to enable and operate Hash and Crypto */ /*! @{ */ + #define HASHCRYPT_CTRL_MODE_MASK (0x7U) #define HASHCRYPT_CTRL_MODE_SHIFT (0U) /*! Mode - The operational mode to use, or 0 if none. Note that the CONFIG register will indicate if @@ -8630,13 +10185,11 @@ typedef struct { * 0b000..Disabled * 0b001..SHA1 is enabled * 0b010..SHA2-256 is enabled - * 0b011..SHA2-512 is enabled (if available) * 0b100..AES if available (see also CRYPTCFG register for more controls) * 0b101..ICB-AES if available (see also CRYPTCFG register for more controls) - * 0b110..Salsa20/20 if available (including XSalsa - see also CRYPTCFG register) - * 0b111..ChaCha20 if available (see also CRYPTCFG register for more controls) */ #define HASHCRYPT_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_MODE_SHIFT)) & HASHCRYPT_CTRL_MODE_MASK) + #define HASHCRYPT_CTRL_NEW_HASH_MASK (0x10U) #define HASHCRYPT_CTRL_NEW_HASH_SHIFT (4U) /*! New_Hash - Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING @@ -8644,6 +10197,7 @@ typedef struct { * 0b1..Starts a new Hash/Crypto and initializes the Digest/Result. */ #define HASHCRYPT_CTRL_NEW_HASH(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_NEW_HASH_SHIFT)) & HASHCRYPT_CTRL_NEW_HASH_MASK) + #define HASHCRYPT_CTRL_DMA_I_MASK (0x100U) #define HASHCRYPT_CTRL_DMA_I_SHIFT (8U) /*! DMA_I - Written with 1 to use DMA to fill INDATA. If Hash, will request from DMA for 16 words @@ -8656,6 +10210,7 @@ typedef struct { * 0b1..DMA will push in the data. */ #define HASHCRYPT_CTRL_DMA_I(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_I_SHIFT)) & HASHCRYPT_CTRL_DMA_I_MASK) + #define HASHCRYPT_CTRL_DMA_O_MASK (0x200U) #define HASHCRYPT_CTRL_DMA_O_SHIFT (9U) /*! DMA_O - Written to 1 to use DMA to drain the digest/output. If both DMA_I and DMA_O are set, the @@ -8663,13 +10218,19 @@ typedef struct { * 0b0..DMA is not used. Processor reads the digest/output in response to DIGEST interrupt. */ #define HASHCRYPT_CTRL_DMA_O(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_DMA_O_SHIFT)) & HASHCRYPT_CTRL_DMA_O_MASK) + #define HASHCRYPT_CTRL_HASHSWPB_MASK (0x1000U) #define HASHCRYPT_CTRL_HASHSWPB_SHIFT (12U) +/*! HASHSWPB - If 1, will swap bytes in the word for SHA hashing. The default is byte order (so LSB + * is 1st byte) but this allows swapping to MSB is 1st such as is shown in SHS spec. For + * cryptographic swapping, see the CRYPTCFG register. + */ #define HASHCRYPT_CTRL_HASHSWPB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CTRL_HASHSWPB_SHIFT)) & HASHCRYPT_CTRL_HASHSWPB_MASK) /*! @} */ /*! @name STATUS - Indicates status of Hash peripheral. */ /*! @{ */ + #define HASHCRYPT_STATUS_WAITING_MASK (0x1U) #define HASHCRYPT_STATUS_WAITING_SHIFT (0U) /*! WAITING - If 1, the block is waiting for more data to process. @@ -8678,17 +10239,19 @@ typedef struct { * 0b1..Waiting for data to be written in (16 words) */ #define HASHCRYPT_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_WAITING_SHIFT)) & HASHCRYPT_STATUS_WAITING_MASK) -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK (0x2U) -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT (1U) -/*! DIGEST_aka_OUTDATA - For Hash, if 1 then a DIGEST is ready and waiting and there is no active - * next block already started. For Cryptographic uses, this will be set for each block processed, - * indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is - * cleared when any data is written, when New is written, for Cryptographic uses when the last - * word is read out, or when the block is disabled. + +#define HASHCRYPT_STATUS_DIGEST_MASK (0x2U) +#define HASHCRYPT_STATUS_DIGEST_SHIFT (1U) +/*! DIGEST - For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block + * already started. For Cryptographic uses, this will be set for each block processed, indicating + * OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared + * when any data is written, when New is written, for Cryptographic uses when the last word is read + * out, or when the block is disabled. * 0b0..No Digest is ready * 0b1..Digest is ready. Application may read it or may write more data */ -#define HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_SHIFT)) & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK) +#define HASHCRYPT_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_DIGEST_SHIFT)) & HASHCRYPT_STATUS_DIGEST_MASK) + #define HASHCRYPT_STATUS_ERROR_MASK (0x4U) #define HASHCRYPT_STATUS_ERROR_SHIFT (2U) /*! ERROR - If 1, an error occurred. For normal uses, this is due to an attempted overrun: INDATA @@ -8698,6 +10261,7 @@ typedef struct { * 0b1..An error occurred since last cleared (written 1 to clear). */ #define HASHCRYPT_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ERROR_SHIFT)) & HASHCRYPT_STATUS_ERROR_MASK) + #define HASHCRYPT_STATUS_NEEDKEY_MASK (0x10U) #define HASHCRYPT_STATUS_NEEDKEY_SHIFT (4U) /*! NEEDKEY - Indicates the block wants the key to be written in (set along with WAITING) @@ -8705,6 +10269,7 @@ typedef struct { * 0b1..Key is needed and INDATA/ALIAS will be accepted as Key. Will also set WAITING. */ #define HASHCRYPT_STATUS_NEEDKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDKEY_SHIFT)) & HASHCRYPT_STATUS_NEEDKEY_MASK) + #define HASHCRYPT_STATUS_NEEDIV_MASK (0x20U) #define HASHCRYPT_STATUS_NEEDIV_SHIFT (5U) /*! NEEDIV - Indicates the block wants an IV/NONE to be written in (set along with WAITING) @@ -8712,13 +10277,19 @@ typedef struct { * 0b1..IV/Nonce is needed and INDATA/ALIAS will be accepted as IV/Nonce. Will also set WAITING. */ #define HASHCRYPT_STATUS_NEEDIV(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_NEEDIV_SHIFT)) & HASHCRYPT_STATUS_NEEDIV_MASK) + #define HASHCRYPT_STATUS_ICBIDX_MASK (0x3F0000U) #define HASHCRYPT_STATUS_ICBIDX_SHIFT (16U) +/*! ICBIDX - If ICB-AES is selected, then reads as the ICB index count based on ICBSTRM (from + * CRYPTCFG). That is, if 3 bits of ICBSTRM, then this will count from 0 to 7 and then back to 0. On 0, + * it has to compute the full ICB, quicker when not 0. + */ #define HASHCRYPT_STATUS_ICBIDX(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_STATUS_ICBIDX_SHIFT)) & HASHCRYPT_STATUS_ICBIDX_MASK) /*! @} */ /*! @name INTENSET - Write 1 to enable interrupts; reads back with which are set. */ /*! @{ */ + #define HASHCRYPT_INTENSET_WAITING_MASK (0x1U) #define HASHCRYPT_INTENSET_WAITING_SHIFT (0U) /*! WAITING - Indicates if should interrupt when waiting for data input. @@ -8726,6 +10297,7 @@ typedef struct { * 0b1..Will interrupt when waiting */ #define HASHCRYPT_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_WAITING_SHIFT)) & HASHCRYPT_INTENSET_WAITING_MASK) + #define HASHCRYPT_INTENSET_DIGEST_MASK (0x2U) #define HASHCRYPT_INTENSET_DIGEST_SHIFT (1U) /*! DIGEST - Indicates if should interrupt when Digest (or Outdata) is ready (completed a hash/crypto or completed a full sequence). @@ -8733,6 +10305,7 @@ typedef struct { * 0b1..Will interrupt when Digest is ready. Interrupt cleared by writing more data, starting a new Hash, or disabling (done). */ #define HASHCRYPT_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENSET_DIGEST_SHIFT)) & HASHCRYPT_INTENSET_DIGEST_MASK) + #define HASHCRYPT_INTENSET_ERROR_MASK (0x4U) #define HASHCRYPT_INTENSET_ERROR_SHIFT (2U) /*! ERROR - Indicates if should interrupt on an ERROR (as defined in Status) @@ -8744,89 +10317,133 @@ typedef struct { /*! @name INTENCLR - Write 1 to clear interrupts. */ /*! @{ */ + #define HASHCRYPT_INTENCLR_WAITING_MASK (0x1U) #define HASHCRYPT_INTENCLR_WAITING_SHIFT (0U) +/*! WAITING - Write 1 to clear mask. + */ #define HASHCRYPT_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_WAITING_SHIFT)) & HASHCRYPT_INTENCLR_WAITING_MASK) + #define HASHCRYPT_INTENCLR_DIGEST_MASK (0x2U) #define HASHCRYPT_INTENCLR_DIGEST_SHIFT (1U) +/*! DIGEST - Write 1 to clear mask. + */ #define HASHCRYPT_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_DIGEST_SHIFT)) & HASHCRYPT_INTENCLR_DIGEST_MASK) + #define HASHCRYPT_INTENCLR_ERROR_MASK (0x4U) #define HASHCRYPT_INTENCLR_ERROR_SHIFT (2U) +/*! ERROR - Write 1 to clear mask. + */ #define HASHCRYPT_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INTENCLR_ERROR_SHIFT)) & HASHCRYPT_INTENCLR_ERROR_MASK) /*! @} */ /*! @name MEMCTRL - Setup Master to access memory (if available) */ /*! @{ */ + #define HASHCRYPT_MEMCTRL_MASTER_MASK (0x1U) #define HASHCRYPT_MEMCTRL_MASTER_SHIFT (0U) -/*! MASTER +/*! MASTER - Enables mastering. * 0b0..Mastering is not used and the normal DMA or Interrupt based model is used with INDATA. * 0b1..Mastering is enabled and DMA and INDATA should not be used. */ #define HASHCRYPT_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_MASTER_SHIFT)) & HASHCRYPT_MEMCTRL_MASTER_MASK) + #define HASHCRYPT_MEMCTRL_COUNT_MASK (0x7FF0000U) #define HASHCRYPT_MEMCTRL_COUNT_SHIFT (16U) +/*! COUNT - Number of 512-bit (128-bit if AES, except 1st block which may include key and IV) blocks + * to copy starting at MEMADDR. This register will decrement after each block is copied, ending + * in 0. For Hash, the DIGEST interrupt will occur when it reaches 0. Fro AES, the DIGEST/OUTDATA + * interrupt will occur on ever block. If a bus error occurs, it will stop with this field set + * to the block that failed. 0:Done - nothing to process. 1 to 2K: Number of 512-bit (or 128bit) + * blocks to hash. + */ #define HASHCRYPT_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMCTRL_COUNT_SHIFT)) & HASHCRYPT_MEMCTRL_COUNT_MASK) /*! @} */ /*! @name MEMADDR - Address to start memory access from (if available). */ /*! @{ */ + #define HASHCRYPT_MEMADDR_BASE_MASK (0xFFFFFFFFU) #define HASHCRYPT_MEMADDR_BASE_SHIFT (0U) +/*! BASE - Address base to start copying from, word aligned (so bits 1:0 must be 0). This field will + * advance as it processes the words. If it fails with a bus error, the register will contain + * the failing word. N:Address in Flash or RAM space; RAM only as mapped in this part. May also be + * able to address SPIFI. + */ #define HASHCRYPT_MEMADDR_BASE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MEMADDR_BASE_SHIFT)) & HASHCRYPT_MEMADDR_BASE_MASK) /*! @} */ /*! @name INDATA - Input of 16 words at a time to load up buffer. */ /*! @{ */ + #define HASHCRYPT_INDATA_DATA_MASK (0xFFFFFFFFU) #define HASHCRYPT_INDATA_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ #define HASHCRYPT_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_INDATA_DATA_SHIFT)) & HASHCRYPT_INDATA_DATA_MASK) /*! @} */ /*! @name ALIAS - */ /*! @{ */ + #define HASHCRYPT_ALIAS_DATA_MASK (0xFFFFFFFFU) #define HASHCRYPT_ALIAS_DATA_SHIFT (0U) +/*! DATA - Write next word in little-endian form. The hash requires big endian word data, but this + * block swaps the bytes automatically. That is, SHA assumes the data coming in is treated as + * bytes (e.g. "abcd") and since the ARM core will treat "abcd" as a word as 0x64636261, the block + * will swap the word to restore into big endian. + */ #define HASHCRYPT_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_ALIAS_DATA_SHIFT)) & HASHCRYPT_ALIAS_DATA_MASK) /*! @} */ /* The count of HASHCRYPT_ALIAS */ #define HASHCRYPT_ALIAS_COUNT (7U) -/*! @name OUTDATA0 - */ +/*! @name DIGEST0 - */ /*! @{ */ -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK (0xFFFFFFFFU) -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT (0U) -#define HASHCRYPT_OUTDATA0_DIGEST_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA0_DIGEST_OUTPUT_MASK) + +#define HASHCRYPT_DIGEST0_DIGEST_MASK (0xFFFFFFFFU) +#define HASHCRYPT_DIGEST0_DIGEST_SHIFT (0U) +/*! DIGEST - One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. + */ +#define HASHCRYPT_DIGEST0_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_DIGEST0_DIGEST_SHIFT)) & HASHCRYPT_DIGEST0_DIGEST_MASK) /*! @} */ -/* The count of HASHCRYPT_OUTDATA0 */ -#define HASHCRYPT_OUTDATA0_COUNT (8U) - -/*! @name OUTDATA1 - */ -/*! @{ */ -#define HASHCRYPT_OUTDATA1_OUTPUT_MASK (0xFFFFFFFFU) -#define HASHCRYPT_OUTDATA1_OUTPUT_SHIFT (0U) -#define HASHCRYPT_OUTDATA1_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_OUTDATA1_OUTPUT_SHIFT)) & HASHCRYPT_OUTDATA1_OUTPUT_MASK) -/*! @} */ - -/* The count of HASHCRYPT_OUTDATA1 */ -#define HASHCRYPT_OUTDATA1_COUNT (8U) +/* The count of HASHCRYPT_DIGEST0 */ +#define HASHCRYPT_DIGEST0_COUNT (8U) /*! @name CRYPTCFG - Crypto settings for AES and Salsa and ChaCha */ /*! @{ */ + #define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK (0x1U) #define HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT (0U) +/*! MSW1ST_OUT - If 1, OUTDATA0 will be read Most significant word 1st for AES. Else it will be read + * in normal little endian - Least significant word 1st. Note: only if allowed by configuration. + */ #define HASHCRYPT_CRYPTCFG_MSW1ST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_OUT_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_OUT_MASK) + #define HASHCRYPT_CRYPTCFG_SWAPKEY_MASK (0x2U) #define HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT (1U) +/*! SWAPKEY - If 1, will Swap the key input (bytes in each word). + */ #define HASHCRYPT_CRYPTCFG_SWAPKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPKEY_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPKEY_MASK) + #define HASHCRYPT_CRYPTCFG_SWAPDAT_MASK (0x4U) #define HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT (2U) +/*! SWAPDAT - If 1, will SWAP the data and IV inputs (bytes in each word). + */ #define HASHCRYPT_CRYPTCFG_SWAPDAT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_SWAPDAT_SHIFT)) & HASHCRYPT_CRYPTCFG_SWAPDAT_MASK) + #define HASHCRYPT_CRYPTCFG_MSW1ST_MASK (0x8U) #define HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT (3U) +/*! MSW1ST - If 1, load of key, IV, and data is MSW 1st for AES. Else, the words are little endian. + * Note: only if allowed by configuration. + */ #define HASHCRYPT_CRYPTCFG_MSW1ST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_MSW1ST_SHIFT)) & HASHCRYPT_CRYPTCFG_MSW1ST_MASK) + #define HASHCRYPT_CRYPTCFG_AESMODE_MASK (0x30U) #define HASHCRYPT_CRYPTCFG_AESMODE_SHIFT (4U) /*! AESMODE - AES Cipher mode to use if plain AES @@ -8836,6 +10453,7 @@ typedef struct { * 0b11..reserved */ #define HASHCRYPT_CRYPTCFG_AESMODE(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESMODE_SHIFT)) & HASHCRYPT_CRYPTCFG_AESMODE_MASK) + #define HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK (0x40U) #define HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT (6U) /*! AESDECRYPT - AES ECB direction. Only encryption used if CTR mode or manual modes such as CFB @@ -8843,6 +10461,7 @@ typedef struct { * 0b1..Decrypt */ #define HASHCRYPT_CRYPTCFG_AESDECRYPT(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESDECRYPT_SHIFT)) & HASHCRYPT_CRYPTCFG_AESDECRYPT_MASK) + #define HASHCRYPT_CRYPTCFG_AESSECRET_MASK (0x80U) #define HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT (7U) /*! AESSECRET - Selects the Hidden Secret key vs. User key, if provided. If security levels are @@ -8851,6 +10470,7 @@ typedef struct { * 0b1..Secret key provided in hidden way by HW */ #define HASHCRYPT_CRYPTCFG_AESSECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESSECRET_SHIFT)) & HASHCRYPT_CRYPTCFG_AESSECRET_MASK) + #define HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK (0x300U) #define HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT (8U) /*! AESKEYSZ - Sets the AES key size @@ -8860,15 +10480,22 @@ typedef struct { * 0b11..reserved */ #define HASHCRYPT_CRYPTCFG_AESKEYSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESKEYSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_AESKEYSZ_MASK) + #define HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK (0x1C00U) #define HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT (10U) +/*! AESCTRPOS - Halfword position of 16b counter in IV if AESMODE is CTR (position is fixed for + * Salsa and ChaCha). Only supports 16b counter, so application must control any additional bytes if + * using more. The 16-bit counter is read from the IV and incremented by 1 each time. Any other + * use CTR should use ECB directly and do its own XOR and so on. + */ #define HASHCRYPT_CRYPTCFG_AESCTRPOS(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_AESCTRPOS_SHIFT)) & HASHCRYPT_CRYPTCFG_AESCTRPOS_MASK) + #define HASHCRYPT_CRYPTCFG_STREAMLAST_MASK (0x10000U) #define HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT (16U) +/*! STREAMLAST - Is 1 if last stream block. If not 1, then the engine will compute the next "hash". + */ #define HASHCRYPT_CRYPTCFG_STREAMLAST(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_STREAMLAST_SHIFT)) & HASHCRYPT_CRYPTCFG_STREAMLAST_MASK) -#define HASHCRYPT_CRYPTCFG_XSALSA_MASK (0x20000U) -#define HASHCRYPT_CRYPTCFG_XSALSA_SHIFT (17U) -#define HASHCRYPT_CRYPTCFG_XSALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_XSALSA_SHIFT)) & HASHCRYPT_CRYPTCFG_XSALSA_MASK) + #define HASHCRYPT_CRYPTCFG_ICBSZ_MASK (0x300000U) #define HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT (20U) /*! ICBSZ - This sets the ICB size between 32 and 128 bits, using the following rules. Note that the @@ -8879,6 +10506,7 @@ typedef struct { * 0b11..All 128 bits of the IV/ctr are used */ #define HASHCRYPT_CRYPTCFG_ICBSZ(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CRYPTCFG_ICBSZ_SHIFT)) & HASHCRYPT_CRYPTCFG_ICBSZ_MASK) + #define HASHCRYPT_CRYPTCFG_ICBSTRM_MASK (0xC00000U) #define HASHCRYPT_CRYPTCFG_ICBSTRM_SHIFT (22U) /*! ICBSTRM - The size of the ICB-AES stream that can be pushed before needing to compute a new @@ -8893,40 +10521,53 @@ typedef struct { /*! @name CONFIG - Returns the configuration of this block in this chip - indicates what services are available. */ /*! @{ */ + #define HASHCRYPT_CONFIG_DUAL_MASK (0x1U) #define HASHCRYPT_CONFIG_DUAL_SHIFT (0U) +/*! DUAL - 1 if 2 x 512 bit buffers, 0 if only 1 x 512 bit + */ #define HASHCRYPT_CONFIG_DUAL(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DUAL_SHIFT)) & HASHCRYPT_CONFIG_DUAL_MASK) + #define HASHCRYPT_CONFIG_DMA_MASK (0x2U) #define HASHCRYPT_CONFIG_DMA_SHIFT (1U) +/*! DMA - 1 if DMA is connected + */ #define HASHCRYPT_CONFIG_DMA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_DMA_SHIFT)) & HASHCRYPT_CONFIG_DMA_MASK) + #define HASHCRYPT_CONFIG_AHB_MASK (0x8U) #define HASHCRYPT_CONFIG_AHB_SHIFT (3U) +/*! AHB - 1 if AHB Master is enabled + */ #define HASHCRYPT_CONFIG_AHB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AHB_SHIFT)) & HASHCRYPT_CONFIG_AHB_MASK) -#define HASHCRYPT_CONFIG_SHA512_MASK (0x20U) -#define HASHCRYPT_CONFIG_SHA512_SHIFT (5U) -#define HASHCRYPT_CONFIG_SHA512(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SHA512_SHIFT)) & HASHCRYPT_CONFIG_SHA512_MASK) + #define HASHCRYPT_CONFIG_AES_MASK (0x40U) #define HASHCRYPT_CONFIG_AES_SHIFT (6U) +/*! AES - 1 if AES 128 included + */ #define HASHCRYPT_CONFIG_AES(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AES_SHIFT)) & HASHCRYPT_CONFIG_AES_MASK) + #define HASHCRYPT_CONFIG_AESKEY_MASK (0x80U) #define HASHCRYPT_CONFIG_AESKEY_SHIFT (7U) +/*! AESKEY - 1 if AES 192 and 256 also included + */ #define HASHCRYPT_CONFIG_AESKEY(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_AESKEY_SHIFT)) & HASHCRYPT_CONFIG_AESKEY_MASK) + #define HASHCRYPT_CONFIG_SECRET_MASK (0x100U) #define HASHCRYPT_CONFIG_SECRET_SHIFT (8U) +/*! SECRET - 1 if AES Secret key available + */ #define HASHCRYPT_CONFIG_SECRET(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SECRET_SHIFT)) & HASHCRYPT_CONFIG_SECRET_MASK) -#define HASHCRYPT_CONFIG_SALSA_MASK (0x200U) -#define HASHCRYPT_CONFIG_SALSA_SHIFT (9U) -#define HASHCRYPT_CONFIG_SALSA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_SALSA_SHIFT)) & HASHCRYPT_CONFIG_SALSA_MASK) -#define HASHCRYPT_CONFIG_CHACHA_MASK (0x400U) -#define HASHCRYPT_CONFIG_CHACHA_SHIFT (10U) -#define HASHCRYPT_CONFIG_CHACHA(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_CHACHA_SHIFT)) & HASHCRYPT_CONFIG_CHACHA_MASK) + #define HASHCRYPT_CONFIG_ICB_MASK (0x800U) #define HASHCRYPT_CONFIG_ICB_SHIFT (11U) +/*! ICB - 1 if ICB over AES included + */ #define HASHCRYPT_CONFIG_ICB(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_CONFIG_ICB_SHIFT)) & HASHCRYPT_CONFIG_ICB_MASK) /*! @} */ /*! @name LOCK - Lock register allows locking to the current security level or unlocking by the lock holding level. */ /*! @{ */ + #define HASHCRYPT_LOCK_SECLOCK_MASK (0x3U) #define HASHCRYPT_LOCK_SECLOCK_SHIFT (0U) /*! SECLOCK - Write 1 to secure-lock this block (if running in a security state). Write 0 to unlock. @@ -8937,15 +10578,21 @@ typedef struct { * 0b01..Locks to the current security level. AHB Master will issue requests at this level. */ #define HASHCRYPT_LOCK_SECLOCK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_SECLOCK_SHIFT)) & HASHCRYPT_LOCK_SECLOCK_MASK) + #define HASHCRYPT_LOCK_PATTERN_MASK (0xFFF0U) #define HASHCRYPT_LOCK_PATTERN_SHIFT (4U) +/*! PATTERN - Must write 0xA75 to change lock state. A75:Pattern needed to change bits 1:0 + */ #define HASHCRYPT_LOCK_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_LOCK_PATTERN_SHIFT)) & HASHCRYPT_LOCK_PATTERN_MASK) /*! @} */ /*! @name MASK - */ /*! @{ */ + #define HASHCRYPT_MASK_MASK_MASK (0xFFFFFFFFU) #define HASHCRYPT_MASK_MASK_SHIFT (0U) +/*! MASK - A random word. + */ #define HASHCRYPT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << HASHCRYPT_MASK_MASK_SHIFT)) & HASHCRYPT_MASK_MASK_MASK) /*! @} */ @@ -8959,7 +10606,7 @@ typedef struct { /* HASHCRYPT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral HASHCRYPT base address */ #define HASHCRYPT_BASE (0x500A4000u) /** Peripheral HASHCRYPT base address */ @@ -9037,6 +10684,7 @@ typedef struct { /*! @name CFG - Configuration for shared functions. */ /*! @{ */ + #define I2C_CFG_MSTEN_MASK (0x1U) #define I2C_CFG_MSTEN_SHIFT (0U) /*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not @@ -9045,6 +10693,7 @@ typedef struct { * 0b1..Enabled. The I2C Master function is enabled. */ #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) + #define I2C_CFG_SLVEN_MASK (0x2U) #define I2C_CFG_SLVEN_SHIFT (1U) /*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not @@ -9053,6 +10702,7 @@ typedef struct { * 0b1..Enabled. The I2C slave function is enabled. */ #define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) + #define I2C_CFG_MONEN_MASK (0x4U) #define I2C_CFG_MONEN_SHIFT (2U) /*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not @@ -9061,6 +10711,7 @@ typedef struct { * 0b1..Enabled. The I2C Monitor function is enabled. */ #define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) + #define I2C_CFG_TIMEOUTEN_MASK (0x8U) #define I2C_CFG_TIMEOUTEN_SHIFT (3U) /*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. @@ -9069,6 +10720,7 @@ typedef struct { * interrupts if they are enabled. Typically, only one time-out will be used in a system. */ #define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) + #define I2C_CFG_MONCLKSTR_MASK (0x10U) #define I2C_CFG_MONCLKSTR_SHIFT (4U) /*! MONCLKSTR - Monitor function Clock Stretching. @@ -9079,6 +10731,7 @@ typedef struct { * read all incoming data supplied by the Monitor function. */ #define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) + #define I2C_CFG_HSCAPABLE_MASK (0x20U) #define I2C_CFG_HSCAPABLE_SHIFT (5U) /*! HSCAPABLE - High-speed mode Capable enable. Since High Speed mode alters the way I2C pins drive @@ -9097,6 +10750,7 @@ typedef struct { /*! @name STAT - Status register for Master, Slave, and Monitor functions. */ /*! @{ */ + #define I2C_STAT_MSTPENDING_MASK (0x1U) #define I2C_STAT_MSTPENDING_SHIFT (0U) /*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on @@ -9110,6 +10764,7 @@ typedef struct { * idle state, it is waiting to receive or transmit data or the NACK bit. */ #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) + #define I2C_STAT_MSTSTATE_MASK (0xEU) #define I2C_STAT_MSTSTATE_SHIFT (1U) /*! MSTSTATE - Master State code. The master state code reflects the master state when the @@ -9123,6 +10778,7 @@ typedef struct { * 0b100..NACK Data. Slave NACKed transmitted data. */ #define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) + #define I2C_STAT_MSTARBLOSS_MASK (0x10U) #define I2C_STAT_MSTARBLOSS_SHIFT (4U) /*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to @@ -9133,6 +10789,7 @@ typedef struct { * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. */ #define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) + #define I2C_STAT_MSTSTSTPERR_MASK (0x40U) #define I2C_STAT_MSTSTSTPERR_SHIFT (6U) /*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to @@ -9144,6 +10801,7 @@ typedef struct { * that the bus has not stalled. */ #define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) + #define I2C_STAT_SLVPENDING_MASK (0x100U) #define I2C_STAT_SLVPENDING_SHIFT (8U) /*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue @@ -9160,6 +10818,7 @@ typedef struct { * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. */ #define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) + #define I2C_STAT_SLVSTATE_MASK (0x600U) #define I2C_STAT_SLVSTATE_SHIFT (9U) /*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for @@ -9171,6 +10830,7 @@ typedef struct { * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). */ #define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) + #define I2C_STAT_SLVNOTSTR_MASK (0x800U) #define I2C_STAT_SLVNOTSTR_SHIFT (11U) /*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. @@ -9181,6 +10841,7 @@ typedef struct { * Power-down mode could be entered at this time. */ #define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) + #define I2C_STAT_SLVIDX_MASK (0x3000U) #define I2C_STAT_SLVIDX_SHIFT (12U) /*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been @@ -9193,6 +10854,7 @@ typedef struct { * 0b11..Address 3. Slave address 3 was matched. */ #define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) + #define I2C_STAT_SLVSEL_MASK (0x4000U) #define I2C_STAT_SLVSEL_SHIFT (14U) /*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave @@ -9205,6 +10867,7 @@ typedef struct { * 0b1..Selected. The Slave function is currently selected. */ #define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) + #define I2C_STAT_SLVDESEL_MASK (0x8000U) #define I2C_STAT_SLVDESEL_SHIFT (15U) /*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via @@ -9215,6 +10878,7 @@ typedef struct { * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. */ #define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) + #define I2C_STAT_MONRDY_MASK (0x10000U) #define I2C_STAT_MONRDY_SHIFT (16U) /*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. @@ -9222,6 +10886,7 @@ typedef struct { * 0b1..Data waiting. The Monitor function has data waiting to be read. */ #define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) + #define I2C_STAT_MONOV_MASK (0x20000U) #define I2C_STAT_MONOV_SHIFT (17U) /*! MONOV - Monitor Overflow flag. @@ -9230,6 +10895,7 @@ typedef struct { * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. */ #define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) + #define I2C_STAT_MONACTIVE_MASK (0x40000U) #define I2C_STAT_MONACTIVE_SHIFT (18U) /*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to @@ -9239,6 +10905,7 @@ typedef struct { * 0b1..Active. The Monitor function considers the I2C bus to be active. */ #define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) + #define I2C_STAT_MONIDLE_MASK (0x80000U) #define I2C_STAT_MONIDLE_SHIFT (19U) /*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change @@ -9249,6 +10916,7 @@ typedef struct { * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. */ #define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) + #define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) #define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) /*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been @@ -9259,6 +10927,7 @@ typedef struct { * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. */ #define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) + #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) #define I2C_STAT_SCLTIMEOUT_SHIFT (25U) /*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the @@ -9271,6 +10940,7 @@ typedef struct { /*! @name INTENSET - Interrupt Enable Set and read register. */ /*! @{ */ + #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) /*! MSTPENDINGEN - Master Pending interrupt Enable. @@ -9278,6 +10948,7 @@ typedef struct { * 0b1..Enabled. The MstPending interrupt is enabled. */ #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) + #define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) #define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) /*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. @@ -9285,6 +10956,7 @@ typedef struct { * 0b1..Enabled. The MstArbLoss interrupt is enabled. */ #define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) + #define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) #define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) /*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. @@ -9292,6 +10964,7 @@ typedef struct { * 0b1..Enabled. The MstStStpErr interrupt is enabled. */ #define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) + #define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) #define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) /*! SLVPENDINGEN - Slave Pending interrupt Enable. @@ -9299,6 +10972,7 @@ typedef struct { * 0b1..Enabled. The SlvPending interrupt is enabled. */ #define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) + #define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) #define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) /*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. @@ -9306,6 +10980,7 @@ typedef struct { * 0b1..Enabled. The SlvNotStr interrupt is enabled. */ #define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) + #define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) #define I2C_INTENSET_SLVDESELEN_SHIFT (15U) /*! SLVDESELEN - Slave Deselect interrupt Enable. @@ -9313,6 +10988,7 @@ typedef struct { * 0b1..Enabled. The SlvDeSel interrupt is enabled. */ #define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) + #define I2C_INTENSET_MONRDYEN_MASK (0x10000U) #define I2C_INTENSET_MONRDYEN_SHIFT (16U) /*! MONRDYEN - Monitor data Ready interrupt Enable. @@ -9320,6 +10996,7 @@ typedef struct { * 0b1..Enabled. The MonRdy interrupt is enabled. */ #define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) + #define I2C_INTENSET_MONOVEN_MASK (0x20000U) #define I2C_INTENSET_MONOVEN_SHIFT (17U) /*! MONOVEN - Monitor Overrun interrupt Enable. @@ -9327,6 +11004,7 @@ typedef struct { * 0b1..Enabled. The MonOv interrupt is enabled. */ #define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) + #define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) #define I2C_INTENSET_MONIDLEEN_SHIFT (19U) /*! MONIDLEEN - Monitor Idle interrupt Enable. @@ -9334,6 +11012,7 @@ typedef struct { * 0b1..Enabled. The MonIdle interrupt is enabled. */ #define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) + #define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) /*! EVENTTIMEOUTEN - Event time-out interrupt Enable. @@ -9341,6 +11020,7 @@ typedef struct { * 0b1..Enabled. The Event time-out interrupt is enabled. */ #define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) + #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) /*! SCLTIMEOUTEN - SCL time-out interrupt Enable. @@ -9352,97 +11032,183 @@ typedef struct { /*! @name INTENCLR - Interrupt Enable Clear register. */ /*! @{ */ + #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) +/*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding + * bit in the INTENSET register if implemented. + */ #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) + #define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) +/*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. + */ #define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) + #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) +/*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. + */ #define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) + #define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) +/*! SLVPENDINGCLR - Slave Pending interrupt clear. + */ #define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) + #define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) +/*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. + */ #define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) + #define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) #define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) +/*! SLVDESELCLR - Slave Deselect interrupt clear. + */ #define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) + #define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) #define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) +/*! MONRDYCLR - Monitor data Ready interrupt clear. + */ #define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) + #define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) #define I2C_INTENCLR_MONOVCLR_SHIFT (17U) +/*! MONOVCLR - Monitor Overrun interrupt clear. + */ #define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) + #define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) #define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) +/*! MONIDLECLR - Monitor Idle interrupt clear. + */ #define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) + #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) +/*! EVENTTIMEOUTCLR - Event time-out interrupt clear. + */ #define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) + #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) +/*! SCLTIMEOUTCLR - SCL time-out interrupt clear. + */ #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) /*! @} */ /*! @name TIMEOUT - Time-out value register. */ /*! @{ */ + #define I2C_TIMEOUT_TOMIN_MASK (0xFU) #define I2C_TIMEOUT_TOMIN_SHIFT (0U) +/*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum + * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. + */ #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) + #define I2C_TIMEOUT_TO_MASK (0xFFF0U) #define I2C_TIMEOUT_TO_SHIFT (4U) +/*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C + * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, + * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A + * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after + * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the + * I2C function clock. + */ #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) /*! @} */ /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ /*! @{ */ + #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) #define I2C_CLKDIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that + * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = + * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is + * divided by 65,536 before use. + */ #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) /*! @} */ /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ /*! @{ */ + #define I2C_INTSTAT_MSTPENDING_MASK (0x1U) #define I2C_INTSTAT_MSTPENDING_SHIFT (0U) +/*! MSTPENDING - Master Pending. + */ #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) + #define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) #define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) +/*! MSTARBLOSS - Master Arbitration Loss flag. + */ #define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) + #define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) #define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) +/*! MSTSTSTPERR - Master Start/Stop Error flag. + */ #define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) + #define I2C_INTSTAT_SLVPENDING_MASK (0x100U) #define I2C_INTSTAT_SLVPENDING_SHIFT (8U) +/*! SLVPENDING - Slave Pending. + */ #define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) + #define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) #define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) +/*! SLVNOTSTR - Slave Not Stretching status. + */ #define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) + #define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) #define I2C_INTSTAT_SLVDESEL_SHIFT (15U) +/*! SLVDESEL - Slave Deselected flag. + */ #define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) + #define I2C_INTSTAT_MONRDY_MASK (0x10000U) #define I2C_INTSTAT_MONRDY_SHIFT (16U) +/*! MONRDY - Monitor Ready. + */ #define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) + #define I2C_INTSTAT_MONOV_MASK (0x20000U) #define I2C_INTSTAT_MONOV_SHIFT (17U) +/*! MONOV - Monitor Overflow flag. + */ #define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) + #define I2C_INTSTAT_MONIDLE_MASK (0x80000U) #define I2C_INTSTAT_MONIDLE_SHIFT (19U) +/*! MONIDLE - Monitor Idle flag. + */ #define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) + #define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) +/*! EVENTTIMEOUT - Event time-out Interrupt flag. + */ #define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) + #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) +/*! SCLTIMEOUT - SCL time-out Interrupt flag. + */ #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) /*! @} */ /*! @name MSTCTL - Master control register. */ /*! @{ */ + #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) /*! MSTCONTINUE - Master Continue. This bit is write-only. @@ -9451,6 +11217,7 @@ typedef struct { * transmit data, reading received data, or any other housekeeping related to the next bus operation. */ #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) + #define I2C_MSTCTL_MSTSTART_MASK (0x2U) #define I2C_MSTCTL_MSTSTART_SHIFT (1U) /*! MSTSTART - Master Start control. This bit is write-only. @@ -9458,6 +11225,7 @@ typedef struct { * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. */ #define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) + #define I2C_MSTCTL_MSTSTOP_MASK (0x4U) #define I2C_MSTCTL_MSTSTOP_SHIFT (2U) /*! MSTSTOP - Master Stop control. This bit is write-only. @@ -9466,6 +11234,7 @@ typedef struct { * if the master is receiving data from the slave (Master Receiver mode). */ #define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) + #define I2C_MSTCTL_MSTDMA_MASK (0x8U) #define I2C_MSTCTL_MSTDMA_SHIFT (3U) /*! MSTDMA - Master DMA enable. Data operations of the I2C can be performed with DMA. Protocol type @@ -9484,6 +11253,7 @@ typedef struct { /*! @name MSTTIME - Master timing configuration. */ /*! @{ */ + #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) /*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this @@ -9500,6 +11270,7 @@ typedef struct { * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. */ #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) + #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) /*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this @@ -9520,13 +11291,18 @@ typedef struct { /*! @name MSTDAT - Combined Master receiver and transmitter data register. */ /*! @{ */ + #define I2C_MSTDAT_DATA_MASK (0xFFU) #define I2C_MSTDAT_DATA_SHIFT (0U) +/*! DATA - Master function data register. Read: read the most recently received data for the Master + * function. Write: transmit data using the Master function. + */ #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) /*! @} */ /*! @name SLVCTL - Slave control register. */ /*! @{ */ + #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) /*! SLVCONTINUE - Slave Continue. @@ -9537,6 +11313,7 @@ typedef struct { * should not be set unless SLVPENDING = 1. */ #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) + #define I2C_SLVCTL_SLVNACK_MASK (0x2U) #define I2C_SLVCTL_SLVNACK_SHIFT (1U) /*! SLVNACK - Slave NACK. @@ -9544,6 +11321,7 @@ typedef struct { * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). */ #define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) + #define I2C_SLVCTL_SLVDMA_MASK (0x8U) #define I2C_SLVCTL_SLVDMA_SHIFT (3U) /*! SLVDMA - Slave DMA enable. @@ -9551,6 +11329,7 @@ typedef struct { * 0b1..Enabled. DMA requests are issued for I2C slave data transmission and reception. */ #define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK) + #define I2C_SLVCTL_AUTOACK_MASK (0x100U) #define I2C_SLVCTL_AUTOACK_SHIFT (8U) /*! AUTOACK - Automatic Acknowledge.When this bit is set, it will cause an I2C header which matches @@ -9566,6 +11345,7 @@ typedef struct { * is set, then it will be Nacked; else if AUTONACK is clear, then a SlvPending interrupt is generated. */ #define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK) + #define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U) #define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U) /*! AUTOMATCHREAD - When AUTOACK is set, this bit controls whether it matches a read or write @@ -9580,13 +11360,18 @@ typedef struct { /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ /*! @{ */ + #define I2C_SLVDAT_DATA_MASK (0xFFU) #define I2C_SLVDAT_DATA_SHIFT (0U) +/*! DATA - Slave function data register. Read: read the most recently received data for the Slave + * function. Write: transmit data using the Slave function. + */ #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) /*! @} */ /*! @name SLVADR - Slave address register. */ /*! @{ */ + #define I2C_SLVADR_SADISABLE_MASK (0x1U) #define I2C_SLVADR_SADISABLE_SHIFT (0U) /*! SADISABLE - Slave Address n Disable. @@ -9594,9 +11379,13 @@ typedef struct { * 0b1..Ignored Slave Address n is ignored. */ #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) + #define I2C_SLVADR_SLVADR_MASK (0xFEU) #define I2C_SLVADR_SLVADR_SHIFT (1U) +/*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. + */ #define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) + #define I2C_SLVADR_AUTONACK_MASK (0x8000U) #define I2C_SLVADR_AUTONACK_SHIFT (15U) /*! AUTONACK - Automatic NACK operation. Used in conjunction with AUTOACK and AUTOMATCHREAD, allows @@ -9613,6 +11402,7 @@ typedef struct { /*! @name SLVQUAL0 - Slave Qualification for address 0. */ /*! @{ */ + #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) /*! QUALMODE0 - Qualify mode for slave address 0. @@ -9620,16 +11410,28 @@ typedef struct { * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. */ #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) + #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) +/*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to + * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is + * set to 1 will cause an automatic match of the corresponding bit of the received address when it + * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for + * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 + * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). + */ #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) /*! @} */ /*! @name MONRXDAT - Monitor receiver data register. */ /*! @{ */ + #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) +/*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. + */ #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) + #define I2C_MONRXDAT_MONSTART_MASK (0x100U) #define I2C_MONRXDAT_MONSTART_SHIFT (8U) /*! MONSTART - Monitor Received Start. @@ -9637,6 +11439,7 @@ typedef struct { * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. */ #define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) + #define I2C_MONRXDAT_MONRESTART_MASK (0x200U) #define I2C_MONRXDAT_MONRESTART_SHIFT (9U) /*! MONRESTART - Monitor Received Repeated Start. @@ -9644,6 +11447,7 @@ typedef struct { * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. */ #define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) + #define I2C_MONRXDAT_MONNACK_MASK (0x400U) #define I2C_MONRXDAT_MONNACK_SHIFT (10U) /*! MONNACK - Monitor Received NACK. @@ -9655,17 +11459,29 @@ typedef struct { /*! @name ID - Peripheral identification register. */ /*! @{ */ + #define I2C_ID_APERTURE_MASK (0xFFU) #define I2C_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ #define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK) + #define I2C_ID_MINOR_REV_MASK (0xF00U) #define I2C_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ #define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK) + #define I2C_ID_MAJOR_REV_MASK (0xF000U) #define I2C_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ #define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK) + #define I2C_ID_ID_MASK (0xFFFF0000U) #define I2C_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ #define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK) /*! @} */ @@ -9676,7 +11492,7 @@ typedef struct { /* I2C - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral I2C0 base address */ #define I2C0_BASE (0x50086000u) /** Peripheral I2C0 base address */ @@ -9812,13 +11628,7 @@ typedef struct { __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */ uint8_t RESERVED_1[16]; __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */ - struct { /* offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0xC20, array step: 0x20 */ - __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0xC24, array step: 0x20 */ - __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0xC28, array step: 0x20 */ - uint8_t RESERVED_0[20]; - } SECCHANNEL[3]; - uint8_t RESERVED_2[384]; + uint8_t RESERVED_2[480]; __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */ @@ -9835,7 +11645,8 @@ typedef struct { uint8_t RESERVED_6[8]; __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */ - uint8_t RESERVED_7[436]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; __I uint32_t ID; /**< I2S Module identification, offset: 0xFFC */ } I2S_Type; @@ -9850,6 +11661,7 @@ typedef struct { /*! @name CFG1 - Configuration register 1 for the primary channel pair. */ /*! @{ */ + #define I2S_CFG1_MAINENABLE_MASK (0x1U) #define I2S_CFG1_MAINENABLE_SHIFT (0U) /*! MAINENABLE - Main enable for I 2S function in this Flexcomm @@ -9858,6 +11670,7 @@ typedef struct { * 0b1..This I 2S channel pair is enabled. Other channel pairs in this Flexcomm may be enabled in their individual PAIRENABLE bits. */ #define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK) + #define I2S_CFG1_DATAPAUSE_MASK (0x2U) #define I2S_CFG1_DATAPAUSE_SHIFT (1U) /*! DATAPAUSE - Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer @@ -9872,6 +11685,7 @@ typedef struct { * 0b1..A pause in the data flow is being requested. It is in effect when DATAPAUSED in STAT = 1. */ #define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK) + #define I2S_CFG1_PAIRCOUNT_MASK (0xCU) #define I2S_CFG1_PAIRCOUNT_SHIFT (2U) /*! PAIRCOUNT - Provides the number of I2S channel pairs in this Flexcomm This is a read-only field @@ -9884,6 +11698,7 @@ typedef struct { * 0b11..4 I2S channel pairs in this flexcomm */ #define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK) + #define I2S_CFG1_MSTSLVCFG_MASK (0x30U) #define I2S_CFG1_MSTSLVCFG_SHIFT (4U) /*! MSTSLVCFG - Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. @@ -9894,6 +11709,7 @@ typedef struct { * 0b11..Normal master mode. SCK and WS are generated so they can be sent to one or more slave devices. */ #define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK) + #define I2S_CFG1_MODE_MASK (0xC0U) #define I2S_CFG1_MODE_SHIFT (6U) /*! MODE - Selects the basic I2S operating mode. Other configurations modify this to obtain all @@ -9908,6 +11724,7 @@ typedef struct { * 0b11..DSP mode where WS has a one data slot long pulse at the beginning of each data frame. */ #define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK) + #define I2S_CFG1_RIGHTLOW_MASK (0x100U) #define I2S_CFG1_RIGHTLOW_SHIFT (8U) /*! RIGHTLOW - Right channel data is in the Low portion of FIFO data. Essentially, this swaps left @@ -9922,6 +11739,7 @@ typedef struct { * bits 15:0 are used for the right channel. */ #define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK) + #define I2S_CFG1_LEFTJUST_MASK (0x200U) #define I2S_CFG1_LEFTJUST_SHIFT (9U) /*! LEFTJUST - Left Justify data. @@ -9933,6 +11751,7 @@ typedef struct { * correspond to left justified data in the stream on the data bus. */ #define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK) + #define I2S_CFG1_ONECHANNEL_MASK (0x400U) #define I2S_CFG1_ONECHANNEL_SHIFT (10U) /*! ONECHANNEL - Single channel mode. Applies to both transmit and receive. This configuration bit @@ -9947,17 +11766,7 @@ typedef struct { * for the single channel of data is placed at the clock defined by POSITION. */ #define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK) -#define I2S_CFG1_PDMDATA_MASK (0x800U) -#define I2S_CFG1_PDMDATA_SHIFT (11U) -/*! PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be - * set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a - * D-Mic subsystem. For the LPC55xx, this bit applies only to Flexcomm 6,7. - * 0b0..Normal operation, data is transferred to or from the Flexcomm FIFO. - * 0b1..The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in - * this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample - * rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. - */ -#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK) + #define I2S_CFG1_SCK_POL_MASK (0x1000U) #define I2S_CFG1_SCK_POL_SHIFT (12U) /*! SCK_POL - SCK polarity. @@ -9965,6 +11774,7 @@ typedef struct { * 0b1..Data is launched on SCK rising edges and sampled on SCK falling edges. */ #define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK) + #define I2S_CFG1_WS_POL_MASK (0x2000U) #define I2S_CFG1_WS_POL_SHIFT (13U) /*! WS_POL - WS polarity. @@ -9972,23 +11782,54 @@ typedef struct { * 0b1..WS is inverted, resulting in a data frame beginning at a rising edge of WS (standard for most 'non-classic' variations of I2S). */ #define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK) + #define I2S_CFG1_DATALEN_MASK (0x1F0000U) #define I2S_CFG1_DATALEN_SHIFT (16U) +/*! DATALEN - Data Length, minus 1 encoded, defines the number of data bits to be transmitted or + * received for all I2S channel pairs in this Flexcomm. Note that data is only driven to or received + * from SDA for the number of bits defined by DATALEN. DATALEN is also used in these ways by the + * I2S: Determines the size of data transfers between the FIFO and the I2S + * serializer/deserializer. See FIFO buffer configurations and usage In mode 1, 2, and 3, determines the location of + * right data following left data in the frame. In mode 3 (where WS has a one data slot long pulse + * at the beginning of each data frame) determines the duration of the WS pulse. Values: 0x00 to + * 0x02 = not supported 0x03 = data is 4 bits in length 0x04 = data is 5 bits in length 0x1F = + * data is 32 bits in length + */ #define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK) /*! @} */ /*! @name CFG2 - Configuration register 2 for the primary channel pair. */ /*! @{ */ + #define I2S_CFG2_FRAMELEN_MASK (0x1FFU) #define I2S_CFG2_FRAMELEN_SHIFT (0U) +/*! FRAMELEN - Frame Length, minus 1 encoded, defines the number of clocks and data bits in the + * frames that this channel pair participates in. See Frame format. 0x000 to 0x002 = not supported + * 0x003 = frame is 4 bits in total length 0x004 = frame is 5 bits in total length 0x1FF = frame is + * 512 bits in total length if FRAMELEN is an defines an odd length frame (e.g. 33 clocks) in + * mode 0 or 1, the extra clock appears in the right half. When MODE = 3, FRAMELEN must be larger + * than DATALEN in order for the WS pulse to be generated correctly. + */ #define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK) + #define I2S_CFG2_POSITION_MASK (0x1FF0000U) #define I2S_CFG2_POSITION_SHIFT (16U) +/*! POSITION - Data Position. Defines the location within the frame of the data for this channel + * pair. POSITION + DATALEN must be less than FRAMELEN. See Frame format. When MODE = 0, POSITION + * defines the location of data in both the left phase and right phase, starting one clock after + * the WS edge. In other modes, POSITION defines the location of data within the entire frame. + * ONECHANNEL = 1 while MODE = 0 is a special case, see the description of ONECHANNEL. The + * combination of DATALEN and the POSITION fields of all channel pairs must be made such that the channels + * do not overlap within the frame. 0x000 = data begins at bit position 0 (the first bit + * position) within the frame or WS phase. 0x001 = data begins at bit position 1 within the frame or WS + * phase. 0x002 = data begins at bit position 2 within the frame or WS phase. + */ #define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK) /*! @} */ /*! @name STAT - Status register for the primary channel pair. */ /*! @{ */ + #define I2S_STAT_BUSY_MASK (0x1U) #define I2S_STAT_BUSY_SHIFT (0U) /*! BUSY - Busy status for the primary channel pair. Other BUSY flags may be found in the STAT register for each channel pair. @@ -9996,6 +11837,7 @@ typedef struct { * 0b1..The transmitter/receiver for channel pair is currently processing data. */ #define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK) + #define I2S_STAT_SLVFRMERR_MASK (0x2U) #define I2S_STAT_SLVFRMERR_SHIFT (1U) /*! SLVFRMERR - Slave Frame Error flag. This applies when at least one channel pair is operating as @@ -10005,6 +11847,7 @@ typedef struct { * 0b1..An error has been recorded for some channel pair that is operating in slave mode. ERROR is cleared by writing a 1 to this bit position. */ #define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK) + #define I2S_STAT_LR_MASK (0x4U) #define I2S_STAT_LR_SHIFT (2U) /*! LR - Left/Right indication. This flag is considered to be a debugging aid and is not expected to @@ -10014,6 +11857,7 @@ typedef struct { * 0b1..Right channel. */ #define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK) + #define I2S_STAT_DATAPAUSED_MASK (0x8U) #define I2S_STAT_DATAPAUSED_SHIFT (3U) /*! DATAPAUSED - Data Paused status flag. Applies to all I2S channels @@ -10026,55 +11870,20 @@ typedef struct { /*! @name DIV - Clock divider, used by all channel pairs. */ /*! @{ */ + #define I2S_DIV_DIV_MASK (0xFFFU) #define I2S_DIV_DIV_SHIFT (0U) +/*! DIV - This field controls how this I2S block uses the Flexcomm function clock. 0x000 = The + * Flexcomm function clock is used directly. 0x001 = The Flexcomm function clock is divided by 2. + * 0x002 = The Flexcomm function clock is divided by 3. 0xFFF = The Flexcomm function clock is + * divided by 4,096. + */ #define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK) /*! @} */ -/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U) -#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U) -#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG1 */ -#define I2S_SECCHANNEL_PCFG1_COUNT (3U) - -/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U) -#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U) -#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PCFG2 */ -#define I2S_SECCHANNEL_PCFG2_COUNT (3U) - -/*! @name SECCHANNEL_PSTAT - Status register for channel pair */ -/*! @{ */ -#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U) -#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U) -#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U) -#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK) -#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U) -#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U) -#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U) -#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK) -/*! @} */ - -/* The count of I2S_SECCHANNEL_PSTAT */ -#define I2S_SECCHANNEL_PSTAT_COUNT (3U) - /*! @name FIFOCFG - FIFO configuration and enable register. */ /*! @{ */ + #define I2S_FIFOCFG_ENABLETX_MASK (0x1U) #define I2S_FIFOCFG_ENABLETX_SHIFT (0U) /*! ENABLETX - Enable the transmit FIFO. @@ -10082,6 +11891,7 @@ typedef struct { * 0b1..The transmit FIFO is enabled. */ #define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK) + #define I2S_FIFOCFG_ENABLERX_MASK (0x2U) #define I2S_FIFOCFG_ENABLERX_SHIFT (1U) /*! ENABLERX - Enable the receive FIFO. @@ -10089,6 +11899,7 @@ typedef struct { * 0b1..The receive FIFO is enabled. */ #define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK) + #define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) #define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) /*! TXI2SE0 - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX @@ -10099,6 +11910,7 @@ typedef struct { * 0b1..If the TX FIFO becomes empty, 0 is sent. Use if the data length is greater than 24 bits or if zero fill is preferred. */ #define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) + #define I2S_FIFOCFG_PACK48_MASK (0x8U) #define I2S_FIFOCFG_PACK48_SHIFT (3U) /*! PACK48 - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA. @@ -10106,9 +11918,14 @@ typedef struct { * 0b1..48-bit I2S FIFO entries are handled as alternating 32-bit and 16-bit values. */ #define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) + #define I2S_FIFOCFG_SIZE_MASK (0x30U) #define I2S_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ #define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK) + #define I2S_FIFOCFG_DMATX_MASK (0x1000U) #define I2S_FIFOCFG_DMATX_SHIFT (12U) /*! DMATX - DMA configuration for transmit. @@ -10116,6 +11933,7 @@ typedef struct { * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. */ #define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK) + #define I2S_FIFOCFG_DMARX_MASK (0x2000U) #define I2S_FIFOCFG_DMARX_SHIFT (13U) /*! DMARX - DMA configuration for receive. @@ -10123,6 +11941,7 @@ typedef struct { * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. */ #define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK) + #define I2S_FIFOCFG_WAKETX_MASK (0x4000U) #define I2S_FIFOCFG_WAKETX_SHIFT (14U) /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power @@ -10135,6 +11954,7 @@ typedef struct { * FIFOTRIG, even when the TXLVL interrupt is not enabled. */ #define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK) + #define I2S_FIFOCFG_WAKERX_MASK (0x8000U) #define I2S_FIFOCFG_WAKERX_SHIFT (15U) /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power @@ -10147,54 +11967,93 @@ typedef struct { * FIFOTRIG, even when the RXLVL interrupt is not enabled. */ #define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK) + #define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U) #define I2S_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ #define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK) + #define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U) #define I2S_FIFOCFG_EMPTYRX_SHIFT (17U) -#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) -#define I2S_FIFOCFG_POPDBG_MASK (0x40000U) -#define I2S_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. */ -#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK) +#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK) /*! @} */ /*! @name FIFOSTAT - FIFO status register. */ /*! @{ */ + #define I2S_FIFOSTAT_TXERR_MASK (0x1U) #define I2S_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ #define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK) + #define I2S_FIFOSTAT_RXERR_MASK (0x2U) #define I2S_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ #define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK) + #define I2S_FIFOSTAT_PERINT_MASK (0x8U) #define I2S_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ #define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK) + #define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U) #define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ #define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK) + #define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U) #define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ #define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK) + #define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) #define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ #define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK) + #define I2S_FIFOSTAT_RXFULL_MASK (0x80U) #define I2S_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ #define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK) + #define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U) #define I2S_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ #define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK) + #define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define I2S_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ #define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK) /*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ /*! @{ */ + #define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U) #define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U) /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -10203,6 +12062,7 @@ typedef struct { * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. */ #define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK) + #define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U) #define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U) /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -10211,16 +12071,32 @@ typedef struct { * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. */ #define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK) + #define I2S_FIFOTRIG_TXLVL_MASK (0xF00U) #define I2S_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ #define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK) + #define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U) #define I2S_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ #define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK) /*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ /*! @{ */ + #define I2S_FIFOINTENSET_TXERR_MASK (0x1U) #define I2S_FIFOINTENSET_TXERR_SHIFT (0U) /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. @@ -10228,6 +12104,7 @@ typedef struct { * 0b1..An interrupt will be generated when a transmit error occurs. */ #define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK) + #define I2S_FIFOINTENSET_RXERR_MASK (0x2U) #define I2S_FIFOINTENSET_RXERR_SHIFT (1U) /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. @@ -10235,6 +12112,7 @@ typedef struct { * 0b1..An interrupt will be generated when a receive error occurs. */ #define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK) + #define I2S_FIFOINTENSET_TXLVL_MASK (0x4U) #define I2S_FIFOINTENSET_TXLVL_SHIFT (2U) /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level @@ -10244,6 +12122,7 @@ typedef struct { * to the level specified by TXLVL in the FIFOTRIG register. */ #define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK) + #define I2S_FIFOINTENSET_RXLVL_MASK (0x8U) #define I2S_FIFOINTENSET_RXLVL_SHIFT (3U) /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level @@ -10257,94 +12136,161 @@ typedef struct { /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ /*! @{ */ + #define I2S_FIFOINTENCLR_TXERR_MASK (0x1U) #define I2S_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK) + #define I2S_FIFOINTENCLR_RXERR_MASK (0x2U) #define I2S_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK) + #define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U) #define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK) + #define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U) #define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK) /*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ /*! @{ */ + #define I2S_FIFOINTSTAT_TXERR_MASK (0x1U) #define I2S_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ #define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK) + #define I2S_FIFOINTSTAT_RXERR_MASK (0x2U) #define I2S_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ #define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK) + #define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U) #define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ #define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK) + #define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U) #define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ #define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK) + #define I2S_FIFOINTSTAT_PERINT_MASK (0x10U) #define I2S_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ #define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK) /*! @} */ /*! @name FIFOWR - FIFO write data. */ /*! @{ */ + #define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. The number of bits used depends on configuration details. + */ #define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK) /*! @} */ /*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ /*! @{ */ + #define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU) #define I2S_FIFOWR48H_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ #define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK) /*! @} */ /*! @name FIFORD - FIFO read data. */ /*! @{ */ + #define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on configuration details. + */ #define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK) /*! @} */ /*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ /*! @{ */ + #define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU) #define I2S_FIFORD48H_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ #define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK) /*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ /*! @{ */ + #define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU) #define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ #define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK) /*! @} */ /*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */ /*! @{ */ + #define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU) #define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. Whether this register is used and the number of bits used depends on configuration details. + */ #define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK) /*! @} */ +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define I2S_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define I2S_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define I2S_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSIZE_FIFOSIZE_SHIFT)) & I2S_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + /*! @name ID - I2S Module identification */ /*! @{ */ -#define I2S_ID_Aperture_MASK (0xFFU) -#define I2S_ID_Aperture_SHIFT (0U) -#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK) -#define I2S_ID_Minor_Rev_MASK (0xF00U) -#define I2S_ID_Minor_Rev_SHIFT (8U) -#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK) -#define I2S_ID_Major_Rev_MASK (0xF000U) -#define I2S_ID_Major_Rev_SHIFT (12U) -#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK) + +#define I2S_ID_APERTURE_MASK (0xFFU) +#define I2S_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ +#define I2S_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_APERTURE_SHIFT)) & I2S_ID_APERTURE_MASK) + +#define I2S_ID_MINOR_REV_MASK (0xF00U) +#define I2S_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation, starting at 0. + */ +#define I2S_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MINOR_REV_SHIFT)) & I2S_ID_MINOR_REV_MASK) + +#define I2S_ID_MAJOR_REV_MASK (0xF000U) +#define I2S_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation, starting at 0. + */ +#define I2S_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_MAJOR_REV_SHIFT)) & I2S_ID_MAJOR_REV_MASK) + #define I2S_ID_ID_MASK (0xFFFF0000U) #define I2S_ID_ID_SHIFT (16U) +/*! ID - Unique module identifier for this IP block. + */ #define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK) /*! @} */ @@ -10355,7 +12301,7 @@ typedef struct { /* I2S - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral I2S0 base address */ #define I2S0_BASE (0x50086000u) /** Peripheral I2S0 base address */ @@ -10547,6 +12493,7 @@ typedef struct { /*! @name SCT0_INMUX - Input mux register for SCT0 input */ /*! @{ */ + #define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU) #define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U) /*! INP_N - Input number to SCT0 inputs 0 to 6.. @@ -10584,6 +12531,7 @@ typedef struct { /*! @name TIMER0CAPTSEL - Capture select registers for TIMER0 inputs */ /*! @{ */ + #define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_MASK (0x1FU) #define INPUTMUX_TIMER0CAPTSEL_CAPTSEL_SHIFT (0U) /*! CAPTSEL - Input number to TIMER0 capture inputs 0 to 4 @@ -10604,9 +12552,9 @@ typedef struct { * 0b01110..CT_INP14 function selected from IOCON register * 0b01111..CT_INP15 function selected from IOCON register * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None * 0b10100..USB0_FRAME_TOGGLE * 0b10101..USB1_FRAME_TOGGLE * 0b10110..COMP_OUTPUT output from analog comparator @@ -10622,6 +12570,7 @@ typedef struct { /*! @name TIMER1CAPTSEL - Capture select registers for TIMER1 inputs */ /*! @{ */ + #define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_MASK (0x1FU) #define INPUTMUX_TIMER1CAPTSEL_CAPTSEL_SHIFT (0U) /*! CAPTSEL - Input number to TIMER1 capture inputs 0 to 4 @@ -10642,9 +12591,9 @@ typedef struct { * 0b01110..CT_INP14 function selected from IOCON register * 0b01111..CT_INP15 function selected from IOCON register * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None * 0b10100..USB0_FRAME_TOGGLE * 0b10101..USB1_FRAME_TOGGLE * 0b10110..COMP_OUTPUT output from analog comparator @@ -10660,6 +12609,7 @@ typedef struct { /*! @name TIMER2CAPTSEL - Capture select registers for TIMER2 inputs */ /*! @{ */ + #define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_MASK (0x1FU) #define INPUTMUX_TIMER2CAPTSEL_CAPTSEL_SHIFT (0U) /*! CAPTSEL - Input number to TIMER2 capture inputs 0 to 4 @@ -10680,9 +12630,9 @@ typedef struct { * 0b01110..CT_INP14 function selected from IOCON register * 0b01111..CT_INP15 function selected from IOCON register * 0b10000..CT_INP16 function selected from IOCON register - * 0b10001..CT_INP17 function selected from IOCON register - * 0b10010..CT_INP18 function selected from IOCON register - * 0b10011..CT_INP19 function selected from IOCON register + * 0b10001..None + * 0b10010..None + * 0b10011..None * 0b10100..USB0_FRAME_TOGGLE * 0b10101..USB1_FRAME_TOGGLE * 0b10110..COMP_OUTPUT output from analog comparator @@ -10698,8 +12648,12 @@ typedef struct { /*! @name PINTSEL - Pin interrupt select register */ /*! @{ */ + #define INPUTMUX_PINTSEL_INTPIN_MASK (0x7FU) #define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt or pattern match engine input. For PIOx_y: INTPIN = + * (x * 32) + y. PIO0_0 to PIO1_31 correspond to numbers 0 to 63. + */ #define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK) /*! @} */ @@ -10708,6 +12662,7 @@ typedef struct { /*! @name DMA0_ITRIG_INMUX - Trigger select register for DMA0 channel */ /*! @{ */ + #define INPUTMUX_DMA0_ITRIG_INMUX_INP_MASK (0x1FU) #define INPUTMUX_DMA0_ITRIG_INMUX_INP_SHIFT (0U) /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 22). @@ -10743,8 +12698,11 @@ typedef struct { /*! @name DMA0_OTRIG_INMUX - DMA0 output trigger selection to become DMA0 trigger */ /*! @{ */ + #define INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK (0x1FU) #define INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 22). + */ #define INPUTMUX_DMA0_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA0_OTRIG_INMUX_INP_MASK) /*! @} */ @@ -10753,20 +12711,43 @@ typedef struct { /*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */ /*! @{ */ + #define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU) #define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function reference clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ #define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK) /*! @} */ /*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */ /*! @{ */ + #define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU) #define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U) +/*! CLKIN - Clock source number (decimal value) for frequency measure function target clock: + * 0b00000..External main crystal oscilator (Clock_in). + * 0b00001..FRO 12MHz clock. + * 0b00010..FRO 96MHz clock. + * 0b00011..Watchdog oscillator / FRO1MHz clock. + * 0b00100..32 kHz oscillator (32k_clk) clock. + * 0b00101..main clock (main_clock). + * 0b00110..FREQME_GPIO_CLK_A. + * 0b00111..FREQME_GPIO_CLK_B. + */ #define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK) /*! @} */ /*! @name TIMER3CAPTSEL - Capture select registers for TIMER3 inputs */ /*! @{ */ + #define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_MASK (0x1FU) #define INPUTMUX_TIMER3CAPTSEL_CAPTSEL_SHIFT (0U) /*! CAPTSEL - Input number to TIMER3 capture inputs 0 to 4 @@ -10805,6 +12786,7 @@ typedef struct { /*! @name TIMER4CAPTSEL - Capture select registers for TIMER4 inputs */ /*! @{ */ + #define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_MASK (0x1FU) #define INPUTMUX_TIMER4CAPTSEL_CAPTSEL_SHIFT (0U) /*! CAPTSEL - Input number to TIMER4 capture inputs 0 to 4 @@ -10843,8 +12825,12 @@ typedef struct { /*! @name PINTSECSEL - Pin interrupt secure select register */ /*! @{ */ + #define INPUTMUX_PINTSECSEL_INTPIN_MASK (0x3FU) #define INPUTMUX_PINTSECSEL_INTPIN_SHIFT (0U) +/*! INTPIN - Pin number select for pin interrupt secure or pattern match engine input. For PIO0_x: + * INTPIN = x. PIO0_0 to PIO0_31 correspond to numbers 0 to 31. + */ #define INPUTMUX_PINTSECSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSECSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSECSEL_INTPIN_MASK) /*! @} */ @@ -10853,6 +12839,7 @@ typedef struct { /*! @name DMA1_ITRIG_INMUX - Trigger select register for DMA1 channel */ /*! @{ */ + #define INPUTMUX_DMA1_ITRIG_INMUX_INP_MASK (0xFU) #define INPUTMUX_DMA1_ITRIG_INMUX_INP_SHIFT (0U) /*! INP - Trigger input number (decimal value) for DMA channel n (n = 0 to 9). @@ -10881,8 +12868,11 @@ typedef struct { /*! @name DMA1_OTRIG_INMUX - DMA1 output trigger selection to become DMA1 trigger */ /*! @{ */ + #define INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK (0xFU) #define INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT (0U) +/*! INP - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9). + */ #define INPUTMUX_DMA1_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA1_OTRIG_INMUX_INP_MASK) /*! @} */ @@ -10891,85 +12881,125 @@ typedef struct { /*! @name DMA0_REQ_ENA - Enable DMA0 requests */ /*! @{ */ + #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK (0x7FFFFFU) #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 23 request inputs of DMA0. If bit i is '1' the DMA request input #i is enabled. + */ #define INPUTMUX_DMA0_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_REQ_ENA_MASK) /*! @} */ /*! @name DMA0_REQ_ENA_SET - Set one or several bits in DMA0_REQ_ENA register */ /*! @{ */ + #define INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK (0x7FFFFFU) #define INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA0_REQ_ENA register + */ #define INPUTMUX_DMA0_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_SET_SET_MASK) /*! @} */ /*! @name DMA0_REQ_ENA_CLR - Clear one or several bits in DMA0_REQ_ENA register */ /*! @{ */ + #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK (0x7FFFFFU) #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA0_REQ_ENA register + */ #define INPUTMUX_DMA0_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_REQ_ENA_CLR_CLR_MASK) /*! @} */ /*! @name DMA1_REQ_ENA - Enable DMA1 requests */ /*! @{ */ + #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK (0x3FFU) #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT (0U) +/*! REQ_ENA - Controls the 10 request inputs of DMA1. If bit i is '1' the DMA request input #i is enabled. + */ #define INPUTMUX_DMA1_REQ_ENA_REQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_REQ_ENA_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_REQ_ENA_MASK) /*! @} */ /*! @name DMA1_REQ_ENA_SET - Set one or several bits in DMA1_REQ_ENA register */ /*! @{ */ + #define INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK (0x3FFU) #define INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is set to 1; if bit #i = 0 , no change in DMA1_REQ_ENA register + */ #define INPUTMUX_DMA1_REQ_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_SET_SET_MASK) /*! @} */ /*! @name DMA1_REQ_ENA_CLR - Clear one or several bits in DMA1_REQ_ENA register */ /*! @{ */ + #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK (0x3FFU) #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_REQ_ENA register is reset to 0; if bit #i = 0 , no change in DMA1_REQ_ENA register + */ #define INPUTMUX_DMA1_REQ_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_REQ_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_REQ_ENA_CLR_CLR_MASK) /*! @} */ /*! @name DMA0_ITRIG_ENA - Enable DMA0 triggers */ /*! @{ */ + #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK (0x3FFFFFU) #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 22 trigger inputs of DMA0. If bit i is '1' the DMA trigger input #i is enabled. + */ #define INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_ITRIG_ENA_MASK) /*! @} */ /*! @name DMA0_ITRIG_ENA_SET - Set one or several bits in DMA0_ITRIG_ENA register */ /*! @{ */ + #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK (0x3FFFFFU) #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ #define INPUTMUX_DMA0_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_SET_SET_MASK) /*! @} */ /*! @name DMA0_ITRIG_ENA_CLR - Clear one or several bits in DMA0_ITRIG_ENA register */ /*! @{ */ + #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK (0x3FFFFFU) #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA0_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA0_ITRIG_ENA register + */ #define INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA0_ITRIG_ENA_CLR_CLR_MASK) /*! @} */ /*! @name DMA1_ITRIG_ENA - Enable DMA1 triggers */ /*! @{ */ + #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK (0x7FFFU) #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT (0U) +/*! ITRIG_ENA - Controls the 15 trigger inputs of DMA1. If bit i is '1' the DMA trigger input #i is enabled. + */ #define INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_ITRIG_ENA_MASK) /*! @} */ /*! @name DMA1_ITRIG_ENA_SET - Set one or several bits in DMA1_ITRIG_ENA register */ /*! @{ */ + #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK (0x7FFFU) #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT (0U) +/*! SET - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is set to 1; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ #define INPUTMUX_DMA1_ITRIG_ENA_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_SET_SET_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_SET_SET_MASK) /*! @} */ /*! @name DMA1_ITRIG_ENA_CLR - Clear one or several bits in DMA1_ITRIG_ENA register */ /*! @{ */ + #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK (0x7FFFU) #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT (0U) +/*! CLR - Write : If bit #i = 1, bit #i in DMA1_ITRIG_ENA register is reset to 0; if bit #i = 0 , no + * change in DMA1_ITRIG_ENA register + */ #define INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_SHIFT)) & INPUTMUX_DMA1_ITRIG_ENA_CLR_CLR_MASK) /*! @} */ @@ -10980,7 +13010,7 @@ typedef struct { /* INPUTMUX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral INPUTMUX base address */ #define INPUTMUX_BASE (0x50006000u) /** Peripheral INPUTMUX base address */ @@ -11038,6 +13068,7 @@ typedef struct { /*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 1 pins PIO1_31 */ /*! @{ */ + #define IOCON_PIO_FUNC_MASK (0xFU) #define IOCON_PIO_FUNC_SHIFT (0U) /*! FUNC - Selects pin function. @@ -11051,6 +13082,7 @@ typedef struct { * 0b0111..Alternative connection 7. */ #define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK) + #define IOCON_PIO_MODE_MASK (0x30U) #define IOCON_PIO_MODE_SHIFT (4U) /*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). @@ -11060,13 +13092,15 @@ typedef struct { * 0b11..Repeater. Repeater mode. */ #define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) + #define IOCON_PIO_SLEW_MASK (0x40U) #define IOCON_PIO_SLEW_SHIFT (6U) /*! SLEW - Driver slew rate. - * 0b0..Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. - * 0b1..Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + * 0b0..Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. + * 0b1..Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. */ #define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK) + #define IOCON_PIO_INVERT_MASK (0x80U) #define IOCON_PIO_INVERT_SHIFT (7U) /*! INVERT - Input polarity. @@ -11074,27 +13108,32 @@ typedef struct { * 0b1..Enabled. Input is function inverted. */ #define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK) + #define IOCON_PIO_DIGIMODE_MASK (0x100U) #define IOCON_PIO_DIGIMODE_SHIFT (8U) /*! DIGIMODE - Select Digital mode. - * 0b0..Analog mode, digital input is disabled. - * 0b1..Digital mode, digital input is enabled. + * 0b0..Disable digital mode. Digital input set to 0. + * 0b1..Enable Digital mode. Digital input is enabled. */ #define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK) + #define IOCON_PIO_OD_MASK (0x200U) #define IOCON_PIO_OD_SHIFT (9U) -/*! OD - Controls open-drain mode. +/*! OD - Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). * 0b0..Normal. Normal push-pull output * 0b1..Open-drain. Simulated open-drain output (high drive disabled). */ #define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) + #define IOCON_PIO_ASW_MASK (0x400U) #define IOCON_PIO_ASW_SHIFT (10U) -/*! ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 - * 0b0..Analog switch is open. - * 0b1..Analog switch is closed. +/*! ASW - Analog switch input control. + * 0b0..For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed + * (enabled). For the other pins, analog switch is open (disabled). + * 0b1..For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) */ #define IOCON_PIO_ASW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ASW_SHIFT)) & IOCON_PIO_ASW_MASK) + #define IOCON_PIO_SSEL_MASK (0x800U) #define IOCON_PIO_SSEL_SHIFT (11U) /*! SSEL - Supply Selection bit. @@ -11102,32 +13141,36 @@ typedef struct { * 0b1..1V8 Signaling in I2C Mode. */ #define IOCON_PIO_SSEL(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SSEL_SHIFT)) & IOCON_PIO_SSEL_MASK) + #define IOCON_PIO_FILTEROFF_MASK (0x1000U) #define IOCON_PIO_FILTEROFF_SHIFT (12U) /*! FILTEROFF - Controls input glitch filter. - * 0b0..Filter enabled. Noise pulses below approximately 10 ns are filtered out. - * 0b1..Filter disabled. No input filtering is done. + * 0b0..Filter enabled. + * 0b1..Filter disabled. */ #define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK) + #define IOCON_PIO_ECS_MASK (0x2000U) #define IOCON_PIO_ECS_SHIFT (13U) -/*! ECS - Pull-up current source enable in IIC mode. +/*! ECS - Pull-up current source enable in I2C mode. * 0b1..Enabled. Pull resistor is conencted. - * 0b0..Disabled. IO is in open drain. + * 0b0..Disabled. IO is in open drain cell. */ #define IOCON_PIO_ECS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_ECS_SHIFT)) & IOCON_PIO_ECS_MASK) + #define IOCON_PIO_EGP_MASK (0x4000U) #define IOCON_PIO_EGP_SHIFT (14U) -/*! EGP - Controls slew rate of I2C pad. +/*! EGP - Switch between GPIO mode and I2C mode. * 0b0..I2C mode. * 0b1..GPIO mode. */ #define IOCON_PIO_EGP(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_EGP_SHIFT)) & IOCON_PIO_EGP_MASK) + #define IOCON_PIO_I2CFILTER_MASK (0x8000U) #define IOCON_PIO_I2CFILTER_SHIFT (15U) -/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. - * 0b0..I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. - * 0b1..I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. +/*! I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. + * 0b0..I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. + * 0b1..I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. */ #define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK) /*! @} */ @@ -11145,7 +13188,7 @@ typedef struct { /* IOCON - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral IOCON base address */ #define IOCON_BASE (0x50001000u) /** Peripheral IOCON base address */ @@ -11210,8 +13253,11 @@ typedef struct { /*! @name MBOXIRQ_IRQ - Interrupt request register for the Cortex-M0+ CPU. */ /*! @{ */ + #define MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT (0U) +/*! INTREQ - If any bit is set, an interrupt request is sent to the Cortex-M0+ interrupt controller. + */ #define MAILBOX_MBOXIRQ_IRQ_INTREQ(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQ_INTREQ_SHIFT)) & MAILBOX_MBOXIRQ_IRQ_INTREQ_MASK) /*! @} */ @@ -11220,8 +13266,11 @@ typedef struct { /*! @name MBOXIRQ_IRQSET - Set bits in IRQ0 */ /*! @{ */ + #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT (0U) +/*! INTREQSET - Writing 1 sets the corresponding bit in the IRQ0 register. + */ #define MAILBOX_MBOXIRQ_IRQSET_INTREQSET(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQSET_INTREQSET_SHIFT)) & MAILBOX_MBOXIRQ_IRQSET_INTREQSET_MASK) /*! @} */ @@ -11230,8 +13279,11 @@ typedef struct { /*! @name MBOXIRQ_IRQCLR - Clear bits in IRQ0 */ /*! @{ */ + #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK (0xFFFFFFFFU) #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT (0U) +/*! INTREQCLR - Writing 1 clears the corresponding bit in the IRQ0 register. + */ #define MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_SHIFT)) & MAILBOX_MBOXIRQ_IRQCLR_INTREQCLR_MASK) /*! @} */ @@ -11240,8 +13292,11 @@ typedef struct { /*! @name MUTEX - Mutual exclusion register[1] */ /*! @{ */ + #define MAILBOX_MUTEX_EX_MASK (0x1U) #define MAILBOX_MUTEX_EX_SHIFT (0U) +/*! EX - Cleared when read, set when written. See usage description above. + */ #define MAILBOX_MUTEX_EX(x) (((uint32_t)(((uint32_t)(x)) << MAILBOX_MUTEX_EX_SHIFT)) & MAILBOX_MUTEX_EX_MASK) /*! @} */ @@ -11252,7 +13307,7 @@ typedef struct { /* MAILBOX - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral MAILBOX base address */ #define MAILBOX_BASE (0x5008B000u) /** Peripheral MAILBOX base address */ @@ -11321,9 +13376,17 @@ typedef struct { /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ /*! @{ */ + #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU) #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) +/*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT + * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to + * this bit field starts the timer immediately. If the timer is running, writing a zero to this + * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer + * stops at the end of the time interval. + */ #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) + #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) /*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. @@ -11340,8 +13403,15 @@ typedef struct { /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ /*! @{ */ + #define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU) #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) +/*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn + * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval + * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn + * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields + * returns -1 (0x00FF FFFF). + */ #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) /*! @} */ @@ -11350,6 +13420,7 @@ typedef struct { /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ /*! @{ */ + #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) /*! INTEN - Enable the TIMERn interrupt. @@ -11357,6 +13428,7 @@ typedef struct { * 0b1..Enabled. TIMERn interrupt is enabled. */ #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) + #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) /*! MODE - Selects timer mode. @@ -11373,6 +13445,7 @@ typedef struct { /*! @name CHANNEL_STAT - MRT Status register. */ /*! @{ */ + #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) /*! INTFLAG - Monitors the interrupt flag. @@ -11382,6 +13455,7 @@ typedef struct { * are raised. Writing a 1 to this bit clears the interrupt request. */ #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) + #define MRT_CHANNEL_STAT_RUN_MASK (0x2U) #define MRT_CHANNEL_STAT_RUN_SHIFT (1U) /*! RUN - Indicates the state of TIMERn. This bit is read-only. @@ -11389,6 +13463,7 @@ typedef struct { * 0b1..Running. TIMERn is running. */ #define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) + #define MRT_CHANNEL_STAT_INUSE_MASK (0x4U) #define MRT_CHANNEL_STAT_INUSE_SHIFT (2U) /*! INUSE - Channel In Use flag. Operating details depend on the MULTITASK bit in the MODCFG @@ -11405,12 +13480,19 @@ typedef struct { /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */ /*! @{ */ + #define MRT_MODCFG_NOC_MASK (0xFU) #define MRT_MODCFG_NOC_SHIFT (0U) +/*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) + */ #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) + #define MRT_MODCFG_NOB_MASK (0x1F0U) #define MRT_MODCFG_NOB_SHIFT (4U) +/*! NOB - Identifies the number of timer bits in this MRT. (24 bits wide on this device.) + */ #define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) + #define MRT_MODCFG_MULTITASK_MASK (0x80000000U) #define MRT_MODCFG_MULTITASK_SHIFT (31U) /*! MULTITASK - Selects the operating mode for the INUSE flags and the IDLE_CH register. @@ -11422,13 +13504,20 @@ typedef struct { /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ /*! @{ */ + #define MRT_IDLE_CH_CHAN_MASK (0xF0U) #define MRT_IDLE_CH_CHAN_SHIFT (4U) +/*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is + * positioned such that it can be used as an offset from the MRT base address in order to access + * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See + * text above for more details. + */ #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) /*! @} */ /*! @name IRQ_FLAG - Global interrupt flag register */ /*! @{ */ + #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) /*! GFLAG0 - Monitors the interrupt flag of TIMER0. @@ -11438,14 +13527,23 @@ typedef struct { * interrupt are raised. Writing a 1 to this bit clears the interrupt request. */ #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) + #define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) #define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) +/*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. + */ #define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) + #define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U) #define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U) +/*! GFLAG2 - Monitors the interrupt flag of TIMER2. See description of channel 0. + */ #define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK) + #define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U) #define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U) +/*! GFLAG3 - Monitors the interrupt flag of TIMER3. See description of channel 0. + */ #define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK) /*! @} */ @@ -11456,7 +13554,7 @@ typedef struct { /* MRT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral MRT0 base address */ #define MRT0_BASE (0x5000D000u) /** Peripheral MRT0 base address */ @@ -11504,12 +13602,12 @@ typedef struct { typedef struct { __I uint32_t EVTIMERL; /**< EVTIMER Low Register, offset: 0x0 */ __I uint32_t EVTIMERH; /**< EVTIMER High Register, offset: 0x4 */ - __I uint32_t CAPTUREN_L; /**< Local Capture Low Register for CPUn, offset: 0x8 */ - __I uint32_t CAPTUREN_H; /**< Local Capture High Register for CPUn, offset: 0xC */ - __IO uint32_t MATCHN_L; /**< Local Match Low Register for CPUn, offset: 0x10 */ - __IO uint32_t MATCHN_H; /**< Match High Register for CPUn, offset: 0x14 */ + __I uint32_t CAPTURE_L; /**< Capture Low Register, offset: 0x8 */ + __I uint32_t CAPTURE_H; /**< Capture High Register, offset: 0xC */ + __IO uint32_t MATCH_L; /**< Match Low Register, offset: 0x10 */ + __IO uint32_t MATCH_H; /**< Match High Register, offset: 0x14 */ uint8_t RESERVED_0[4]; - __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register for CPUn, offset: 0x1C */ + __IO uint32_t OSEVENT_CTRL; /**< OS_EVENT TIMER Control Register, offset: 0x1C */ } OSTIMER_Type; /* ---------------------------------------------------------------------------- @@ -11523,54 +13621,96 @@ typedef struct { /*! @name EVTIMERL - EVTIMER Low Register */ /*! @{ */ + #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the 42-bits + * EVTIMER. Note: There is only one EVTIMER, readable from all domains. + */ #define OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERL_EVTIMER_COUNT_VALUE_MASK) /*! @} */ /*! @name EVTIMERH - EVTIMER High Register */ /*! @{ */ -#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0xFFFFFFFFU) + +#define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK (0x3FFU) #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT (0U) +/*! EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 10 bits of the 42-bits + * EVTIMER. Note there is only one EVTIMER, readable from all domains. + */ #define OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_SHIFT)) & OSTIMER_EVTIMERH_EVTIMER_COUNT_VALUE_MASK) /*! @} */ -/*! @name CAPTUREN_L - Local Capture Low Register for CPUn */ +/*! @name CAPTURE_L - Capture Low Register */ /*! @{ */ -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT (0U) -#define OSTIMER_CAPTUREN_L_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_L_CAPTUREn_VALUE_MASK) + +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_L_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_L_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_L_CAPTURE_VALUE_MASK) /*! @} */ -/*! @name CAPTUREN_H - Local Capture High Register for CPUn */ +/*! @name CAPTURE_H - Capture High Register */ /*! @{ */ -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT (0U) -#define OSTIMER_CAPTUREN_H_CAPTUREn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_SHIFT)) & OSTIMER_CAPTUREN_H_CAPTUREn_VALUE_MASK) + +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK (0x3FFU) +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT (0U) +/*! CAPTURE_VALUE - A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at + * the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). + */ +#define OSTIMER_CAPTURE_H_CAPTURE_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_CAPTURE_H_CAPTURE_VALUE_SHIFT)) & OSTIMER_CAPTURE_H_CAPTURE_VALUE_MASK) /*! @} */ -/*! @name MATCHN_L - Local Match Low Register for CPUn */ +/*! @name MATCH_L - Match Low Register */ /*! @{ */ -#define OSTIMER_MATCHN_L_MATCHn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT (0U) -#define OSTIMER_MATCHN_L_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_L_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_L_MATCHn_VALUE_MASK) + +#define OSTIMER_MATCH_L_MATCH_VALUE_MASK (0xFFFFFFFFU) +#define OSTIMER_MATCH_L_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written to the MATCH (L/H) register pair is compared against the central + * EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_L_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_L_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_L_MATCH_VALUE_MASK) /*! @} */ -/*! @name MATCHN_H - Match High Register for CPUn */ +/*! @name MATCH_H - Match High Register */ /*! @{ */ -#define OSTIMER_MATCHN_H_MATCHn_VALUE_MASK (0xFFFFFFFFU) -#define OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT (0U) -#define OSTIMER_MATCHN_H_MATCHn_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCHN_H_MATCHn_VALUE_SHIFT)) & OSTIMER_MATCHN_H_MATCHn_VALUE_MASK) + +#define OSTIMER_MATCH_H_MATCH_VALUE_MASK (0x3FFU) +#define OSTIMER_MATCH_H_MATCH_VALUE_SHIFT (0U) +/*! MATCH_VALUE - The value written (upper 10 bits) to the MATCH (L/H) register pair is compared + * against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. + */ +#define OSTIMER_MATCH_H_MATCH_VALUE(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_MATCH_H_MATCH_VALUE_SHIFT)) & OSTIMER_MATCH_H_MATCH_VALUE_MASK) /*! @} */ -/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register for CPUn */ +/*! @name OSEVENT_CTRL - OS_EVENT TIMER Control Register */ /*! @{ */ + #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK (0x1U) #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT (0U) +/*! OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 42-bits EVTIMER and + * the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes + * to clear this bit are asynchronous. It should be done before a new match value is written into + * the MATCH_L/H registers. + */ #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK) + #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK (0x2U) #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT (1U) +/*! OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the domain processor will + * be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests + * due to the OSTIMER_INTR flag are blocked. + */ #define OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_SHIFT)) & OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK) + +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK (0x4U) +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT (2U) +/*! MATCH_WR_RDY - This bit will be low when it is safe to write to reload the Match Registers. In + * typical applications it should not be necessary to test this bit. [1] + */ +#define OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY(x) (((uint32_t)(((uint32_t)(x)) << OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_SHIFT)) & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK) /*! @} */ @@ -11580,7 +13720,7 @@ typedef struct { /* OSTIMER - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral OSTIMER base address */ #define OSTIMER_BASE (0x5002D000u) /** Peripheral OSTIMER base address */ @@ -11652,76 +13792,131 @@ typedef struct { /*! @name ISEL - Pin Interrupt Mode register */ /*! @{ */ + #define PINT_ISEL_PMODE_MASK (0xFFU) #define PINT_ISEL_PMODE_SHIFT (0U) +/*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt + * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive + */ #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) /*! @} */ /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ /*! @{ */ + #define PINT_IENR_ENRL_MASK (0xFFU) #define PINT_IENR_ENRL_SHIFT (0U) +/*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the + * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable + * rising edge or level interrupt. + */ #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) /*! @} */ /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ /*! @{ */ + #define PINT_SIENR_SETENRL_MASK (0xFFU) #define PINT_SIENR_SETENRL_SHIFT (0U) +/*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n + * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. + */ #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) /*! @} */ /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ /*! @{ */ + #define PINT_CIENR_CENRL_MASK (0xFFU) #define PINT_CIENR_CENRL_SHIFT (0U) +/*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit + * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level + * interrupt. + */ #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) /*! @} */ /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ /*! @{ */ + #define PINT_IENF_ENAF_MASK (0xFFU) #define PINT_IENF_ENAF_SHIFT (0U) +/*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. + * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt + * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active + * interrupt level HIGH. + */ #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) /*! @} */ /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ /*! @{ */ + #define PINT_SIENF_SETENAF_MASK (0xFFU) #define PINT_SIENF_SETENAF_SHIFT (0U) +/*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n + * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable + * falling edge interrupt. + */ #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) /*! @} */ /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ /*! @{ */ + #define PINT_CIENF_CENAF_MASK (0xFFU) #define PINT_CIENF_CENAF_SHIFT (0U) +/*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n + * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or + * falling edge interrupt disabled. + */ #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) /*! @} */ /*! @name RISE - Pin interrupt rising edge register */ /*! @{ */ + #define PINT_RISE_RDET_MASK (0xFFU) #define PINT_RISE_RDET_SHIFT (0U) +/*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read + * 0: No rising edge has been detected on this pin since Reset or the last time a one was written + * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the + * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. + */ #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) /*! @} */ /*! @name FALL - Pin interrupt falling edge register */ /*! @{ */ + #define PINT_FALL_FDET_MASK (0xFFU) #define PINT_FALL_FDET_SHIFT (0U) +/*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read + * 0: No falling edge has been detected on this pin since Reset or the last time a one was + * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or + * the last time a one was written to this bit. Write 1: clear falling edge detection for this + * pin. + */ #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) /*! @} */ /*! @name IST - Pin interrupt status register */ /*! @{ */ + #define PINT_IST_PSTAT_MASK (0xFFU) #define PINT_IST_PSTAT_SHIFT (0U) +/*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts + * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for + * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this + * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. + * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). + */ #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) /*! @} */ /*! @name PMCTRL - Pattern match interrupt control register */ /*! @{ */ + #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) /*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. @@ -11729,6 +13924,7 @@ typedef struct { * 0b1..Pattern match. Interrupts are driven in response to pattern matches. */ #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) + #define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) #define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) /*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. @@ -11736,13 +13932,19 @@ typedef struct { * 0b1..Enabled. RXEV output to the CPU is enabled. */ #define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) + #define PINT_PMCTRL_PMAT_MASK (0xFF000000U) #define PINT_PMCTRL_PMAT_SHIFT (24U) +/*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field + * indicates that the corresponding product term is matched by the current state of the appropriate + * inputs. + */ #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) /*! @} */ /*! @name PMSRC - Pattern match interrupt bit-slice source register */ /*! @{ */ + #define PINT_PMSRC_SRC0_MASK (0x700U) #define PINT_PMSRC_SRC0_SHIFT (8U) /*! SRC0 - Selects the input source for bit slice 0 @@ -11756,6 +13958,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. */ #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) + #define PINT_PMSRC_SRC1_MASK (0x3800U) #define PINT_PMSRC_SRC1_SHIFT (11U) /*! SRC1 - Selects the input source for bit slice 1 @@ -11769,6 +13972,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. */ #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) + #define PINT_PMSRC_SRC2_MASK (0x1C000U) #define PINT_PMSRC_SRC2_SHIFT (14U) /*! SRC2 - Selects the input source for bit slice 2 @@ -11782,6 +13986,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. */ #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) + #define PINT_PMSRC_SRC3_MASK (0xE0000U) #define PINT_PMSRC_SRC3_SHIFT (17U) /*! SRC3 - Selects the input source for bit slice 3 @@ -11795,6 +14000,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. */ #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) + #define PINT_PMSRC_SRC4_MASK (0x700000U) #define PINT_PMSRC_SRC4_SHIFT (20U) /*! SRC4 - Selects the input source for bit slice 4 @@ -11808,6 +14014,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. */ #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) + #define PINT_PMSRC_SRC5_MASK (0x3800000U) #define PINT_PMSRC_SRC5_SHIFT (23U) /*! SRC5 - Selects the input source for bit slice 5 @@ -11821,6 +14028,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. */ #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) + #define PINT_PMSRC_SRC6_MASK (0x1C000000U) #define PINT_PMSRC_SRC6_SHIFT (26U) /*! SRC6 - Selects the input source for bit slice 6 @@ -11834,6 +14042,7 @@ typedef struct { * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. */ #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) + #define PINT_PMSRC_SRC7_MASK (0xE0000000U) #define PINT_PMSRC_SRC7_SHIFT (29U) /*! SRC7 - Selects the input source for bit slice 7 @@ -11851,6 +14060,7 @@ typedef struct { /*! @name PMCFG - Pattern match interrupt bit slice configuration register */ /*! @{ */ + #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) /*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. @@ -11858,6 +14068,7 @@ typedef struct { * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) + #define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) #define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) /*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. @@ -11865,6 +14076,7 @@ typedef struct { * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) + #define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) #define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) /*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. @@ -11872,6 +14084,7 @@ typedef struct { * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) + #define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) #define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) /*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. @@ -11879,6 +14092,7 @@ typedef struct { * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) + #define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) #define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) /*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. @@ -11886,6 +14100,7 @@ typedef struct { * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) + #define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) #define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) /*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. @@ -11893,6 +14108,7 @@ typedef struct { * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) + #define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) #define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) /*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. @@ -11900,6 +14116,7 @@ typedef struct { * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. */ #define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) + #define PINT_PMCFG_CFG0_MASK (0x700U) #define PINT_PMCFG_CFG0_SHIFT (8U) /*! CFG0 - Specifies the match contribution condition for bit slice 0. @@ -11921,6 +14138,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) + #define PINT_PMCFG_CFG1_MASK (0x3800U) #define PINT_PMCFG_CFG1_SHIFT (11U) /*! CFG1 - Specifies the match contribution condition for bit slice 1. @@ -11942,6 +14160,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) + #define PINT_PMCFG_CFG2_MASK (0x1C000U) #define PINT_PMCFG_CFG2_SHIFT (14U) /*! CFG2 - Specifies the match contribution condition for bit slice 2. @@ -11963,6 +14182,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) + #define PINT_PMCFG_CFG3_MASK (0xE0000U) #define PINT_PMCFG_CFG3_SHIFT (17U) /*! CFG3 - Specifies the match contribution condition for bit slice 3. @@ -11984,6 +14204,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) + #define PINT_PMCFG_CFG4_MASK (0x700000U) #define PINT_PMCFG_CFG4_SHIFT (20U) /*! CFG4 - Specifies the match contribution condition for bit slice 4. @@ -12005,6 +14226,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) + #define PINT_PMCFG_CFG5_MASK (0x3800000U) #define PINT_PMCFG_CFG5_SHIFT (23U) /*! CFG5 - Specifies the match contribution condition for bit slice 5. @@ -12026,6 +14248,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) + #define PINT_PMCFG_CFG6_MASK (0x1C000000U) #define PINT_PMCFG_CFG6_SHIFT (26U) /*! CFG6 - Specifies the match contribution condition for bit slice 6. @@ -12047,6 +14270,7 @@ typedef struct { * is cleared after one clock cycle. */ #define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) + #define PINT_PMCFG_CFG7_MASK (0xE0000000U) #define PINT_PMCFG_CFG7_SHIFT (29U) /*! CFG7 - Specifies the match contribution condition for bit slice 7. @@ -12077,7 +14301,7 @@ typedef struct { /* PINT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral PINT base address */ #define PINT_BASE (0x50004000u) /** Peripheral PINT base address */ @@ -12136,14 +14360,14 @@ typedef struct { /** PLU - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x20 */ - __IO uint32_t INP[5]; /**< LUT0 input 0 MUX..LUT25 input 4 MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ + __IO uint32_t INP_MUX[5]; /**< LUTn input x MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ uint8_t RESERVED_0[12]; } LUT[26]; uint8_t RESERVED_0[1216]; __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ uint8_t RESERVED_1[152]; __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ - __IO uint32_t WAKEINT; /**< Wakeup interrupt control for PLU, offset: 0x904 */ + __IO uint32_t WAKEINT_CTRL; /**< Wakeup interrupt control for PLU, offset: 0x904 */ uint8_t RESERVED_2[760]; __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ } PLU_Type; @@ -12157,18 +14381,20 @@ typedef struct { * @{ */ -/*! @name LUT_INP - LUT0 input 0 MUX..LUT25 input 4 MUX */ +/*! @name LUT_INP_MUX - LUTn input x MUX */ /*! @{ */ -#define PLU_LUT_INP_LUT_INP_MASK (0x3FU) -#define PLU_LUT_INP_LUT_INP_SHIFT (0U) -/*! LUT_INP - Selects the input source to be connected to LUT25 input4. + +#define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) +#define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) +/*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot + * associated with the output from LUTn itself is tied low. * 0b000000..The PLU primary inputs 0. * 0b000001..The PLU primary inputs 1. * 0b000010..The PLU primary inputs 2. * 0b000011..The PLU primary inputs 3. * 0b000100..The PLU primary inputs 4. * 0b000101..The PLU primary inputs 5. - * 0b000110..Tie low. + * 0b000110..The output of LUT0. * 0b000111..The output of LUT1. * 0b001000..The output of LUT2. * 0b001001..The output of LUT3. @@ -12199,59 +14425,83 @@ typedef struct { * 0b100010..state(2). * 0b100011..state(3). */ -#define PLU_LUT_INP_LUT_INP(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_LUT_INP_SHIFT)) & PLU_LUT_INP_LUT_INP_MASK) +#define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) /*! @} */ -/* The count of PLU_LUT_INP */ -#define PLU_LUT_INP_COUNT (26U) +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT (26U) -/* The count of PLU_LUT_INP */ -#define PLU_LUT_INP_COUNT2 (5U) +/* The count of PLU_LUT_INP_MUX */ +#define PLU_LUT_INP_MUX_COUNT2 (5U) -/*! @name LUT_T_LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ +/*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ /*! @{ */ -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK (0xFFFFFFFFU) -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT (0U) -#define PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_SHIFT)) & PLU_LUT_T_LUT_TRUTH_TRUTH_TABLE_MASK) + +#define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) +#define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) +/*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. + */ +#define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) /*! @} */ -/* The count of PLU_LUT_T_LUT_TRUTH */ -#define PLU_LUT_T_LUT_TRUTH_COUNT (26U) +/* The count of PLU_LUT_TRUTH */ +#define PLU_LUT_TRUTH_COUNT (26U) /*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ /*! @{ */ + #define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) #define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) +/*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. + */ #define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) /*! @} */ -/*! @name WAKEINT - Wakeup interrupt control for PLU */ +/*! @name WAKEINT_CTRL - Wakeup interrupt control for PLU */ /*! @{ */ -#define PLU_WAKEINT_MASK_MASK (0xFFU) -#define PLU_WAKEINT_MASK_SHIFT (0U) -#define PLU_WAKEINT_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_MASK_SHIFT)) & PLU_WAKEINT_MASK_MASK) -#define PLU_WAKEINT_FILTER_MODE_MASK (0x300U) -#define PLU_WAKEINT_FILTER_MODE_SHIFT (8U) -/*! FILTER_MODE - control input of the PLU, add filtering for glitch + +#define PLU_WAKEINT_CTRL_MASK_MASK (0xFFU) +#define PLU_WAKEINT_CTRL_MASK_SHIFT (0U) +/*! MASK - Interrupt mask (which of the 8 PLU Outputs contribute to interrupt) + */ +#define PLU_WAKEINT_CTRL_MASK(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_MASK_SHIFT)) & PLU_WAKEINT_CTRL_MASK_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_MODE_MASK (0x300U) +#define PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT (8U) +/*! FILTER_MODE - control input of the PLU, add filtering for glitch. * 0b00..Bypass mode. * 0b01..Filter 1 clock period. * 0b10..Filter 2 clock period. * 0b11..Filter 3 clock period. */ -#define PLU_WAKEINT_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_MODE_SHIFT)) & PLU_WAKEINT_FILTER_MODE_MASK) -#define PLU_WAKEINT_FILTER_CLKSEL_MASK (0xC00U) -#define PLU_WAKEINT_FILTER_CLKSEL_SHIFT (10U) -#define PLU_WAKEINT_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_FILTER_CLKSEL_MASK) -#define PLU_WAKEINT_LATCH_ENABLE_MASK (0x1000U) -#define PLU_WAKEINT_LATCH_ENABLE_SHIFT (12U) -#define PLU_WAKEINT_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_LATCH_ENABLE_MASK) -#define PLU_WAKEINT_INTR_CLEAR_MASK (0x2000U) -#define PLU_WAKEINT_INTR_CLEAR_SHIFT (13U) -#define PLU_WAKEINT_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_INTR_CLEAR_MASK) +#define PLU_WAKEINT_CTRL_FILTER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_MODE_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_MODE_MASK) + +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK (0xC00U) +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT (10U) +/*! FILTER_CLKSEL - hclk is divided by 2**filter_clksel. + * 0b00..Selects the 1 MHz low-power oscillator as the filter clock. + * 0b01..Selects the 12 Mhz FRO as the filter clock. + * 0b10..Selects a third filter clock source, if provided. + * 0b11..Reserved. + */ +#define PLU_WAKEINT_CTRL_FILTER_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_FILTER_CLKSEL_SHIFT)) & PLU_WAKEINT_CTRL_FILTER_CLKSEL_MASK) + +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK (0x1000U) +#define PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT (12U) +/*! LATCH_ENABLE - latch the interrupt , then can be cleared with next bit INTR_CLEAR + */ +#define PLU_WAKEINT_CTRL_LATCH_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_LATCH_ENABLE_SHIFT)) & PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK) + +#define PLU_WAKEINT_CTRL_INTR_CLEAR_MASK (0x2000U) +#define PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT (13U) +/*! INTR_CLEAR - Write to clear wakeint_latched + */ +#define PLU_WAKEINT_CTRL_INTR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << PLU_WAKEINT_CTRL_INTR_CLEAR_SHIFT)) & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK) /*! @} */ /*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ /*! @{ */ + #define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) #define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) /*! OUTPUTn - Selects the source to be connected to PLU Output 7. @@ -12299,7 +14549,7 @@ typedef struct { /* PLU - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral PLU base address */ #define PLU_BASE (0x5003D000u) /** Peripheral PLU base address */ @@ -12343,35 +14593,41 @@ typedef struct { /** PMC - Register Layout Typedef */ typedef struct { - uint8_t RESERVED_0[8]; + uint8_t RESERVED_0[4]; + __I uint32_t STATUS; /**< Power Management Controller FSM (Finite State Machines) status, offset: 0x4 */ __IO uint32_t RESETCTRL; /**< Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x8 */ - __IO uint32_t RESETCAUSE; /**< Reset Cause register [Reset by: PoR], offset: 0xC */ - uint8_t RESERVED_1[32]; - __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ + uint8_t RESERVED_1[4]; + __IO uint32_t DCDC0; /**< DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x10 */ + __IO uint32_t DCDC1; /**< DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x14 */ uint8_t RESERVED_2[4]; - __IO uint32_t BODCORE; /**< Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x38 */ - uint8_t RESERVED_3[8]; - __IO uint32_t FRO1M; /**< 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x44 */ - __IO uint32_t FRO32K; /**< 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x48 */ + __IO uint32_t LDOPMU; /**< Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x1C */ + uint8_t RESERVED_3[16]; + __IO uint32_t BODVBAT; /**< VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset], offset: 0x30 */ + uint8_t RESERVED_4[12]; + __IO uint32_t REFFASTWKUP; /**< Analog References fast wake-up Control register [Reset by: PoR], offset: 0x40 */ + uint8_t RESERVED_5[8]; __IO uint32_t XTAL32K; /**< 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x4C */ __IO uint32_t COMP; /**< Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x50 */ - uint8_t RESERVED_4[20]; + uint8_t RESERVED_6[16]; + __IO uint32_t WAKEUPIOCTRL; /**< Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset], offset: 0x64 */ __IO uint32_t WAKEIOCAUSE; /**< Allows to identify the Wake-up I/O source from Deep Power Down mode, offset: 0x68 */ - uint8_t RESERVED_5[8]; + uint8_t RESERVED_7[8]; __IO uint32_t STATUSCLK; /**< FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x74 */ - uint8_t RESERVED_6[12]; + uint8_t RESERVED_8[12]; __IO uint32_t AOREG1; /**< General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset], offset: 0x84 */ - uint8_t RESERVED_7[16]; + uint8_t RESERVED_9[8]; + __IO uint32_t MISCCTRL; /**< Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0x90 */ + uint8_t RESERVED_10[4]; __IO uint32_t RTCOSC32K; /**< RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x98 */ __IO uint32_t OSTIMERr; /**< OS Timer control register [Reset by: PoR, Brown Out Detectors Reset], offset: 0x9C */ - uint8_t RESERVED_8[16]; - __IO uint32_t PDSLEEPCFG0; /**< Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xB0 */ - uint8_t RESERVED_9[4]; + uint8_t RESERVED_11[24]; __IO uint32_t PDRUNCFG0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xB8 */ - uint8_t RESERVED_10[4]; + uint8_t RESERVED_12[4]; __O uint32_t PDRUNCFGSET0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC0 */ - uint8_t RESERVED_11[4]; + uint8_t RESERVED_13[4]; __O uint32_t PDRUNCFGCLR0; /**< Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset], offset: 0xC8 */ + uint8_t RESERVED_14[8]; + __IO uint32_t SRAMCTRL; /**< All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset], offset: 0xD4 */ } PMC_Type; /* ---------------------------------------------------------------------------- @@ -12383,8 +14639,23 @@ typedef struct { * @{ */ +/*! @name STATUS - Power Management Controller FSM (Finite State Machines) status */ +/*! @{ */ + +#define PMC_STATUS_BOOTMODE_MASK (0xC0000U) +#define PMC_STATUS_BOOTMODE_SHIFT (18U) +/*! BOOTMODE - Latest IC Boot cause:. + * 0b00..Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). + * 0b01..Latest IC boot was from DEEP SLEEP low power mode. + * 0b10..Latest IC boot was from POWER DOWN low power mode. + * 0b11..Latest IC boot was from DEEP POWER DOWN low power mode. + */ +#define PMC_STATUS_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUS_BOOTMODE_SHIFT)) & PMC_STATUS_BOOTMODE_MASK) +/*! @} */ + /*! @name RESETCTRL - Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ + #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK (0x1U) #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT (0U) /*! DPDWAKEUPRESETENABLE - Wake-up from DEEP POWER DOWN reset event (either from wake up I/O or RTC or OS Event Timer). @@ -12392,6 +14663,7 @@ typedef struct { * 0b1..Reset event from DEEP POWER DOWN mode is enable. */ #define PMC_RESETCTRL_DPDWAKEUPRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_DPDWAKEUPRESETENABLE_SHIFT)) & PMC_RESETCTRL_DPDWAKEUPRESETENABLE_MASK) + #define PMC_RESETCTRL_BODVBATRESETENABLE_MASK (0x2U) #define PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT (1U) /*! BODVBATRESETENABLE - BOD VBAT reset enable. @@ -12399,6 +14671,7 @@ typedef struct { * 0b1..BOD VBAT reset is enable. */ #define PMC_RESETCTRL_BODVBATRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODVBATRESETENABLE_SHIFT)) & PMC_RESETCTRL_BODVBATRESETENABLE_MASK) + #define PMC_RESETCTRL_BODCORERESETENABLE_MASK (0x4U) #define PMC_RESETCTRL_BODCORERESETENABLE_SHIFT (2U) /*! BODCORERESETENABLE - BOD CORE reset enable. @@ -12406,6 +14679,7 @@ typedef struct { * 0b1..BOD CORE reset is enable. */ #define PMC_RESETCTRL_BODCORERESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_BODCORERESETENABLE_SHIFT)) & PMC_RESETCTRL_BODCORERESETENABLE_MASK) + #define PMC_RESETCTRL_SWRRESETENABLE_MASK (0x8U) #define PMC_RESETCTRL_SWRRESETENABLE_SHIFT (3U) /*! SWRRESETENABLE - Software reset enable. @@ -12415,39 +14689,242 @@ typedef struct { #define PMC_RESETCTRL_SWRRESETENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCTRL_SWRRESETENABLE_SHIFT)) & PMC_RESETCTRL_SWRRESETENABLE_MASK) /*! @} */ -/*! @name RESETCAUSE - Reset Cause register [Reset by: PoR] */ +/*! @name DCDC0 - DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ -#define PMC_RESETCAUSE_POR_MASK (0x1U) -#define PMC_RESETCAUSE_POR_SHIFT (0U) -#define PMC_RESETCAUSE_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_POR_SHIFT)) & PMC_RESETCAUSE_POR_MASK) -#define PMC_RESETCAUSE_PADRESET_MASK (0x2U) -#define PMC_RESETCAUSE_PADRESET_SHIFT (1U) -#define PMC_RESETCAUSE_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_PADRESET_SHIFT)) & PMC_RESETCAUSE_PADRESET_MASK) -#define PMC_RESETCAUSE_BODRESET_MASK (0x4U) -#define PMC_RESETCAUSE_BODRESET_SHIFT (2U) -#define PMC_RESETCAUSE_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_BODRESET_SHIFT)) & PMC_RESETCAUSE_BODRESET_MASK) -#define PMC_RESETCAUSE_SYSTEMRESET_MASK (0x8U) -#define PMC_RESETCAUSE_SYSTEMRESET_SHIFT (3U) -#define PMC_RESETCAUSE_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SYSTEMRESET_SHIFT)) & PMC_RESETCAUSE_SYSTEMRESET_MASK) -#define PMC_RESETCAUSE_WDTRESET_MASK (0x10U) -#define PMC_RESETCAUSE_WDTRESET_SHIFT (4U) -#define PMC_RESETCAUSE_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_WDTRESET_SHIFT)) & PMC_RESETCAUSE_WDTRESET_MASK) -#define PMC_RESETCAUSE_SWRRESET_MASK (0x20U) -#define PMC_RESETCAUSE_SWRRESET_SHIFT (5U) -#define PMC_RESETCAUSE_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_SWRRESET_SHIFT)) & PMC_RESETCAUSE_SWRRESET_MASK) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK (0x40U) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT (6U) -#define PMC_RESETCAUSE_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_WAKEUPIO_SHIFT)) & PMC_RESETCAUSE_DPDRESET_WAKEUPIO_MASK) -#define PMC_RESETCAUSE_DPDRESET_RTC_MASK (0x80U) -#define PMC_RESETCAUSE_DPDRESET_RTC_SHIFT (7U) -#define PMC_RESETCAUSE_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_RTC_SHIFT)) & PMC_RESETCAUSE_DPDRESET_RTC_MASK) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK (0x100U) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT (8U) -#define PMC_RESETCAUSE_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_RESETCAUSE_DPDRESET_OSTIMER_SHIFT)) & PMC_RESETCAUSE_DPDRESET_OSTIMER_MASK) + +#define PMC_DCDC0_RC_MASK (0x3FU) +#define PMC_DCDC0_RC_SHIFT (0U) +/*! RC - Constant On-Time calibration. + */ +#define PMC_DCDC0_RC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_RC_SHIFT)) & PMC_DCDC0_RC_MASK) + +#define PMC_DCDC0_ICOMP_MASK (0xC0U) +#define PMC_DCDC0_ICOMP_SHIFT (6U) +/*! ICOMP - Select the type of ZCD comparator. + */ +#define PMC_DCDC0_ICOMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICOMP_SHIFT)) & PMC_DCDC0_ICOMP_MASK) + +#define PMC_DCDC0_ISEL_MASK (0x300U) +#define PMC_DCDC0_ISEL_SHIFT (8U) +/*! ISEL - Alter Internal biasing currents. + */ +#define PMC_DCDC0_ISEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ISEL_SHIFT)) & PMC_DCDC0_ISEL_MASK) + +#define PMC_DCDC0_ICENABLE_MASK (0x400U) +#define PMC_DCDC0_ICENABLE_SHIFT (10U) +/*! ICENABLE - Selection of auto scaling of COT period with variations in VDD. + */ +#define PMC_DCDC0_ICENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_ICENABLE_SHIFT)) & PMC_DCDC0_ICENABLE_MASK) + +#define PMC_DCDC0_TMOS_MASK (0xF800U) +#define PMC_DCDC0_TMOS_SHIFT (11U) +/*! TMOS - One-shot generator reference current trimming signal. + */ +#define PMC_DCDC0_TMOS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_TMOS_SHIFT)) & PMC_DCDC0_TMOS_MASK) + +#define PMC_DCDC0_DISABLEISENSE_MASK (0x10000U) +#define PMC_DCDC0_DISABLEISENSE_SHIFT (16U) +/*! DISABLEISENSE - Disable Current sensing. + */ +#define PMC_DCDC0_DISABLEISENSE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_DISABLEISENSE_SHIFT)) & PMC_DCDC0_DISABLEISENSE_MASK) + +#define PMC_DCDC0_VOUT_MASK (0x1E0000U) +#define PMC_DCDC0_VOUT_SHIFT (17U) +/*! VOUT - Set output regulation voltage. + * 0b0000..0.95 V. + * 0b0001..0.975 V. + * 0b0010..1 V. + * 0b0011..1.025 V. + * 0b0100..1.05 V. + * 0b0101..1.075 V. + * 0b0110..1.1 V. + * 0b0111..1.125 V. + * 0b1000..1.15 V. + * 0b1001..1.175 V. + * 0b1010..1.2 V. + */ +#define PMC_DCDC0_VOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_SHIFT)) & PMC_DCDC0_VOUT_MASK) + +#define PMC_DCDC0_SLICINGENABLE_MASK (0x200000U) +#define PMC_DCDC0_SLICINGENABLE_SHIFT (21U) +/*! SLICINGENABLE - Enable staggered switching of power switches. + */ +#define PMC_DCDC0_SLICINGENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_SLICINGENABLE_SHIFT)) & PMC_DCDC0_SLICINGENABLE_MASK) + +#define PMC_DCDC0_INDUCTORCLAMPENABLE_MASK (0x400000U) +#define PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT (22U) +/*! INDUCTORCLAMPENABLE - Enable shorting of Inductor during PFM idle time. + */ +#define PMC_DCDC0_INDUCTORCLAMPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_INDUCTORCLAMPENABLE_SHIFT)) & PMC_DCDC0_INDUCTORCLAMPENABLE_MASK) + +#define PMC_DCDC0_VOUT_PWD_MASK (0x7800000U) +#define PMC_DCDC0_VOUT_PWD_SHIFT (23U) +/*! VOUT_PWD - Set output regulation voltage during Deep Sleep. + */ +#define PMC_DCDC0_VOUT_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC0_VOUT_PWD_SHIFT)) & PMC_DCDC0_VOUT_PWD_MASK) +/*! @} */ + +/*! @name DCDC1 - DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_DCDC1_RTRIMOFFET_MASK (0xFU) +#define PMC_DCDC1_RTRIMOFFET_SHIFT (0U) +/*! RTRIMOFFET - Adjust the offset voltage of BJT based comparator. + */ +#define PMC_DCDC1_RTRIMOFFET(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RTRIMOFFET_SHIFT)) & PMC_DCDC1_RTRIMOFFET_MASK) + +#define PMC_DCDC1_RSENSETRIM_MASK (0xF0U) +#define PMC_DCDC1_RSENSETRIM_SHIFT (4U) +/*! RSENSETRIM - Adjust Max inductor peak current limiting. + */ +#define PMC_DCDC1_RSENSETRIM(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_RSENSETRIM_SHIFT)) & PMC_DCDC1_RSENSETRIM_MASK) + +#define PMC_DCDC1_DTESTENABLE_MASK (0x100U) +#define PMC_DCDC1_DTESTENABLE_SHIFT (8U) +/*! DTESTENABLE - Enable Digital test signals. + */ +#define PMC_DCDC1_DTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTENABLE_SHIFT)) & PMC_DCDC1_DTESTENABLE_MASK) + +#define PMC_DCDC1_SETCURVE_MASK (0x600U) +#define PMC_DCDC1_SETCURVE_SHIFT (9U) +/*! SETCURVE - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETCURVE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETCURVE_SHIFT)) & PMC_DCDC1_SETCURVE_MASK) + +#define PMC_DCDC1_SETDC_MASK (0x7800U) +#define PMC_DCDC1_SETDC_SHIFT (11U) +/*! SETDC - Bandgap calibration parameter. + */ +#define PMC_DCDC1_SETDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_SETDC_SHIFT)) & PMC_DCDC1_SETDC_MASK) + +#define PMC_DCDC1_DTESTSEL_MASK (0x38000U) +#define PMC_DCDC1_DTESTSEL_SHIFT (15U) +/*! DTESTSEL - Select the output signal for test. + */ +#define PMC_DCDC1_DTESTSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_DTESTSEL_SHIFT)) & PMC_DCDC1_DTESTSEL_MASK) + +#define PMC_DCDC1_ISCALEENABLE_MASK (0x40000U) +#define PMC_DCDC1_ISCALEENABLE_SHIFT (18U) +/*! ISCALEENABLE - Modify COT behavior. + */ +#define PMC_DCDC1_ISCALEENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_ISCALEENABLE_SHIFT)) & PMC_DCDC1_ISCALEENABLE_MASK) + +#define PMC_DCDC1_FORCEBYPASS_MASK (0x80000U) +#define PMC_DCDC1_FORCEBYPASS_SHIFT (19U) +/*! FORCEBYPASS - Force bypass mode. + */ +#define PMC_DCDC1_FORCEBYPASS(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEBYPASS_SHIFT)) & PMC_DCDC1_FORCEBYPASS_MASK) + +#define PMC_DCDC1_TRIMAUTOCOT_MASK (0xF00000U) +#define PMC_DCDC1_TRIMAUTOCOT_SHIFT (20U) +/*! TRIMAUTOCOT - Change the scaling ratio of the feedforward compensation. + */ +#define PMC_DCDC1_TRIMAUTOCOT(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TRIMAUTOCOT_SHIFT)) & PMC_DCDC1_TRIMAUTOCOT_MASK) + +#define PMC_DCDC1_FORCEFULLCYCLE_MASK (0x1000000U) +#define PMC_DCDC1_FORCEFULLCYCLE_SHIFT (24U) +/*! FORCEFULLCYCLE - Force full PFM PMOS and NMOS cycle. + */ +#define PMC_DCDC1_FORCEFULLCYCLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_FORCEFULLCYCLE_SHIFT)) & PMC_DCDC1_FORCEFULLCYCLE_MASK) + +#define PMC_DCDC1_LCENABLE_MASK (0x2000000U) +#define PMC_DCDC1_LCENABLE_SHIFT (25U) +/*! LCENABLE - Change the range of the peak detector of current inside the inductor. + */ +#define PMC_DCDC1_LCENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_LCENABLE_SHIFT)) & PMC_DCDC1_LCENABLE_MASK) + +#define PMC_DCDC1_TOFF_MASK (0x7C000000U) +#define PMC_DCDC1_TOFF_SHIFT (26U) +/*! TOFF - Constant Off-Time calibration input. + */ +#define PMC_DCDC1_TOFF(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFF_SHIFT)) & PMC_DCDC1_TOFF_MASK) + +#define PMC_DCDC1_TOFFENABLE_MASK (0x80000000U) +#define PMC_DCDC1_TOFFENABLE_SHIFT (31U) +/*! TOFFENABLE - Enable Constant Off-Time feature. + */ +#define PMC_DCDC1_TOFFENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_DCDC1_TOFFENABLE_SHIFT)) & PMC_DCDC1_TOFFENABLE_MASK) +/*! @} */ + +/*! @name LDOPMU - Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_LDOPMU_VADJ_MASK (0x1FU) +#define PMC_LDOPMU_VADJ_SHIFT (0U) +/*! VADJ - Sets the Always-On domain LDO output level. + * 0b00000..1.22 V. + * 0b00001..0.7 V. + * 0b00010..0.725 V. + * 0b00011..0.75 V. + * 0b00100..0.775 V. + * 0b00101..0.8 V. + * 0b00110..0.825 V. + * 0b00111..0.85 V. + * 0b01000..0.875 V. + * 0b01001..0.9 V. + * 0b01010..0.96 V. + * 0b01011..0.97 V. + * 0b01100..0.98 V. + * 0b01101..0.99 V. + * 0b01110..1 V. + * 0b01111..1.01 V. + * 0b10000..1.02 V. + * 0b10001..1.03 V. + * 0b10010..1.04 V. + * 0b10011..1.05 V. + * 0b10100..1.06 V. + * 0b10101..1.07 V. + * 0b10110..1.08 V. + * 0b10111..1.09 V. + * 0b11000..1.1 V. + * 0b11001..1.11 V. + * 0b11010..1.12 V. + * 0b11011..1.13 V. + * 0b11100..1.14 V. + * 0b11101..1.15 V. + * 0b11110..1.16 V. + * 0b11111..1.22 V. + */ +#define PMC_LDOPMU_VADJ(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_SHIFT)) & PMC_LDOPMU_VADJ_MASK) + +#define PMC_LDOPMU_VADJ_PWD_MASK (0x3E0U) +#define PMC_LDOPMU_VADJ_PWD_SHIFT (5U) +/*! VADJ_PWD - Sets the Always-On domain LDO output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_PWD_SHIFT)) & PMC_LDOPMU_VADJ_PWD_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_MASK (0x7C00U) +#define PMC_LDOPMU_VADJ_BOOST_SHIFT (10U) +/*! VADJ_BOOST - Sets the Always-On domain LDO Boost output level. + */ +#define PMC_LDOPMU_VADJ_BOOST(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_MASK) + +#define PMC_LDOPMU_VADJ_BOOST_PWD_MASK (0xF8000U) +#define PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT (15U) +/*! VADJ_BOOST_PWD - Sets the Always-On domain LDO Boost output level in all power down modes. + */ +#define PMC_LDOPMU_VADJ_BOOST_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_VADJ_BOOST_PWD_SHIFT)) & PMC_LDOPMU_VADJ_BOOST_PWD_MASK) + +#define PMC_LDOPMU_BOOST_ENA_MASK (0x1000000U) +#define PMC_LDOPMU_BOOST_ENA_SHIFT (24U) +/*! BOOST_ENA - Control the LDO AO boost mode in ACTIVE mode. + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_SHIFT)) & PMC_LDOPMU_BOOST_ENA_MASK) + +#define PMC_LDOPMU_BOOST_ENA_PWD_MASK (0x2000000U) +#define PMC_LDOPMU_BOOST_ENA_PWD_SHIFT (25U) +/*! BOOST_ENA_PWD - Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). + * 0b0..LDO AO Boost Mode is disable. + * 0b1..LDO AO Boost Mode is enable. + */ +#define PMC_LDOPMU_BOOST_ENA_PWD(x) (((uint32_t)(((uint32_t)(x)) << PMC_LDOPMU_BOOST_ENA_PWD_SHIFT)) & PMC_LDOPMU_BOOST_ENA_PWD_MASK) /*! @} */ /*! @name BODVBAT - VBAT Brown Out Dectector (BoD) control register [Reset by: PoR, Pin Reset, Software Reset] */ /*! @{ */ + #define PMC_BODVBAT_TRIGLVL_MASK (0x1FU) #define PMC_BODVBAT_TRIGLVL_SHIFT (0U) /*! TRIGLVL - BoD trigger level. @@ -12485,6 +14962,7 @@ typedef struct { * 0b11111..3.30 V. */ #define PMC_BODVBAT_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_TRIGLVL_SHIFT)) & PMC_BODVBAT_TRIGLVL_MASK) + #define PMC_BODVBAT_HYST_MASK (0x60U) #define PMC_BODVBAT_HYST_SHIFT (5U) /*! HYST - BoD Hysteresis control. @@ -12496,115 +14974,65 @@ typedef struct { #define PMC_BODVBAT_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODVBAT_HYST_SHIFT)) & PMC_BODVBAT_HYST_MASK) /*! @} */ -/*! @name BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @name REFFASTWKUP - Analog References fast wake-up Control register [Reset by: PoR] */ /*! @{ */ -#define PMC_BODCORE_TRIGLVL_MASK (0x7U) -#define PMC_BODCORE_TRIGLVL_SHIFT (0U) -/*! TRIGLVL - BoD trigger level. - * 0b000..0.60 V. - * 0b001..0.65 V. - * 0b010..0.70 V. - * 0b011..0.75 V. - * 0b100..0.80 V. - * 0b101..0.85 V. - * 0b110..0.90 V. - * 0b111..0.95 V. - */ -#define PMC_BODCORE_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_TRIGLVL_SHIFT)) & PMC_BODCORE_TRIGLVL_MASK) -#define PMC_BODCORE_HYST_MASK (0x30U) -#define PMC_BODCORE_HYST_SHIFT (4U) -/*! HYST - BoD Core Hysteresis control. - * 0b00..25 mV. - * 0b01..50 mV. - * 0b10..75 mV. - * 0b11..100 mV. - */ -#define PMC_BODCORE_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_BODCORE_HYST_SHIFT)) & PMC_BODCORE_HYST_MASK) -/*! @} */ -/*! @name FRO1M - 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ -/*! @{ */ -#define PMC_FRO1M_FREQSEL_MASK (0x7FU) -#define PMC_FRO1M_FREQSEL_SHIFT (0U) -#define PMC_FRO1M_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_FREQSEL_SHIFT)) & PMC_FRO1M_FREQSEL_MASK) -#define PMC_FRO1M_ATBCTRL_MASK (0x180U) -#define PMC_FRO1M_ATBCTRL_SHIFT (7U) -#define PMC_FRO1M_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_ATBCTRL_SHIFT)) & PMC_FRO1M_ATBCTRL_MASK) -#define PMC_FRO1M_DIVSEL_MASK (0x3E00U) -#define PMC_FRO1M_DIVSEL_SHIFT (9U) -/*! DIVSEL - Divider selection bits. - * 0b00000..2.0. - * 0b00001..4.0. - * 0b00010..6.0. - * 0b00011..8.0. - * 0b00100..10.0. - * 0b00101..12.0. - * 0b00110..14.0. - * 0b00111..16.0. - * 0b01000..18.0. - * 0b01001..20.0. - * 0b01010..22.0. - * 0b01011..24.0. - * 0b01100..26.0. - * 0b01101..28.0. - * 0b01110..30.0. - * 0b01111..32.0. - * 0b10000..34.0. - * 0b10001..36.0. - * 0b10010..38.0. - * 0b10011..40.0. - * 0b10100..42.0. - * 0b10101..44.0. - * 0b10110..46.0. - * 0b10111..48.0. - * 0b11000..50.0. - * 0b11001..52.0. - * 0b11010..54.0. - * 0b11011..56.0. - * 0b11100..58.0. - * 0b11101..60.0. - * 0b11110..62.0. - * 0b11111..1.0. +#define PMC_REFFASTWKUP_LPWKUP_MASK (0x1U) +#define PMC_REFFASTWKUP_LPWKUP_SHIFT (0U) +/*! LPWKUP - Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . + * 0b0..Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. + * 0b1..Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. */ -#define PMC_FRO1M_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO1M_DIVSEL_SHIFT)) & PMC_FRO1M_DIVSEL_MASK) -/*! @} */ +#define PMC_REFFASTWKUP_LPWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_LPWKUP_SHIFT)) & PMC_REFFASTWKUP_LPWKUP_MASK) -/*! @name FRO32K - 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset] */ -/*! @{ */ -#define PMC_FRO32K_NTAT_MASK (0xEU) -#define PMC_FRO32K_NTAT_SHIFT (1U) -#define PMC_FRO32K_NTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_NTAT_SHIFT)) & PMC_FRO32K_NTAT_MASK) -#define PMC_FRO32K_PTAT_MASK (0x70U) -#define PMC_FRO32K_PTAT_SHIFT (4U) -#define PMC_FRO32K_PTAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_PTAT_SHIFT)) & PMC_FRO32K_PTAT_MASK) -#define PMC_FRO32K_CAPCAL_MASK (0xFF80U) -#define PMC_FRO32K_CAPCAL_SHIFT (7U) -#define PMC_FRO32K_CAPCAL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_CAPCAL_SHIFT)) & PMC_FRO32K_CAPCAL_MASK) -#define PMC_FRO32K_ATBCTRL_MASK (0x30000U) -#define PMC_FRO32K_ATBCTRL_SHIFT (16U) -#define PMC_FRO32K_ATBCTRL(x) (((uint32_t)(((uint32_t)(x)) << PMC_FRO32K_ATBCTRL_SHIFT)) & PMC_FRO32K_ATBCTRL_MASK) +#define PMC_REFFASTWKUP_HWWKUP_MASK (0x2U) +#define PMC_REFFASTWKUP_HWWKUP_SHIFT (1U) +/*! HWWKUP - Analog References fast wake-up in case of Hardware Pin reset: . + * 0b0..Analog References fast wake-up feature is disabled in case of Hardware Pin reset. + * 0b1..Analog References fast wake-up feature is enabled in case of Hardware Pin reset. + */ +#define PMC_REFFASTWKUP_HWWKUP(x) (((uint32_t)(((uint32_t)(x)) << PMC_REFFASTWKUP_HWWKUP_SHIFT)) & PMC_REFFASTWKUP_HWWKUP_MASK) /*! @} */ /*! @name XTAL32K - 32 KHz Crystal oscillator (XTAL) control register [Reset by: PoR, Brown Out Detectors Reset] */ /*! @{ */ + #define PMC_XTAL32K_IREF_MASK (0x6U) #define PMC_XTAL32K_IREF_SHIFT (1U) +/*! IREF - reference output current selection inputs. + */ #define PMC_XTAL32K_IREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IREF_SHIFT)) & PMC_XTAL32K_IREF_MASK) + #define PMC_XTAL32K_TEST_MASK (0x8U) #define PMC_XTAL32K_TEST_SHIFT (3U) +/*! TEST - Oscillator Test Mode. + */ #define PMC_XTAL32K_TEST(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_TEST_SHIFT)) & PMC_XTAL32K_TEST_MASK) + #define PMC_XTAL32K_IBIAS_MASK (0x30U) #define PMC_XTAL32K_IBIAS_SHIFT (4U) +/*! IBIAS - bias current selection inputs. + */ #define PMC_XTAL32K_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_IBIAS_SHIFT)) & PMC_XTAL32K_IBIAS_MASK) + #define PMC_XTAL32K_AMPL_MASK (0xC0U) #define PMC_XTAL32K_AMPL_SHIFT (6U) +/*! AMPL - oscillator amplitude selection inputs. + */ #define PMC_XTAL32K_AMPL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_AMPL_SHIFT)) & PMC_XTAL32K_AMPL_MASK) + #define PMC_XTAL32K_CAPBANKIN_MASK (0x7F00U) #define PMC_XTAL32K_CAPBANKIN_SHIFT (8U) +/*! CAPBANKIN - Capa bank setting input. + */ #define PMC_XTAL32K_CAPBANKIN(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKIN_SHIFT)) & PMC_XTAL32K_CAPBANKIN_MASK) + #define PMC_XTAL32K_CAPBANKOUT_MASK (0x3F8000U) #define PMC_XTAL32K_CAPBANKOUT_SHIFT (15U) +/*! CAPBANKOUT - Capa bank setting output. + */ #define PMC_XTAL32K_CAPBANKOUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPBANKOUT_SHIFT)) & PMC_XTAL32K_CAPBANKOUT_MASK) + #define PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK (0x400000U) #define PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT (22U) /*! CAPTESTSTARTSRCSEL - Source selection for xo32k_captest_start_ao_set. @@ -12612,12 +15040,19 @@ typedef struct { * 0b1..Sourced from calibration. */ #define PMC_XTAL32K_CAPTESTSTARTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTARTSRCSEL_SHIFT)) & PMC_XTAL32K_CAPTESTSTARTSRCSEL_MASK) + #define PMC_XTAL32K_CAPTESTSTART_MASK (0x800000U) #define PMC_XTAL32K_CAPTESTSTART_SHIFT (23U) +/*! CAPTESTSTART - Start test. + */ #define PMC_XTAL32K_CAPTESTSTART(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTSTART_SHIFT)) & PMC_XTAL32K_CAPTESTSTART_MASK) + #define PMC_XTAL32K_CAPTESTENABLE_MASK (0x1000000U) #define PMC_XTAL32K_CAPTESTENABLE_SHIFT (24U) +/*! CAPTESTENABLE - Enable signal for cap test. + */ #define PMC_XTAL32K_CAPTESTENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_XTAL32K_CAPTESTENABLE_SHIFT)) & PMC_XTAL32K_CAPTESTENABLE_MASK) + #define PMC_XTAL32K_CAPTESTOSCINSEL_MASK (0x2000000U) #define PMC_XTAL32K_CAPTESTOSCINSEL_SHIFT (25U) /*! CAPTESTOSCINSEL - Select the input for test. @@ -12629,6 +15064,7 @@ typedef struct { /*! @name COMP - Analog Comparator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ + #define PMC_COMP_HYST_MASK (0x2U) #define PMC_COMP_HYST_SHIFT (1U) /*! HYST - Hysteris when hyst = '1'. @@ -12636,6 +15072,7 @@ typedef struct { * 0b1..Hysteresis is enable. */ #define PMC_COMP_HYST(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_HYST_SHIFT)) & PMC_COMP_HYST_MASK) + #define PMC_COMP_VREFINPUT_MASK (0x4U) #define PMC_COMP_VREFINPUT_SHIFT (2U) /*! VREFINPUT - Dedicated control bit to select between internal VREF and VDDA (for the resistive ladder). @@ -12643,6 +15080,7 @@ typedef struct { * 0b1..Select VDDA. */ #define PMC_COMP_VREFINPUT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREFINPUT_SHIFT)) & PMC_COMP_VREFINPUT_MASK) + #define PMC_COMP_LOWPOWER_MASK (0x8U) #define PMC_COMP_LOWPOWER_SHIFT (3U) /*! LOWPOWER - Low power mode. @@ -12650,6 +15088,7 @@ typedef struct { * 0b1..Low power mode (Low speed). */ #define PMC_COMP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_LOWPOWER_SHIFT)) & PMC_COMP_LOWPOWER_MASK) + #define PMC_COMP_PMUX_MASK (0x70U) #define PMC_COMP_PMUX_SHIFT (4U) /*! PMUX - Control word for P multiplexer:. @@ -12661,6 +15100,7 @@ typedef struct { * 0b101..Pin P2_23. */ #define PMC_COMP_PMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUX_SHIFT)) & PMC_COMP_PMUX_MASK) + #define PMC_COMP_NMUX_MASK (0x380U) #define PMC_COMP_NMUX_SHIFT (7U) /*! NMUX - Control word for N multiplexer:. @@ -12672,22 +15112,133 @@ typedef struct { * 0b101..Pin P2_23. */ #define PMC_COMP_NMUX(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_NMUX_SHIFT)) & PMC_COMP_NMUX_MASK) + #define PMC_COMP_VREF_MASK (0x7C00U) #define PMC_COMP_VREF_SHIFT (10U) +/*! VREF - Control reference voltage step, per steps of (VREFINPUT/31). + */ #define PMC_COMP_VREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_VREF_SHIFT)) & PMC_COMP_VREF_MASK) + #define PMC_COMP_FILTERCGF_SAMPLEMODE_MASK (0x30000U) #define PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT (16U) +/*! FILTERCGF_SAMPLEMODE - Control the filtering of the Analog Comparator output. + * 0b00..Bypass mode. + * 0b01..Filter 1 clock period. + * 0b10..Filter 2 clock period. + * 0b11..Filter 3 clock period. + */ #define PMC_COMP_FILTERCGF_SAMPLEMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)) & PMC_COMP_FILTERCGF_SAMPLEMODE_MASK) + #define PMC_COMP_FILTERCGF_CLKDIV_MASK (0x1C0000U) #define PMC_COMP_FILTERCGF_CLKDIV_SHIFT (18U) +/*! FILTERCGF_CLKDIV - Filter Clock divider. + * 0b000..Filter clock period duration equals 1 Analog Comparator clock period. + * 0b001..Filter clock period duration equals 2 Analog Comparator clock period. + * 0b010..Filter clock period duration equals 4 Analog Comparator clock period. + * 0b011..Filter clock period duration equals 8 Analog Comparator clock period. + * 0b100..Filter clock period duration equals 16 Analog Comparator clock period. + * 0b101..Filter clock period duration equals 32 Analog Comparator clock period. + * 0b110..Filter clock period duration equals 64 Analog Comparator clock period. + * 0b111..Filter clock period duration equals 128 Analog Comparator clock period. + */ #define PMC_COMP_FILTERCGF_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_FILTERCGF_CLKDIV_SHIFT)) & PMC_COMP_FILTERCGF_CLKDIV_MASK) -#define PMC_COMP_PMUXCAPT_MASK (0xE00000U) -#define PMC_COMP_PMUXCAPT_SHIFT (21U) -#define PMC_COMP_PMUXCAPT(x) (((uint32_t)(((uint32_t)(x)) << PMC_COMP_PMUXCAPT_SHIFT)) & PMC_COMP_PMUXCAPT_MASK) +/*! @} */ + +/*! @name WAKEUPIOCTRL - Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] */ +/*! @{ */ + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK (0x1U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT (0U) +/*! RISINGEDGEWAKEUP0 - Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK (0x2U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT (1U) +/*! FALLINGEDGEWAKEUP0 - Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK (0x4U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT (2U) +/*! RISINGEDGEWAKEUP1 - Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK (0x8U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT (3U) +/*! FALLINGEDGEWAKEUP1 - Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK (0x10U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT (4U) +/*! RISINGEDGEWAKEUP2 - Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK (0x20U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT (5U) +/*! FALLINGEDGEWAKEUP2 - Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK (0x40U) +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT (6U) +/*! RISINGEDGEWAKEUP3 - Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Rising edge detection is disable. + * 0b1..Rising edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_RISINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK (0x80U) +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT (7U) +/*! FALLINGEDGEWAKEUP3 - Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. + * 0b0..Falling edge detection is disable. + * 0b1..Falling edge detection is enable. + */ +#define PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_FALLINGEDGEWAKEUP3_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK (0x100U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT (8U) +/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP0_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP0_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK (0x200U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT (9U) +/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP1_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP1_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK (0x400U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT (10U) +/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP2_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP2_MASK) + +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK (0x800U) +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT (11U) +/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode + */ +#define PMC_WAKEUPIOCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEUPIOCTRL_MODEWAKEUP3_SHIFT)) & PMC_WAKEUPIOCTRL_MODEWAKEUP3_MASK) /*! @} */ /*! @name WAKEIOCAUSE - Allows to identify the Wake-up I/O source from Deep Power Down mode */ /*! @{ */ + #define PMC_WAKEIOCAUSE_WAKEUP0_MASK (0x1U) #define PMC_WAKEIOCAUSE_WAKEUP0_SHIFT (0U) /*! WAKEUP0 - Allows to identify Wake up I/O 0 as the wake-up source from Deep Power Down mode. @@ -12695,6 +15246,7 @@ typedef struct { * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 0. */ #define PMC_WAKEIOCAUSE_WAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP0_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP0_MASK) + #define PMC_WAKEIOCAUSE_WAKEUP1_MASK (0x2U) #define PMC_WAKEIOCAUSE_WAKEUP1_SHIFT (1U) /*! WAKEUP1 - Allows to identify Wake up I/O 1 as the wake-up source from Deep Power Down mode. @@ -12702,6 +15254,7 @@ typedef struct { * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 1. */ #define PMC_WAKEIOCAUSE_WAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP1_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP1_MASK) + #define PMC_WAKEIOCAUSE_WAKEUP2_MASK (0x4U) #define PMC_WAKEIOCAUSE_WAKEUP2_SHIFT (2U) /*! WAKEUP2 - Allows to identify Wake up I/O 2 as the wake-up source from Deep Power Down mode. @@ -12709,6 +15262,7 @@ typedef struct { * 0b1..Last wake up from Deep Power down mode was triggred by wake up I/O 2. */ #define PMC_WAKEIOCAUSE_WAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_WAKEIOCAUSE_WAKEUP2_SHIFT)) & PMC_WAKEIOCAUSE_WAKEUP2_MASK) + #define PMC_WAKEIOCAUSE_WAKEUP3_MASK (0x8U) #define PMC_WAKEIOCAUSE_WAKEUP3_SHIFT (3U) /*! WAKEUP3 - Allows to identify Wake up I/O 3 as the wake-up source from Deep Power Down mode. @@ -12720,30 +15274,167 @@ typedef struct { /*! @name STATUSCLK - FRO and XTAL status register [Reset by: PoR, Brown Out Detectors Reset] */ /*! @{ */ + #define PMC_STATUSCLK_XTAL32KOK_MASK (0x1U) #define PMC_STATUSCLK_XTAL32KOK_SHIFT (0U) +/*! XTAL32KOK - XTAL oscillator 32 K OK signal. + */ #define PMC_STATUSCLK_XTAL32KOK(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOK_SHIFT)) & PMC_STATUSCLK_XTAL32KOK_MASK) -#define PMC_STATUSCLK_FRO1MCLKVALID_MASK (0x2U) -#define PMC_STATUSCLK_FRO1MCLKVALID_SHIFT (1U) -#define PMC_STATUSCLK_FRO1MCLKVALID(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_FRO1MCLKVALID_SHIFT)) & PMC_STATUSCLK_FRO1MCLKVALID_MASK) + #define PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK (0x4U) #define PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT (2U) /*! XTAL32KOSCFAILURE - XTAL32 KHZ oscillator oscillation failure detection indicator. - * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared.. - * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared.. + * 0b0..No oscillation failure has been detetced since the last time this bit has been cleared. + * 0b1..At least one oscillation failure has been detetced since the last time this bit has been cleared. */ #define PMC_STATUSCLK_XTAL32KOSCFAILURE(x) (((uint32_t)(((uint32_t)(x)) << PMC_STATUSCLK_XTAL32KOSCFAILURE_SHIFT)) & PMC_STATUSCLK_XTAL32KOSCFAILURE_MASK) /*! @} */ /*! @name AOREG1 - General purpose always on domain data storage [Reset by: PoR, Brown Out Detectors Reset] */ /*! @{ */ -#define PMC_AOREG1_DATA31_0_MASK (0xFFFFFFFFU) -#define PMC_AOREG1_DATA31_0_SHIFT (0U) -#define PMC_AOREG1_DATA31_0(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DATA31_0_SHIFT)) & PMC_AOREG1_DATA31_0_MASK) + +#define PMC_AOREG1_POR_MASK (0x10U) +#define PMC_AOREG1_POR_SHIFT (4U) +/*! POR - The last chip reset was caused by a Power On Reset. + */ +#define PMC_AOREG1_POR(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_POR_SHIFT)) & PMC_AOREG1_POR_MASK) + +#define PMC_AOREG1_PADRESET_MASK (0x20U) +#define PMC_AOREG1_PADRESET_SHIFT (5U) +/*! PADRESET - The last chip reset was caused by a Pin Reset. + */ +#define PMC_AOREG1_PADRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_PADRESET_SHIFT)) & PMC_AOREG1_PADRESET_MASK) + +#define PMC_AOREG1_BODRESET_MASK (0x40U) +#define PMC_AOREG1_BODRESET_SHIFT (6U) +/*! BODRESET - The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. + */ +#define PMC_AOREG1_BODRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BODRESET_SHIFT)) & PMC_AOREG1_BODRESET_MASK) + +#define PMC_AOREG1_SYSTEMRESET_MASK (0x80U) +#define PMC_AOREG1_SYSTEMRESET_SHIFT (7U) +/*! SYSTEMRESET - The last chip reset was caused by a System Reset requested by the ARM CPU. + */ +#define PMC_AOREG1_SYSTEMRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SYSTEMRESET_SHIFT)) & PMC_AOREG1_SYSTEMRESET_MASK) + +#define PMC_AOREG1_WDTRESET_MASK (0x100U) +#define PMC_AOREG1_WDTRESET_SHIFT (8U) +/*! WDTRESET - The last chip reset was caused by the Watchdog Timer. + */ +#define PMC_AOREG1_WDTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_WDTRESET_SHIFT)) & PMC_AOREG1_WDTRESET_MASK) + +#define PMC_AOREG1_SWRRESET_MASK (0x200U) +#define PMC_AOREG1_SWRRESET_SHIFT (9U) +/*! SWRRESET - The last chip reset was caused by a Software event. + */ +#define PMC_AOREG1_SWRRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_SWRRESET_SHIFT)) & PMC_AOREG1_SWRRESET_MASK) + +#define PMC_AOREG1_DPDRESET_WAKEUPIO_MASK (0x400U) +#define PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT (10U) +/*! DPDRESET_WAKEUPIO - The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_WAKEUPIO(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT)) & PMC_AOREG1_DPDRESET_WAKEUPIO_MASK) + +#define PMC_AOREG1_DPDRESET_RTC_MASK (0x800U) +#define PMC_AOREG1_DPDRESET_RTC_SHIFT (11U) +/*! DPDRESET_RTC - The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_RTC(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_RTC_SHIFT)) & PMC_AOREG1_DPDRESET_RTC_MASK) + +#define PMC_AOREG1_DPDRESET_OSTIMER_MASK (0x1000U) +#define PMC_AOREG1_DPDRESET_OSTIMER_SHIFT (12U) +/*! DPDRESET_OSTIMER - The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. + */ +#define PMC_AOREG1_DPDRESET_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_DPDRESET_OSTIMER_SHIFT)) & PMC_AOREG1_DPDRESET_OSTIMER_MASK) + +#define PMC_AOREG1_BOOTERRORCOUNTER_MASK (0xF0000U) +#define PMC_AOREG1_BOOTERRORCOUNTER_SHIFT (16U) +/*! BOOTERRORCOUNTER - ROM Boot Fatal Error Counter. + */ +#define PMC_AOREG1_BOOTERRORCOUNTER(x) (((uint32_t)(((uint32_t)(x)) << PMC_AOREG1_BOOTERRORCOUNTER_SHIFT)) & PMC_AOREG1_BOOTERRORCOUNTER_MASK) +/*! @} */ + +/*! @name MISCCTRL - Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ +/*! @{ */ + +#define PMC_MISCCTRL_LDODEEPSLEEPREF_MASK (0x1U) +#define PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT (0U) +/*! LDODEEPSLEEPREF - Select LDO Deep Sleep reference source. + * 0b0..LDO DEEP Sleep uses Flash buffer biasing as reference. + * 0b1..LDO DEEP Sleep uses Band Gap 0.8V as reference. + */ +#define PMC_MISCCTRL_LDODEEPSLEEPREF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDODEEPSLEEPREF_SHIFT)) & PMC_MISCCTRL_LDODEEPSLEEPREF_MASK) + +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK (0x2U) +#define PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT (1U) +/*! LDOMEMHIGHZMODE - Control the activation of LDO MEM High Z mode. + * 0b0..LDO MEM High Z mode is disabled. + * 0b1..LDO MEM High Z mode is enabled. + */ +#define PMC_MISCCTRL_LDOMEMHIGHZMODE(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LDOMEMHIGHZMODE_SHIFT)) & PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK) + +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK (0x4U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT (2U) +#define PMC_MISCCTRL_LOWPWR_FLASH_BUF(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_LOWPWR_FLASH_BUF_SHIFT)) & PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) + +#define PMC_MISCCTRL_MISCCTRL_3_8_MASK (0xF8U) +#define PMC_MISCCTRL_MISCCTRL_3_8_SHIFT (3U) +/*! MISCCTRL_3_8 - Reserved. + */ +#define PMC_MISCCTRL_MISCCTRL_3_8(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_3_8_SHIFT)) & PMC_MISCCTRL_MISCCTRL_3_8_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP0_MASK (0x100U) +#define PMC_MISCCTRL_MODEWAKEUP0_SHIFT (8U) +/*! MODEWAKEUP0 - Configure wake up I/O 0 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP0(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP0_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP0_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP1_MASK (0x200U) +#define PMC_MISCCTRL_MODEWAKEUP1_SHIFT (9U) +/*! MODEWAKEUP1 - Configure wake up I/O 1 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP1(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP1_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP1_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP2_MASK (0x400U) +#define PMC_MISCCTRL_MODEWAKEUP2_SHIFT (10U) +/*! MODEWAKEUP2 - Configure wake up I/O 2 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP2(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP2_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP2_MASK) + +#define PMC_MISCCTRL_MODEWAKEUP3_MASK (0x800U) +#define PMC_MISCCTRL_MODEWAKEUP3_SHIFT (11U) +/*! MODEWAKEUP3 - Configure wake up I/O 3 in Deep Power Down mode + */ +#define PMC_MISCCTRL_MODEWAKEUP3(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MODEWAKEUP3_SHIFT)) & PMC_MISCCTRL_MODEWAKEUP3_MASK) + +#define PMC_MISCCTRL_DISABLE_BLEED_MASK (0x1000U) +#define PMC_MISCCTRL_DISABLE_BLEED_SHIFT (12U) +/*! DISABLE_BLEED - Controls LDO MEM bleed current. This field is expected to be controlled by the + * Low Power Software only in DEEP SLEEP low power mode. + * 0b0..LDO_MEM bleed current is enabled. + * 0b1..LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared + * after wake up from Deep SLeep low power mode. + */ +#define PMC_MISCCTRL_DISABLE_BLEED(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_DISABLE_BLEED_SHIFT)) & PMC_MISCCTRL_DISABLE_BLEED_MASK) + +#define PMC_MISCCTRL_MISCCTRL_13_14_MASK (0x6000U) +#define PMC_MISCCTRL_MISCCTRL_13_14_SHIFT (13U) +/*! MISCCTRL_13_14 - Reserved. + */ +#define PMC_MISCCTRL_MISCCTRL_13_14(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_MISCCTRL_13_14_SHIFT)) & PMC_MISCCTRL_MISCCTRL_13_14_MASK) + +#define PMC_MISCCTRL_WAKUPIO_RST_MASK (0x8000U) +#define PMC_MISCCTRL_WAKUPIO_RST_SHIFT (15U) +/*! WAKUPIO_RST - WAKEUP IO event detector reset control. + * 0b1..Wakeup IO is reset. + * 0b0..Wakeup IO is not reset. + */ +#define PMC_MISCCTRL_WAKUPIO_RST(x) (((uint32_t)(((uint32_t)(x)) << PMC_MISCCTRL_WAKUPIO_RST_SHIFT)) & PMC_MISCCTRL_WAKUPIO_RST_MASK) /*! @} */ /*! @name RTCOSC32K - RTC 1 KHZ and 1 Hz clocks source control register [Reset by: PoR, Brown Out Detectors Reset] */ /*! @{ */ + #define PMC_RTCOSC32K_SEL_MASK (0x1U) #define PMC_RTCOSC32K_SEL_SHIFT (0U) /*! SEL - Select the 32K oscillator to be used in Deep Power Down Mode for the RTC (either XTAL32KHz or FRO32KHz) . @@ -12751,246 +15442,69 @@ typedef struct { * 0b1..XTAL 32KHz. */ #define PMC_RTCOSC32K_SEL(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_SEL_SHIFT)) & PMC_RTCOSC32K_SEL_MASK) + #define PMC_RTCOSC32K_CLK1KHZDIV_MASK (0xEU) #define PMC_RTCOSC32K_CLK1KHZDIV_SHIFT (1U) +/*! CLK1KHZDIV - Actual division ratio is : 28 + CLK1KHZDIV. + */ #define PMC_RTCOSC32K_CLK1KHZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIV_MASK) + #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK (0x8000U) #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT (15U) +/*! CLK1KHZDIVUPDATEREQ - RTC 1KHz clock Divider status flag. + */ #define PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1KHZDIVUPDATEREQ_MASK) + #define PMC_RTCOSC32K_CLK1HZDIV_MASK (0x7FF0000U) #define PMC_RTCOSC32K_CLK1HZDIV_SHIFT (16U) +/*! CLK1HZDIV - Actual division ratio is : 31744 + CLK1HZDIV. + */ #define PMC_RTCOSC32K_CLK1HZDIV(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIV_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIV_MASK) + #define PMC_RTCOSC32K_CLK1HZDIVHALT_MASK (0x40000000U) #define PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT (30U) +/*! CLK1HZDIVHALT - Halts the divider counter. + */ #define PMC_RTCOSC32K_CLK1HZDIVHALT(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVHALT_MASK) + #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK (0x80000000U) #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT (31U) +/*! CLK1HZDIVUPDATEREQ - RTC 1Hz Divider status flag. + */ #define PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ(x) (((uint32_t)(((uint32_t)(x)) << PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_SHIFT)) & PMC_RTCOSC32K_CLK1HZDIVUPDATEREQ_MASK) /*! @} */ /*! @name OSTIMER - OS Timer control register [Reset by: PoR, Brown Out Detectors Reset] */ /*! @{ */ + #define PMC_OSTIMER_SOFTRESET_MASK (0x1U) #define PMC_OSTIMER_SOFTRESET_SHIFT (0U) +/*! SOFTRESET - Active high reset. + */ #define PMC_OSTIMER_SOFTRESET(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_SOFTRESET_SHIFT)) & PMC_OSTIMER_SOFTRESET_MASK) + #define PMC_OSTIMER_CLOCKENABLE_MASK (0x2U) #define PMC_OSTIMER_CLOCKENABLE_SHIFT (1U) +/*! CLOCKENABLE - Enable OSTIMER 32 KHz clock. + */ #define PMC_OSTIMER_CLOCKENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_CLOCKENABLE_SHIFT)) & PMC_OSTIMER_CLOCKENABLE_MASK) + #define PMC_OSTIMER_DPDWAKEUPENABLE_MASK (0x4U) #define PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT (2U) +/*! DPDWAKEUPENABLE - Wake up enable in Deep Power Down mode (To be used in Enable Deep Power Down mode). + */ #define PMC_OSTIMER_DPDWAKEUPENABLE(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_DPDWAKEUPENABLE_SHIFT)) & PMC_OSTIMER_DPDWAKEUPENABLE_MASK) + #define PMC_OSTIMER_OSC32KPD_MASK (0x8U) #define PMC_OSTIMER_OSC32KPD_SHIFT (3U) +/*! OSC32KPD - Oscilator 32KHz (either FRO32KHz or XTAL32KHz according to RTCOSC32K. + */ #define PMC_OSTIMER_OSC32KPD(x) (((uint32_t)(((uint32_t)(x)) << PMC_OSTIMER_OSC32KPD_SHIFT)) & PMC_OSTIMER_OSC32KPD_MASK) /*! @} */ -/*! @name PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ -/*! @{ */ -#define PMC_PDSLEEPCFG0_PDEN_DCDC_MASK (0x1U) -#define PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT (0U) -/*! PDEN_DCDC - Controls DCDC power during DEEP SLEEP (DCDC is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..DCDC is powered on during low power mode.. - * 0b1..DCDC is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_DCDC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_DCDC_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BIAS_MASK (0x2U) -#define PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT (1U) -/*! PDEN_BIAS - Controls Analog Bias power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Analog Bias is powered on during low power mode.. - * 0b1..Analog Bias is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BIAS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK (0x4U) -#define PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT (2U) -/*! PDEN_BODCORE - Controls Core Logic BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..BOD CORE is powered on during low power mode.. - * 0b1..BOD CORE is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODCORE_MASK) -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK (0x8U) -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT (3U) -/*! PDEN_BODVBAT - Controls VBAT BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..BOD VBAT is powered on during low power mode.. - * 0b1..BOD VBAT is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_BODVBAT_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK (0x10U) -#define PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT (4U) -/*! PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..FRO 1MHz is powered on during low power mode.. - * 0b1..FRO 1MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO1M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO1M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO1M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK (0x20U) -#define PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT (5U) -/*! PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP SLEEP (always shut down - * during POWER DOWN and DEEP POWER DOWN). - * 0b0..FRO 192 MHz is powered on during low power mode.. - * 0b1..FRO 192 MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO192M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK (0x40U) -#define PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT (6U) -/*! PDEN_FRO32K - Controls power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..FRO 32 KHz is powered on during low power mode.. - * 0b1..FRO 32 KHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_FRO32K_MASK) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK (0x80U) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT (7U) -/*! PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..crystal 32 KHz is powered on during low power mode.. - * 0b1..crystal 32 KHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32K_MASK) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK (0x100U) -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls crystal 32 MHz power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..crystal 32 MHz is powered on during low power mode.. - * 0b1..crystal 32 MHz is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_XTAL32M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_MASK (0x200U) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT (9U) -/*! PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP SLEEP (always shut down - * during POWER DOWN and DEEP POWER DOWN). - * 0b0..System PLL (also refered as PLL0) is powered on during low power mode.. - * 0b1..System PLL (also refered as PLL0) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL1_MASK (0x400U) -#define PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT (10U) -/*! PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP SLEEP (always shut down - * during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB PLL (also refered as PLL1) is powered on during low power mode.. - * 0b1..USB PLL (also refered as PLL1) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL1_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL1_MASK) -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK (0x800U) -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT (11U) -/*! PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB Full Speed phy is powered on during low power mode.. - * 0b1..USB Full Speed phy is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBFSPHY_MASK) -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK (0x1000U) -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT (12U) -/*! PDEN_USBHSPHY - Controls USB High Speed Phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB High Speed Phy is powered on during low power mode.. - * 0b1..USB High Speed Phy is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_USBHSPHY_MASK) -#define PMC_PDSLEEPCFG0_PDEN_COMP_MASK (0x2000U) -#define PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT (13U) -/*! PDEN_COMP - Controls Analog Comparator power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Analog Comparator is powered on during low power mode.. - * 0b1..Analog Comparator is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_COMP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_COMP_MASK) -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK (0x4000U) -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT (14U) -/*! PDEN_TEMPSENS - Controls Temperature Sensor power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..Temperature Sensor is powered on during low power mode.. - * 0b1..Temperature Sensor is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_TEMPSENS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_GPADC_MASK (0x8000U) -#define PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT (15U) -/*! PDEN_GPADC - Controls General Purpose ADC (GPADC) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..General Purpose ADC (GPADC) is powered on during low power mode.. - * 0b1..General Purpose ADC (GPADC) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_GPADC_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_GPADC_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK (0x10000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT (16U) -/*! PDEN_LDOMEM - Controls Memories LDO power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - * 0b0..Memories LDO is powered on during low power mode.. - * 0b1..Memories LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOMEM_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) -/*! PDEN_LDODEEPSLEEP - Controls Deep Sleep LDO power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..Deep Sleep LDO is powered on during low power mode.. - * 0b1..Deep Sleep LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDODEEPSLEEP_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK (0x40000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT (18U) -/*! PDEN_LDOUSBHS - Controls USB high speed LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..USB high speed LDO is powered on during low power mode.. - * 0b1..USB high speed LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOUSBHS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK (0x80000U) -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT (19U) -/*! PDEN_AUXBIAS - during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - * 0b0..is powered on during low power mode.. - * 0b1..is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_AUXBIAS_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK (0x100000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls crystal 32 MHz LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..crystal 32 MHz LDO is powered on during low power mode.. - * 0b1..crystal 32 MHz LDO is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOXO32M_MASK) -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT (21U) -/*! PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..Flash NV (high voltage) is powered on during low power mode.. - * 0b1..Flash NV (high voltage) is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_LDOFLASHNV_MASK) -#define PMC_PDSLEEPCFG0_PDEN_RNG_MASK (0x400000U) -#define PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT (22U) -/*! PDEN_RNG - Controls True Random Number Genetaor (TRNG) clock sources power during DEEP SLEEP - * (always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..True Random Number Genetaor (TRNG) clock sources are powered on during low power mode.. - * 0b1..True Random Number Genetaor (TRNG) clock sources are powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_RNG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_RNG_MASK) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT (23U) -/*! PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP SLEEP (PLL0 Spread - * Spectrum is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..PLL0 Spread Sprectrum module is powered on during low power mode.. - * 0b1..PLL0 Spread Sprectrum module is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_PLL0_SSCG_MASK) -#define PMC_PDSLEEPCFG0_PDEN_ROM_MASK (0x1000000U) -#define PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT (24U) -/*! PDEN_ROM - Controls ROM power during DEEP SLEEP (ROM is always shut down during POWER DOWN and DEEP POWER DOWN). - * 0b0..ROM is powered on during low power mode.. - * 0b1..ROM is powered off during low power mode.. - */ -#define PMC_PDSLEEPCFG0_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDSLEEPCFG0_PDEN_ROM_SHIFT)) & PMC_PDSLEEPCFG0_PDEN_ROM_MASK) -/*! @} */ - /*! @name PDRUNCFG0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ -#define PMC_PDRUNCFG0_PDEN_DCDC_MASK (0x1U) -#define PMC_PDRUNCFG0_PDEN_DCDC_SHIFT (0U) -/*! PDEN_DCDC - Controls power to Bulk DCDC Converter. - * 0b0..DCDC is powered. - * 0b1..DCDC is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_DCDC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_DCDC_SHIFT)) & PMC_PDRUNCFG0_PDEN_DCDC_MASK) -#define PMC_PDRUNCFG0_PDEN_BIAS_MASK (0x2U) -#define PMC_PDRUNCFG0_PDEN_BIAS_SHIFT (1U) -/*! PDEN_BIAS - Controls power to . - * 0b0..Analog Bias is powered. - * 0b1..Analog Bias is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_BIAS_MASK) -#define PMC_PDRUNCFG0_PDEN_BODCORE_MASK (0x4U) -#define PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT (2U) -/*! PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD). - * 0b0..BOD CORE is powered. - * 0b1..BOD CORE is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_BODCORE(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODCORE_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODCORE_MASK) + #define PMC_PDRUNCFG0_PDEN_BODVBAT_MASK (0x8U) #define PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT (3U) /*! PDEN_BODVBAT - Controls power to VBAT Brown Out Detector (BOD). @@ -12998,14 +15512,7 @@ typedef struct { * 0b1..BOD VBAT is powered down. */ #define PMC_PDRUNCFG0_PDEN_BODVBAT(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_BODVBAT_SHIFT)) & PMC_PDRUNCFG0_PDEN_BODVBAT_MASK) -#define PMC_PDRUNCFG0_PDEN_FRO192M_MASK (0x20U) -#define PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT (5U) -/*! PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz - * and 96 MHz clocks are derived from this FRO. - * 0b0..FRO 192MHz is powered. - * 0b1..FRO 192MHz is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_FRO192M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO192M_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) + #define PMC_PDRUNCFG0_PDEN_FRO32K_MASK (0x40U) #define PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT (6U) /*! PDEN_FRO32K - Controls power to the Free Running Oscillator (FRO) 32 KHz. @@ -13013,6 +15520,7 @@ typedef struct { * 0b1..FRO32KHz is powered down. */ #define PMC_PDRUNCFG0_PDEN_FRO32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_FRO32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_FRO32K_MASK) + #define PMC_PDRUNCFG0_PDEN_XTAL32K_MASK (0x80U) #define PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT (7U) /*! PDEN_XTAL32K - Controls power to crystal 32 KHz. @@ -13020,13 +15528,15 @@ typedef struct { * 0b1..Crystal 32KHz is powered down. */ #define PMC_PDRUNCFG0_PDEN_XTAL32K(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32K_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK) + #define PMC_PDRUNCFG0_PDEN_XTAL32M_MASK (0x100U) #define PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT (8U) -/*! PDEN_XTAL32M - Controls power to crystal 32 MHz. - * 0b0..Crystal 32MHz is powered. - * 0b1..Crystal 32MHz is powered down. +/*! PDEN_XTAL32M - Controls power to high speed crystal. + * 0b0..High speed crystal is powered. + * 0b1..High speed crystal is powered down. */ #define PMC_PDRUNCFG0_PDEN_XTAL32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_XTAL32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_XTAL32M_MASK) + #define PMC_PDRUNCFG0_PDEN_PLL0_MASK (0x200U) #define PMC_PDRUNCFG0_PDEN_PLL0_SHIFT (9U) /*! PDEN_PLL0 - Controls power to System PLL (also refered as PLL0). @@ -13034,6 +15544,7 @@ typedef struct { * 0b1..PLL0 is powered down. */ #define PMC_PDRUNCFG0_PDEN_PLL0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL0_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL0_MASK) + #define PMC_PDRUNCFG0_PDEN_PLL1_MASK (0x400U) #define PMC_PDRUNCFG0_PDEN_PLL1_SHIFT (10U) /*! PDEN_PLL1 - Controls power to USB PLL (also refered as PLL1). @@ -13041,6 +15552,7 @@ typedef struct { * 0b1..PLL1 is powered down. */ #define PMC_PDRUNCFG0_PDEN_PLL1(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_PLL1_SHIFT)) & PMC_PDRUNCFG0_PDEN_PLL1_MASK) + #define PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK (0x800U) #define PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT (11U) /*! PDEN_USBFSPHY - Controls power to USB Full Speed phy. @@ -13048,6 +15560,7 @@ typedef struct { * 0b1..USB Full Speed phy is powered down. */ #define PMC_PDRUNCFG0_PDEN_USBFSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBFSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBFSPHY_MASK) + #define PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK (0x1000U) #define PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT (12U) /*! PDEN_USBHSPHY - Controls power to USB High Speed Phy. @@ -13055,6 +15568,7 @@ typedef struct { * 0b1..USB HS phy is powered down. */ #define PMC_PDRUNCFG0_PDEN_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_USBHSPHY_SHIFT)) & PMC_PDRUNCFG0_PDEN_USBHSPHY_MASK) + #define PMC_PDRUNCFG0_PDEN_COMP_MASK (0x2000U) #define PMC_PDRUNCFG0_PDEN_COMP_SHIFT (13U) /*! PDEN_COMP - Controls power to Analog Comparator. @@ -13062,34 +15576,7 @@ typedef struct { * 0b1..Analog Comparator is powered down. */ #define PMC_PDRUNCFG0_PDEN_COMP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_COMP_SHIFT)) & PMC_PDRUNCFG0_PDEN_COMP_MASK) -#define PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK (0x4000U) -#define PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT (14U) -/*! PDEN_TEMPSENS - Controls power to Temperature Sensor. - * 0b0..Temperature Sensor is powered. - * 0b1..Temperature Sensor is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_TEMPSENS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_TEMPSENS_SHIFT)) & PMC_PDRUNCFG0_PDEN_TEMPSENS_MASK) -#define PMC_PDRUNCFG0_PDEN_GPADC_MASK (0x8000U) -#define PMC_PDRUNCFG0_PDEN_GPADC_SHIFT (15U) -/*! PDEN_GPADC - Controls power to General Purpose ADC (GPADC). - * 0b0..GPADC is powered. - * 0b1..GPADC is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_GPADC(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_GPADC_SHIFT)) & PMC_PDRUNCFG0_PDEN_GPADC_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOMEM_MASK (0x10000U) -#define PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT (16U) -/*! PDEN_LDOMEM - Controls power to Memories LDO. - * 0b0..Memories LDO is powered. - * 0b1..Memories LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOMEM(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOMEM_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOMEM_MASK) -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK (0x20000U) -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT (17U) -/*! PDEN_LDODEEPSLEEP - Controls power to Deep Sleep LDO. - * 0b0..Deep Sleep LDO is powered. - * 0b1..Deep Sleep LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDODEEPSLEEP_MASK) + #define PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK (0x40000U) #define PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT (18U) /*! PDEN_LDOUSBHS - Controls power to USB high speed LDO. @@ -13097,6 +15584,7 @@ typedef struct { * 0b1..USB high speed LDO is powered down. */ #define PMC_PDRUNCFG0_PDEN_LDOUSBHS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOUSBHS_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOUSBHS_MASK) + #define PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK (0x80000U) #define PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT (19U) /*! PDEN_AUXBIAS - Controls power to auxiliary biasing (AUXBIAS) @@ -13104,20 +15592,15 @@ typedef struct { * 0b1..auxiliary biasing is powered down. */ #define PMC_PDRUNCFG0_PDEN_AUXBIAS(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_AUXBIAS_SHIFT)) & PMC_PDRUNCFG0_PDEN_AUXBIAS_MASK) + #define PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK (0x100000U) #define PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT (20U) -/*! PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO. - * 0b0..crystal 32 MHz LDO is powered. - * 0b1..crystal 32 MHz LDO is powered down. +/*! PDEN_LDOXO32M - Controls power to high speed crystal LDO. + * 0b0..High speed crystal LDO is powered. + * 0b1..High speed crystal LDO is powered down. */ #define PMC_PDRUNCFG0_PDEN_LDOXO32M(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOXO32M_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK) -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK (0x200000U) -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT (21U) -/*! PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO. - * 0b0..Flash NV LDO is powered. - * 0b1..Flash NV LDO is powered down. - */ -#define PMC_PDRUNCFG0_PDEN_LDOFLASHNV(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_LDOFLASHNV_SHIFT)) & PMC_PDRUNCFG0_PDEN_LDOFLASHNV_MASK) + #define PMC_PDRUNCFG0_PDEN_RNG_MASK (0x400000U) #define PMC_PDRUNCFG0_PDEN_RNG_SHIFT (22U) /*! PDEN_RNG - Controls power to all True Random Number Genetaor (TRNG) clock sources. @@ -13125,6 +15608,7 @@ typedef struct { * 0b1..TRNG clocks are powered down. */ #define PMC_PDRUNCFG0_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFG0_PDEN_RNG_SHIFT)) & PMC_PDRUNCFG0_PDEN_RNG_MASK) + #define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK (0x800000U) #define PMC_PDRUNCFG0_PDEN_PLL0_SSCG_SHIFT (23U) /*! PDEN_PLL0_SSCG - Controls power to System PLL (PLL0) Spread Spectrum module. @@ -13136,18 +15620,56 @@ typedef struct { /*! @name PDRUNCFGSET0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ + #define PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK (0xFFFFFFFFU) #define PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT (0U) +/*! PDRUNCFGSET0 - Writing ones to this register sets the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ #define PMC_PDRUNCFGSET0_PDRUNCFGSET0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGSET0_PDRUNCFGSET0_SHIFT)) & PMC_PDRUNCFGSET0_PDRUNCFGSET0_MASK) /*! @} */ /*! @name PDRUNCFGCLR0 - Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] */ /*! @{ */ + #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK (0xFFFFFFFFU) #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT (0U) +/*! PDRUNCFGCLR0 - Writing ones to this register clears the corresponding bit or bits in the PDRUNCFG0 register, if they are implemented. + */ #define PMC_PDRUNCFGCLR0_PDRUNCFGCLR0(x) (((uint32_t)(((uint32_t)(x)) << PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_SHIFT)) & PMC_PDRUNCFGCLR0_PDRUNCFGCLR0_MASK) /*! @} */ +/*! @name SRAMCTRL - All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] */ +/*! @{ */ + +#define PMC_SRAMCTRL_SMB_MASK (0x3U) +#define PMC_SRAMCTRL_SMB_SHIFT (0U) +/*! SMB - Source Biasing voltage. + * 0b00..Low leakage. + * 0b01..Medium leakage. + * 0b10..Highest leakage. + * 0b11..Disable. + */ +#define PMC_SRAMCTRL_SMB(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_SMB_SHIFT)) & PMC_SRAMCTRL_SMB_MASK) + +#define PMC_SRAMCTRL_RM_MASK (0x1CU) +#define PMC_SRAMCTRL_RM_SHIFT (2U) +/*! RM - Read Margin control settings. + */ +#define PMC_SRAMCTRL_RM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_RM_SHIFT)) & PMC_SRAMCTRL_RM_MASK) + +#define PMC_SRAMCTRL_WM_MASK (0xE0U) +#define PMC_SRAMCTRL_WM_SHIFT (5U) +/*! WM - Write Margin control settings. + */ +#define PMC_SRAMCTRL_WM(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WM_SHIFT)) & PMC_SRAMCTRL_WM_MASK) + +#define PMC_SRAMCTRL_WRME_MASK (0x100U) +#define PMC_SRAMCTRL_WRME_SHIFT (8U) +/*! WRME - Write read margin enable. + */ +#define PMC_SRAMCTRL_WRME(x) (((uint32_t)(((uint32_t)(x)) << PMC_SRAMCTRL_WRME_SHIFT)) & PMC_SRAMCTRL_WRME_MASK) +/*! @} */ + /*! * @} @@ -13155,7 +15677,7 @@ typedef struct { /* PMC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral PMC base address */ #define PMC_BASE (0x50020000u) /** Peripheral PMC base address */ @@ -13237,229 +15759,375 @@ typedef struct { /*! @name OUTBASE - Base address register for output region */ /*! @{ */ + #define POWERQUAD_OUTBASE_OUTBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_OUTBASE_OUTBASE_SHIFT (0U) +/*! outbase - Base address register for the output region + */ #define POWERQUAD_OUTBASE_OUTBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTBASE_OUTBASE_SHIFT)) & POWERQUAD_OUTBASE_OUTBASE_MASK) /*! @} */ /*! @name OUTFORMAT - Output format */ /*! @{ */ + #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK (0x3U) #define POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT (0U) +/*! out_formatint - Output Internal format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_OUTFORMAT_OUT_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATINT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATINT_MASK) + #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK (0x30U) #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT (4U) +/*! out_formatext - Output External format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_OUTFORMAT_OUT_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_FORMATEXT_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_FORMATEXT_MASK) + #define POWERQUAD_OUTFORMAT_OUT_SCALER_MASK (0xFF00U) #define POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT (8U) +/*! out_scaler - Output Scaler value (for scaled 'q31' formats) + */ #define POWERQUAD_OUTFORMAT_OUT_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_OUTFORMAT_OUT_SCALER_SHIFT)) & POWERQUAD_OUTFORMAT_OUT_SCALER_MASK) /*! @} */ /*! @name TMPBASE - Base address register for temp region */ /*! @{ */ + #define POWERQUAD_TMPBASE_TMPBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_TMPBASE_TMPBASE_SHIFT (0U) +/*! tmpbase - Base address register for the temporary region + */ #define POWERQUAD_TMPBASE_TMPBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPBASE_TMPBASE_SHIFT)) & POWERQUAD_TMPBASE_TMPBASE_MASK) /*! @} */ /*! @name TMPFORMAT - Temp format */ /*! @{ */ + #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK (0x3U) #define POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT (0U) +/*! tmp_formatint - Temp Internal format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_TMPFORMAT_TMP_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATINT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATINT_MASK) + #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK (0x30U) #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT (4U) +/*! tmp_formatext - Temp External format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_TMPFORMAT_TMP_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_FORMATEXT_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_FORMATEXT_MASK) + #define POWERQUAD_TMPFORMAT_TMP_SCALER_MASK (0xFF00U) #define POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT (8U) +/*! tmp_scaler - Temp Scaler value (for scaled 'q31' formats) + */ #define POWERQUAD_TMPFORMAT_TMP_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_TMPFORMAT_TMP_SCALER_SHIFT)) & POWERQUAD_TMPFORMAT_TMP_SCALER_MASK) /*! @} */ /*! @name INABASE - Base address register for input A region */ /*! @{ */ + #define POWERQUAD_INABASE_INABASE_MASK (0xFFFFFFFFU) #define POWERQUAD_INABASE_INABASE_SHIFT (0U) +/*! inabase - Base address register for the input A region + */ #define POWERQUAD_INABASE_INABASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INABASE_INABASE_SHIFT)) & POWERQUAD_INABASE_INABASE_MASK) /*! @} */ /*! @name INAFORMAT - Input A format */ /*! @{ */ + #define POWERQUAD_INAFORMAT_INA_FORMATINT_MASK (0x3U) #define POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT (0U) +/*! ina_formatint - Input A Internal format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_INAFORMAT_INA_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATINT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATINT_MASK) + #define POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK (0x30U) #define POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT (4U) +/*! ina_formatext - Input A External format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_INAFORMAT_INA_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_FORMATEXT_SHIFT)) & POWERQUAD_INAFORMAT_INA_FORMATEXT_MASK) + #define POWERQUAD_INAFORMAT_INA_SCALER_MASK (0xFF00U) #define POWERQUAD_INAFORMAT_INA_SCALER_SHIFT (8U) +/*! ina_scaler - Input A Scaler value (for scaled 'q31' formats) + */ #define POWERQUAD_INAFORMAT_INA_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INAFORMAT_INA_SCALER_SHIFT)) & POWERQUAD_INAFORMAT_INA_SCALER_MASK) /*! @} */ /*! @name INBBASE - Base address register for input B region */ /*! @{ */ + #define POWERQUAD_INBBASE_INBBASE_MASK (0xFFFFFFFFU) #define POWERQUAD_INBBASE_INBBASE_SHIFT (0U) +/*! inbbase - Base address register for the input B region + */ #define POWERQUAD_INBBASE_INBBASE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBBASE_INBBASE_SHIFT)) & POWERQUAD_INBBASE_INBBASE_MASK) /*! @} */ /*! @name INBFORMAT - Input B format */ /*! @{ */ + #define POWERQUAD_INBFORMAT_INB_FORMATINT_MASK (0x3U) #define POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT (0U) +/*! inb_formatint - Input B Internal format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_INBFORMAT_INB_FORMATINT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATINT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATINT_MASK) + #define POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK (0x30U) #define POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT (4U) +/*! inb_formatext - Input B External format (00: q15; 01:q31; 10:float) + */ #define POWERQUAD_INBFORMAT_INB_FORMATEXT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_FORMATEXT_SHIFT)) & POWERQUAD_INBFORMAT_INB_FORMATEXT_MASK) + #define POWERQUAD_INBFORMAT_INB_SCALER_MASK (0xFF00U) #define POWERQUAD_INBFORMAT_INB_SCALER_SHIFT (8U) +/*! inb_scaler - Input B Scaler value (for scaled 'q31' formats) + */ #define POWERQUAD_INBFORMAT_INB_SCALER(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INBFORMAT_INB_SCALER_SHIFT)) & POWERQUAD_INBFORMAT_INB_SCALER_MASK) /*! @} */ /*! @name CONTROL - PowerQuad Control register */ /*! @{ */ + #define POWERQUAD_CONTROL_DECODE_OPCODE_MASK (0xFU) #define POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT (0U) +/*! decode_opcode - opcode specific to decode_machine + */ #define POWERQUAD_CONTROL_DECODE_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_OPCODE_SHIFT)) & POWERQUAD_CONTROL_DECODE_OPCODE_MASK) + #define POWERQUAD_CONTROL_DECODE_MACHINE_MASK (0xF0U) #define POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT (4U) +/*! decode_machine - 0 : Coprocessor , 1 : matrix , 2 : fft , 3 : fir , 4 : stat , 5 : cordic , 6 -15 : NA + */ #define POWERQUAD_CONTROL_DECODE_MACHINE(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_DECODE_MACHINE_SHIFT)) & POWERQUAD_CONTROL_DECODE_MACHINE_MASK) + #define POWERQUAD_CONTROL_INST_BUSY_MASK (0x80000000U) #define POWERQUAD_CONTROL_INST_BUSY_SHIFT (31U) +/*! inst_busy - Instruction busy signal when high indicates processing is on + */ #define POWERQUAD_CONTROL_INST_BUSY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CONTROL_INST_BUSY_SHIFT)) & POWERQUAD_CONTROL_INST_BUSY_MASK) /*! @} */ /*! @name LENGTH - Length register */ /*! @{ */ + #define POWERQUAD_LENGTH_INST_LENGTH_MASK (0xFFFFFFFFU) #define POWERQUAD_LENGTH_INST_LENGTH_SHIFT (0U) +/*! inst_length - Length register. When FIR : fir_xlength = inst_length[15:0] , fir_tlength = + * inst_len[31:16]. When MTX : rows_a = inst_length[4:0] , cols_a = inst_length[12:8] , cols_b = + * inst_length[20:16] + */ #define POWERQUAD_LENGTH_INST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_LENGTH_INST_LENGTH_SHIFT)) & POWERQUAD_LENGTH_INST_LENGTH_MASK) /*! @} */ /*! @name CPPRE - Pre-scale register */ /*! @{ */ + #define POWERQUAD_CPPRE_CPPRE_IN_MASK (0xFFU) #define POWERQUAD_CPPRE_CPPRE_IN_SHIFT (0U) +/*! cppre_in - co-processor scaling of input + */ #define POWERQUAD_CPPRE_CPPRE_IN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_IN_SHIFT)) & POWERQUAD_CPPRE_CPPRE_IN_MASK) + #define POWERQUAD_CPPRE_CPPRE_OUT_MASK (0xFF00U) #define POWERQUAD_CPPRE_CPPRE_OUT_SHIFT (8U) +/*! cppre_out - co-processor fixed point output + */ #define POWERQUAD_CPPRE_CPPRE_OUT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_OUT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_OUT_MASK) + #define POWERQUAD_CPPRE_CPPRE_SAT_MASK (0x10000U) #define POWERQUAD_CPPRE_CPPRE_SAT_SHIFT (16U) +/*! cppre_sat - 1 : forces sub-32 bit saturation + */ #define POWERQUAD_CPPRE_CPPRE_SAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT_MASK) + #define POWERQUAD_CPPRE_CPPRE_SAT8_MASK (0x20000U) #define POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT (17U) +/*! cppre_sat8 - 0 = 8bits, 1 = 16bits + */ #define POWERQUAD_CPPRE_CPPRE_SAT8(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CPPRE_CPPRE_SAT8_SHIFT)) & POWERQUAD_CPPRE_CPPRE_SAT8_MASK) /*! @} */ /*! @name MISC - Misc register */ /*! @{ */ + #define POWERQUAD_MISC_INST_MISC_MASK (0xFFFFFFFFU) #define POWERQUAD_MISC_INST_MISC_SHIFT (0U) +/*! inst_misc - Misc register. For Matrix : Used for scale factor + */ #define POWERQUAD_MISC_INST_MISC(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_MISC_INST_MISC_SHIFT)) & POWERQUAD_MISC_INST_MISC_MASK) /*! @} */ /*! @name CURSORY - Cursory register */ /*! @{ */ + #define POWERQUAD_CURSORY_CURSORY_MASK (0x1U) #define POWERQUAD_CURSORY_CURSORY_SHIFT (0U) +/*! cursory - 1 : Enable cursory mode + */ #define POWERQUAD_CURSORY_CURSORY(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CURSORY_CURSORY_SHIFT)) & POWERQUAD_CURSORY_CURSORY_MASK) /*! @} */ /*! @name CORDIC_X - Cordic input X register */ /*! @{ */ + #define POWERQUAD_CORDIC_X_CORDIC_X_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_X_CORDIC_X_SHIFT (0U) +/*! cordic_x - Cordic input x + */ #define POWERQUAD_CORDIC_X_CORDIC_X(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_X_CORDIC_X_SHIFT)) & POWERQUAD_CORDIC_X_CORDIC_X_MASK) /*! @} */ /*! @name CORDIC_Y - Cordic input Y register */ /*! @{ */ + #define POWERQUAD_CORDIC_Y_CORDIC_Y_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT (0U) +/*! cordic_y - Cordic input y + */ #define POWERQUAD_CORDIC_Y_CORDIC_Y(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Y_CORDIC_Y_SHIFT)) & POWERQUAD_CORDIC_Y_CORDIC_Y_MASK) /*! @} */ /*! @name CORDIC_Z - Cordic input Z register */ /*! @{ */ + #define POWERQUAD_CORDIC_Z_CORDIC_Z_MASK (0xFFFFFFFFU) #define POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT (0U) +/*! cordic_z - Cordic input z + */ #define POWERQUAD_CORDIC_Z_CORDIC_Z(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_CORDIC_Z_CORDIC_Z_SHIFT)) & POWERQUAD_CORDIC_Z_CORDIC_Z_MASK) /*! @} */ /*! @name ERRSTAT - Read/Write register where error statuses are captured (sticky) */ /*! @{ */ + #define POWERQUAD_ERRSTAT_OVERFLOW_MASK (0x1U) #define POWERQUAD_ERRSTAT_OVERFLOW_SHIFT (0U) +/*! OVERFLOW - overflow + */ #define POWERQUAD_ERRSTAT_OVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_OVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_OVERFLOW_MASK) + #define POWERQUAD_ERRSTAT_NAN_MASK (0x2U) #define POWERQUAD_ERRSTAT_NAN_SHIFT (1U) +/*! NAN - nan + */ #define POWERQUAD_ERRSTAT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_NAN_SHIFT)) & POWERQUAD_ERRSTAT_NAN_MASK) + #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK (0x4U) #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT (2U) +/*! FIXEDOVERFLOW - fixed_pt_overflow + */ #define POWERQUAD_ERRSTAT_FIXEDOVERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_FIXEDOVERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_FIXEDOVERFLOW_MASK) + #define POWERQUAD_ERRSTAT_UNDERFLOW_MASK (0x8U) #define POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT (3U) +/*! UNDERFLOW - underflow + */ #define POWERQUAD_ERRSTAT_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_UNDERFLOW_SHIFT)) & POWERQUAD_ERRSTAT_UNDERFLOW_MASK) + #define POWERQUAD_ERRSTAT_BUSERROR_MASK (0x10U) #define POWERQUAD_ERRSTAT_BUSERROR_SHIFT (4U) +/*! BUSERROR - bus_error + */ #define POWERQUAD_ERRSTAT_BUSERROR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_ERRSTAT_BUSERROR_SHIFT)) & POWERQUAD_ERRSTAT_BUSERROR_MASK) /*! @} */ /*! @name INTREN - INTERRUPT enable register */ /*! @{ */ + #define POWERQUAD_INTREN_INTR_OFLOW_MASK (0x1U) #define POWERQUAD_INTREN_INTR_OFLOW_SHIFT (0U) +/*! intr_oflow - 1 : Enable interrupt on Floating point overflow + */ #define POWERQUAD_INTREN_INTR_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_OFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_OFLOW_MASK) + #define POWERQUAD_INTREN_INTR_NAN_MASK (0x2U) #define POWERQUAD_INTREN_INTR_NAN_SHIFT (1U) +/*! intr_nan - 1 : Enable interrupt on Floating point NaN + */ #define POWERQUAD_INTREN_INTR_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_NAN_SHIFT)) & POWERQUAD_INTREN_INTR_NAN_MASK) + #define POWERQUAD_INTREN_INTR_FIXED_MASK (0x4U) #define POWERQUAD_INTREN_INTR_FIXED_SHIFT (2U) +/*! intr_fixed - 1: Enable interrupt on Fixed point Overflow + */ #define POWERQUAD_INTREN_INTR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_FIXED_SHIFT)) & POWERQUAD_INTREN_INTR_FIXED_MASK) + #define POWERQUAD_INTREN_INTR_UFLOW_MASK (0x8U) #define POWERQUAD_INTREN_INTR_UFLOW_SHIFT (3U) +/*! intr_uflow - 1 : Enable interrupt on Subnormal truncation + */ #define POWERQUAD_INTREN_INTR_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_UFLOW_SHIFT)) & POWERQUAD_INTREN_INTR_UFLOW_MASK) + #define POWERQUAD_INTREN_INTR_BERR_MASK (0x10U) #define POWERQUAD_INTREN_INTR_BERR_SHIFT (4U) +/*! intr_berr - 1: Enable interrupt on AHBM Buss Error + */ #define POWERQUAD_INTREN_INTR_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_BERR_SHIFT)) & POWERQUAD_INTREN_INTR_BERR_MASK) + #define POWERQUAD_INTREN_INTR_COMP_MASK (0x80U) #define POWERQUAD_INTREN_INTR_COMP_SHIFT (7U) +/*! intr_comp - 1: Enable interrupt on instruction completion + */ #define POWERQUAD_INTREN_INTR_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTREN_INTR_COMP_SHIFT)) & POWERQUAD_INTREN_INTR_COMP_MASK) /*! @} */ /*! @name EVENTEN - Event Enable register */ /*! @{ */ + #define POWERQUAD_EVENTEN_EVENT_OFLOW_MASK (0x1U) #define POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT (0U) +/*! event_oflow - 1 : Enable event trigger on Floating point overflow + */ #define POWERQUAD_EVENTEN_EVENT_OFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_OFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_OFLOW_MASK) + #define POWERQUAD_EVENTEN_EVENT_NAN_MASK (0x2U) #define POWERQUAD_EVENTEN_EVENT_NAN_SHIFT (1U) +/*! event_nan - 1 : Enable event trigger on Floating point NaN + */ #define POWERQUAD_EVENTEN_EVENT_NAN(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_NAN_SHIFT)) & POWERQUAD_EVENTEN_EVENT_NAN_MASK) + #define POWERQUAD_EVENTEN_EVENT_FIXED_MASK (0x4U) #define POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT (2U) +/*! event_fixed - 1: Enable event trigger on Fixed point Overflow + */ #define POWERQUAD_EVENTEN_EVENT_FIXED(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_FIXED_SHIFT)) & POWERQUAD_EVENTEN_EVENT_FIXED_MASK) + #define POWERQUAD_EVENTEN_EVENT_UFLOW_MASK (0x8U) #define POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT (3U) +/*! event_uflow - 1 : Enable event trigger on Subnormal truncation + */ #define POWERQUAD_EVENTEN_EVENT_UFLOW(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_UFLOW_SHIFT)) & POWERQUAD_EVENTEN_EVENT_UFLOW_MASK) + #define POWERQUAD_EVENTEN_EVENT_BERR_MASK (0x10U) #define POWERQUAD_EVENTEN_EVENT_BERR_SHIFT (4U) +/*! event_berr - 1: Enable event trigger on AHBM Buss Error + */ #define POWERQUAD_EVENTEN_EVENT_BERR(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_BERR_SHIFT)) & POWERQUAD_EVENTEN_EVENT_BERR_MASK) + #define POWERQUAD_EVENTEN_EVENT_COMP_MASK (0x80U) #define POWERQUAD_EVENTEN_EVENT_COMP_SHIFT (7U) +/*! event_comp - 1: Enable event trigger on instruction completion + */ #define POWERQUAD_EVENTEN_EVENT_COMP(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_EVENTEN_EVENT_COMP_SHIFT)) & POWERQUAD_EVENTEN_EVENT_COMP_MASK) /*! @} */ /*! @name INTRSTAT - INTERRUPT STATUS register */ /*! @{ */ + #define POWERQUAD_INTRSTAT_INTR_STAT_MASK (0x1U) #define POWERQUAD_INTRSTAT_INTR_STAT_SHIFT (0U) +/*! intr_stat - Intr status ( 1 bit to indicate interrupt captured, 0 means no new interrupt), write any value will clear this bit + */ #define POWERQUAD_INTRSTAT_INTR_STAT(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_INTRSTAT_INTR_STAT_SHIFT)) & POWERQUAD_INTRSTAT_INTR_STAT_MASK) /*! @} */ /*! @name GPREG - General purpose register bank N. */ /*! @{ */ + #define POWERQUAD_GPREG_GPREG_MASK (0xFFFFFFFFU) #define POWERQUAD_GPREG_GPREG_SHIFT (0U) +/*! gpreg - General purpose register bank + */ #define POWERQUAD_GPREG_GPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_GPREG_GPREG_SHIFT)) & POWERQUAD_GPREG_GPREG_MASK) /*! @} */ @@ -13468,8 +16136,11 @@ typedef struct { /*! @name COMPREGS_COMPREG - Compute register bank */ /*! @{ */ + #define POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK (0xFFFFFFFFU) #define POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT (0U) +/*! compreg - Compute register bank + */ #define POWERQUAD_COMPREGS_COMPREG_COMPREG(x) (((uint32_t)(((uint32_t)(x)) << POWERQUAD_COMPREGS_COMPREG_COMPREG_SHIFT)) & POWERQUAD_COMPREGS_COMPREG_COMPREG_MASK) /*! @} */ @@ -13483,7 +16154,7 @@ typedef struct { /* POWERQUAD - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral POWERQUAD base address */ #define POWERQUAD_BASE (0x500A6000u) /** Peripheral POWERQUAD base address */ @@ -13556,31 +16227,39 @@ typedef struct { /*! @name ENC_ENABLE - Encryption Enable register */ /*! @{ */ + #define PRINCE_ENC_ENABLE_EN_MASK (0x1U) #define PRINCE_ENC_ENABLE_EN_SHIFT (0U) /*! EN - Encryption Enable. - * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled.. - * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled.. + * 0b0..Encryption of writes to the flash controller DATAW* registers is disabled. + * 0b1..Encryption of writes to the flash controller DATAW* registers is enabled. */ #define PRINCE_ENC_ENABLE_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_ENC_ENABLE_EN_SHIFT)) & PRINCE_ENC_ENABLE_EN_MASK) /*! @} */ /*! @name MASK_LSB - Data Mask register, 32 Least Significant Bits */ /*! @{ */ + #define PRINCE_MASK_LSB_MASKVAL_MASK (0xFFFFFFFFU) #define PRINCE_MASK_LSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Least Significant Bits of the 64-bit data mask. + */ #define PRINCE_MASK_LSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_LSB_MASKVAL_SHIFT)) & PRINCE_MASK_LSB_MASKVAL_MASK) /*! @} */ /*! @name MASK_MSB - Data Mask register, 32 Most Significant Bits */ /*! @{ */ + #define PRINCE_MASK_MSB_MASKVAL_MASK (0xFFFFFFFFU) #define PRINCE_MASK_MSB_MASKVAL_SHIFT (0U) +/*! MASKVAL - Value of the 32 Most Significant Bits of the 64-bit data mask. + */ #define PRINCE_MASK_MSB_MASKVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_MASK_MSB_MASKVAL_SHIFT)) & PRINCE_MASK_MSB_MASKVAL_MASK) /*! @} */ /*! @name LOCK - Lock register */ /*! @{ */ + #define PRINCE_LOCK_LOCKREG0_MASK (0x1U) #define PRINCE_LOCK_LOCKREG0_SHIFT (0U) /*! LOCKREG0 - Lock Region 0 registers. @@ -13588,6 +16267,7 @@ typedef struct { * 0b1..Enabled. IV_LSB0, IV_MSB0, BASE_ADDR0, and SR_ENABLE0 are not writable.. */ #define PRINCE_LOCK_LOCKREG0(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG0_SHIFT)) & PRINCE_LOCK_LOCKREG0_MASK) + #define PRINCE_LOCK_LOCKREG1_MASK (0x2U) #define PRINCE_LOCK_LOCKREG1_SHIFT (1U) /*! LOCKREG1 - Lock Region 1 registers. @@ -13595,6 +16275,7 @@ typedef struct { * 0b1..Enabled. IV_LSB1, IV_MSB1, BASE_ADDR1, and SR_ENABLE1 are not writable.. */ #define PRINCE_LOCK_LOCKREG1(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG1_SHIFT)) & PRINCE_LOCK_LOCKREG1_MASK) + #define PRINCE_LOCK_LOCKREG2_MASK (0x4U) #define PRINCE_LOCK_LOCKREG2_SHIFT (2U) /*! LOCKREG2 - Lock Region 2 registers. @@ -13602,6 +16283,7 @@ typedef struct { * 0b1..Enabled. IV_LSB2, IV_MSB2, BASE_ADDR2, and SR_ENABLE2 are not writable.. */ #define PRINCE_LOCK_LOCKREG2(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_LOCK_LOCKREG2_SHIFT)) & PRINCE_LOCK_LOCKREG2_MASK) + #define PRINCE_LOCK_LOCKMASK_MASK (0x100U) #define PRINCE_LOCK_LOCKMASK_SHIFT (8U) /*! LOCKMASK - Lock the Mask registers. @@ -13613,94 +16295,139 @@ typedef struct { /*! @name IV_LSB0 - Initial Vector register for region 0, Least Significant Bits */ /*! @{ */ + #define PRINCE_IV_LSB0_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_LSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_LSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB0_IVVAL_SHIFT)) & PRINCE_IV_LSB0_IVVAL_MASK) /*! @} */ /*! @name IV_MSB0 - Initial Vector register for region 0, Most Significant Bits */ /*! @{ */ + #define PRINCE_IV_MSB0_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_MSB0_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_MSB0_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB0_IVVAL_SHIFT)) & PRINCE_IV_MSB0_IVVAL_MASK) /*! @} */ /*! @name BASE_ADDR0 - Base Address for region 0 register */ /*! @{ */ + #define PRINCE_BASE_ADDR0_ADDR_FIXED_MASK (0x3FFFFU) #define PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 0. + */ #define PRINCE_BASE_ADDR0_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_FIXED_MASK) + #define PRINCE_BASE_ADDR0_ADDR_PRG_MASK (0xC0000U) #define PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 0. + */ #define PRINCE_BASE_ADDR0_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR0_ADDR_PRG_MASK) /*! @} */ /*! @name SR_ENABLE0 - Sub-Region Enable register for region 0 */ /*! @{ */ + #define PRINCE_SR_ENABLE0_EN_MASK (0xFFFFFFFFU) #define PRINCE_SR_ENABLE0_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 0. + */ #define PRINCE_SR_ENABLE0_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE0_EN_SHIFT)) & PRINCE_SR_ENABLE0_EN_MASK) /*! @} */ /*! @name IV_LSB1 - Initial Vector register for region 1, Least Significant Bits */ /*! @{ */ + #define PRINCE_IV_LSB1_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_LSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_LSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB1_IVVAL_SHIFT)) & PRINCE_IV_LSB1_IVVAL_MASK) /*! @} */ /*! @name IV_MSB1 - Initial Vector register for region 1, Most Significant Bits */ /*! @{ */ + #define PRINCE_IV_MSB1_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_MSB1_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_MSB1_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB1_IVVAL_SHIFT)) & PRINCE_IV_MSB1_IVVAL_MASK) /*! @} */ /*! @name BASE_ADDR1 - Base Address for region 1 register */ /*! @{ */ + #define PRINCE_BASE_ADDR1_ADDR_FIXED_MASK (0x3FFFFU) #define PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 1. + */ #define PRINCE_BASE_ADDR1_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_FIXED_MASK) + #define PRINCE_BASE_ADDR1_ADDR_PRG_MASK (0xC0000U) #define PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 1. + */ #define PRINCE_BASE_ADDR1_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR1_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR1_ADDR_PRG_MASK) /*! @} */ /*! @name SR_ENABLE1 - Sub-Region Enable register for region 1 */ /*! @{ */ + #define PRINCE_SR_ENABLE1_EN_MASK (0xFFFFFFFFU) #define PRINCE_SR_ENABLE1_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 1. + */ #define PRINCE_SR_ENABLE1_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE1_EN_SHIFT)) & PRINCE_SR_ENABLE1_EN_MASK) /*! @} */ /*! @name IV_LSB2 - Initial Vector register for region 2, Least Significant Bits */ /*! @{ */ + #define PRINCE_IV_LSB2_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_LSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Least Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_LSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_LSB2_IVVAL_SHIFT)) & PRINCE_IV_LSB2_IVVAL_MASK) /*! @} */ /*! @name IV_MSB2 - Initial Vector register for region 2, Most Significant Bits */ /*! @{ */ + #define PRINCE_IV_MSB2_IVVAL_MASK (0xFFFFFFFFU) #define PRINCE_IV_MSB2_IVVAL_SHIFT (0U) +/*! IVVAL - Initial Vector value for the 32 Most Significant Bits of the 64-bit Initial Vector. + */ #define PRINCE_IV_MSB2_IVVAL(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_IV_MSB2_IVVAL_SHIFT)) & PRINCE_IV_MSB2_IVVAL_MASK) /*! @} */ /*! @name BASE_ADDR2 - Base Address for region 2 register */ /*! @{ */ + #define PRINCE_BASE_ADDR2_ADDR_FIXED_MASK (0x3FFFFU) #define PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT (0U) +/*! ADDR_FIXED - Fixed portion of the base address of region 2. + */ #define PRINCE_BASE_ADDR2_ADDR_FIXED(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_FIXED_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_FIXED_MASK) + #define PRINCE_BASE_ADDR2_ADDR_PRG_MASK (0xC0000U) #define PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT (18U) +/*! ADDR_PRG - Programmable portion of the base address of region 2. + */ #define PRINCE_BASE_ADDR2_ADDR_PRG(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_BASE_ADDR2_ADDR_PRG_SHIFT)) & PRINCE_BASE_ADDR2_ADDR_PRG_MASK) /*! @} */ /*! @name SR_ENABLE2 - Sub-Region Enable register for region 2 */ /*! @{ */ + #define PRINCE_SR_ENABLE2_EN_MASK (0xFFFFFFFFU) #define PRINCE_SR_ENABLE2_EN_SHIFT (0U) +/*! EN - Each bit in this field enables an 8KB subregion for encryption at offset 8KB*bitnum of region 2. + */ #define PRINCE_SR_ENABLE2_EN(x) (((uint32_t)(((uint32_t)(x)) << PRINCE_SR_ENABLE2_EN_SHIFT)) & PRINCE_SR_ENABLE2_EN_MASK) /*! @} */ @@ -13711,7 +16438,7 @@ typedef struct { /* PRINCE - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral PRINCE base address */ #define PRINCE_BASE (0x50035000u) /** Peripheral PRINCE base address */ @@ -13801,309 +16528,539 @@ typedef struct { /*! @name CTRL - PUF Control register */ /*! @{ */ + #define PUF_CTRL_ZEROIZE_MASK (0x1U) #define PUF_CTRL_ZEROIZE_SHIFT (0U) +/*! zeroize - Begin Zeroize operation for PUF and go to Error state + */ #define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) + #define PUF_CTRL_ENROLL_MASK (0x2U) #define PUF_CTRL_ENROLL_SHIFT (1U) +/*! enroll - Begin Enroll operation + */ #define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) + #define PUF_CTRL_START_MASK (0x4U) #define PUF_CTRL_START_SHIFT (2U) +/*! start - Begin Start operation + */ #define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) + #define PUF_CTRL_GENERATEKEY_MASK (0x8U) #define PUF_CTRL_GENERATEKEY_SHIFT (3U) +/*! GENERATEKEY - Begin Set Intrinsic Key operation + */ #define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) + #define PUF_CTRL_SETKEY_MASK (0x10U) #define PUF_CTRL_SETKEY_SHIFT (4U) +/*! SETKEY - Begin Set User Key operation + */ #define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) + #define PUF_CTRL_GETKEY_MASK (0x40U) #define PUF_CTRL_GETKEY_SHIFT (6U) +/*! GETKEY - Begin Get Key operation + */ #define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) /*! @} */ /*! @name KEYINDEX - PUF Key Index register */ /*! @{ */ + #define PUF_KEYINDEX_KEYIDX_MASK (0xFU) #define PUF_KEYINDEX_KEYIDX_SHIFT (0U) +/*! KEYIDX - Key index for Set Key operations + */ #define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) /*! @} */ /*! @name KEYSIZE - PUF Key Size register */ /*! @{ */ + #define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) #define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) +/*! KEYSIZE - Key size for Set Key operations + */ #define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) /*! @} */ /*! @name STAT - PUF Status register */ /*! @{ */ + #define PUF_STAT_BUSY_MASK (0x1U) #define PUF_STAT_BUSY_SHIFT (0U) +/*! busy - Indicates that operation is in progress + */ #define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) + #define PUF_STAT_SUCCESS_MASK (0x2U) #define PUF_STAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Last operation was successful + */ #define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) + #define PUF_STAT_ERROR_MASK (0x4U) #define PUF_STAT_ERROR_SHIFT (2U) +/*! error - PUF is in the Error state and no operations can be performed + */ #define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) + #define PUF_STAT_KEYINREQ_MASK (0x10U) #define PUF_STAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Request for next part of key + */ #define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) + #define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) #define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Next part of key is available + */ #define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) + #define PUF_STAT_CODEINREQ_MASK (0x40U) #define PUF_STAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Request for next part of AC/KC + */ #define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) + #define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) #define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Next part of AC/KC is available + */ #define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) /*! @} */ /*! @name ALLOW - PUF Allow register */ /*! @{ */ + #define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) #define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) +/*! ALLOWENROLL - Enroll operation is allowed + */ #define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) + #define PUF_ALLOW_ALLOWSTART_MASK (0x2U) #define PUF_ALLOW_ALLOWSTART_SHIFT (1U) +/*! ALLOWSTART - Start operation is allowed + */ #define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) + #define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) #define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) +/*! ALLOWSETKEY - Set Key operations are allowed + */ #define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) + #define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) #define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) +/*! ALLOWGETKEY - Get Key operation is allowed + */ #define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) /*! @} */ /*! @name KEYINPUT - PUF Key Input register */ /*! @{ */ + #define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) #define PUF_KEYINPUT_KEYIN_SHIFT (0U) +/*! KEYIN - Key input data + */ #define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) /*! @} */ /*! @name CODEINPUT - PUF Code Input register */ /*! @{ */ + #define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) #define PUF_CODEINPUT_CODEIN_SHIFT (0U) +/*! CODEIN - AC/KC input data + */ #define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) /*! @} */ /*! @name CODEOUTPUT - PUF Code Output register */ /*! @{ */ + #define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) #define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) +/*! CODEOUT - AC/KC output data + */ #define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) /*! @} */ /*! @name KEYOUTINDEX - PUF Key Output Index register */ /*! @{ */ + #define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFU) #define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) +/*! KEYOUTIDX - Key index for the key that is currently output via the Key Output register + */ #define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) /*! @} */ /*! @name KEYOUTPUT - PUF Key Output register */ /*! @{ */ + #define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) #define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) +/*! KEYOUT - Key output data + */ #define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) /*! @} */ /*! @name IFSTAT - PUF Interface Status and clear register */ /*! @{ */ + #define PUF_IFSTAT_ERROR_MASK (0x1U) #define PUF_IFSTAT_ERROR_SHIFT (0U) +/*! ERROR - Indicates that an APB error has occurred,Writing logic1 clears the if_error bit + */ #define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) /*! @} */ /*! @name VERSION - PUF version register. */ /*! @{ */ -#define PUF_VERSION_KEYOUT_MASK (0xFFFFFFFFU) -#define PUF_VERSION_KEYOUT_SHIFT (0U) -#define PUF_VERSION_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_KEYOUT_SHIFT)) & PUF_VERSION_KEYOUT_MASK) + +#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU) +#define PUF_VERSION_VERSION_SHIFT (0U) +/*! VERSION - Version of the PUF module. + */ +#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK) /*! @} */ /*! @name INTEN - PUF Interrupt Enable */ /*! @{ */ + #define PUF_INTEN_READYEN_MASK (0x1U) #define PUF_INTEN_READYEN_SHIFT (0U) +/*! READYEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) + #define PUF_INTEN_SUCCESEN_MASK (0x2U) #define PUF_INTEN_SUCCESEN_SHIFT (1U) +/*! SUCCESEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) + #define PUF_INTEN_ERROREN_MASK (0x4U) #define PUF_INTEN_ERROREN_SHIFT (2U) +/*! ERROREN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) + #define PUF_INTEN_KEYINREQEN_MASK (0x10U) #define PUF_INTEN_KEYINREQEN_SHIFT (4U) +/*! KEYINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) + #define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) #define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) +/*! KEYOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) + #define PUF_INTEN_CODEINREQEN_MASK (0x40U) #define PUF_INTEN_CODEINREQEN_SHIFT (6U) +/*! CODEINREQEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) + #define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) #define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) +/*! CODEOUTAVAILEN - Enable corresponding interrupt. Note that bit numbers match those assigned in QK_SR (Quiddikey Status Register) + */ #define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) /*! @} */ /*! @name INTSTAT - PUF interrupt status */ /*! @{ */ + #define PUF_INTSTAT_READY_MASK (0x1U) #define PUF_INTSTAT_READY_SHIFT (0U) +/*! READY - Triggers on falling edge of busy, write 1 to clear + */ #define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) + #define PUF_INTSTAT_SUCCESS_MASK (0x2U) #define PUF_INTSTAT_SUCCESS_SHIFT (1U) +/*! SUCCESS - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) + #define PUF_INTSTAT_ERROR_MASK (0x4U) #define PUF_INTSTAT_ERROR_SHIFT (2U) +/*! ERROR - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) + #define PUF_INTSTAT_KEYINREQ_MASK (0x10U) #define PUF_INTSTAT_KEYINREQ_SHIFT (4U) +/*! KEYINREQ - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) + #define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) #define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) +/*! KEYOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) + #define PUF_INTSTAT_CODEINREQ_MASK (0x40U) #define PUF_INTSTAT_CODEINREQ_SHIFT (6U) +/*! CODEINREQ - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) + #define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) #define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) +/*! CODEOUTAVAIL - Level sensitive interrupt, cleared when interrupt source clears + */ #define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) /*! @} */ /*! @name PWRCTRL - PUF RAM Power Control */ /*! @{ */ + #define PUF_PWRCTRL_RAMON_MASK (0x1U) #define PUF_PWRCTRL_RAMON_SHIFT (0U) +/*! RAMON - Power on the PUF RAM. + */ #define PUF_PWRCTRL_RAMON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMON_SHIFT)) & PUF_PWRCTRL_RAMON_MASK) + #define PUF_PWRCTRL_RAMSTAT_MASK (0x2U) #define PUF_PWRCTRL_RAMSTAT_SHIFT (1U) +/*! RAMSTAT - PUF RAM status. + */ #define PUF_PWRCTRL_RAMSTAT(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAMSTAT_SHIFT)) & PUF_PWRCTRL_RAMSTAT_MASK) /*! @} */ /*! @name CFG - PUF config register for block bits */ /*! @{ */ + #define PUF_CFG_BLOCKENROLL_SETKEY_MASK (0x1U) #define PUF_CFG_BLOCKENROLL_SETKEY_SHIFT (0U) +/*! BLOCKENROLL_SETKEY - Block enroll operation. Write 1 to set, cleared on reset. + */ #define PUF_CFG_BLOCKENROLL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKENROLL_SETKEY_SHIFT)) & PUF_CFG_BLOCKENROLL_SETKEY_MASK) + #define PUF_CFG_BLOCKKEYOUTPUT_MASK (0x2U) #define PUF_CFG_BLOCKKEYOUTPUT_SHIFT (1U) +/*! BLOCKKEYOUTPUT - Block set key operation. Write 1 to set, cleared on reset. + */ #define PUF_CFG_BLOCKKEYOUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_BLOCKKEYOUTPUT_SHIFT)) & PUF_CFG_BLOCKKEYOUTPUT_MASK) /*! @} */ /*! @name KEYLOCK - Only reset in case of full IC reset */ /*! @{ */ + #define PUF_KEYLOCK_KEY0_MASK (0x3U) #define PUF_KEYLOCK_KEY0_SHIFT (0U) +/*! KEY0 - "10:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is allowed. 00, 01, + * 11:Write access to KEY0MASK, KEYENABLE.KEY0 and KEYRESET.KEY0 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ #define PUF_KEYLOCK_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY0_SHIFT)) & PUF_KEYLOCK_KEY0_MASK) + #define PUF_KEYLOCK_KEY1_MASK (0xCU) #define PUF_KEYLOCK_KEY1_SHIFT (2U) +/*! KEY1 - "10:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is allowed. 00, 01, + * 11:Write access to KEY1MASK, KEYENABLE.KEY1 and KEYRESET.KEY1 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ #define PUF_KEYLOCK_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY1_SHIFT)) & PUF_KEYLOCK_KEY1_MASK) + #define PUF_KEYLOCK_KEY2_MASK (0x30U) #define PUF_KEYLOCK_KEY2_SHIFT (4U) +/*! KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, + * 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ #define PUF_KEYLOCK_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY2_SHIFT)) & PUF_KEYLOCK_KEY2_MASK) + #define PUF_KEYLOCK_KEY3_MASK (0xC0U) #define PUF_KEYLOCK_KEY3_SHIFT (6U) +/*! KEY3 - "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, + * 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once + * this field is written with a value different from '10', its value can no longer be modified + * until un Power On Reset occurs." + */ #define PUF_KEYLOCK_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_KEY3_SHIFT)) & PUF_KEYLOCK_KEY3_MASK) /*! @} */ /*! @name KEYENABLE - */ /*! @{ */ + #define PUF_KEYENABLE_KEY0_MASK (0x3U) #define PUF_KEYENABLE_KEY0_SHIFT (0U) +/*! KEY0 - "10: Data coming out from PUF Index 0 interface are shifted in KEY0 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY0 register." + */ #define PUF_KEYENABLE_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY0_SHIFT)) & PUF_KEYENABLE_KEY0_MASK) + #define PUF_KEYENABLE_KEY1_MASK (0xCU) #define PUF_KEYENABLE_KEY1_SHIFT (2U) +/*! KEY1 - "10: Data coming out from PUF Index 0 interface are shifted in KEY1 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY1 register." + */ #define PUF_KEYENABLE_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY1_SHIFT)) & PUF_KEYENABLE_KEY1_MASK) + #define PUF_KEYENABLE_KEY2_MASK (0x30U) #define PUF_KEYENABLE_KEY2_SHIFT (4U) +/*! KEY2 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY2 register." + */ #define PUF_KEYENABLE_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY2_SHIFT)) & PUF_KEYENABLE_KEY2_MASK) + #define PUF_KEYENABLE_KEY3_MASK (0xC0U) #define PUF_KEYENABLE_KEY3_SHIFT (6U) +/*! KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 + * : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." + */ #define PUF_KEYENABLE_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_KEY3_SHIFT)) & PUF_KEYENABLE_KEY3_MASK) /*! @} */ /*! @name KEYRESET - Reinitialize Keys shift registers counters */ /*! @{ */ + #define PUF_KEYRESET_KEY0_MASK (0x3U) #define PUF_KEYRESET_KEY0_SHIFT (0U) +/*! KEY0 - 10: Reset KEY0 shift register. Self clearing. Must be done before loading any new key. + */ #define PUF_KEYRESET_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY0_SHIFT)) & PUF_KEYRESET_KEY0_MASK) + #define PUF_KEYRESET_KEY1_MASK (0xCU) #define PUF_KEYRESET_KEY1_SHIFT (2U) +/*! KEY1 - 10: Reset KEY1 shift register. Self clearing. Must be done before loading any new key. + */ #define PUF_KEYRESET_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY1_SHIFT)) & PUF_KEYRESET_KEY1_MASK) + #define PUF_KEYRESET_KEY2_MASK (0x30U) #define PUF_KEYRESET_KEY2_SHIFT (4U) +/*! KEY2 - 10: Reset KEY2 shift register. Self clearing. Must be done before loading any new key. + */ #define PUF_KEYRESET_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY2_SHIFT)) & PUF_KEYRESET_KEY2_MASK) + #define PUF_KEYRESET_KEY3_MASK (0xC0U) #define PUF_KEYRESET_KEY3_SHIFT (6U) +/*! KEY3 - 10: Reset KEY3 shift register. Self clearing. Must be done before loading any new key. + */ #define PUF_KEYRESET_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_KEY3_SHIFT)) & PUF_KEYRESET_KEY3_MASK) /*! @} */ /*! @name IDXBLK_L - */ /*! @{ */ -#define PUF_IDXBLK_L_IDX0_MASK (0x3U) -#define PUF_IDXBLK_L_IDX0_SHIFT (0U) -#define PUF_IDXBLK_L_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX0_SHIFT)) & PUF_IDXBLK_L_IDX0_MASK) + #define PUF_IDXBLK_L_IDX1_MASK (0xCU) #define PUF_IDXBLK_L_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 + */ #define PUF_IDXBLK_L_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX1_SHIFT)) & PUF_IDXBLK_L_IDX1_MASK) + #define PUF_IDXBLK_L_IDX2_MASK (0x30U) #define PUF_IDXBLK_L_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 + */ #define PUF_IDXBLK_L_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX2_SHIFT)) & PUF_IDXBLK_L_IDX2_MASK) + #define PUF_IDXBLK_L_IDX3_MASK (0xC0U) #define PUF_IDXBLK_L_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 + */ #define PUF_IDXBLK_L_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX3_SHIFT)) & PUF_IDXBLK_L_IDX3_MASK) + #define PUF_IDXBLK_L_IDX4_MASK (0x300U) #define PUF_IDXBLK_L_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 + */ #define PUF_IDXBLK_L_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX4_SHIFT)) & PUF_IDXBLK_L_IDX4_MASK) + #define PUF_IDXBLK_L_IDX5_MASK (0xC00U) #define PUF_IDXBLK_L_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 + */ #define PUF_IDXBLK_L_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX5_SHIFT)) & PUF_IDXBLK_L_IDX5_MASK) + #define PUF_IDXBLK_L_IDX6_MASK (0x3000U) #define PUF_IDXBLK_L_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 + */ #define PUF_IDXBLK_L_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX6_SHIFT)) & PUF_IDXBLK_L_IDX6_MASK) + #define PUF_IDXBLK_L_IDX7_MASK (0xC000U) #define PUF_IDXBLK_L_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 + */ #define PUF_IDXBLK_L_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_IDX7_SHIFT)) & PUF_IDXBLK_L_IDX7_MASK) + #define PUF_IDXBLK_L_LOCK_IDX_MASK (0xC0000000U) #define PUF_IDXBLK_L_LOCK_IDX_SHIFT (30U) +/*! LOCK_IDX - Lock 0 to 7 PUF key indexes + */ #define PUF_IDXBLK_L_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_LOCK_IDX_SHIFT)) & PUF_IDXBLK_L_LOCK_IDX_MASK) /*! @} */ /*! @name IDXBLK_H_DP - */ /*! @{ */ + #define PUF_IDXBLK_H_DP_IDX8_MASK (0x3U) #define PUF_IDXBLK_H_DP_IDX8_SHIFT (0U) +/*! IDX8 - Use to block PUF index 8 + */ #define PUF_IDXBLK_H_DP_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX8_SHIFT)) & PUF_IDXBLK_H_DP_IDX8_MASK) + #define PUF_IDXBLK_H_DP_IDX9_MASK (0xCU) #define PUF_IDXBLK_H_DP_IDX9_SHIFT (2U) +/*! IDX9 - Use to block PUF index 9 + */ #define PUF_IDXBLK_H_DP_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX9_SHIFT)) & PUF_IDXBLK_H_DP_IDX9_MASK) + #define PUF_IDXBLK_H_DP_IDX10_MASK (0x30U) #define PUF_IDXBLK_H_DP_IDX10_SHIFT (4U) +/*! IDX10 - Use to block PUF index 10 + */ #define PUF_IDXBLK_H_DP_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX10_SHIFT)) & PUF_IDXBLK_H_DP_IDX10_MASK) + #define PUF_IDXBLK_H_DP_IDX11_MASK (0xC0U) #define PUF_IDXBLK_H_DP_IDX11_SHIFT (6U) +/*! IDX11 - Use to block PUF index 11 + */ #define PUF_IDXBLK_H_DP_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX11_SHIFT)) & PUF_IDXBLK_H_DP_IDX11_MASK) + #define PUF_IDXBLK_H_DP_IDX12_MASK (0x300U) #define PUF_IDXBLK_H_DP_IDX12_SHIFT (8U) +/*! IDX12 - Use to block PUF index 12 + */ #define PUF_IDXBLK_H_DP_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX12_SHIFT)) & PUF_IDXBLK_H_DP_IDX12_MASK) + #define PUF_IDXBLK_H_DP_IDX13_MASK (0xC00U) #define PUF_IDXBLK_H_DP_IDX13_SHIFT (10U) +/*! IDX13 - Use to block PUF index 13 + */ #define PUF_IDXBLK_H_DP_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX13_SHIFT)) & PUF_IDXBLK_H_DP_IDX13_MASK) + #define PUF_IDXBLK_H_DP_IDX14_MASK (0x3000U) #define PUF_IDXBLK_H_DP_IDX14_SHIFT (12U) +/*! IDX14 - Use to block PUF index 14 + */ #define PUF_IDXBLK_H_DP_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX14_SHIFT)) & PUF_IDXBLK_H_DP_IDX14_MASK) + #define PUF_IDXBLK_H_DP_IDX15_MASK (0xC000U) #define PUF_IDXBLK_H_DP_IDX15_SHIFT (14U) +/*! IDX15 - Use to block PUF index 15 + */ #define PUF_IDXBLK_H_DP_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_DP_IDX15_SHIFT)) & PUF_IDXBLK_H_DP_IDX15_MASK) /*! @} */ /*! @name KEYMASK - Only reset in case of full IC reset */ /*! @{ */ + #define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) #define PUF_KEYMASK_KEYMASK_SHIFT (0U) #define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK) @@ -14114,76 +17071,133 @@ typedef struct { /*! @name IDXBLK_H - */ /*! @{ */ + #define PUF_IDXBLK_H_IDX8_MASK (0x3U) #define PUF_IDXBLK_H_IDX8_SHIFT (0U) +/*! IDX8 - Use to block PUF index 8 + */ #define PUF_IDXBLK_H_IDX8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX8_SHIFT)) & PUF_IDXBLK_H_IDX8_MASK) + #define PUF_IDXBLK_H_IDX9_MASK (0xCU) #define PUF_IDXBLK_H_IDX9_SHIFT (2U) +/*! IDX9 - Use to block PUF index 9 + */ #define PUF_IDXBLK_H_IDX9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX9_SHIFT)) & PUF_IDXBLK_H_IDX9_MASK) + #define PUF_IDXBLK_H_IDX10_MASK (0x30U) #define PUF_IDXBLK_H_IDX10_SHIFT (4U) +/*! IDX10 - Use to block PUF index 10 + */ #define PUF_IDXBLK_H_IDX10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX10_SHIFT)) & PUF_IDXBLK_H_IDX10_MASK) + #define PUF_IDXBLK_H_IDX11_MASK (0xC0U) #define PUF_IDXBLK_H_IDX11_SHIFT (6U) +/*! IDX11 - Use to block PUF index 11 + */ #define PUF_IDXBLK_H_IDX11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX11_SHIFT)) & PUF_IDXBLK_H_IDX11_MASK) + #define PUF_IDXBLK_H_IDX12_MASK (0x300U) #define PUF_IDXBLK_H_IDX12_SHIFT (8U) +/*! IDX12 - Use to block PUF index 12 + */ #define PUF_IDXBLK_H_IDX12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX12_SHIFT)) & PUF_IDXBLK_H_IDX12_MASK) + #define PUF_IDXBLK_H_IDX13_MASK (0xC00U) #define PUF_IDXBLK_H_IDX13_SHIFT (10U) +/*! IDX13 - Use to block PUF index 13 + */ #define PUF_IDXBLK_H_IDX13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX13_SHIFT)) & PUF_IDXBLK_H_IDX13_MASK) + #define PUF_IDXBLK_H_IDX14_MASK (0x3000U) #define PUF_IDXBLK_H_IDX14_SHIFT (12U) +/*! IDX14 - Use to block PUF index 14 + */ #define PUF_IDXBLK_H_IDX14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX14_SHIFT)) & PUF_IDXBLK_H_IDX14_MASK) + #define PUF_IDXBLK_H_IDX15_MASK (0xC000U) #define PUF_IDXBLK_H_IDX15_SHIFT (14U) +/*! IDX15 - Use to block PUF index 15 + */ #define PUF_IDXBLK_H_IDX15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_IDX15_SHIFT)) & PUF_IDXBLK_H_IDX15_MASK) + #define PUF_IDXBLK_H_LOCK_IDX_MASK (0xC0000000U) #define PUF_IDXBLK_H_LOCK_IDX_SHIFT (30U) +/*! LOCK_IDX - Lock 8 to 15 PUF key indexes + */ #define PUF_IDXBLK_H_LOCK_IDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_H_LOCK_IDX_SHIFT)) & PUF_IDXBLK_H_LOCK_IDX_MASK) /*! @} */ /*! @name IDXBLK_L_DP - */ /*! @{ */ -#define PUF_IDXBLK_L_DP_IDX0_MASK (0x3U) -#define PUF_IDXBLK_L_DP_IDX0_SHIFT (0U) -#define PUF_IDXBLK_L_DP_IDX0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX0_SHIFT)) & PUF_IDXBLK_L_DP_IDX0_MASK) + #define PUF_IDXBLK_L_DP_IDX1_MASK (0xCU) #define PUF_IDXBLK_L_DP_IDX1_SHIFT (2U) +/*! IDX1 - Use to block PUF index 1 + */ #define PUF_IDXBLK_L_DP_IDX1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX1_SHIFT)) & PUF_IDXBLK_L_DP_IDX1_MASK) + #define PUF_IDXBLK_L_DP_IDX2_MASK (0x30U) #define PUF_IDXBLK_L_DP_IDX2_SHIFT (4U) +/*! IDX2 - Use to block PUF index 2 + */ #define PUF_IDXBLK_L_DP_IDX2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX2_SHIFT)) & PUF_IDXBLK_L_DP_IDX2_MASK) + #define PUF_IDXBLK_L_DP_IDX3_MASK (0xC0U) #define PUF_IDXBLK_L_DP_IDX3_SHIFT (6U) +/*! IDX3 - Use to block PUF index 3 + */ #define PUF_IDXBLK_L_DP_IDX3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX3_SHIFT)) & PUF_IDXBLK_L_DP_IDX3_MASK) + #define PUF_IDXBLK_L_DP_IDX4_MASK (0x300U) #define PUF_IDXBLK_L_DP_IDX4_SHIFT (8U) +/*! IDX4 - Use to block PUF index 4 + */ #define PUF_IDXBLK_L_DP_IDX4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX4_SHIFT)) & PUF_IDXBLK_L_DP_IDX4_MASK) + #define PUF_IDXBLK_L_DP_IDX5_MASK (0xC00U) #define PUF_IDXBLK_L_DP_IDX5_SHIFT (10U) +/*! IDX5 - Use to block PUF index 5 + */ #define PUF_IDXBLK_L_DP_IDX5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX5_SHIFT)) & PUF_IDXBLK_L_DP_IDX5_MASK) + #define PUF_IDXBLK_L_DP_IDX6_MASK (0x3000U) #define PUF_IDXBLK_L_DP_IDX6_SHIFT (12U) +/*! IDX6 - Use to block PUF index 6 + */ #define PUF_IDXBLK_L_DP_IDX6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX6_SHIFT)) & PUF_IDXBLK_L_DP_IDX6_MASK) + #define PUF_IDXBLK_L_DP_IDX7_MASK (0xC000U) #define PUF_IDXBLK_L_DP_IDX7_SHIFT (14U) +/*! IDX7 - Use to block PUF index 7 + */ #define PUF_IDXBLK_L_DP_IDX7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_L_DP_IDX7_SHIFT)) & PUF_IDXBLK_L_DP_IDX7_MASK) /*! @} */ /*! @name SHIFT_STATUS - */ /*! @{ */ + #define PUF_SHIFT_STATUS_KEY0_MASK (0xFU) #define PUF_SHIFT_STATUS_KEY0_SHIFT (0U) +/*! KEY0 - Index counter from key 0 shift register + */ #define PUF_SHIFT_STATUS_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY0_SHIFT)) & PUF_SHIFT_STATUS_KEY0_MASK) + #define PUF_SHIFT_STATUS_KEY1_MASK (0xF0U) #define PUF_SHIFT_STATUS_KEY1_SHIFT (4U) +/*! KEY1 - Index counter from key 1 shift register + */ #define PUF_SHIFT_STATUS_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY1_SHIFT)) & PUF_SHIFT_STATUS_KEY1_MASK) + #define PUF_SHIFT_STATUS_KEY2_MASK (0xF00U) #define PUF_SHIFT_STATUS_KEY2_SHIFT (8U) +/*! KEY2 - Index counter from key 2 shift register + */ #define PUF_SHIFT_STATUS_KEY2(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY2_SHIFT)) & PUF_SHIFT_STATUS_KEY2_MASK) + #define PUF_SHIFT_STATUS_KEY3_MASK (0xF000U) #define PUF_SHIFT_STATUS_KEY3_SHIFT (12U) +/*! KEY3 - Index counter from key 3 shift register + */ #define PUF_SHIFT_STATUS_KEY3(x) (((uint32_t)(((uint32_t)(x)) << PUF_SHIFT_STATUS_KEY3_SHIFT)) & PUF_SHIFT_STATUS_KEY3_MASK) /*! @} */ @@ -14194,7 +17208,7 @@ typedef struct { /* PUF - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral PUF base address */ #define PUF_BASE (0x5003B000u) /** Peripheral PUF base address */ @@ -14241,15 +17255,12 @@ typedef struct { /** RNG - Register Layout Typedef */ typedef struct { __I uint32_t RANDOM_NUMBER; /**< This register contains a random 32 bit number which is computed on demand, at each time it is read, offset: 0x0 */ - __I uint32_t ENCRYPTED_NUMBER; /**< This register contains a random 32 bit number which is pre-computed, offset: 0x4 */ + uint8_t RESERVED_0[4]; __I uint32_t COUNTER_VAL; /**< , offset: 0x8 */ __IO uint32_t COUNTER_CFG; /**< , offset: 0xC */ __IO uint32_t ONLINE_TEST_CFG; /**< , offset: 0x10 */ __I uint32_t ONLINE_TEST_VAL; /**< , offset: 0x14 */ - __IO uint32_t MISC_CFG; /**< , offset: 0x18 */ - uint8_t RESERVED_0[4056]; - __IO uint32_t POWERDOWN; /**< Powerdown mode (standard but certainly useless here), offset: 0xFF4 */ - uint8_t RESERVED_1[4]; + uint8_t RESERVED_1[4068]; __I uint32_t MODULEID; /**< IP identifier, offset: 0xFFC */ } RNG_Type; @@ -14264,106 +17275,119 @@ typedef struct { /*! @name RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read */ /*! @{ */ + #define RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK (0xFFFFFFFFU) #define RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT (0U) +/*! RANDOM_NUMBER - This register contains a random 32 bit number which is computed on demand, at each time it is read. + */ #define RNG_RANDOM_NUMBER_RANDOM_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_RANDOM_NUMBER_RANDOM_NUMBER_SHIFT)) & RNG_RANDOM_NUMBER_RANDOM_NUMBER_MASK) /*! @} */ -/*! @name ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed */ -/*! @{ */ -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK (0xFFFFFFFFU) -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT (0U) -#define RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_SHIFT)) & RNG_ENCRYPTED_NUMBER_ENCRYPTED_NUMBER_MASK) -/*! @} */ - /*! @name COUNTER_VAL - */ /*! @{ */ + #define RNG_COUNTER_VAL_CLK_RATIO_MASK (0xFFU) #define RNG_COUNTER_VAL_CLK_RATIO_SHIFT (0U) +/*! CLK_RATIO - Gives the ratio between the internal clocks frequencies and the register clock + * frequency for evaluation and certification purposes. + */ #define RNG_COUNTER_VAL_CLK_RATIO(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_CLK_RATIO_SHIFT)) & RNG_COUNTER_VAL_CLK_RATIO_MASK) + #define RNG_COUNTER_VAL_REFRESH_CNT_MASK (0x1F00U) #define RNG_COUNTER_VAL_REFRESH_CNT_SHIFT (8U) +/*! REFRESH_CNT - Incremented (till max possible value) each time COUNTER was updated since last reading to any *_NUMBER. + */ #define RNG_COUNTER_VAL_REFRESH_CNT(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_VAL_REFRESH_CNT_SHIFT)) & RNG_COUNTER_VAL_REFRESH_CNT_MASK) /*! @} */ /*! @name COUNTER_CFG - */ /*! @{ */ + #define RNG_COUNTER_CFG_MODE_MASK (0x3U) #define RNG_COUNTER_CFG_MODE_SHIFT (0U) +/*! MODE - 00: disabled 01: update once. + */ #define RNG_COUNTER_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_MODE_SHIFT)) & RNG_COUNTER_CFG_MODE_MASK) + #define RNG_COUNTER_CFG_CLOCK_SEL_MASK (0x1CU) #define RNG_COUNTER_CFG_CLOCK_SEL_SHIFT (2U) +/*! CLOCK_SEL - Selects the internal clock on which to compute statistics. + */ #define RNG_COUNTER_CFG_CLOCK_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_CLOCK_SEL_SHIFT)) & RNG_COUNTER_CFG_CLOCK_SEL_MASK) + #define RNG_COUNTER_CFG_SHIFT4X_MASK (0xE0U) #define RNG_COUNTER_CFG_SHIFT4X_SHIFT (5U) +/*! SHIFT4X - To be used to add precision to clock_ratio and determine 'entropy refill'. + */ #define RNG_COUNTER_CFG_SHIFT4X(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_SHIFT4X_SHIFT)) & RNG_COUNTER_CFG_SHIFT4X_MASK) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK (0x100U) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT (8U) -#define RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_SHIFT)) & RNG_COUNTER_CFG_DIS_ENH_ENTR_REFILL_MASK) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK (0x200U) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT (9U) -#define RNG_COUNTER_CFG_FORCE_ENTR_SPREADING(x) (((uint32_t)(((uint32_t)(x)) << RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_SHIFT)) & RNG_COUNTER_CFG_FORCE_ENTR_SPREADING_MASK) /*! @} */ /*! @name ONLINE_TEST_CFG - */ /*! @{ */ + #define RNG_ONLINE_TEST_CFG_ACTIVATE_MASK (0x1U) #define RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT (0U) +/*! ACTIVATE - 0: disabled 1: activated Update rythm for VAL depends on COUNTER_CFG if data_sel is set to COUNTER. + */ #define RNG_ONLINE_TEST_CFG_ACTIVATE(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_ACTIVATE_SHIFT)) & RNG_ONLINE_TEST_CFG_ACTIVATE_MASK) + #define RNG_ONLINE_TEST_CFG_DATA_SEL_MASK (0x6U) #define RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT (1U) +/*! DATA_SEL - Selects source on which to apply online test: 00: LSB of COUNTER: raw data from one + * or all sources of entropy 01: MSB of COUNTER: raw data from one or all sources of entropy 10: + * RANDOM_NUMBER 11: ENCRYPTED_NUMBER 'activate' should be set to 'disabled' before changing this + * field. + */ #define RNG_ONLINE_TEST_CFG_DATA_SEL(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_CFG_DATA_SEL_SHIFT)) & RNG_ONLINE_TEST_CFG_DATA_SEL_MASK) /*! @} */ /*! @name ONLINE_TEST_VAL - */ /*! @{ */ + #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK (0xFU) #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT (0U) +/*! LIVE_CHI_SQUARED - This value is updated as described in field 'activate'. + */ #define RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_LIVE_CHI_SQUARED_MASK) + #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK (0xF0U) #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT (4U) +/*! MIN_CHI_SQUARED - This field is reset when 'activate'==0. + */ #define RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) + #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK (0xF00U) #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT (8U) +/*! MAX_CHI_SQUARED - This field is reset when 'activate'==0. + */ #define RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED(x) (((uint32_t)(((uint32_t)(x)) << RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT)) & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) /*! @} */ -/*! @name MISC_CFG - */ -/*! @{ */ -#define RNG_MISC_CFG_AES_RESEED_MASK (0x1U) -#define RNG_MISC_CFG_AES_RESEED_SHIFT (0U) -#define RNG_MISC_CFG_AES_RESEED(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_RESEED_SHIFT)) & RNG_MISC_CFG_AES_RESEED_MASK) -#define RNG_MISC_CFG_AES_DT_CFG_MASK (0x2U) -#define RNG_MISC_CFG_AES_DT_CFG_SHIFT (1U) -#define RNG_MISC_CFG_AES_DT_CFG(x) (((uint32_t)(((uint32_t)(x)) << RNG_MISC_CFG_AES_DT_CFG_SHIFT)) & RNG_MISC_CFG_AES_DT_CFG_MASK) -/*! @} */ - -/*! @name POWERDOWN - Powerdown mode (standard but certainly useless here) */ -/*! @{ */ -#define RNG_POWERDOWN_SOFT_RESET_MASK (0x1U) -#define RNG_POWERDOWN_SOFT_RESET_SHIFT (0U) -#define RNG_POWERDOWN_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_SOFT_RESET_MASK) -#define RNG_POWERDOWN_FORCE_SOFT_RESET_MASK (0x2U) -#define RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT (1U) -#define RNG_POWERDOWN_FORCE_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_FORCE_SOFT_RESET_SHIFT)) & RNG_POWERDOWN_FORCE_SOFT_RESET_MASK) -#define RNG_POWERDOWN_POWERDOWN_MASK (0x80000000U) -#define RNG_POWERDOWN_POWERDOWN_SHIFT (31U) -#define RNG_POWERDOWN_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << RNG_POWERDOWN_POWERDOWN_SHIFT)) & RNG_POWERDOWN_POWERDOWN_MASK) -/*! @} */ - /*! @name MODULEID - IP identifier */ /*! @{ */ + #define RNG_MODULEID_APERTURE_MASK (0xFFU) #define RNG_MODULEID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture i. + */ #define RNG_MODULEID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_APERTURE_SHIFT)) & RNG_MODULEID_APERTURE_MASK) + #define RNG_MODULEID_MIN_REV_MASK (0xF00U) #define RNG_MODULEID_MIN_REV_SHIFT (8U) +/*! MIN_REV - Minor revision i. + */ #define RNG_MODULEID_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MIN_REV_SHIFT)) & RNG_MODULEID_MIN_REV_MASK) + #define RNG_MODULEID_MAJ_REV_MASK (0xF000U) #define RNG_MODULEID_MAJ_REV_SHIFT (12U) +/*! MAJ_REV - Major revision i. + */ #define RNG_MODULEID_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_MAJ_REV_SHIFT)) & RNG_MODULEID_MAJ_REV_MASK) + #define RNG_MODULEID_ID_MASK (0xFFFF0000U) #define RNG_MODULEID_ID_SHIFT (16U) +/*! ID - Identifier. + */ #define RNG_MODULEID_ID(x) (((uint32_t)(((uint32_t)(x)) << RNG_MODULEID_ID_SHIFT)) & RNG_MODULEID_ID_MASK) /*! @} */ @@ -14374,7 +17398,7 @@ typedef struct { /* RNG - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral RNG base address */ #define RNG_BASE (0x5003A000u) /** Peripheral RNG base address */ @@ -14422,7 +17446,7 @@ typedef struct { __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */ __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */ __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */ - __I uint32_t SUBSEC; /**< RTC Sub-second Counter register, offset: 0x10 */ + __I uint32_t SUBSEC; /**< Sub-second counter register, offset: 0x10 */ uint8_t RESERVED_0[44]; __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */ } RTC_Type; @@ -14438,6 +17462,7 @@ typedef struct { /*! @name CTRL - RTC control register */ /*! @{ */ + #define RTC_CTRL_SWRESET_MASK (0x1U) #define RTC_CTRL_SWRESET_SHIFT (0U) /*! SWRESET - Software reset control @@ -14448,6 +17473,7 @@ typedef struct { * the same time that the reset bit is being cleared. */ #define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK) + #define RTC_CTRL_ALARM1HZ_MASK (0x4U) #define RTC_CTRL_ALARM1HZ_SHIFT (2U) /*! ALARM1HZ - RTC 1 Hz timer alarm flag status. @@ -14456,6 +17482,7 @@ typedef struct { * request RTC_ALARM which can also wake up the part from any low power mode. Writing a 1 clears this bit. */ #define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK) + #define RTC_CTRL_WAKE1KHZ_MASK (0x8U) #define RTC_CTRL_WAKE1KHZ_SHIFT (3U) /*! WAKE1KHZ - RTC 1 kHz timer wake-up flag status. @@ -14464,6 +17491,7 @@ typedef struct { * interrupt request RTC-WAKE which can also wake up the part from any low power mode. Writing a 1 clears this bit. */ #define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK) + #define RTC_CTRL_ALARMDPD_EN_MASK (0x10U) #define RTC_CTRL_ALARMDPD_EN_SHIFT (4U) /*! ALARMDPD_EN - RTC 1 Hz timer alarm enable for Deep power-down. @@ -14471,6 +17499,7 @@ typedef struct { * 0b1..Enable. A match on the 1 Hz RTC timer bring the part out of Deep power-down mode. */ #define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK) + #define RTC_CTRL_WAKEDPD_EN_MASK (0x20U) #define RTC_CTRL_WAKEDPD_EN_SHIFT (5U) /*! WAKEDPD_EN - RTC 1 kHz timer wake-up enable for Deep power-down. @@ -14478,6 +17507,7 @@ typedef struct { * 0b1..Enable. A match on the 1 kHz RTC timer bring the part out of Deep power-down mode. */ #define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK) + #define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U) #define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U) /*! RTC1KHZ_EN - RTC 1 kHz clock enable. This bit can be set to 0 to conserve power if the 1 kHz @@ -14486,6 +17516,7 @@ typedef struct { * 0b1..Enable. The 1 kHz RTC timer is enabled. */ #define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK) + #define RTC_CTRL_RTC_EN_MASK (0x80U) #define RTC_CTRL_RTC_EN_SHIFT (7U) /*! RTC_EN - RTC enable. @@ -14496,6 +17527,7 @@ typedef struct { * high-resolution, 1 kHz clock, set bit 6 in this register. */ #define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK) + #define RTC_CTRL_RTC_OSC_PD_MASK (0x100U) #define RTC_CTRL_RTC_OSC_PD_SHIFT (8U) /*! RTC_OSC_PD - RTC oscillator power-down control. @@ -14503,6 +17535,7 @@ typedef struct { * 0b1..RTC oscillator is powered-down. */ #define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK) + #define RTC_CTRL_RTC_OSC_BYPASS_MASK (0x200U) #define RTC_CTRL_RTC_OSC_BYPASS_SHIFT (9U) /*! RTC_OSC_BYPASS - RTC oscillator bypass control. @@ -14510,6 +17543,7 @@ typedef struct { * 0b1..The RTC Oscillator is in bypass mode. In this mode a clock can be directly input into the RTC_XTALIN pin. */ #define RTC_CTRL_RTC_OSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_BYPASS_SHIFT)) & RTC_CTRL_RTC_OSC_BYPASS_MASK) + #define RTC_CTRL_RTC_SUBSEC_ENA_MASK (0x400U) #define RTC_CTRL_RTC_SUBSEC_ENA_SHIFT (10U) /*! RTC_SUBSEC_ENA - RTC Sub-second counter control. @@ -14526,36 +17560,63 @@ typedef struct { /*! @name MATCH - RTC match register */ /*! @{ */ + #define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU) #define RTC_MATCH_MATVAL_SHIFT (0U) +/*! MATVAL - Contains the match value against which the 1 Hz RTC timer will be compared to set the + * alarm flag RTC_ALARM and generate an alarm interrupt/wake-up if enabled. + */ #define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK) /*! @} */ /*! @name COUNT - RTC counter register */ /*! @{ */ + #define RTC_COUNT_VAL_MASK (0xFFFFFFFFU) #define RTC_COUNT_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the main, 1 Hz RTC timer. A write loads a new initial + * value into the timer. The RTC counter will count up continuously at a 1 Hz rate once the RTC + * Software Reset is removed (by clearing bit 0 of the CTRL register). Only write to this + * register when the RTC_EN bit in the RTC CTRL Register is 0. The counter increments one second after + * the RTC_EN bit is set. + */ #define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK) /*! @} */ /*! @name WAKE - High-resolution/wake-up timer control register */ /*! @{ */ + #define RTC_WAKE_VAL_MASK (0xFFFFU) #define RTC_WAKE_VAL_SHIFT (0U) +/*! VAL - A read reflects the current value of the high-resolution/wake-up timer. A write pre-loads + * a start count value into the wake-up timer and initializes a count-down sequence. Do not write + * to this register while counting is in progress. + */ #define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK) /*! @} */ -/*! @name SUBSEC - RTC Sub-second Counter register */ +/*! @name SUBSEC - Sub-second counter register */ /*! @{ */ + #define RTC_SUBSEC_SUBSEC_MASK (0x7FFFU) #define RTC_SUBSEC_SUBSEC_SHIFT (0U) +/*! SUBSEC - A read reflects the current value of the 32KHz sub-second counter. This counter is + * cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz + * rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This + * counter must be re-enabled after exiting deep power-down mode or after the main RTC module is + * disabled and re-enabled. On modules not equipped with a sub-second counter, this register + * will read-back as all zeroes. + */ #define RTC_SUBSEC_SUBSEC(x) (((uint32_t)(((uint32_t)(x)) << RTC_SUBSEC_SUBSEC_SHIFT)) & RTC_SUBSEC_SUBSEC_MASK) /*! @} */ /*! @name GPREG - General Purpose register */ /*! @{ */ + #define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU) #define RTC_GPREG_GPDATA_SHIFT (0U) +/*! GPDATA - Data retained during Deep power-down mode or loss of main power as long as VBAT is supplied. + */ #define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK) /*! @} */ @@ -14569,7 +17630,7 @@ typedef struct { /* RTC - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral RTC base address */ #define RTC_BASE (0x5002C000u) /** Peripheral RTC base address */ @@ -14616,40 +17677,112 @@ typedef struct { /** SCT - Register Layout Typedef */ typedef struct { __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */ - __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ - __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ - __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ - __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ - __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + union { /* offset: 0x4 */ + struct { /* offset: 0x4 */ + __IO uint16_t CTRLL; /**< SCT_CTRLL register, offset: 0x4 */ + __IO uint16_t CTRLH; /**< SCT_CTRLH register, offset: 0x6 */ + } CTRL_ACCESS16BIT; + __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */ + }; + union { /* offset: 0x8 */ + struct { /* offset: 0x8 */ + __IO uint16_t LIMITL; /**< SCT_LIMITL register, offset: 0x8 */ + __IO uint16_t LIMITH; /**< SCT_LIMITH register, offset: 0xA */ + } LIMIT_ACCESS16BIT; + __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */ + }; + union { /* offset: 0xC */ + struct { /* offset: 0xC */ + __IO uint16_t HALTL; /**< SCT_HALTL register, offset: 0xC */ + __IO uint16_t HALTH; /**< SCT_HALTH register, offset: 0xE */ + } HALT_ACCESS16BIT; + __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */ + }; + union { /* offset: 0x10 */ + struct { /* offset: 0x10 */ + __IO uint16_t STOPL; /**< SCT_STOPL register, offset: 0x10 */ + __IO uint16_t STOPH; /**< SCT_STOPH register, offset: 0x12 */ + } STOP_ACCESS16BIT; + __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */ + }; + union { /* offset: 0x14 */ + struct { /* offset: 0x14 */ + __IO uint16_t STARTL; /**< SCT_STARTL register, offset: 0x14 */ + __IO uint16_t STARTH; /**< SCT_STARTH register, offset: 0x16 */ + } START_ACCESS16BIT; + __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */ + }; uint8_t RESERVED_0[40]; - __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ - __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + union { /* offset: 0x40 */ + struct { /* offset: 0x40 */ + __IO uint16_t COUNTL; /**< SCT_COUNTL register, offset: 0x40 */ + __IO uint16_t COUNTH; /**< SCT_COUNTH register, offset: 0x42 */ + } COUNT_ACCESS16BIT; + __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */ + }; + union { /* offset: 0x44 */ + struct { /* offset: 0x44 */ + __IO uint16_t STATEL; /**< SCT_STATEL register, offset: 0x44 */ + __IO uint16_t STATEH; /**< SCT_STATEH register, offset: 0x46 */ + } STATE_ACCESS16BIT; + __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */ + }; __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */ - __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + union { /* offset: 0x4C */ + struct { /* offset: 0x4C */ + __IO uint16_t REGMODEL; /**< SCT_REGMODEL register, offset: 0x4C */ + __IO uint16_t REGMODEH; /**< SCT_REGMODEH register, offset: 0x4E */ + } REGMODE_ACCESS16BIT; + __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */ + }; __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */ __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */ __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */ - __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */ - __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */ + __IO uint32_t DMAREQ0; /**< SCT DMA request 0 register, offset: 0x5C */ + __IO uint32_t DMAREQ1; /**< SCT DMA request 1 register, offset: 0x60 */ uint8_t RESERVED_1[140]; __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */ __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */ __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */ __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */ union { /* offset: 0x100 */ - __IO uint32_t SCTCAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ - __IO uint32_t SCTMATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPL; /**< SCT_CAPL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t CAPH; /**< SCT_CAPH register, array offset: 0x102, array step: 0x4 */ + } CAP_ACCESS16BIT[16]; + __IO uint32_t CAP[16]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */ + }; + union { /* offset: 0x100, array step: 0x4 */ + struct { /* offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHL; /**< SCT_MATCHL register, array offset: 0x100, array step: 0x4 */ + __IO uint16_t MATCHH; /**< SCT_MATCHH register, array offset: 0x102, array step: 0x4 */ + } MATCH_ACCESS16BIT[16]; + __IO uint32_t MATCH[16]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */ + }; }; uint8_t RESERVED_2[192]; union { /* offset: 0x200 */ - __IO uint32_t SCTCAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ - __IO uint32_t SCTMATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLL; /**< SCT_CAPCTRLL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t CAPCTRLH; /**< SCT_CAPCTRLH register, array offset: 0x202, array step: 0x4 */ + } CAPCTRL_ACCESS16BIT[16]; + __IO uint32_t CAPCTRL[16]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */ + }; + union { /* offset: 0x200, array step: 0x4 */ + struct { /* offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELL; /**< SCT_MATCHRELL register, array offset: 0x200, array step: 0x4 */ + __IO uint16_t MATCHRELH; /**< SCT_MATCHRELH register, array offset: 0x202, array step: 0x4 */ + } MATCHREL_ACCESS16BIT[16]; + __IO uint32_t MATCHREL[16]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */ + }; }; uint8_t RESERVED_3[192]; struct { /* offset: 0x300, array step: 0x8 */ __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */ __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */ - } EVENT[16]; + } EV[16]; uint8_t RESERVED_4[384]; struct { /* offset: 0x500, array step: 0x8 */ __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */ @@ -14668,6 +17801,7 @@ typedef struct { /*! @name CONFIG - SCT configuration register */ /*! @{ */ + #define SCT_CONFIG_UNIFY_MASK (0x1U) #define SCT_CONFIG_UNIFY_SHIFT (0U) /*! UNIFY - SCT operation @@ -14675,6 +17809,7 @@ typedef struct { * 0b1..The SCT operates as a unified 32-bit counter. */ #define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK) + #define SCT_CONFIG_CLKMODE_MASK (0x6U) #define SCT_CONFIG_CLKMODE_SHIFT (1U) /*! CLKMODE - SCT clock mode @@ -14692,6 +17827,7 @@ typedef struct { * the system clock. */ #define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK) + #define SCT_CONFIG_CKSEL_MASK (0x78U) #define SCT_CONFIG_CKSEL_SHIFT (3U) /*! CKSEL - SCT clock select. The specific functionality of the designated input/edge is dependent @@ -14704,39 +17840,207 @@ typedef struct { * 0b0101..Falling edges on input 2. * 0b0110..Rising edges on input 3. * 0b0111..Falling edges on input 3. + * 0b1000..Rising edges on input 4. + * 0b1001..Falling edges on input 4. + * 0b1010..Rising edges on input 5. + * 0b1011..Falling edges on input 5. + * 0b1100..Rising edges on input 6. + * 0b1101..Falling edges on input 6. + * 0b1110..Rising edges on input 7. + * 0b1111..Falling edges on input 7. */ #define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK) -#define SCT_CONFIG_NORELAOD_L_MASK (0x80U) -#define SCT_CONFIG_NORELAOD_L_SHIFT (7U) -#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK) + +#define SCT_CONFIG_NORELOAD_L_MASK (0x80U) +#define SCT_CONFIG_NORELOAD_L_SHIFT (7U) +/*! NORELOAD_L - A 1 in this bit prevents the lower match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any + * time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ +#define SCT_CONFIG_NORELOAD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_L_SHIFT)) & SCT_CONFIG_NORELOAD_L_MASK) + #define SCT_CONFIG_NORELOAD_H_MASK (0x100U) #define SCT_CONFIG_NORELOAD_H_SHIFT (8U) +/*! NORELOAD_H - A 1 in this bit prevents the higher match registers from being reloaded from their + * respective reload registers. Setting this bit eliminates the need to write to the reload + * registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at + * any time. This bit is not used when the UNIFY bit is set. + */ #define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK) + #define SCT_CONFIG_INSYNC_MASK (0x1E00U) #define SCT_CONFIG_INSYNC_SHIFT (9U) +/*! INSYNC - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,, bit 12 = input 3); all + * other bits are reserved. A 1 in one of these bits subjects the corresponding input to + * synchronization to the SCT clock, before it is used to create an event. If an input is known to + * already be synchronous to the SCT clock, this bit may be set to 0 for faster input response. (Note: + * The SCT clock is the system clock for CKMODEs 0-2. It is the selected, asynchronous SCT input + * clock for CKMODE3). Note that the INSYNC field only affects inputs used for event generation. + * It does not apply to the clock input specified in the CKSEL field. + */ #define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK) + #define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U) #define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U) +/*! AUTOLIMIT_L - A one in this bit causes a match on match register 0 to be treated as a de-facto + * LIMIT condition without the need to define an associated event. As with any LIMIT event, this + * automatic limit causes the counter to be cleared to zero in unidirectional mode or to change + * the direction of count in bi-directional mode. Software can write to set or clear this bit at + * any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. + */ #define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK) + #define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U) #define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U) +/*! AUTOLIMIT_H - A one in this bit will cause a match on match register 0 to be treated as a + * de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, + * this automatic limit causes the counter to be cleared to zero in unidirectional mode or to + * change the direction of count in bi-directional mode. Software can write to set or clear this bit + * at any time. This bit is not used when the UNIFY bit is set. + */ #define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK) /*! @} */ +/*! @name CTRLL - SCT_CTRLL register */ +/*! @{ */ + +#define SCT_CTRLL_DOWN_L_MASK (0x1U) +#define SCT_CTRLL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLL_DOWN_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_DOWN_L_SHIFT)) & SCT_CTRLL_DOWN_L_MASK) + +#define SCT_CTRLL_STOP_L_MASK (0x2U) +#define SCT_CTRLL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ +#define SCT_CTRLL_STOP_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_STOP_L_SHIFT)) & SCT_CTRLL_STOP_L_MASK) + +#define SCT_CTRLL_HALT_L_MASK (0x4U) +#define SCT_CTRLL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLL_HALT_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_HALT_L_SHIFT)) & SCT_CTRLL_HALT_L_MASK) + +#define SCT_CTRLL_CLRCTR_L_MASK (0x8U) +#define SCT_CTRLL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + */ +#define SCT_CTRLL_CLRCTR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_CLRCTR_L_SHIFT)) & SCT_CTRLL_CLRCTR_L_MASK) + +#define SCT_CTRLL_BIDIR_L_MASK (0x10U) +#define SCT_CTRLL_BIDIR_L_SHIFT (4U) +/*! BIDIR_L - L or unified counter direction select + * 0b0..Up. The counter counts up to a limit condition, then is cleared to zero. + * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLL_BIDIR_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_BIDIR_L_SHIFT)) & SCT_CTRLL_BIDIR_L_MASK) + +#define SCT_CTRLL_PRE_L_MASK (0x1FE0U) +#define SCT_CTRLL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLL_PRE_L(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLL_PRE_L_SHIFT)) & SCT_CTRLL_PRE_L_MASK) +/*! @} */ + +/*! @name CTRLH - SCT_CTRLH register */ +/*! @{ */ + +#define SCT_CTRLH_DOWN_H_MASK (0x1U) +#define SCT_CTRLH_DOWN_H_SHIFT (0U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ +#define SCT_CTRLH_DOWN_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_DOWN_H_SHIFT)) & SCT_CTRLH_DOWN_H_MASK) + +#define SCT_CTRLH_STOP_H_MASK (0x2U) +#define SCT_CTRLH_STOP_H_SHIFT (1U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ +#define SCT_CTRLH_STOP_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_STOP_H_SHIFT)) & SCT_CTRLH_STOP_H_MASK) + +#define SCT_CTRLH_HALT_H_MASK (0x4U) +#define SCT_CTRLH_HALT_H_SHIFT (2U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ +#define SCT_CTRLH_HALT_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_HALT_H_SHIFT)) & SCT_CTRLH_HALT_H_MASK) + +#define SCT_CTRLH_CLRCTR_H_MASK (0x8U) +#define SCT_CTRLH_CLRCTR_H_SHIFT (3U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. + */ +#define SCT_CTRLH_CLRCTR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_CLRCTR_H_SHIFT)) & SCT_CTRLH_CLRCTR_H_MASK) + +#define SCT_CTRLH_BIDIR_H_MASK (0x10U) +#define SCT_CTRLH_BIDIR_H_SHIFT (4U) +/*! BIDIR_H - Direction select + * 0b0..The H counter counts up to its limit condition, then is cleared to zero. + * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. + */ +#define SCT_CTRLH_BIDIR_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_BIDIR_H_SHIFT)) & SCT_CTRLH_BIDIR_H_MASK) + +#define SCT_CTRLH_PRE_H_MASK (0x1FE0U) +#define SCT_CTRLH_PRE_H_SHIFT (5U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ +#define SCT_CTRLH_PRE_H(x) (((uint16_t)(((uint16_t)(x)) << SCT_CTRLH_PRE_H_SHIFT)) & SCT_CTRLH_PRE_H_MASK) +/*! @} */ + /*! @name CTRL - SCT control register */ /*! @{ */ + #define SCT_CTRL_DOWN_L_MASK (0x1U) #define SCT_CTRL_DOWN_L_SHIFT (0U) +/*! DOWN_L - This bit is 1 when the L or unified counter is counting down. Hardware sets this bit + * when the counter is counting up, counter limit occurs, and BIDIR = 1.Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ #define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK) + #define SCT_CTRL_STOP_L_MASK (0x2U) #define SCT_CTRL_STOP_L_SHIFT (1U) +/*! STOP_L - When this bit is 1 and HALT is 0, the L or unified counter does not run, but I/O events + * related to the counter can occur. If a designated start event occurs, this bit is cleared and + * counting resumes. + */ #define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK) + #define SCT_CTRL_HALT_L_MASK (0x4U) #define SCT_CTRL_HALT_L_SHIFT (2U) +/*! HALT_L - When this bit is 1, the L or unified counter does not run and no events can occur. A + * reset sets this bit. When the HALT_L bit is one, the STOP_L bit is cleared. It is possible to + * remove the halt condition while keeping the SCT in the stop condition (not running) with a + * single write to this register to simultaneously clear the HALT bit and set the STOP bit. Once set, + * only software can clear this bit to restore counter operation. This bit is set on reset. + */ #define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK) + #define SCT_CTRL_CLRCTR_L_MASK (0x8U) #define SCT_CTRL_CLRCTR_L_SHIFT (3U) +/*! CLRCTR_L - Writing a 1 to this bit clears the L or unified counter. This bit always reads as 0. + */ #define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK) + #define SCT_CTRL_BIDIR_L_MASK (0x10U) #define SCT_CTRL_BIDIR_L_SHIFT (4U) /*! BIDIR_L - L or unified counter direction select @@ -14744,21 +18048,47 @@ typedef struct { * 0b1..Up-down. The counter counts up to a limit, then counts down to a limit condition or to 0. */ #define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK) + #define SCT_CTRL_PRE_L_MASK (0x1FE0U) #define SCT_CTRL_PRE_L_SHIFT (5U) +/*! PRE_L - Specifies the factor by which the SCT clock is prescaled to produce the L or unified + * counter clock. The counter clock is clocked at the rate of the SCT clock divided by PRE_L+1. + * Clear the counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ #define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK) + #define SCT_CTRL_DOWN_H_MASK (0x10000U) #define SCT_CTRL_DOWN_H_SHIFT (16U) +/*! DOWN_H - This bit is 1 when the H counter is counting down. Hardware sets this bit when the + * counter is counting, a counter limit condition occurs, and BIDIR is 1. Hardware clears this bit + * when the counter is counting down and a limit condition occurs or when the counter reaches 0. + */ #define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK) + #define SCT_CTRL_STOP_H_MASK (0x20000U) #define SCT_CTRL_STOP_H_SHIFT (17U) +/*! STOP_H - When this bit is 1 and HALT is 0, the H counter does not, run but I/O events related to + * the counter can occur. If such an event matches the mask in the Start register, this bit is + * cleared and counting resumes. + */ #define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK) + #define SCT_CTRL_HALT_H_MASK (0x40000U) #define SCT_CTRL_HALT_H_SHIFT (18U) +/*! HALT_H - When this bit is 1, the H counter does not run and no events can occur. A reset sets + * this bit. When the HALT_H bit is one, the STOP_H bit is cleared. It is possible to remove the + * halt condition while keeping the SCT in the stop condition (not running) with a single write to + * this register to simultaneously clear the HALT bit and set the STOP bit. Once set, this bit + * can only be cleared by software to restore counter operation. This bit is set on reset. + */ #define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK) + #define SCT_CTRL_CLRCTR_H_MASK (0x80000U) #define SCT_CTRL_CLRCTR_H_SHIFT (19U) +/*! CLRCTR_H - Writing a 1 to this bit clears the H counter. This bit always reads as 0. + */ #define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK) + #define SCT_CTRL_BIDIR_H_MASK (0x100000U) #define SCT_CTRL_BIDIR_H_SHIFT (20U) /*! BIDIR_H - Direction select @@ -14766,190 +18096,465 @@ typedef struct { * 0b1..The H counter counts up to its limit, then counts down to a limit condition or to 0. */ #define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK) + #define SCT_CTRL_PRE_H_MASK (0x1FE00000U) #define SCT_CTRL_PRE_H_SHIFT (21U) +/*! PRE_H - Specifies the factor by which the SCT clock is prescaled to produce the H counter clock. + * The counter clock is clocked at the rate of the SCT clock divided by PRELH+1. Clear the + * counter (by writing a 1 to the CLRCTR bit) whenever changing the PRE value. + */ #define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK) /*! @} */ +/*! @name LIMITL - SCT_LIMITL register */ +/*! @{ */ + +#define SCT_LIMITL_LIMITL_MASK (0xFFFFU) +#define SCT_LIMITL_LIMITL_SHIFT (0U) +#define SCT_LIMITL_LIMITL(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITL_LIMITL_SHIFT)) & SCT_LIMITL_LIMITL_MASK) +/*! @} */ + +/*! @name LIMITH - SCT_LIMITH register */ +/*! @{ */ + +#define SCT_LIMITH_LIMITH_MASK (0xFFFFU) +#define SCT_LIMITH_LIMITH_SHIFT (0U) +#define SCT_LIMITH_LIMITH(x) (((uint16_t)(((uint16_t)(x)) << SCT_LIMITH_LIMITH_SHIFT)) & SCT_LIMITH_LIMITH_MASK) +/*! @} */ + /*! @name LIMIT - SCT limit event select register */ /*! @{ */ + #define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU) #define SCT_LIMIT_LIMMSK_L_SHIFT (0U) +/*! LIMMSK_L - If bit n is one, event n is used as a counter limit for the L or unified counter + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ #define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK) + #define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U) #define SCT_LIMIT_LIMMSK_H_SHIFT (16U) +/*! LIMMSK_H - If bit n is one, event n is used as a counter limit for the H counter (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ #define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK) /*! @} */ +/*! @name HALTL - SCT_HALTL register */ +/*! @{ */ + +#define SCT_HALTL_HALTL_MASK (0xFFFFU) +#define SCT_HALTL_HALTL_SHIFT (0U) +#define SCT_HALTL_HALTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTL_HALTL_SHIFT)) & SCT_HALTL_HALTL_MASK) +/*! @} */ + +/*! @name HALTH - SCT_HALTH register */ +/*! @{ */ + +#define SCT_HALTH_HALTH_MASK (0xFFFFU) +#define SCT_HALTH_HALTH_SHIFT (0U) +#define SCT_HALTH_HALTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_HALTH_HALTH_SHIFT)) & SCT_HALTH_HALTH_MASK) +/*! @} */ + /*! @name HALT - SCT halt event select register */ /*! @{ */ + #define SCT_HALT_HALTMSK_L_MASK (0xFFFFU) #define SCT_HALT_HALTMSK_L_SHIFT (0U) +/*! HALTMSK_L - If bit n is one, event n sets the HALT_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ #define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK) + #define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U) #define SCT_HALT_HALTMSK_H_SHIFT (16U) +/*! HALTMSK_H - If bit n is one, event n sets the HALT_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ #define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK) /*! @} */ +/*! @name STOPL - SCT_STOPL register */ +/*! @{ */ + +#define SCT_STOPL_STOPL_MASK (0xFFFFU) +#define SCT_STOPL_STOPL_SHIFT (0U) +#define SCT_STOPL_STOPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPL_STOPL_SHIFT)) & SCT_STOPL_STOPL_MASK) +/*! @} */ + +/*! @name STOPH - SCT_STOPH register */ +/*! @{ */ + +#define SCT_STOPH_STOPH_MASK (0xFFFFU) +#define SCT_STOPH_STOPH_SHIFT (0U) +#define SCT_STOPH_STOPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STOPH_STOPH_SHIFT)) & SCT_STOPH_STOPH_MASK) +/*! @} */ + /*! @name STOP - SCT stop event select register */ /*! @{ */ + #define SCT_STOP_STOPMSK_L_MASK (0xFFFFU) #define SCT_STOP_STOPMSK_L_SHIFT (0U) +/*! STOPMSK_L - If bit n is one, event n sets the STOP_L bit in the CTRL register (event 0 = bit 0, + * event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ #define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK) + #define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U) #define SCT_STOP_STOPMSK_H_SHIFT (16U) +/*! STOPMSK_H - If bit n is one, event n sets the STOP_H bit in the CTRL register (event 0 = bit 16, + * event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ #define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK) /*! @} */ +/*! @name STARTL - SCT_STARTL register */ +/*! @{ */ + +#define SCT_STARTL_STARTL_MASK (0xFFFFU) +#define SCT_STARTL_STARTL_SHIFT (0U) +#define SCT_STARTL_STARTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTL_STARTL_SHIFT)) & SCT_STARTL_STARTL_MASK) +/*! @} */ + +/*! @name STARTH - SCT_STARTH register */ +/*! @{ */ + +#define SCT_STARTH_STARTH_MASK (0xFFFFU) +#define SCT_STARTH_STARTH_SHIFT (0U) +#define SCT_STARTH_STARTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STARTH_STARTH_SHIFT)) & SCT_STARTH_STARTH_MASK) +/*! @} */ + /*! @name START - SCT start event select register */ /*! @{ */ + #define SCT_START_STARTMSK_L_MASK (0xFFFFU) #define SCT_START_STARTMSK_L_SHIFT (0U) +/*! STARTMSK_L - If bit n is one, event n clears the STOP_L bit in the CTRL register (event 0 = bit + * 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ #define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK) + #define SCT_START_STARTMSK_H_MASK (0xFFFF0000U) #define SCT_START_STARTMSK_H_SHIFT (16U) +/*! STARTMSK_H - If bit n is one, event n clears the STOP_H bit in the CTRL register (event 0 = bit + * 16, event 1 = bit 17, etc.). The number of bits = number of events in this SCT. + */ #define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK) /*! @} */ +/*! @name COUNTL - SCT_COUNTL register */ +/*! @{ */ + +#define SCT_COUNTL_COUNTL_MASK (0xFFFFU) +#define SCT_COUNTL_COUNTL_SHIFT (0U) +#define SCT_COUNTL_COUNTL(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTL_COUNTL_SHIFT)) & SCT_COUNTL_COUNTL_MASK) +/*! @} */ + +/*! @name COUNTH - SCT_COUNTH register */ +/*! @{ */ + +#define SCT_COUNTH_COUNTH_MASK (0xFFFFU) +#define SCT_COUNTH_COUNTH_SHIFT (0U) +#define SCT_COUNTH_COUNTH(x) (((uint16_t)(((uint16_t)(x)) << SCT_COUNTH_COUNTH_SHIFT)) & SCT_COUNTH_COUNTH_MASK) +/*! @} */ + /*! @name COUNT - SCT counter register */ /*! @{ */ + #define SCT_COUNT_CTR_L_MASK (0xFFFFU) #define SCT_COUNT_CTR_L_SHIFT (0U) +/*! CTR_L - When UNIFY = 0, read or write the 16-bit L counter value. When UNIFY = 1, read or write + * the lower 16 bits of the 32-bit unified counter. + */ #define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK) + #define SCT_COUNT_CTR_H_MASK (0xFFFF0000U) #define SCT_COUNT_CTR_H_SHIFT (16U) +/*! CTR_H - When UNIFY = 0, read or write the 16-bit H counter value. When UNIFY = 1, read or write + * the upper 16 bits of the 32-bit unified counter. + */ #define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK) /*! @} */ +/*! @name STATEL - SCT_STATEL register */ +/*! @{ */ + +#define SCT_STATEL_STATEL_MASK (0xFFFFU) +#define SCT_STATEL_STATEL_SHIFT (0U) +#define SCT_STATEL_STATEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEL_STATEL_SHIFT)) & SCT_STATEL_STATEL_MASK) +/*! @} */ + +/*! @name STATEH - SCT_STATEH register */ +/*! @{ */ + +#define SCT_STATEH_STATEH_MASK (0xFFFFU) +#define SCT_STATEH_STATEH_SHIFT (0U) +#define SCT_STATEH_STATEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_STATEH_STATEH_SHIFT)) & SCT_STATEH_STATEH_MASK) +/*! @} */ + /*! @name STATE - SCT state register */ /*! @{ */ + #define SCT_STATE_STATE_L_MASK (0x1FU) #define SCT_STATE_STATE_L_SHIFT (0U) +/*! STATE_L - State variable. + */ #define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK) + #define SCT_STATE_STATE_H_MASK (0x1F0000U) #define SCT_STATE_STATE_H_SHIFT (16U) +/*! STATE_H - State variable. + */ #define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK) /*! @} */ /*! @name INPUT - SCT input register */ /*! @{ */ + #define SCT_INPUT_AIN0_MASK (0x1U) #define SCT_INPUT_AIN0_SHIFT (0U) +/*! AIN0 - Input 0 state. Input 0 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK) + #define SCT_INPUT_AIN1_MASK (0x2U) #define SCT_INPUT_AIN1_SHIFT (1U) +/*! AIN1 - Input 1 state. Input 1 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK) + #define SCT_INPUT_AIN2_MASK (0x4U) #define SCT_INPUT_AIN2_SHIFT (2U) +/*! AIN2 - Input 2 state. Input 2 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK) + #define SCT_INPUT_AIN3_MASK (0x8U) #define SCT_INPUT_AIN3_SHIFT (3U) +/*! AIN3 - Input 3 state. Input 3 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK) + #define SCT_INPUT_AIN4_MASK (0x10U) #define SCT_INPUT_AIN4_SHIFT (4U) +/*! AIN4 - Input 4 state. Input 4 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK) + #define SCT_INPUT_AIN5_MASK (0x20U) #define SCT_INPUT_AIN5_SHIFT (5U) +/*! AIN5 - Input 5 state. Input 5 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK) + #define SCT_INPUT_AIN6_MASK (0x40U) #define SCT_INPUT_AIN6_SHIFT (6U) +/*! AIN6 - Input 6 state. Input 6 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK) + #define SCT_INPUT_AIN7_MASK (0x80U) #define SCT_INPUT_AIN7_SHIFT (7U) +/*! AIN7 - Input 7 state. Input 7 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK) + #define SCT_INPUT_AIN8_MASK (0x100U) #define SCT_INPUT_AIN8_SHIFT (8U) +/*! AIN8 - Input 8 state. Input 8 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK) + #define SCT_INPUT_AIN9_MASK (0x200U) #define SCT_INPUT_AIN9_SHIFT (9U) +/*! AIN9 - Input 9 state. Input 9 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK) + #define SCT_INPUT_AIN10_MASK (0x400U) #define SCT_INPUT_AIN10_SHIFT (10U) +/*! AIN10 - Input 10 state. Input 10 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK) + #define SCT_INPUT_AIN11_MASK (0x800U) #define SCT_INPUT_AIN11_SHIFT (11U) +/*! AIN11 - Input 11 state. Input 11 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK) + #define SCT_INPUT_AIN12_MASK (0x1000U) #define SCT_INPUT_AIN12_SHIFT (12U) +/*! AIN12 - Input 12 state. Input 12 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK) + #define SCT_INPUT_AIN13_MASK (0x2000U) #define SCT_INPUT_AIN13_SHIFT (13U) +/*! AIN13 - Input 13 state. Input 13 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK) + #define SCT_INPUT_AIN14_MASK (0x4000U) #define SCT_INPUT_AIN14_SHIFT (14U) +/*! AIN14 - Input 14 state. Input 14 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK) + #define SCT_INPUT_AIN15_MASK (0x8000U) #define SCT_INPUT_AIN15_SHIFT (15U) +/*! AIN15 - Input 15 state. Input 15 state on the last SCT clock edge. + */ #define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK) + #define SCT_INPUT_SIN0_MASK (0x10000U) #define SCT_INPUT_SIN0_SHIFT (16U) +/*! SIN0 - Input 0 state. Input 0 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK) + #define SCT_INPUT_SIN1_MASK (0x20000U) #define SCT_INPUT_SIN1_SHIFT (17U) +/*! SIN1 - Input 1 state. Input 1 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK) + #define SCT_INPUT_SIN2_MASK (0x40000U) #define SCT_INPUT_SIN2_SHIFT (18U) +/*! SIN2 - Input 2 state. Input 2 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK) + #define SCT_INPUT_SIN3_MASK (0x80000U) #define SCT_INPUT_SIN3_SHIFT (19U) +/*! SIN3 - Input 3 state. Input 3 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK) + #define SCT_INPUT_SIN4_MASK (0x100000U) #define SCT_INPUT_SIN4_SHIFT (20U) +/*! SIN4 - Input 4 state. Input 4 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK) + #define SCT_INPUT_SIN5_MASK (0x200000U) #define SCT_INPUT_SIN5_SHIFT (21U) +/*! SIN5 - Input 5 state. Input 5 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK) + #define SCT_INPUT_SIN6_MASK (0x400000U) #define SCT_INPUT_SIN6_SHIFT (22U) +/*! SIN6 - Input 6 state. Input 6 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK) + #define SCT_INPUT_SIN7_MASK (0x800000U) #define SCT_INPUT_SIN7_SHIFT (23U) +/*! SIN7 - Input 7 state. Input 7 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK) + #define SCT_INPUT_SIN8_MASK (0x1000000U) #define SCT_INPUT_SIN8_SHIFT (24U) +/*! SIN8 - Input 8 state. Input 8 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK) + #define SCT_INPUT_SIN9_MASK (0x2000000U) #define SCT_INPUT_SIN9_SHIFT (25U) +/*! SIN9 - Input 9 state. Input 9 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK) + #define SCT_INPUT_SIN10_MASK (0x4000000U) #define SCT_INPUT_SIN10_SHIFT (26U) +/*! SIN10 - Input 10 state. Input 10 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK) + #define SCT_INPUT_SIN11_MASK (0x8000000U) #define SCT_INPUT_SIN11_SHIFT (27U) +/*! SIN11 - Input 11 state. Input 11 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK) + #define SCT_INPUT_SIN12_MASK (0x10000000U) #define SCT_INPUT_SIN12_SHIFT (28U) +/*! SIN12 - Input 12 state. Input 12 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK) + #define SCT_INPUT_SIN13_MASK (0x20000000U) #define SCT_INPUT_SIN13_SHIFT (29U) +/*! SIN13 - Input 13 state. Input 13 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK) + #define SCT_INPUT_SIN14_MASK (0x40000000U) #define SCT_INPUT_SIN14_SHIFT (30U) +/*! SIN14 - Input 14 state. Input 14 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK) + #define SCT_INPUT_SIN15_MASK (0x80000000U) #define SCT_INPUT_SIN15_SHIFT (31U) +/*! SIN15 - Input 15 state. Input 15 state following the synchronization specified by INSYNC. + */ #define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK) /*! @} */ +/*! @name REGMODEL - SCT_REGMODEL register */ +/*! @{ */ + +#define SCT_REGMODEL_REGMODEL_MASK (0xFFFFU) +#define SCT_REGMODEL_REGMODEL_SHIFT (0U) +#define SCT_REGMODEL_REGMODEL(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEL_REGMODEL_SHIFT)) & SCT_REGMODEL_REGMODEL_MASK) +/*! @} */ + +/*! @name REGMODEH - SCT_REGMODEH register */ +/*! @{ */ + +#define SCT_REGMODEH_REGMODEH_MASK (0xFFFFU) +#define SCT_REGMODEH_REGMODEH_SHIFT (0U) +#define SCT_REGMODEH_REGMODEH(x) (((uint16_t)(((uint16_t)(x)) << SCT_REGMODEH_REGMODEH_SHIFT)) & SCT_REGMODEH_REGMODEH_MASK) +/*! @} */ + /*! @name REGMODE - SCT match/capture mode register */ /*! @{ */ + #define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU) #define SCT_REGMODE_REGMOD_L_SHIFT (0U) +/*! REGMOD_L - Each bit controls one match/capture register (register 0 = bit 0, register 1 = bit 1, + * etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match register. 1 = register operates as capture register. + */ #define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK) + #define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U) #define SCT_REGMODE_REGMOD_H_SHIFT (16U) +/*! REGMOD_H - Each bit controls one match/capture register (register 0 = bit 16, register 1 = bit + * 17, etc.). The number of bits = number of match/captures in this SCT. 0 = register operates as + * match registers. 1 = register operates as capture registers. + */ #define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK) /*! @} */ /*! @name OUTPUT - SCT output register */ /*! @{ */ + #define SCT_OUTPUT_OUT_MASK (0xFFFFU) #define SCT_OUTPUT_OUT_SHIFT (0U) +/*! OUT - Writing a 1 to bit n forces the corresponding output HIGH. Writing a 0 forces the + * corresponding output LOW (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ #define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK) /*! @} */ /*! @name OUTPUTDIRCTRL - SCT output counter direction control register */ /*! @{ */ + #define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U) #define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U) /*! SETCLR0 - Set/clear operation on output 0. Value 0x3 is reserved. Do not program this value. @@ -14958,6 +18563,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU) #define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U) /*! SETCLR1 - Set/clear operation on output 1. Value 0x3 is reserved. Do not program this value. @@ -14966,6 +18572,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U) #define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U) /*! SETCLR2 - Set/clear operation on output 2. Value 0x3 is reserved. Do not program this value. @@ -14974,6 +18581,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U) #define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U) /*! SETCLR3 - Set/clear operation on output 3. Value 0x3 is reserved. Do not program this value. @@ -14982,6 +18590,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U) #define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U) /*! SETCLR4 - Set/clear operation on output 4. Value 0x3 is reserved. Do not program this value. @@ -14990,6 +18599,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U) #define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U) /*! SETCLR5 - Set/clear operation on output 5. Value 0x3 is reserved. Do not program this value. @@ -14998,6 +18608,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U) #define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U) /*! SETCLR6 - Set/clear operation on output 6. Value 0x3 is reserved. Do not program this value. @@ -15006,6 +18617,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U) #define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U) /*! SETCLR7 - Set/clear operation on output 7. Value 0x3 is reserved. Do not program this value. @@ -15014,6 +18626,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U) #define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U) /*! SETCLR8 - Set/clear operation on output 8. Value 0x3 is reserved. Do not program this value. @@ -15022,6 +18635,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U) #define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U) /*! SETCLR9 - Set/clear operation on output 9. Value 0x3 is reserved. Do not program this value. @@ -15030,6 +18644,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U) #define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U) /*! SETCLR10 - Set/clear operation on output 10. Value 0x3 is reserved. Do not program this value. @@ -15038,6 +18653,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U) #define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U) /*! SETCLR11 - Set/clear operation on output 11. Value 0x3 is reserved. Do not program this value. @@ -15046,6 +18662,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U) #define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U) /*! SETCLR12 - Set/clear operation on output 12. Value 0x3 is reserved. Do not program this value. @@ -15054,6 +18671,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U) #define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U) /*! SETCLR13 - Set/clear operation on output 13. Value 0x3 is reserved. Do not program this value. @@ -15062,6 +18680,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U) #define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U) /*! SETCLR14 - Set/clear operation on output 14. Value 0x3 is reserved. Do not program this value. @@ -15070,6 +18689,7 @@ typedef struct { * 0b10..Set and clear are reversed when counter H is counting down. Do not use if UNIFY = 1. */ #define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK) + #define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U) #define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U) /*! SETCLR15 - Set/clear operation on output 15. Value 0x3 is reserved. Do not program this value. @@ -15082,6 +18702,7 @@ typedef struct { /*! @name RES - SCT conflict resolution register */ /*! @{ */ + #define SCT_RES_O0RES_MASK (0x3U) #define SCT_RES_O0RES_SHIFT (0U) /*! O0RES - Effect of simultaneous set and clear on output 0. @@ -15091,6 +18712,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK) + #define SCT_RES_O1RES_MASK (0xCU) #define SCT_RES_O1RES_SHIFT (2U) /*! O1RES - Effect of simultaneous set and clear on output 1. @@ -15100,6 +18722,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK) + #define SCT_RES_O2RES_MASK (0x30U) #define SCT_RES_O2RES_SHIFT (4U) /*! O2RES - Effect of simultaneous set and clear on output 2. @@ -15109,6 +18732,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK) + #define SCT_RES_O3RES_MASK (0xC0U) #define SCT_RES_O3RES_SHIFT (6U) /*! O3RES - Effect of simultaneous set and clear on output 3. @@ -15118,6 +18742,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK) + #define SCT_RES_O4RES_MASK (0x300U) #define SCT_RES_O4RES_SHIFT (8U) /*! O4RES - Effect of simultaneous set and clear on output 4. @@ -15127,6 +18752,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK) + #define SCT_RES_O5RES_MASK (0xC00U) #define SCT_RES_O5RES_SHIFT (10U) /*! O5RES - Effect of simultaneous set and clear on output 5. @@ -15136,6 +18762,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK) + #define SCT_RES_O6RES_MASK (0x3000U) #define SCT_RES_O6RES_SHIFT (12U) /*! O6RES - Effect of simultaneous set and clear on output 6. @@ -15145,6 +18772,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK) + #define SCT_RES_O7RES_MASK (0xC000U) #define SCT_RES_O7RES_SHIFT (14U) /*! O7RES - Effect of simultaneous set and clear on output 7. @@ -15154,6 +18782,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK) + #define SCT_RES_O8RES_MASK (0x30000U) #define SCT_RES_O8RES_SHIFT (16U) /*! O8RES - Effect of simultaneous set and clear on output 8. @@ -15163,6 +18792,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK) + #define SCT_RES_O9RES_MASK (0xC0000U) #define SCT_RES_O9RES_SHIFT (18U) /*! O9RES - Effect of simultaneous set and clear on output 9. @@ -15172,6 +18802,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK) + #define SCT_RES_O10RES_MASK (0x300000U) #define SCT_RES_O10RES_SHIFT (20U) /*! O10RES - Effect of simultaneous set and clear on output 10. @@ -15181,6 +18812,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK) + #define SCT_RES_O11RES_MASK (0xC00000U) #define SCT_RES_O11RES_SHIFT (22U) /*! O11RES - Effect of simultaneous set and clear on output 11. @@ -15190,6 +18822,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK) + #define SCT_RES_O12RES_MASK (0x3000000U) #define SCT_RES_O12RES_SHIFT (24U) /*! O12RES - Effect of simultaneous set and clear on output 12. @@ -15199,6 +18832,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK) + #define SCT_RES_O13RES_MASK (0xC000000U) #define SCT_RES_O13RES_SHIFT (26U) /*! O13RES - Effect of simultaneous set and clear on output 13. @@ -15208,6 +18842,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK) + #define SCT_RES_O14RES_MASK (0x30000000U) #define SCT_RES_O14RES_SHIFT (28U) /*! O14RES - Effect of simultaneous set and clear on output 14. @@ -15217,6 +18852,7 @@ typedef struct { * 0b11..Toggle output. */ #define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK) + #define SCT_RES_O15RES_MASK (0xC0000000U) #define SCT_RES_O15RES_SHIFT (30U) /*! O15RES - Effect of simultaneous set and clear on output 15. @@ -15228,152 +18864,350 @@ typedef struct { #define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK) /*! @} */ -/*! @name DMA0REQUEST - SCT DMA request 0 register */ +/*! @name DMAREQ0 - SCT DMA request 0 register */ /*! @{ */ -#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU) -#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U) -#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK) -#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U) -#define SCT_DMA0REQUEST_DRL0_SHIFT (30U) -#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK) -#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U) -#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U) -#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK) + +#define SCT_DMAREQ0_DEV_0_MASK (0xFFFFU) +#define SCT_DMAREQ0_DEV_0_SHIFT (0U) +/*! DEV_0 - If bit n is one, event n triggers DMA request 0 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ0_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DEV_0_SHIFT)) & SCT_DMAREQ0_DEV_0_MASK) + +#define SCT_DMAREQ0_DRL0_MASK (0x40000000U) +#define SCT_DMAREQ0_DRL0_SHIFT (30U) +/*! DRL0 - A 1 in this bit triggers DMA request 0 when it loads the MATCH_L/Unified registers from the RELOAD_L/Unified registers. + */ +#define SCT_DMAREQ0_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRL0_SHIFT)) & SCT_DMAREQ0_DRL0_MASK) + +#define SCT_DMAREQ0_DRQ0_MASK (0x80000000U) +#define SCT_DMAREQ0_DRQ0_SHIFT (31U) +/*! DRQ0 - This read-only bit indicates the state of DMA Request 0. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ0_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ0_DRQ0_SHIFT)) & SCT_DMAREQ0_DRQ0_MASK) /*! @} */ -/*! @name DMA1REQUEST - SCT DMA request 1 register */ +/*! @name DMAREQ1 - SCT DMA request 1 register */ /*! @{ */ -#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU) -#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U) -#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK) -#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U) -#define SCT_DMA1REQUEST_DRL1_SHIFT (30U) -#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK) -#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U) -#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U) -#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK) + +#define SCT_DMAREQ1_DEV_1_MASK (0xFFFFU) +#define SCT_DMAREQ1_DEV_1_SHIFT (0U) +/*! DEV_1 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, + * etc.). The number of bits = number of events in this SCT. + */ +#define SCT_DMAREQ1_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DEV_1_SHIFT)) & SCT_DMAREQ1_DEV_1_MASK) + +#define SCT_DMAREQ1_DRL1_MASK (0x40000000U) +#define SCT_DMAREQ1_DRL1_SHIFT (30U) +/*! DRL1 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers. + */ +#define SCT_DMAREQ1_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRL1_SHIFT)) & SCT_DMAREQ1_DRL1_MASK) + +#define SCT_DMAREQ1_DRQ1_MASK (0x80000000U) +#define SCT_DMAREQ1_DRQ1_SHIFT (31U) +/*! DRQ1 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA + * channel is enabled and properly set up, it is unlikely that software will see this flag, it will + * be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA + * setup. + */ +#define SCT_DMAREQ1_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMAREQ1_DRQ1_SHIFT)) & SCT_DMAREQ1_DRQ1_MASK) /*! @} */ /*! @name EVEN - SCT event interrupt enable register */ /*! @{ */ + #define SCT_EVEN_IEN_MASK (0xFFFFU) #define SCT_EVEN_IEN_SHIFT (0U) +/*! IEN - The SCT requests an interrupt when bit n of this register and the event flag register are + * both one (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in + * this SCT. + */ #define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK) /*! @} */ /*! @name EVFLAG - SCT event flag register */ /*! @{ */ + #define SCT_EVFLAG_FLAG_MASK (0xFFFFU) #define SCT_EVFLAG_FLAG_SHIFT (0U) +/*! FLAG - Bit n is one if event n has occurred since reset or a 1 was last written to this bit + * (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT. + */ #define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK) /*! @} */ /*! @name CONEN - SCT conflict interrupt enable register */ /*! @{ */ + #define SCT_CONEN_NCEN_MASK (0xFFFFU) #define SCT_CONEN_NCEN_SHIFT (0U) +/*! NCEN - The SCT requests an interrupt when bit n of this register and the SCT conflict flag + * register are both one (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = number of + * outputs in this SCT. + */ #define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK) /*! @} */ /*! @name CONFLAG - SCT conflict flag register */ /*! @{ */ + #define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU) #define SCT_CONFLAG_NCFLAG_SHIFT (0U) +/*! NCFLAG - Bit n is one if a no-change conflict event occurred on output n since reset or a 1 was + * last written to this bit (output 0 = bit 0, output 1 = bit 1, etc.). The number of bits = + * number of outputs in this SCT. + */ #define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK) + #define SCT_CONFLAG_BUSERRL_MASK (0x40000000U) #define SCT_CONFLAG_BUSERRL_SHIFT (30U) +/*! BUSERRL - The most recent bus error from this SCT involved writing CTR L/Unified, STATE + * L/Unified, MATCH L/Unified, or the Output register when the L/U counter was not halted. A word write + * to certain L and H registers can be half successful and half unsuccessful. + */ #define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK) + #define SCT_CONFLAG_BUSERRH_MASK (0x80000000U) #define SCT_CONFLAG_BUSERRH_SHIFT (31U) +/*! BUSERRH - The most recent bus error from this SCT involved writing CTR H, STATE H, MATCH H, or + * the Output register when the H counter was not halted. + */ #define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK) /*! @} */ -/*! @name SCTCAP - SCT capture register of capture channel */ +/*! @name CAPL - SCT_CAPL register */ /*! @{ */ -#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU) -#define SCT_SCTCAP_CAPn_L_SHIFT (0U) -#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK) -#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAP_CAPn_H_SHIFT (16U) -#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK) + +#define SCT_CAPL_CAPL_MASK (0xFFFFU) +#define SCT_CAPL_CAPL_SHIFT (0U) +#define SCT_CAPL_CAPL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPL_CAPL_SHIFT)) & SCT_CAPL_CAPL_MASK) /*! @} */ -/* The count of SCT_SCTCAP */ -#define SCT_SCTCAP_COUNT (16U) +/* The count of SCT_CAPL */ +#define SCT_CAPL_COUNT (16U) -/*! @name SCTMATCH - SCT match value register of match channels */ +/*! @name CAPH - SCT_CAPH register */ /*! @{ */ -#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU) -#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U) -#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK) -#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U) -#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK) + +#define SCT_CAPH_CAPH_MASK (0xFFFFU) +#define SCT_CAPH_CAPH_SHIFT (0U) +#define SCT_CAPH_CAPH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPH_CAPH_SHIFT)) & SCT_CAPH_CAPH_MASK) /*! @} */ -/* The count of SCT_SCTMATCH */ -#define SCT_SCTMATCH_COUNT (16U) +/* The count of SCT_CAPH */ +#define SCT_CAPH_COUNT (16U) -/*! @name SCTCAPCTRL - SCT capture control register */ +/*! @name CAP - SCT capture register of capture channel */ /*! @{ */ -#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU) -#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U) -#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK) -#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) -#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U) -#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK) + +#define SCT_CAP_CAPn_L_MASK (0xFFFFU) +#define SCT_CAP_CAPn_L_SHIFT (0U) +/*! CAPn_L - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the lower 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_L_SHIFT)) & SCT_CAP_CAPn_L_MASK) + +#define SCT_CAP_CAPn_H_MASK (0xFFFF0000U) +#define SCT_CAP_CAPn_H_SHIFT (16U) +/*! CAPn_H - When UNIFY = 0, read the 16-bit counter value at which this register was last captured. + * When UNIFY = 1, read the upper 16 bits of the 32-bit value at which this register was last + * captured. + */ +#define SCT_CAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAP_CAPn_H_SHIFT)) & SCT_CAP_CAPn_H_MASK) /*! @} */ -/* The count of SCT_SCTCAPCTRL */ -#define SCT_SCTCAPCTRL_COUNT (16U) +/* The count of SCT_CAP */ +#define SCT_CAP_COUNT (16U) -/*! @name SCTMATCHREL - SCT match reload value register */ +/*! @name MATCHL - SCT_MATCHL register */ /*! @{ */ -#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU) -#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U) -#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK) -#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U) -#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U) -#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK) + +#define SCT_MATCHL_MATCHL_MASK (0xFFFFU) +#define SCT_MATCHL_MATCHL_SHIFT (0U) +#define SCT_MATCHL_MATCHL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHL_MATCHL_SHIFT)) & SCT_MATCHL_MATCHL_MASK) /*! @} */ -/* The count of SCT_SCTMATCHREL */ -#define SCT_SCTMATCHREL_COUNT (16U) +/* The count of SCT_MATCHL */ +#define SCT_MATCHL_COUNT (16U) -/*! @name EVENT_STATE - SCT event state register 0 */ +/*! @name MATCHH - SCT_MATCHH register */ /*! @{ */ -#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU) -#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U) -#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK) + +#define SCT_MATCHH_MATCHH_MASK (0xFFFFU) +#define SCT_MATCHH_MATCHH_SHIFT (0U) +#define SCT_MATCHH_MATCHH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHH_MATCHH_SHIFT)) & SCT_MATCHH_MATCHH_MASK) /*! @} */ -/* The count of SCT_EVENT_STATE */ -#define SCT_EVENT_STATE_COUNT (16U) +/* The count of SCT_MATCHH */ +#define SCT_MATCHH_COUNT (16U) -/*! @name EVENT_CTRL - SCT event control register 0 */ +/*! @name MATCH - SCT match value register of match channels */ /*! @{ */ -#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU) -#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U) -#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK) -#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U) -#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U) + +#define SCT_MATCH_MATCHn_L_MASK (0xFFFFU) +#define SCT_MATCH_MATCHn_L_SHIFT (0U) +/*! MATCHn_L - When UNIFY = 0, read or write the 16-bit value to be compared to the L counter. When + * UNIFY = 1, read or write the lower 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_L_SHIFT)) & SCT_MATCH_MATCHn_L_MASK) + +#define SCT_MATCH_MATCHn_H_MASK (0xFFFF0000U) +#define SCT_MATCH_MATCHn_H_SHIFT (16U) +/*! MATCHn_H - When UNIFY = 0, read or write the 16-bit value to be compared to the H counter. When + * UNIFY = 1, read or write the upper 16 bits of the 32-bit value to be compared to the unified + * counter. + */ +#define SCT_MATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCH_MATCHn_H_SHIFT)) & SCT_MATCH_MATCHn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCH */ +#define SCT_MATCH_COUNT (16U) + +/*! @name CAPCTRLL - SCT_CAPCTRLL register */ +/*! @{ */ + +#define SCT_CAPCTRLL_CAPCTRLL_MASK (0xFFFFU) +#define SCT_CAPCTRLL_CAPCTRLL_SHIFT (0U) +#define SCT_CAPCTRLL_CAPCTRLL(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLL_CAPCTRLL_SHIFT)) & SCT_CAPCTRLL_CAPCTRLL_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLL */ +#define SCT_CAPCTRLL_COUNT (16U) + +/*! @name CAPCTRLH - SCT_CAPCTRLH register */ +/*! @{ */ + +#define SCT_CAPCTRLH_CAPCTRLH_MASK (0xFFFFU) +#define SCT_CAPCTRLH_CAPCTRLH_SHIFT (0U) +#define SCT_CAPCTRLH_CAPCTRLH(x) (((uint16_t)(((uint16_t)(x)) << SCT_CAPCTRLH_CAPCTRLH_SHIFT)) & SCT_CAPCTRLH_CAPCTRLH_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRLH */ +#define SCT_CAPCTRLH_COUNT (16U) + +/*! @name CAPCTRL - SCT capture control register */ +/*! @{ */ + +#define SCT_CAPCTRL_CAPCONn_L_MASK (0xFFFFU) +#define SCT_CAPCTRL_CAPCONn_L_SHIFT (0U) +/*! CAPCONn_L - If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the CAPn (UNIFY = 1) + * register to be loaded (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of + * match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_L_SHIFT)) & SCT_CAPCTRL_CAPCONn_L_MASK) + +#define SCT_CAPCTRL_CAPCONn_H_MASK (0xFFFF0000U) +#define SCT_CAPCTRL_CAPCONn_H_SHIFT (16U) +/*! CAPCONn_H - If bit m is one, event m causes the CAPn_H (UNIFY = 0) register to be loaded (event + * 0 = bit 16, event 1 = bit 17, etc.). The number of bits = number of match/captures in this SCT. + */ +#define SCT_CAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CAPCTRL_CAPCONn_H_SHIFT)) & SCT_CAPCTRL_CAPCONn_H_MASK) +/*! @} */ + +/* The count of SCT_CAPCTRL */ +#define SCT_CAPCTRL_COUNT (16U) + +/*! @name MATCHRELL - SCT_MATCHRELL register */ +/*! @{ */ + +#define SCT_MATCHRELL_MATCHRELL_MASK (0xFFFFU) +#define SCT_MATCHRELL_MATCHRELL_SHIFT (0U) +#define SCT_MATCHRELL_MATCHRELL(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELL_MATCHRELL_SHIFT)) & SCT_MATCHRELL_MATCHRELL_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELL */ +#define SCT_MATCHRELL_COUNT (16U) + +/*! @name MATCHRELH - SCT_MATCHRELH register */ +/*! @{ */ + +#define SCT_MATCHRELH_MATCHRELH_MASK (0xFFFFU) +#define SCT_MATCHRELH_MATCHRELH_SHIFT (0U) +#define SCT_MATCHRELH_MATCHRELH(x) (((uint16_t)(((uint16_t)(x)) << SCT_MATCHRELH_MATCHRELH_SHIFT)) & SCT_MATCHRELH_MATCHRELH_MASK) +/*! @} */ + +/* The count of SCT_MATCHRELH */ +#define SCT_MATCHRELH_COUNT (16U) + +/*! @name MATCHREL - SCT match reload value register */ +/*! @{ */ + +#define SCT_MATCHREL_RELOADn_L_MASK (0xFFFFU) +#define SCT_MATCHREL_RELOADn_L_SHIFT (0U) +/*! RELOADn_L - When UNIFY = 0, specifies the 16-bit value to be loaded into the MATCHn_L register. + * When UNIFY = 1, specifies the lower 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_L_SHIFT)) & SCT_MATCHREL_RELOADn_L_MASK) + +#define SCT_MATCHREL_RELOADn_H_MASK (0xFFFF0000U) +#define SCT_MATCHREL_RELOADn_H_SHIFT (16U) +/*! RELOADn_H - When UNIFY = 0, specifies the 16-bit to be loaded into the MATCHn_H register. When + * UNIFY = 1, specifies the upper 16 bits of the 32-bit value to be loaded into the MATCHn + * register. + */ +#define SCT_MATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_MATCHREL_RELOADn_H_SHIFT)) & SCT_MATCHREL_RELOADn_H_MASK) +/*! @} */ + +/* The count of SCT_MATCHREL */ +#define SCT_MATCHREL_COUNT (16U) + +/*! @name EV_STATE - SCT event state register 0 */ +/*! @{ */ + +#define SCT_EV_STATE_STATEMSKn_MASK (0xFFFFU) +#define SCT_EV_STATE_STATEMSKn_SHIFT (0U) +/*! STATEMSKn - If bit m is one, event n happens in state m of the counter selected by the HEVENT + * bit (n = event number, m = state number; state 0 = bit 0, state 1= bit 1, etc.). The number of + * bits = number of states in this SCT. + */ +#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_STATE_STATEMSKn_SHIFT)) & SCT_EV_STATE_STATEMSKn_MASK) +/*! @} */ + +/* The count of SCT_EV_STATE */ +#define SCT_EV_STATE_COUNT (16U) + +/*! @name EV_CTRL - SCT event control register 0 */ +/*! @{ */ + +#define SCT_EV_CTRL_MATCHSEL_MASK (0xFU) +#define SCT_EV_CTRL_MATCHSEL_SHIFT (0U) +/*! MATCHSEL - Selects the Match register associated with this event (if any). A match can occur + * only when the counter selected by the HEVENT bit is running. + */ +#define SCT_EV_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHSEL_SHIFT)) & SCT_EV_CTRL_MATCHSEL_MASK) + +#define SCT_EV_CTRL_HEVENT_MASK (0x10U) +#define SCT_EV_CTRL_HEVENT_SHIFT (4U) /*! HEVENT - Select L/H counter. Do not set this bit if UNIFY = 1. * 0b0..Selects the L state and the L match register selected by MATCHSEL. * 0b1..Selects the H state and the H match register selected by MATCHSEL. */ -#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK) -#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U) -#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U) +#define SCT_EV_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_HEVENT_SHIFT)) & SCT_EV_CTRL_HEVENT_MASK) + +#define SCT_EV_CTRL_OUTSEL_MASK (0x20U) +#define SCT_EV_CTRL_OUTSEL_SHIFT (5U) /*! OUTSEL - Input/output select * 0b0..Selects the inputs selected by IOSEL. * 0b1..Selects the outputs selected by IOSEL. */ -#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK) -#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U) -#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U) -#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK) -#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U) -#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U) +#define SCT_EV_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_OUTSEL_SHIFT)) & SCT_EV_CTRL_OUTSEL_MASK) + +#define SCT_EV_CTRL_IOSEL_MASK (0x3C0U) +#define SCT_EV_CTRL_IOSEL_SHIFT (6U) +/*! IOSEL - Selects the input or output signal number associated with this event (if any). Do not + * select an input in this register if CKMODE is 1x. In this case the clock input is an implicit + * ingredient of every event. + */ +#define SCT_EV_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOSEL_SHIFT)) & SCT_EV_CTRL_IOSEL_MASK) + +#define SCT_EV_CTRL_IOCOND_MASK (0xC00U) +#define SCT_EV_CTRL_IOCOND_SHIFT (10U) /*! IOCOND - Selects the I/O condition for event n. (The detection of edges on outputs lag the * conditions that switch the outputs by one SCT clock). In order to guarantee proper edge/state * detection, an input must have a minimum pulse width of at least one SCT clock period . @@ -15382,48 +19216,69 @@ typedef struct { * 0b10..Fall * 0b11..HIGH */ -#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK) -#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U) -#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U) +#define SCT_EV_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_IOCOND_SHIFT)) & SCT_EV_CTRL_IOCOND_MASK) + +#define SCT_EV_CTRL_COMBMODE_MASK (0x3000U) +#define SCT_EV_CTRL_COMBMODE_SHIFT (12U) /*! COMBMODE - Selects how the specified match and I/O condition are used and combined. * 0b00..OR. The event occurs when either the specified match or I/O condition occurs. * 0b01..MATCH. Uses the specified match only. * 0b10..IO. Uses the specified I/O condition only. * 0b11..AND. The event occurs when the specified match and I/O condition occur simultaneously. */ -#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK) -#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U) -#define SCT_EVENT_CTRL_STATELD_SHIFT (14U) +#define SCT_EV_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_COMBMODE_SHIFT)) & SCT_EV_CTRL_COMBMODE_MASK) + +#define SCT_EV_CTRL_STATELD_MASK (0x4000U) +#define SCT_EV_CTRL_STATELD_SHIFT (14U) /*! STATELD - This bit controls how the STATEV value modifies the state selected by HEVENT when this * event is the highest-numbered event occurring for that state. * 0b0..STATEV value is added into STATE (the carry-out is ignored). * 0b1..STATEV value is loaded into STATE. */ -#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK) -#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U) -#define SCT_EVENT_CTRL_STATEV_SHIFT (15U) -#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK) -#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U) -#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U) -#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK) -#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U) -#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U) +#define SCT_EV_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATELD_SHIFT)) & SCT_EV_CTRL_STATELD_MASK) + +#define SCT_EV_CTRL_STATEV_MASK (0xF8000U) +#define SCT_EV_CTRL_STATEV_SHIFT (15U) +/*! STATEV - This value is loaded into or added to the state selected by HEVENT, depending on + * STATELD, when this event is the highest-numbered event occurring for that state. If STATELD and + * STATEV are both zero, there is no change to the STATE value. + */ +#define SCT_EV_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_STATEV_SHIFT)) & SCT_EV_CTRL_STATEV_MASK) + +#define SCT_EV_CTRL_MATCHMEM_MASK (0x100000U) +#define SCT_EV_CTRL_MATCHMEM_SHIFT (20U) +/*! MATCHMEM - If this bit is one and the COMBMODE field specifies a match component to the + * triggering of this event, then a match is considered to be active whenever the counter value is + * GREATER THAN OR EQUAL TO the value specified in the match register when counting up, LESS THEN OR + * EQUAL TO the match value when counting down. If this bit is zero, a match is only be active + * during the cycle when the counter is equal to the match value. + */ +#define SCT_EV_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_MATCHMEM_SHIFT)) & SCT_EV_CTRL_MATCHMEM_MASK) + +#define SCT_EV_CTRL_DIRECTION_MASK (0x600000U) +#define SCT_EV_CTRL_DIRECTION_SHIFT (21U) /*! DIRECTION - Direction qualifier for event generation. This field only applies when the counters * are operating in BIDIR mode. If BIDIR = 0, the SCT ignores this field. Value 0x3 is reserved. * 0b00..Direction independent. This event is triggered regardless of the count direction. * 0b01..Counting up. This event is triggered only during up-counting when BIDIR = 1. * 0b10..Counting down. This event is triggered only during down-counting when BIDIR = 1. */ -#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK) +#define SCT_EV_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EV_CTRL_DIRECTION_SHIFT)) & SCT_EV_CTRL_DIRECTION_MASK) /*! @} */ -/* The count of SCT_EVENT_CTRL */ -#define SCT_EVENT_CTRL_COUNT (16U) +/* The count of SCT_EV_CTRL */ +#define SCT_EV_CTRL_COUNT (16U) /*! @name OUT_SET - SCT output 0 set register */ /*! @{ */ + #define SCT_OUT_SET_SET_MASK (0xFFFFU) #define SCT_OUT_SET_SET_SHIFT (0U) +/*! SET - A 1 in bit m selects event m to set output n (or clear it if SETCLRn = 0x1 or 0x2) output + * 0 = bit 0, output 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ #define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK) /*! @} */ @@ -15432,8 +19287,14 @@ typedef struct { /*! @name OUT_CLR - SCT output 0 clear register */ /*! @{ */ + #define SCT_OUT_CLR_CLR_MASK (0xFFFFU) #define SCT_OUT_CLR_CLR_SHIFT (0U) +/*! CLR - A 1 in bit m selects event m to clear output n (or set it if SETCLRn = 0x1 or 0x2) event 0 + * = bit 0, event 1 = bit 1, etc. The number of bits = number of events in this SCT. When the + * counter is used in bi-directional mode, it is possible to reverse the action specified by the + * output set and clear registers when counting down, See the OUTPUTCTRL register. + */ #define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK) /*! @} */ @@ -15447,7 +19308,7 @@ typedef struct { /* SCT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral SCT0 base address */ #define SCT0_BASE (0x50085000u) /** Peripheral SCT0 base address */ @@ -15544,220 +19405,401 @@ typedef struct { /*! @name CTRL - Control register */ /*! @{ */ + #define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U) #define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U) +/*! CONTROLLER_RESET - Controller reset. + */ #define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK) + #define SDIF_CTRL_FIFO_RESET_MASK (0x2U) #define SDIF_CTRL_FIFO_RESET_SHIFT (1U) +/*! FIFO_RESET - Fifo reset. + */ #define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK) + #define SDIF_CTRL_DMA_RESET_MASK (0x4U) #define SDIF_CTRL_DMA_RESET_SHIFT (2U) +/*! DMA_RESET - DMA reset. + */ #define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK) + #define SDIF_CTRL_INT_ENABLE_MASK (0x10U) #define SDIF_CTRL_INT_ENABLE_SHIFT (4U) +/*! INT_ENABLE - Global interrupt enable/disable bit. + */ #define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK) + #define SDIF_CTRL_READ_WAIT_MASK (0x40U) #define SDIF_CTRL_READ_WAIT_SHIFT (6U) +/*! READ_WAIT - Read/wait. + */ #define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK) + #define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U) #define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U) +/*! SEND_IRQ_RESPONSE - Send irq response. + */ #define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK) + #define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U) #define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U) +/*! ABORT_READ_DATA - Abort read data. + */ #define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK) + #define SDIF_CTRL_SEND_CCSD_MASK (0x200U) #define SDIF_CTRL_SEND_CCSD_SHIFT (9U) +/*! SEND_CCSD - Send ccsd. + */ #define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK) + #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U) #define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U) +/*! SEND_AUTO_STOP_CCSD - Send auto stop ccsd. + */ #define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK) + #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U) #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U) +/*! CEATA_DEVICE_INTERRUPT_STATUS - CEATA device interrupt status. + */ #define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK) + #define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U) #define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U) +/*! CARD_VOLTAGE_A0 - Controls the state of the SD_VOLT0 pin. + */ #define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK) + #define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U) #define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U) +/*! CARD_VOLTAGE_A1 - Controls the state of the SD_VOLT1 pin. + */ #define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK) + #define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U) #define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U) +/*! CARD_VOLTAGE_A2 - Controls the state of the SD_VOLT2 pin. + */ #define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK) + #define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U) #define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U) +/*! USE_INTERNAL_DMAC - SD/MMC DMA use. + */ #define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) /*! @} */ /*! @name PWREN - Power Enable register */ /*! @{ */ + #define SDIF_PWREN_POWER_ENABLE0_MASK (0x1U) #define SDIF_PWREN_POWER_ENABLE0_SHIFT (0U) +/*! POWER_ENABLE0 - Power on/off switch for card 0; once power is turned on, software should wait + * for regulator/switch ramp-up time before trying to initialize card 0. + */ #define SDIF_PWREN_POWER_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE0_SHIFT)) & SDIF_PWREN_POWER_ENABLE0_MASK) + #define SDIF_PWREN_POWER_ENABLE1_MASK (0x2U) #define SDIF_PWREN_POWER_ENABLE1_SHIFT (1U) +/*! POWER_ENABLE1 - Power on/off switch for card 1; once power is turned on, software should wait + * for regulator/switch ramp-up time before trying to initialize card 1. + */ #define SDIF_PWREN_POWER_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE1_SHIFT)) & SDIF_PWREN_POWER_ENABLE1_MASK) /*! @} */ /*! @name CLKDIV - Clock Divider register */ /*! @{ */ + #define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU) #define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U) +/*! CLK_DIVIDER0 - Clock divider-0 value. + */ #define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK) /*! @} */ /*! @name CLKENA - Clock Enable register */ /*! @{ */ + #define SDIF_CLKENA_CCLK0_ENABLE_MASK (0x1U) #define SDIF_CLKENA_CCLK0_ENABLE_SHIFT (0U) +/*! CCLK0_ENABLE - Clock-enable control for SD card 0 clock. + */ #define SDIF_CLKENA_CCLK0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK0_ENABLE_MASK) + #define SDIF_CLKENA_CCLK1_ENABLE_MASK (0x2U) #define SDIF_CLKENA_CCLK1_ENABLE_SHIFT (1U) +/*! CCLK1_ENABLE - Clock-enable control for SD card 1 clock. + */ #define SDIF_CLKENA_CCLK1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK1_ENABLE_MASK) + #define SDIF_CLKENA_CCLK0_LOW_POWER_MASK (0x10000U) #define SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT (16U) +/*! CCLK0_LOW_POWER - Low-power control for SD card 0 clock. + */ #define SDIF_CLKENA_CCLK0_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK0_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK0_LOW_POWER_MASK) + #define SDIF_CLKENA_CCLK1_LOW_POWER_MASK (0x20000U) #define SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT (17U) +/*! CCLK1_LOW_POWER - Low-power control for SD card 1 clock. + */ #define SDIF_CLKENA_CCLK1_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK1_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK1_LOW_POWER_MASK) /*! @} */ /*! @name TMOUT - Time-out register */ /*! @{ */ + #define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU) #define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U) +/*! RESPONSE_TIMEOUT - Response time-out value. + */ #define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK) + #define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U) #define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U) +/*! DATA_TIMEOUT - Value for card Data Read time-out; same value also used for Data Starvation by Host time-out. + */ #define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK) /*! @} */ /*! @name CTYPE - Card Type register */ /*! @{ */ + #define SDIF_CTYPE_CARD0_WIDTH0_MASK (0x1U) #define SDIF_CTYPE_CARD0_WIDTH0_SHIFT (0U) +/*! CARD0_WIDTH0 - Indicates if card 0 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit + * modes only work when 8-bit mode in CARD0_WIDTH1 is not enabled (bit 16 in this register is set + * to 0). + */ #define SDIF_CTYPE_CARD0_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH0_MASK) + #define SDIF_CTYPE_CARD1_WIDTH0_MASK (0x2U) #define SDIF_CTYPE_CARD1_WIDTH0_SHIFT (1U) +/*! CARD1_WIDTH0 - Indicates if card 1 is 1-bit or 4-bit: 0 - 1-bit mode 1 - 4-bit mode 1 and 4-bit + * modes only work when 8-bit mode in CARD1_WIDTH1 is not enabled (bit 16 in this register is set + * to 0). + */ #define SDIF_CTYPE_CARD1_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH0_MASK) + #define SDIF_CTYPE_CARD0_WIDTH1_MASK (0x10000U) #define SDIF_CTYPE_CARD0_WIDTH1_SHIFT (16U) +/*! CARD0_WIDTH1 - Indicates if card 0 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + */ #define SDIF_CTYPE_CARD0_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD0_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD0_WIDTH1_MASK) + #define SDIF_CTYPE_CARD1_WIDTH1_MASK (0x20000U) #define SDIF_CTYPE_CARD1_WIDTH1_SHIFT (17U) +/*! CARD1_WIDTH1 - Indicates if card 1 is 8-bit: 0 - Non 8-bit mode 1 - 8-bit mode. + */ #define SDIF_CTYPE_CARD1_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD1_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD1_WIDTH1_MASK) /*! @} */ /*! @name BLKSIZ - Block Size register */ /*! @{ */ + #define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU) #define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U) +/*! BLOCK_SIZE - Block size. + */ #define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK) /*! @} */ /*! @name BYTCNT - Byte Count register */ /*! @{ */ + #define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU) #define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U) +/*! BYTE_COUNT - Number of bytes to be transferred; should be integer multiple of Block Size for block transfers. + */ #define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK) /*! @} */ /*! @name INTMASK - Interrupt Mask register */ /*! @{ */ + #define SDIF_INTMASK_CDET_MASK (0x1U) #define SDIF_INTMASK_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ #define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK) + #define SDIF_INTMASK_RE_MASK (0x2U) #define SDIF_INTMASK_RE_SHIFT (1U) +/*! RE - Response error. + */ #define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK) + #define SDIF_INTMASK_CDONE_MASK (0x4U) #define SDIF_INTMASK_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ #define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK) + #define SDIF_INTMASK_DTO_MASK (0x8U) #define SDIF_INTMASK_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ #define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK) + #define SDIF_INTMASK_TXDR_MASK (0x10U) #define SDIF_INTMASK_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ #define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK) + #define SDIF_INTMASK_RXDR_MASK (0x20U) #define SDIF_INTMASK_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ #define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK) + #define SDIF_INTMASK_RCRC_MASK (0x40U) #define SDIF_INTMASK_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ #define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK) + #define SDIF_INTMASK_DCRC_MASK (0x80U) #define SDIF_INTMASK_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ #define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK) + #define SDIF_INTMASK_RTO_MASK (0x100U) #define SDIF_INTMASK_RTO_SHIFT (8U) +/*! RTO - Response time-out. + */ #define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK) + #define SDIF_INTMASK_DRTO_MASK (0x200U) #define SDIF_INTMASK_DRTO_SHIFT (9U) +/*! DRTO - Data read time-out. + */ #define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK) + #define SDIF_INTMASK_HTO_MASK (0x400U) #define SDIF_INTMASK_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ #define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK) + #define SDIF_INTMASK_FRUN_MASK (0x800U) #define SDIF_INTMASK_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ #define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK) + #define SDIF_INTMASK_HLE_MASK (0x1000U) #define SDIF_INTMASK_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ #define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK) + #define SDIF_INTMASK_SBE_MASK (0x2000U) #define SDIF_INTMASK_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ #define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK) + #define SDIF_INTMASK_ACD_MASK (0x4000U) #define SDIF_INTMASK_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ #define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK) + #define SDIF_INTMASK_EBE_MASK (0x8000U) #define SDIF_INTMASK_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/Write no CRC. + */ #define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK) + #define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U) #define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U) +/*! SDIO_INT_MASK - Mask SDIO interrupt. + */ #define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK) /*! @} */ /*! @name CMDARG - Command Argument register */ /*! @{ */ + #define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU) #define SDIF_CMDARG_CMD_ARG_SHIFT (0U) +/*! CMD_ARG - Value indicates command argument to be passed to card. + */ #define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK) /*! @} */ /*! @name CMD - Command register */ /*! @{ */ + #define SDIF_CMD_CMD_INDEX_MASK (0x3FU) #define SDIF_CMD_CMD_INDEX_SHIFT (0U) +/*! CMD_INDEX - Command index. + */ #define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK) + #define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U) #define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U) +/*! RESPONSE_EXPECT - Response expect. + */ #define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK) + #define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U) #define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U) +/*! RESPONSE_LENGTH - Response length. + */ #define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK) + #define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U) #define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U) +/*! CHECK_RESPONSE_CRC - Check response CRC. + */ #define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK) + #define SDIF_CMD_DATA_EXPECTED_MASK (0x200U) #define SDIF_CMD_DATA_EXPECTED_SHIFT (9U) +/*! DATA_EXPECTED - Data expected. + */ #define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK) + #define SDIF_CMD_READ_WRITE_MASK (0x400U) #define SDIF_CMD_READ_WRITE_SHIFT (10U) +/*! READ_WRITE - read/write. + */ #define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK) + #define SDIF_CMD_TRANSFER_MODE_MASK (0x800U) #define SDIF_CMD_TRANSFER_MODE_SHIFT (11U) +/*! TRANSFER_MODE - Transfer mode. + */ #define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK) + #define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U) #define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U) +/*! SEND_AUTO_STOP - Send auto stop. + */ #define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK) + #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U) #define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U) +/*! WAIT_PRVDATA_COMPLETE - Wait prvdata complete. + */ #define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK) + #define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U) #define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U) +/*! STOP_ABORT_CMD - Stop abort command. + */ #define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK) + #define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U) #define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U) +/*! SEND_INITIALIZATION - Send initialization. + */ #define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK) + #define SDIF_CMD_CARD_NUMBER_MASK (0x1F0000U) #define SDIF_CMD_CARD_NUMBER_SHIFT (16U) /*! CARD_NUMBER - Specifies the card number of SDCARD for which the current Command is being executed @@ -15765,42 +19807,75 @@ typedef struct { * 0b00001..Command will be execute on SDCARD 1 */ #define SDIF_CMD_CARD_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CARD_NUMBER_SHIFT)) & SDIF_CMD_CARD_NUMBER_MASK) + #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U) #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U) +/*! UPDATE_CLOCK_REGISTERS_ONLY - Update clock registers only. + */ #define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK) + #define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U) #define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U) +/*! READ_CEATA_DEVICE - Read ceata device. + */ #define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK) + #define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U) #define SDIF_CMD_CCS_EXPECTED_SHIFT (23U) +/*! CCS_EXPECTED - CCS expected. + */ #define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK) + #define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U) #define SDIF_CMD_ENABLE_BOOT_SHIFT (24U) +/*! ENABLE_BOOT - Enable Boot - this bit should be set only for mandatory boot mode. + */ #define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK) + #define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U) #define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U) +/*! EXPECT_BOOT_ACK - Expect Boot Acknowledge. + */ #define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK) + #define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U) #define SDIF_CMD_DISABLE_BOOT_SHIFT (26U) +/*! DISABLE_BOOT - Disable Boot. + */ #define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK) + #define SDIF_CMD_BOOT_MODE_MASK (0x8000000U) #define SDIF_CMD_BOOT_MODE_SHIFT (27U) +/*! BOOT_MODE - Boot Mode. + */ #define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK) + #define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U) #define SDIF_CMD_VOLT_SWITCH_SHIFT (28U) +/*! VOLT_SWITCH - Voltage switch bit. + */ #define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK) + #define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U) #define SDIF_CMD_USE_HOLD_REG_SHIFT (29U) +/*! USE_HOLD_REG - Use Hold Register. + */ #define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK) + #define SDIF_CMD_START_CMD_MASK (0x80000000U) #define SDIF_CMD_START_CMD_SHIFT (31U) +/*! START_CMD - Start command. + */ #define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK) /*! @} */ /*! @name RESP - Response register */ /*! @{ */ + #define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU) #define SDIF_RESP_RESPONSE_SHIFT (0U) +/*! RESPONSE - Bits of response. + */ #define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK) /*! @} */ @@ -15809,339 +19884,602 @@ typedef struct { /*! @name MINTSTS - Masked Interrupt Status register */ /*! @{ */ + #define SDIF_MINTSTS_CDET_MASK (0x1U) #define SDIF_MINTSTS_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ #define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK) + #define SDIF_MINTSTS_RE_MASK (0x2U) #define SDIF_MINTSTS_RE_SHIFT (1U) +/*! RE - Response error. + */ #define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK) + #define SDIF_MINTSTS_CDONE_MASK (0x4U) #define SDIF_MINTSTS_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ #define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK) + #define SDIF_MINTSTS_DTO_MASK (0x8U) #define SDIF_MINTSTS_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ #define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK) + #define SDIF_MINTSTS_TXDR_MASK (0x10U) #define SDIF_MINTSTS_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ #define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK) + #define SDIF_MINTSTS_RXDR_MASK (0x20U) #define SDIF_MINTSTS_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ #define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK) + #define SDIF_MINTSTS_RCRC_MASK (0x40U) #define SDIF_MINTSTS_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ #define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK) + #define SDIF_MINTSTS_DCRC_MASK (0x80U) #define SDIF_MINTSTS_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ #define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK) + #define SDIF_MINTSTS_RTO_MASK (0x100U) #define SDIF_MINTSTS_RTO_SHIFT (8U) +/*! RTO - Response time-out. + */ #define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK) + #define SDIF_MINTSTS_DRTO_MASK (0x200U) #define SDIF_MINTSTS_DRTO_SHIFT (9U) +/*! DRTO - Data read time-out. + */ #define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK) + #define SDIF_MINTSTS_HTO_MASK (0x400U) #define SDIF_MINTSTS_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ #define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK) + #define SDIF_MINTSTS_FRUN_MASK (0x800U) #define SDIF_MINTSTS_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ #define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK) + #define SDIF_MINTSTS_HLE_MASK (0x1000U) #define SDIF_MINTSTS_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ #define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK) + #define SDIF_MINTSTS_SBE_MASK (0x2000U) #define SDIF_MINTSTS_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ #define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK) + #define SDIF_MINTSTS_ACD_MASK (0x4000U) #define SDIF_MINTSTS_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ #define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK) + #define SDIF_MINTSTS_EBE_MASK (0x8000U) #define SDIF_MINTSTS_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/write no CRC. + */ #define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK) + #define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U) #define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U) +/*! SDIO_INTERRUPT - Interrupt from SDIO card. + */ #define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK) /*! @} */ /*! @name RINTSTS - Raw Interrupt Status register */ /*! @{ */ + #define SDIF_RINTSTS_CDET_MASK (0x1U) #define SDIF_RINTSTS_CDET_SHIFT (0U) +/*! CDET - Card detect. + */ #define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK) + #define SDIF_RINTSTS_RE_MASK (0x2U) #define SDIF_RINTSTS_RE_SHIFT (1U) +/*! RE - Response error. + */ #define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK) + #define SDIF_RINTSTS_CDONE_MASK (0x4U) #define SDIF_RINTSTS_CDONE_SHIFT (2U) +/*! CDONE - Command done. + */ #define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK) + #define SDIF_RINTSTS_DTO_MASK (0x8U) #define SDIF_RINTSTS_DTO_SHIFT (3U) +/*! DTO - Data transfer over. + */ #define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK) + #define SDIF_RINTSTS_TXDR_MASK (0x10U) #define SDIF_RINTSTS_TXDR_SHIFT (4U) +/*! TXDR - Transmit FIFO data request. + */ #define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK) + #define SDIF_RINTSTS_RXDR_MASK (0x20U) #define SDIF_RINTSTS_RXDR_SHIFT (5U) +/*! RXDR - Receive FIFO data request. + */ #define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK) + #define SDIF_RINTSTS_RCRC_MASK (0x40U) #define SDIF_RINTSTS_RCRC_SHIFT (6U) +/*! RCRC - Response CRC error. + */ #define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK) + #define SDIF_RINTSTS_DCRC_MASK (0x80U) #define SDIF_RINTSTS_DCRC_SHIFT (7U) +/*! DCRC - Data CRC error. + */ #define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK) + #define SDIF_RINTSTS_RTO_BAR_MASK (0x100U) #define SDIF_RINTSTS_RTO_BAR_SHIFT (8U) +/*! RTO_BAR - Response time-out (RTO)/Boot Ack Received (BAR). + */ #define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK) + #define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U) #define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U) +/*! DRTO_BDS - Data read time-out (DRTO)/Boot Data Start (BDS). + */ #define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK) + #define SDIF_RINTSTS_HTO_MASK (0x400U) #define SDIF_RINTSTS_HTO_SHIFT (10U) +/*! HTO - Data starvation-by-host time-out (HTO). + */ #define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK) + #define SDIF_RINTSTS_FRUN_MASK (0x800U) #define SDIF_RINTSTS_FRUN_SHIFT (11U) +/*! FRUN - FIFO underrun/overrun error. + */ #define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK) + #define SDIF_RINTSTS_HLE_MASK (0x1000U) #define SDIF_RINTSTS_HLE_SHIFT (12U) +/*! HLE - Hardware locked write error. + */ #define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK) + #define SDIF_RINTSTS_SBE_MASK (0x2000U) #define SDIF_RINTSTS_SBE_SHIFT (13U) +/*! SBE - Start-bit error. + */ #define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK) + #define SDIF_RINTSTS_ACD_MASK (0x4000U) #define SDIF_RINTSTS_ACD_SHIFT (14U) +/*! ACD - Auto command done. + */ #define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK) + #define SDIF_RINTSTS_EBE_MASK (0x8000U) #define SDIF_RINTSTS_EBE_SHIFT (15U) +/*! EBE - End-bit error (read)/write no CRC. + */ #define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK) + #define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U) #define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U) +/*! SDIO_INTERRUPT - Interrupt from SDIO card. + */ #define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK) /*! @} */ /*! @name STATUS - Status register */ /*! @{ */ + #define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U) #define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U) +/*! FIFO_RX_WATERMARK - FIFO reached Receive watermark level; not qualified with data transfer. + */ #define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK) + #define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U) #define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U) +/*! FIFO_TX_WATERMARK - FIFO reached Transmit watermark level; not qualified with data transfer. + */ #define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK) + #define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U) #define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U) +/*! FIFO_EMPTY - FIFO is empty status. + */ #define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK) + #define SDIF_STATUS_FIFO_FULL_MASK (0x8U) #define SDIF_STATUS_FIFO_FULL_SHIFT (3U) +/*! FIFO_FULL - FIFO is full status. + */ #define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK) + #define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U) #define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U) +/*! CMDFSMSTATES - Command FSM states: 0 - Idle 1 - Send init sequence 2 - Tx cmd start bit 3 - Tx + * cmd tx bit 4 - Tx cmd index + arg 5 - Tx cmd crc7 6 - Tx cmd end bit 7 - Rx resp start bit 8 - + * Rx resp IRQ response 9 - Rx resp tx bit 10 - Rx resp cmd idx 11 - Rx resp data 12 - Rx resp + * crc7 13 - Rx resp end bit 14 - Cmd path wait NCC 15 - Wait; CMD-to-response turnaround NOTE: The + * command FSM state is represented using 19 bits. + */ #define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK) + #define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U) #define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U) +/*! DATA_3_STATUS - Raw selected card_data[3]; checks whether card is present 0 - card not present 1 - card present. + */ #define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK) + #define SDIF_STATUS_DATA_BUSY_MASK (0x200U) #define SDIF_STATUS_DATA_BUSY_SHIFT (9U) +/*! DATA_BUSY - Inverted version of raw selected card_data[0] 0 - card data not busy 1 - card data busy. + */ #define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK) + #define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U) #define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U) +/*! DATA_STATE_MC_BUSY - Data transmit or receive state-machine is busy. + */ #define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK) + #define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U) #define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U) +/*! RESPONSE_INDEX - Index of previous response, including any auto-stop sent by core. + */ #define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK) + #define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U) #define SDIF_STATUS_FIFO_COUNT_SHIFT (17U) +/*! FIFO_COUNT - FIFO count - Number of filled locations in FIFO. + */ #define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK) + #define SDIF_STATUS_DMA_ACK_MASK (0x40000000U) #define SDIF_STATUS_DMA_ACK_SHIFT (30U) +/*! DMA_ACK - DMA acknowledge signal state. + */ #define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK) + #define SDIF_STATUS_DMA_REQ_MASK (0x80000000U) #define SDIF_STATUS_DMA_REQ_SHIFT (31U) +/*! DMA_REQ - DMA request signal state. + */ #define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK) /*! @} */ /*! @name FIFOTH - FIFO Threshold Watermark register */ /*! @{ */ + #define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU) #define SDIF_FIFOTH_TX_WMARK_SHIFT (0U) +/*! TX_WMARK - FIFO threshold watermark level when transmitting data to card. + */ #define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK) + #define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U) #define SDIF_FIFOTH_RX_WMARK_SHIFT (16U) +/*! RX_WMARK - FIFO threshold watermark level when receiving data to card. + */ #define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK) + #define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U) #define SDIF_FIFOTH_DMA_MTS_SHIFT (28U) +/*! DMA_MTS - Burst size of multiple transaction; should be programmed same as DW-DMA controller + * multiple-transaction-size SRC/DEST_MSIZE. + */ #define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK) /*! @} */ /*! @name CDETECT - Card Detect register */ /*! @{ */ + #define SDIF_CDETECT_CARD0_DETECT_MASK (0x1U) #define SDIF_CDETECT_CARD0_DETECT_SHIFT (0U) +/*! CARD0_DETECT - Card 0 detect + */ #define SDIF_CDETECT_CARD0_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD0_DETECT_SHIFT)) & SDIF_CDETECT_CARD0_DETECT_MASK) + #define SDIF_CDETECT_CARD1_DETECT_MASK (0x2U) #define SDIF_CDETECT_CARD1_DETECT_SHIFT (1U) +/*! CARD1_DETECT - Card 1 detect + */ #define SDIF_CDETECT_CARD1_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD1_DETECT_SHIFT)) & SDIF_CDETECT_CARD1_DETECT_MASK) /*! @} */ /*! @name WRTPRT - Write Protect register */ /*! @{ */ + #define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U) #define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U) +/*! WRITE_PROTECT - Write protect. + */ #define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK) /*! @} */ /*! @name TCBCNT - Transferred CIU Card Byte Count register */ /*! @{ */ + #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU) #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U) +/*! TRANS_CARD_BYTE_COUNT - Number of bytes transferred by CIU unit to card. + */ #define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK) /*! @} */ /*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */ /*! @{ */ + #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU) #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U) +/*! TRANS_FIFO_BYTE_COUNT - Number of bytes transferred between Host/DMA memory and BIU FIFO. + */ #define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK) /*! @} */ /*! @name DEBNCE - Debounce Count register */ /*! @{ */ + #define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU) #define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U) +/*! DEBOUNCE_COUNT - Number of host clocks (SD_CLK) used by debounce filter logic for card detect; typical debounce time is 5-25 ms. + */ #define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK) /*! @} */ /*! @name RST_N - Hardware Reset */ /*! @{ */ + #define SDIF_RST_N_CARD_RESET_MASK (0x1U) #define SDIF_RST_N_CARD_RESET_SHIFT (0U) +/*! CARD_RESET - Hardware reset. + */ #define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK) /*! @} */ /*! @name BMOD - Bus Mode register */ /*! @{ */ + #define SDIF_BMOD_SWR_MASK (0x1U) #define SDIF_BMOD_SWR_SHIFT (0U) +/*! SWR - Software Reset. + */ #define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK) + #define SDIF_BMOD_FB_MASK (0x2U) #define SDIF_BMOD_FB_SHIFT (1U) +/*! FB - Fixed Burst. + */ #define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK) + #define SDIF_BMOD_DSL_MASK (0x7CU) #define SDIF_BMOD_DSL_SHIFT (2U) +/*! DSL - Descriptor Skip Length. + */ #define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK) + #define SDIF_BMOD_DE_MASK (0x80U) #define SDIF_BMOD_DE_SHIFT (7U) +/*! DE - SD/MMC DMA Enable. + */ #define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK) + #define SDIF_BMOD_PBL_MASK (0x700U) #define SDIF_BMOD_PBL_SHIFT (8U) +/*! PBL - Programmable Burst Length. + */ #define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK) /*! @} */ /*! @name PLDMND - Poll Demand register */ /*! @{ */ + #define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU) #define SDIF_PLDMND_PD_SHIFT (0U) +/*! PD - Poll Demand. + */ #define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK) /*! @} */ /*! @name DBADDR - Descriptor List Base Address register */ /*! @{ */ + #define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU) #define SDIF_DBADDR_SDL_SHIFT (0U) +/*! SDL - Start of Descriptor List. + */ #define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK) /*! @} */ /*! @name IDSTS - Internal DMAC Status register */ /*! @{ */ + #define SDIF_IDSTS_TI_MASK (0x1U) #define SDIF_IDSTS_TI_SHIFT (0U) +/*! TI - Transmit Interrupt. + */ #define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK) + #define SDIF_IDSTS_RI_MASK (0x2U) #define SDIF_IDSTS_RI_SHIFT (1U) +/*! RI - Receive Interrupt. + */ #define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK) + #define SDIF_IDSTS_FBE_MASK (0x4U) #define SDIF_IDSTS_FBE_SHIFT (2U) +/*! FBE - Fatal Bus Error Interrupt. + */ #define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK) + #define SDIF_IDSTS_DU_MASK (0x10U) #define SDIF_IDSTS_DU_SHIFT (4U) +/*! DU - Descriptor Unavailable Interrupt. + */ #define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK) + #define SDIF_IDSTS_CES_MASK (0x20U) #define SDIF_IDSTS_CES_SHIFT (5U) +/*! CES - Card Error Summary. + */ #define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK) + #define SDIF_IDSTS_NIS_MASK (0x100U) #define SDIF_IDSTS_NIS_SHIFT (8U) +/*! NIS - Normal Interrupt Summary. + */ #define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK) + #define SDIF_IDSTS_AIS_MASK (0x200U) #define SDIF_IDSTS_AIS_SHIFT (9U) +/*! AIS - Abnormal Interrupt Summary. + */ #define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK) + #define SDIF_IDSTS_EB_MASK (0x1C00U) #define SDIF_IDSTS_EB_SHIFT (10U) +/*! EB - Error Bits. + */ #define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK) + #define SDIF_IDSTS_FSM_MASK (0x1E000U) #define SDIF_IDSTS_FSM_SHIFT (13U) +/*! FSM - DMAC state machine present state. + */ #define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK) /*! @} */ /*! @name IDINTEN - Internal DMAC Interrupt Enable register */ /*! @{ */ + #define SDIF_IDINTEN_TI_MASK (0x1U) #define SDIF_IDINTEN_TI_SHIFT (0U) +/*! TI - Transmit Interrupt Enable. + */ #define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK) + #define SDIF_IDINTEN_RI_MASK (0x2U) #define SDIF_IDINTEN_RI_SHIFT (1U) +/*! RI - Receive Interrupt Enable. + */ #define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK) + #define SDIF_IDINTEN_FBE_MASK (0x4U) #define SDIF_IDINTEN_FBE_SHIFT (2U) +/*! FBE - Fatal Bus Error Enable. + */ #define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK) + #define SDIF_IDINTEN_DU_MASK (0x10U) #define SDIF_IDINTEN_DU_SHIFT (4U) +/*! DU - Descriptor Unavailable Interrupt. + */ #define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK) + #define SDIF_IDINTEN_CES_MASK (0x20U) #define SDIF_IDINTEN_CES_SHIFT (5U) +/*! CES - Card Error summary Interrupt Enable. + */ #define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK) + #define SDIF_IDINTEN_NIS_MASK (0x100U) #define SDIF_IDINTEN_NIS_SHIFT (8U) +/*! NIS - Normal Interrupt Summary Enable. + */ #define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK) + #define SDIF_IDINTEN_AIS_MASK (0x200U) #define SDIF_IDINTEN_AIS_SHIFT (9U) +/*! AIS - Abnormal Interrupt Summary Enable. + */ #define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK) /*! @} */ /*! @name DSCADDR - Current Host Descriptor Address register */ /*! @{ */ + #define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU) #define SDIF_DSCADDR_HDA_SHIFT (0U) +/*! HDA - Host Descriptor Address Pointer. + */ #define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK) /*! @} */ /*! @name BUFADDR - Current Buffer Descriptor Address register */ /*! @{ */ + #define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU) #define SDIF_BUFADDR_HBA_SHIFT (0U) +/*! HBA - Host Buffer Address Pointer. + */ #define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK) /*! @} */ /*! @name CARDTHRCTL - Card Threshold Control */ /*! @{ */ + #define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U) #define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U) +/*! CARDRDTHREN - Card Read Threshold Enable. + */ #define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK) + #define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U) #define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U) +/*! BSYCLRINTEN - Busy Clear Interrupt Enable. + */ #define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK) + #define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U) #define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U) +/*! CARDTHRESHOLD - Card Threshold size. + */ #define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK) /*! @} */ /*! @name BACKENDPWR - Power control */ /*! @{ */ + #define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U) #define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U) +/*! BACKENDPWR - Back-end Power control for card application. + */ #define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK) /*! @} */ /*! @name FIFO - SDIF FIFO */ /*! @{ */ + #define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU) #define SDIF_FIFO_DATA_SHIFT (0U) +/*! DATA - SDIF FIFO. + */ #define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK) /*! @} */ @@ -16155,7 +20493,7 @@ typedef struct { /* SDIF - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral SDIF base address */ #define SDIF_BASE (0x5009B000u) /** Peripheral SDIF base address */ @@ -16224,7 +20562,9 @@ typedef struct { __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ uint8_t RESERVED_6[12]; __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_7[440]; + uint8_t RESERVED_7[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_8[432]; __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ } SPI_Type; @@ -16239,6 +20579,7 @@ typedef struct { /*! @name CFG - SPI Configuration register */ /*! @{ */ + #define SPI_CFG_ENABLE_MASK (0x1U) #define SPI_CFG_ENABLE_SHIFT (0U) /*! ENABLE - SPI enable. @@ -16246,6 +20587,7 @@ typedef struct { * 0b1..Enabled. The SPI is enabled for operation. */ #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) + #define SPI_CFG_MASTER_MASK (0x4U) #define SPI_CFG_MASTER_SHIFT (2U) /*! MASTER - Master mode select. @@ -16253,6 +20595,7 @@ typedef struct { * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. */ #define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) + #define SPI_CFG_LSBF_MASK (0x8U) #define SPI_CFG_LSBF_SHIFT (3U) /*! LSBF - LSB First mode enable. @@ -16260,6 +20603,7 @@ typedef struct { * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). */ #define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) + #define SPI_CFG_CPHA_MASK (0x10U) #define SPI_CFG_CPHA_SHIFT (4U) /*! CPHA - Clock Phase select. @@ -16269,6 +20613,7 @@ typedef struct { * changes away from the rest state). Data is captured on the following edge. */ #define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) + #define SPI_CFG_CPOL_MASK (0x20U) #define SPI_CFG_CPOL_SHIFT (5U) /*! CPOL - Clock Polarity select. @@ -16276,6 +20621,7 @@ typedef struct { * 0b1..High. The rest state of the clock (between transfers) is high. */ #define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) + #define SPI_CFG_LOOP_MASK (0x80U) #define SPI_CFG_LOOP_SHIFT (7U) /*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit @@ -16284,6 +20630,7 @@ typedef struct { * 0b1..Enabled. */ #define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) + #define SPI_CFG_SPOL0_MASK (0x100U) #define SPI_CFG_SPOL0_SHIFT (8U) /*! SPOL0 - SSEL0 Polarity select. @@ -16291,6 +20638,7 @@ typedef struct { * 0b1..High. The SSEL0 pin is active high. */ #define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) + #define SPI_CFG_SPOL1_MASK (0x200U) #define SPI_CFG_SPOL1_SHIFT (9U) /*! SPOL1 - SSEL1 Polarity select. @@ -16298,6 +20646,7 @@ typedef struct { * 0b1..High. The SSEL1 pin is active high. */ #define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) + #define SPI_CFG_SPOL2_MASK (0x400U) #define SPI_CFG_SPOL2_SHIFT (10U) /*! SPOL2 - SSEL2 Polarity select. @@ -16305,6 +20654,7 @@ typedef struct { * 0b1..High. The SSEL2 pin is active high. */ #define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK) + #define SPI_CFG_SPOL3_MASK (0x800U) #define SPI_CFG_SPOL3_SHIFT (11U) /*! SPOL3 - SSEL3 Polarity select. @@ -16316,41 +20666,94 @@ typedef struct { /*! @name DLY - SPI Delay register */ /*! @{ */ + #define SPI_DLY_PRE_DELAY_MASK (0xFU) #define SPI_DLY_PRE_DELAY_SHIFT (0U) +/*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data + * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This + * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI + * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are + * inserted. + */ #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) + #define SPI_DLY_POST_DELAY_MASK (0xF0U) #define SPI_DLY_POST_DELAY_SHIFT (4U) +/*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL + * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock + * times are inserted. 0xF = 15 SPI clock times are inserted. + */ #define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) + #define SPI_DLY_FRAME_DELAY_MASK (0xF00U) #define SPI_DLY_FRAME_DELAY_SHIFT (8U) +/*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current + * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 + * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock + * times are inserted. + */ #define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) + #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) +/*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between + * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 + * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that + * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 + * SPI clock times. + */ #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) /*! @} */ /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */ /*! @{ */ + #define SPI_STAT_SSA_MASK (0x10U) #define SPI_STAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from + * deasserted to asserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a + * slave mode access begins. This flag is cleared by software. + */ #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) + #define SPI_STAT_SSD_MASK (0x20U) #define SPI_STAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to + * deasserted, in both master and slave modes. This allows determining when the SPI + * transmit/receive functions become idle. This flag is cleared by software. + */ #define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) + #define SPI_STAT_STALLED_MASK (0x40U) #define SPI_STAT_STALLED_SHIFT (6U) +/*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. + */ #define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) + #define SPI_STAT_ENDTRANSFER_MASK (0x80U) #define SPI_STAT_ENDTRANSFER_SHIFT (7U) +/*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current + * transfer when the transmitter finishes any activity already in progress, as if the EOT flag + * had been set prior to the last transmission. This capability is included to support cases where + * it is not known when transmit data is written that it will be the end of a transfer. The bit + * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end + * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. + */ #define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) + #define SPI_STAT_MSTIDLE_MASK (0x100U) #define SPI_STAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. + * This means that the transmit holding register is empty and the transmitter is not in the + * process of sending data. + */ #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) /*! @} */ /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ /*! @{ */ + #define SPI_INTENSET_SSAEN_MASK (0x10U) #define SPI_INTENSET_SSAEN_SHIFT (4U) /*! SSAEN - Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted. @@ -16358,6 +20761,7 @@ typedef struct { * 0b1..Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted. */ #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) + #define SPI_INTENSET_SSDEN_MASK (0x20U) #define SPI_INTENSET_SSDEN_SHIFT (5U) /*! SSDEN - Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted. @@ -16365,6 +20769,7 @@ typedef struct { * 0b1..Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted. */ #define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) + #define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) #define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) /*! MSTIDLEEN - Master idle interrupt enable. @@ -16376,39 +20781,64 @@ typedef struct { /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ /*! @{ */ + #define SPI_INTENCLR_SSAEN_MASK (0x10U) #define SPI_INTENCLR_SSAEN_SHIFT (4U) +/*! SSAEN - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) + #define SPI_INTENCLR_SSDEN_MASK (0x20U) #define SPI_INTENCLR_SSDEN_SHIFT (5U) +/*! SSDEN - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) + #define SPI_INTENCLR_MSTIDLE_MASK (0x100U) #define SPI_INTENCLR_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) /*! @} */ /*! @name DIV - SPI clock Divider */ /*! @{ */ + #define SPI_DIV_DIVVAL_MASK (0xFFFFU) #define SPI_DIV_DIVVAL_SHIFT (0U) +/*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the + * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, + * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results + * in FCLK/65536. + */ #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) /*! @} */ /*! @name INTSTAT - SPI Interrupt Status */ /*! @{ */ + #define SPI_INTSTAT_SSA_MASK (0x10U) #define SPI_INTSTAT_SSA_SHIFT (4U) +/*! SSA - Slave Select Assert. + */ #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) + #define SPI_INTSTAT_SSD_MASK (0x20U) #define SPI_INTSTAT_SSD_SHIFT (5U) +/*! SSD - Slave Select Deassert. + */ #define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) + #define SPI_INTSTAT_MSTIDLE_MASK (0x100U) #define SPI_INTSTAT_MSTIDLE_SHIFT (8U) +/*! MSTIDLE - Master Idle status flag. + */ #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) /*! @} */ /*! @name FIFOCFG - FIFO configuration and enable register. */ /*! @{ */ + #define SPI_FIFOCFG_ENABLETX_MASK (0x1U) #define SPI_FIFOCFG_ENABLETX_SHIFT (0U) /*! ENABLETX - Enable the transmit FIFO. @@ -16416,6 +20846,7 @@ typedef struct { * 0b1..The transmit FIFO is enabled. */ #define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK) + #define SPI_FIFOCFG_ENABLERX_MASK (0x2U) #define SPI_FIFOCFG_ENABLERX_SHIFT (1U) /*! ENABLERX - Enable the receive FIFO. @@ -16423,9 +20854,14 @@ typedef struct { * 0b1..The receive FIFO is enabled. */ #define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK) + #define SPI_FIFOCFG_SIZE_MASK (0x30U) #define SPI_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ #define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK) + #define SPI_FIFOCFG_DMATX_MASK (0x1000U) #define SPI_FIFOCFG_DMATX_SHIFT (12U) /*! DMATX - DMA configuration for transmit. @@ -16433,6 +20869,7 @@ typedef struct { * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. */ #define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK) + #define SPI_FIFOCFG_DMARX_MASK (0x2000U) #define SPI_FIFOCFG_DMARX_SHIFT (13U) /*! DMARX - DMA configuration for receive. @@ -16440,6 +20877,7 @@ typedef struct { * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. */ #define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK) + #define SPI_FIFOCFG_WAKETX_MASK (0x4000U) #define SPI_FIFOCFG_WAKETX_SHIFT (14U) /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power @@ -16452,6 +20890,7 @@ typedef struct { * FIFOTRIG, even when the TXLVL interrupt is not enabled. */ #define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK) + #define SPI_FIFOCFG_WAKERX_MASK (0x8000U) #define SPI_FIFOCFG_WAKERX_SHIFT (15U) /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power @@ -16464,54 +20903,93 @@ typedef struct { * FIFOTRIG, even when the RXLVL interrupt is not enabled. */ #define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK) + #define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U) #define SPI_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ #define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK) + #define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U) #define SPI_FIFOCFG_EMPTYRX_SHIFT (17U) -#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) -#define SPI_FIFOCFG_POPDBG_MASK (0x40000U) -#define SPI_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. */ -#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK) +#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK) /*! @} */ /*! @name FIFOSTAT - FIFO status register. */ /*! @{ */ + #define SPI_FIFOSTAT_TXERR_MASK (0x1U) #define SPI_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ #define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK) + #define SPI_FIFOSTAT_RXERR_MASK (0x2U) #define SPI_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ #define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK) + #define SPI_FIFOSTAT_PERINT_MASK (0x8U) #define SPI_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ #define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK) + #define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U) #define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ #define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK) + #define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U) #define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ #define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK) + #define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) #define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ #define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + #define SPI_FIFOSTAT_RXFULL_MASK (0x80U) #define SPI_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ #define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK) + #define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U) #define SPI_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ #define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK) + #define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define SPI_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ #define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK) /*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ /*! @{ */ + #define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U) #define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U) /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -16520,6 +20998,7 @@ typedef struct { * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. */ #define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK) + #define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U) #define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U) /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -16528,16 +21007,32 @@ typedef struct { * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. */ #define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK) + #define SPI_FIFOTRIG_TXLVL_MASK (0xF00U) #define SPI_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ #define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK) + #define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U) #define SPI_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ #define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK) /*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ /*! @{ */ + #define SPI_FIFOINTENSET_TXERR_MASK (0x1U) #define SPI_FIFOINTENSET_TXERR_SHIFT (0U) /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. @@ -16545,6 +21040,7 @@ typedef struct { * 0b1..An interrupt will be generated when a transmit error occurs. */ #define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK) + #define SPI_FIFOINTENSET_RXERR_MASK (0x2U) #define SPI_FIFOINTENSET_RXERR_SHIFT (1U) /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. @@ -16552,6 +21048,7 @@ typedef struct { * 0b1..An interrupt will be generated when a receive error occurs. */ #define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK) + #define SPI_FIFOINTENSET_TXLVL_MASK (0x4U) #define SPI_FIFOINTENSET_TXLVL_SHIFT (2U) /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level @@ -16561,6 +21058,7 @@ typedef struct { * to the level specified by TXLVL in the FIFOTRIG register. */ #define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK) + #define SPI_FIFOINTENSET_RXLVL_MASK (0x8U) #define SPI_FIFOINTENSET_RXLVL_SHIFT (3U) /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level @@ -16574,44 +21072,75 @@ typedef struct { /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ /*! @{ */ + #define SPI_FIFOINTENCLR_TXERR_MASK (0x1U) #define SPI_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK) + #define SPI_FIFOINTENCLR_RXERR_MASK (0x2U) #define SPI_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK) + #define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U) #define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK) + #define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U) #define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK) /*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ /*! @{ */ + #define SPI_FIFOINTSTAT_TXERR_MASK (0x1U) #define SPI_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ #define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK) + #define SPI_FIFOINTSTAT_RXERR_MASK (0x2U) #define SPI_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ #define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK) + #define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U) #define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ #define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK) + #define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U) #define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ #define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK) + #define SPI_FIFOINTSTAT_PERINT_MASK (0x10U) #define SPI_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ #define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK) /*! @} */ /*! @name FIFOWR - FIFO write data. */ /*! @{ */ + #define SPI_FIFOWR_TXDATA_MASK (0xFFFFU) #define SPI_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. + */ #define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK) + #define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U) #define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U) /*! TXSSEL0_N - Transmit slave select. This field asserts SSEL0 in master mode. The output on the pin is active LOW by default. @@ -16619,6 +21148,7 @@ typedef struct { * 0b1..SSEL0 not asserted. */ #define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK) + #define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U) #define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U) /*! TXSSEL1_N - Transmit slave select. This field asserts SSEL1 in master mode. The output on the pin is active LOW by default. @@ -16626,6 +21156,7 @@ typedef struct { * 0b1..SSEL1 not asserted. */ #define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK) + #define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U) #define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U) /*! TXSSEL2_N - Transmit slave select. This field asserts SSEL2 in master mode. The output on the pin is active LOW by default. @@ -16633,6 +21164,7 @@ typedef struct { * 0b1..SSEL2 not asserted. */ #define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK) + #define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U) #define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U) /*! TXSSEL3_N - Transmit slave select. This field asserts SSEL3 in master mode. The output on the pin is active LOW by default. @@ -16640,6 +21172,7 @@ typedef struct { * 0b1..SSEL3 not asserted. */ #define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK) + #define SPI_FIFOWR_EOT_MASK (0x100000U) #define SPI_FIFOWR_EOT_SHIFT (20U) /*! EOT - End of transfer. The asserted SSEL will be deasserted at the end of a transfer and remain @@ -16648,6 +21181,7 @@ typedef struct { * 0b1..SSEL deasserted. This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. */ #define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK) + #define SPI_FIFOWR_EOF_MASK (0x200000U) #define SPI_FIFOWR_EOF_SHIFT (21U) /*! EOF - End of frame. Between frames, a delay may be inserted, as defined by the Frame_delay value @@ -16659,6 +21193,7 @@ typedef struct { * inserted before subsequent data is transmitted. */ #define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK) + #define SPI_FIFOWR_RXIGNORE_MASK (0x400000U) #define SPI_FIFOWR_RXIGNORE_SHIFT (22U) /*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to @@ -16671,68 +21206,147 @@ typedef struct { * data. No receiver flags are generated. */ #define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK) + #define SPI_FIFOWR_LEN_MASK (0xF000000U) #define SPI_FIFOWR_LEN_SHIFT (24U) +/*! LEN - Data Length. Specifies the data length from 4 to 16 bits. Note that transfer lengths + * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0-2 = Reserved. + * 0x3 = Data transfer is 4 bits in length. 0x4 = Data transfer is 5 bits in length. 0xF = Data + * transfer is 16 bits in length. + */ #define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK) /*! @} */ /*! @name FIFORD - FIFO read data. */ /*! @{ */ + #define SPI_FIFORD_RXDATA_MASK (0xFFFFU) #define SPI_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ #define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK) + #define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U) #define SPI_FIFORD_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved + * along with received data. The value will reflect the SSEL0 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ #define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK) + #define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U) #define SPI_FIFORD_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved + * along with received data. The value will reflect the SSEL1 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ #define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK) + #define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U) #define SPI_FIFORD_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved + * along with received data. The value will reflect the SSEL2 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ #define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK) + #define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U) #define SPI_FIFORD_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved + * along with received data. The value will reflect the SSEL3 pin for both master and slave + * operation. A zero indicates that a slave select is active. The actual polarity of each slave select + * pin is configured by the related SPOL bit in CFG. + */ #define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK) + #define SPI_FIFORD_SOT_MASK (0x100000U) #define SPI_FIFORD_SOT_SHIFT (20U) +/*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went + * from deasserted to asserted (i.e., any previous transfer has ended). This information can be + * used to identify the first piece of data in cases where the transfer length is greater than 16 + * bits. + */ #define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK) /*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ /*! @{ */ + #define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU) #define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. + */ #define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK) + #define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U) #define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U) +/*! RXSSEL0_N - Slave Select for receive. + */ #define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK) + #define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U) #define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U) +/*! RXSSEL1_N - Slave Select for receive. + */ #define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK) + #define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U) #define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U) +/*! RXSSEL2_N - Slave Select for receive. + */ #define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK) + #define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U) #define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U) +/*! RXSSEL3_N - Slave Select for receive. + */ #define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK) + #define SPI_FIFORDNOPOP_SOT_MASK (0x100000U) #define SPI_FIFORDNOPOP_SOT_SHIFT (20U) +/*! SOT - Start of transfer flag. + */ #define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK) /*! @} */ +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define SPI_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define SPI_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define SPI_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSIZE_FIFOSIZE_SHIFT)) & SPI_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + /*! @name ID - Peripheral identification register. */ /*! @{ */ + #define SPI_ID_APERTURE_MASK (0xFFU) #define SPI_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ #define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK) + #define SPI_ID_MINOR_REV_MASK (0xF00U) #define SPI_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ #define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK) + #define SPI_ID_MAJOR_REV_MASK (0xF000U) #define SPI_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ #define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK) + #define SPI_ID_ID_MASK (0xFFFF0000U) #define SPI_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ #define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK) /*! @} */ @@ -16743,7 +21357,7 @@ typedef struct { /* SPI - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral SPI0 base address */ #define SPI0_BASE (0x50086000u) /** Peripheral SPI0 base address */ @@ -16891,7 +21505,7 @@ typedef struct { uint8_t RESERVED_1[36]; __IO uint32_t CPU0STCKCAL; /**< System tick calibration for secure part of CPU0, offset: 0x38 */ __IO uint32_t CPU0NSTCKCAL; /**< System tick calibration for non-secure part of CPU0, offset: 0x3C */ - __IO uint32_t CPU1TCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ + __IO uint32_t CPU1STCKCAL; /**< System tick calibration for CPU1, offset: 0x40 */ uint8_t RESERVED_2[4]; __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */ uint8_t RESERVED_3[180]; @@ -16906,7 +21520,7 @@ typedef struct { uint8_t RESERVED_4[20]; __IO uint32_t PRESETCTRLSET[3]; /**< Peripheral reset control set register, array offset: 0x120, array step: 0x4 */ uint8_t RESERVED_5[20]; - __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset contro clearl register, array offset: 0x140, array step: 0x4 */ + __IO uint32_t PRESETCTRLCLR[3]; /**< Peripheral reset control clear register, array offset: 0x140, array step: 0x4 */ uint8_t RESERVED_6[20]; __O uint32_t SWR_RESET; /**< generate a software_reset, offset: 0x160 */ uint8_t RESERVED_7[156]; @@ -16950,7 +21564,7 @@ typedef struct { uint8_t RESERVED_12[12]; __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */ __IO uint32_t USB0CLKSEL; /**< FS USB clock source select, offset: 0x2A8 */ - __IO uint32_t USB1CLKSEL; /**< HS USB clock source select - NOT USED, offset: 0x2AC */ + uint8_t RESERVED_13[4]; union { /* offset: 0x2B0 */ struct { /* offset: 0x2B0 */ __IO uint32_t FCCLKSEL0; /**< Flexcomm Interface 0 clock source select for Fractional Rate Divider, offset: 0x2B0 */ @@ -16965,17 +21579,17 @@ typedef struct { __IO uint32_t FCCLKSELX[8]; /**< Peripheral reset control register, array offset: 0x2B0, array step: 0x4 */ }; __IO uint32_t HSLSPICLKSEL; /**< HS LSPI clock source select, offset: 0x2D0 */ - uint8_t RESERVED_13[12]; - __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ uint8_t RESERVED_14[12]; + __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */ + uint8_t RESERVED_15[12]; __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */ - uint8_t RESERVED_15[4]; - __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ uint8_t RESERVED_16[4]; + __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */ + uint8_t RESERVED_17[4]; __IO uint32_t SYSTICKCLKDIV0; /**< System Tick Timer divider for CPU0, offset: 0x300 */ __IO uint32_t SYSTICKCLKDIV1; /**< System Tick Timer divider for CPU1, offset: 0x304 */ __IO uint32_t TRACECLKDIV; /**< TRACE clock divider, offset: 0x308 */ - uint8_t RESERVED_17[20]; + uint8_t RESERVED_18[20]; union { /* offset: 0x320 */ struct { /* offset: 0x320 */ __IO uint32_t FLEXFRG0CTRL; /**< Fractional rate divider for flexcomm 0, offset: 0x320 */ @@ -16989,36 +21603,34 @@ typedef struct { } FLEXFRGCTRL; __IO uint32_t FLEXFRGXCTRL[8]; /**< Peripheral reset control register, array offset: 0x320, array step: 0x4 */ }; - uint8_t RESERVED_18[64]; + uint8_t RESERVED_19[64]; __IO uint32_t AHBCLKDIV; /**< System clock divider, offset: 0x380 */ __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */ __IO uint32_t FROHFDIV; /**< FRO_HF (96MHz) clock divider, offset: 0x388 */ __IO uint32_t WDTCLKDIV; /**< WDT clock divider, offset: 0x38C */ - uint8_t RESERVED_19[4]; + uint8_t RESERVED_20[4]; __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */ __IO uint32_t USB0CLKDIV; /**< USB0 Clock divider, offset: 0x398 */ - uint8_t RESERVED_20[16]; + uint8_t RESERVED_21[16]; __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */ - uint8_t RESERVED_21[4]; - __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ uint8_t RESERVED_22[4]; - __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ + __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */ uint8_t RESERVED_23[4]; + __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */ + uint8_t RESERVED_24[4]; __IO uint32_t PLL0CLKDIV; /**< PLL0 clock divider, offset: 0x3C4 */ - uint8_t RESERVED_24[52]; + uint8_t RESERVED_25[52]; __IO uint32_t CLOCKGENUPDATELOCKOUT; /**< Control clock configuration registers access (like xxxDIV, xxxSEL), offset: 0x3FC */ - __IO uint32_t FMCCR; /**< FMC configuration register - INTERNAL USE ONLY, offset: 0x400 */ - uint8_t RESERVED_25[8]; - __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */ - __I uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */ + __IO uint32_t FMCCR; /**< FMC configuration register, offset: 0x400 */ uint8_t RESERVED_26[8]; + __IO uint32_t USB0NEEDCLKCTRL; /**< USB0 need clock control, offset: 0x40C */ + __I uint32_t USB0NEEDCLKSTAT; /**< USB0 need clock status, offset: 0x410 */ + uint8_t RESERVED_27[8]; __O uint32_t FMCFLUSH; /**< FMCflush control, offset: 0x41C */ __IO uint32_t MCLKIO; /**< MCLK control, offset: 0x420 */ - __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */ - __I uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */ - uint8_t RESERVED_27[36]; - __IO uint32_t FLASHBANKENABLE; /**< Flash Banks control, offset: 0x450 */ - uint8_t RESERVED_28[12]; + __IO uint32_t USB1NEEDCLKCTRL; /**< USB1 need clock control, offset: 0x424 */ + __I uint32_t USB1NEEDCLKSTAT; /**< USB1 need clock status, offset: 0x428 */ + uint8_t RESERVED_28[52]; __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */ uint8_t RESERVED_29[252]; __IO uint32_t PLL1CTRL; /**< PLL1 550m control, offset: 0x560 */ @@ -17033,53 +21645,31 @@ typedef struct { __IO uint32_t PLL0PDEC; /**< PLL0 550m P divider, offset: 0x58C */ __IO uint32_t PLL0SSCG0; /**< PLL0 Spread Spectrum Wrapper control register 0, offset: 0x590 */ __IO uint32_t PLL0SSCG1; /**< PLL0 Spread Spectrum Wrapper control register 1, offset: 0x594 */ - uint8_t RESERVED_31[52]; - __IO uint32_t EFUSECLKCTRL; /**< eFUSE controller clock enable, offset: 0x5CC */ - uint8_t RESERVED_32[176]; - __IO uint32_t STARTER[2]; /**< Start logic wake-up enable register, array offset: 0x680, array step: 0x4 */ - uint8_t RESERVED_33[24]; - __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */ - uint8_t RESERVED_34[24]; - __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER, array offset: 0x6C0, array step: 0x4 */ - uint8_t RESERVED_35[184]; - __IO uint32_t HARDWARESLEEP; /**< Hardware Sleep control, offset: 0x780 */ - uint8_t RESERVED_36[124]; + uint8_t RESERVED_31[364]; + __IO uint32_t FUNCRETENTIONCTRL; /**< Functional retention control register, offset: 0x704 */ + uint8_t RESERVED_32[248]; __IO uint32_t CPUCTRL; /**< CPU Control for multiple processors, offset: 0x800 */ __IO uint32_t CPBOOT; /**< Coprocessor Boot Address, offset: 0x804 */ - __IO uint32_t CPSTACK; /**< Coprocessor Stack Address, offset: 0x808 */ + uint8_t RESERVED_33[4]; __I uint32_t CPSTAT; /**< CPU Status, offset: 0x80C */ - uint8_t RESERVED_37[240]; - __IO uint32_t DICE_REG0; /**< Composite Device Identifier, offset: 0x900 */ - __IO uint32_t DICE_REG1; /**< Composite Device Identifier, offset: 0x904 */ - __IO uint32_t DICE_REG2; /**< Composite Device Identifier, offset: 0x908 */ - __IO uint32_t DICE_REG3; /**< Composite Device Identifier, offset: 0x90C */ - __IO uint32_t DICE_REG4; /**< Composite Device Identifier, offset: 0x910 */ - __IO uint32_t DICE_REG5; /**< Composite Device Identifier, offset: 0x914 */ - __IO uint32_t DICE_REG6; /**< Composite Device Identifier, offset: 0x918 */ - __IO uint32_t DICE_REG7; /**< Composite Device Identifier, offset: 0x91C */ - uint8_t RESERVED_38[248]; + uint8_t RESERVED_34[520]; __IO uint32_t CLOCK_CTRL; /**< Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures, offset: 0xA18 */ - uint8_t RESERVED_39[244]; + uint8_t RESERVED_35[244]; __IO uint32_t COMP_INT_CTRL; /**< Comparator Interrupt control, offset: 0xB10 */ __I uint32_t COMP_INT_STATUS; /**< Comparator Interrupt status, offset: 0xB14 */ - uint8_t RESERVED_40[748]; + uint8_t RESERVED_36[748]; __IO uint32_t AUTOCLKGATEOVERRIDE; /**< Control automatic clock gating, offset: 0xE04 */ __IO uint32_t GPIOPSYNC; /**< Enable bypass of the first stage of synchonization inside GPIO_INT module, offset: 0xE08 */ - uint8_t RESERVED_41[404]; - __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers -- FOR INTERNAl USE ONLY, offset: 0xFA0 */ - __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY, offset: 0xFA4 */ - __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY, offset: 0xFA8 */ - uint8_t RESERVED_42[4]; - __O uint32_t CODESECURITYPROTTEST; /**< Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY, offset: 0xFB0 */ - __O uint32_t CODESECURITYPROTCPU0; /**< Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB4 */ - __O uint32_t CODESECURITYPROTCPU1; /**< Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY, offset: 0xFB8 */ - __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY, offset: 0xFBC */ - __IO uint32_t DEBUG_AUTH_SCRATCH; /**< Debug authentication scratch registers -- FOR INTERNAL USE ONLY, offset: 0xFC0 */ - uint8_t RESERVED_43[16]; + uint8_t RESERVED_37[404]; + __IO uint32_t DEBUG_LOCK_EN; /**< Control write access to security registers., offset: 0xFA0 */ + __IO uint32_t DEBUG_FEATURES; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control., offset: 0xFA4 */ + __IO uint32_t DEBUG_FEATURES_DP; /**< Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register., offset: 0xFA8 */ + uint8_t RESERVED_38[16]; + __O uint32_t KEY_BLOCK; /**< block quiddikey/PUF all index., offset: 0xFBC */ + __IO uint32_t DEBUG_AUTH_BEACON; /**< Debug authentication BEACON register, offset: 0xFC0 */ + uint8_t RESERVED_39[16]; __IO uint32_t CPUCFG; /**< CPUs configuration register, offset: 0xFD4 */ - uint8_t RESERVED_44[20]; - __IO uint32_t PERIPHENCFG; /**< peripheral enable configuration -- FOR INTERNAL USE ONLY, offset: 0xFEC */ - uint8_t RESERVED_45[8]; + uint8_t RESERVED_40[32]; __I uint32_t DEVICE_ID0; /**< Device ID, offset: 0xFF8 */ __I uint32_t DIEID; /**< Chip revision ID and Number, offset: 0xFFC */ } SYSCON_Type; @@ -17095,6 +21685,7 @@ typedef struct { /*! @name MEMORYREMAP - Memory Remap control register */ /*! @{ */ + #define SYSCON_MEMORYREMAP_MAP_MASK (0x3U) #define SYSCON_MEMORYREMAP_MAP_SHIFT (0U) /*! MAP - Select the location of the vector table :. @@ -17108,104 +21699,176 @@ typedef struct { /*! @name AHBMATPRIO - AHB Matrix priority control register Priority values are 3 = highest, 0 = lowest */ /*! @{ */ -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK (0x3U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT (0U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_CBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK (0xCU) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT (2U) -#define SYSCON_AHBMATPRIO_PRI_TEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_TEAL_SBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK (0x30U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT (4U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_CBUS_MASK) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK (0xC0U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT (6U) -#define SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_UTEAL_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK (0x3U) +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT (0U) +/*! PRI_CPU0_CBUS - CPU0 C-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK (0xCU) +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT (2U) +/*! PRI_CPU0_SBUS - CPU0 S-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU0_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU0_SBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK (0x30U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT (4U) +/*! PRI_CPU1_CBUS - CPU1 C-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU1_CBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_CBUS_MASK) + +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK (0xC0U) +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT (6U) +/*! PRI_CPU1_SBUS - CPU1 S-AHB bus. + */ +#define SYSCON_AHBMATPRIO_PRI_CPU1_SBUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_CPU1_SBUS_MASK) + #define SYSCON_AHBMATPRIO_PRI_USB_FS_MASK (0x300U) #define SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT (8U) +/*! PRI_USB_FS - USB-FS.(USB0) + */ #define SYSCON_AHBMATPRIO_PRI_USB_FS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_FS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_FS_MASK) + #define SYSCON_AHBMATPRIO_PRI_SDMA0_MASK (0xC00U) #define SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT (10U) +/*! PRI_SDMA0 - DMA0 controller priority. + */ #define SYSCON_AHBMATPRIO_PRI_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA0_MASK) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK (0x3000U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT (12U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_D_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_D_MASK) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK (0xC000U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT (14U) -#define SYSCON_AHBMATPRIO_PRI_EZH_B_I(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_EZH_B_I_SHIFT)) & SYSCON_AHBMATPRIO_PRI_EZH_B_I_MASK) + #define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0x30000U) #define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (16U) +/*! PRI_SDIO - SDIO. + */ #define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK) + #define SYSCON_AHBMATPRIO_PRI_PQ_MASK (0xC0000U) #define SYSCON_AHBMATPRIO_PRI_PQ_SHIFT (18U) +/*! PRI_PQ - PQ (HW Accelerator). + */ #define SYSCON_AHBMATPRIO_PRI_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_PQ_SHIFT)) & SYSCON_AHBMATPRIO_PRI_PQ_MASK) -#define SYSCON_AHBMATPRIO_PRI_SHA2_MASK (0x300000U) -#define SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT (20U) -#define SYSCON_AHBMATPRIO_PRI_SHA2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA2_MASK) + +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK (0x300000U) +#define SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT (20U) +/*! PRI_HASH_AES - HASH_AES. + */ +#define SYSCON_AHBMATPRIO_PRI_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_HASH_AES_SHIFT)) & SYSCON_AHBMATPRIO_PRI_HASH_AES_MASK) + #define SYSCON_AHBMATPRIO_PRI_USB_HS_MASK (0xC00000U) #define SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT (22U) +/*! PRI_USB_HS - USB-HS.(USB1) + */ #define SYSCON_AHBMATPRIO_PRI_USB_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB_HS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB_HS_MASK) + #define SYSCON_AHBMATPRIO_PRI_SDMA1_MASK (0x3000000U) #define SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT (24U) +/*! PRI_SDMA1 - DMA1 controller priority. + */ #define SYSCON_AHBMATPRIO_PRI_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDMA1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDMA1_MASK) /*! @} */ /*! @name CPU0STCKCAL - System tick calibration for secure part of CPU0 */ /*! @{ */ -#define SYSCON_CPU0STCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU0STCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU0STCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_CAL_SHIFT)) & SYSCON_CPU0STCKCAL_CAL_MASK) + +#define SYSCON_CPU0STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_TENMS_SHIFT)) & SYSCON_CPU0STCKCAL_TENMS_MASK) + #define SYSCON_CPU0STCKCAL_SKEW_MASK (0x1000000U) #define SYSCON_CPU0STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Initial value for the Systick timer. + */ #define SYSCON_CPU0STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_SKEW_SHIFT)) & SYSCON_CPU0STCKCAL_SKEW_MASK) + #define SYSCON_CPU0STCKCAL_NOREF_MASK (0x2000000U) #define SYSCON_CPU0STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference + * clock provided; 1 = no reference clock provided. + */ #define SYSCON_CPU0STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0STCKCAL_NOREF_SHIFT)) & SYSCON_CPU0STCKCAL_NOREF_MASK) /*! @} */ /*! @name CPU0NSTCKCAL - System tick calibration for non-secure part of CPU0 */ /*! @{ */ -#define SYSCON_CPU0NSTCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU0NSTCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU0NSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_CAL_SHIFT)) & SYSCON_CPU0NSTCKCAL_CAL_MASK) + +#define SYSCON_CPU0NSTCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU0NSTCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the + * value reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU0NSTCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_TENMS_SHIFT)) & SYSCON_CPU0NSTCKCAL_TENMS_MASK) + #define SYSCON_CPU0NSTCKCAL_SKEW_MASK (0x1000000U) #define SYSCON_CPU0NSTCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. + */ #define SYSCON_CPU0NSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_SKEW_SHIFT)) & SYSCON_CPU0NSTCKCAL_SKEW_MASK) + #define SYSCON_CPU0NSTCKCAL_NOREF_MASK (0x2000000U) #define SYSCON_CPU0NSTCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Initial value for the Systick timer. + */ #define SYSCON_CPU0NSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU0NSTCKCAL_NOREF_SHIFT)) & SYSCON_CPU0NSTCKCAL_NOREF_MASK) /*! @} */ -/*! @name CPU1TCKCAL - System tick calibration for CPU1 */ +/*! @name CPU1STCKCAL - System tick calibration for CPU1 */ /*! @{ */ -#define SYSCON_CPU1TCKCAL_CAL_MASK (0xFFFFFFU) -#define SYSCON_CPU1TCKCAL_CAL_SHIFT (0U) -#define SYSCON_CPU1TCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_CAL_SHIFT)) & SYSCON_CPU1TCKCAL_CAL_MASK) -#define SYSCON_CPU1TCKCAL_SKEW_MASK (0x1000000U) -#define SYSCON_CPU1TCKCAL_SKEW_SHIFT (24U) -#define SYSCON_CPU1TCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_SKEW_SHIFT)) & SYSCON_CPU1TCKCAL_SKEW_MASK) -#define SYSCON_CPU1TCKCAL_NOREF_MASK (0x2000000U) -#define SYSCON_CPU1TCKCAL_NOREF_SHIFT (25U) -#define SYSCON_CPU1TCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1TCKCAL_NOREF_SHIFT)) & SYSCON_CPU1TCKCAL_NOREF_MASK) + +#define SYSCON_CPU1STCKCAL_TENMS_MASK (0xFFFFFFU) +#define SYSCON_CPU1STCKCAL_TENMS_SHIFT (0U) +/*! TENMS - Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value + * reads as zero, the calibration value is not known. + */ +#define SYSCON_CPU1STCKCAL_TENMS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_TENMS_SHIFT)) & SYSCON_CPU1STCKCAL_TENMS_MASK) + +#define SYSCON_CPU1STCKCAL_SKEW_MASK (0x1000000U) +#define SYSCON_CPU1STCKCAL_SKEW_SHIFT (24U) +/*! SKEW - Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. + */ +#define SYSCON_CPU1STCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_SKEW_SHIFT)) & SYSCON_CPU1STCKCAL_SKEW_MASK) + +#define SYSCON_CPU1STCKCAL_NOREF_MASK (0x2000000U) +#define SYSCON_CPU1STCKCAL_NOREF_SHIFT (25U) +/*! NOREF - Indicates whether the device provides a reference clock to the processor: 0 = reference + * clock provided; 1 = no reference clock provided. + */ +#define SYSCON_CPU1STCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPU1STCKCAL_NOREF_SHIFT)) & SYSCON_CPU1STCKCAL_NOREF_MASK) /*! @} */ /*! @name NMISRC - NMI Source Select */ /*! @{ */ + #define SYSCON_NMISRC_IRQCPU0_MASK (0x3FU) #define SYSCON_NMISRC_IRQCPU0_SHIFT (0U) +/*! IRQCPU0 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU0, if enabled by NMIENCPU0. + */ #define SYSCON_NMISRC_IRQCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU0_SHIFT)) & SYSCON_NMISRC_IRQCPU0_MASK) + #define SYSCON_NMISRC_IRQCPU1_MASK (0x3F00U) #define SYSCON_NMISRC_IRQCPU1_SHIFT (8U) +/*! IRQCPU1 - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) for the CPU1, if enabled by NMIENCPU1. + */ #define SYSCON_NMISRC_IRQCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQCPU1_SHIFT)) & SYSCON_NMISRC_IRQCPU1_MASK) + #define SYSCON_NMISRC_NMIENCPU1_MASK (0x40000000U) #define SYSCON_NMISRC_NMIENCPU1_SHIFT (30U) +/*! NMIENCPU1 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU1. + */ #define SYSCON_NMISRC_NMIENCPU1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU1_SHIFT)) & SYSCON_NMISRC_NMIENCPU1_MASK) + #define SYSCON_NMISRC_NMIENCPU0_MASK (0x80000000U) #define SYSCON_NMISRC_NMIENCPU0_SHIFT (31U) +/*! NMIENCPU0 - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by IRQCPU0. + */ #define SYSCON_NMISRC_NMIENCPU0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENCPU0_SHIFT)) & SYSCON_NMISRC_NMIENCPU0_MASK) /*! @} */ /*! @name PRESETCTRL0 - Peripheral reset control 0 */ /*! @{ */ + #define SYSCON_PRESETCTRL0_ROM_RST_MASK (0x2U) #define SYSCON_PRESETCTRL0_ROM_RST_SHIFT (1U) /*! ROM_RST - ROM reset control. @@ -17213,6 +21876,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_ROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ROM_RST_SHIFT)) & SYSCON_PRESETCTRL0_ROM_RST_MASK) + #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK (0x8U) #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT (3U) /*! SRAM_CTRL1_RST - SRAM Controller 1 reset control. @@ -17220,6 +21884,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_SRAM_CTRL1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL1_RST_MASK) + #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK (0x10U) #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT (4U) /*! SRAM_CTRL2_RST - SRAM Controller 2 reset control. @@ -17227,6 +21892,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_SRAM_CTRL2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL2_RST_MASK) + #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK (0x20U) #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT (5U) /*! SRAM_CTRL3_RST - SRAM Controller 3 reset control. @@ -17234,6 +21900,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_SRAM_CTRL3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL3_RST_MASK) + #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK (0x40U) #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT (6U) /*! SRAM_CTRL4_RST - SRAM Controller 4 reset control. @@ -17241,6 +21908,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_SRAM_CTRL4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_SHIFT)) & SYSCON_PRESETCTRL0_SRAM_CTRL4_RST_MASK) + #define SYSCON_PRESETCTRL0_FLASH_RST_MASK (0x80U) #define SYSCON_PRESETCTRL0_FLASH_RST_SHIFT (7U) /*! FLASH_RST - Flash controller reset control. @@ -17248,6 +21916,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_MASK) + #define SYSCON_PRESETCTRL0_FMC_RST_MASK (0x100U) #define SYSCON_PRESETCTRL0_FMC_RST_SHIFT (8U) /*! FMC_RST - FMC controller reset control. @@ -17255,13 +21924,15 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL0_FMC_RST_MASK) -#define SYSCON_PRESETCTRL0_MUX0_RST_MASK (0x800U) -#define SYSCON_PRESETCTRL0_MUX0_RST_SHIFT (11U) -/*! MUX0_RST - Input Mux 0 reset control. + +#define SYSCON_PRESETCTRL0_MUX_RST_MASK (0x800U) +#define SYSCON_PRESETCTRL0_MUX_RST_SHIFT (11U) +/*! MUX_RST - Input Mux reset control. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL0_MUX0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX0_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX0_RST_MASK) +#define SYSCON_PRESETCTRL0_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MUX_RST_MASK) + #define SYSCON_PRESETCTRL0_IOCON_RST_MASK (0x2000U) #define SYSCON_PRESETCTRL0_IOCON_RST_SHIFT (13U) /*! IOCON_RST - I/O controller reset control. @@ -17269,6 +21940,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_MASK) + #define SYSCON_PRESETCTRL0_GPIO0_RST_MASK (0x4000U) #define SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT (14U) /*! GPIO0_RST - GPIO0 reset control. @@ -17276,6 +21948,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_MASK) + #define SYSCON_PRESETCTRL0_GPIO1_RST_MASK (0x8000U) #define SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT (15U) /*! GPIO1_RST - GPIO1 reset control. @@ -17283,6 +21956,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO1_RST_MASK) + #define SYSCON_PRESETCTRL0_GPIO2_RST_MASK (0x10000U) #define SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT (16U) /*! GPIO2_RST - GPIO2 reset control. @@ -17290,6 +21964,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO2_RST_MASK) + #define SYSCON_PRESETCTRL0_GPIO3_RST_MASK (0x20000U) #define SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT (17U) /*! GPIO3_RST - GPIO3 reset control. @@ -17297,6 +21972,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL0_GPIO3_RST_MASK) + #define SYSCON_PRESETCTRL0_PINT_RST_MASK (0x40000U) #define SYSCON_PRESETCTRL0_PINT_RST_SHIFT (18U) /*! PINT_RST - Pin interrupt (PINT) reset control. @@ -17304,6 +21980,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_PINT_RST_MASK) + #define SYSCON_PRESETCTRL0_GINT_RST_MASK (0x80000U) #define SYSCON_PRESETCTRL0_GINT_RST_SHIFT (19U) /*! GINT_RST - Group interrupt (GINT) reset control. @@ -17311,6 +21988,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL0_GINT_RST_MASK) + #define SYSCON_PRESETCTRL0_DMA0_RST_MASK (0x100000U) #define SYSCON_PRESETCTRL0_DMA0_RST_SHIFT (20U) /*! DMA0_RST - DMA0 reset control. @@ -17318,6 +21996,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL0_DMA0_RST_MASK) + #define SYSCON_PRESETCTRL0_CRCGEN_RST_MASK (0x200000U) #define SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT (21U) /*! CRCGEN_RST - CRCGEN reset control. @@ -17325,6 +22004,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_CRCGEN_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRCGEN_RST_SHIFT)) & SYSCON_PRESETCTRL0_CRCGEN_RST_MASK) + #define SYSCON_PRESETCTRL0_WWDT_RST_MASK (0x400000U) #define SYSCON_PRESETCTRL0_WWDT_RST_SHIFT (22U) /*! WWDT_RST - Watchdog Timer reset control. @@ -17332,6 +22012,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL0_WWDT_RST_MASK) + #define SYSCON_PRESETCTRL0_RTC_RST_MASK (0x800000U) #define SYSCON_PRESETCTRL0_RTC_RST_SHIFT (23U) /*! RTC_RST - Real Time Clock (RTC) reset control. @@ -17339,6 +22020,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_RTC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_RTC_RST_SHIFT)) & SYSCON_PRESETCTRL0_RTC_RST_MASK) + #define SYSCON_PRESETCTRL0_MAILBOX_RST_MASK (0x4000000U) #define SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT (26U) /*! MAILBOX_RST - Inter CPU communication Mailbox reset control. @@ -17346,6 +22028,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL0_MAILBOX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MAILBOX_RST_SHIFT)) & SYSCON_PRESETCTRL0_MAILBOX_RST_MASK) + #define SYSCON_PRESETCTRL0_ADC_RST_MASK (0x8000000U) #define SYSCON_PRESETCTRL0_ADC_RST_SHIFT (27U) /*! ADC_RST - ADC reset control. @@ -17357,6 +22040,7 @@ typedef struct { /*! @name PRESETCTRL1 - Peripheral reset control 1 */ /*! @{ */ + #define SYSCON_PRESETCTRL1_MRT_RST_MASK (0x1U) #define SYSCON_PRESETCTRL1_MRT_RST_SHIFT (0U) /*! MRT_RST - MRT reset control. @@ -17364,20 +22048,23 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL1_MRT_RST_MASK) -#define SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK (0x2U) -#define SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT (1U) -/*! OSTIMER0_RST - OS Timer 0 reset control. + +#define SYSCON_PRESETCTRL1_OSTIMER_RST_MASK (0x2U) +#define SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT (1U) +/*! OSTIMER_RST - OS Event Timer reset control. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL1_OSTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER0_RST_MASK) -#define SYSCON_PRESETCTRL1_SCT0_RST_MASK (0x4U) -#define SYSCON_PRESETCTRL1_SCT0_RST_SHIFT (2U) -/*! SCT0_RST - SCT0 reset control. +#define SYSCON_PRESETCTRL1_OSTIMER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_OSTIMER_RST_SHIFT)) & SYSCON_PRESETCTRL1_OSTIMER_RST_MASK) + +#define SYSCON_PRESETCTRL1_SCT_RST_MASK (0x4U) +#define SYSCON_PRESETCTRL1_SCT_RST_SHIFT (2U) +/*! SCT_RST - SCT reset control. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL1_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT0_RST_MASK) +#define SYSCON_PRESETCTRL1_SCT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCT_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCT_RST_MASK) + #define SYSCON_PRESETCTRL1_SCTIPU_RST_MASK (0x40U) #define SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT (6U) /*! SCTIPU_RST - SCTIPU reset control. @@ -17385,13 +22072,15 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_SCTIPU_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_SCTIPU_RST_SHIFT)) & SYSCON_PRESETCTRL1_SCTIPU_RST_MASK) -#define SYSCON_PRESETCTRL1_UTICK0_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT (10U) -/*! UTICK0_RST - UTICK0 reset control. + +#define SYSCON_PRESETCTRL1_UTICK_RST_MASK (0x400U) +#define SYSCON_PRESETCTRL1_UTICK_RST_SHIFT (10U) +/*! UTICK_RST - UTICK reset control. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL1_UTICK0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK0_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK0_RST_MASK) +#define SYSCON_PRESETCTRL1_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL1_UTICK_RST_MASK) + #define SYSCON_PRESETCTRL1_FC0_RST_MASK (0x800U) #define SYSCON_PRESETCTRL1_FC0_RST_SHIFT (11U) /*! FC0_RST - FC0 reset control. @@ -17399,6 +22088,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC0_RST_MASK) + #define SYSCON_PRESETCTRL1_FC1_RST_MASK (0x1000U) #define SYSCON_PRESETCTRL1_FC1_RST_SHIFT (12U) /*! FC1_RST - FC1 reset control. @@ -17406,6 +22096,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC1_RST_MASK) + #define SYSCON_PRESETCTRL1_FC2_RST_MASK (0x2000U) #define SYSCON_PRESETCTRL1_FC2_RST_SHIFT (13U) /*! FC2_RST - FC2 reset control. @@ -17413,6 +22104,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC2_RST_MASK) + #define SYSCON_PRESETCTRL1_FC3_RST_MASK (0x4000U) #define SYSCON_PRESETCTRL1_FC3_RST_SHIFT (14U) /*! FC3_RST - FC3 reset control. @@ -17420,6 +22112,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC3_RST_MASK) + #define SYSCON_PRESETCTRL1_FC4_RST_MASK (0x8000U) #define SYSCON_PRESETCTRL1_FC4_RST_SHIFT (15U) /*! FC4_RST - FC4 reset control. @@ -17427,6 +22120,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC4_RST_MASK) + #define SYSCON_PRESETCTRL1_FC5_RST_MASK (0x10000U) #define SYSCON_PRESETCTRL1_FC5_RST_SHIFT (16U) /*! FC5_RST - FC5 reset control. @@ -17434,6 +22128,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC5_RST_MASK) + #define SYSCON_PRESETCTRL1_FC6_RST_MASK (0x20000U) #define SYSCON_PRESETCTRL1_FC6_RST_SHIFT (17U) /*! FC6_RST - FC6 reset control. @@ -17441,6 +22136,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC6_RST_MASK) + #define SYSCON_PRESETCTRL1_FC7_RST_MASK (0x40000U) #define SYSCON_PRESETCTRL1_FC7_RST_SHIFT (18U) /*! FC7_RST - FC7 reset control. @@ -17448,6 +22144,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL1_FC7_RST_MASK) + #define SYSCON_PRESETCTRL1_TIMER2_RST_MASK (0x400000U) #define SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT (22U) /*! TIMER2_RST - Timer 2 reset control. @@ -17455,6 +22152,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_TIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER2_RST_MASK) + #define SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK (0x2000000U) #define SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT (25U) /*! USB0_DEV_RST - USB0 DEV reset control. @@ -17462,6 +22160,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_USB0_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_USB0_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL1_USB0_DEV_RST_MASK) + #define SYSCON_PRESETCTRL1_TIMER0_RST_MASK (0x4000000U) #define SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT (26U) /*! TIMER0_RST - Timer 0 reset control. @@ -17469,6 +22168,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_TIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER0_RST_MASK) + #define SYSCON_PRESETCTRL1_TIMER1_RST_MASK (0x8000000U) #define SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT (27U) /*! TIMER1_RST - Timer 1 reset control. @@ -17476,31 +22176,11 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL1_TIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_TIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL1_TIMER1_RST_MASK) -#define SYSCON_PRESETCTRL1_PVT_RST_MASK (0x10000000U) -#define SYSCON_PRESETCTRL1_PVT_RST_SHIFT (28U) -/*! PVT_RST - PVT reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_PVT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_PVT_RST_SHIFT)) & SYSCON_PRESETCTRL1_PVT_RST_MASK) -#define SYSCON_PRESETCTRL1_EZHA_RST_MASK (0x40000000U) -#define SYSCON_PRESETCTRL1_EZHA_RST_SHIFT (30U) -/*! EZHA_RST - EZH a reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_EZHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHA_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHA_RST_MASK) -#define SYSCON_PRESETCTRL1_EZHB_RST_MASK (0x80000000U) -#define SYSCON_PRESETCTRL1_EZHB_RST_SHIFT (31U) -/*! EZHB_RST - EZH b reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL1_EZHB_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_EZHB_RST_SHIFT)) & SYSCON_PRESETCTRL1_EZHB_RST_MASK) /*! @} */ /*! @name PRESETCTRL2 - Peripheral reset control 2 */ /*! @{ */ + #define SYSCON_PRESETCTRL2_DMA1_RST_MASK (0x2U) #define SYSCON_PRESETCTRL2_DMA1_RST_SHIFT (1U) /*! DMA1_RST - DMA1 reset control. @@ -17508,6 +22188,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_DMA1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_DMA1_RST_SHIFT)) & SYSCON_PRESETCTRL2_DMA1_RST_MASK) + #define SYSCON_PRESETCTRL2_COMP_RST_MASK (0x4U) #define SYSCON_PRESETCTRL2_COMP_RST_SHIFT (2U) /*! COMP_RST - Comparator reset control. @@ -17515,6 +22196,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_COMP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_COMP_RST_SHIFT)) & SYSCON_PRESETCTRL2_COMP_RST_MASK) + #define SYSCON_PRESETCTRL2_SDIO_RST_MASK (0x8U) #define SYSCON_PRESETCTRL2_SDIO_RST_SHIFT (3U) /*! SDIO_RST - SDIO reset control. @@ -17522,6 +22204,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL2_SDIO_RST_MASK) + #define SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK (0x10U) #define SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT (4U) /*! USB1_HOST_RST - USB1 Host reset control. @@ -17529,6 +22212,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB1_HOST_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_HOST_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_HOST_RST_MASK) + #define SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK (0x20U) #define SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT (5U) /*! USB1_DEV_RST - USB1 dev reset control. @@ -17536,6 +22220,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB1_DEV_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_DEV_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_DEV_RST_MASK) + #define SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK (0x40U) #define SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT (6U) /*! USB1_RAM_RST - USB1 RAM reset control. @@ -17543,6 +22228,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB1_RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_RAM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_RAM_RST_MASK) + #define SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK (0x80U) #define SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT (7U) /*! USB1_PHY_RST - USB1 PHY reset control. @@ -17550,6 +22236,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB1_PHY_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB1_PHY_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB1_PHY_RST_MASK) + #define SYSCON_PRESETCTRL2_FREQME_RST_MASK (0x100U) #define SYSCON_PRESETCTRL2_FREQME_RST_SHIFT (8U) /*! FREQME_RST - Frequency meter reset control. @@ -17557,27 +22244,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_FREQME_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_FREQME_RST_SHIFT)) & SYSCON_PRESETCTRL2_FREQME_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO4_RST_MASK (0x200U) -#define SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT (9U) -/*! GPIO4_RST - GPIO4 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO4_RST_MASK) -#define SYSCON_PRESETCTRL2_GPIO5_RST_MASK (0x400U) -#define SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT (10U) -/*! GPIO5_RST - GPIO5 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO5_RST_MASK) -#define SYSCON_PRESETCTRL2_OTP_RST_MASK (0x1000U) -#define SYSCON_PRESETCTRL2_OTP_RST_SHIFT (12U) -/*! OTP_RST - OTP reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL2_OTP_RST_MASK) + #define SYSCON_PRESETCTRL2_RNG_RST_MASK (0x2000U) #define SYSCON_PRESETCTRL2_RNG_RST_SHIFT (13U) /*! RNG_RST - RNG reset control. @@ -17585,13 +22252,15 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL2_RNG_RST_MASK) -#define SYSCON_PRESETCTRL2_MUX1_RST_MASK (0x4000U) -#define SYSCON_PRESETCTRL2_MUX1_RST_SHIFT (14U) -/*! MUX1_RST - Peripheral Input Mux 1 reset control. + +#define SYSCON_PRESETCTRL2_SYSCTL_RST_MASK (0x8000U) +#define SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT (15U) +/*! SYSCTL_RST - SYSCTL Block reset. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL2_MUX1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_MUX1_RST_SHIFT)) & SYSCON_PRESETCTRL2_MUX1_RST_MASK) +#define SYSCON_PRESETCTRL2_SYSCTL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_SYSCTL_RST_SHIFT)) & SYSCON_PRESETCTRL2_SYSCTL_RST_MASK) + #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK (0x10000U) #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT (16U) /*! USB0_HOSTM_RST - USB0 Host Master reset control. @@ -17599,6 +22268,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB0_HOSTM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTM_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTM_RST_MASK) + #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK (0x20000U) #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT (17U) /*! USB0_HOSTS_RST - USB0 Host Slave reset control. @@ -17606,13 +22276,15 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_USB0_HOSTS_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_USB0_HOSTS_RST_SHIFT)) & SYSCON_PRESETCTRL2_USB0_HOSTS_RST_MASK) -#define SYSCON_PRESETCTRL2_HASH0_RST_MASK (0x40000U) -#define SYSCON_PRESETCTRL2_HASH0_RST_SHIFT (18U) -/*! HASH0_RST - HASH0 reset control. + +#define SYSCON_PRESETCTRL2_HASH_AES_RST_MASK (0x40000U) +#define SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT (18U) +/*! HASH_AES_RST - HASH_AES reset control. * 0b1..Bloc is reset. * 0b0..Bloc is not reset. */ -#define SYSCON_PRESETCTRL2_HASH0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH0_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH0_RST_MASK) +#define SYSCON_PRESETCTRL2_HASH_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HASH_AES_RST_SHIFT)) & SYSCON_PRESETCTRL2_HASH_AES_RST_MASK) + #define SYSCON_PRESETCTRL2_PQ_RST_MASK (0x80000U) #define SYSCON_PRESETCTRL2_PQ_RST_SHIFT (19U) /*! PQ_RST - Power Quad reset control. @@ -17620,6 +22292,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_PQ_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PQ_RST_SHIFT)) & SYSCON_PRESETCTRL2_PQ_RST_MASK) + #define SYSCON_PRESETCTRL2_PLULUT_RST_MASK (0x100000U) #define SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT (20U) /*! PLULUT_RST - PLU LUT reset control. @@ -17627,6 +22300,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_PLULUT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PLULUT_RST_SHIFT)) & SYSCON_PRESETCTRL2_PLULUT_RST_MASK) + #define SYSCON_PRESETCTRL2_TIMER3_RST_MASK (0x200000U) #define SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT (21U) /*! TIMER3_RST - Timer 3 reset control. @@ -17634,6 +22308,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_TIMER3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER3_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER3_RST_MASK) + #define SYSCON_PRESETCTRL2_TIMER4_RST_MASK (0x400000U) #define SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT (22U) /*! TIMER4_RST - Timer 4 reset control. @@ -17641,6 +22316,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_TIMER4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_TIMER4_RST_SHIFT)) & SYSCON_PRESETCTRL2_TIMER4_RST_MASK) + #define SYSCON_PRESETCTRL2_PUF_RST_MASK (0x800000U) #define SYSCON_PRESETCTRL2_PUF_RST_SHIFT (23U) /*! PUF_RST - PUF reset control reset control. @@ -17648,6 +22324,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_PUF_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_PUF_RST_SHIFT)) & SYSCON_PRESETCTRL2_PUF_RST_MASK) + #define SYSCON_PRESETCTRL2_CASPER_RST_MASK (0x1000000U) #define SYSCON_PRESETCTRL2_CASPER_RST_SHIFT (24U) /*! CASPER_RST - Casper reset control. @@ -17655,13 +22332,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_CASPER_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CASPER_RST_SHIFT)) & SYSCON_PRESETCTRL2_CASPER_RST_MASK) -#define SYSCON_PRESETCTRL2_CAPT0_RST_MASK (0x2000000U) -#define SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT (25U) -/*! CAPT0_RST - CAPT0 reset control. - * 0b1..Bloc is reset. - * 0b0..Bloc is not reset. - */ -#define SYSCON_PRESETCTRL2_CAPT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_CAPT0_RST_SHIFT)) & SYSCON_PRESETCTRL2_CAPT0_RST_MASK) + #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK (0x8000000U) #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT (27U) /*! ANALOG_CTRL_RST - analog control reset control. @@ -17669,6 +22340,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_ANALOG_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT)) & SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_MASK) + #define SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK (0x10000000U) #define SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT (28U) /*! HS_LSPI_RST - HS LSPI reset control. @@ -17676,6 +22348,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_HS_LSPI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_HS_LSPI_RST_SHIFT)) & SYSCON_PRESETCTRL2_HS_LSPI_RST_MASK) + #define SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK (0x20000000U) #define SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT (29U) /*! GPIO_SEC_RST - GPIO secure reset control. @@ -17683,6 +22356,7 @@ typedef struct { * 0b0..Bloc is not reset. */ #define SYSCON_PRESETCTRL2_GPIO_SEC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL2_GPIO_SEC_RST_SHIFT)) & SYSCON_PRESETCTRL2_GPIO_SEC_RST_MASK) + #define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_MASK (0x40000000U) #define SYSCON_PRESETCTRL2_GPIO_SEC_INT_RST_SHIFT (30U) /*! GPIO_SEC_INT_RST - GPIO secure int reset control. @@ -17694,8 +22368,11 @@ typedef struct { /*! @name PRESETCTRLX - Peripheral reset control register */ /*! @{ */ + #define SYSCON_PRESETCTRLX_DATA_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_PRESETCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLX_DATA_SHIFT)) & SYSCON_PRESETCTRLX_DATA_MASK) /*! @} */ @@ -17704,18 +22381,24 @@ typedef struct { /*! @name PRESETCTRLSET - Peripheral reset control set register */ /*! @{ */ + #define SYSCON_PRESETCTRLSET_DATA_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_PRESETCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_DATA_SHIFT)) & SYSCON_PRESETCTRLSET_DATA_MASK) /*! @} */ /* The count of SYSCON_PRESETCTRLSET */ #define SYSCON_PRESETCTRLSET_COUNT (3U) -/*! @name PRESETCTRLCLR - Peripheral reset contro clearl register */ +/*! @name PRESETCTRLCLR - Peripheral reset control clear register */ /*! @{ */ + #define SYSCON_PRESETCTRLCLR_DATA_MASK (0xFFFFFFFFU) #define SYSCON_PRESETCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_PRESETCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_DATA_SHIFT)) & SYSCON_PRESETCTRLCLR_DATA_MASK) /*! @} */ @@ -17724,6 +22407,7 @@ typedef struct { /*! @name SWR_RESET - generate a software_reset */ /*! @{ */ + #define SYSCON_SWR_RESET_SWR_RESET_MASK (0xFFFFFFFFU) #define SYSCON_SWR_RESET_SWR_RESET_SHIFT (0U) /*! SWR_RESET - Write 0x5A00_0001 to generate a software_reset. @@ -17735,6 +22419,7 @@ typedef struct { /*! @name AHBCLKCTRL0 - AHB Clock control 0 */ /*! @{ */ + #define SYSCON_AHBCLKCTRL0_ROM_MASK (0x2U) #define SYSCON_AHBCLKCTRL0_ROM_SHIFT (1U) /*! ROM - Enables the clock for the ROM. @@ -17742,6 +22427,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_ROM_SHIFT)) & SYSCON_AHBCLKCTRL0_ROM_MASK) + #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK (0x8U) #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT (3U) /*! SRAM_CTRL1 - Enables the clock for the SRAM Controller 1. @@ -17749,6 +22435,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_SRAM_CTRL1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL1_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK) + #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK (0x10U) #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT (4U) /*! SRAM_CTRL2 - Enables the clock for the SRAM Controller 2. @@ -17756,6 +22443,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_SRAM_CTRL2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL2_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK) + #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK (0x20U) #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT (5U) /*! SRAM_CTRL3 - Enables the clock for the SRAM Controller 3. @@ -17763,6 +22451,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_SRAM_CTRL3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL3_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK) + #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK (0x40U) #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT (6U) /*! SRAM_CTRL4 - Enables the clock for the SRAM Controller 4. @@ -17770,6 +22459,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_SRAM_CTRL4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_SRAM_CTRL4_SHIFT)) & SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK) + #define SYSCON_AHBCLKCTRL0_FLASH_MASK (0x80U) #define SYSCON_AHBCLKCTRL0_FLASH_SHIFT (7U) /*! FLASH - Enables the clock for the Flash controller. @@ -17777,6 +22467,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL0_FLASH_MASK) + #define SYSCON_AHBCLKCTRL0_FMC_MASK (0x100U) #define SYSCON_AHBCLKCTRL0_FMC_SHIFT (8U) /*! FMC - Enables the clock for the FMC controller. @@ -17784,13 +22475,15 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_FMC_SHIFT)) & SYSCON_AHBCLKCTRL0_FMC_MASK) -#define SYSCON_AHBCLKCTRL0_MUX0_MASK (0x800U) -#define SYSCON_AHBCLKCTRL0_MUX0_SHIFT (11U) -/*! MUX0 - Enables the clock for the Input Mux 0. + +#define SYSCON_AHBCLKCTRL0_MUX_MASK (0x800U) +#define SYSCON_AHBCLKCTRL0_MUX_SHIFT (11U) +/*! MUX - Enables the clock for the Input Mux. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL0_MUX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX0_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX0_MASK) +#define SYSCON_AHBCLKCTRL0_MUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MUX_SHIFT)) & SYSCON_AHBCLKCTRL0_MUX_MASK) + #define SYSCON_AHBCLKCTRL0_IOCON_MASK (0x2000U) #define SYSCON_AHBCLKCTRL0_IOCON_SHIFT (13U) /*! IOCON - Enables the clock for the I/O controller. @@ -17798,6 +22491,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL0_IOCON_MASK) + #define SYSCON_AHBCLKCTRL0_GPIO0_MASK (0x4000U) #define SYSCON_AHBCLKCTRL0_GPIO0_SHIFT (14U) /*! GPIO0 - Enables the clock for the GPIO0. @@ -17805,6 +22499,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO0_MASK) + #define SYSCON_AHBCLKCTRL0_GPIO1_MASK (0x8000U) #define SYSCON_AHBCLKCTRL0_GPIO1_SHIFT (15U) /*! GPIO1 - Enables the clock for the GPIO1. @@ -17812,6 +22507,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO1_MASK) + #define SYSCON_AHBCLKCTRL0_GPIO2_MASK (0x10000U) #define SYSCON_AHBCLKCTRL0_GPIO2_SHIFT (16U) /*! GPIO2 - Enables the clock for the GPIO2. @@ -17819,6 +22515,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO2_MASK) + #define SYSCON_AHBCLKCTRL0_GPIO3_MASK (0x20000U) #define SYSCON_AHBCLKCTRL0_GPIO3_SHIFT (17U) /*! GPIO3 - Enables the clock for the GPIO3. @@ -17826,6 +22523,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL0_GPIO3_MASK) + #define SYSCON_AHBCLKCTRL0_PINT_MASK (0x40000U) #define SYSCON_AHBCLKCTRL0_PINT_SHIFT (18U) /*! PINT - Enables the clock for the Pin interrupt (PINT). @@ -17833,6 +22531,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_PINT_SHIFT)) & SYSCON_AHBCLKCTRL0_PINT_MASK) + #define SYSCON_AHBCLKCTRL0_GINT_MASK (0x80000U) #define SYSCON_AHBCLKCTRL0_GINT_SHIFT (19U) /*! GINT - Enables the clock for the Group interrupt (GINT). @@ -17840,6 +22539,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_GINT_SHIFT)) & SYSCON_AHBCLKCTRL0_GINT_MASK) + #define SYSCON_AHBCLKCTRL0_DMA0_MASK (0x100000U) #define SYSCON_AHBCLKCTRL0_DMA0_SHIFT (20U) /*! DMA0 - Enables the clock for the DMA0. @@ -17847,6 +22547,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_DMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_DMA0_SHIFT)) & SYSCON_AHBCLKCTRL0_DMA0_MASK) + #define SYSCON_AHBCLKCTRL0_CRCGEN_MASK (0x200000U) #define SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT (21U) /*! CRCGEN - Enables the clock for the CRCGEN. @@ -17854,6 +22555,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_CRCGEN_SHIFT)) & SYSCON_AHBCLKCTRL0_CRCGEN_MASK) + #define SYSCON_AHBCLKCTRL0_WWDT_MASK (0x400000U) #define SYSCON_AHBCLKCTRL0_WWDT_SHIFT (22U) /*! WWDT - Enables the clock for the Watchdog Timer. @@ -17861,6 +22563,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL0_WWDT_MASK) + #define SYSCON_AHBCLKCTRL0_RTC_MASK (0x800000U) #define SYSCON_AHBCLKCTRL0_RTC_SHIFT (23U) /*! RTC - Enables the clock for the Real Time Clock (RTC). @@ -17868,6 +22571,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_RTC_SHIFT)) & SYSCON_AHBCLKCTRL0_RTC_MASK) + #define SYSCON_AHBCLKCTRL0_MAILBOX_MASK (0x4000000U) #define SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT (26U) /*! MAILBOX - Enables the clock for the Inter CPU communication Mailbox. @@ -17875,6 +22579,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL0_MAILBOX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL0_MAILBOX_SHIFT)) & SYSCON_AHBCLKCTRL0_MAILBOX_MASK) + #define SYSCON_AHBCLKCTRL0_ADC_MASK (0x8000000U) #define SYSCON_AHBCLKCTRL0_ADC_SHIFT (27U) /*! ADC - Enables the clock for the ADC. @@ -17886,6 +22591,7 @@ typedef struct { /*! @name AHBCLKCTRL1 - AHB Clock control 1 */ /*! @{ */ + #define SYSCON_AHBCLKCTRL1_MRT_MASK (0x1U) #define SYSCON_AHBCLKCTRL1_MRT_SHIFT (0U) /*! MRT - Enables the clock for the MRT. @@ -17893,34 +22599,31 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_MRT_SHIFT)) & SYSCON_AHBCLKCTRL1_MRT_MASK) -#define SYSCON_AHBCLKCTRL1_OSTIMER0_MASK (0x2U) -#define SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT (1U) -/*! OSTIMER0 - Enables the clock for the OS Timer 0. + +#define SYSCON_AHBCLKCTRL1_OSTIMER_MASK (0x2U) +#define SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT (1U) +/*! OSTIMER - Enables the clock for the OS Event Timer. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL1_OSTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER0_MASK) -#define SYSCON_AHBCLKCTRL1_SCT0_MASK (0x4U) -#define SYSCON_AHBCLKCTRL1_SCT0_SHIFT (2U) -/*! SCT0 - Enables the clock for the SCT0. +#define SYSCON_AHBCLKCTRL1_OSTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_OSTIMER_SHIFT)) & SYSCON_AHBCLKCTRL1_OSTIMER_MASK) + +#define SYSCON_AHBCLKCTRL1_SCT_MASK (0x4U) +#define SYSCON_AHBCLKCTRL1_SCT_SHIFT (2U) +/*! SCT - Enables the clock for the SCT. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL1_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT0_MASK) -#define SYSCON_AHBCLKCTRL1_SCTIPU_MASK (0x40U) -#define SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT (6U) -/*! SCTIPU - Enables the clock for the SCTIPU. +#define SYSCON_AHBCLKCTRL1_SCT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCT_SHIFT)) & SYSCON_AHBCLKCTRL1_SCT_MASK) + +#define SYSCON_AHBCLKCTRL1_UTICK_MASK (0x400U) +#define SYSCON_AHBCLKCTRL1_UTICK_SHIFT (10U) +/*! UTICK - Enables the clock for the UTICK. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL1_SCTIPU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_SCTIPU_SHIFT)) & SYSCON_AHBCLKCTRL1_SCTIPU_MASK) -#define SYSCON_AHBCLKCTRL1_UTICK0_MASK (0x400U) -#define SYSCON_AHBCLKCTRL1_UTICK0_SHIFT (10U) -/*! UTICK0 - Enables the clock for the UTICK0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK0_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK0_MASK) +#define SYSCON_AHBCLKCTRL1_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL1_UTICK_MASK) + #define SYSCON_AHBCLKCTRL1_FC0_MASK (0x800U) #define SYSCON_AHBCLKCTRL1_FC0_SHIFT (11U) /*! FC0 - Enables the clock for the FC0. @@ -17928,6 +22631,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC0_SHIFT)) & SYSCON_AHBCLKCTRL1_FC0_MASK) + #define SYSCON_AHBCLKCTRL1_FC1_MASK (0x1000U) #define SYSCON_AHBCLKCTRL1_FC1_SHIFT (12U) /*! FC1 - Enables the clock for the FC1. @@ -17935,6 +22639,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC1_SHIFT)) & SYSCON_AHBCLKCTRL1_FC1_MASK) + #define SYSCON_AHBCLKCTRL1_FC2_MASK (0x2000U) #define SYSCON_AHBCLKCTRL1_FC2_SHIFT (13U) /*! FC2 - Enables the clock for the FC2. @@ -17942,6 +22647,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC2_SHIFT)) & SYSCON_AHBCLKCTRL1_FC2_MASK) + #define SYSCON_AHBCLKCTRL1_FC3_MASK (0x4000U) #define SYSCON_AHBCLKCTRL1_FC3_SHIFT (14U) /*! FC3 - Enables the clock for the FC3. @@ -17949,6 +22655,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC3_SHIFT)) & SYSCON_AHBCLKCTRL1_FC3_MASK) + #define SYSCON_AHBCLKCTRL1_FC4_MASK (0x8000U) #define SYSCON_AHBCLKCTRL1_FC4_SHIFT (15U) /*! FC4 - Enables the clock for the FC4. @@ -17956,6 +22663,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC4_SHIFT)) & SYSCON_AHBCLKCTRL1_FC4_MASK) + #define SYSCON_AHBCLKCTRL1_FC5_MASK (0x10000U) #define SYSCON_AHBCLKCTRL1_FC5_SHIFT (16U) /*! FC5 - Enables the clock for the FC5. @@ -17963,6 +22671,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC5_SHIFT)) & SYSCON_AHBCLKCTRL1_FC5_MASK) + #define SYSCON_AHBCLKCTRL1_FC6_MASK (0x20000U) #define SYSCON_AHBCLKCTRL1_FC6_SHIFT (17U) /*! FC6 - Enables the clock for the FC6. @@ -17970,6 +22679,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC6_SHIFT)) & SYSCON_AHBCLKCTRL1_FC6_MASK) + #define SYSCON_AHBCLKCTRL1_FC7_MASK (0x40000U) #define SYSCON_AHBCLKCTRL1_FC7_SHIFT (18U) /*! FC7 - Enables the clock for the FC7. @@ -17977,6 +22687,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_FC7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_FC7_SHIFT)) & SYSCON_AHBCLKCTRL1_FC7_MASK) + #define SYSCON_AHBCLKCTRL1_TIMER2_MASK (0x400000U) #define SYSCON_AHBCLKCTRL1_TIMER2_SHIFT (22U) /*! TIMER2 - Enables the clock for the Timer 2. @@ -17984,6 +22695,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_TIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER2_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER2_MASK) + #define SYSCON_AHBCLKCTRL1_USB0_DEV_MASK (0x2000000U) #define SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT (25U) /*! USB0_DEV - Enables the clock for the USB0 DEV. @@ -17991,6 +22703,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_USB0_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_USB0_DEV_SHIFT)) & SYSCON_AHBCLKCTRL1_USB0_DEV_MASK) + #define SYSCON_AHBCLKCTRL1_TIMER0_MASK (0x4000000U) #define SYSCON_AHBCLKCTRL1_TIMER0_SHIFT (26U) /*! TIMER0 - Enables the clock for the Timer 0. @@ -17998,6 +22711,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_TIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER0_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER0_MASK) + #define SYSCON_AHBCLKCTRL1_TIMER1_MASK (0x8000000U) #define SYSCON_AHBCLKCTRL1_TIMER1_SHIFT (27U) /*! TIMER1 - Enables the clock for the Timer 1. @@ -18005,31 +22719,11 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL1_TIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_TIMER1_SHIFT)) & SYSCON_AHBCLKCTRL1_TIMER1_MASK) -#define SYSCON_AHBCLKCTRL1_PVT_MASK (0x10000000U) -#define SYSCON_AHBCLKCTRL1_PVT_SHIFT (28U) -/*! PVT - Enables the clock for the PVT. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_PVT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_PVT_SHIFT)) & SYSCON_AHBCLKCTRL1_PVT_MASK) -#define SYSCON_AHBCLKCTRL1_EZHA_MASK (0x40000000U) -#define SYSCON_AHBCLKCTRL1_EZHA_SHIFT (30U) -/*! EZHA - Enables the clock for the EZH a. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_EZHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHA_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHA_MASK) -#define SYSCON_AHBCLKCTRL1_EZHB_MASK (0x80000000U) -#define SYSCON_AHBCLKCTRL1_EZHB_SHIFT (31U) -/*! EZHB - Enables the clock for the EZH b. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL1_EZHB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL1_EZHB_SHIFT)) & SYSCON_AHBCLKCTRL1_EZHB_MASK) /*! @} */ /*! @name AHBCLKCTRL2 - AHB Clock control 2 */ /*! @{ */ + #define SYSCON_AHBCLKCTRL2_DMA1_MASK (0x2U) #define SYSCON_AHBCLKCTRL2_DMA1_SHIFT (1U) /*! DMA1 - Enables the clock for the DMA1. @@ -18037,6 +22731,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_DMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_DMA1_SHIFT)) & SYSCON_AHBCLKCTRL2_DMA1_MASK) + #define SYSCON_AHBCLKCTRL2_COMP_MASK (0x4U) #define SYSCON_AHBCLKCTRL2_COMP_SHIFT (2U) /*! COMP - Enables the clock for the Comparator. @@ -18044,6 +22739,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_COMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_COMP_SHIFT)) & SYSCON_AHBCLKCTRL2_COMP_MASK) + #define SYSCON_AHBCLKCTRL2_SDIO_MASK (0x8U) #define SYSCON_AHBCLKCTRL2_SDIO_SHIFT (3U) /*! SDIO - Enables the clock for the SDIO. @@ -18051,6 +22747,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL2_SDIO_MASK) + #define SYSCON_AHBCLKCTRL2_USB1_HOST_MASK (0x10U) #define SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT (4U) /*! USB1_HOST - Enables the clock for the USB1 Host. @@ -18058,6 +22755,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB1_HOST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_HOST_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_HOST_MASK) + #define SYSCON_AHBCLKCTRL2_USB1_DEV_MASK (0x20U) #define SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT (5U) /*! USB1_DEV - Enables the clock for the USB1 dev. @@ -18065,6 +22763,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB1_DEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_DEV_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_DEV_MASK) + #define SYSCON_AHBCLKCTRL2_USB1_RAM_MASK (0x40U) #define SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT (6U) /*! USB1_RAM - Enables the clock for the USB1 RAM. @@ -18072,6 +22771,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB1_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_RAM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_RAM_MASK) + #define SYSCON_AHBCLKCTRL2_USB1_PHY_MASK (0x80U) #define SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT (7U) /*! USB1_PHY - Enables the clock for the USB1 PHY. @@ -18079,6 +22779,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB1_PHY_SHIFT)) & SYSCON_AHBCLKCTRL2_USB1_PHY_MASK) + #define SYSCON_AHBCLKCTRL2_FREQME_MASK (0x100U) #define SYSCON_AHBCLKCTRL2_FREQME_SHIFT (8U) /*! FREQME - Enables the clock for the Frequency meter. @@ -18086,27 +22787,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_FREQME(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_FREQME_SHIFT)) & SYSCON_AHBCLKCTRL2_FREQME_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO4_MASK (0x200U) -#define SYSCON_AHBCLKCTRL2_GPIO4_SHIFT (9U) -/*! GPIO4 - Enables the clock for the GPIO4. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO4_MASK) -#define SYSCON_AHBCLKCTRL2_GPIO5_MASK (0x400U) -#define SYSCON_AHBCLKCTRL2_GPIO5_SHIFT (10U) -/*! GPIO5 - Enables the clock for the GPIO5. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO5_MASK) -#define SYSCON_AHBCLKCTRL2_OTP_MASK (0x1000U) -#define SYSCON_AHBCLKCTRL2_OTP_SHIFT (12U) -/*! OTP - Enables the clock for the OTP. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_OTP_SHIFT)) & SYSCON_AHBCLKCTRL2_OTP_MASK) + #define SYSCON_AHBCLKCTRL2_RNG_MASK (0x2000U) #define SYSCON_AHBCLKCTRL2_RNG_SHIFT (13U) /*! RNG - Enables the clock for the RNG. @@ -18114,13 +22795,15 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_RNG_SHIFT)) & SYSCON_AHBCLKCTRL2_RNG_MASK) -#define SYSCON_AHBCLKCTRL2_MUX1_MASK (0x4000U) -#define SYSCON_AHBCLKCTRL2_MUX1_SHIFT (14U) -/*! MUX1 - Enables the clock for the Peripheral Input Mux 1. + +#define SYSCON_AHBCLKCTRL2_SYSCTL_MASK (0x8000U) +#define SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT (15U) +/*! SYSCTL - SYSCTL block clock. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL2_MUX1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_MUX1_SHIFT)) & SYSCON_AHBCLKCTRL2_MUX1_MASK) +#define SYSCON_AHBCLKCTRL2_SYSCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_SYSCTL_SHIFT)) & SYSCON_AHBCLKCTRL2_SYSCTL_MASK) + #define SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK (0x10000U) #define SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT (16U) /*! USB0_HOSTM - Enables the clock for the USB0 Host Master. @@ -18128,6 +22811,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB0_HOSTM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTM_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTM_MASK) + #define SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK (0x20000U) #define SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT (17U) /*! USB0_HOSTS - Enables the clock for the USB0 Host Slave. @@ -18135,13 +22819,15 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_USB0_HOSTS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_USB0_HOSTS_SHIFT)) & SYSCON_AHBCLKCTRL2_USB0_HOSTS_MASK) -#define SYSCON_AHBCLKCTRL2_HASH0_MASK (0x40000U) -#define SYSCON_AHBCLKCTRL2_HASH0_SHIFT (18U) -/*! HASH0 - Enables the clock for the HASH0. + +#define SYSCON_AHBCLKCTRL2_HASH_AES_MASK (0x40000U) +#define SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT (18U) +/*! HASH_AES - Enables the clock for the HASH_AES. * 0b1..Enable Clock. * 0b0..Disable Clock. */ -#define SYSCON_AHBCLKCTRL2_HASH0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH0_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH0_MASK) +#define SYSCON_AHBCLKCTRL2_HASH_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HASH_AES_SHIFT)) & SYSCON_AHBCLKCTRL2_HASH_AES_MASK) + #define SYSCON_AHBCLKCTRL2_PQ_MASK (0x80000U) #define SYSCON_AHBCLKCTRL2_PQ_SHIFT (19U) /*! PQ - Enables the clock for the Power Quad. @@ -18149,6 +22835,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PQ_SHIFT)) & SYSCON_AHBCLKCTRL2_PQ_MASK) + #define SYSCON_AHBCLKCTRL2_PLULUT_MASK (0x100000U) #define SYSCON_AHBCLKCTRL2_PLULUT_SHIFT (20U) /*! PLULUT - Enables the clock for the PLU LUT. @@ -18156,6 +22843,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_PLULUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PLULUT_SHIFT)) & SYSCON_AHBCLKCTRL2_PLULUT_MASK) + #define SYSCON_AHBCLKCTRL2_TIMER3_MASK (0x200000U) #define SYSCON_AHBCLKCTRL2_TIMER3_SHIFT (21U) /*! TIMER3 - Enables the clock for the Timer 3. @@ -18163,6 +22851,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_TIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER3_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER3_MASK) + #define SYSCON_AHBCLKCTRL2_TIMER4_MASK (0x400000U) #define SYSCON_AHBCLKCTRL2_TIMER4_SHIFT (22U) /*! TIMER4 - Enables the clock for the Timer 4. @@ -18170,6 +22859,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_TIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_TIMER4_SHIFT)) & SYSCON_AHBCLKCTRL2_TIMER4_MASK) + #define SYSCON_AHBCLKCTRL2_PUF_MASK (0x800000U) #define SYSCON_AHBCLKCTRL2_PUF_SHIFT (23U) /*! PUF - Enables the clock for the PUF reset control. @@ -18177,6 +22867,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_PUF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_PUF_SHIFT)) & SYSCON_AHBCLKCTRL2_PUF_MASK) + #define SYSCON_AHBCLKCTRL2_CASPER_MASK (0x1000000U) #define SYSCON_AHBCLKCTRL2_CASPER_SHIFT (24U) /*! CASPER - Enables the clock for the Casper. @@ -18184,13 +22875,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_CASPER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CASPER_SHIFT)) & SYSCON_AHBCLKCTRL2_CASPER_MASK) -#define SYSCON_AHBCLKCTRL2_CAPT0_MASK (0x2000000U) -#define SYSCON_AHBCLKCTRL2_CAPT0_SHIFT (25U) -/*! CAPT0 - Enables the clock for the CAPT0. - * 0b1..Enable Clock. - * 0b0..Disable Clock. - */ -#define SYSCON_AHBCLKCTRL2_CAPT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_CAPT0_SHIFT)) & SYSCON_AHBCLKCTRL2_CAPT0_MASK) + #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK (0x8000000U) #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT (27U) /*! ANALOG_CTRL - Enables the clock for the analog control. @@ -18198,6 +22883,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_ANALOG_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_ANALOG_CTRL_SHIFT)) & SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK) + #define SYSCON_AHBCLKCTRL2_HS_LSPI_MASK (0x10000000U) #define SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT (28U) /*! HS_LSPI - Enables the clock for the HS LSPI. @@ -18205,6 +22891,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_HS_LSPI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_HS_LSPI_SHIFT)) & SYSCON_AHBCLKCTRL2_HS_LSPI_MASK) + #define SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK (0x20000000U) #define SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT (29U) /*! GPIO_SEC - Enables the clock for the GPIO secure. @@ -18212,6 +22899,7 @@ typedef struct { * 0b0..Disable Clock. */ #define SYSCON_AHBCLKCTRL2_GPIO_SEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL2_GPIO_SEC_SHIFT)) & SYSCON_AHBCLKCTRL2_GPIO_SEC_MASK) + #define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_MASK (0x40000000U) #define SYSCON_AHBCLKCTRL2_GPIO_SEC_INT_SHIFT (30U) /*! GPIO_SEC_INT - Enables the clock for the GPIO secure int. @@ -18223,8 +22911,11 @@ typedef struct { /*! @name AHBCLKCTRLX - Peripheral reset control register */ /*! @{ */ + #define SYSCON_AHBCLKCTRLX_DATA_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_AHBCLKCTRLX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLX_DATA_SHIFT)) & SYSCON_AHBCLKCTRLX_DATA_MASK) /*! @} */ @@ -18233,8 +22924,11 @@ typedef struct { /*! @name AHBCLKCTRLSET - Peripheral reset control register */ /*! @{ */ + #define SYSCON_AHBCLKCTRLSET_DATA_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLSET_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_AHBCLKCTRLSET_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_DATA_SHIFT)) & SYSCON_AHBCLKCTRLSET_DATA_MASK) /*! @} */ @@ -18243,8 +22937,11 @@ typedef struct { /*! @name AHBCLKCTRLCLR - Peripheral reset control register */ /*! @{ */ + #define SYSCON_AHBCLKCTRLCLR_DATA_MASK (0xFFFFFFFFU) #define SYSCON_AHBCLKCTRLCLR_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_AHBCLKCTRLCLR_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_DATA_SHIFT)) & SYSCON_AHBCLKCTRLCLR_DATA_MASK) /*! @} */ @@ -18253,6 +22950,7 @@ typedef struct { /*! @name SYSTICKCLKSEL0 - System Tick Timer for CPU0 source select */ /*! @{ */ + #define SYSCON_SYSTICKCLKSEL0_SEL_MASK (0x7U) #define SYSCON_SYSTICKCLKSEL0_SEL_SHIFT (0U) /*! SEL - System Tick Timer for CPU0 source select. @@ -18270,6 +22968,7 @@ typedef struct { /*! @name SYSTICKCLKSEL1 - System Tick Timer for CPU1 source select */ /*! @{ */ + #define SYSCON_SYSTICKCLKSEL1_SEL_MASK (0x7U) #define SYSCON_SYSTICKCLKSEL1_SEL_SHIFT (0U) /*! SEL - System Tick Timer for CPU1 source select. @@ -18287,8 +22986,11 @@ typedef struct { /*! @name SYSTICKCLKSELX - Peripheral reset control register */ /*! @{ */ + #define SYSCON_SYSTICKCLKSELX_DATA_MASK (0xFFFFFFFFU) #define SYSCON_SYSTICKCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_SYSTICKCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKSELX_DATA_SHIFT)) & SYSCON_SYSTICKCLKSELX_DATA_MASK) /*! @} */ @@ -18297,6 +22999,7 @@ typedef struct { /*! @name TRACECLKSEL - Trace clock source select */ /*! @{ */ + #define SYSCON_TRACECLKSEL_SEL_MASK (0x7U) #define SYSCON_TRACECLKSEL_SEL_SHIFT (0U) /*! SEL - Trace clock source select. @@ -18314,6 +23017,7 @@ typedef struct { /*! @name CTIMERCLKSEL0 - CTimer 0 clock source select */ /*! @{ */ + #define SYSCON_CTIMERCLKSEL0_SEL_MASK (0x7U) #define SYSCON_CTIMERCLKSEL0_SEL_SHIFT (0U) /*! SEL - CTimer 0 clock source select. @@ -18331,6 +23035,7 @@ typedef struct { /*! @name CTIMERCLKSEL1 - CTimer 1 clock source select */ /*! @{ */ + #define SYSCON_CTIMERCLKSEL1_SEL_MASK (0x7U) #define SYSCON_CTIMERCLKSEL1_SEL_SHIFT (0U) /*! SEL - CTimer 1 clock source select. @@ -18348,6 +23053,7 @@ typedef struct { /*! @name CTIMERCLKSEL2 - CTimer 2 clock source select */ /*! @{ */ + #define SYSCON_CTIMERCLKSEL2_SEL_MASK (0x7U) #define SYSCON_CTIMERCLKSEL2_SEL_SHIFT (0U) /*! SEL - CTimer 2 clock source select. @@ -18365,6 +23071,7 @@ typedef struct { /*! @name CTIMERCLKSEL3 - CTimer 3 clock source select */ /*! @{ */ + #define SYSCON_CTIMERCLKSEL3_SEL_MASK (0x7U) #define SYSCON_CTIMERCLKSEL3_SEL_SHIFT (0U) /*! SEL - CTimer 3 clock source select. @@ -18382,6 +23089,7 @@ typedef struct { /*! @name CTIMERCLKSEL4 - CTimer 4 clock source select */ /*! @{ */ + #define SYSCON_CTIMERCLKSEL4_SEL_MASK (0x7U) #define SYSCON_CTIMERCLKSEL4_SEL_SHIFT (0U) /*! SEL - CTimer 4 clock source select. @@ -18399,8 +23107,11 @@ typedef struct { /*! @name CTIMERCLKSELX - Peripheral reset control register */ /*! @{ */ + #define SYSCON_CTIMERCLKSELX_DATA_MASK (0xFFFFFFFFU) #define SYSCON_CTIMERCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_CTIMERCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CTIMERCLKSELX_DATA_SHIFT)) & SYSCON_CTIMERCLKSELX_DATA_MASK) /*! @} */ @@ -18409,6 +23120,7 @@ typedef struct { /*! @name MAINCLKSELA - Main clock A source select */ /*! @{ */ + #define SYSCON_MAINCLKSELA_SEL_MASK (0x7U) #define SYSCON_MAINCLKSELA_SEL_SHIFT (0U) /*! SEL - Main clock A source select. @@ -18416,16 +23128,17 @@ typedef struct { * 0b001..CLKIN clock. * 0b010..FRO 1MHz clock. * 0b011..FRO 96 MHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. */ #define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK) /*! @} */ /*! @name MAINCLKSELB - Main clock source select */ /*! @{ */ + #define SYSCON_MAINCLKSELB_SEL_MASK (0x7U) #define SYSCON_MAINCLKSELB_SEL_SHIFT (0U) /*! SEL - Main clock source select. @@ -18433,16 +23146,17 @@ typedef struct { * 0b001..PLL0 clock. * 0b010..PLL1 clock. * 0b011..Oscillator 32 kHz clock. - * 0b100..No clock. - * 0b101..No clock. - * 0b110..No clock. - * 0b111..No clock. + * 0b100..Reserved. + * 0b101..Reserved. + * 0b110..Reserved. + * 0b111..Reserved. */ #define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK) /*! @} */ /*! @name CLKOUTSEL - CLKOUT clock source select */ /*! @{ */ + #define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) #define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) /*! SEL - CLKOUT clock source select. @@ -18460,6 +23174,7 @@ typedef struct { /*! @name PLL0CLKSEL - PLL0 clock source select */ /*! @{ */ + #define SYSCON_PLL0CLKSEL_SEL_MASK (0x7U) #define SYSCON_PLL0CLKSEL_SEL_SHIFT (0U) /*! SEL - PLL0 clock source select. @@ -18477,6 +23192,7 @@ typedef struct { /*! @name PLL1CLKSEL - PLL1 clock source select */ /*! @{ */ + #define SYSCON_PLL1CLKSEL_SEL_MASK (0x7U) #define SYSCON_PLL1CLKSEL_SEL_SHIFT (0U) /*! SEL - PLL1 clock source select. @@ -18494,13 +23210,14 @@ typedef struct { /*! @name ADCCLKSEL - ADC clock source select */ /*! @{ */ + #define SYSCON_ADCCLKSEL_SEL_MASK (0x7U) #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) /*! SEL - ADC clock source select. * 0b000..Main clock. * 0b001..PLL0 clock. * 0b010..FRO 96 MHz clock. - * 0b011..No clock. + * 0b011..Reserved. * 0b100..No clock. * 0b101..No clock. * 0b110..No clock. @@ -18511,6 +23228,7 @@ typedef struct { /*! @name USB0CLKSEL - FS USB clock source select */ /*! @{ */ + #define SYSCON_USB0CLKSEL_SEL_MASK (0x7U) #define SYSCON_USB0CLKSEL_SEL_SHIFT (0U) /*! SEL - FS USB clock source select. @@ -18526,25 +23244,9 @@ typedef struct { #define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK) /*! @} */ -/*! @name USB1CLKSEL - HS USB clock source select - NOT USED */ -/*! @{ */ -#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U) -#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U) -/*! SEL - HS USB clock source select. - * 0b000..Main clock. - * 0b001..PLL0 clock. - * 0b010..CLKIN clock. - * 0b011..No clock. - * 0b100..No clock. - * 0b101..PLL1 clock. - * 0b110..No clock. - * 0b111..No clock. - */ -#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK) -/*! @} */ - /*! @name FCCLKSEL0 - Flexcomm Interface 0 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL0_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL0_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 0 clock source select for Fractional Rate Divider. @@ -18562,6 +23264,7 @@ typedef struct { /*! @name FCCLKSEL1 - Flexcomm Interface 1 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL1_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL1_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 1 clock source select for Fractional Rate Divider. @@ -18579,6 +23282,7 @@ typedef struct { /*! @name FCCLKSEL2 - Flexcomm Interface 2 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL2_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL2_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 2 clock source select for Fractional Rate Divider. @@ -18596,6 +23300,7 @@ typedef struct { /*! @name FCCLKSEL3 - Flexcomm Interface 3 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL3_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL3_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 3 clock source select for Fractional Rate Divider. @@ -18613,6 +23318,7 @@ typedef struct { /*! @name FCCLKSEL4 - Flexcomm Interface 4 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL4_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL4_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 4 clock source select for Fractional Rate Divider. @@ -18630,6 +23336,7 @@ typedef struct { /*! @name FCCLKSEL5 - Flexcomm Interface 5 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL5_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL5_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 5 clock source select for Fractional Rate Divider. @@ -18647,6 +23354,7 @@ typedef struct { /*! @name FCCLKSEL6 - Flexcomm Interface 6 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL6_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL6_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 6 clock source select for Fractional Rate Divider. @@ -18664,6 +23372,7 @@ typedef struct { /*! @name FCCLKSEL7 - Flexcomm Interface 7 clock source select for Fractional Rate Divider */ /*! @{ */ + #define SYSCON_FCCLKSEL7_SEL_MASK (0x7U) #define SYSCON_FCCLKSEL7_SEL_SHIFT (0U) /*! SEL - Flexcomm Interface 7 clock source select for Fractional Rate Divider. @@ -18681,8 +23390,11 @@ typedef struct { /*! @name FCCLKSELX - Peripheral reset control register */ /*! @{ */ + #define SYSCON_FCCLKSELX_DATA_MASK (0xFFFFFFFFU) #define SYSCON_FCCLKSELX_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_FCCLKSELX_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCCLKSELX_DATA_SHIFT)) & SYSCON_FCCLKSELX_DATA_MASK) /*! @} */ @@ -18691,6 +23403,7 @@ typedef struct { /*! @name HSLSPICLKSEL - HS LSPI clock source select */ /*! @{ */ + #define SYSCON_HSLSPICLKSEL_SEL_MASK (0x7U) #define SYSCON_HSLSPICLKSEL_SEL_SHIFT (0U) /*! SEL - HS LSPI clock source select. @@ -18708,13 +23421,14 @@ typedef struct { /*! @name MCLKCLKSEL - MCLK clock source select */ /*! @{ */ + #define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U) #define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U) /*! SEL - MCLK clock source select. * 0b000..FRO 96 MHz clock. * 0b001..PLL0 clock. - * 0b010..No clock. - * 0b011..No clock. + * 0b010..Reserved. + * 0b011..Reserved. * 0b100..No clock. * 0b101..No clock. * 0b110..No clock. @@ -18725,6 +23439,7 @@ typedef struct { /*! @name SCTCLKSEL - SCTimer/PWM clock source select */ /*! @{ */ + #define SYSCON_SCTCLKSEL_SEL_MASK (0x7U) #define SYSCON_SCTCLKSEL_SEL_SHIFT (0U) /*! SEL - SCTimer/PWM clock source select. @@ -18742,6 +23457,7 @@ typedef struct { /*! @name SDIOCLKSEL - SDIO clock source select */ /*! @{ */ + #define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U) #define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U) /*! SEL - SDIO clock source select. @@ -18759,9 +23475,13 @@ typedef struct { /*! @name SYSTICKCLKDIV0 - System Tick Timer divider for CPU0 */ /*! @{ */ + #define SYSCON_SYSTICKCLKDIV0_DIV_MASK (0xFFU) #define SYSCON_SYSTICKCLKDIV0_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_SYSTICKCLKDIV0_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV0_DIV_MASK) + #define SYSCON_SYSTICKCLKDIV0_RESET_MASK (0x20000000U) #define SYSCON_SYSTICKCLKDIV0_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18769,6 +23489,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_SYSTICKCLKDIV0_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV0_RESET_MASK) + #define SYSCON_SYSTICKCLKDIV0_HALT_MASK (0x40000000U) #define SYSCON_SYSTICKCLKDIV0_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -18776,6 +23497,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_SYSTICKCLKDIV0_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV0_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV0_HALT_MASK) + #define SYSCON_SYSTICKCLKDIV0_REQFLAG_MASK (0x80000000U) #define SYSCON_SYSTICKCLKDIV0_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -18787,9 +23509,13 @@ typedef struct { /*! @name SYSTICKCLKDIV1 - System Tick Timer divider for CPU1 */ /*! @{ */ + #define SYSCON_SYSTICKCLKDIV1_DIV_MASK (0xFFU) #define SYSCON_SYSTICKCLKDIV1_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_SYSTICKCLKDIV1_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV1_DIV_MASK) + #define SYSCON_SYSTICKCLKDIV1_RESET_MASK (0x20000000U) #define SYSCON_SYSTICKCLKDIV1_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18797,6 +23523,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_SYSTICKCLKDIV1_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV1_RESET_MASK) + #define SYSCON_SYSTICKCLKDIV1_HALT_MASK (0x40000000U) #define SYSCON_SYSTICKCLKDIV1_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -18804,6 +23531,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_SYSTICKCLKDIV1_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV1_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV1_HALT_MASK) + #define SYSCON_SYSTICKCLKDIV1_REQFLAG_MASK (0x80000000U) #define SYSCON_SYSTICKCLKDIV1_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -18815,9 +23543,13 @@ typedef struct { /*! @name TRACECLKDIV - TRACE clock divider */ /*! @{ */ + #define SYSCON_TRACECLKDIV_DIV_MASK (0xFFU) #define SYSCON_TRACECLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_TRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_DIV_SHIFT)) & SYSCON_TRACECLKDIV_DIV_MASK) + #define SYSCON_TRACECLKDIV_RESET_MASK (0x20000000U) #define SYSCON_TRACECLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18825,6 +23557,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_TRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_RESET_SHIFT)) & SYSCON_TRACECLKDIV_RESET_MASK) + #define SYSCON_TRACECLKDIV_HALT_MASK (0x40000000U) #define SYSCON_TRACECLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -18832,6 +23565,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_TRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_TRACECLKDIV_HALT_SHIFT)) & SYSCON_TRACECLKDIV_HALT_MASK) + #define SYSCON_TRACECLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_TRACECLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -18843,88 +23577,139 @@ typedef struct { /*! @name FLEXFRG0CTRL - Fractional rate divider for flexcomm 0 */ /*! @{ */ + #define SYSCON_FLEXFRG0CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG0CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG0CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG0CTRL_DIV_MASK) + #define SYSCON_FLEXFRG0CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG0CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG0CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG0CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG0CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG1CTRL - Fractional rate divider for flexcomm 1 */ /*! @{ */ + #define SYSCON_FLEXFRG1CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG1CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG1CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG1CTRL_DIV_MASK) + #define SYSCON_FLEXFRG1CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG1CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG1CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG1CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG1CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG2CTRL - Fractional rate divider for flexcomm 2 */ /*! @{ */ + #define SYSCON_FLEXFRG2CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG2CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG2CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG2CTRL_DIV_MASK) + #define SYSCON_FLEXFRG2CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG2CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG2CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG2CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG2CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG3CTRL - Fractional rate divider for flexcomm 3 */ /*! @{ */ + #define SYSCON_FLEXFRG3CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG3CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG3CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG3CTRL_DIV_MASK) + #define SYSCON_FLEXFRG3CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG3CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG3CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG3CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG3CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG4CTRL - Fractional rate divider for flexcomm 4 */ /*! @{ */ + #define SYSCON_FLEXFRG4CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG4CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG4CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG4CTRL_DIV_MASK) + #define SYSCON_FLEXFRG4CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG4CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG4CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG4CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG4CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG5CTRL - Fractional rate divider for flexcomm 5 */ /*! @{ */ + #define SYSCON_FLEXFRG5CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG5CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG5CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG5CTRL_DIV_MASK) + #define SYSCON_FLEXFRG5CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG5CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG5CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG5CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG5CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG6CTRL - Fractional rate divider for flexcomm 6 */ /*! @{ */ + #define SYSCON_FLEXFRG6CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG6CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG6CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG6CTRL_DIV_MASK) + #define SYSCON_FLEXFRG6CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG6CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG6CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG6CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG6CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRG7CTRL - Fractional rate divider for flexcomm 7 */ /*! @{ */ + #define SYSCON_FLEXFRG7CTRL_DIV_MASK (0xFFU) #define SYSCON_FLEXFRG7CTRL_DIV_SHIFT (0U) +/*! DIV - Denominator of the fractional rate divider. + */ #define SYSCON_FLEXFRG7CTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_DIV_SHIFT)) & SYSCON_FLEXFRG7CTRL_DIV_MASK) + #define SYSCON_FLEXFRG7CTRL_MULT_MASK (0xFF00U) #define SYSCON_FLEXFRG7CTRL_MULT_SHIFT (8U) +/*! MULT - Numerator of the fractional rate divider. + */ #define SYSCON_FLEXFRG7CTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRG7CTRL_MULT_SHIFT)) & SYSCON_FLEXFRG7CTRL_MULT_MASK) /*! @} */ /*! @name FLEXFRGXCTRL - Peripheral reset control register */ /*! @{ */ + #define SYSCON_FLEXFRGXCTRL_DATA_MASK (0xFFFFFFFFU) #define SYSCON_FLEXFRGXCTRL_DATA_SHIFT (0U) +/*! DATA - Data array value + */ #define SYSCON_FLEXFRGXCTRL_DATA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLEXFRGXCTRL_DATA_SHIFT)) & SYSCON_FLEXFRGXCTRL_DATA_MASK) /*! @} */ @@ -18933,9 +23718,13 @@ typedef struct { /*! @name AHBCLKDIV - System clock divider */ /*! @{ */ + #define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU) #define SYSCON_AHBCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK) + #define SYSCON_AHBCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_AHBCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18943,6 +23732,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_AHBCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_RESET_SHIFT)) & SYSCON_AHBCLKDIV_RESET_MASK) + #define SYSCON_AHBCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_AHBCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -18950,6 +23740,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_AHBCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_HALT_SHIFT)) & SYSCON_AHBCLKDIV_HALT_MASK) + #define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -18961,9 +23752,13 @@ typedef struct { /*! @name CLKOUTDIV - CLKOUT clock divider */ /*! @{ */ + #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) + #define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U) #define SYSCON_CLKOUTDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18971,6 +23766,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK) + #define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U) #define SYSCON_CLKOUTDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -18978,6 +23774,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK) + #define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -18989,9 +23786,13 @@ typedef struct { /*! @name FROHFDIV - FRO_HF (96MHz) clock divider */ /*! @{ */ + #define SYSCON_FROHFDIV_DIV_MASK (0xFFU) #define SYSCON_FROHFDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_FROHFDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_DIV_SHIFT)) & SYSCON_FROHFDIV_DIV_MASK) + #define SYSCON_FROHFDIV_RESET_MASK (0x20000000U) #define SYSCON_FROHFDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -18999,6 +23800,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_FROHFDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_RESET_SHIFT)) & SYSCON_FROHFDIV_RESET_MASK) + #define SYSCON_FROHFDIV_HALT_MASK (0x40000000U) #define SYSCON_FROHFDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19006,6 +23808,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_FROHFDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFDIV_HALT_SHIFT)) & SYSCON_FROHFDIV_HALT_MASK) + #define SYSCON_FROHFDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_FROHFDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19017,9 +23820,13 @@ typedef struct { /*! @name WDTCLKDIV - WDT clock divider */ /*! @{ */ + #define SYSCON_WDTCLKDIV_DIV_MASK (0x3FU) #define SYSCON_WDTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_WDTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_DIV_SHIFT)) & SYSCON_WDTCLKDIV_DIV_MASK) + #define SYSCON_WDTCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_WDTCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19027,6 +23834,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_WDTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_RESET_SHIFT)) & SYSCON_WDTCLKDIV_RESET_MASK) + #define SYSCON_WDTCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_WDTCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19034,6 +23842,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_WDTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTCLKDIV_HALT_SHIFT)) & SYSCON_WDTCLKDIV_HALT_MASK) + #define SYSCON_WDTCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_WDTCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19045,9 +23854,13 @@ typedef struct { /*! @name ADCCLKDIV - ADC clock divider */ /*! @{ */ + #define SYSCON_ADCCLKDIV_DIV_MASK (0x7U) #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) + #define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_ADCCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19055,6 +23868,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK) + #define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_ADCCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19062,6 +23876,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK) + #define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19073,9 +23888,13 @@ typedef struct { /*! @name USB0CLKDIV - USB0 Clock divider */ /*! @{ */ + #define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU) #define SYSCON_USB0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK) + #define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_USB0CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19083,6 +23902,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK) + #define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_USB0CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19090,6 +23910,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK) + #define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19101,9 +23922,13 @@ typedef struct { /*! @name MCLKDIV - I2S MCLK clock divider */ /*! @{ */ + #define SYSCON_MCLKDIV_DIV_MASK (0xFFU) #define SYSCON_MCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK) + #define SYSCON_MCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_MCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19111,6 +23936,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK) + #define SYSCON_MCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_MCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19118,6 +23944,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK) + #define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19129,9 +23956,13 @@ typedef struct { /*! @name SCTCLKDIV - SCT/PWM clock divider */ /*! @{ */ + #define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU) #define SYSCON_SCTCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK) + #define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_SCTCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19139,6 +23970,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK) + #define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SCTCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19146,6 +23978,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK) + #define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19157,9 +23990,13 @@ typedef struct { /*! @name SDIOCLKDIV - SDIO clock divider */ /*! @{ */ + #define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU) #define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK) + #define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U) #define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19167,6 +24004,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK) + #define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U) #define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19174,6 +24012,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK) + #define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19185,9 +24024,13 @@ typedef struct { /*! @name PLL0CLKDIV - PLL0 clock divider */ /*! @{ */ + #define SYSCON_PLL0CLKDIV_DIV_MASK (0xFFU) #define SYSCON_PLL0CLKDIV_DIV_SHIFT (0U) +/*! DIV - Clock divider value. + */ #define SYSCON_PLL0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_DIV_SHIFT)) & SYSCON_PLL0CLKDIV_DIV_MASK) + #define SYSCON_PLL0CLKDIV_RESET_MASK (0x20000000U) #define SYSCON_PLL0CLKDIV_RESET_SHIFT (29U) /*! RESET - Resets the divider counter. @@ -19195,6 +24038,7 @@ typedef struct { * 0b0..Divider is not reset. */ #define SYSCON_PLL0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_RESET_SHIFT)) & SYSCON_PLL0CLKDIV_RESET_MASK) + #define SYSCON_PLL0CLKDIV_HALT_MASK (0x40000000U) #define SYSCON_PLL0CLKDIV_HALT_SHIFT (30U) /*! HALT - Halts the divider counter. @@ -19202,6 +24046,7 @@ typedef struct { * 0b0..Divider clock is running. */ #define SYSCON_PLL0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CLKDIV_HALT_SHIFT)) & SYSCON_PLL0CLKDIV_HALT_MASK) + #define SYSCON_PLL0CLKDIV_REQFLAG_MASK (0x80000000U) #define SYSCON_PLL0CLKDIV_REQFLAG_SHIFT (31U) /*! REQFLAG - Divider status flag. @@ -19213,6 +24058,7 @@ typedef struct { /*! @name CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL) */ /*! @{ */ + #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK (0xFFFFFFFFU) #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT (0U) /*! CLOCKGENUPDATELOCKOUT - Control clock configuration registers access (like xxxDIV, xxxSEL). @@ -19222,208 +24068,218 @@ typedef struct { #define SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_SHIFT)) & SYSCON_CLOCKGENUPDATELOCKOUT_CLOCKGENUPDATELOCKOUT_MASK) /*! @} */ -/*! @name FMCCR - FMC configuration register - INTERNAL USE ONLY */ +/*! @name FMCCR - FMC configuration register */ /*! @{ */ -#define SYSCON_FMCCR_FETCHCTL_MASK (0x3U) -#define SYSCON_FMCCR_FETCHCTL_SHIFT (0U) -/*! FETCHCTL - Fetch control - * 0b00..No buffering (bypass always used) for Fetch cycles - * 0b01..One buffer is used for all Fetch cycles - * 0b10..All buffers can be used for Fetch cycles + +#define SYSCON_FMCCR_FETCHCFG_MASK (0x3U) +#define SYSCON_FMCCR_FETCHCFG_SHIFT (0U) +/*! FETCHCFG - Instruction fetch configuration. + * 0b00..Instruction fetches from flash are not buffered. + * 0b01..One buffer is used for all instruction fetches. + * 0b10..All buffers may be used for instruction fetches. */ -#define SYSCON_FMCCR_FETCHCTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCTL_SHIFT)) & SYSCON_FMCCR_FETCHCTL_MASK) -#define SYSCON_FMCCR_DATACTL_MASK (0xCU) -#define SYSCON_FMCCR_DATACTL_SHIFT (2U) -/*! DATACTL - Data control - * 0b00..No buffering (bypass always used) for Data cycles - * 0b01..One buffer is used for all Data cycles - * 0b10..All buffers can be used for Data cycles +#define SYSCON_FMCCR_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FETCHCFG_SHIFT)) & SYSCON_FMCCR_FETCHCFG_MASK) + +#define SYSCON_FMCCR_DATACFG_MASK (0xCU) +#define SYSCON_FMCCR_DATACFG_SHIFT (2U) +/*! DATACFG - Data read configuration. + * 0b00..Data accesses from flash are not buffered. + * 0b01..One buffer is used for all data accesses. + * 0b10..All buffers can be used for data accesses. */ -#define SYSCON_FMCCR_DATACTL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACTL_SHIFT)) & SYSCON_FMCCR_DATACTL_MASK) +#define SYSCON_FMCCR_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_DATACFG_SHIFT)) & SYSCON_FMCCR_DATACFG_MASK) + #define SYSCON_FMCCR_ACCEL_MASK (0x10U) #define SYSCON_FMCCR_ACCEL_SHIFT (4U) +/*! ACCEL - Acceleration enable. + * 0b0..Flash acceleration is disabled. + * 0b1..Flash acceleration is enabled. + */ #define SYSCON_FMCCR_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_ACCEL_SHIFT)) & SYSCON_FMCCR_ACCEL_MASK) + #define SYSCON_FMCCR_PREFEN_MASK (0x20U) #define SYSCON_FMCCR_PREFEN_SHIFT (5U) +/*! PREFEN - Prefetch enable. + * 0b0..No instruction prefetch is performed. + * 0b1..Instruction prefetch is enabled. + */ #define SYSCON_FMCCR_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFEN_SHIFT)) & SYSCON_FMCCR_PREFEN_MASK) + #define SYSCON_FMCCR_PREFOVR_MASK (0x40U) #define SYSCON_FMCCR_PREFOVR_SHIFT (6U) +/*! PREFOVR - Prefetch override. + * 0b0..Any previously initiated prefetch will be completed. + * 0b1..Any previously initiated prefetch will be aborted, and the next flash line following the current + * execution address will be prefetched if not already buffered. + */ #define SYSCON_FMCCR_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFOVR_SHIFT)) & SYSCON_FMCCR_PREFOVR_MASK) -#define SYSCON_FMCCR_PREFCRI_MASK (0x700U) -#define SYSCON_FMCCR_PREFCRI_SHIFT (8U) -#define SYSCON_FMCCR_PREFCRI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PREFCRI_SHIFT)) & SYSCON_FMCCR_PREFCRI_MASK) -#define SYSCON_FMCCR_FMCTIM_MASK (0x1F000U) -#define SYSCON_FMCCR_FMCTIM_SHIFT (12U) -#define SYSCON_FMCCR_FMCTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FMCTIM_SHIFT)) & SYSCON_FMCCR_FMCTIM_MASK) -#define SYSCON_FMCCR_PFISLRU_MASK (0x20000U) -#define SYSCON_FMCCR_PFISLRU_SHIFT (17U) -#define SYSCON_FMCCR_PFISLRU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFISLRU_SHIFT)) & SYSCON_FMCCR_PFISLRU_MASK) -#define SYSCON_FMCCR_PFADAP_MASK (0x40000U) -#define SYSCON_FMCCR_PFADAP_SHIFT (18U) -#define SYSCON_FMCCR_PFADAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_PFADAP_SHIFT)) & SYSCON_FMCCR_PFADAP_MASK) + +#define SYSCON_FMCCR_FLASHTIM_MASK (0xF000U) +#define SYSCON_FMCCR_FLASHTIM_SHIFT (12U) +/*! FLASHTIM - Flash memory access time. + * 0b0000..1 system clock flash access time (for system clock rates up to 11 MHz). + * 0b0001..2 system clocks flash access time (for system clock rates up to 22 MHz). + * 0b0010..3 system clocks flash access time (for system clock rates up to 33 MHz). + * 0b0011..4 system clocks flash access time (for system clock rates up to 44 MHz). + * 0b0100..5 system clocks flash access time (for system clock rates up to 55 MHz). + * 0b0101..6 system clocks flash access time (for system clock rates up to 66 MHz). + * 0b0110..7 system clocks flash access time (for system clock rates up to 77 MHz). + * 0b0111..8 system clocks flash access time (for system clock rates up to 88 MHz). + * 0b1000..9 system clocks flash access time (for system clock rates up to 100 MHz). + * 0b1001..10 system clocks flash access time (for system clock rates up to 115 MHz). + * 0b1010..11 system clocks flash access time (for system clock rates up to 130 MHz). + * 0b1011..12 system clocks flash access time (for system clock rates up to 150 MHz). + */ +#define SYSCON_FMCCR_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCCR_FLASHTIM_SHIFT)) & SYSCON_FMCCR_FLASHTIM_MASK) /*! @} */ -/*! @name USB0CLKCTRL - USB0 clock control */ +/*! @name USB0NEEDCLKCTRL - USB0 need clock control */ /*! @{ */ -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U) -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U) -/*! AP_FS_DEV_CLK - USB0 Device USB0_NEEDCLK signal control:. + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal control:. * 0b0..Under hardware control. * 0b1..Forced high. */ -#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK) -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U) -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U) -/*! POL_FS_DEV_CLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_FS_DEV_NEEDCLK - USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. */ -#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK) -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U) -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U) -/*! AP_FS_HOST_CLK - USB0 Host USB0_NEEDCLK signal control:. +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal control:. * 0b0..Under hardware control. * 0b1..Forced high. */ -#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK) -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U) -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U) -/*! POL_FS_HOST_CLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. +#define SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_AP_FS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_FS_HOST_NEEDCLK - USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. * 0b0..Falling edge of device USB0_NEEDCLK triggers wake-up. * 0b1..Rising edge of device USB0_NEEDCLK triggers wake-up. */ -#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK) -#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U) -#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U) -/*! PU_DISABLE - Internal pull-up disable control. - * 0b1..Internal pull-up disable. - * 0b0..Internal pull-up enable. - */ -#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK) +#define SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKCTRL_POL_FS_HOST_NEEDCLK_MASK) /*! @} */ -/*! @name USB0CLKSTAT - USB0 clock status */ +/*! @name USB0NEEDCLKSTAT - USB0 need clock status */ /*! @{ */ -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) -/*! DEV_NEED_CLKST - USB0 Device USB0_NEEDCLK signal status:. + +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB0 Device USB0_NEEDCLK signal status:. * 0b1..USB0 Device clock is high. * 0b0..USB0 Device clock is low. */ -#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK) -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) -/*! HOST_NEED_CLKST - USB0 Host USB0_NEEDCLK signal status:. +#define SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB0 Host USB0_NEEDCLK signal status:. * 0b1..USB0 Host clock is high. * 0b0..USB0 Host clock is low. */ -#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK) +#define SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB0NEEDCLKSTAT_HOST_NEEDCLK_MASK) /*! @} */ /*! @name FMCFLUSH - FMCflush control */ /*! @{ */ + #define SYSCON_FMCFLUSH_FLUSH_MASK (0x1U) #define SYSCON_FMCFLUSH_FLUSH_SHIFT (0U) +/*! FLUSH - Flush control + * 0b1..Flush the FMC buffer contents. + * 0b0..No action is performed. + */ #define SYSCON_FMCFLUSH_FLUSH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FMCFLUSH_FLUSH_SHIFT)) & SYSCON_FMCFLUSH_FLUSH_MASK) /*! @} */ /*! @name MCLKIO - MCLK control */ /*! @{ */ -#define SYSCON_MCLKIO_MCLKIO_MASK (0xFFFFFFFFU) + +#define SYSCON_MCLKIO_MCLKIO_MASK (0x1U) #define SYSCON_MCLKIO_MCLKIO_SHIFT (0U) /*! MCLKIO - MCLK control. - * 0b00000000000000000000000000000000..input mode. - * 0b00000000000000000000000000000001..output mode. + * 0b0..input mode. + * 0b1..output mode. */ #define SYSCON_MCLKIO_MCLKIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_MCLKIO_SHIFT)) & SYSCON_MCLKIO_MCLKIO_MASK) /*! @} */ -/*! @name USB1CLKCTRL - USB1 clock control */ +/*! @name USB1NEEDCLKCTRL - USB1 need clock control */ /*! @{ */ -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK (0x1U) -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT (0U) -/*! AP_HS_DEV_CLK - USB1 Device need_clock signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT (0U) +/*! AP_HS_DEV_NEEDCLK - USB1 Device need_clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. */ -#define SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_DEV_CLK_MASK) -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK (0x2U) -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT (1U) -/*! POL_HS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt:. - * 0b0..Falling edge of device need_clock triggers wake-up. - * 0b1..Rising edge of device need_clock triggers wake-up. +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT (1U) +/*! POL_HS_DEV_NEEDCLK - USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: + * 0b0..Falling edge of DEV_NEEDCLK triggers wake-up. + * 0b1..Rising edge of DEV_NEEDCLK triggers wake-up. */ -#define SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_DEV_CLK_MASK) -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK (0x4U) -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT (2U) -/*! AP_HS_HOST_CLK - USB1 Host need_clock signal control:. - * 0b0..Under hardware control. - * 0b1..Forced high. +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK (0x4U) +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT (2U) +/*! AP_HS_HOST_NEEDCLK - USB1 Host need clock signal control: + * 0b0..HOST_NEEDCLK is under hardware control. + * 0b1..HOST_NEEDCLK is forced high. */ -#define SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_HS_HOST_CLK_MASK) -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK (0x8U) -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT (3U) -/*! POL_HS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt: 0 - * Falling edge of device need_clock triggers wake-up. - * 0b0..Falling edge of device need_clock triggers wake-up. - * 0b1..Rising edge of device need_clock triggers wake-up. +#define SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_AP_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK (0x8U) +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT (3U) +/*! POL_HS_HOST_NEEDCLK - USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. + * 0b0..Falling edge of HOST_NEEDCLK triggers wake-up. + * 0b1..Rising edge of HOST_NEEDCLK triggers wake-up. */ -#define SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_HS_HOST_CLK_MASK) -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) -/*! HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active - * low) will result in exiting the low power mode; input to synchronous control logic:. - * 0b0..Forces USB1 PHY to wake-up. - * 0b1..Normal USB1 PHY behavior. +#define SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_POL_HS_HOST_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U) +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U) +/*! HS_DEV_WAKEUP_N - Software override of device controller PHY wake up logic. + * 0b0..Forces USB1_PHY to wake-up. + * 0b1..Normal USB1_PHY behavior. */ -#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK) +#define SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1NEEDCLKCTRL_HS_DEV_WAKEUP_N_MASK) /*! @} */ -/*! @name USB1CLKSTAT - USB1 clock status */ +/*! @name USB1NEEDCLKSTAT - USB1 need clock status */ /*! @{ */ -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U) -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U) -/*! DEV_NEED_CLKST - USB1 Device need_clock signal status:. - * 0b1..USB1 Device clock is high. - * 0b0..USB1 Device clock is low. - */ -#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK) -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U) -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U) -/*! HOST_NEED_CLKST - USB1 Host need_clock signal status:. - * 0b1..USB1 Host clock is high. - * 0b0..USB1 Host clock is low. - */ -#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK) -/*! @} */ -/*! @name FLASHBANKENABLE - Flash Banks control */ -/*! @{ */ -#define SYSCON_FLASHBANKENABLE_BANK0_MASK (0xFU) -#define SYSCON_FLASHBANKENABLE_BANK0_SHIFT (0U) -/*! BANK0 - Flash Bank0 control. - * 0b0000..Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased and programmed). +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK (0x1U) +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT (0U) +/*! DEV_NEEDCLK - USB1 Device need_clock signal status:. + * 0b1..DEV_NEEDCLK is high. + * 0b0..DEV_NEEDCLK is low. */ -#define SYSCON_FLASHBANKENABLE_BANK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK0_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK0_MASK) -#define SYSCON_FLASHBANKENABLE_BANK1_MASK (0xF0U) -#define SYSCON_FLASHBANKENABLE_BANK1_SHIFT (4U) -/*! BANK1 - Flash Bank1 control. - * 0b0000..Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased and programmed). +#define SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_DEV_NEEDCLK_MASK) + +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK (0x2U) +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT (1U) +/*! HOST_NEEDCLK - USB1 Host need_clock signal status:. + * 0b1..HOST_NEEDCLK is high. + * 0b0..HOST_NEEDCLK is low. */ -#define SYSCON_FLASHBANKENABLE_BANK1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK1_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK1_MASK) -#define SYSCON_FLASHBANKENABLE_BANK2_MASK (0xF00U) -#define SYSCON_FLASHBANKENABLE_BANK2_SHIFT (8U) -/*! BANK2 - Flash Bank2 control. - * 0b0000..Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - * 0b1010..1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased and programmed). - */ -#define SYSCON_FLASHBANKENABLE_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHBANKENABLE_BANK2_SHIFT)) & SYSCON_FLASHBANKENABLE_BANK2_MASK) +#define SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_SHIFT)) & SYSCON_USB1NEEDCLKSTAT_HOST_NEEDCLK_MASK) /*! @} */ /*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */ /*! @{ */ + #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U) #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U) /*! CCLK_DRV_PHASE - Programmable delay value by which cclk_in_drv is phase-shifted with regard to cclk_in. @@ -19433,6 +24289,7 @@ typedef struct { * 0b11..270 degree shift. */ #define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK) + #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU) #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U) /*! CCLK_SAMPLE_PHASE - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. @@ -19442,6 +24299,7 @@ typedef struct { * 0b11..270 degree shift. */ #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK) + #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U) #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U) /*! PHASE_ACTIVE - Enables the delays CCLK_DRV_PHASE and CCLK_SAMPLE_PHASE. @@ -19449,9 +24307,13 @@ typedef struct { * 0b1..Activates phase shift logic. When active, the clock divider is active and phase delays are enabled. */ #define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK) + #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U) #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U) +/*! CCLK_DRV_DELAY - Programmable delay value by which cclk_in_drv is delayed with regard to cclk_in. + */ #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK) + #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U) #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U) /*! CCLK_DRV_DELAY_ACTIVE - Enables drive delay, as controlled by the CCLK_DRV_DELAY field. @@ -19459,9 +24321,13 @@ typedef struct { * 0b0..Disable drive delay. */ #define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK) + #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U) #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U) +/*! CCLK_SAMPLE_DELAY - Programmable delay value by which cclk_in_sample is delayed with regard to cclk_in. + */ #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK) + #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U) #define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U) /*! CCLK_SAMPLE_DELAY_ACTIVE - Enables sample delay, as controlled by the CCLK_SAMPLE_DELAY field. @@ -19473,15 +24339,25 @@ typedef struct { /*! @name PLL1CTRL - PLL1 550m control */ /*! @{ */ + #define SYSCON_PLL1CTRL_SELR_MASK (0xFU) #define SYSCON_PLL1CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ #define SYSCON_PLL1CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELR_SHIFT)) & SYSCON_PLL1CTRL_SELR_MASK) + #define SYSCON_PLL1CTRL_SELI_MASK (0x3F0U) #define SYSCON_PLL1CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ #define SYSCON_PLL1CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELI_SHIFT)) & SYSCON_PLL1CTRL_SELI_MASK) + #define SYSCON_PLL1CTRL_SELP_MASK (0x7C00U) #define SYSCON_PLL1CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ #define SYSCON_PLL1CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_SELP_SHIFT)) & SYSCON_PLL1CTRL_SELP_MASK) + #define SYSCON_PLL1CTRL_BYPASSPLL_MASK (0x8000U) #define SYSCON_PLL1CTRL_BYPASSPLL_SHIFT (15U) /*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). @@ -19489,6 +24365,7 @@ typedef struct { * 0b0..use PLL. */ #define SYSCON_PLL1CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPLL_MASK) + #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK (0x10000U) #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT (16U) /*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. @@ -19496,9 +24373,13 @@ typedef struct { * 0b0..use the divide-by-2 divider in the post-divider. */ #define SYSCON_PLL1CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) + #define SYSCON_PLL1CTRL_LIMUPOFF_MASK (0x20000U) #define SYSCON_PLL1CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ #define SYSCON_PLL1CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL1CTRL_LIMUPOFF_MASK) + #define SYSCON_PLL1CTRL_BWDIRECT_MASK (0x40000U) #define SYSCON_PLL1CTRL_BWDIRECT_SHIFT (18U) /*! BWDIRECT - control of the bandwidth of the PLL. @@ -19506,6 +24387,7 @@ typedef struct { * 0b0..the bandwidth is changed synchronously with the feedback-divider. */ #define SYSCON_PLL1CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL1CTRL_BWDIRECT_MASK) + #define SYSCON_PLL1CTRL_BYPASSPREDIV_MASK (0x80000U) #define SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT (19U) /*! BYPASSPREDIV - bypass of the pre-divider. @@ -19513,6 +24395,7 @@ typedef struct { * 0b0..use the pre-divider. */ #define SYSCON_PLL1CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) + #define SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK (0x100000U) #define SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT (20U) /*! BYPASSPOSTDIV - bypass of the post-divider. @@ -19520,6 +24403,7 @@ typedef struct { * 0b0..use the post-divider. */ #define SYSCON_PLL1CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) + #define SYSCON_PLL1CTRL_CLKEN_MASK (0x200000U) #define SYSCON_PLL1CTRL_CLKEN_SHIFT (21U) /*! CLKEN - enable the output clock. @@ -19527,12 +24411,19 @@ typedef struct { * 0b0..Disable the output clock. */ #define SYSCON_PLL1CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_CLKEN_SHIFT)) & SYSCON_PLL1CTRL_CLKEN_MASK) + #define SYSCON_PLL1CTRL_FRMEN_MASK (0x400000U) #define SYSCON_PLL1CTRL_FRMEN_SHIFT (22U) +/*! FRMEN - 1: free running mode. + */ #define SYSCON_PLL1CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMEN_SHIFT)) & SYSCON_PLL1CTRL_FRMEN_MASK) + #define SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK (0x800000U) #define SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable = 1 after the PLL output frequency is stable. + */ #define SYSCON_PLL1CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL1CTRL_FRMCLKSTABLE_MASK) + #define SYSCON_PLL1CTRL_SKEWEN_MASK (0x1000000U) #define SYSCON_PLL1CTRL_SKEWEN_SHIFT (24U) /*! SKEWEN - Skew mode. @@ -19544,64 +24435,107 @@ typedef struct { /*! @name PLL1STAT - PLL1 550m status */ /*! @{ */ + #define SYSCON_PLL1STAT_LOCK_MASK (0x1U) #define SYSCON_PLL1STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ #define SYSCON_PLL1STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_LOCK_SHIFT)) & SYSCON_PLL1STAT_LOCK_MASK) + #define SYSCON_PLL1STAT_PREDIVACK_MASK (0x2U) #define SYSCON_PLL1STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ #define SYSCON_PLL1STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_PREDIVACK_SHIFT)) & SYSCON_PLL1STAT_PREDIVACK_MASK) + #define SYSCON_PLL1STAT_FEEDDIVACK_MASK (0x4U) #define SYSCON_PLL1STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ #define SYSCON_PLL1STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL1STAT_FEEDDIVACK_MASK) + #define SYSCON_PLL1STAT_POSTDIVACK_MASK (0x8U) #define SYSCON_PLL1STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ #define SYSCON_PLL1STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL1STAT_POSTDIVACK_MASK) + #define SYSCON_PLL1STAT_FRMDET_MASK (0x10U) #define SYSCON_PLL1STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ #define SYSCON_PLL1STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1STAT_FRMDET_SHIFT)) & SYSCON_PLL1STAT_FRMDET_MASK) /*! @} */ /*! @name PLL1NDEC - PLL1 550m N divider */ /*! @{ */ + #define SYSCON_PLL1NDEC_NDIV_MASK (0xFFU) #define SYSCON_PLL1NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ #define SYSCON_PLL1NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NDIV_SHIFT)) & SYSCON_PLL1NDEC_NDIV_MASK) + #define SYSCON_PLL1NDEC_NREQ_MASK (0x100U) #define SYSCON_PLL1NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ #define SYSCON_PLL1NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1NDEC_NREQ_SHIFT)) & SYSCON_PLL1NDEC_NREQ_MASK) /*! @} */ /*! @name PLL1MDEC - PLL1 550m M divider */ /*! @{ */ + #define SYSCON_PLL1MDEC_MDIV_MASK (0xFFFFU) #define SYSCON_PLL1MDEC_MDIV_SHIFT (0U) +/*! MDIV - feedback divider divider ratio (M-divider). + */ #define SYSCON_PLL1MDEC_MDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MDIV_SHIFT)) & SYSCON_PLL1MDEC_MDIV_MASK) + #define SYSCON_PLL1MDEC_MREQ_MASK (0x10000U) #define SYSCON_PLL1MDEC_MREQ_SHIFT (16U) +/*! MREQ - feedback ratio change request. + */ #define SYSCON_PLL1MDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1MDEC_MREQ_SHIFT)) & SYSCON_PLL1MDEC_MREQ_MASK) /*! @} */ /*! @name PLL1PDEC - PLL1 550m P divider */ /*! @{ */ + #define SYSCON_PLL1PDEC_PDIV_MASK (0x1FU) #define SYSCON_PLL1PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ #define SYSCON_PLL1PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PDIV_SHIFT)) & SYSCON_PLL1PDEC_PDIV_MASK) + #define SYSCON_PLL1PDEC_PREQ_MASK (0x20U) #define SYSCON_PLL1PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ #define SYSCON_PLL1PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL1PDEC_PREQ_SHIFT)) & SYSCON_PLL1PDEC_PREQ_MASK) /*! @} */ /*! @name PLL0CTRL - PLL0 550m control */ /*! @{ */ + #define SYSCON_PLL0CTRL_SELR_MASK (0xFU) #define SYSCON_PLL0CTRL_SELR_SHIFT (0U) +/*! SELR - Bandwidth select R value. + */ #define SYSCON_PLL0CTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELR_SHIFT)) & SYSCON_PLL0CTRL_SELR_MASK) + #define SYSCON_PLL0CTRL_SELI_MASK (0x3F0U) #define SYSCON_PLL0CTRL_SELI_SHIFT (4U) +/*! SELI - Bandwidth select I value. + */ #define SYSCON_PLL0CTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELI_SHIFT)) & SYSCON_PLL0CTRL_SELI_MASK) + #define SYSCON_PLL0CTRL_SELP_MASK (0x7C00U) #define SYSCON_PLL0CTRL_SELP_SHIFT (10U) +/*! SELP - Bandwidth select P value. + */ #define SYSCON_PLL0CTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_SELP_SHIFT)) & SYSCON_PLL0CTRL_SELP_MASK) + #define SYSCON_PLL0CTRL_BYPASSPLL_MASK (0x8000U) #define SYSCON_PLL0CTRL_BYPASSPLL_SHIFT (15U) /*! BYPASSPLL - Bypass PLL input clock is sent directly to the PLL output (default). @@ -19609,6 +24543,7 @@ typedef struct { * 0b0..use PLL. */ #define SYSCON_PLL0CTRL_BYPASSPLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPLL_MASK) + #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK (0x10000U) #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT (16U) /*! BYPASSPOSTDIV2 - bypass of the divide-by-2 divider in the post-divider. @@ -19616,9 +24551,13 @@ typedef struct { * 0b0..use the divide-by-2 divider in the post-divider. */ #define SYSCON_PLL0CTRL_BYPASSPOSTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV2_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + #define SYSCON_PLL0CTRL_LIMUPOFF_MASK (0x20000U) #define SYSCON_PLL0CTRL_LIMUPOFF_SHIFT (17U) +/*! LIMUPOFF - limup_off = 1 in spread spectrum and fractional PLL applications. + */ #define SYSCON_PLL0CTRL_LIMUPOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT)) & SYSCON_PLL0CTRL_LIMUPOFF_MASK) + #define SYSCON_PLL0CTRL_BWDIRECT_MASK (0x40000U) #define SYSCON_PLL0CTRL_BWDIRECT_SHIFT (18U) /*! BWDIRECT - Control of the bandwidth of the PLL. @@ -19626,6 +24565,7 @@ typedef struct { * 0b0..the bandwidth is changed synchronously with the feedback-divider. */ #define SYSCON_PLL0CTRL_BWDIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BWDIRECT_SHIFT)) & SYSCON_PLL0CTRL_BWDIRECT_MASK) + #define SYSCON_PLL0CTRL_BYPASSPREDIV_MASK (0x80000U) #define SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT (19U) /*! BYPASSPREDIV - bypass of the pre-divider. @@ -19633,6 +24573,7 @@ typedef struct { * 0b0..use the pre-divider. */ #define SYSCON_PLL0CTRL_BYPASSPREDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) + #define SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK (0x100000U) #define SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT (20U) /*! BYPASSPOSTDIV - bypass of the post-divider. @@ -19640,6 +24581,7 @@ typedef struct { * 0b0..use the post-divider. */ #define SYSCON_PLL0CTRL_BYPASSPOSTDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT)) & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) + #define SYSCON_PLL0CTRL_CLKEN_MASK (0x200000U) #define SYSCON_PLL0CTRL_CLKEN_SHIFT (21U) /*! CLKEN - enable the output clock. @@ -19647,6 +24589,7 @@ typedef struct { * 0b0..disable the output clock. */ #define SYSCON_PLL0CTRL_CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_CLKEN_SHIFT)) & SYSCON_PLL0CTRL_CLKEN_MASK) + #define SYSCON_PLL0CTRL_FRMEN_MASK (0x400000U) #define SYSCON_PLL0CTRL_FRMEN_SHIFT (22U) /*! FRMEN - free running mode. @@ -19654,9 +24597,13 @@ typedef struct { * 0b0..free running mode is disable. */ #define SYSCON_PLL0CTRL_FRMEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMEN_SHIFT)) & SYSCON_PLL0CTRL_FRMEN_MASK) + #define SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK (0x800000U) #define SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT (23U) +/*! FRMCLKSTABLE - free running mode clockstable: Warning: Only make frm_clockstable =1 after the PLL output frequency is stable. + */ #define SYSCON_PLL0CTRL_FRMCLKSTABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0CTRL_FRMCLKSTABLE_SHIFT)) & SYSCON_PLL0CTRL_FRMCLKSTABLE_MASK) + #define SYSCON_PLL0CTRL_SKEWEN_MASK (0x1000000U) #define SYSCON_PLL0CTRL_SKEWEN_SHIFT (24U) /*! SKEWEN - skew mode. @@ -19668,786 +24615,169 @@ typedef struct { /*! @name PLL0STAT - PLL0 550m status */ /*! @{ */ + #define SYSCON_PLL0STAT_LOCK_MASK (0x1U) #define SYSCON_PLL0STAT_LOCK_SHIFT (0U) +/*! LOCK - lock detector output (active high) Warning: The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. + */ #define SYSCON_PLL0STAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_LOCK_SHIFT)) & SYSCON_PLL0STAT_LOCK_MASK) + #define SYSCON_PLL0STAT_PREDIVACK_MASK (0x2U) #define SYSCON_PLL0STAT_PREDIVACK_SHIFT (1U) +/*! PREDIVACK - pre-divider ratio change acknowledge. + */ #define SYSCON_PLL0STAT_PREDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_PREDIVACK_SHIFT)) & SYSCON_PLL0STAT_PREDIVACK_MASK) + #define SYSCON_PLL0STAT_FEEDDIVACK_MASK (0x4U) #define SYSCON_PLL0STAT_FEEDDIVACK_SHIFT (2U) +/*! FEEDDIVACK - feedback divider ratio change acknowledge. + */ #define SYSCON_PLL0STAT_FEEDDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FEEDDIVACK_SHIFT)) & SYSCON_PLL0STAT_FEEDDIVACK_MASK) + #define SYSCON_PLL0STAT_POSTDIVACK_MASK (0x8U) #define SYSCON_PLL0STAT_POSTDIVACK_SHIFT (3U) +/*! POSTDIVACK - post-divider ratio change acknowledge. + */ #define SYSCON_PLL0STAT_POSTDIVACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_POSTDIVACK_SHIFT)) & SYSCON_PLL0STAT_POSTDIVACK_MASK) + #define SYSCON_PLL0STAT_FRMDET_MASK (0x10U) #define SYSCON_PLL0STAT_FRMDET_SHIFT (4U) +/*! FRMDET - free running detector output (active high). + */ #define SYSCON_PLL0STAT_FRMDET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0STAT_FRMDET_SHIFT)) & SYSCON_PLL0STAT_FRMDET_MASK) /*! @} */ /*! @name PLL0NDEC - PLL0 550m N divider */ /*! @{ */ + #define SYSCON_PLL0NDEC_NDIV_MASK (0xFFU) #define SYSCON_PLL0NDEC_NDIV_SHIFT (0U) +/*! NDIV - pre-divider divider ratio (N-divider). + */ #define SYSCON_PLL0NDEC_NDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NDIV_SHIFT)) & SYSCON_PLL0NDEC_NDIV_MASK) + #define SYSCON_PLL0NDEC_NREQ_MASK (0x100U) #define SYSCON_PLL0NDEC_NREQ_SHIFT (8U) +/*! NREQ - pre-divider ratio change request. + */ #define SYSCON_PLL0NDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0NDEC_NREQ_SHIFT)) & SYSCON_PLL0NDEC_NREQ_MASK) /*! @} */ /*! @name PLL0PDEC - PLL0 550m P divider */ /*! @{ */ + #define SYSCON_PLL0PDEC_PDIV_MASK (0x1FU) #define SYSCON_PLL0PDEC_PDIV_SHIFT (0U) +/*! PDIV - post-divider divider ratio (P-divider) + */ #define SYSCON_PLL0PDEC_PDIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PDIV_SHIFT)) & SYSCON_PLL0PDEC_PDIV_MASK) + #define SYSCON_PLL0PDEC_PREQ_MASK (0x20U) #define SYSCON_PLL0PDEC_PREQ_SHIFT (5U) +/*! PREQ - feedback ratio change request. + */ #define SYSCON_PLL0PDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0PDEC_PREQ_SHIFT)) & SYSCON_PLL0PDEC_PREQ_MASK) /*! @} */ /*! @name PLL0SSCG0 - PLL0 Spread Spectrum Wrapper control register 0 */ /*! @{ */ + #define SYSCON_PLL0SSCG0_MD_LBS_MASK (0xFFFFFFFFU) #define SYSCON_PLL0SSCG0_MD_LBS_SHIFT (0U) +/*! MD_LBS - input word of the wrapper bit 31 to 0. + */ #define SYSCON_PLL0SSCG0_MD_LBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG0_MD_LBS_SHIFT)) & SYSCON_PLL0SSCG0_MD_LBS_MASK) /*! @} */ /*! @name PLL0SSCG1 - PLL0 Spread Spectrum Wrapper control register 1 */ /*! @{ */ + #define SYSCON_PLL0SSCG1_MD_MBS_MASK (0x1U) #define SYSCON_PLL0SSCG1_MD_MBS_SHIFT (0U) +/*! MD_MBS - input word of the wrapper bit 32. + */ #define SYSCON_PLL0SSCG1_MD_MBS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_MBS_SHIFT)) & SYSCON_PLL0SSCG1_MD_MBS_MASK) + #define SYSCON_PLL0SSCG1_MD_REQ_MASK (0x2U) #define SYSCON_PLL0SSCG1_MD_REQ_SHIFT (1U) +/*! MD_REQ - md change request. + */ #define SYSCON_PLL0SSCG1_MD_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MD_REQ_SHIFT)) & SYSCON_PLL0SSCG1_MD_REQ_MASK) + #define SYSCON_PLL0SSCG1_MF_MASK (0x1CU) #define SYSCON_PLL0SSCG1_MF_SHIFT (2U) +/*! MF - programmable modulation frequency fm = Fref/Nss mf[2:0] = 000 => Nss=512 (fm ~ 3. + */ #define SYSCON_PLL0SSCG1_MF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MF_SHIFT)) & SYSCON_PLL0SSCG1_MF_MASK) + #define SYSCON_PLL0SSCG1_MR_MASK (0xE0U) #define SYSCON_PLL0SSCG1_MR_SHIFT (5U) +/*! MR - programmable frequency modulation depth Dfmodpk-pk = Fref*kss/Fcco = kss/(2*md[32:25]dec) + * mr[2:0] = 000 => kss = 0 (no spread spectrum) mr[2:0] = 001 => kss ~ 1 mr[2:0] = 010 => kss ~ 1. + */ #define SYSCON_PLL0SSCG1_MR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MR_SHIFT)) & SYSCON_PLL0SSCG1_MR_MASK) + #define SYSCON_PLL0SSCG1_MC_MASK (0x300U) #define SYSCON_PLL0SSCG1_MC_SHIFT (8U) +/*! MC - modulation waveform control Compensation for low pass filtering of the PLL to get a + * triangular modulation at the output of the PLL, giving a flat frequency spectrum. + */ #define SYSCON_PLL0SSCG1_MC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MC_SHIFT)) & SYSCON_PLL0SSCG1_MC_MASK) + #define SYSCON_PLL0SSCG1_MDIV_EXT_MASK (0x3FFFC00U) #define SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT (10U) +/*! MDIV_EXT - to select an external mdiv value. + */ #define SYSCON_PLL0SSCG1_MDIV_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT)) & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) + #define SYSCON_PLL0SSCG1_MREQ_MASK (0x4000000U) #define SYSCON_PLL0SSCG1_MREQ_SHIFT (26U) +/*! MREQ - to select an external mreq value. + */ #define SYSCON_PLL0SSCG1_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_MREQ_SHIFT)) & SYSCON_PLL0SSCG1_MREQ_MASK) + #define SYSCON_PLL0SSCG1_DITHER_MASK (0x8000000U) #define SYSCON_PLL0SSCG1_DITHER_SHIFT (27U) +/*! DITHER - dithering between two modulation frequencies in a random way or in a pseudo random way + * (white noise), in order to decrease the probability that the modulated waveform will occur + * with the same phase on a particular point on the screen. + */ #define SYSCON_PLL0SSCG1_DITHER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_DITHER_SHIFT)) & SYSCON_PLL0SSCG1_DITHER_MASK) + #define SYSCON_PLL0SSCG1_SEL_EXT_MASK (0x10000000U) #define SYSCON_PLL0SSCG1_SEL_EXT_SHIFT (28U) +/*! SEL_EXT - to select mdiv_ext and mreq_ext sel_ext = 0: mdiv ~ md[32:0], mreq = 1 sel_ext = 1 : mdiv = mdiv_ext, mreq = mreq_ext. + */ #define SYSCON_PLL0SSCG1_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)) & SYSCON_PLL0SSCG1_SEL_EXT_MASK) /*! @} */ -/*! @name EFUSECLKCTRL - eFUSE controller clock enable */ +/*! @name FUNCRETENTIONCTRL - Functional retention control register */ /*! @{ */ -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK (0x1U) -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT (0U) -#define SYSCON_EFUSECLKCTRL_EFUSECLKENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EFUSECLKCTRL_EFUSECLKENA_SHIFT)) & SYSCON_EFUSECLKCTRL_EFUSECLKENA_MASK) -/*! @} */ -/*! @name STARTER - Start logic wake-up enable register */ -/*! @{ */ -#define SYSCON_STARTER_GPIO_INT04_MASK (0x1U) -#define SYSCON_STARTER_GPIO_INT04_SHIFT (0U) -/*! GPIO_INT04 - GPIO_INT04 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK (0x1U) +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT (0U) +/*! FUNCRETENA - functional retention in power down only. + * 0b1..enable functional retention. + * 0b0..disable functional retention. */ -#define SYSCON_STARTER_GPIO_INT04(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT04_SHIFT)) & SYSCON_STARTER_GPIO_INT04_MASK) -#define SYSCON_STARTER_SYS_MASK (0x1U) -#define SYSCON_STARTER_SYS_SHIFT (0U) -/*! SYS - SYS interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SYS_SHIFT)) & SYSCON_STARTER_SYS_MASK) -#define SYSCON_STARTER_GPIO_INT05_MASK (0x2U) -#define SYSCON_STARTER_GPIO_INT05_SHIFT (1U) -/*! GPIO_INT05 - GPIO_INT05 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT05(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT05_SHIFT)) & SYSCON_STARTER_GPIO_INT05_MASK) -#define SYSCON_STARTER_SDMA0_MASK (0x2U) -#define SYSCON_STARTER_SDMA0_SHIFT (1U) -/*! SDMA0 - SDMA0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA0_SHIFT)) & SYSCON_STARTER_SDMA0_MASK) -#define SYSCON_STARTER_GINT0_MASK (0x4U) -#define SYSCON_STARTER_GINT0_SHIFT (2U) -/*! GINT0 - GINT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK) -#define SYSCON_STARTER_GPIO_INT06_MASK (0x4U) -#define SYSCON_STARTER_GPIO_INT06_SHIFT (2U) -/*! GPIO_INT06 - GPIO_INT06 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT06(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT06_SHIFT)) & SYSCON_STARTER_GPIO_INT06_MASK) -#define SYSCON_STARTER_GINT1_MASK (0x8U) -#define SYSCON_STARTER_GINT1_SHIFT (3U) -/*! GINT1 - GINT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK) -#define SYSCON_STARTER_GPIO_INT07_MASK (0x8U) -#define SYSCON_STARTER_GPIO_INT07_SHIFT (3U) -/*! GPIO_INT07 - GPIO_INT07 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_GPIO_INT07(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GPIO_INT07_SHIFT)) & SYSCON_STARTER_GPIO_INT07_MASK) -#define SYSCON_STARTER_CTIMER2_MASK (0x10U) -#define SYSCON_STARTER_CTIMER2_SHIFT (4U) -/*! CTIMER2 - CTIMER2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK) -#define SYSCON_STARTER_PIO_INT0_MASK (0x10U) -#define SYSCON_STARTER_PIO_INT0_SHIFT (4U) -/*! PIO_INT0 - PIO_INT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT0_SHIFT)) & SYSCON_STARTER_PIO_INT0_MASK) -#define SYSCON_STARTER_CTIMER4_MASK (0x20U) -#define SYSCON_STARTER_CTIMER4_SHIFT (5U) -/*! CTIMER4 - CTIMER4 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK) -#define SYSCON_STARTER_PIO_INT1_MASK (0x20U) -#define SYSCON_STARTER_PIO_INT1_SHIFT (5U) -/*! PIO_INT1 - PIO_INT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT1_SHIFT)) & SYSCON_STARTER_PIO_INT1_MASK) -#define SYSCON_STARTER_OS_EVENT_MASK (0x40U) -#define SYSCON_STARTER_OS_EVENT_SHIFT (6U) -/*! OS_EVENT - OS_EVENT interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_OS_EVENT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_OS_EVENT_SHIFT)) & SYSCON_STARTER_OS_EVENT_MASK) -#define SYSCON_STARTER_PIO_INT2_MASK (0x40U) -#define SYSCON_STARTER_PIO_INT2_SHIFT (6U) -/*! PIO_INT2 - PIO_INT2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT2_SHIFT)) & SYSCON_STARTER_PIO_INT2_MASK) -#define SYSCON_STARTER_PIO_INT3_MASK (0x80U) -#define SYSCON_STARTER_PIO_INT3_SHIFT (7U) -/*! PIO_INT3 - PIO_INT3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PIO_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIO_INT3_SHIFT)) & SYSCON_STARTER_PIO_INT3_MASK) -#define SYSCON_STARTER_UTICK0_MASK (0x100U) -#define SYSCON_STARTER_UTICK0_SHIFT (8U) -/*! UTICK0 - UTICK0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_UTICK0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK0_SHIFT)) & SYSCON_STARTER_UTICK0_MASK) -#define SYSCON_STARTER_MRT0_MASK (0x200U) -#define SYSCON_STARTER_MRT0_SHIFT (9U) -/*! MRT0 - MRT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_MRT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT0_SHIFT)) & SYSCON_STARTER_MRT0_MASK) -#define SYSCON_STARTER_CTIMER0_MASK (0x400U) -#define SYSCON_STARTER_CTIMER0_SHIFT (10U) -/*! CTIMER0 - CTIMER0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK) -#define SYSCON_STARTER_SDIO_MASK (0x400U) -#define SYSCON_STARTER_SDIO_SHIFT (10U) -/*! SDIO - SDIO interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDIO_SHIFT)) & SYSCON_STARTER_SDIO_MASK) -#define SYSCON_STARTER_CTIMER1_MASK (0x800U) -#define SYSCON_STARTER_CTIMER1_SHIFT (11U) -/*! CTIMER1 - CTIMER1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK) -#define SYSCON_STARTER_SCT0_MASK (0x1000U) -#define SYSCON_STARTER_SCT0_SHIFT (12U) -/*! SCT0 - SCT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK) -#define SYSCON_STARTER_CTIMER3_MASK (0x2000U) -#define SYSCON_STARTER_CTIMER3_SHIFT (13U) -/*! CTIMER3 - CTIMER3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK) -#define SYSCON_STARTER_FLEXINT0_MASK (0x4000U) -#define SYSCON_STARTER_FLEXINT0_SHIFT (14U) -/*! FLEXINT0 - FLEXINT0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT0_SHIFT)) & SYSCON_STARTER_FLEXINT0_MASK) -#define SYSCON_STARTER_FLEXINT1_MASK (0x8000U) -#define SYSCON_STARTER_FLEXINT1_SHIFT (15U) -/*! FLEXINT1 - FLEXINT1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT1_SHIFT)) & SYSCON_STARTER_FLEXINT1_MASK) -#define SYSCON_STARTER_USB1_MASK (0x8000U) -#define SYSCON_STARTER_USB1_SHIFT (15U) -/*! USB1 - USB1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK) -#define SYSCON_STARTER_FLEXINT2_MASK (0x10000U) -#define SYSCON_STARTER_FLEXINT2_SHIFT (16U) -/*! FLEXINT2 - FLEXINT2 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT2_SHIFT)) & SYSCON_STARTER_FLEXINT2_MASK) -#define SYSCON_STARTER_USB1_NEEDCLK_MASK (0x10000U) -#define SYSCON_STARTER_USB1_NEEDCLK_SHIFT (16U) -/*! USB1_NEEDCLK - USB1_NEEDCLK interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB1_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB1_NEEDCLK_MASK) -#define SYSCON_STARTER_FLEXINT3_MASK (0x20000U) -#define SYSCON_STARTER_FLEXINT3_SHIFT (17U) -/*! FLEXINT3 - FLEXINT3 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT3_SHIFT)) & SYSCON_STARTER_FLEXINT3_MASK) -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK (0x20000U) -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT (17U) -/*! SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_HYPERVISOR_CALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_HYPERVISOR_CALL_SHIFT)) & SYSCON_STARTER_SEC_HYPERVISOR_CALL_MASK) -#define SYSCON_STARTER_FLEXINT4_MASK (0x40000U) -#define SYSCON_STARTER_FLEXINT4_SHIFT (18U) -/*! FLEXINT4 - FLEXINT4 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT4_SHIFT)) & SYSCON_STARTER_FLEXINT4_MASK) -#define SYSCON_STARTER_SEC_GPIO_INT00_MASK (0x40000U) -#define SYSCON_STARTER_SEC_GPIO_INT00_SHIFT (18U) -/*! SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_GPIO_INT00(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT00_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT00_MASK) -#define SYSCON_STARTER_FLEXINT5_MASK (0x80000U) -#define SYSCON_STARTER_FLEXINT5_SHIFT (19U) -/*! FLEXINT5 - FLEXINT5 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT5_SHIFT)) & SYSCON_STARTER_FLEXINT5_MASK) -#define SYSCON_STARTER_SEC_GPIO_INT01_MASK (0x80000U) -#define SYSCON_STARTER_SEC_GPIO_INT01_SHIFT (19U) -/*! SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_GPIO_INT01(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_GPIO_INT01_SHIFT)) & SYSCON_STARTER_SEC_GPIO_INT01_MASK) -#define SYSCON_STARTER_FLEXINT6_MASK (0x100000U) -#define SYSCON_STARTER_FLEXINT6_SHIFT (20U) -/*! FLEXINT6 - FLEXINT6 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT6_SHIFT)) & SYSCON_STARTER_FLEXINT6_MASK) -#define SYSCON_STARTER_PLU_MASK (0x100000U) -#define SYSCON_STARTER_PLU_SHIFT (20U) -/*! PLU - PLU interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PLU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PLU_SHIFT)) & SYSCON_STARTER_PLU_MASK) -#define SYSCON_STARTER_FLEXINT7_MASK (0x200000U) -#define SYSCON_STARTER_FLEXINT7_SHIFT (21U) -/*! FLEXINT7 - FLEXINT7 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_FLEXINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXINT7_SHIFT)) & SYSCON_STARTER_FLEXINT7_MASK) -#define SYSCON_STARTER_SEC_VIO_MASK (0x200000U) -#define SYSCON_STARTER_SEC_VIO_SHIFT (21U) -/*! SEC_VIO - SEC_VIO interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SEC_VIO_SHIFT)) & SYSCON_STARTER_SEC_VIO_MASK) -#define SYSCON_STARTER_ADC0_MASK (0x400000U) -#define SYSCON_STARTER_ADC0_SHIFT (22U) -/*! ADC0 - ADC0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SHIFT)) & SYSCON_STARTER_ADC0_MASK) -#define SYSCON_STARTER_SHA_MASK (0x400000U) -#define SYSCON_STARTER_SHA_SHIFT (22U) -/*! SHA - SHA interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SHA_SHIFT)) & SYSCON_STARTER_SHA_MASK) -#define SYSCON_STARTER_CASER_MASK (0x800000U) -#define SYSCON_STARTER_CASER_SHIFT (23U) -/*! CASER - CASER interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_CASER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CASER_SHIFT)) & SYSCON_STARTER_CASER_MASK) -#define SYSCON_STARTER_ADC0_THCMP_OVR_MASK (0x1000000U) -#define SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT (24U) -/*! ADC0_THCMP_OVR - ADC0_THCMP_OVR interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_ADC0_THCMP_OVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_OVR_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_OVR_MASK) -#define SYSCON_STARTER_QDDKEY_MASK (0x1000000U) -#define SYSCON_STARTER_QDDKEY_SHIFT (24U) -/*! QDDKEY - QDDKEY interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_QDDKEY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_QDDKEY_SHIFT)) & SYSCON_STARTER_QDDKEY_MASK) -#define SYSCON_STARTER_PQ_MASK (0x2000000U) -#define SYSCON_STARTER_PQ_SHIFT (25U) -/*! PQ - PQ interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_PQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PQ_SHIFT)) & SYSCON_STARTER_PQ_MASK) -#define SYSCON_STARTER_SDMA1_MASK (0x4000000U) -#define SYSCON_STARTER_SDMA1_SHIFT (26U) -/*! SDMA1 - SDMA1 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SDMA1_SHIFT)) & SYSCON_STARTER_SDMA1_MASK) -#define SYSCON_STARTER_LSPI_HS_MASK (0x8000000U) -#define SYSCON_STARTER_LSPI_HS_SHIFT (27U) -/*! LSPI_HS - LSPI_HS interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_LSPI_HS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_LSPI_HS_SHIFT)) & SYSCON_STARTER_LSPI_HS_MASK) -#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U) -#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U) -/*! USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK) -#define SYSCON_STARTER_USB0_MASK (0x10000000U) -#define SYSCON_STARTER_USB0_SHIFT (28U) -/*! USB0 - USB0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK) -#define SYSCON_STARTER_RTC_LITE0_MASK (0x20000000U) -#define SYSCON_STARTER_RTC_LITE0_SHIFT (29U) -/*! RTC_LITE0 - RTC_LITE0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_RTC_LITE0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_LITE0_SHIFT)) & SYSCON_STARTER_RTC_LITE0_MASK) -#define SYSCON_STARTER_EZH_ARCH_B0_MASK (0x40000000U) -#define SYSCON_STARTER_EZH_ARCH_B0_SHIFT (30U) -/*! EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_EZH_ARCH_B0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_EZH_ARCH_B0_SHIFT)) & SYSCON_STARTER_EZH_ARCH_B0_MASK) -#define SYSCON_STARTER_WAKEUPPADS_MASK (0x80000000U) -#define SYSCON_STARTER_WAKEUPPADS_SHIFT (31U) -#define SYSCON_STARTER_WAKEUPPADS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUPPADS_SHIFT)) & SYSCON_STARTER_WAKEUPPADS_MASK) -#define SYSCON_STARTER_WAKEUP_MAILBOX0_MASK (0x80000000U) -#define SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT (31U) -/*! WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up. - * 0b0..Wake-up disabled. - * 0b1..Wake-up enabled. - */ -#define SYSCON_STARTER_WAKEUP_MAILBOX0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WAKEUP_MAILBOX0_SHIFT)) & SYSCON_STARTER_WAKEUP_MAILBOX0_MASK) -/*! @} */ +#define SYSCON_FUNCRETENTIONCTRL_FUNCRETENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_FUNCRETENA_MASK) -/* The count of SYSCON_STARTER */ -#define SYSCON_STARTER_COUNT (2U) +#define SYSCON_FUNCRETENTIONCTRL_RET_START_MASK (0x3FFEU) +#define SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT (1U) +/*! RET_START - Start address divided by 4 inside SRAMX bank. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_START_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_START_MASK) -/*! @name STARTERSET - Set bits in STARTER */ -/*! @{ */ -#define SYSCON_STARTERSET_GPIO_INT04_SET_MASK (0x1U) -#define SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT (0U) -#define SYSCON_STARTERSET_GPIO_INT04_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT04_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT04_SET_MASK) -#define SYSCON_STARTERSET_SYS_SET_MASK (0x1U) -#define SYSCON_STARTERSET_SYS_SET_SHIFT (0U) -#define SYSCON_STARTERSET_SYS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SYS_SET_SHIFT)) & SYSCON_STARTERSET_SYS_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT05_SET_MASK (0x2U) -#define SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT (1U) -#define SYSCON_STARTERSET_GPIO_INT05_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT05_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT05_SET_MASK) -#define SYSCON_STARTERSET_SDMA0_SET_MASK (0x2U) -#define SYSCON_STARTERSET_SDMA0_SET_SHIFT (1U) -#define SYSCON_STARTERSET_SDMA0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA0_SET_SHIFT)) & SYSCON_STARTERSET_SDMA0_SET_MASK) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK (0x4U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT (2U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT0_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT06_SET_MASK (0x4U) -#define SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT (2U) -#define SYSCON_STARTERSET_GPIO_INT06_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT06_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT06_SET_MASK) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK (0x8U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT (3U) -#define SYSCON_STARTERSET_GPIO_GLOBALINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_GLOBALINT1_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT07_SET_MASK (0x8U) -#define SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT (3U) -#define SYSCON_STARTERSET_GPIO_INT07_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT07_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT07_SET_MASK) -#define SYSCON_STARTERSET_CTIMER2_SET_MASK (0x10U) -#define SYSCON_STARTERSET_CTIMER2_SET_SHIFT (4U) -#define SYSCON_STARTERSET_CTIMER2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER2_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER2_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT00_SET_MASK (0x10U) -#define SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT (4U) -#define SYSCON_STARTERSET_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT00_SET_MASK) -#define SYSCON_STARTERSET_CTIMER4_SET_MASK (0x20U) -#define SYSCON_STARTERSET_CTIMER4_SET_SHIFT (5U) -#define SYSCON_STARTERSET_CTIMER4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER4_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER4_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT01_SET_MASK (0x20U) -#define SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT (5U) -#define SYSCON_STARTERSET_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT01_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT02_SET_MASK (0x40U) -#define SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT (6U) -#define SYSCON_STARTERSET_GPIO_INT02_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT02_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT02_SET_MASK) -#define SYSCON_STARTERSET_OS_EVENT_SET_MASK (0x40U) -#define SYSCON_STARTERSET_OS_EVENT_SET_SHIFT (6U) -#define SYSCON_STARTERSET_OS_EVENT_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_OS_EVENT_SET_SHIFT)) & SYSCON_STARTERSET_OS_EVENT_SET_MASK) -#define SYSCON_STARTERSET_GPIO_INT03_SET_MASK (0x80U) -#define SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT (7U) -#define SYSCON_STARTERSET_GPIO_INT03_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_GPIO_INT03_SET_SHIFT)) & SYSCON_STARTERSET_GPIO_INT03_SET_MASK) -#define SYSCON_STARTERSET_UTICK0_SET_MASK (0x100U) -#define SYSCON_STARTERSET_UTICK0_SET_SHIFT (8U) -#define SYSCON_STARTERSET_UTICK0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_UTICK0_SET_SHIFT)) & SYSCON_STARTERSET_UTICK0_SET_MASK) -#define SYSCON_STARTERSET_MRT0_SET_MASK (0x200U) -#define SYSCON_STARTERSET_MRT0_SET_SHIFT (9U) -#define SYSCON_STARTERSET_MRT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_MRT0_SET_SHIFT)) & SYSCON_STARTERSET_MRT0_SET_MASK) -#define SYSCON_STARTERSET_CTIMER0_SET_MASK (0x400U) -#define SYSCON_STARTERSET_CTIMER0_SET_SHIFT (10U) -#define SYSCON_STARTERSET_CTIMER0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER0_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER0_SET_MASK) -#define SYSCON_STARTERSET_SDIO_SET_MASK (0x400U) -#define SYSCON_STARTERSET_SDIO_SET_SHIFT (10U) -#define SYSCON_STARTERSET_SDIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDIO_SET_SHIFT)) & SYSCON_STARTERSET_SDIO_SET_MASK) -#define SYSCON_STARTERSET_CTIMER1_SET_MASK (0x800U) -#define SYSCON_STARTERSET_CTIMER1_SET_SHIFT (11U) -#define SYSCON_STARTERSET_CTIMER1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER1_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER1_SET_MASK) -#define SYSCON_STARTERSET_SCT0_SET_MASK (0x1000U) -#define SYSCON_STARTERSET_SCT0_SET_SHIFT (12U) -#define SYSCON_STARTERSET_SCT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SCT0_SET_SHIFT)) & SYSCON_STARTERSET_SCT0_SET_MASK) -#define SYSCON_STARTERSET_CTIMER3_SET_MASK (0x2000U) -#define SYSCON_STARTERSET_CTIMER3_SET_SHIFT (13U) -#define SYSCON_STARTERSET_CTIMER3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CTIMER3_SET_SHIFT)) & SYSCON_STARTERSET_CTIMER3_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT0_SET_MASK (0x4000U) -#define SYSCON_STARTERSET_FLEXINT0_SET_SHIFT (14U) -#define SYSCON_STARTERSET_FLEXINT0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT0_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT0_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT1_SET_MASK (0x8000U) -#define SYSCON_STARTERSET_FLEXINT1_SET_SHIFT (15U) -#define SYSCON_STARTERSET_FLEXINT1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT1_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT1_SET_MASK) -#define SYSCON_STARTERSET_USB1_SET_MASK (0x8000U) -#define SYSCON_STARTERSET_USB1_SET_SHIFT (15U) -#define SYSCON_STARTERSET_USB1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_SET_SHIFT)) & SYSCON_STARTERSET_USB1_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT2_SET_MASK (0x10000U) -#define SYSCON_STARTERSET_FLEXINT2_SET_SHIFT (16U) -#define SYSCON_STARTERSET_FLEXINT2_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT2_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT2_SET_MASK) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK (0x10000U) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT (16U) -#define SYSCON_STARTERSET_USB1_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB1_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB1_NEEDCLK_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT3_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_FLEXINT3_SET_SHIFT (17U) -#define SYSCON_STARTERSET_FLEXINT3_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT3_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT3_SET_MASK) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK (0x20000U) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT (17U) -#define SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_SHIFT)) & SYSCON_STARTERSET_SEC_HYPERVISOR_CALL_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT4_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_FLEXINT4_SET_SHIFT (18U) -#define SYSCON_STARTERSET_FLEXINT4_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT4_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT4_SET_MASK) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK (0x40000U) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT (18U) -#define SYSCON_STARTERSET_SEC_GPIO_INT00_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT00_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT00_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT5_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_FLEXINT5_SET_SHIFT (19U) -#define SYSCON_STARTERSET_FLEXINT5_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT5_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT5_SET_MASK) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK (0x80000U) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT (19U) -#define SYSCON_STARTERSET_SEC_GPIO_INT01_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_GPIO_INT01_SET_SHIFT)) & SYSCON_STARTERSET_SEC_GPIO_INT01_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT6_SET_MASK (0x100000U) -#define SYSCON_STARTERSET_FLEXINT6_SET_SHIFT (20U) -#define SYSCON_STARTERSET_FLEXINT6_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT6_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT6_SET_MASK) -#define SYSCON_STARTERSET_PLU_SET_MASK (0x100000U) -#define SYSCON_STARTERSET_PLU_SET_SHIFT (20U) -#define SYSCON_STARTERSET_PLU_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PLU_SET_SHIFT)) & SYSCON_STARTERSET_PLU_SET_MASK) -#define SYSCON_STARTERSET_FLEXINT7_SET_MASK (0x200000U) -#define SYSCON_STARTERSET_FLEXINT7_SET_SHIFT (21U) -#define SYSCON_STARTERSET_FLEXINT7_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_FLEXINT7_SET_SHIFT)) & SYSCON_STARTERSET_FLEXINT7_SET_MASK) -#define SYSCON_STARTERSET_SEC_VIO_SET_MASK (0x200000U) -#define SYSCON_STARTERSET_SEC_VIO_SET_SHIFT (21U) -#define SYSCON_STARTERSET_SEC_VIO_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SEC_VIO_SET_SHIFT)) & SYSCON_STARTERSET_SEC_VIO_SET_MASK) -#define SYSCON_STARTERSET_ADC0_SET_MASK (0x400000U) -#define SYSCON_STARTERSET_ADC0_SET_SHIFT (22U) -#define SYSCON_STARTERSET_ADC0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_SET_MASK) -#define SYSCON_STARTERSET_SHA_SET_MASK (0x400000U) -#define SYSCON_STARTERSET_SHA_SET_SHIFT (22U) -#define SYSCON_STARTERSET_SHA_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SHA_SET_SHIFT)) & SYSCON_STARTERSET_SHA_SET_MASK) -#define SYSCON_STARTERSET_CASER_SET_MASK (0x800000U) -#define SYSCON_STARTERSET_CASER_SET_SHIFT (23U) -#define SYSCON_STARTERSET_CASER_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_CASER_SET_SHIFT)) & SYSCON_STARTERSET_CASER_SET_MASK) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK (0x1000000U) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT (24U) -#define SYSCON_STARTERSET_ADC0_THCMP_OVR_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_SHIFT)) & SYSCON_STARTERSET_ADC0_THCMP_OVR_SET_MASK) -#define SYSCON_STARTERSET_QDDKEY_SET_MASK (0x1000000U) -#define SYSCON_STARTERSET_QDDKEY_SET_SHIFT (24U) -#define SYSCON_STARTERSET_QDDKEY_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_QDDKEY_SET_SHIFT)) & SYSCON_STARTERSET_QDDKEY_SET_MASK) -#define SYSCON_STARTERSET_PQ_SET_MASK (0x2000000U) -#define SYSCON_STARTERSET_PQ_SET_SHIFT (25U) -#define SYSCON_STARTERSET_PQ_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_PQ_SET_SHIFT)) & SYSCON_STARTERSET_PQ_SET_MASK) -#define SYSCON_STARTERSET_SDMA1_SET_MASK (0x4000000U) -#define SYSCON_STARTERSET_SDMA1_SET_SHIFT (26U) -#define SYSCON_STARTERSET_SDMA1_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_SDMA1_SET_SHIFT)) & SYSCON_STARTERSET_SDMA1_SET_MASK) -#define SYSCON_STARTERSET_LSPI_HS_SET_MASK (0x8000000U) -#define SYSCON_STARTERSET_LSPI_HS_SET_SHIFT (27U) -#define SYSCON_STARTERSET_LSPI_HS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_LSPI_HS_SET_SHIFT)) & SYSCON_STARTERSET_LSPI_HS_SET_MASK) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK (0x8000000U) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT (27U) -#define SYSCON_STARTERSET_USB0_NEEDCLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_NEEDCLK_SET_SHIFT)) & SYSCON_STARTERSET_USB0_NEEDCLK_SET_MASK) -#define SYSCON_STARTERSET_USB0_SET_MASK (0x10000000U) -#define SYSCON_STARTERSET_USB0_SET_SHIFT (28U) -#define SYSCON_STARTERSET_USB0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_USB0_SET_SHIFT)) & SYSCON_STARTERSET_USB0_SET_MASK) -#define SYSCON_STARTERSET_RTC_LITE0_SET_MASK (0x20000000U) -#define SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT (29U) -#define SYSCON_STARTERSET_RTC_LITE0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_RTC_LITE0_SET_SHIFT)) & SYSCON_STARTERSET_RTC_LITE0_SET_MASK) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK (0x40000000U) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT (30U) -#define SYSCON_STARTERSET_EZH_ARCH_B0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_EZH_ARCH_B0_SET_SHIFT)) & SYSCON_STARTERSET_EZH_ARCH_B0_SET_MASK) -#define SYSCON_STARTERSET_WAKEUPPADS_SET_MASK (0x80000000U) -#define SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT (31U) -#define SYSCON_STARTERSET_WAKEUPPADS_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUPPADS_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUPPADS_SET_MASK) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK (0x80000000U) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT (31U) -#define SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_SHIFT)) & SYSCON_STARTERSET_WAKEUP_MAILBOX0_SET_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERSET */ -#define SYSCON_STARTERSET_COUNT (2U) - -/*! @name STARTERCLR - Clear bits in STARTER */ -/*! @{ */ -#define SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK (0x1U) -#define SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_GPIO_INT04_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT04_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT04_CLR_MASK) -#define SYSCON_STARTERCLR_SYS_CLR_MASK (0x1U) -#define SYSCON_STARTERCLR_SYS_CLR_SHIFT (0U) -#define SYSCON_STARTERCLR_SYS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SYS_CLR_SHIFT)) & SYSCON_STARTERCLR_SYS_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK (0x2U) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT (1U) -#define SYSCON_STARTERCLR_GPIO_INT05_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT05_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT05_CLR_MASK) -#define SYSCON_STARTERCLR_SDMA0_CLR_MASK (0x2U) -#define SYSCON_STARTERCLR_SDMA0_CLR_SHIFT (1U) -#define SYSCON_STARTERCLR_SDMA0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA0_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA0_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK (0x4U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT (2U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT0_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK (0x4U) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT (2U) -#define SYSCON_STARTERCLR_GPIO_INT06_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT06_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT06_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK (0x8U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT (3U) -#define SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_GLOBALINT1_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK (0x8U) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT (3U) -#define SYSCON_STARTERCLR_GPIO_INT07_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT07_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT07_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER2_CLR_MASK (0x10U) -#define SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT (4U) -#define SYSCON_STARTERCLR_CTIMER2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER2_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER2_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK (0x10U) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT (4U) -#define SYSCON_STARTERCLR_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT00_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER4_CLR_MASK (0x20U) -#define SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT (5U) -#define SYSCON_STARTERCLR_CTIMER4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER4_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER4_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK (0x20U) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT (5U) -#define SYSCON_STARTERCLR_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT01_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK (0x40U) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT (6U) -#define SYSCON_STARTERCLR_GPIO_INT02_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT02_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT02_CLR_MASK) -#define SYSCON_STARTERCLR_OS_EVENT_CLR_MASK (0x40U) -#define SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT (6U) -#define SYSCON_STARTERCLR_OS_EVENT_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_OS_EVENT_CLR_SHIFT)) & SYSCON_STARTERCLR_OS_EVENT_CLR_MASK) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK (0x80U) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT (7U) -#define SYSCON_STARTERCLR_GPIO_INT03_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_GPIO_INT03_CLR_SHIFT)) & SYSCON_STARTERCLR_GPIO_INT03_CLR_MASK) -#define SYSCON_STARTERCLR_UTICK0_CLR_MASK (0x100U) -#define SYSCON_STARTERCLR_UTICK0_CLR_SHIFT (8U) -#define SYSCON_STARTERCLR_UTICK0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_UTICK0_CLR_SHIFT)) & SYSCON_STARTERCLR_UTICK0_CLR_MASK) -#define SYSCON_STARTERCLR_MRT0_CLR_MASK (0x200U) -#define SYSCON_STARTERCLR_MRT0_CLR_SHIFT (9U) -#define SYSCON_STARTERCLR_MRT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_MRT0_CLR_SHIFT)) & SYSCON_STARTERCLR_MRT0_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER0_CLR_MASK (0x400U) -#define SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT (10U) -#define SYSCON_STARTERCLR_CTIMER0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER0_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER0_CLR_MASK) -#define SYSCON_STARTERCLR_SDIO_CLR_MASK (0x400U) -#define SYSCON_STARTERCLR_SDIO_CLR_SHIFT (10U) -#define SYSCON_STARTERCLR_SDIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SDIO_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER1_CLR_MASK (0x800U) -#define SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT (11U) -#define SYSCON_STARTERCLR_CTIMER1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER1_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER1_CLR_MASK) -#define SYSCON_STARTERCLR_SCT0_CLR_MASK (0x1000U) -#define SYSCON_STARTERCLR_SCT0_CLR_SHIFT (12U) -#define SYSCON_STARTERCLR_SCT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SCT0_CLR_SHIFT)) & SYSCON_STARTERCLR_SCT0_CLR_MASK) -#define SYSCON_STARTERCLR_CTIMER3_CLR_MASK (0x2000U) -#define SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT (13U) -#define SYSCON_STARTERCLR_CTIMER3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CTIMER3_CLR_SHIFT)) & SYSCON_STARTERCLR_CTIMER3_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT0_CLR_MASK (0x4000U) -#define SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT (14U) -#define SYSCON_STARTERCLR_FLEXINT0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT0_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT0_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT1_CLR_MASK (0x8000U) -#define SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT (15U) -#define SYSCON_STARTERCLR_FLEXINT1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT1_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT1_CLR_MASK) -#define SYSCON_STARTERCLR_USB1_CLR_MASK (0x8000U) -#define SYSCON_STARTERCLR_USB1_CLR_SHIFT (15U) -#define SYSCON_STARTERCLR_USB1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT2_CLR_MASK (0x10000U) -#define SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT (16U) -#define SYSCON_STARTERCLR_FLEXINT2_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT2_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT2_CLR_MASK) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK (0x10000U) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT (16U) -#define SYSCON_STARTERCLR_USB1_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB1_NEEDCLK_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT3_CLR_MASK (0x20000U) -#define SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT (17U) -#define SYSCON_STARTERCLR_FLEXINT3_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT3_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT3_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK (0x20000U) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT (17U) -#define SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_HYPERVISOR_CALL_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT4_CLR_MASK (0x40000U) -#define SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT (18U) -#define SYSCON_STARTERCLR_FLEXINT4_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT4_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT4_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK (0x40000U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT (18U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT00_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT5_CLR_MASK (0x80000U) -#define SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT (19U) -#define SYSCON_STARTERCLR_FLEXINT5_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT5_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT5_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK (0x80000U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT (19U) -#define SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_GPIO_INT01_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT6_CLR_MASK (0x100000U) -#define SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT (20U) -#define SYSCON_STARTERCLR_FLEXINT6_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT6_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT6_CLR_MASK) -#define SYSCON_STARTERCLR_PLU_CLR_MASK (0x100000U) -#define SYSCON_STARTERCLR_PLU_CLR_SHIFT (20U) -#define SYSCON_STARTERCLR_PLU_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PLU_CLR_SHIFT)) & SYSCON_STARTERCLR_PLU_CLR_MASK) -#define SYSCON_STARTERCLR_FLEXINT7_CLR_MASK (0x200000U) -#define SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT (21U) -#define SYSCON_STARTERCLR_FLEXINT7_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_FLEXINT7_CLR_SHIFT)) & SYSCON_STARTERCLR_FLEXINT7_CLR_MASK) -#define SYSCON_STARTERCLR_SEC_VIO_CLR_MASK (0x200000U) -#define SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT (21U) -#define SYSCON_STARTERCLR_SEC_VIO_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SEC_VIO_CLR_SHIFT)) & SYSCON_STARTERCLR_SEC_VIO_CLR_MASK) -#define SYSCON_STARTERCLR_ADC0_CLR_MASK (0x400000U) -#define SYSCON_STARTERCLR_ADC0_CLR_SHIFT (22U) -#define SYSCON_STARTERCLR_ADC0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_CLR_MASK) -#define SYSCON_STARTERCLR_SHA_CLR_MASK (0x400000U) -#define SYSCON_STARTERCLR_SHA_CLR_SHIFT (22U) -#define SYSCON_STARTERCLR_SHA_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SHA_CLR_SHIFT)) & SYSCON_STARTERCLR_SHA_CLR_MASK) -#define SYSCON_STARTERCLR_CASER_CLR_MASK (0x800000U) -#define SYSCON_STARTERCLR_CASER_CLR_SHIFT (23U) -#define SYSCON_STARTERCLR_CASER_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_CASER_CLR_SHIFT)) & SYSCON_STARTERCLR_CASER_CLR_MASK) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK (0x1000000U) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT (24U) -#define SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_SHIFT)) & SYSCON_STARTERCLR_ADC0_THCMP_OVR_CLR_MASK) -#define SYSCON_STARTERCLR_QDDKEY_CLR_MASK (0x1000000U) -#define SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT (24U) -#define SYSCON_STARTERCLR_QDDKEY_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_QDDKEY_CLR_SHIFT)) & SYSCON_STARTERCLR_QDDKEY_CLR_MASK) -#define SYSCON_STARTERCLR_PQ_CLR_MASK (0x2000000U) -#define SYSCON_STARTERCLR_PQ_CLR_SHIFT (25U) -#define SYSCON_STARTERCLR_PQ_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_PQ_CLR_SHIFT)) & SYSCON_STARTERCLR_PQ_CLR_MASK) -#define SYSCON_STARTERCLR_SDMA1_CLR_MASK (0x4000000U) -#define SYSCON_STARTERCLR_SDMA1_CLR_SHIFT (26U) -#define SYSCON_STARTERCLR_SDMA1_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_SDMA1_CLR_SHIFT)) & SYSCON_STARTERCLR_SDMA1_CLR_MASK) -#define SYSCON_STARTERCLR_LSPI_HS_CLR_MASK (0x8000000U) -#define SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT (27U) -#define SYSCON_STARTERCLR_LSPI_HS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_LSPI_HS_CLR_SHIFT)) & SYSCON_STARTERCLR_LSPI_HS_CLR_MASK) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK (0x8000000U) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT (27U) -#define SYSCON_STARTERCLR_USB0_NEEDCLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_NEEDCLK_CLR_MASK) -#define SYSCON_STARTERCLR_USB0_CLR_MASK (0x10000000U) -#define SYSCON_STARTERCLR_USB0_CLR_SHIFT (28U) -#define SYSCON_STARTERCLR_USB0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_USB0_CLR_SHIFT)) & SYSCON_STARTERCLR_USB0_CLR_MASK) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK (0x20000000U) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT (29U) -#define SYSCON_STARTERCLR_RTC_LITE0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_RTC_LITE0_CLR_SHIFT)) & SYSCON_STARTERCLR_RTC_LITE0_CLR_MASK) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK (0x40000000U) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT (30U) -#define SYSCON_STARTERCLR_EZH_ARCH_B0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_SHIFT)) & SYSCON_STARTERCLR_EZH_ARCH_B0_CLR_MASK) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK (0x80000000U) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT (31U) -#define SYSCON_STARTERCLR_WAKEUPPADS_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUPPADS_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUPPADS_CLR_MASK) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK (0x80000000U) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT (31U) -#define SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_SHIFT)) & SYSCON_STARTERCLR_WAKEUP_MAILBOX0_CLR_MASK) -/*! @} */ - -/* The count of SYSCON_STARTERCLR */ -#define SYSCON_STARTERCLR_COUNT (2U) - -/*! @name HARDWARESLEEP - Hardware Sleep control */ -/*! @{ */ -#define SYSCON_HARDWARESLEEP_FORCED_MASK (0x1U) -#define SYSCON_HARDWARESLEEP_FORCED_SHIFT (0U) -#define SYSCON_HARDWARESLEEP_FORCED(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_FORCED_SHIFT)) & SYSCON_HARDWARESLEEP_FORCED_MASK) -#define SYSCON_HARDWARESLEEP_PERIPHERALS_MASK (0x2U) -#define SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT (1U) -#define SYSCON_HARDWARESLEEP_PERIPHERALS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_PERIPHERALS_SHIFT)) & SYSCON_HARDWARESLEEP_PERIPHERALS_MASK) -#define SYSCON_HARDWARESLEEP_SDMA0_MASK (0x8U) -#define SYSCON_HARDWARESLEEP_SDMA0_SHIFT (3U) -#define SYSCON_HARDWARESLEEP_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA0_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA0_MASK) -#define SYSCON_HARDWARESLEEP_SDMA1_MASK (0x20U) -#define SYSCON_HARDWARESLEEP_SDMA1_SHIFT (5U) -#define SYSCON_HARDWARESLEEP_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HARDWARESLEEP_SDMA1_SHIFT)) & SYSCON_HARDWARESLEEP_SDMA1_MASK) +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK (0xFFC000U) +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT (14U) +/*! RET_LENTH - lenth of Scan chains to save. + */ +#define SYSCON_FUNCRETENTIONCTRL_RET_LENTH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FUNCRETENTIONCTRL_RET_LENTH_SHIFT)) & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) /*! @} */ /*! @name CPUCTRL - CPU Control for multiple processors */ /*! @{ */ + #define SYSCON_CPUCTRL_CPU1CLKEN_MASK (0x8U) #define SYSCON_CPUCTRL_CPU1CLKEN_SHIFT (3U) /*! CPU1CLKEN - CPU1 clock enable. @@ -20455,6 +24785,7 @@ typedef struct { * 0b0..The CPU1 clock is not enabled. */ #define SYSCON_CPUCTRL_CPU1CLKEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCTRL_CPU1CLKEN_SHIFT)) & SYSCON_CPUCTRL_CPU1CLKEN_MASK) + #define SYSCON_CPUCTRL_CPU1RSTEN_MASK (0x20U) #define SYSCON_CPUCTRL_CPU1RSTEN_SHIFT (5U) /*! CPU1RSTEN - CPU1 reset. @@ -20466,20 +24797,17 @@ typedef struct { /*! @name CPBOOT - Coprocessor Boot Address */ /*! @{ */ + #define SYSCON_CPBOOT_CPBOOT_MASK (0xFFFFFFFFU) #define SYSCON_CPBOOT_CPBOOT_SHIFT (0U) +/*! CPBOOT - Coprocessor Boot Address for CPU1. + */ #define SYSCON_CPBOOT_CPBOOT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPBOOT_CPBOOT_SHIFT)) & SYSCON_CPBOOT_CPBOOT_MASK) /*! @} */ -/*! @name CPSTACK - Coprocessor Stack Address */ -/*! @{ */ -#define SYSCON_CPSTACK_CPSTACK_MASK (0xFFFFFFFFU) -#define SYSCON_CPSTACK_CPSTACK_SHIFT (0U) -#define SYSCON_CPSTACK_CPSTACK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTACK_CPSTACK_SHIFT)) & SYSCON_CPSTACK_CPSTACK_MASK) -/*! @} */ - /*! @name CPSTAT - CPU Status */ /*! @{ */ + #define SYSCON_CPSTAT_CPU0SLEEPING_MASK (0x1U) #define SYSCON_CPSTAT_CPU0SLEEPING_SHIFT (0U) /*! CPU0SLEEPING - The CPU0 sleeping state. @@ -20487,6 +24815,7 @@ typedef struct { * 0b0..the CPU is not sleeping. */ #define SYSCON_CPSTAT_CPU0SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU0SLEEPING_MASK) + #define SYSCON_CPSTAT_CPU1SLEEPING_MASK (0x2U) #define SYSCON_CPSTAT_CPU1SLEEPING_SHIFT (1U) /*! CPU1SLEEPING - The CPU1 sleeping state. @@ -20494,6 +24823,7 @@ typedef struct { * 0b0..the CPU is not sleeping. */ #define SYSCON_CPSTAT_CPU1SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1SLEEPING_SHIFT)) & SYSCON_CPSTAT_CPU1SLEEPING_MASK) + #define SYSCON_CPSTAT_CPU0LOCKUP_MASK (0x4U) #define SYSCON_CPSTAT_CPU0LOCKUP_SHIFT (2U) /*! CPU0LOCKUP - The CPU0 lockup state. @@ -20501,6 +24831,7 @@ typedef struct { * 0b0..the CPU is not in lockup. */ #define SYSCON_CPSTAT_CPU0LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU0LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU0LOCKUP_MASK) + #define SYSCON_CPSTAT_CPU1LOCKUP_MASK (0x8U) #define SYSCON_CPSTAT_CPU1LOCKUP_SHIFT (3U) /*! CPU1LOCKUP - The CPU1 lockup state. @@ -20510,71 +24841,9 @@ typedef struct { #define SYSCON_CPSTAT_CPU1LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPSTAT_CPU1LOCKUP_SHIFT)) & SYSCON_CPSTAT_CPU1LOCKUP_MASK) /*! @} */ -/*! @name DICE_REG0 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG0_DICE_REG0_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG0_DICE_REG0_SHIFT (0U) -#define SYSCON_DICE_REG0_DICE_REG0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG0_DICE_REG0_SHIFT)) & SYSCON_DICE_REG0_DICE_REG0_MASK) -/*! @} */ - -/*! @name DICE_REG1 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG1_DICE_REG1_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG1_DICE_REG1_SHIFT (0U) -#define SYSCON_DICE_REG1_DICE_REG1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG1_DICE_REG1_SHIFT)) & SYSCON_DICE_REG1_DICE_REG1_MASK) -/*! @} */ - -/*! @name DICE_REG2 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG2_DICE_REG2_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG2_DICE_REG2_SHIFT (0U) -#define SYSCON_DICE_REG2_DICE_REG2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG2_DICE_REG2_SHIFT)) & SYSCON_DICE_REG2_DICE_REG2_MASK) -/*! @} */ - -/*! @name DICE_REG3 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG3_DICE_REG3_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG3_DICE_REG3_SHIFT (0U) -#define SYSCON_DICE_REG3_DICE_REG3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG3_DICE_REG3_SHIFT)) & SYSCON_DICE_REG3_DICE_REG3_MASK) -/*! @} */ - -/*! @name DICE_REG4 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG4_DICE_REG4_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG4_DICE_REG4_SHIFT (0U) -#define SYSCON_DICE_REG4_DICE_REG4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG4_DICE_REG4_SHIFT)) & SYSCON_DICE_REG4_DICE_REG4_MASK) -/*! @} */ - -/*! @name DICE_REG5 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG5_DICE_REG5_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG5_DICE_REG5_SHIFT (0U) -#define SYSCON_DICE_REG5_DICE_REG5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG5_DICE_REG5_SHIFT)) & SYSCON_DICE_REG5_DICE_REG5_MASK) -/*! @} */ - -/*! @name DICE_REG6 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG6_DICE_REG6_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG6_DICE_REG6_SHIFT (0U) -#define SYSCON_DICE_REG6_DICE_REG6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG6_DICE_REG6_SHIFT)) & SYSCON_DICE_REG6_DICE_REG6_MASK) -/*! @} */ - -/*! @name DICE_REG7 - Composite Device Identifier */ -/*! @{ */ -#define SYSCON_DICE_REG7_DICE_REG7_MASK (0xFFFFFFFFU) -#define SYSCON_DICE_REG7_DICE_REG7_SHIFT (0U) -#define SYSCON_DICE_REG7_DICE_REG7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DICE_REG7_DICE_REG7_SHIFT)) & SYSCON_DICE_REG7_DICE_REG7_MASK) -/*! @} */ - /*! @name CLOCK_CTRL - Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures */ /*! @{ */ -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK (0x1U) -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT (0U) -/*! FLASH48MHZ_ENA - Enable Flash 48 MHz clock. - * 0b1..The clock is enabled. - * 0b0..The clock is not enabled. - */ -#define SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FLASH48MHZ_ENA_MASK) + #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK (0x2U) #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT (1U) /*! XTAL32MHZ_FREQM_ENA - Enable XTAL32MHz clock for Frequency Measure module. @@ -20582,6 +24851,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XTAL32MHZ_FREQM_ENA_MASK) + #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK (0x4U) #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT (2U) /*! FRO1MHZ_UTICK_ENA - Enable FRO 1MHz clock for Frequency Measure module and for UTICK. @@ -20589,6 +24859,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_UTICK_ENA_MASK) + #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK (0x8U) #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT (3U) /*! FRO12MHZ_FREQM_ENA - Enable FRO 12MHz clock for Frequency Measure module. @@ -20596,6 +24867,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO12MHZ_FREQM_ENA_MASK) + #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK (0x10U) #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT (4U) /*! FRO_HF_FREQM_ENA - Enable FRO 96MHz clock for Frequency Measure module. @@ -20603,6 +24875,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO_HF_FREQM_ENA_MASK) + #define SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK (0x20U) #define SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT (5U) /*! CLKIN_ENA - Enable clock_in clock for clock module. @@ -20610,6 +24883,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_CLKIN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_CLKIN_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK) + #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK (0x40U) #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT (6U) /*! FRO1MHZ_CLK_ENA - Enable FRO 1MHz clock for clock muxing in clock gen. @@ -20617,6 +24891,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) + #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK (0x80U) #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT (7U) /*! ANA_FRO12M_CLK_ENA - Enable FRO 12MHz clock for analog control of the FRO 192MHz. @@ -20624,6 +24899,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_ANA_FRO12M_CLK_ENA_MASK) + #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK (0x100U) #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT (8U) /*! XO_CAL_CLK_ENA - Enable clock for cristal oscilator calibration. @@ -20631,6 +24907,7 @@ typedef struct { * 0b0..The clock is not enabled. */ #define SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_SHIFT)) & SYSCON_CLOCK_CTRL_XO_CAL_CLK_ENA_MASK) + #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_MASK (0x200U) #define SYSCON_CLOCK_CTRL_PLU_DEGLITCH_CLK_ENA_SHIFT (9U) /*! PLU_DEGLITCH_CLK_ENA - Enable clocks FRO_1MHz and FRO_12MHz for PLU deglitching. @@ -20642,6 +24919,7 @@ typedef struct { /*! @name COMP_INT_CTRL - Comparator Interrupt control */ /*! @{ */ + #define SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK (0x1U) #define SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT (0U) /*! INT_ENABLE - Analog Comparator interrupt enable control:. @@ -20649,6 +24927,7 @@ typedef struct { * 0b0..interrupt disable. */ #define SYSCON_COMP_INT_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_ENABLE_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK) + #define SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK (0x2U) #define SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT (1U) /*! INT_CLEAR - Analog Comparator interrupt clear. @@ -20656,6 +24935,7 @@ typedef struct { * 0b1..Clear the interrupt. Self-cleared bit. */ #define SYSCON_COMP_INT_CTRL_INT_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CLEAR_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK) + #define SYSCON_COMP_INT_CTRL_INT_CTRL_MASK (0x1CU) #define SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT (2U) /*! INT_CTRL - Comparator interrupt type selector:. @@ -20669,6 +24949,7 @@ typedef struct { * 0b111..The analog comparator interrupt level sensitive is disabled. */ #define SYSCON_COMP_INT_CTRL_INT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT)) & SYSCON_COMP_INT_CTRL_INT_CTRL_MASK) + #define SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK (0x20U) #define SYSCON_COMP_INT_CTRL_INT_SOURCE_SHIFT (5U) /*! INT_SOURCE - Select which Analog comparator output (filtered our un-filtered) is used for interrupt detection. @@ -20681,6 +24962,7 @@ typedef struct { /*! @name COMP_INT_STATUS - Comparator Interrupt status */ /*! @{ */ + #define SYSCON_COMP_INT_STATUS_STATUS_MASK (0x1U) #define SYSCON_COMP_INT_STATUS_STATUS_SHIFT (0U) /*! STATUS - Interrupt status BEFORE Interrupt Enable. @@ -20688,6 +24970,7 @@ typedef struct { * 0b1..interrupt pending. */ #define SYSCON_COMP_INT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_STATUS_MASK) + #define SYSCON_COMP_INT_STATUS_INT_STATUS_MASK (0x2U) #define SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT (1U) /*! INT_STATUS - Interrupt status AFTER Interrupt Enable. @@ -20695,6 +24978,7 @@ typedef struct { * 0b1..interrupt pending. */ #define SYSCON_COMP_INT_STATUS_INT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_COMP_INT_STATUS_INT_STATUS_SHIFT)) & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) + #define SYSCON_COMP_INT_STATUS_VAL_MASK (0x4U) #define SYSCON_COMP_INT_STATUS_VAL_SHIFT (2U) /*! VAL - comparator analog output. @@ -20706,6 +24990,7 @@ typedef struct { /*! @name AUTOCLKGATEOVERRIDE - Control automatic clock gating */ /*! @{ */ + #define SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK (0x1U) #define SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT (0U) /*! ROM - Control automatic clock gating of ROM controller. @@ -20713,6 +24998,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ROM_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ROM_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK (0x2U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT (1U) /*! RAMX_CTRL - Control automatic clock gating of RAMX controller. @@ -20720,6 +25006,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAMX_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK (0x4U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT (2U) /*! RAM0_CTRL - Control automatic clock gating of RAM0 controller. @@ -20727,6 +25014,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM0_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK (0x8U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT (3U) /*! RAM1_CTRL - Control automatic clock gating of RAM1 controller. @@ -20734,6 +25022,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM1_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK (0x10U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT (4U) /*! RAM2_CTRL - Control automatic clock gating of RAM2 controller. @@ -20741,6 +25030,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM2_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK (0x20U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT (5U) /*! RAM3_CTRL - Control automatic clock gating of RAM3 controller. @@ -20748,6 +25038,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM3_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK (0x40U) #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT (6U) /*! RAM4_CTRL - Control automatic clock gating of RAM4 controller. @@ -20755,6 +25046,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_RAM4_CTRL_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK (0x80U) #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT (7U) /*! SYNC0_APB - Control automatic clock gating of synchronous bridge controller 0. @@ -20762,6 +25054,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC0_APB_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK (0x100U) #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT (8U) /*! SYNC1_APB - Control automatic clock gating of synchronous bridge controller 1. @@ -20769,20 +25062,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYNC1_APB_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK (0x200U) -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT (9U) -/*! FLASH - Control automatic clock gating of FLASH controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FLASH_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FLASH_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK (0x400U) -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT (10U) -/*! FMC - Control automatic clock gating of FMC controller. - * 0b1..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0..Automatic clock gating is not overridden. - */ -#define SYSCON_AUTOCLKGATEOVERRIDE_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_FMC_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_FMC_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK (0x800U) #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT (11U) /*! CRCGEN - Control automatic clock gating of CRCGEN controller. @@ -20790,6 +25070,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_CRCGEN_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK (0x1000U) #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT (12U) /*! SDMA0 - Control automatic clock gating of DMA0 controller. @@ -20797,6 +25078,7 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA0_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK (0x2000U) #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT (13U) /*! SDMA1 - Control automatic clock gating of DMA1 controller. @@ -20804,13 +25086,15 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_SDMA1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SDMA1_MASK) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK (0x4000U) -#define SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT (14U) -/*! USB - Control automatic clock gating of USB controller. + +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK (0x4000U) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT (14U) +/*! USB0 - Control automatic clock gating of USB controller. * 0b1..Automatic clock gating is overridden (Clock gating is disabled). * 0b0..Automatic clock gating is not overridden. */ -#define SYSCON_AUTOCLKGATEOVERRIDE_USB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB_MASK) +#define SYSCON_AUTOCLKGATEOVERRIDE_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_USB0_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_USB0_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK (0x8000U) #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT (15U) /*! SYSCON - Control automatic clock gating of synchronous system controller registers bank. @@ -20818,17 +25102,19 @@ typedef struct { * 0b0..Automatic clock gating is not overridden. */ #define SYSCON_AUTOCLKGATEOVERRIDE_SYSCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_SYSCON_MASK) + #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK (0xFFFF0000U) #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT (16U) /*! ENABLEUPDATE - The value 0xC0DE must be written for AUTOCLKGATEOVERRIDE registers fields updates to have effect. - * 0b1100000011011110..Automatic clock gating is overridden (Clock gating is disabled). - * 0b0000000000000000..Automatic clock gating is not overridden. + * 0b1100000011011110..Bit Fields 0 - 15 of this register are updated + * 0b0000000000000000..Bit Fields 0 - 15 of this register are not updated */ #define SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_SHIFT)) & SYSCON_AUTOCLKGATEOVERRIDE_ENABLEUPDATE_MASK) /*! @} */ /*! @name GPIOPSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module */ /*! @{ */ + #define SYSCON_GPIOPSYNC_PSYNC_MASK (0x1U) #define SYSCON_GPIOPSYNC_PSYNC_SHIFT (0U) /*! PSYNC - Enable bypass of the first stage of synchonization inside GPIO_INT module. @@ -20838,159 +25124,147 @@ typedef struct { #define SYSCON_GPIOPSYNC_PSYNC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_GPIOPSYNC_PSYNC_SHIFT)) & SYSCON_GPIOPSYNC_PSYNC_MASK) /*! @} */ -/*! @name DEBUG_LOCK_EN - Control write access to security registers -- FOR INTERNAl USE ONLY */ +/*! @name DEBUG_LOCK_EN - Control write access to security registers. */ /*! @{ */ + #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK (0xFU) #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT (0U) /*! LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, - * CODESECURITYPROTCPU1, CM33_DEBUG_FEATURES, MCM33_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + * CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. * 0b1010..1010: Enable write access to all 6 registers. * 0b0000..Any other value than b1010: disable write access to all 6 registers. */ #define SYSCON_DEBUG_LOCK_EN_LOCK_ALL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_LOCK_EN_LOCK_ALL_SHIFT)) & SYSCON_DEBUG_LOCK_EN_LOCK_ALL_MASK) /*! @} */ -/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY */ +/*! @name DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. */ /*! @{ */ -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT (0U) -/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT (2U) -/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_NIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT (4U) -/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT (6U) -/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CM33_SPNIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT (8U) -/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU0_SPNIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT (10U) -/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_MCM33_NIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_CPU1_NIDEN_MASK) /*! @} */ -/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY */ +/*! @name DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. */ /*! @{ */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK (0x3U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT (0U) -/*! CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK (0x3U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT (0U) +/*! CPU0_DBGEN - CPU0 (CPU0) Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK (0xCU) -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT (2U) -/*! CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK (0xCU) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT (2U) +/*! CPU0_NIDEN - CPU0 Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_NIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK (0x30U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT (4U) -/*! CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_NIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK (0x30U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT (4U) +/*! CPU0_SPIDEN - CPU0 Secure Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK (0xC0U) -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT (6U) -/*! CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK (0xC0U) +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT (6U) +/*! CPU0_SPNIDEN - CPU0 Secure Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CM33_SPNIDEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK (0x300U) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT (8U) -/*! MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU0_SPNIDEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK (0x300U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT (8U) +/*! CPU1_DBGEN - CPU1 Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_DBGEN_MASK) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK (0xC00U) -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT (10U) -/*! MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. +#define SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_DBGEN_MASK) + +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK (0xC00U) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT (10U) +/*! CPU1_NIDEN - CPU1 Non Invasive debug control:. * 0b10..10: Invasive debug is enabled. * 0b01..Any other value than b10: invasive debug is disable. */ -#define SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_MCM33_NIDEN_MASK) +#define SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_SHIFT)) & SYSCON_DEBUG_FEATURES_DP_CPU1_NIDEN_MASK) /*! @} */ -/*! @name CODESECURITYPROTTEST - Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY */ +/*! @name KEY_BLOCK - block quiddikey/PUF all index. */ /*! @{ */ -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow test access : 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow test access. - * 0b00000000000000000000000000000000..test access is not allowed. - */ -#define SYSCON_CODESECURITYPROTTEST_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTTEST_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTTEST_SEC_CODE_MASK) -/*! @} */ -/*! @name CODESECURITYPROTCPU0 - Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow CPU0 DAP: 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow CPU0 DAP. - * 0b00000000000000000000000000000000..CPU0 DAP is not allowed. - */ -#define SYSCON_CODESECURITYPROTCPU0_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU0_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU0_SEC_CODE_MASK) -/*! @} */ - -/*! @name CODESECURITYPROTCPU1 - Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY */ -/*! @{ */ -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK (0xFFFFFFFFU) -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT (0U) -/*! SEC_CODE - Security code to allow CPU1 DAP: 0x12345678. - * 0b00010010001101000101011001111000..Security code to allow CPU1 DAP. - * 0b00000000000000000000000000000000..CPU1 DAP is not allowed. - */ -#define SYSCON_CODESECURITYPROTCPU1_SEC_CODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CODESECURITYPROTCPU1_SEC_CODE_SHIFT)) & SYSCON_CODESECURITYPROTCPU1_SEC_CODE_MASK) -/*! @} */ - -/*! @name KEY_BLOCK - block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY */ -/*! @{ */ #define SYSCON_KEY_BLOCK_KEY_BLOCK_MASK (0xFFFFFFFFU) #define SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT (0U) +/*! KEY_BLOCK - Write a value to block quiddikey/PUF all index. + */ #define SYSCON_KEY_BLOCK_KEY_BLOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_KEY_BLOCK_KEY_BLOCK_SHIFT)) & SYSCON_KEY_BLOCK_KEY_BLOCK_MASK) /*! @} */ -/*! @name DEBUG_AUTH_SCRATCH - Debug authentication scratch registers -- FOR INTERNAL USE ONLY */ +/*! @name DEBUG_AUTH_BEACON - Debug authentication BEACON register */ /*! @{ */ -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK (0xFFFFFFFFU) -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT (0U) -#define SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_SHIFT)) & SYSCON_DEBUG_AUTH_SCRATCH_SCRATCH_MASK) + +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK (0xFFFFFFFFU) +#define SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT (0U) +/*! BEACON - Set by the debug authentication code in ROM to pass the debug beacons (Credential + * Beacon and Authentication Beacon) to application code. + */ +#define SYSCON_DEBUG_AUTH_BEACON_BEACON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEBUG_AUTH_BEACON_BEACON_SHIFT)) & SYSCON_DEBUG_AUTH_BEACON_BEACON_MASK) /*! @} */ /*! @name CPUCFG - CPUs configuration register */ /*! @{ */ + #define SYSCON_CPUCFG_CPU1ENABLE_MASK (0x4U) #define SYSCON_CPUCFG_CPU1ENABLE_SHIFT (2U) /*! CPU1ENABLE - Enable CPU1. @@ -21000,92 +25274,29 @@ typedef struct { #define SYSCON_CPUCFG_CPU1ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CPUCFG_CPU1ENABLE_SHIFT)) & SYSCON_CPUCFG_CPU1ENABLE_MASK) /*! @} */ -/*! @name PERIPHENCFG - peripheral enable configuration -- FOR INTERNAL USE ONLY */ -/*! @{ */ -#define SYSCON_PERIPHENCFG_SCTEN_MASK (0x1U) -#define SYSCON_PERIPHENCFG_SCTEN_SHIFT (0U) -/*! SCTEN - SCT enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_SCTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SCTEN_SHIFT)) & SYSCON_PERIPHENCFG_SCTEN_MASK) -#define SYSCON_PERIPHENCFG_ADCEN_MASK (0x2U) -#define SYSCON_PERIPHENCFG_ADCEN_SHIFT (1U) -/*! ADCEN - ADC enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_ADCEN_SHIFT)) & SYSCON_PERIPHENCFG_ADCEN_MASK) -#define SYSCON_PERIPHENCFG_USB0EN_MASK (0x4U) -#define SYSCON_PERIPHENCFG_USB0EN_SHIFT (2U) -/*! USB0EN - USB0 enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_USB0EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB0EN_SHIFT)) & SYSCON_PERIPHENCFG_USB0EN_MASK) -#define SYSCON_PERIPHENCFG_PUFFEN_MASK (0x40U) -#define SYSCON_PERIPHENCFG_PUFFEN_SHIFT (6U) -/*! PUFFEN - Puff enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_PUFFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PUFFEN_SHIFT)) & SYSCON_PERIPHENCFG_PUFFEN_MASK) -#define SYSCON_PERIPHENCFG_USB1EN_MASK (0x400U) -#define SYSCON_PERIPHENCFG_USB1EN_SHIFT (10U) -/*! USB1EN - USB1 enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_USB1EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_USB1EN_SHIFT)) & SYSCON_PERIPHENCFG_USB1EN_MASK) -#define SYSCON_PERIPHENCFG_SDIOEN_MASK (0x800U) -#define SYSCON_PERIPHENCFG_SDIOEN_SHIFT (11U) -/*! SDIOEN - SDIO enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_SDIOEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_SDIOEN_SHIFT)) & SYSCON_PERIPHENCFG_SDIOEN_MASK) -#define SYSCON_PERIPHENCFG_HASHEN_MASK (0x1000U) -#define SYSCON_PERIPHENCFG_HASHEN_SHIFT (12U) -/*! HASHEN - HASH enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_HASHEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_HASHEN_SHIFT)) & SYSCON_PERIPHENCFG_HASHEN_MASK) -#define SYSCON_PERIPHENCFG_PRINCEEN_MASK (0x4000U) -#define SYSCON_PERIPHENCFG_PRINCEEN_SHIFT (14U) -/*! PRINCEEN - PRINCE enable. - * 0b1..peripheral is enable. - * 0b0..peripheral is disable. - */ -#define SYSCON_PERIPHENCFG_PRINCEEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PERIPHENCFG_PRINCEEN_SHIFT)) & SYSCON_PERIPHENCFG_PRINCEEN_MASK) -/*! @} */ - /*! @name DEVICE_ID0 - Device ID */ /*! @{ */ -#define SYSCON_DEVICE_ID0_PARTCONFIG_MASK (0xFFU) -#define SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT (0U) -#define SYSCON_DEVICE_ID0_PARTCONFIG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTCONFIG_SHIFT)) & SYSCON_DEVICE_ID0_PARTCONFIG_MASK) -#define SYSCON_DEVICE_ID0_SRAM_SIZE_MASK (0xF00U) -#define SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT (8U) -#define SYSCON_DEVICE_ID0_SRAM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_SRAM_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_SRAM_SIZE_MASK) -#define SYSCON_DEVICE_ID0_FLASH_SIZE_MASK (0x7000U) -#define SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT (12U) -#define SYSCON_DEVICE_ID0_FLASH_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_FLASH_SIZE_SHIFT)) & SYSCON_DEVICE_ID0_FLASH_SIZE_MASK) + #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK (0xF00000U) #define SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT (20U) +/*! ROM_REV_MINOR - ROM revision. + */ #define SYSCON_DEVICE_ID0_ROM_REV_MINOR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_ROM_REV_MINOR_SHIFT)) & SYSCON_DEVICE_ID0_ROM_REV_MINOR_MASK) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK (0x7000000U) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT (24U) -#define SYSCON_DEVICE_ID0_MODELNUM_EXTENTION(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_SHIFT)) & SYSCON_DEVICE_ID0_MODELNUM_EXTENTION_MASK) /*! @} */ /*! @name DIEID - Chip revision ID and Number */ /*! @{ */ + #define SYSCON_DIEID_REV_ID_MASK (0xFU) #define SYSCON_DIEID_REV_ID_SHIFT (0U) +/*! REV_ID - Chip Metal Revision ID. + */ #define SYSCON_DIEID_REV_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_REV_ID_SHIFT)) & SYSCON_DIEID_REV_ID_MASK) + #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK (0xFFFFF0U) #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT (4U) +/*! MCO_NUM_IN_DIE_ID - Chip Number 0x426B. + */ #define SYSCON_DIEID_MCO_NUM_IN_DIE_ID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DIEID_MCO_NUM_IN_DIE_ID_SHIFT)) & SYSCON_DIEID_MCO_NUM_IN_DIE_ID_MASK) /*! @} */ @@ -21096,7 +25307,7 @@ typedef struct { /* SYSCON - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral SYSCON base address */ #define SYSCON_BASE (0x50000000u) /** Peripheral SYSCON base address */ @@ -21160,6 +25371,7 @@ typedef struct { /*! @name UPDATELCKOUT - update lock out control */ /*! @{ */ + #define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK (0x1U) #define SYSCTL_UPDATELCKOUT_UPDATELCKOUT_SHIFT (0U) /*! UPDATELCKOUT - All Registers @@ -21171,6 +25383,7 @@ typedef struct { /*! @name FCCTRLSEL - Selects the source for SCK going into Flexcomm 0..Selects the source for SCK going into Flexcomm 7 */ /*! @{ */ + #define SYSCTL_FCCTRLSEL_SCKINSEL_MASK (0x3U) #define SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT (0U) /*! SCKINSEL - Selects the source for SCK going into this Flexcomm. @@ -21180,6 +25393,7 @@ typedef struct { * 0b11..Reserved. */ #define SYSCTL_FCCTRLSEL_SCKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_SCKINSEL_MASK) + #define SYSCTL_FCCTRLSEL_WSINSEL_MASK (0x300U) #define SYSCTL_FCCTRLSEL_WSINSEL_SHIFT (8U) /*! WSINSEL - Selects the source for WS going into this Flexcomm. @@ -21189,6 +25403,7 @@ typedef struct { * 0b11..Reserved. */ #define SYSCTL_FCCTRLSEL_WSINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_WSINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_WSINSEL_MASK) + #define SYSCTL_FCCTRLSEL_DATAINSEL_MASK (0x30000U) #define SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT (16U) /*! DATAINSEL - Selects the source for DATA input to this Flexcomm. @@ -21198,6 +25413,7 @@ typedef struct { * 0b11..Reserved. */ #define SYSCTL_FCCTRLSEL_DATAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT)) & SYSCTL_FCCTRLSEL_DATAINSEL_MASK) + #define SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK (0x3000000U) #define SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT (24U) /*! DATAOUTSEL - Selects the source for DATA output from this Flexcomm. @@ -21212,10 +25428,11 @@ typedef struct { /* The count of SYSCTL_FCCTRLSEL */ #define SYSCTL_FCCTRLSEL_COUNT (8U) -/*! @name SHARECTRLSET_SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ +/*! @name SHAREDCTRLSET - Selects sources and data combinations for shared signal set 0...Selects sources and data combinations for shared signal set 1. */ /*! @{ */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) + +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK (0x7U) +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT (0U) /*! SHAREDSCKSEL - Selects the source for SCK of this shared signal set. * 0b000..SCK for this shared signal set comes from Flexcomm 0. * 0b001..SCK for this shared signal set comes from Flexcomm 1. @@ -21226,9 +25443,10 @@ typedef struct { * 0b110..SCK for this shared signal set comes from Flexcomm 6. * 0b111..SCK for this shared signal set comes from Flexcomm 7. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) +#define SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK (0x70U) +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT (4U) /*! SHAREDWSSEL - Selects the source for WS of this shared signal set. * 0b000..WS for this shared signal set comes from Flexcomm 0. * 0b001..WS for this shared signal set comes from Flexcomm 1. @@ -21239,9 +25457,10 @@ typedef struct { * 0b110..WS for this shared signal set comes from Flexcomm 6. * 0b111..WS for this shared signal set comes from Flexcomm 7. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) +#define SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK (0x700U) +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT (8U) /*! SHAREDDATASEL - Selects the source for DATA input for this shared signal set. * 0b000..DATA input for this shared signal set comes from Flexcomm 0. * 0b001..DATA input for this shared signal set comes from Flexcomm 1. @@ -21252,70 +25471,71 @@ typedef struct { * 0b110..DATA input for this shared signal set comes from Flexcomm 6. * 0b111..DATA input for this shared signal set comes from Flexcomm 7. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) +#define SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT)) & SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK (0x10000U) +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT (16U) /*! FC0DATAOUTEN - Controls FC0 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC0 does not contribute to this shared set. * 0b1..Data output from FC0 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) +#define SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK (0x20000U) +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT (17U) /*! FC1DATAOUTEN - Controls FC1 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC1 does not contribute to this shared set. * 0b1..Data output from FC1 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK (0x40000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT (18U) -/*! F20DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. +#define SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK (0x40000U) +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT (18U) +/*! FC2DATAOUTEN - Controls FC2 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC2 does not contribute to this shared set. * 0b1..Data output from FC2 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK (0x80000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT (19U) -/*! FC3DATAOUTEN - Controls FC3 contribution to SHAREDDATAOUT for this shared set. - * 0b0..Data output from FC3 does not contribute to this shared set. - * 0b1..Data output from FC3 does contribute to this shared set. - */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) +#define SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK (0x100000U) +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT (20U) /*! FC4DATAOUTEN - Controls FC4 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC4 does not contribute to this shared set. * 0b1..Data output from FC4 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) +#define SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK (0x200000U) +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT (21U) /*! FC5DATAOUTEN - Controls FC5 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC5 does not contribute to this shared set. * 0b1..Data output from FC5 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) +#define SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK (0x400000U) +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT (22U) /*! FC6DATAOUTEN - Controls FC6 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC6 does not contribute to this shared set. * 0b1..Data output from FC6 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) +#define SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK) + +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK (0x800000U) +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT (23U) /*! FC7DATAOUTEN - Controls FC7 contribution to SHAREDDATAOUT for this shared set. * 0b0..Data output from FC7 does not contribute to this shared set. * 0b1..Data output from FC7 does contribute to this shared set. */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK) +#define SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_SHIFT)) & SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK) /*! @} */ -/* The count of SYSCTL_SHARECTRLSET_SHAREDCTRLSET */ -#define SYSCTL_SHARECTRLSET_SHAREDCTRLSET_COUNT (2U) +/* The count of SYSCTL_SHAREDCTRLSET */ +#define SYSCTL_SHAREDCTRLSET_COUNT (2U) /*! @name USB_HS_STATUS - Status register for USB HS */ /*! @{ */ + #define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_MASK (0x1U) #define SYSCTL_USB_HS_STATUS_USBHS_3V_NOK_SHIFT (0U) /*! USBHS_3V_NOK - USB_HS: Low voltage detection on 3.3V supply. @@ -21332,7 +25552,7 @@ typedef struct { /* SYSCTL - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral SYSCTL base address */ #define SYSCTL_BASE (0x50023000u) /** Peripheral SYSCTL base address */ @@ -21400,7 +25620,9 @@ typedef struct { __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */ uint8_t RESERVED_5[12]; __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */ - uint8_t RESERVED_6[440]; + uint8_t RESERVED_6[4]; + __I uint32_t FIFOSIZE; /**< FIFO size register, offset: 0xE48 */ + uint8_t RESERVED_7[432]; __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */ } USART_Type; @@ -21415,6 +25637,7 @@ typedef struct { /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ /*! @{ */ + #define USART_CFG_ENABLE_MASK (0x1U) #define USART_CFG_ENABLE_SHIFT (0U) /*! ENABLE - USART Enable. @@ -21425,6 +25648,7 @@ typedef struct { * 0b1..Enabled. The USART is enabled for operation. */ #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) + #define USART_CFG_DATALEN_MASK (0xCU) #define USART_CFG_DATALEN_SHIFT (2U) /*! DATALEN - Selects the data size for the USART. @@ -21434,6 +25658,7 @@ typedef struct { * 0b11..Reserved. */ #define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) + #define USART_CFG_PARITYSEL_MASK (0x30U) #define USART_CFG_PARITYSEL_SHIFT (4U) /*! PARITYSEL - Selects what type of parity is used by the USART. @@ -21445,6 +25670,7 @@ typedef struct { * and the number of 1s in a received character is expected to be odd. */ #define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) + #define USART_CFG_STOPLEN_MASK (0x40U) #define USART_CFG_STOPLEN_SHIFT (6U) /*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. @@ -21452,6 +25678,7 @@ typedef struct { * 0b1..2 stop bits. This setting should only be used for asynchronous communication. */ #define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) + #define USART_CFG_MODE32K_MASK (0x80U) #define USART_CFG_MODE32K_SHIFT (7U) /*! MODE32K - Selects standard or 32 kHz clocking mode. @@ -21459,6 +25686,7 @@ typedef struct { * 0b1..Enabled. USART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme. */ #define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK) + #define USART_CFG_LINMODE_MASK (0x100U) #define USART_CFG_LINMODE_SHIFT (8U) /*! LINMODE - LIN break mode enable. @@ -21466,6 +25694,7 @@ typedef struct { * 0b1..Enabled. Break detect and generate is configured for LIN bus operation. */ #define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK) + #define USART_CFG_CTSEN_MASK (0x200U) #define USART_CFG_CTSEN_SHIFT (9U) /*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input @@ -21474,6 +25703,7 @@ typedef struct { * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. */ #define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) + #define USART_CFG_SYNCEN_MASK (0x800U) #define USART_CFG_SYNCEN_SHIFT (11U) /*! SYNCEN - Selects synchronous or asynchronous operation. @@ -21481,6 +25711,7 @@ typedef struct { * 0b1..Synchronous mode. */ #define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) + #define USART_CFG_CLKPOL_MASK (0x1000U) #define USART_CFG_CLKPOL_SHIFT (12U) /*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. @@ -21488,6 +25719,7 @@ typedef struct { * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. */ #define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) + #define USART_CFG_SYNCMST_MASK (0x4000U) #define USART_CFG_SYNCMST_SHIFT (14U) /*! SYNCMST - Synchronous mode Master select. @@ -21495,6 +25727,7 @@ typedef struct { * 0b1..Master. When synchronous mode is enabled, the USART is a master. */ #define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) + #define USART_CFG_LOOP_MASK (0x8000U) #define USART_CFG_LOOP_SHIFT (15U) /*! LOOP - Selects data loopback mode. @@ -21505,6 +25738,7 @@ typedef struct { * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. */ #define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) + #define USART_CFG_OETA_MASK (0x40000U) #define USART_CFG_OETA_SHIFT (18U) /*! OETA - Output Enable Turnaround time enable for RS-485 operation. @@ -21514,6 +25748,7 @@ typedef struct { * before it is deasserted. */ #define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) + #define USART_CFG_AUTOADDR_MASK (0x80000U) #define USART_CFG_AUTOADDR_SHIFT (19U) /*! AUTOADDR - Automatic Address matching enable. @@ -21523,6 +25758,7 @@ typedef struct { * the ADDR register as the address to match. */ #define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) + #define USART_CFG_OESEL_MASK (0x100000U) #define USART_CFG_OESEL_SHIFT (20U) /*! OESEL - Output Enable Select. @@ -21530,6 +25766,7 @@ typedef struct { * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. */ #define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) + #define USART_CFG_OEPOL_MASK (0x200000U) #define USART_CFG_OEPOL_SHIFT (21U) /*! OEPOL - Output Enable Polarity. @@ -21537,6 +25774,7 @@ typedef struct { * 0b1..High. If selected by OESEL, the output enable is active high. */ #define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) + #define USART_CFG_RXPOL_MASK (0x400000U) #define USART_CFG_RXPOL_SHIFT (22U) /*! RXPOL - Receive data polarity. @@ -21546,6 +25784,7 @@ typedef struct { * 0, start bit is 1, data is inverted, and the stop bit is 0. */ #define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) + #define USART_CFG_TXPOL_MASK (0x800000U) #define USART_CFG_TXPOL_SHIFT (23U) /*! TXPOL - Transmit data polarity. @@ -21559,6 +25798,7 @@ typedef struct { /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ /*! @{ */ + #define USART_CTL_TXBRKEN_MASK (0x2U) #define USART_CTL_TXBRKEN_SHIFT (1U) /*! TXBRKEN - Break Enable. @@ -21569,6 +25809,7 @@ typedef struct { * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. */ #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) + #define USART_CTL_ADDRDET_MASK (0x4U) #define USART_CTL_ADDRDET_SHIFT (2U) /*! ADDRDET - Enable address detect mode. @@ -21580,6 +25821,7 @@ typedef struct { * normally. */ #define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) + #define USART_CTL_TXDIS_MASK (0x40U) #define USART_CTL_TXDIS_SHIFT (6U) /*! TXDIS - Transmit Disable. @@ -21588,6 +25830,7 @@ typedef struct { * feature can be used to facilitate software flow control. */ #define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) + #define USART_CTL_CC_MASK (0x100U) #define USART_CTL_CC_SHIFT (8U) /*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. @@ -21597,6 +25840,7 @@ typedef struct { * Un_RxD independently from transmission on Un_TXD). */ #define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) + #define USART_CTL_CLRCCONRX_MASK (0x200U) #define USART_CTL_CLRCCONRX_SHIFT (9U) /*! CLRCCONRX - Clear Continuous Clock. @@ -21604,6 +25848,7 @@ typedef struct { * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. */ #define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) + #define USART_CTL_AUTOBAUD_MASK (0x10000U) #define USART_CTL_AUTOBAUD_SHIFT (16U) /*! AUTOBAUD - Autobaud enable. @@ -21617,160 +25862,314 @@ typedef struct { /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ /*! @{ */ + #define USART_STAT_RXIDLE_MASK (0x2U) #define USART_STAT_RXIDLE_SHIFT (1U) +/*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of + * receiving data. When 1, indicates that the receiver is not currently in the process of receiving + * data. + */ #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) + #define USART_STAT_TXIDLE_MASK (0x8U) #define USART_STAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of + * sending data.When 1, indicate that the transmitter is not currently in the process of sending + * data. + */ #define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) + #define USART_STAT_CTS_MASK (0x10U) #define USART_STAT_CTS_SHIFT (4U) +/*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the + * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode + * is enabled. + */ #define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) + #define USART_STAT_DELTACTS_MASK (0x20U) #define USART_STAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. + */ #define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) + #define USART_STAT_TXDISSTAT_MASK (0x40U) #define USART_STAT_TXDISSTAT_SHIFT (6U) +/*! TXDISSTAT - Transmitter Disabled Status flag. When 1, this bit indicates that the USART + * transmitter is fully idle after being disabled via the TXDIS bit in the CFG register (TXDIS = 1). + */ #define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) + #define USART_STAT_RXBRK_MASK (0x400U) #define USART_STAT_RXBRK_SHIFT (10U) +/*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection + * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also + * be set when this condition occurs because the stop bit(s) for the character would be missing. + * RXBRK is cleared when the Un_RXD pin goes high. + */ #define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) + #define USART_STAT_DELTARXBRK_MASK (0x800U) #define USART_STAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. Cleared by software. + */ #define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) + #define USART_STAT_START_MASK (0x1000U) #define USART_STAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily + * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. + * Cleared by software. + */ #define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) + #define USART_STAT_FRAMERRINT_MASK (0x2000U) #define USART_STAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a + * missing stop bit at the expected location. This could be an indication of a baud rate or + * configuration mismatch with the transmitting source. + */ #define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) + #define USART_STAT_PARITYERRINT_MASK (0x4000U) #define USART_STAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. + */ #define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) + #define USART_STAT_RXNOISEINT_MASK (0x8000U) #define USART_STAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to + * determine the value of each received data bit, except in synchronous mode. This acts as a + * noise filter if one sample disagrees. This flag is set when a received data bit contains one + * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or + * loss of synchronization during data reception. + */ #define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) + #define USART_STAT_ABERR_MASK (0x10000U) #define USART_STAT_ABERR_SHIFT (16U) +/*! ABERR - Auto baud Error. An auto baud error can occur if the BRG counts to its limit before the + * end of the start bit that is being measured, essentially an auto baud time-out. + */ #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) /*! @} */ /*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ /*! @{ */ + #define USART_INTENSET_TXIDLEEN_MASK (0x8U) #define USART_INTENSET_TXIDLEEN_SHIFT (3U) +/*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). + */ #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) + #define USART_INTENSET_DELTACTSEN_MASK (0x20U) #define USART_INTENSET_DELTACTSEN_SHIFT (5U) +/*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. + */ #define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) + #define USART_INTENSET_TXDISEN_MASK (0x40U) #define USART_INTENSET_TXDISEN_SHIFT (6U) +/*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by + * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. + */ #define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) + #define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) #define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) +/*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection + * of a received break condition (break condition asserted or deasserted). + */ #define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) + #define USART_INTENSET_STARTEN_MASK (0x1000U) #define USART_INTENSET_STARTEN_SHIFT (12U) +/*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. + */ #define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) + #define USART_INTENSET_FRAMERREN_MASK (0x2000U) #define USART_INTENSET_FRAMERREN_SHIFT (13U) +/*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. + */ #define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) + #define USART_INTENSET_PARITYERREN_MASK (0x4000U) #define USART_INTENSET_PARITYERREN_SHIFT (14U) +/*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. + */ #define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) + #define USART_INTENSET_RXNOISEEN_MASK (0x8000U) #define USART_INTENSET_RXNOISEEN_SHIFT (15U) +/*! RXNOISEEN - When 1, enables an interrupt when noise is detected. See description of the RXNOISEINT bit in Table 354. + */ #define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) + #define USART_INTENSET_ABERREN_MASK (0x10000U) #define USART_INTENSET_ABERREN_SHIFT (16U) +/*! ABERREN - When 1, enables an interrupt when an auto baud error occurs. + */ #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) /*! @} */ /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ /*! @{ */ + #define USART_INTENCLR_TXIDLECLR_MASK (0x8U) #define USART_INTENCLR_TXIDLECLR_SHIFT (3U) +/*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) + #define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) #define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) +/*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) + #define USART_INTENCLR_TXDISCLR_MASK (0x40U) #define USART_INTENCLR_TXDISCLR_SHIFT (6U) +/*! TXDISCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK) + #define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) #define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) +/*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) + #define USART_INTENCLR_STARTCLR_MASK (0x1000U) #define USART_INTENCLR_STARTCLR_SHIFT (12U) +/*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) + #define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) #define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) +/*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) + #define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) #define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) +/*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) + #define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) #define USART_INTENCLR_RXNOISECLR_SHIFT (15U) +/*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) + #define USART_INTENCLR_ABERRCLR_MASK (0x10000U) #define USART_INTENCLR_ABERRCLR_SHIFT (16U) +/*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. + */ #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) /*! @} */ /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ /*! @{ */ + #define USART_BRG_BRGVAL_MASK (0xFFFFU) #define USART_BRG_BRGVAL_SHIFT (0U) +/*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on + * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is + * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART + * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. + */ #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) /*! @} */ /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ /*! @{ */ + #define USART_INTSTAT_TXIDLE_MASK (0x8U) #define USART_INTSTAT_TXIDLE_SHIFT (3U) +/*! TXIDLE - Transmitter Idle status. + */ #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) + #define USART_INTSTAT_DELTACTS_MASK (0x20U) #define USART_INTSTAT_DELTACTS_SHIFT (5U) +/*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. + */ #define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) + #define USART_INTSTAT_TXDISINT_MASK (0x40U) #define USART_INTSTAT_TXDISINT_SHIFT (6U) +/*! TXDISINT - Transmitter Disabled Interrupt flag. + */ #define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) + #define USART_INTSTAT_DELTARXBRK_MASK (0x800U) #define USART_INTSTAT_DELTARXBRK_SHIFT (11U) +/*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. + */ #define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) + #define USART_INTSTAT_START_MASK (0x1000U) #define USART_INTSTAT_START_SHIFT (12U) +/*! START - This bit is set when a start is detected on the receiver input. + */ #define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) + #define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) #define USART_INTSTAT_FRAMERRINT_SHIFT (13U) +/*! FRAMERRINT - Framing Error interrupt flag. + */ #define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) + #define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) #define USART_INTSTAT_PARITYERRINT_SHIFT (14U) +/*! PARITYERRINT - Parity Error interrupt flag. + */ #define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) + #define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) #define USART_INTSTAT_RXNOISEINT_SHIFT (15U) +/*! RXNOISEINT - Received Noise interrupt flag. + */ #define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) + #define USART_INTSTAT_ABERRINT_MASK (0x10000U) #define USART_INTSTAT_ABERRINT_SHIFT (16U) +/*! ABERRINT - Auto baud Error Interrupt flag. + */ #define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK) /*! @} */ /*! @name OSR - Oversample selection register for asynchronous communication. */ /*! @{ */ + #define USART_OSR_OSRVAL_MASK (0xFU) #define USART_OSR_OSRVAL_SHIFT (0U) +/*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to + * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive + * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. + */ #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) /*! @} */ /*! @name ADDR - Address register for automatic address matching. */ /*! @{ */ + #define USART_ADDR_ADDRESS_MASK (0xFFU) #define USART_ADDR_ADDRESS_SHIFT (0U) +/*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is + * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). + */ #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) /*! @} */ /*! @name FIFOCFG - FIFO configuration and enable register. */ /*! @{ */ + #define USART_FIFOCFG_ENABLETX_MASK (0x1U) #define USART_FIFOCFG_ENABLETX_SHIFT (0U) /*! ENABLETX - Enable the transmit FIFO. @@ -21778,6 +26177,7 @@ typedef struct { * 0b1..The transmit FIFO is enabled. */ #define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK) + #define USART_FIFOCFG_ENABLERX_MASK (0x2U) #define USART_FIFOCFG_ENABLERX_SHIFT (1U) /*! ENABLERX - Enable the receive FIFO. @@ -21785,9 +26185,14 @@ typedef struct { * 0b1..The receive FIFO is enabled. */ #define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK) + #define USART_FIFOCFG_SIZE_MASK (0x30U) #define USART_FIFOCFG_SIZE_SHIFT (4U) +/*! SIZE - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 + * entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART. + */ #define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK) + #define USART_FIFOCFG_DMATX_MASK (0x1000U) #define USART_FIFOCFG_DMATX_SHIFT (12U) /*! DMATX - DMA configuration for transmit. @@ -21795,6 +26200,7 @@ typedef struct { * 0b1..Trigger DMA for the transmit function if the FIFO is not full. Generally, data interrupts would be disabled if DMA is enabled. */ #define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK) + #define USART_FIFOCFG_DMARX_MASK (0x2000U) #define USART_FIFOCFG_DMARX_SHIFT (13U) /*! DMARX - DMA configuration for receive. @@ -21802,6 +26208,7 @@ typedef struct { * 0b1..Trigger DMA for the receive function if the FIFO is not empty. Generally, data interrupts would be disabled if DMA is enabled. */ #define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK) + #define USART_FIFOCFG_WAKETX_MASK (0x4000U) #define USART_FIFOCFG_WAKETX_SHIFT (14U) /*! WAKETX - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power @@ -21814,6 +26221,7 @@ typedef struct { * FIFOTRIG, even when the TXLVL interrupt is not enabled. */ #define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK) + #define USART_FIFOCFG_WAKERX_MASK (0x8000U) #define USART_FIFOCFG_WAKERX_SHIFT (15U) /*! WAKERX - Wake-up for receive FIFO level. This allows the device to be woken from reduced power @@ -21826,54 +26234,93 @@ typedef struct { * FIFOTRIG, even when the RXLVL interrupt is not enabled. */ #define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK) + #define USART_FIFOCFG_EMPTYTX_MASK (0x10000U) #define USART_FIFOCFG_EMPTYTX_SHIFT (16U) +/*! EMPTYTX - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied. + */ #define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK) + #define USART_FIFOCFG_EMPTYRX_MASK (0x20000U) #define USART_FIFOCFG_EMPTYRX_SHIFT (17U) -#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) -#define USART_FIFOCFG_POPDBG_MASK (0x40000U) -#define USART_FIFOCFG_POPDBG_SHIFT (18U) -/*! POPDBG - Pop FIFO for debug reads. - * 0b0..Debug reads of the FIFO do not pop the FIFO. - * 0b1..A debug read will cause the FIFO to pop. +/*! EMPTYRX - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied. */ -#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK) +#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK) /*! @} */ /*! @name FIFOSTAT - FIFO status register. */ /*! @{ */ + #define USART_FIFOSTAT_TXERR_MASK (0x1U) #define USART_FIFOSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. Will be set if a transmit FIFO error occurs. This could be an overflow + * caused by pushing data into a full FIFO, or by an underflow if the FIFO is empty when data is + * needed. Cleared by writing a 1 to this bit. + */ #define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK) + #define USART_FIFOSTAT_RXERR_MASK (0x2U) #define USART_FIFOSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. Will be set if a receive FIFO overflow occurs, caused by software or DMA + * not emptying the FIFO fast enough. Cleared by writing a 1 to this bit. + */ #define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK) + #define USART_FIFOSTAT_PERINT_MASK (0x8U) #define USART_FIFOSTAT_PERINT_SHIFT (3U) +/*! PERINT - Peripheral interrupt. When 1, this indicates that the peripheral function has asserted + * an interrupt. The details can be found by reading the peripheral's STAT register. + */ #define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK) + #define USART_FIFOSTAT_TXEMPTY_MASK (0x10U) #define USART_FIFOSTAT_TXEMPTY_SHIFT (4U) +/*! TXEMPTY - Transmit FIFO empty. When 1, the transmit FIFO is empty. The peripheral may still be processing the last piece of data. + */ #define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK) + #define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U) #define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U) +/*! TXNOTFULL - Transmit FIFO not full. When 1, the transmit FIFO is not full, so more data can be + * written. When 0, the transmit FIFO is full and another write would cause it to overflow. + */ #define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK) + #define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U) #define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U) +/*! RXNOTEMPTY - Receive FIFO not empty. When 1, the receive FIFO is not empty, so data can be read. When 0, the receive FIFO is empty. + */ #define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK) + #define USART_FIFOSTAT_RXFULL_MASK (0x80U) #define USART_FIFOSTAT_RXFULL_SHIFT (7U) +/*! RXFULL - Receive FIFO full. When 1, the receive FIFO is full. Data needs to be read out to + * prevent the peripheral from causing an overflow. + */ #define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK) + #define USART_FIFOSTAT_TXLVL_MASK (0x1F00U) #define USART_FIFOSTAT_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO current level. A 0 means the TX FIFO is currently empty, and the TXEMPTY + * and TXNOTFULL flags will be 1. Other values tell how much data is actually in the TX FIFO at + * the point where the read occurs. If the TX FIFO is full, the TXEMPTY and TXNOTFULL flags will be + * 0. + */ #define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK) + #define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U) #define USART_FIFOSTAT_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO current level. A 0 means the RX FIFO is currently empty, and the RXFULL and + * RXNOTEMPTY flags will be 0. Other values tell how much data is actually in the RX FIFO at the + * point where the read occurs. If the RX FIFO is full, the RXFULL and RXNOTEMPTY flags will be + * 1. + */ #define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK) /*! @} */ /*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */ /*! @{ */ + #define USART_FIFOTRIG_TXLVLENA_MASK (0x1U) #define USART_FIFOTRIG_TXLVLENA_SHIFT (0U) /*! TXLVLENA - Transmit FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -21882,6 +26329,7 @@ typedef struct { * 0b1..An trigger will be generated if the transmit FIFO level reaches the value specified by the TXLVL field in this register. */ #define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK) + #define USART_FIFOTRIG_RXLVLENA_MASK (0x2U) #define USART_FIFOTRIG_RXLVLENA_SHIFT (1U) /*! RXLVLENA - Receive FIFO level trigger enable. This trigger will become an interrupt if enabled @@ -21890,16 +26338,32 @@ typedef struct { * 0b1..An trigger will be generated if the receive FIFO level reaches the value specified by the RXLVL field in this register. */ #define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK) + #define USART_FIFOTRIG_TXLVL_MASK (0xF00U) #define USART_FIFOTRIG_TXLVL_SHIFT (8U) +/*! TXLVL - Transmit FIFO level trigger point. This field is used only when TXLVLENA = 1. If enabled + * to do so, the FIFO level can wake up the device just enough to perform DMA, then return to + * the reduced power mode. See Hardware Wake-up control register. 0 = trigger when the TX FIFO + * becomes empty. 1 = trigger when the TX FIFO level decreases to one entry. 15 = trigger when the TX + * FIFO level decreases to 15 entries (is no longer full). + */ #define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK) + #define USART_FIFOTRIG_RXLVL_MASK (0xF0000U) #define USART_FIFOTRIG_RXLVL_SHIFT (16U) +/*! RXLVL - Receive FIFO level trigger point. The RX FIFO level is checked when a new piece of data + * is received. This field is used only when RXLVLENA = 1. If enabled to do so, the FIFO level + * can wake up the device just enough to perform DMA, then return to the reduced power mode. See + * Hardware Wake-up control register. 0 = trigger when the RX FIFO has received one entry (is no + * longer empty). 1 = trigger when the RX FIFO has received two entries. 15 = trigger when the RX + * FIFO has received 16 entries (has become full). + */ #define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK) /*! @} */ /*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */ /*! @{ */ + #define USART_FIFOINTENSET_TXERR_MASK (0x1U) #define USART_FIFOINTENSET_TXERR_SHIFT (0U) /*! TXERR - Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. @@ -21907,6 +26371,7 @@ typedef struct { * 0b1..An interrupt will be generated when a transmit error occurs. */ #define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK) + #define USART_FIFOINTENSET_RXERR_MASK (0x2U) #define USART_FIFOINTENSET_RXERR_SHIFT (1U) /*! RXERR - Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. @@ -21914,6 +26379,7 @@ typedef struct { * 0b1..An interrupt will be generated when a receive error occurs. */ #define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK) + #define USART_FIFOINTENSET_TXLVL_MASK (0x4U) #define USART_FIFOINTENSET_TXLVL_SHIFT (2U) /*! TXLVL - Determines whether an interrupt occurs when a the transmit FIFO reaches the level @@ -21923,6 +26389,7 @@ typedef struct { * to the level specified by TXLVL in the FIFOTRIG register. */ #define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK) + #define USART_FIFOINTENSET_RXLVL_MASK (0x8U) #define USART_FIFOINTENSET_RXLVL_SHIFT (3U) /*! RXLVL - Determines whether an interrupt occurs when a the receive FIFO reaches the level @@ -21936,91 +26403,177 @@ typedef struct { /*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */ /*! @{ */ + #define USART_FIFOINTENCLR_TXERR_MASK (0x1U) #define USART_FIFOINTENCLR_TXERR_SHIFT (0U) +/*! TXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK) + #define USART_FIFOINTENCLR_RXERR_MASK (0x2U) #define USART_FIFOINTENCLR_RXERR_SHIFT (1U) +/*! RXERR - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK) + #define USART_FIFOINTENCLR_TXLVL_MASK (0x4U) #define USART_FIFOINTENCLR_TXLVL_SHIFT (2U) +/*! TXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK) + #define USART_FIFOINTENCLR_RXLVL_MASK (0x8U) #define USART_FIFOINTENCLR_RXLVL_SHIFT (3U) +/*! RXLVL - Writing one clears the corresponding bits in the FIFOINTENSET register. + */ #define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK) /*! @} */ /*! @name FIFOINTSTAT - FIFO interrupt status register. */ /*! @{ */ + #define USART_FIFOINTSTAT_TXERR_MASK (0x1U) #define USART_FIFOINTSTAT_TXERR_SHIFT (0U) +/*! TXERR - TX FIFO error. + */ #define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK) + #define USART_FIFOINTSTAT_RXERR_MASK (0x2U) #define USART_FIFOINTSTAT_RXERR_SHIFT (1U) +/*! RXERR - RX FIFO error. + */ #define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK) + #define USART_FIFOINTSTAT_TXLVL_MASK (0x4U) #define USART_FIFOINTSTAT_TXLVL_SHIFT (2U) +/*! TXLVL - Transmit FIFO level interrupt. + */ #define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK) + #define USART_FIFOINTSTAT_RXLVL_MASK (0x8U) #define USART_FIFOINTSTAT_RXLVL_SHIFT (3U) +/*! RXLVL - Receive FIFO level interrupt. + */ #define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK) + #define USART_FIFOINTSTAT_PERINT_MASK (0x10U) #define USART_FIFOINTSTAT_PERINT_SHIFT (4U) +/*! PERINT - Peripheral interrupt. + */ #define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK) /*! @} */ /*! @name FIFOWR - FIFO write data. */ /*! @{ */ + #define USART_FIFOWR_TXDATA_MASK (0x1FFU) #define USART_FIFOWR_TXDATA_SHIFT (0U) +/*! TXDATA - Transmit data to the FIFO. + */ #define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK) /*! @} */ /*! @name FIFORD - FIFO read data. */ /*! @{ */ + #define USART_FIFORD_RXDATA_MASK (0x1FFU) #define USART_FIFORD_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + */ #define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK) + #define USART_FIFORD_FRAMERR_MASK (0x2000U) #define USART_FIFORD_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ #define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK) + #define USART_FIFORD_PARITYERR_MASK (0x4000U) #define USART_FIFORD_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ #define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK) + #define USART_FIFORD_RXNOISE_MASK (0x8000U) #define USART_FIFORD_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. + */ #define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK) /*! @} */ /*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */ /*! @{ */ + #define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU) #define USART_FIFORDNOPOP_RXDATA_SHIFT (0U) +/*! RXDATA - Received data from the FIFO. The number of bits used depends on the DATALEN and PARITYSEL settings. + */ #define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK) + #define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U) #define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U) +/*! FRAMERR - Framing Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO, and indicates that the character was received with a missing stop bit at + * the expected location. This could be an indication of a baud rate or configuration mismatch + * with the transmitting source. + */ #define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK) + #define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U) #define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U) +/*! PARITYERR - Parity Error status flag. This bit reflects the status for the data it is read along + * with from the FIFO. This bit will be set when a parity error is detected in a received + * character. + */ #define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK) + #define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U) #define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U) +/*! RXNOISE - Received Noise flag. See description of the RxNoiseInt bit in Table 354. + */ #define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK) /*! @} */ +/*! @name FIFOSIZE - FIFO size register */ +/*! @{ */ + +#define USART_FIFOSIZE_FIFOSIZE_MASK (0x1FU) +#define USART_FIFOSIZE_FIFOSIZE_SHIFT (0U) +/*! FIFOSIZE - Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + */ +#define USART_FIFOSIZE_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSIZE_FIFOSIZE_SHIFT)) & USART_FIFOSIZE_FIFOSIZE_MASK) +/*! @} */ + /*! @name ID - Peripheral identification register. */ /*! @{ */ + #define USART_ID_APERTURE_MASK (0xFFU) #define USART_ID_APERTURE_SHIFT (0U) +/*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. + */ #define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK) + #define USART_ID_MINOR_REV_MASK (0xF00U) #define USART_ID_MINOR_REV_SHIFT (8U) +/*! MINOR_REV - Minor revision of module implementation. + */ #define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK) + #define USART_ID_MAJOR_REV_MASK (0xF000U) #define USART_ID_MAJOR_REV_SHIFT (12U) +/*! MAJOR_REV - Major revision of module implementation. + */ #define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK) + #define USART_ID_ID_MASK (0xFFFF0000U) #define USART_ID_ID_SHIFT (16U) +/*! ID - Module identifier for the selected function. + */ #define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK) /*! @} */ @@ -22031,7 +26584,7 @@ typedef struct { /* USART - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USART0 base address */ #define USART0_BASE (0x50086000u) /** Peripheral USART0 base address */ @@ -22187,15 +26740,31 @@ typedef struct { /*! @name DEVCMDSTAT - USB Device Command/Status register */ /*! @{ */ + #define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) #define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. After bus reset, the address is reset to 0x00. If the enable bit + * is set, the device will respond on packets for function address DEV_ADDR. When receiving a + * SetAddress Control Request from the USB host, software must program the new address before + * completing the status phase of the SetAddress Control Request. + */ #define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK) + #define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U) #define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. If this bit is set, the HW will start responding on packets for function address DEV_ADDR. + */ #define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK) + #define USB_DEVCMDSTAT_SETUP_MASK (0x100U) #define USB_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. If a SETUP token is received and acknowledged by the device, this + * bit is set. As long as this bit is set all received IN and OUT tokens will be NAKed by HW. SW + * must clear this bit by writing a one. If this bit is zero, HW will handle the tokens to the + * CTRL EP0 as indicated by the CTRL EP0 IN and OUT data information programmed by SW. + */ #define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK) + #define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) #define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) /*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on: @@ -22203,6 +26772,7 @@ typedef struct { * 0b1..USB_NEEDCLK always 1. Clock will not be stopped in case of suspend. */ #define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK) + #define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U) #define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U) /*! LPM_SUP - LPM Supported: @@ -22210,6 +26780,7 @@ typedef struct { * 0b1..LPM supported. */ #define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK) + #define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) #define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) /*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP @@ -22217,6 +26788,7 @@ typedef struct { * 0b1..Both acknowledged and NAKed packets generate interrupts. */ #define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK) + #define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) #define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) /*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP @@ -22224,6 +26796,7 @@ typedef struct { * 0b1..Both acknowledged and NAKed packets generate interrupts. */ #define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK) + #define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) #define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) /*! INTONNAK_CO - Interrupt on NAK for control OUT EP @@ -22231,6 +26804,7 @@ typedef struct { * 0b1..Both acknowledged and NAKed packets generate interrupts. */ #define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK) + #define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) #define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) /*! INTONNAK_CI - Interrupt on NAK for control IN EP @@ -22238,37 +26812,93 @@ typedef struct { * 0b1..Both acknowledged and NAKed packets generate interrupts. */ #define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK) + #define USB_DEVCMDSTAT_DCON_MASK (0x10000U) #define USB_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. The connect bit must be set by SW to indicate that the device + * must signal a connect. The pull-up resistor on USB_DP will be enabled when this bit is set and + * the VBUSDEBOUNCED bit is one. + */ #define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK) + #define USB_DEVCMDSTAT_DSUS_MASK (0x20000U) #define USB_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. The suspend bit indicates the current suspend state. It is set + * to 1 when the device hasn't seen any activity on its upstream port for more than 3 + * milliseconds. It is reset to 0 on any activity. When the device is suspended (Suspend bit DSUS = 1) and + * the software writes a 0 to it, the device will generate a remote wake-up. This will only happen + * when the device is connected (Connect bit = 1). When the device is not connected or not + * suspended, a writing a 0 has no effect. Writing a 1 never has an effect. + */ #define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK) + #define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) #define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. This bit represents the current LPM suspend state. It is + * set to 1 by HW when the device has acknowledged the LPM request from the USB host and the + * Token Retry Time of 10 ms has elapsed. When the device is in the LPM suspended state (LPM suspend + * bit = 1) and the software writes a zero to this bit, the device will generate a remote + * walk-up. Software can only write a zero to this bit when the LPM_REWP bit is set to 1. HW resets this + * bit when it receives a host initiated resume. HW only updates the LPM_SUS bit when the + * LPM_SUPP bit is equal to one. + */ #define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK) + #define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) #define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. HW sets this bit to one when the bRemoteWake + * bit in the LPM extended token is set to 1. HW will reset this bit to 0 when it receives the + * host initiated LPM resume, when a remote wake-up is sent by the device or when a USB bus reset + * is received. Software can use this bit to check if the remote wake-up feature is enabled by the + * host for the LPM transaction. + */ #define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK) + #define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U) #define USB_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. The Connect Change bit is set when the device's pull-up + * resistor is disconnected because VBus disappeared. The bit is reset by writing a one to it. + */ #define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK) + #define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) #define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. The suspend change bit is set to 1 when the suspend bit + * toggles. The suspend bit can toggle because: - The device goes in the suspended state - The + * device is disconnected - The device receives resume signaling on its upstream port. The bit is + * reset by writing a one to it. + */ #define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK) + #define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U) #define USB_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. This bit is set when the device received a bus reset. On + * a bus reset the device will automatically go to the default state (unconfigured and responding + * to address 0). The bit is reset by writing a one to it. + */ #define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK) + #define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U) #define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U) +/*! VBUSDEBOUNCED - This bit indicates if Vbus is detected or not. The bit raises immediately when + * Vbus becomes high. It drops to zero if Vbus is low for at least 3 ms. If this bit is high and + * the DCon bit is set, the HW will enable the pull-up resistor to signal a connect. + */ #define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK) /*! @} */ /*! @name INFO - USB Info register */ /*! @{ */ + #define USB_INFO_FRAME_NR_MASK (0x7FFU) #define USB_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. This contains the frame number of the last successfully received SOF. + * In case no SOF was received by the device at the beginning of a frame, the frame number + * returned is that of the last successfully received SOF. In case the SOF frame number contained a CRC + * error, the frame number returned will be the corrupted frame number as received by the device. + */ #define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK) + #define USB_INFO_ERR_CODE_MASK (0x7800U) #define USB_INFO_ERR_CODE_SHIFT (11U) /*! ERR_CODE - The error code which last occurred: @@ -22290,132 +26920,285 @@ typedef struct { * 0b1111..Wrong data toggle */ #define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK) + #define USB_INFO_MINREV_MASK (0xFF0000U) #define USB_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor Revision. + */ #define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK) + #define USB_INFO_MAJREV_MASK (0xFF000000U) #define USB_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major Revision. + */ #define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK) /*! @} */ /*! @name EPLISTSTART - USB EP Command/Status List start address */ /*! @{ */ + #define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U) #define USB_EPLISTSTART_EP_LIST_SHIFT (8U) +/*! EP_LIST - Start address of the USB EP Command/Status List. + */ #define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK) /*! @} */ /*! @name DATABUFSTART - USB Data buffer start address */ /*! @{ */ + #define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U) #define USB_DATABUFSTART_DA_BUF_SHIFT (22U) +/*! DA_BUF - Start address of the buffer pointer page where all endpoint data buffers are located. + */ #define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK) /*! @} */ /*! @name LPM - USB Link Power Management register */ /*! @{ */ + #define USB_LPM_HIRD_HW_MASK (0xFU) #define USB_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. This is the HIRD value from the last received LPM token + */ #define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK) + #define USB_LPM_HIRD_SW_MASK (0xF0U) #define USB_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. This is the time duration required by the USB + * device system to come out of LPM initiated suspend after receiving the host initiated LPM resume. + */ #define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK) + #define USB_LPM_DATA_PENDING_MASK (0x100U) #define USB_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. If LPM supported bit is set to one and + * this bit is zero, HW will return an ACK handshake on every LPM token it receives. If SW has + * still data pending and LPM is supported, it must set this bit to 1. + */ #define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK) /*! @} */ /*! @name EPSKIP - USB Endpoint skip */ /*! @{ */ + #define USB_EPSKIP_SKIP_MASK (0x3FFU) #define USB_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. When HW has + * deactivated the endpoint, it will clear this bit, but it will not modify the EPINUSE bit. An + * interrupt will be generated when the Active bit goes from 1 to 0. Note: In case of double-buffering, + * HW will only clear the Active bit of the buffer indicated by the EPINUSE bit. + */ #define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK) /*! @} */ /*! @name EPINUSE - USB Endpoint Buffer in use */ /*! @{ */ + #define USB_EPINUSE_BUF_MASK (0x3FCU) #define USB_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. 0: HW is accessing buffer + * 0. 1: HW is accessing buffer 1. + */ #define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK) /*! @} */ /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ /*! @{ */ + #define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU) #define USB_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. 0: Single-buffer. 1: + * Double-buffer. If the bit is set to single-buffer (0), it will not toggle the corresponding + * EPINUSE bit when it clears the active bit. If the bit is set to double-buffer (1), HW will toggle + * the EPINUSE bit when it clears the Active bit for the buffer. + */ #define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK) /*! @} */ /*! @name INTSTAT - USB interrupt status register */ /*! @{ */ + #define USB_INTSTAT_EP0OUT_MASK (0x1U) #define USB_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. This bit will be set + * if NBytes transitions to zero or the skip bit is set by software or a SETUP packet is + * successfully received for the control EP0. If the IntOnNAK_CO is set, this bit will also be set when a + * NAK is transmitted for the Control EP0 OUT direction. Software can clear this bit by writing a + * one to it. + */ #define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK) + #define USB_INTSTAT_EP0IN_MASK (0x2U) #define USB_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. This bit will be set if + * NBytes transitions to zero or the skip bit is set by software. If the IntOnNAK_CI is set, this + * bit will also be set when a NAK is transmitted for the Control EP0 IN direction. Software can + * clear this bit by writing a one to it. + */ #define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK) + #define USB_INTSTAT_EP1OUT_MASK (0x4U) #define USB_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP1 OUT direction. Software can clear this bit by + * writing a one to it. + */ #define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK) + #define USB_INTSTAT_EP1IN_MASK (0x8U) #define USB_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP1 IN direction. Software can clear this bit by writing + * a one to it. + */ #define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK) + #define USB_INTSTAT_EP2OUT_MASK (0x10U) #define USB_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP2 OUT direction. Software can clear this bit by + * writing a one to it. + */ #define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK) + #define USB_INTSTAT_EP2IN_MASK (0x20U) #define USB_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP2 IN direction. Software can clear this bit by writing + * a one to it. + */ #define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK) + #define USB_INTSTAT_EP3OUT_MASK (0x40U) #define USB_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP3 OUT direction. Software can clear this bit by + * writing a one to it. + */ #define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK) + #define USB_INTSTAT_EP3IN_MASK (0x80U) #define USB_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP3 IN direction. Software can clear this bit by writing + * a one to it. + */ #define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK) + #define USB_INTSTAT_EP4OUT_MASK (0x100U) #define USB_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes + * transitions to zero or the skip bit is set by software. If the IntOnNAK_AO is set, this bit will also be + * set when a NAK is transmitted for the EP4 OUT direction. Software can clear this bit by + * writing a one to it. + */ #define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK) + #define USB_INTSTAT_EP4IN_MASK (0x200U) #define USB_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. This bit will be set if the + * corresponding Active bit is cleared by HW. This is done in case the programmed NBytes transitions + * to zero or the skip bit is set by software. If the IntOnNAK_AI is set, this bit will also be + * set when a NAK is transmitted for the EP4 IN direction. Software can clear this bit by writing + * a one to it. + */ #define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK) + #define USB_INTSTAT_FRAME_INT_MASK (0x40000000U) #define USB_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. This bit is set to one every millisecond when the VbusDebounced bit + * and the DCON bit are set. This bit can be used by software when handling isochronous + * endpoints. Software can clear this bit by writing a one to it. + */ #define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK) + #define USB_INTSTAT_DEV_INT_MASK (0x80000000U) #define USB_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. This bit is set by HW when one of the bits in the Device + * Status Change register are set. Software can clear this bit by writing a one to it. + */ #define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK) /*! @} */ /*! @name INTEN - USB interrupt enable register */ /*! @{ */ + #define USB_INTEN_EP_INT_EN_MASK (0x3FFU) #define USB_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ #define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK) + #define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U) #define USB_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt + * routing bit. + */ #define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK) + #define USB_INTEN_DEV_INT_EN_MASK (0x80000000U) #define USB_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line indicated by the corresponding USB interrupt routing + * bit. + */ #define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK) /*! @} */ /*! @name INTSETSTAT - USB set interrupt status register */ /*! @{ */ + #define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU) #define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status register + * is returned. + */ #define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK) + #define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) #define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ #define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK) + #define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) #define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt + * status bit is set. When this register is read, the same value as the USB interrupt status + * register is returned. + */ #define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK) /*! @} */ /*! @name EPTOGGLE - USB Endpoint toggle register */ /*! @{ */ + #define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU) #define USB_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + */ #define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK) /*! @} */ @@ -22426,7 +27209,7 @@ typedef struct { /* USB - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USB0 base address */ #define USB0_BASE (0x50084000u) /** Peripheral USB0 base address */ @@ -22480,15 +27263,15 @@ typedef struct { __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */ __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */ __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */ - __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ + __I uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */ __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */ __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */ __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */ __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */ - __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ + __I uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */ __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */ - __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ - __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ + __I uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */ + __I uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */ __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */ __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */ __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */ @@ -22510,351 +27293,625 @@ typedef struct { /*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */ /*! @{ */ + #define USBFSH_HCREVISION_REV_MASK (0xFFU) #define USBFSH_HCREVISION_REV_SHIFT (0U) +/*! REV - Revision. + */ #define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK) /*! @} */ /*! @name HCCONTROL - Defines the operating modes of the HC */ /*! @{ */ + #define USBFSH_HCCONTROL_CBSR_MASK (0x3U) #define USBFSH_HCCONTROL_CBSR_SHIFT (0U) +/*! CBSR - ControlBulkServiceRatio. + */ #define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK) + #define USBFSH_HCCONTROL_PLE_MASK (0x4U) #define USBFSH_HCCONTROL_PLE_SHIFT (2U) +/*! PLE - PeriodicListEnable. + */ #define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK) + #define USBFSH_HCCONTROL_IE_MASK (0x8U) #define USBFSH_HCCONTROL_IE_SHIFT (3U) +/*! IE - IsochronousEnable. + */ #define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK) + #define USBFSH_HCCONTROL_CLE_MASK (0x10U) #define USBFSH_HCCONTROL_CLE_SHIFT (4U) +/*! CLE - ControlListEnable. + */ #define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK) + #define USBFSH_HCCONTROL_BLE_MASK (0x20U) #define USBFSH_HCCONTROL_BLE_SHIFT (5U) +/*! BLE - BulkListEnable This bit is set to enable the processing of the Bulk list in the next Frame. + */ #define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK) + #define USBFSH_HCCONTROL_HCFS_MASK (0xC0U) #define USBFSH_HCCONTROL_HCFS_SHIFT (6U) +/*! HCFS - HostControllerFunctionalState for USB 00b: USBRESET 01b: USBRESUME 10b: USBOPERATIONAL + * 11b: USBSUSPEND A transition to USBOPERATIONAL from another state causes SOFgeneration to begin + * 1 ms later. + */ #define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK) + #define USBFSH_HCCONTROL_IR_MASK (0x100U) #define USBFSH_HCCONTROL_IR_SHIFT (8U) +/*! IR - InterruptRouting This bit determines the routing of interrupts generated by events registered in HcInterruptStatus. + */ #define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK) + #define USBFSH_HCCONTROL_RWC_MASK (0x200U) #define USBFSH_HCCONTROL_RWC_SHIFT (9U) +/*! RWC - RemoteWakeupConnected This bit indicates whether HC supports remote wake-up signaling. + */ #define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK) + #define USBFSH_HCCONTROL_RWE_MASK (0x400U) #define USBFSH_HCCONTROL_RWE_SHIFT (10U) +/*! RWE - RemoteWakeupEnable This bit is used by HCD to enable or disable the remote wake-up feature + * upon the detection of upstream resume signaling. + */ #define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK) /*! @} */ /*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */ /*! @{ */ + #define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U) #define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U) +/*! HCR - HostControllerReset This bit is set by HCD to initiate a software reset of HC. + */ #define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK) + #define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U) #define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U) +/*! CLF - ControlListFilled This bit is used to indicate whether there are any TDs on the Control list. + */ #define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK) + #define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U) #define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U) +/*! BLF - BulkListFilled This bit is used to indicate whether there are any TDs on the Bulk list. + */ #define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK) + #define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U) #define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U) +/*! OCR - OwnershipChangeRequest This bit is set by an OS HCD to request a change of control of the HC. + */ #define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK) + #define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U) #define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U) +/*! SOC - SchedulingOverrunCount These bits are incremented on each scheduling overrun error. + */ #define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK) /*! @} */ /*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */ /*! @{ */ + #define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U) #define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U) +/*! SO - SchedulingOverrun This bit is set when the USB schedule for the current Frame overruns and + * after the update of HccaFrameNumber. + */ #define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK) + #define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U) #define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U) +/*! WDH - WritebackDoneHead This bit is set immediately after HC has written HcDoneHead to HccaDoneHead. + */ #define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK) + #define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U) #define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U) +/*! SF - StartofFrame This bit is set by HC at each start of a frame and after the update of HccaFrameNumber. + */ #define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK) + #define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U) #define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U) +/*! RD - ResumeDetected This bit is set when HC detects that a device on the USB is asserting resume signaling. + */ #define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK) + #define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U) #define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U) +/*! UE - UnrecoverableError This bit is set when HC detects a system error not related to USB. + */ #define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK) + #define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U) #define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U) +/*! FNO - FrameNumberOverflow This bit is set when the MSb of HcFmNumber (bit 15) changes value, + * from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been updated. + */ #define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK) + #define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U) #define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U) +/*! RHSC - RootHubStatusChange This bit is set when the content of HcRhStatus or the content of any + * of HcRhPortStatus[NumberofDownstreamPort] has changed. + */ #define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK) + #define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U) #define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U) +/*! OC - OwnershipChange This bit is set by HC when HCD sets the OwnershipChangeRequest field in HcCommandStatus. + */ #define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK) /*! @} */ /*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */ /*! @{ */ + #define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U) #define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK) + #define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U) #define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK) + #define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U) #define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK) + #define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U) #define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK) + #define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U) #define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK) + #define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U) #define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK) + #define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U) #define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK) + #define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U) #define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + */ #define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK) + #define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U) #define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U) +/*! MIE - Master Interrupt Enable. + */ #define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK) /*! @} */ /*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */ /*! @{ */ + #define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U) #define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U) +/*! SO - Scheduling Overrun interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK) + #define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U) #define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U) +/*! WDH - HcDoneHead Writeback interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK) + #define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U) #define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U) +/*! SF - Start of Frame interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK) + #define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U) #define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U) +/*! RD - Resume Detect interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK) + #define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U) #define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U) +/*! UE - Unrecoverable Error interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK) + #define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U) #define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U) +/*! FNO - Frame Number Overflow interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK) + #define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U) #define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U) +/*! RHSC - Root Hub Status Change interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK) + #define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U) #define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U) +/*! OC - Ownership Change interrupt. + */ #define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK) + #define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U) #define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U) +/*! MIE - A 0 written to this field is ignored by HC. + */ #define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK) /*! @} */ /*! @name HCHCCA - Contains the physical address of the host controller communication area */ /*! @{ */ + #define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U) #define USBFSH_HCHCCA_HCCA_SHIFT (8U) +/*! HCCA - Base address of the Host Controller Communication Area. + */ #define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK) /*! @} */ /*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */ /*! @{ */ + #define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U) #define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U) +/*! PCED - The content of this register is updated by HC after a periodic ED is processed. + */ #define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK) /*! @} */ /*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */ /*! @{ */ + #define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U) #define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U) +/*! CHED - HC traverses the Control list starting with the HcControlHeadED pointer. + */ #define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK) /*! @} */ /*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */ /*! @{ */ + #define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U) #define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U) +/*! CCED - ControlCurrentED. + */ #define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK) /*! @} */ /*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */ /*! @{ */ + #define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U) #define USBFSH_HCBULKHEADED_BHED_SHIFT (4U) +/*! BHED - BulkHeadED HC traverses the bulk list starting with the HcBulkHeadED pointer. + */ #define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK) /*! @} */ /*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */ /*! @{ */ + #define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U) #define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U) +/*! BCED - BulkCurrentED This is advanced to the next ED after the HC has served the current one. + */ #define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK) /*! @} */ /*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */ /*! @{ */ + #define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U) #define USBFSH_HCDONEHEAD_DH_SHIFT (4U) +/*! DH - DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. + */ #define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK) /*! @} */ /*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */ /*! @{ */ + #define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU) #define USBFSH_HCFMINTERVAL_FI_SHIFT (0U) +/*! FI - FrameInterval This specifies the interval between two consecutive SOFs in bit times. + */ #define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK) + #define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U) #define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U) +/*! FSMPS - FSLargestDataPacket This field specifies a value which is loaded into the Largest Data + * Packet Counter at the beginning of each frame. + */ #define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK) + #define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U) #define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U) +/*! FIT - FrameIntervalToggle HCD toggles this bit whenever it loads a new value to FrameInterval. + */ #define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK) /*! @} */ /*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */ /*! @{ */ + #define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU) #define USBFSH_HCFMREMAINING_FR_SHIFT (0U) +/*! FR - FrameRemaining This counter is decremented at each bit time. + */ #define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK) + #define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U) #define USBFSH_HCFMREMAINING_FRT_SHIFT (31U) +/*! FRT - FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval + * whenever FrameRemaining reaches 0. + */ #define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK) /*! @} */ /*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */ /*! @{ */ + #define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU) #define USBFSH_HCFMNUMBER_FN_SHIFT (0U) +/*! FN - FrameNumber This is incremented when HcFmRemaining is re-loaded. + */ #define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK) /*! @} */ /*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */ /*! @{ */ + #define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU) #define USBFSH_HCPERIODICSTART_PS_SHIFT (0U) +/*! PS - PeriodicStart After a hardware reset, this field is cleared and then set by HCD during the HC initialization. + */ #define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK) /*! @} */ /*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */ /*! @{ */ + #define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU) #define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U) +/*! LST - LSThreshold This field contains a value which is compared to the FrameRemaining field + * prior to initiating a Low Speed transaction. + */ #define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK) /*! @} */ /*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */ /*! @{ */ + #define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU) #define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U) +/*! NDP - NumberDownstreamPorts These bits specify the number of downstream ports supported by the root hub. + */ #define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK) + #define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U) #define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U) +/*! PSM - PowerSwitchingMode This bit is used to specify how the power switching of the root hub ports is controlled. + */ #define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK) + #define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U) #define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U) +/*! NPS - NoPowerSwitching These bits are used to specify whether power switching is supported or port are always powered. + */ #define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK) + #define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U) #define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U) +/*! DT - DeviceType This bit specifies that the root hub is not a compound device. + */ #define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK) + #define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U) #define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U) +/*! OCPM - OverCurrentProtectionMode This bit describes how the overcurrent status for the root hub ports are reported. + */ #define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK) + #define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U) #define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U) +/*! NOCP - NoOverCurrentProtection This bit describes how the overcurrent status for the root hub ports are reported. + */ #define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK) + #define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U) #define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U) +/*! POTPGT - PowerOnToPowerGoodTime This byte specifies the duration the HCD has to wait before + * accessing a powered-on port of the root hub. + */ #define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK) /*! @} */ /*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */ /*! @{ */ + #define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU) #define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U) +/*! DR - DeviceRemovable Each bit is dedicated to a port of the Root Hub. + */ #define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK) + #define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U) #define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U) +/*! PPCM - PortPowerControlMask Each bit indicates if a port is affected by a global power control + * command when PowerSwitchingMode is set. + */ #define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK) /*! @} */ /*! @name HCRHSTATUS - This register is divided into two parts */ /*! @{ */ + #define USBFSH_HCRHSTATUS_LPS_MASK (0x1U) #define USBFSH_HCRHSTATUS_LPS_SHIFT (0U) +/*! LPS - (read) LocalPowerStatus The Root Hub does not support the local power status feature; + * thus, this bit is always read as 0. + */ #define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK) + #define USBFSH_HCRHSTATUS_OCI_MASK (0x2U) #define USBFSH_HCRHSTATUS_OCI_SHIFT (1U) +/*! OCI - OverCurrentIndicator This bit reports overcurrent conditions when the global reporting is implemented. + */ #define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK) + #define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U) #define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U) +/*! DRWE - (read) DeviceRemoteWakeupEnable This bit enables a ConnectStatusChange bit as a resume + * event, causing a USBSUSPEND to USBRESUME state transition and setting the ResumeDetected + * interrupt. + */ #define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK) + #define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U) #define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U) +/*! LPSC - (read) LocalPowerStatusChange The root hub does not support the local power status feature. + */ #define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK) + #define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U) #define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U) +/*! OCIC - OverCurrentIndicatorChange This bit is set by hardware when a change has occurred to the OCI field of this register. + */ #define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK) + #define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U) #define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U) +/*! CRWE - (write) ClearRemoteWakeupEnable Writing a 1 clears DeviceRemoveWakeupEnable. + */ #define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK) /*! @} */ /*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */ /*! @{ */ + #define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U) #define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U) +/*! CCS - (read) CurrentConnectStatus This bit reflects the current state of the downstream port. + */ #define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK) + #define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U) #define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U) +/*! PES - (read) PortEnableStatus This bit indicates whether the port is enabled or disabled. + */ #define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK) + #define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U) #define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U) +/*! PSS - (read) PortSuspendStatus This bit indicates the port is suspended or in the resume sequence. + */ #define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK) + #define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U) #define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U) +/*! POCI - (read) PortOverCurrentIndicator This bit is only valid when the Root Hub is configured in + * such a way that overcurrent conditions are reported on a per-port basis. + */ #define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK) + #define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U) #define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U) +/*! PRS - (read) PortResetStatus When this bit is set by a write to SetPortReset, port reset signaling is asserted. + */ #define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK) + #define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U) #define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U) +/*! PPS - (read) PortPowerStatus This bit reflects the porta's power status, regardless of the type + * of power switching implemented. + */ #define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK) + #define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U) #define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U) +/*! LSDA - (read) LowSpeedDeviceAttached This bit indicates the speed of the device attached to this port. + */ #define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK) + #define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U) #define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U) +/*! CSC - ConnectStatusChange This bit is set whenever a connect or disconnect event occurs. + */ #define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK) + #define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U) #define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U) +/*! PESC - PortEnableStatusChange This bit is set when hardware events cause the PortEnableStatus bit to be cleared. + */ #define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK) + #define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U) #define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U) +/*! PSSC - PortSuspendStatusChange This bit is set when the full resume sequence is completed. + */ #define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK) + #define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U) #define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U) +/*! OCIC - PortOverCurrentIndicatorChange This bit is valid only if overcurrent conditions are reported on a per-port basis. + */ #define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK) + #define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U) #define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U) +/*! PRSC - PortResetStatusChange This bit is set at the end of the 10 ms port reset signal. + */ #define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK) /*! @} */ /*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ /*! @{ */ + #define USBFSH_PORTMODE_ID_MASK (0x1U) #define USBFSH_PORTMODE_ID_SHIFT (0U) +/*! ID - Port ID pin value. + */ #define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK) + #define USBFSH_PORTMODE_ID_EN_MASK (0x100U) #define USBFSH_PORTMODE_ID_EN_SHIFT (8U) +/*! ID_EN - Port ID pin pull-up enable. + */ #define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK) + #define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) #define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - 1: device 0: host. + */ #define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK) /*! @} */ @@ -22865,7 +27922,7 @@ typedef struct { /* USBFSH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USBFSH base address */ #define USBFSH_BASE (0x500A2000u) /** Peripheral USBFSH base address */ @@ -22925,8 +27982,6 @@ typedef struct { __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */ uint8_t RESERVED_0[8]; __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */ - uint8_t RESERVED_1[4]; - __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */ } USBHSD_Type; /* ---------------------------------------------------------------------------- @@ -22940,236 +27995,382 @@ typedef struct { /*! @name DEVCMDSTAT - USB Device Command/Status register */ /*! @{ */ + #define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU) #define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U) +/*! DEV_ADDR - USB device address. + */ #define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK) + #define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U) #define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U) +/*! DEV_EN - USB device enable. + */ #define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK) + #define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U) #define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U) +/*! SETUP - SETUP token received. + */ #define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK) + #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U) #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U) +/*! FORCE_NEEDCLK - Forces the NEEDCLK output to always be on:. + */ #define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U) -#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK) + #define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U) #define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U) +/*! LPM_SUP - LPM Supported:. + */ #define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK) + #define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U) #define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U) +/*! INTONNAK_AO - Interrupt on NAK for interrupt and bulk OUT EP:. + */ #define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK) + #define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U) #define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U) +/*! INTONNAK_AI - Interrupt on NAK for interrupt and bulk IN EP:. + */ #define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK) + #define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U) #define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U) +/*! INTONNAK_CO - Interrupt on NAK for control OUT EP:. + */ #define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK) + #define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U) #define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U) +/*! INTONNAK_CI - Interrupt on NAK for control IN EP:. + */ #define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK) + #define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U) #define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U) +/*! DCON - Device status - connect. + */ #define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK) + #define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U) #define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U) +/*! DSUS - Device status - suspend. + */ #define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK) + #define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U) #define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U) +/*! LPM_SUS - Device status - LPM Suspend. + */ #define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK) + #define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U) #define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U) +/*! LPM_REWP - LPM Remote Wake-up Enabled by USB host. + */ #define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK) + #define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U) #define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U) +/*! Speed - This field indicates the speed at which the device operates: 00b: reserved 01b: + * full-speed 10b: high-speed 11b: super-speed (reserved for future use). + */ #define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK) + #define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U) #define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U) +/*! DCON_C - Device status - connect change. + */ #define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK) + #define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U) #define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U) +/*! DSUS_C - Device status - suspend change. + */ #define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK) + #define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U) #define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U) +/*! DRES_C - Device status - reset change. + */ #define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK) + #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U) #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U) +/*! VBUS_DEBOUNCED - This bit indicates if VBUS is detected or not. + */ #define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK) + #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U) #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U) +/*! PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. + * 0b000..Test mode disabled. + * 0b001..Test_J. + * 0b010..Test_K. + * 0b011..Test_SE0_NAK. + * 0b100..Test_Packet. + * 0b101..Test_Force_Enable. + */ #define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK) /*! @} */ /*! @name INFO - USB Info register */ /*! @{ */ + #define USBHSD_INFO_FRAME_NR_MASK (0x7FFU) #define USBHSD_INFO_FRAME_NR_SHIFT (0U) +/*! FRAME_NR - Frame number. + */ #define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK) + #define USBHSD_INFO_ERR_CODE_MASK (0x7800U) #define USBHSD_INFO_ERR_CODE_SHIFT (11U) +/*! ERR_CODE - The error code which last occurred:. + */ #define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK) -#define USBHSD_INFO_Minrev_MASK (0xFF0000U) -#define USBHSD_INFO_Minrev_SHIFT (16U) -#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK) -#define USBHSD_INFO_Majrev_MASK (0xFF000000U) -#define USBHSD_INFO_Majrev_SHIFT (24U) -#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK) + +#define USBHSD_INFO_MINREV_MASK (0xFF0000U) +#define USBHSD_INFO_MINREV_SHIFT (16U) +/*! MINREV - Minor revision. + */ +#define USBHSD_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MINREV_SHIFT)) & USBHSD_INFO_MINREV_MASK) + +#define USBHSD_INFO_MAJREV_MASK (0xFF000000U) +#define USBHSD_INFO_MAJREV_SHIFT (24U) +/*! MAJREV - Major revision. + */ +#define USBHSD_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_MAJREV_SHIFT)) & USBHSD_INFO_MAJREV_MASK) /*! @} */ /*! @name EPLISTSTART - USB EP Command/Status List start address */ /*! @{ */ + #define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U) #define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U) +/*! EP_LIST_PRG - Programmable portion of the USB EP Command/Status List address. + */ #define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK) + #define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U) #define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U) +/*! EP_LIST_FIXED - Fixed portion of USB EP Command/Status List address. + */ #define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK) /*! @} */ /*! @name DATABUFSTART - USB Data buffer start address */ /*! @{ */ + #define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU) #define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U) +/*! DA_BUF - Start address of the memory page where all endpoint data buffers are located. + */ #define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK) /*! @} */ /*! @name LPM - USB Link Power Management register */ /*! @{ */ + #define USBHSD_LPM_HIRD_HW_MASK (0xFU) #define USBHSD_LPM_HIRD_HW_SHIFT (0U) +/*! HIRD_HW - Host Initiated Resume Duration - HW. + */ #define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK) + #define USBHSD_LPM_HIRD_SW_MASK (0xF0U) #define USBHSD_LPM_HIRD_SW_SHIFT (4U) +/*! HIRD_SW - Host Initiated Resume Duration - SW. + */ #define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK) + #define USBHSD_LPM_DATA_PENDING_MASK (0x100U) #define USBHSD_LPM_DATA_PENDING_SHIFT (8U) +/*! DATA_PENDING - As long as this bit is set to one and LPM supported bit is set to one, HW will + * return a NYET handshake on every LPM token it receives. + */ #define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK) /*! @} */ /*! @name EPSKIP - USB Endpoint skip */ /*! @{ */ + #define USBHSD_EPSKIP_SKIP_MASK (0xFFFU) #define USBHSD_EPSKIP_SKIP_SHIFT (0U) +/*! SKIP - Endpoint skip: Writing 1 to one of these bits, will indicate to HW that it must + * deactivate the buffer assigned to this endpoint and return control back to software. + */ #define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK) /*! @} */ /*! @name EPINUSE - USB Endpoint Buffer in use */ /*! @{ */ + #define USBHSD_EPINUSE_BUF_MASK (0xFFCU) #define USBHSD_EPINUSE_BUF_SHIFT (2U) +/*! BUF - Buffer in use: This register has one bit per physical endpoint. + */ #define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK) /*! @} */ /*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */ /*! @{ */ + #define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU) #define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U) +/*! BUF_SB - Buffer usage: This register has one bit per physical endpoint. + */ #define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK) /*! @} */ /*! @name INTSTAT - USB interrupt status register */ /*! @{ */ + #define USBHSD_INTSTAT_EP0OUT_MASK (0x1U) #define USBHSD_INTSTAT_EP0OUT_SHIFT (0U) +/*! EP0OUT - Interrupt status register bit for the Control EP0 OUT direction. + */ #define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK) + #define USBHSD_INTSTAT_EP0IN_MASK (0x2U) #define USBHSD_INTSTAT_EP0IN_SHIFT (1U) +/*! EP0IN - Interrupt status register bit for the Control EP0 IN direction. + */ #define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK) + #define USBHSD_INTSTAT_EP1OUT_MASK (0x4U) #define USBHSD_INTSTAT_EP1OUT_SHIFT (2U) +/*! EP1OUT - Interrupt status register bit for the EP1 OUT direction. + */ #define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK) + #define USBHSD_INTSTAT_EP1IN_MASK (0x8U) #define USBHSD_INTSTAT_EP1IN_SHIFT (3U) +/*! EP1IN - Interrupt status register bit for the EP1 IN direction. + */ #define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK) + #define USBHSD_INTSTAT_EP2OUT_MASK (0x10U) #define USBHSD_INTSTAT_EP2OUT_SHIFT (4U) +/*! EP2OUT - Interrupt status register bit for the EP2 OUT direction. + */ #define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK) + #define USBHSD_INTSTAT_EP2IN_MASK (0x20U) #define USBHSD_INTSTAT_EP2IN_SHIFT (5U) +/*! EP2IN - Interrupt status register bit for the EP2 IN direction. + */ #define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK) + #define USBHSD_INTSTAT_EP3OUT_MASK (0x40U) #define USBHSD_INTSTAT_EP3OUT_SHIFT (6U) +/*! EP3OUT - Interrupt status register bit for the EP3 OUT direction. + */ #define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK) + #define USBHSD_INTSTAT_EP3IN_MASK (0x80U) #define USBHSD_INTSTAT_EP3IN_SHIFT (7U) +/*! EP3IN - Interrupt status register bit for the EP3 IN direction. + */ #define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK) + #define USBHSD_INTSTAT_EP4OUT_MASK (0x100U) #define USBHSD_INTSTAT_EP4OUT_SHIFT (8U) +/*! EP4OUT - Interrupt status register bit for the EP4 OUT direction. + */ #define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK) + #define USBHSD_INTSTAT_EP4IN_MASK (0x200U) #define USBHSD_INTSTAT_EP4IN_SHIFT (9U) +/*! EP4IN - Interrupt status register bit for the EP4 IN direction. + */ #define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK) + #define USBHSD_INTSTAT_EP5OUT_MASK (0x400U) #define USBHSD_INTSTAT_EP5OUT_SHIFT (10U) +/*! EP5OUT - Interrupt status register bit for the EP5 OUT direction. + */ #define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK) + #define USBHSD_INTSTAT_EP5IN_MASK (0x800U) #define USBHSD_INTSTAT_EP5IN_SHIFT (11U) +/*! EP5IN - Interrupt status register bit for the EP5 IN direction. + */ #define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK) + #define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U) #define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U) +/*! FRAME_INT - Frame interrupt. + */ #define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK) + #define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U) #define USBHSD_INTSTAT_DEV_INT_SHIFT (31U) +/*! DEV_INT - Device status interrupt. + */ #define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK) /*! @} */ /*! @name INTEN - USB interrupt enable register */ /*! @{ */ + #define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU) #define USBHSD_INTEN_EP_INT_EN_SHIFT (0U) +/*! EP_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ #define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK) + #define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U) #define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U) +/*! FRAME_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ #define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK) + #define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U) #define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U) +/*! DEV_INT_EN - If this bit is set and the corresponding USB interrupt status bit is set, a HW + * interrupt is generated on the interrupt line. + */ #define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK) /*! @} */ /*! @name INTSETSTAT - USB set interrupt status register */ /*! @{ */ + #define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU) #define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U) +/*! EP_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ #define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK) + #define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U) #define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U) +/*! FRAME_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ #define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK) + #define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U) #define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U) +/*! DEV_SET_INT - If software writes a one to one of these bits, the corresponding USB interrupt status bit is set. + */ #define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK) /*! @} */ /*! @name EPTOGGLE - USB Endpoint toggle register */ /*! @{ */ + #define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU) #define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U) +/*! TOGGLE - Endpoint data toggle: This field indicates the current value of the data toggle for the corresponding endpoint. + */ #define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK) /*! @} */ -/*! @name ULPIDEBUG - UTMI/ULPI debug register */ -/*! @{ */ -#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU) -#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U) -#define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK) -#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U) -#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U) -#define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK) -#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U) -#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U) -#define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK) -#define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U) -#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U) -#define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK) -#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U) -#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U) -#define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK) -#define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U) -#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U) -#define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK) -/*! @} */ - /*! * @} @@ -23177,7 +28378,7 @@ typedef struct { /* USBHSD - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USBHSD base address */ #define USBHSD_BASE (0x50094000u) /** Peripheral USBHSD base address */ @@ -23226,24 +28427,24 @@ typedef struct { typedef struct { __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */ - __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */ + uint8_t RESERVED_0[4]; __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */ - __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ - __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ - __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ - __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ + __IO uint32_t ATLPTD; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */ + __IO uint32_t ISOPTD; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */ + __IO uint32_t INTPTD; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */ + __IO uint32_t DATAPAYLOAD; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */ __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */ __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */ __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */ __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */ - __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */ - __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */ - __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */ - __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */ - __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */ - __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */ - __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ - __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */ + __IO uint32_t ATLPTDD; /**< Done map for each ATL PTD, offset: 0x30 */ + __IO uint32_t ATLPTDS; /**< Skip map for each ATL PTD, offset: 0x34 */ + __IO uint32_t ISOPTDD; /**< Done map for each ISO PTD, offset: 0x38 */ + __IO uint32_t ISOPTDS; /**< Skip map for each ISO PTD, offset: 0x3C */ + __IO uint32_t INTPTDD; /**< Done map for each INT PTD, offset: 0x40 */ + __IO uint32_t INTPTDS; /**< Skip map for each INT PTD, offset: 0x44 */ + __IO uint32_t LASTPTD; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */ + uint8_t RESERVED_1[4]; __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */ } USBHSH_Type; @@ -23258,307 +28459,446 @@ typedef struct { /*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */ /*! @{ */ + #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU) #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - Capability Length: This is used as an offset. + */ #define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK) + #define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U) #define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U) +/*! CHIPID - Chip identification: indicates major and minor revision of the IP: [31:24] = Major + * revision [23:16] = Minor revision Major revisions used: 0x01: USB2. + */ #define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK) /*! @} */ /*! @name HCSPARAMS - Host Controller Structural Parameters */ /*! @{ */ + #define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU) #define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - This register specifies the number of physical downstream ports implemented on this host controller. + */ #define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK) + #define USBHSH_HCSPARAMS_PPC_MASK (0x10U) #define USBHSH_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - This field indicates whether the host controller implementation includes port power control. + */ #define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK) + #define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U) #define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U) +/*! P_INDICATOR - This bit indicates whether the ports support port indicator control. + */ #define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK) /*! @} */ -/*! @name HCCPARAMS - Host Controller Capability Parameters */ -/*! @{ */ -#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U) -#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U) -#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK) -/*! @} */ - /*! @name FLADJ_FRINDEX - Frame Length Adjustment */ /*! @{ */ + #define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU) #define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U) +/*! FLADJ - Frame Length Timing Value. + */ #define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK) + #define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U) #define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U) +/*! FRINDEX - Frame Index: Bits 29 to16 in this register are used for the frame number field in the SOF packet. + */ #define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK) /*! @} */ -/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */ +/*! @name ATLPTD - Memory base address where ATL PTD0 is stored */ /*! @{ */ -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U) -#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK) + +#define USBHSH_ATLPTD_ATL_CUR_MASK (0x1F0U) +#define USBHSH_ATLPTD_ATL_CUR_SHIFT (4U) +/*! ATL_CUR - This indicates the current PTD that is used by the hardware when it is processing the ATL list. + */ +#define USBHSH_ATLPTD_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_CUR_SHIFT)) & USBHSH_ATLPTD_ATL_CUR_MASK) + +#define USBHSH_ATLPTD_ATL_BASE_MASK (0xFFFFFE00U) +#define USBHSH_ATLPTD_ATL_BASE_SHIFT (9U) +/*! ATL_BASE - Base address to be used by the hardware to find the start of the ATL list. + */ +#define USBHSH_ATLPTD_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTD_ATL_BASE_SHIFT)) & USBHSH_ATLPTD_ATL_BASE_MASK) /*! @} */ -/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */ +/*! @name ISOPTD - Memory base address where ISO PTD0 is stored */ /*! @{ */ -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U) -#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK) + +#define USBHSH_ISOPTD_ISO_FIRST_MASK (0x3E0U) +#define USBHSH_ISOPTD_ISO_FIRST_SHIFT (5U) +/*! ISO_FIRST - This indicates the first PTD that is used by the hardware when it is processing the ISO list. + */ +#define USBHSH_ISOPTD_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_FIRST_SHIFT)) & USBHSH_ISOPTD_ISO_FIRST_MASK) + +#define USBHSH_ISOPTD_ISO_BASE_MASK (0xFFFFFC00U) +#define USBHSH_ISOPTD_ISO_BASE_SHIFT (10U) +/*! ISO_BASE - Base address to be used by the hardware to find the start of the ISO list. + */ +#define USBHSH_ISOPTD_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTD_ISO_BASE_SHIFT)) & USBHSH_ISOPTD_ISO_BASE_MASK) /*! @} */ -/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */ +/*! @name INTPTD - Memory base address where INT PTD0 is stored */ /*! @{ */ -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U) -#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK) + +#define USBHSH_INTPTD_INT_FIRST_MASK (0x3E0U) +#define USBHSH_INTPTD_INT_FIRST_SHIFT (5U) +/*! INT_FIRST - This indicates the first PTD that is used by the hardware when it is processing the INT list. + */ +#define USBHSH_INTPTD_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_FIRST_SHIFT)) & USBHSH_INTPTD_INT_FIRST_MASK) + +#define USBHSH_INTPTD_INT_BASE_MASK (0xFFFFFC00U) +#define USBHSH_INTPTD_INT_BASE_SHIFT (10U) +/*! INT_BASE - Base address to be used by the hardware to find the start of the INT list. + */ +#define USBHSH_INTPTD_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTD_INT_BASE_SHIFT)) & USBHSH_INTPTD_INT_BASE_MASK) /*! @} */ -/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */ +/*! @name DATAPAYLOAD - Memory base address that indicates the start of the data payload buffers */ /*! @{ */ -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U) -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U) -#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK) + +#define USBHSH_DATAPAYLOAD_DAT_BASE_MASK (0xFFFF0000U) +#define USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT (16U) +/*! DAT_BASE - Base address to be used by the hardware to find the start of the data payload section. + */ +#define USBHSH_DATAPAYLOAD_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATAPAYLOAD_DAT_BASE_SHIFT)) & USBHSH_DATAPAYLOAD_DAT_BASE_MASK) /*! @} */ /*! @name USBCMD - USB Command register */ /*! @{ */ + #define USBHSH_USBCMD_RS_MASK (0x1U) #define USBHSH_USBCMD_RS_SHIFT (0U) +/*! RS - Run/Stop: 1b = Run. + */ #define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK) + #define USBHSH_USBCMD_HCRESET_MASK (0x2U) #define USBHSH_USBCMD_HCRESET_SHIFT (1U) +/*! HCRESET - Host Controller Reset: This control bit is used by the software to reset the host controller. + */ #define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK) + #define USBHSH_USBCMD_FLS_MASK (0xCU) #define USBHSH_USBCMD_FLS_SHIFT (2U) +/*! FLS - Frame List Size: This field specifies the size of the frame list. + */ #define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK) + #define USBHSH_USBCMD_LHCR_MASK (0x80U) #define USBHSH_USBCMD_LHCR_SHIFT (7U) +/*! LHCR - Light Host Controller Reset: This bit allows the driver software to reset the host + * controller without affecting the state of the ports. + */ #define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK) + #define USBHSH_USBCMD_ATL_EN_MASK (0x100U) #define USBHSH_USBCMD_ATL_EN_SHIFT (8U) +/*! ATL_EN - ATL List enabled. + */ #define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK) + #define USBHSH_USBCMD_ISO_EN_MASK (0x200U) #define USBHSH_USBCMD_ISO_EN_SHIFT (9U) +/*! ISO_EN - ISO List enabled. + */ #define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK) + #define USBHSH_USBCMD_INT_EN_MASK (0x400U) #define USBHSH_USBCMD_INT_EN_SHIFT (10U) +/*! INT_EN - INT List enabled. + */ #define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK) -#define USBHSH_USBCMD_HIRD_MASK (0xF000000U) -#define USBHSH_USBCMD_HIRD_SHIFT (24U) -#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK) -#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U) -#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U) -#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK) /*! @} */ /*! @name USBSTS - USB Interrupt Status register */ /*! @{ */ + #define USBHSH_USBSTS_PCD_MASK (0x4U) #define USBHSH_USBSTS_PCD_SHIFT (2U) +/*! PCD - Port Change Detect: The host controller sets this bit to logic 1 when any port has a + * change bit transition from a 0 to a one or a Force Port Resume bit transition from a 0 to a 1 as a + * result of a J-K transition detected on a suspended port. + */ #define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK) + #define USBHSH_USBSTS_FLR_MASK (0x8U) #define USBHSH_USBSTS_FLR_SHIFT (3U) +/*! FLR - Frame List Rollover: The host controller sets this bit to logic 1 when the frame list + * index rolls over its maximum value to 0. + */ #define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK) + #define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U) #define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U) +/*! ATL_IRQ - ATL IRQ: Indicates that an ATL PTD (with I-bit set) was completed. + */ #define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK) + #define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U) #define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U) +/*! ISO_IRQ - ISO IRQ: Indicates that an ISO PTD (with I-bit set) was completed. + */ #define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK) + #define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U) #define USBHSH_USBSTS_INT_IRQ_SHIFT (18U) +/*! INT_IRQ - INT IRQ: Indicates that an INT PTD (with I-bit set) was completed. + */ #define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK) + #define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U) #define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U) +/*! SOF_IRQ - SOF interrupt: Every time when the host sends a Start of Frame token on the USB bus, this bit is set. + */ #define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK) /*! @} */ /*! @name USBINTR - USB Interrupt Enable register */ /*! @{ */ + #define USBHSH_USBINTR_PCDE_MASK (0x4U) #define USBHSH_USBINTR_PCDE_SHIFT (2U) +/*! PCDE - Port Change Detect Interrupt Enable: 1: enable 0: disable. + */ #define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK) + #define USBHSH_USBINTR_FLRE_MASK (0x8U) #define USBHSH_USBINTR_FLRE_SHIFT (3U) +/*! FLRE - Frame List Rollover Interrupt Enable: 1: enable 0: disable. + */ #define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK) + #define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U) #define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U) +/*! ATL_IRQ_E - ATL IRQ Enable bit: 1: enable 0: disable. + */ #define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK) + #define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U) #define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U) +/*! ISO_IRQ_E - ISO IRQ Enable bit: 1: enable 0: disable. + */ #define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK) + #define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U) #define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U) +/*! INT_IRQ_E - INT IRQ Enable bit: 1: enable 0: disable. + */ #define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK) + #define USBHSH_USBINTR_SOF_E_MASK (0x80000U) #define USBHSH_USBINTR_SOF_E_SHIFT (19U) +/*! SOF_E - SOF Interrupt Enable bit: 1: enable 0: disable. + */ #define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK) /*! @} */ /*! @name PORTSC1 - Port Status and Control register */ /*! @{ */ + #define USBHSH_PORTSC1_CCS_MASK (0x1U) #define USBHSH_PORTSC1_CCS_SHIFT (0U) +/*! CCS - Current Connect Status: Logic 1 indicates a device is present on the port. + */ #define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK) + #define USBHSH_PORTSC1_CSC_MASK (0x2U) #define USBHSH_PORTSC1_CSC_SHIFT (1U) +/*! CSC - Connect Status Change: Logic 1 means that the value of CCS has changed. + */ #define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK) + #define USBHSH_PORTSC1_PED_MASK (0x4U) #define USBHSH_PORTSC1_PED_SHIFT (2U) +/*! PED - Port Enabled/Disabled. + */ #define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK) + #define USBHSH_PORTSC1_PEDC_MASK (0x8U) #define USBHSH_PORTSC1_PEDC_SHIFT (3U) +/*! PEDC - Port Enabled/Disabled Change: Logic 1 means that the value of PED has changed. + */ #define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK) + #define USBHSH_PORTSC1_OCA_MASK (0x10U) #define USBHSH_PORTSC1_OCA_SHIFT (4U) +/*! OCA - Over-current active: Logic 1 means that this port has an over-current condition. + */ #define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK) + #define USBHSH_PORTSC1_OCC_MASK (0x20U) #define USBHSH_PORTSC1_OCC_SHIFT (5U) +/*! OCC - Over-current change: Logic 1 means that the value of OCA has changed. + */ #define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK) + #define USBHSH_PORTSC1_FPR_MASK (0x40U) #define USBHSH_PORTSC1_FPR_SHIFT (6U) +/*! FPR - Force Port Resume: Logic 1 means resume (K-state) detected or driven on the port. + */ #define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK) + #define USBHSH_PORTSC1_SUSP_MASK (0x80U) #define USBHSH_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - Suspend: Logic 1 means port is in the suspend state. + */ #define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK) + #define USBHSH_PORTSC1_PR_MASK (0x100U) #define USBHSH_PORTSC1_PR_SHIFT (8U) +/*! PR - Port Reset: Logic 1 means the port is in the reset state. + */ #define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK) -#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U) -#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U) -#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK) + #define USBHSH_PORTSC1_LS_MASK (0xC00U) #define USBHSH_PORTSC1_LS_SHIFT (10U) +/*! LS - Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. + */ #define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK) + #define USBHSH_PORTSC1_PP_MASK (0x1000U) #define USBHSH_PORTSC1_PP_SHIFT (12U) +/*! PP - Port Power: The function of this bit depends on the value of the Port Power Control (PPC) bit in the HCSPARAMS register. + */ #define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK) + #define USBHSH_PORTSC1_PIC_MASK (0xC000U) #define USBHSH_PORTSC1_PIC_SHIFT (14U) +/*! PIC - Port Indicator Control : Writing to this field has no effect if the P_INDICATOR bit in the + * HCSPARAMS register is logic 0. + */ #define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK) + #define USBHSH_PORTSC1_PTC_MASK (0xF0000U) #define USBHSH_PORTSC1_PTC_SHIFT (16U) +/*! PTC - Port Test Control: A non-zero value indicates that the port is operating in the test mode as indicated by the value. + */ #define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK) + #define USBHSH_PORTSC1_PSPD_MASK (0x300000U) #define USBHSH_PORTSC1_PSPD_SHIFT (20U) +/*! PSPD - Port Speed: 00b: Low-speed 01b: Full-speed 10b: High-speed 11b: Reserved. + */ #define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK) + #define USBHSH_PORTSC1_WOO_MASK (0x400000U) #define USBHSH_PORTSC1_WOO_SHIFT (22U) +/*! WOO - Wake on overcurrent enable: Writing this bit to a one enables the port to be sensitive to + * overcurrent conditions as wake-up events. + */ #define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK) -#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U) -#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U) -#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK) -#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U) -#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U) -#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK) /*! @} */ -/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */ +/*! @name ATLPTDD - Done map for each ATL PTD */ /*! @{ */ -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U) -#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK) + +#define USBHSH_ATLPTDD_ATL_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDD_ATL_DONE_SHIFT (0U) +/*! ATL_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ATLPTDD_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDD_ATL_DONE_SHIFT)) & USBHSH_ATLPTDD_ATL_DONE_MASK) /*! @} */ -/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */ +/*! @name ATLPTDS - Skip map for each ATL PTD */ /*! @{ */ -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U) -#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK) + +#define USBHSH_ATLPTDS_ATL_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ATLPTDS_ATL_SKIP_SHIFT (0U) +/*! ATL_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_ATLPTDS_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATLPTDS_ATL_SKIP_SHIFT)) & USBHSH_ATLPTDS_ATL_SKIP_MASK) /*! @} */ -/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */ +/*! @name ISOPTDD - Done map for each ISO PTD */ /*! @{ */ -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U) -#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK) + +#define USBHSH_ISOPTDD_ISO_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDD_ISO_DONE_SHIFT (0U) +/*! ISO_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ISOPTDD_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDD_ISO_DONE_SHIFT)) & USBHSH_ISOPTDD_ISO_DONE_MASK) /*! @} */ -/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */ +/*! @name ISOPTDS - Skip map for each ISO PTD */ /*! @{ */ -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U) -#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK) + +#define USBHSH_ISOPTDS_ISO_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_ISOPTDS_ISO_SKIP_SHIFT (0U) +/*! ISO_SKIP - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_ISOPTDS_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISOPTDS_ISO_SKIP_SHIFT)) & USBHSH_ISOPTDS_ISO_SKIP_MASK) /*! @} */ -/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */ +/*! @name INTPTDD - Done map for each INT PTD */ /*! @{ */ -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU) -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U) -#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK) + +#define USBHSH_INTPTDD_INT_DONE_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDD_INT_DONE_SHIFT (0U) +/*! INT_DONE - The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. + */ +#define USBHSH_INTPTDD_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDD_INT_DONE_SHIFT)) & USBHSH_INTPTDD_INT_DONE_MASK) /*! @} */ -/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */ +/*! @name INTPTDS - Skip map for each INT PTD */ /*! @{ */ -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU) -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U) -#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK) + +#define USBHSH_INTPTDS_INT_SKIP_MASK (0xFFFFFFFFU) +#define USBHSH_INTPTDS_INT_SKIP_SHIFT (0U) +/*! INT_SKIP - When a bit in the PTD Skip Map is set to logic 1, the corresponding PTD will be + * skipped, independent of the V bit setting. + */ +#define USBHSH_INTPTDS_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INTPTDS_INT_SKIP_SHIFT)) & USBHSH_INTPTDS_INT_SKIP_MASK) /*! @} */ -/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */ +/*! @name LASTPTD - Marks the last PTD in the list for ISO, INT and ATL */ /*! @{ */ -#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU) -#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U) -#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U) -#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK) -#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U) -#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U) -#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK) -/*! @} */ -/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */ -/*! @{ */ -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U) -#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK) +#define USBHSH_LASTPTD_ATL_LAST_MASK (0x1FU) +#define USBHSH_LASTPTD_ATL_LAST_SHIFT (0U) +/*! ATL_LAST - If hardware has reached this PTD and the J bit is not set, it will go to PTD0 as the next PTD to be processed. + */ +#define USBHSH_LASTPTD_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ATL_LAST_SHIFT)) & USBHSH_LASTPTD_ATL_LAST_MASK) + +#define USBHSH_LASTPTD_ISO_LAST_MASK (0x1F00U) +#define USBHSH_LASTPTD_ISO_LAST_SHIFT (8U) +/*! ISO_LAST - This indicates the last PTD in the ISO list. + */ +#define USBHSH_LASTPTD_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_ISO_LAST_SHIFT)) & USBHSH_LASTPTD_ISO_LAST_MASK) + +#define USBHSH_LASTPTD_INT_LAST_MASK (0x1F0000U) +#define USBHSH_LASTPTD_INT_LAST_SHIFT (16U) +/*! INT_LAST - This indicates the last PTD in the INT list. + */ +#define USBHSH_LASTPTD_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LASTPTD_INT_LAST_SHIFT)) & USBHSH_LASTPTD_INT_LAST_MASK) /*! @} */ /*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */ /*! @{ */ -#define USBHSH_PORTMODE_ID0_MASK (0x1U) -#define USBHSH_PORTMODE_ID0_SHIFT (0U) -#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK) -#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U) -#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U) -#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK) + #define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U) #define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U) +/*! DEV_ENABLE - If this bit is set to one, one of the ports will behave as a USB device. + */ #define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK) + #define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U) #define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U) +/*! SW_CTRL_PDCOM - This bit indicates if the PHY power-down input is controlled by software or by hardware. + */ #define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK) + #define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U) #define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U) +/*! SW_PDCOM - This bit is only used when SW_CTRL_PDCOM is set to 1b. + */ #define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK) /*! @} */ @@ -23569,7 +28909,7 @@ typedef struct { /* USBHSH - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USBHSH base address */ #define USBHSH_BASE (0x500A3000u) /** Peripheral USBHSH base address */ @@ -23632,36 +28972,18 @@ typedef struct { __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */ __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */ __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ - __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ - uint8_t RESERVED_0[12]; - __IO uint32_t DEBUG0; /**< USB PHY Debug Register 0, offset: 0x50 */ - __IO uint32_t DEBUG0_SET; /**< USB PHY Debug Register 0, offset: 0x54 */ - __IO uint32_t DEBUG0_CLR; /**< USB PHY Debug Register 0, offset: 0x58 */ - __IO uint32_t DEBUG0_TOG; /**< USB PHY Debug Register 0, offset: 0x5C */ - uint8_t RESERVED_1[16]; - __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ - __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ - __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ - __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */ - __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */ - uint8_t RESERVED_2[28]; + __I uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ + uint8_t RESERVED_0[92]; __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */ __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */ __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */ __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */ - uint8_t RESERVED_3[16]; + uint8_t RESERVED_1[16]; __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */ __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */ __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */ __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */ - __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */ - uint8_t RESERVED_4[12]; - __IO uint32_t USB1_CHRG_DETECT; /**< USB PHY Charger Detect Control Register, offset: 0xE0 */ - __IO uint32_t USB1_CHRG_DETECT_SET; /**< USB PHY Charger Detect Control Register, offset: 0xE4 */ - __IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB PHY Charger Detect Control Register, offset: 0xE8 */ - __IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB PHY Charger Detect Control Register, offset: 0xEC */ - __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */ - uint8_t RESERVED_5[12]; + uint8_t RESERVED_2[48]; __IO uint32_t ANACTRLr; /**< USB PHY Analog Control Register, offset: 0x100 */ __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */ __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */ @@ -23679,6 +29001,7 @@ typedef struct { /*! @name PWD - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TXPWDFS_SHIFT (10U) /*! TXPWDFS @@ -23686,6 +29009,7 @@ typedef struct { * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the */ #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) + #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS @@ -23693,6 +29017,7 @@ typedef struct { * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the */ #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) + #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I @@ -23700,6 +29025,7 @@ typedef struct { * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) + #define USBPHY_PWD_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_RXPWDENV_SHIFT (17U) /*! RXPWDENV @@ -23707,6 +29033,7 @@ typedef struct { * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) + #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 @@ -23714,6 +29041,7 @@ typedef struct { * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) + #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF @@ -23721,6 +29049,7 @@ typedef struct { * 0b1..Power-down the USB high-speed differential receive */ #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) + #define USBPHY_PWD_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_RXPWDRX_SHIFT (20U) /*! RXPWDRX @@ -23732,6 +29061,7 @@ typedef struct { /*! @name PWD_SET - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) /*! TXPWDFS @@ -23739,6 +29069,7 @@ typedef struct { * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the */ #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) + #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS @@ -23746,6 +29077,7 @@ typedef struct { * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the */ #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) + #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I @@ -23753,6 +29085,7 @@ typedef struct { * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) + #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) /*! RXPWDENV @@ -23760,6 +29093,7 @@ typedef struct { * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) + #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 @@ -23767,6 +29101,7 @@ typedef struct { * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) + #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF @@ -23774,6 +29109,7 @@ typedef struct { * 0b1..Power-down the USB high-speed differential receive */ #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) + #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) /*! RXPWDRX @@ -23785,6 +29121,7 @@ typedef struct { /*! @name PWD_CLR - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) /*! TXPWDFS @@ -23792,6 +29129,7 @@ typedef struct { * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the */ #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) + #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS @@ -23799,6 +29137,7 @@ typedef struct { * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the */ #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) + #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I @@ -23806,6 +29145,7 @@ typedef struct { * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) + #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) /*! RXPWDENV @@ -23813,6 +29153,7 @@ typedef struct { * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) + #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 @@ -23820,6 +29161,7 @@ typedef struct { * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) + #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF @@ -23827,6 +29169,7 @@ typedef struct { * 0b1..Power-down the USB high-speed differential receive */ #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) + #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) /*! RXPWDRX @@ -23838,6 +29181,7 @@ typedef struct { /*! @name PWD_TOG - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) /*! TXPWDFS @@ -23845,6 +29189,7 @@ typedef struct { * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the */ #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) + #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) /*! TXPWDIBIAS @@ -23852,6 +29197,7 @@ typedef struct { * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the */ #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) + #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) /*! TXPWDV2I @@ -23859,6 +29205,7 @@ typedef struct { * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) + #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) /*! RXPWDENV @@ -23866,6 +29213,7 @@ typedef struct { * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) + #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) /*! RXPWD1PT1 @@ -23873,6 +29221,7 @@ typedef struct { * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) + #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) /*! RXPWDDIFF @@ -23880,6 +29229,7 @@ typedef struct { * 0b1..Power-down the USB high-speed differential receive */ #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) + #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) /*! RXPWDRX @@ -23891,6 +29241,7 @@ typedef struct { /*! @name TX - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_D_CAL_MASK (0xFU) #define USBPHY_TX_D_CAL_SHIFT (0U) /*! D_CAL @@ -23899,15 +29250,19 @@ typedef struct { * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) + #define USBPHY_TX_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) + #define USBPHY_TX_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DN_SHIFT)) & USBPHY_TX_TXENCAL45DN_MASK) + #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) + #define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) @@ -23915,6 +29270,7 @@ typedef struct { /*! @name TX_SET - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_SET_D_CAL_MASK (0xFU) #define USBPHY_TX_SET_D_CAL_SHIFT (0U) /*! D_CAL @@ -23923,15 +29279,19 @@ typedef struct { * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) + #define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) + #define USBPHY_TX_SET_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_SET_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_SET_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DN_SHIFT)) & USBPHY_TX_SET_TXENCAL45DN_MASK) + #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) + #define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) @@ -23939,6 +29299,7 @@ typedef struct { /*! @name TX_CLR - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_CLR_D_CAL_MASK (0xFU) #define USBPHY_TX_CLR_D_CAL_SHIFT (0U) /*! D_CAL @@ -23947,15 +29308,19 @@ typedef struct { * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) + #define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) + #define USBPHY_TX_CLR_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_CLR_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_CLR_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DN_MASK) + #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) + #define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) @@ -23963,6 +29328,7 @@ typedef struct { /*! @name TX_TOG - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_TOG_D_CAL_MASK (0xFU) #define USBPHY_TX_TOG_D_CAL_SHIFT (0U) /*! D_CAL @@ -23971,15 +29337,19 @@ typedef struct { * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) + #define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) #define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) #define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) + #define USBPHY_TX_TOG_TXENCAL45DN_MASK (0x2000U) #define USBPHY_TX_TOG_TXENCAL45DN_SHIFT (13U) #define USBPHY_TX_TOG_TXENCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DN_MASK) + #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) + #define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) #define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) #define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) @@ -23987,6 +29357,7 @@ typedef struct { /*! @name RX - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_ENVADJ_MASK (0x7U) #define USBPHY_RX_ENVADJ_SHIFT (0U) /*! ENVADJ @@ -24000,6 +29371,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) + #define USBPHY_RX_DISCONADJ_MASK (0x70U) #define USBPHY_RX_DISCONADJ_SHIFT (4U) /*! DISCONADJ @@ -24013,6 +29385,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) + #define USBPHY_RX_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS @@ -24024,6 +29397,7 @@ typedef struct { /*! @name RX_SET - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_SET_ENVADJ_MASK (0x7U) #define USBPHY_RX_SET_ENVADJ_SHIFT (0U) /*! ENVADJ @@ -24037,6 +29411,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) + #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) /*! DISCONADJ @@ -24050,6 +29425,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) + #define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS @@ -24061,6 +29437,7 @@ typedef struct { /*! @name RX_CLR - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) /*! ENVADJ @@ -24074,6 +29451,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) + #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) /*! DISCONADJ @@ -24087,6 +29465,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) + #define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS @@ -24098,6 +29477,7 @@ typedef struct { /*! @name RX_TOG - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) /*! ENVADJ @@ -24111,6 +29491,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) + #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) /*! DISCONADJ @@ -24124,6 +29505,7 @@ typedef struct { * 0b111..reserved */ #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) + #define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) /*! RXDBYPASS @@ -24135,12 +29517,19 @@ typedef struct { /*! @name CTRL - USB PHY General Control Register */ /*! @{ */ + #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) + #define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET @@ -24148,42 +29537,83 @@ typedef struct { * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) + #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) -#define USBPHY_CTRL_DATA_ON_LRADC_MASK (0x2000U) -#define USBPHY_CTRL_DATA_ON_LRADC_SHIFT (13U) -#define USBPHY_CTRL_DATA_ON_LRADC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DATA_ON_LRADC_SHIFT)) & USBPHY_CTRL_DATA_ON_LRADC_MASK) + #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_ENAUTOSET_USBCLKS_MASK) + #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) + #define USBPHY_CTRL_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) @@ -24191,12 +29621,19 @@ typedef struct { /*! @name CTRL_SET - USB PHY General Control Register */ /*! @{ */ + #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) + #define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET @@ -24204,39 +29641,83 @@ typedef struct { * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) + #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) + #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_SET_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_SET_ENAUTOSET_USBCLKS_MASK) + #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) + #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) @@ -24244,12 +29725,19 @@ typedef struct { /*! @name CTRL_CLR - USB PHY General Control Register */ /*! @{ */ + #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) + #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET @@ -24257,39 +29745,83 @@ typedef struct { * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) + #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) + #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOSET_USBCLKS_MASK) + #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) + #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) @@ -24297,12 +29829,19 @@ typedef struct { /*! @name CTRL_TOG - USB PHY General Control Register */ /*! @{ */ + #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) + #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) /*! ENDEVPLUGINDET @@ -24310,39 +29849,83 @@ typedef struct { * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins */ #define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) + #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) + #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) #define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) -#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) -#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) + +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK (0x2000000U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT (25U) +#define USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_USBCLKGATE_MASK) + +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK (0x4000000U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT (26U) +#define USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOSET_USBCLKS_MASK) + #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) + #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) @@ -24350,6 +29933,11 @@ typedef struct { /*! @name STATUS - USB PHY Status Register */ /*! @{ */ + +#define USBPHY_STATUS_OK_STATUS_3V_MASK (0x1U) +#define USBPHY_STATUS_OK_STATUS_3V_SHIFT (0U) +#define USBPHY_STATUS_OK_STATUS_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OK_STATUS_3V_SHIFT)) & USBPHY_STATUS_OK_STATUS_3V_MASK) + #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) /*! HOSTDISCONDETECT_STATUS @@ -24357,6 +29945,7 @@ typedef struct { * 0b1..USB cable disconnect has been detected at the local host */ #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) + #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) /*! DEVPLUGIN_STATUS @@ -24364,268 +29953,27 @@ typedef struct { * 0b1..Cable attachment to a USB host is detected */ #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) -#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) -#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) -#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) + #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) /*! @} */ -/*! @name DEBUG0 - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_SET - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_SET_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_CLR - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_TOG - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG1 - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ -/*! @{ */ -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) -#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% - */ -#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U) -#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK) -/*! @} */ - -/*! @name VERSION - UTMI RTL Version */ -/*! @{ */ -#define USBPHY_VERSION_STEP_MASK (0xFFFFU) -#define USBPHY_VERSION_STEP_SHIFT (0U) -#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) -#define USBPHY_VERSION_MINOR_MASK (0xFF0000U) -#define USBPHY_VERSION_MINOR_SHIFT (16U) -#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) -#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) -#define USBPHY_VERSION_MAJOR_SHIFT (24U) -#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) -/*! @} */ - /*! @name PLL_SIC - USB PHY PLL Control/Status Register */ /*! @{ */ -#define USBPHY_PLL_SIC_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_MISC2_CONTROL0_MASK) + #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL @@ -24633,12 +29981,15 @@ typedef struct { * 0b1..Selects REFBIAS_PWD to control the reference bias */ #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) #define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL @@ -24652,6 +30003,11 @@ typedef struct { * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_PREDIV_MASK) + #define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK @@ -24663,21 +30019,19 @@ typedef struct { /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ /*! @{ */ -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_SET_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK) + #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL @@ -24685,12 +30039,15 @@ typedef struct { * 0b1..Selects REFBIAS_PWD to control the reference bias */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL @@ -24704,6 +30061,11 @@ typedef struct { * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_SET_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_PREDIV_MASK) + #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK @@ -24715,21 +30077,19 @@ typedef struct { /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ /*! @{ */ -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_CLR_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_CLR_MISC2_CONTROL0_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL @@ -24737,12 +30097,15 @@ typedef struct { * 0b1..Selects REFBIAS_PWD to control the reference bias */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL @@ -24756,6 +30119,11 @@ typedef struct { * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_CLR_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_PREDIV_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK @@ -24767,21 +30135,19 @@ typedef struct { /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ /*! @{ */ -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK (0x20U) -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT (5U) -#define USBPHY_PLL_SIC_TOG_MISC2_CONTROL0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_SHIFT)) & USBPHY_PLL_SIC_TOG_MISC2_CONTROL0_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) #define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) -#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) /*! REFBIAS_PWD_SEL @@ -24789,12 +30155,15 @@ typedef struct { * 0b1..Selects REFBIAS_PWD to control the reference bias */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) /*! PLL_DIV_SEL @@ -24808,6 +30177,11 @@ typedef struct { * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) + +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK (0x40000000U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT (30U) +#define USBPHY_PLL_SIC_TOG_PLL_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_PREDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_PREDIV_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) /*! PLL_LOCK @@ -24819,6 +30193,7 @@ typedef struct { /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH @@ -24832,6 +30207,7 @@ typedef struct { * 0b111..4.7V */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN @@ -24839,18 +30215,23 @@ typedef struct { * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL @@ -24858,6 +30239,7 @@ typedef struct { * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL @@ -24867,6 +30249,31 @@ typedef struct { * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EXT_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID @@ -24874,13 +30281,19 @@ typedef struct { * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS @@ -24888,17 +30301,11 @@ typedef struct { * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH @@ -24912,6 +30319,7 @@ typedef struct { * 0b111..4.7V */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN @@ -24919,18 +30327,23 @@ typedef struct { * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL @@ -24938,6 +30351,7 @@ typedef struct { * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL @@ -24947,6 +30361,31 @@ typedef struct { * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EXT_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID @@ -24954,13 +30393,19 @@ typedef struct { * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS @@ -24968,17 +30413,11 @@ typedef struct { * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH @@ -24992,6 +30431,7 @@ typedef struct { * 0b111..4.7V */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN @@ -24999,18 +30439,23 @@ typedef struct { * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL @@ -25018,6 +30463,7 @@ typedef struct { * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL @@ -25027,6 +30473,31 @@ typedef struct { * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EXT_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID @@ -25034,13 +30505,19 @@ typedef struct { * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS @@ -25048,17 +30525,11 @@ typedef struct { * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) /*! VBUSVALID_THRESH @@ -25072,6 +30543,7 @@ typedef struct { * 0b111..4.7V */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN @@ -25079,18 +30551,23 @@ typedef struct { * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL @@ -25098,6 +30575,7 @@ typedef struct { * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL @@ -25107,6 +30585,31 @@ typedef struct { * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK (0x2000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT (13U) +/*! EXT_ID_OVERRIDE_EN + * 0b0..Select the muxed value chosen using ID_OVERRIDE_EN. + * 0b1..Select the external ID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK (0x4000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT (14U) +/*! EXT_VBUS_OVERRIDE_EN + * 0b0..Select the Muxed value chosen using VBUS_OVERRIDE_EN. + * 0b1..Select the external VBUS VALID value. + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EXT_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID @@ -25114,13 +30617,19 @@ typedef struct { * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK (0x80000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT (19U) +#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_5VDETECT_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) + * 0b000..Powers down the VBUS_VALID comparator + * 0b111..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS @@ -25128,151 +30637,19 @@ typedef struct { * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U) -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U) -/*! EN_CHARGER_RESISTOR - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP - */ -#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK) -/*! @} */ - -/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */ -/*! @{ */ -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) -/*! SESSEND - * 0b0..The VBUS voltage is above the Session Valid threshold - * 0b1..The VBUS voltage is below the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) -#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) -/*! BVALID - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) -#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) -/*! AVALID - * 0b0..The VBUS voltage is below the Session Valid threshold - * 0b1..The VBUS voltage is above the Session Valid threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) -/*! VBUS_VALID - * 0b0..VBUS is below the comparator threshold - * 0b1..VBUS is above the comparator threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) -/*! VBUS_VALID_3V - * 0b0..VBUS voltage is below VBUS_VALID_3V threshold - * 0b1..VBUS voltage is above VBUS_VALID_3V threshold - */ -#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) -#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. - */ -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK) -/*! @} */ - -/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */ -/*! @{ */ -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - * 0b0..No USB cable attachment has been detected - * 0b1..A USB cable attachment between the device and host has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - * 0b0..Standard Downstream Port (SDP) has been detected - * 0b1..Charging Port has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) -/*! DM_STATE - * 0b0..USB_DM pin voltage is < 0.8V - * 0b1..USB_DM pin voltage is > 2.0V - */ -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) -/*! DP_STATE - * 0b0..USB_DP pin voltage is < 0.8V - * 0b1..USB_DP pin voltage is > 2.0V - */ -#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) -/*! SECDET_DCP - * 0b0..Charging Downstream Port (CDP) has been detected - * 0b1..Downstream Charging Port (DCP) has been detected - */ -#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK) /*! @} */ /*! @name ANACTRL - USB PHY Analog Control Register */ /*! @{ */ + +#define USBPHY_ANACTRL_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_LVI_EN_SHIFT)) & USBPHY_ANACTRL_LVI_EN_MASK) + +#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK) + #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN @@ -25284,6 +30661,15 @@ typedef struct { /*! @name ANACTRL_SET - USB PHY Analog Control Register */ /*! @{ */ + +#define USBPHY_ANACTRL_SET_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_SET_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_SET_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_LVI_EN_SHIFT)) & USBPHY_ANACTRL_SET_LVI_EN_MASK) + +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK) + #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN @@ -25295,6 +30681,15 @@ typedef struct { /*! @name ANACTRL_CLR - USB PHY Analog Control Register */ /*! @{ */ + +#define USBPHY_ANACTRL_CLR_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_CLR_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_CLR_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_LVI_EN_SHIFT)) & USBPHY_ANACTRL_CLR_LVI_EN_MASK) + +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK) + #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN @@ -25306,6 +30701,15 @@ typedef struct { /*! @name ANACTRL_TOG - USB PHY Analog Control Register */ /*! @{ */ + +#define USBPHY_ANACTRL_TOG_LVI_EN_MASK (0x2U) +#define USBPHY_ANACTRL_TOG_LVI_EN_SHIFT (1U) +#define USBPHY_ANACTRL_TOG_LVI_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_LVI_EN_SHIFT)) & USBPHY_ANACTRL_TOG_LVI_EN_MASK) + +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U) +#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK) + #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) /*! DEV_PULLDOWN @@ -25322,7 +30726,7 @@ typedef struct { /* USBPHY - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral USBPHY base address */ #define USBPHY_BASE (0x50038000u) /** Peripheral USBPHY base address */ @@ -25349,6 +30753,8 @@ typedef struct { /** Array initializer of USBPHY peripheral base pointers */ #define USBPHY_BASE_PTRS { USBPHY } #endif +/** Interrupt vectors for the USBPHY peripheral type */ +#define USBPHY_IRQS { USB1_PHY_IRQn } /*! * @} @@ -25384,75 +30790,133 @@ typedef struct { /*! @name CTRL - Control register. */ /*! @{ */ + #define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU) #define UTICK_CTRL_DELAYVAL_SHIFT (0U) +/*! DELAYVAL - Tick interval value. The delay will be equal to DELAYVAL + 1 periods of the timer + * clock. The minimum usable value is 1, for a delay of 2 timer clocks. A value of 0 stops the timer. + */ #define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK) + #define UTICK_CTRL_REPEAT_MASK (0x80000000U) #define UTICK_CTRL_REPEAT_SHIFT (31U) +/*! REPEAT - Repeat delay. 0 = One-time delay. 1 = Delay repeats continuously. + */ #define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK) /*! @} */ /*! @name STAT - Status register. */ /*! @{ */ + #define UTICK_STAT_INTR_MASK (0x1U) #define UTICK_STAT_INTR_SHIFT (0U) +/*! INTR - Interrupt flag. 0 = No interrupt is pending. 1 = An interrupt is pending. A write of any + * value to this register clears this flag. + */ #define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK) + #define UTICK_STAT_ACTIVE_MASK (0x2U) #define UTICK_STAT_ACTIVE_SHIFT (1U) +/*! ACTIVE - Active flag. 0 = The Micro-Tick Timer is stopped. 1 = The Micro-Tick Timer is currently active. + */ #define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK) /*! @} */ /*! @name CFG - Capture configuration register. */ /*! @{ */ + #define UTICK_CFG_CAPEN0_MASK (0x1U) #define UTICK_CFG_CAPEN0_SHIFT (0U) +/*! CAPEN0 - Enable Capture 0. 1 = Enabled, 0 = Disabled. + */ #define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK) + #define UTICK_CFG_CAPEN1_MASK (0x2U) #define UTICK_CFG_CAPEN1_SHIFT (1U) +/*! CAPEN1 - Enable Capture 1. 1 = Enabled, 0 = Disabled. + */ #define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK) + #define UTICK_CFG_CAPEN2_MASK (0x4U) #define UTICK_CFG_CAPEN2_SHIFT (2U) +/*! CAPEN2 - Enable Capture 2. 1 = Enabled, 0 = Disabled. + */ #define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK) + #define UTICK_CFG_CAPEN3_MASK (0x8U) #define UTICK_CFG_CAPEN3_SHIFT (3U) +/*! CAPEN3 - Enable Capture 3. 1 = Enabled, 0 = Disabled. + */ #define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK) + #define UTICK_CFG_CAPPOL0_MASK (0x100U) #define UTICK_CFG_CAPPOL0_SHIFT (8U) +/*! CAPPOL0 - Capture Polarity 0. 0 = Positive edge capture, 1 = Negative edge capture. + */ #define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK) + #define UTICK_CFG_CAPPOL1_MASK (0x200U) #define UTICK_CFG_CAPPOL1_SHIFT (9U) +/*! CAPPOL1 - Capture Polarity 1. 0 = Positive edge capture, 1 = Negative edge capture. + */ #define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK) + #define UTICK_CFG_CAPPOL2_MASK (0x400U) #define UTICK_CFG_CAPPOL2_SHIFT (10U) +/*! CAPPOL2 - Capture Polarity 2. 0 = Positive edge capture, 1 = Negative edge capture. + */ #define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK) + #define UTICK_CFG_CAPPOL3_MASK (0x800U) #define UTICK_CFG_CAPPOL3_SHIFT (11U) +/*! CAPPOL3 - Capture Polarity 3. 0 = Positive edge capture, 1 = Negative edge capture. + */ #define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK) /*! @} */ /*! @name CAPCLR - Capture clear register. */ /*! @{ */ + #define UTICK_CAPCLR_CAPCLR0_MASK (0x1U) #define UTICK_CAPCLR_CAPCLR0_SHIFT (0U) +/*! CAPCLR0 - Clear capture 0. Writing 1 to this bit clears the CAP0 register value. + */ #define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK) + #define UTICK_CAPCLR_CAPCLR1_MASK (0x2U) #define UTICK_CAPCLR_CAPCLR1_SHIFT (1U) +/*! CAPCLR1 - Clear capture 1. Writing 1 to this bit clears the CAP1 register value. + */ #define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK) + #define UTICK_CAPCLR_CAPCLR2_MASK (0x4U) #define UTICK_CAPCLR_CAPCLR2_SHIFT (2U) +/*! CAPCLR2 - Clear capture 2. Writing 1 to this bit clears the CAP2 register value. + */ #define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK) + #define UTICK_CAPCLR_CAPCLR3_MASK (0x8U) #define UTICK_CAPCLR_CAPCLR3_SHIFT (3U) +/*! CAPCLR3 - Clear capture 3. Writing 1 to this bit clears the CAP3 register value. + */ #define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK) /*! @} */ /*! @name CAP - Capture register . */ /*! @{ */ + #define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU) #define UTICK_CAP_CAP_VALUE_SHIFT (0U) +/*! CAP_VALUE - Capture value for the related capture event (UTICK_CAPn. Note: the value is 1 lower + * than the actual value of the Micro-tick Timer at the moment of the capture event. + */ #define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK) + #define UTICK_CAP_VALID_MASK (0x80000000U) #define UTICK_CAP_VALID_SHIFT (31U) +/*! VALID - Capture Valid. When 1, a value has been captured based on a transition of the related + * UTICK_CAPn pin. Cleared by writing to the related bit in the CAPCLR register. + */ #define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK) /*! @} */ @@ -25466,7 +30930,7 @@ typedef struct { /* UTICK - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral UTICK0 base address */ #define UTICK0_BASE (0x5000E000u) /** Peripheral UTICK0 base address */ @@ -25532,6 +30996,7 @@ typedef struct { /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ /*! @{ */ + #define WWDT_MOD_WDEN_MASK (0x1U) #define WWDT_MOD_WDEN_SHIFT (0U) /*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the @@ -25540,6 +31005,7 @@ typedef struct { * 0b1..Run. The watchdog timer is running. */ #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) + #define WWDT_MOD_WDRESET_MASK (0x2U) #define WWDT_MOD_WDRESET_SHIFT (1U) /*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. @@ -25547,12 +31013,24 @@ typedef struct { * 0b1..Reset. A watchdog time-out will cause a chip reset. */ #define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) + #define WWDT_MOD_WDTOF_MASK (0x4U) #define WWDT_MOD_WDTOF_SHIFT (2U) +/*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by + * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a + * chip reset if WDRESET = 1. + */ #define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) + #define WWDT_MOD_WDINT_MASK (0x8U) #define WWDT_MOD_WDINT_SHIFT (3U) +/*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. + * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the + * WARNINT value is equal to the value of the TV register. This can occur if the value of + * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. + */ #define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) + #define WWDT_MOD_WDPROTECT_MASK (0x10U) #define WWDT_MOD_WDPROTECT_SHIFT (4U) /*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. @@ -25564,36 +31042,51 @@ typedef struct { /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ /*! @{ */ + #define WWDT_TC_COUNT_MASK (0xFFFFFFU) #define WWDT_TC_COUNT_SHIFT (0U) +/*! COUNT - Watchdog time-out value. + */ #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) /*! @} */ /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ /*! @{ */ + #define WWDT_FEED_FEED_MASK (0xFFU) #define WWDT_FEED_FEED_SHIFT (0U) +/*! FEED - Feed value should be 0xAA followed by 0x55. + */ #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) /*! @} */ /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ /*! @{ */ + #define WWDT_TV_COUNT_MASK (0xFFFFFFU) #define WWDT_TV_COUNT_SHIFT (0U) +/*! COUNT - Counter timer value. + */ #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) /*! @} */ /*! @name WARNINT - Watchdog Warning Interrupt compare value. */ /*! @{ */ + #define WWDT_WARNINT_WARNINT_MASK (0x3FFU) #define WWDT_WARNINT_WARNINT_SHIFT (0U) +/*! WARNINT - Watchdog warning interrupt compare value. + */ #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) /*! @} */ /*! @name WINDOW - Watchdog Window compare value. */ /*! @{ */ + #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) #define WWDT_WINDOW_WINDOW_SHIFT (0U) +/*! WINDOW - Watchdog window value. + */ #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) /*! @} */ @@ -25604,7 +31097,7 @@ typedef struct { /* WWDT - Peripheral instance base addresses */ -#if (__ARM_FEATURE_CMSE & 0x2) +#if (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE & 0x2)) /** Peripheral WWDT base address */ #define WWDT_BASE (0x5000C000u) /** Peripheral WWDT base address */ @@ -25711,48 +31204,31 @@ typedef struct { /** High Speed SPI (Flexcomm 8) interrupt name */ #define LSPI_HS_IRQn FLEXCOMM8_IRQn -/** EMC CS base address */ -#define EMC_CS0_BASE (0x80000000u) -#define EMC_CS1_BASE (0x90000000u) -#define EMC_CS2_BASE (0x98000000u) -#define EMC_CS3_BASE (0x9C000000u) -#define EMC_DYCS0_BASE (0xA0000000u) -#define EMC_DYCS1_BASE (0xB0000000u) -#define EMC_DYCS2_BASE (0xC0000000u) -#define EMC_DYCS3_BASE (0xD0000000u) -#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE} -#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE} +/*! + * @brief Get the chip value. + * + * @return chip version, 0x0: A0 version chip, 0x1: A1 version chip, 0xFF: invalid version. + */ +static inline uint32_t Chip_GetVersion(void) +{ + uint32_t deviceRevision; -/** OTP API */ -typedef struct { - uint32_t (*otpInit)(void); /** Initializes OTP controller */ - uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */ - uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */ - uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, - uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */ - uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask, - uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */ - uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */ - uint32_t RESERVED_0[5]; - uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */ - uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */ -} OTP_API_Type; + deviceRevision = SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK; -/** ROM API */ -typedef struct { - __I uint32_t usbdApiBase; /** USB API Base */ - uint32_t RESERVED_0[13]; - __I OTP_API_Type *otpApiBase; /** OTP API Base */ - __I uint32_t aesApiBase; /** AES API Base */ - __I uint32_t secureApiBase; /** Secure API Base */ -} ROM_API_Type; + if(0UL == deviceRevision) /* A0 device revision is 0 */ + { + return 0x0; + } + else if(1UL == deviceRevision) /* A1 device revision is 1 */ + { + return 0x1; + } + else + { + return 0xFF; + } +} -/** ROM API base address */ -#define ROM_API_BASE (0x03000200u) -/** ROM API base pointer */ -#define ROM_API (*(ROM_API_Type**) ROM_API_BASE) -/** OTP API base pointer */ -#define OTP_API (ROM_API->otpApiBase) /*! * @} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml index edfadd5701..cbdca23f9d 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1.xml @@ -3,9 +3,9 @@ nxp.com LPC55S69_cm33_core1 1.0 - LPC55S69JBD100,LPC55S69JBD64,LPC55S69JET98 + LPC55S69JBD100,LPC55S69JBD64,LPC55S69JEV98 -Copyright 2016-2019 NXP +Copyright 2016-2021 NXP All rights reserved. SPDX-License-Identifier: BSD-3-Clause @@ -37,7 +37,7 @@ SPDX-License-Identifier: BSD-3-Clause HEADER - . + no description available 0 32 read-write @@ -46,7 +46,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -55,7 +55,7 @@ SPDX-License-Identifier: BSD-3-Clause VERSION - . + no description available 0x4 32 read-write @@ -64,7 +64,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -82,7 +82,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -100,7 +100,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -118,7 +118,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -127,7 +127,7 @@ SPDX-License-Identifier: BSD-3-Clause ROTKH_REVOKE - . + no description available 0x18 32 read-write @@ -155,11 +155,18 @@ SPDX-License-Identifier: BSD-3-Clause 2 read-write + + RoTK3_EN + RoT Key 3 enable. 00 - Invalid 01 - Enabled 10, 11 - Key revoked + 6 + 2 + read-write + VENDOR_USAGE - . + no description available 0x1C 32 read-write @@ -199,12 +206,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -218,12 +225,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -237,12 +244,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -256,12 +263,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -275,31 +282,31 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 - MCM33_DBGEN - Micro CM33 invasive debug enable + CPU1_DBGEN + CPU1 (Micro cortex M33) invasive debug enable 5 1 read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -313,12 +320,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -332,12 +339,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -351,31 +358,31 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 - MCM33_NIDEN - Micro CM33 non-invasive debug enable + CPU1_NIDEN + CPU1 (Micro cortex M33) non-invasive debug enable 9 1 read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -502,8 +509,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_DBGEN - Micro CM33 invasive debug fixed state + CPU1_DBGEN + CPU1 (Micro cortex M33) invasive debug fixed state 5 1 read-write @@ -578,8 +585,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_NIDEN - Micro CM33 non-invasive debug fixed state + CPU1_NIDEN + CPU1 (Micro cortex M33) non-invasive debug fixed state 9 1 read-write @@ -616,7 +623,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -634,7 +641,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -643,7 +650,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE0 - . + no description available PRINCE_REGION0_IV_CODE 0x30 32 @@ -653,7 +660,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -662,7 +669,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_HEADER0 - . + no description available PRINCE_REGION0_IV_CODE 0x30 32 @@ -672,7 +679,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -681,7 +688,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE1 - . + no description available PRINCE_REGION0_IV_CODE 0x34 32 @@ -691,7 +698,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -700,7 +707,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_HEADER1 - . + no description available PRINCE_REGION0_IV_CODE 0x34 32 @@ -710,21 +717,21 @@ SPDX-License-Identifier: BSD-3-Clause TYPE - . + no description available 0 2 read-write INDEX - . + no description available 8 4 read-write SIZE - . + no description available 24 6 read-write @@ -733,7 +740,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY0 - . + no description available PRINCE_REGION0_IV_CODE 0x38 32 @@ -743,7 +750,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -752,7 +759,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE2 - . + no description available PRINCE_REGION0_IV_CODE 0x38 32 @@ -762,7 +769,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -771,7 +778,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY1 - . + no description available PRINCE_REGION0_IV_CODE 0x3C 32 @@ -781,7 +788,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -790,7 +797,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE3 - . + no description available PRINCE_REGION0_IV_CODE 0x3C 32 @@ -800,7 +807,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -809,7 +816,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY2 - . + no description available PRINCE_REGION0_IV_CODE 0x40 32 @@ -819,7 +826,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -828,7 +835,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE4 - . + no description available PRINCE_REGION0_IV_CODE 0x40 32 @@ -838,7 +845,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -847,7 +854,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY3 - . + no description available PRINCE_REGION0_IV_CODE 0x44 32 @@ -857,7 +864,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -866,7 +873,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE5 - . + no description available PRINCE_REGION0_IV_CODE 0x44 32 @@ -876,7 +883,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -885,7 +892,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY4 - . + no description available PRINCE_REGION0_IV_CODE 0x48 32 @@ -895,7 +902,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -904,7 +911,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE6 - . + no description available PRINCE_REGION0_IV_CODE 0x48 32 @@ -914,7 +921,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -923,7 +930,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY5 - . + no description available PRINCE_REGION0_IV_CODE 0x4C 32 @@ -933,7 +940,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -942,7 +949,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE7 - . + no description available PRINCE_REGION0_IV_CODE 0x4C 32 @@ -952,7 +959,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -961,7 +968,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY6 - . + no description available PRINCE_REGION0_IV_CODE 0x50 32 @@ -971,7 +978,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -980,7 +987,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE8 - . + no description available PRINCE_REGION0_IV_CODE 0x50 32 @@ -990,7 +997,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -999,7 +1006,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY7 - . + no description available PRINCE_REGION0_IV_CODE 0x54 32 @@ -1009,7 +1016,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1018,7 +1025,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE9 - . + no description available PRINCE_REGION0_IV_CODE 0x54 32 @@ -1028,7 +1035,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1037,7 +1044,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY8 - . + no description available PRINCE_REGION0_IV_CODE 0x58 32 @@ -1047,7 +1054,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1056,7 +1063,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE10 - . + no description available PRINCE_REGION0_IV_CODE 0x58 32 @@ -1066,7 +1073,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1075,7 +1082,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY9 - . + no description available PRINCE_REGION0_IV_CODE 0x5C 32 @@ -1085,7 +1092,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1094,7 +1101,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE11 - . + no description available PRINCE_REGION0_IV_CODE 0x5C 32 @@ -1104,7 +1111,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1113,7 +1120,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY10 - . + no description available PRINCE_REGION0_IV_CODE 0x60 32 @@ -1123,7 +1130,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1132,7 +1139,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE12 - . + no description available PRINCE_REGION0_IV_CODE 0x60 32 @@ -1142,7 +1149,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1151,7 +1158,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_BODY11 - . + no description available PRINCE_REGION0_IV_CODE 0x64 32 @@ -1161,7 +1168,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1170,7 +1177,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION0_IV_CODE13 - . + no description available PRINCE_REGION0_IV_CODE 0x64 32 @@ -1180,7 +1187,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1189,7 +1196,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE0 - . + no description available PRINCE_REGION1_IV_CODE 0x68 32 @@ -1199,7 +1206,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1208,7 +1215,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_HEADER0 - . + no description available PRINCE_REGION1_IV_CODE 0x68 32 @@ -1218,7 +1225,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1227,7 +1234,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE1 - . + no description available PRINCE_REGION1_IV_CODE 0x6C 32 @@ -1237,7 +1244,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1246,7 +1253,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_HEADER1 - . + no description available PRINCE_REGION1_IV_CODE 0x6C 32 @@ -1256,21 +1263,21 @@ SPDX-License-Identifier: BSD-3-Clause TYPE - . + no description available 0 2 read-write INDEX - . + no description available 8 4 read-write SIZE - . + no description available 24 6 read-write @@ -1279,7 +1286,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY0 - . + no description available PRINCE_REGION1_IV_CODE 0x70 32 @@ -1289,7 +1296,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1298,7 +1305,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE2 - . + no description available PRINCE_REGION1_IV_CODE 0x70 32 @@ -1308,7 +1315,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1317,7 +1324,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY1 - . + no description available PRINCE_REGION1_IV_CODE 0x74 32 @@ -1327,7 +1334,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1336,7 +1343,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE3 - . + no description available PRINCE_REGION1_IV_CODE 0x74 32 @@ -1346,7 +1353,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1355,7 +1362,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY2 - . + no description available PRINCE_REGION1_IV_CODE 0x78 32 @@ -1365,7 +1372,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1374,7 +1381,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE4 - . + no description available PRINCE_REGION1_IV_CODE 0x78 32 @@ -1384,7 +1391,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1393,7 +1400,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY3 - . + no description available PRINCE_REGION1_IV_CODE 0x7C 32 @@ -1403,7 +1410,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1412,7 +1419,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE5 - . + no description available PRINCE_REGION1_IV_CODE 0x7C 32 @@ -1422,7 +1429,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1431,7 +1438,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY4 - . + no description available PRINCE_REGION1_IV_CODE 0x80 32 @@ -1441,7 +1448,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1450,7 +1457,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE6 - . + no description available PRINCE_REGION1_IV_CODE 0x80 32 @@ -1460,7 +1467,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1469,7 +1476,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY5 - . + no description available PRINCE_REGION1_IV_CODE 0x84 32 @@ -1479,7 +1486,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1488,7 +1495,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE7 - . + no description available PRINCE_REGION1_IV_CODE 0x84 32 @@ -1498,7 +1505,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1507,7 +1514,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY6 - . + no description available PRINCE_REGION1_IV_CODE 0x88 32 @@ -1517,7 +1524,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1526,7 +1533,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE8 - . + no description available PRINCE_REGION1_IV_CODE 0x88 32 @@ -1536,7 +1543,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1545,7 +1552,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY7 - . + no description available PRINCE_REGION1_IV_CODE 0x8C 32 @@ -1555,7 +1562,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1564,7 +1571,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE9 - . + no description available PRINCE_REGION1_IV_CODE 0x8C 32 @@ -1574,7 +1581,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1583,7 +1590,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY8 - . + no description available PRINCE_REGION1_IV_CODE 0x90 32 @@ -1593,7 +1600,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1602,7 +1609,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE10 - . + no description available PRINCE_REGION1_IV_CODE 0x90 32 @@ -1612,7 +1619,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1621,7 +1628,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY9 - . + no description available PRINCE_REGION1_IV_CODE 0x94 32 @@ -1631,7 +1638,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1640,7 +1647,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE11 - . + no description available PRINCE_REGION1_IV_CODE 0x94 32 @@ -1650,7 +1657,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1659,7 +1666,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY10 - . + no description available PRINCE_REGION1_IV_CODE 0x98 32 @@ -1669,7 +1676,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1678,7 +1685,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE12 - . + no description available PRINCE_REGION1_IV_CODE 0x98 32 @@ -1688,7 +1695,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1697,7 +1704,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_BODY11 - . + no description available PRINCE_REGION1_IV_CODE 0x9C 32 @@ -1707,7 +1714,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1716,7 +1723,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION1_IV_CODE13 - . + no description available PRINCE_REGION1_IV_CODE 0x9C 32 @@ -1726,7 +1733,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1735,7 +1742,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE0 - . + no description available PRINCE_REGION2_IV_CODE 0xA0 32 @@ -1745,7 +1752,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1754,7 +1761,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_HEADER0 - . + no description available PRINCE_REGION2_IV_CODE 0xA0 32 @@ -1764,7 +1771,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1773,7 +1780,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE1 - . + no description available PRINCE_REGION2_IV_CODE 0xA4 32 @@ -1783,7 +1790,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1792,7 +1799,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_HEADER1 - . + no description available PRINCE_REGION2_IV_CODE 0xA4 32 @@ -1802,21 +1809,21 @@ SPDX-License-Identifier: BSD-3-Clause TYPE - . + no description available 0 2 read-write INDEX - . + no description available 8 4 read-write SIZE - . + no description available 24 6 read-write @@ -1825,7 +1832,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY0 - . + no description available PRINCE_REGION2_IV_CODE 0xA8 32 @@ -1835,7 +1842,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1844,7 +1851,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE2 - . + no description available PRINCE_REGION2_IV_CODE 0xA8 32 @@ -1854,7 +1861,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1863,7 +1870,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY1 - . + no description available PRINCE_REGION2_IV_CODE 0xAC 32 @@ -1873,7 +1880,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1882,7 +1889,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE3 - . + no description available PRINCE_REGION2_IV_CODE 0xAC 32 @@ -1892,7 +1899,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1901,7 +1908,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY2 - . + no description available PRINCE_REGION2_IV_CODE 0xB0 32 @@ -1911,7 +1918,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1920,7 +1927,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE4 - . + no description available PRINCE_REGION2_IV_CODE 0xB0 32 @@ -1930,7 +1937,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1939,7 +1946,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY3 - . + no description available PRINCE_REGION2_IV_CODE 0xB4 32 @@ -1949,7 +1956,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1958,7 +1965,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE5 - . + no description available PRINCE_REGION2_IV_CODE 0xB4 32 @@ -1968,7 +1975,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1977,7 +1984,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY4 - . + no description available PRINCE_REGION2_IV_CODE 0xB8 32 @@ -1987,7 +1994,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -1996,7 +2003,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE6 - . + no description available PRINCE_REGION2_IV_CODE 0xB8 32 @@ -2006,7 +2013,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2015,7 +2022,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY5 - . + no description available PRINCE_REGION2_IV_CODE 0xBC 32 @@ -2025,7 +2032,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2034,7 +2041,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE7 - . + no description available PRINCE_REGION2_IV_CODE 0xBC 32 @@ -2044,7 +2051,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2053,7 +2060,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY6 - . + no description available PRINCE_REGION2_IV_CODE 0xC0 32 @@ -2063,7 +2070,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2072,7 +2079,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE8 - . + no description available PRINCE_REGION2_IV_CODE 0xC0 32 @@ -2082,7 +2089,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2091,7 +2098,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY7 - . + no description available PRINCE_REGION2_IV_CODE 0xC4 32 @@ -2101,7 +2108,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2110,7 +2117,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE9 - . + no description available PRINCE_REGION2_IV_CODE 0xC4 32 @@ -2120,7 +2127,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2129,7 +2136,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY8 - . + no description available PRINCE_REGION2_IV_CODE 0xC8 32 @@ -2139,7 +2146,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2148,7 +2155,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE10 - . + no description available PRINCE_REGION2_IV_CODE 0xC8 32 @@ -2158,7 +2165,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2167,7 +2174,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY9 - . + no description available PRINCE_REGION2_IV_CODE 0xCC 32 @@ -2177,7 +2184,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2186,7 +2193,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE11 - . + no description available PRINCE_REGION2_IV_CODE 0xCC 32 @@ -2196,7 +2203,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2205,7 +2212,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY10 - . + no description available PRINCE_REGION2_IV_CODE 0xD0 32 @@ -2215,7 +2222,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2224,7 +2231,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE12 - . + no description available PRINCE_REGION2_IV_CODE 0xD0 32 @@ -2234,7 +2241,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2243,7 +2250,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_BODY11 - . + no description available PRINCE_REGION2_IV_CODE 0xD4 32 @@ -2253,7 +2260,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2262,7 +2269,7 @@ SPDX-License-Identifier: BSD-3-Clause PRINCE_REGION2_IV_CODE13 - . + no description available PRINCE_REGION2_IV_CODE 0xD4 32 @@ -2272,7 +2279,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2292,7 +2299,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2303,7 +2310,7 @@ SPDX-License-Identifier: BSD-3-Clause 8 0x4 SHA256_DIGEST[%s] - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] + SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] 0x1E0 32 read-write @@ -2312,7 +2319,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2356,7 +2363,7 @@ SPDX-License-Identifier: BSD-3-Clause BOOT_CFG - . + no description available 0 32 read-write @@ -2371,27 +2378,32 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + AUTO_ISP Auto ISP 0 - VALUE_1 - USB_HID_MSC + USB_HID_ISP + USB_HID_ISP 0x1 - VALUE_2 - SPI Slave ISP + UART_ISP + UART ISP 0x2 - VALUE_3 - I2C Slave ISP + SPI_ISP + SPI Slave ISP 0x3 - VALUE_7 + I2C_ISP + I2C Slave ISP + 0x4 + + + DISABLE Disable ISP fall through 0x7 @@ -2411,12 +2423,12 @@ SPDX-License-Identifier: BSD-3-Clause VALUE_1 - 48MHz FRO + 96MHz FRO 0x1 VALUE_2 - 96MHz FRO + 48MHz FRO 0x2 @@ -2432,7 +2444,7 @@ SPDX-License-Identifier: BSD-3-Clause SPI_FLASH_CFG - . + no description available 0x4 32 read-write @@ -2440,17 +2452,17 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - FIELD - . + SPI_RECOVERY_BOOT_EN + SPI flash recovery boot is enabled, if non-zero value is written to this field. 0 - 32 + 5 read-write USB_ID - . + no description available 0x8 32 read-write @@ -2459,14 +2471,14 @@ SPDX-License-Identifier: BSD-3-Clause USB_VENDOR_ID - . + no description available 0 16 read-write USB_PRODUCT_ID - . + no description available 16 16 read-write @@ -2475,7 +2487,7 @@ SPDX-License-Identifier: BSD-3-Clause SDIO_CFG - . + no description available 0xC 32 read-write @@ -2484,7 +2496,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -2492,8 +2504,8 @@ SPDX-License-Identifier: BSD-3-Clause - DCFG_CC_SOCU_PIN - . + CC_SOCU_PIN + no description available 0x10 32 read-write @@ -2508,12 +2520,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2527,12 +2539,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2546,12 +2558,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2565,12 +2577,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2584,31 +2596,31 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 - MCM33_DBGEN - Micro CM33 invasive debug enable + CPU1_DBGEN + CPU1 (Micro cortex M33) invasive debug enable 5 1 read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2622,12 +2634,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2641,12 +2653,12 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2660,31 +2672,31 @@ SPDX-License-Identifier: BSD-3-Clause read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 - MCM33_NIDEN - Micro CM33 non-invasive debug enable + CPU1_NIDEN + CPU1 (Micro cortex M33) non-invasive debug enable 9 1 read-write - VALUE_0 + ENABLE Use DAP to enable 0 - VALUE_1 + DISABLE Fixed state 0x1 @@ -2707,8 +2719,8 @@ SPDX-License-Identifier: BSD-3-Clause - DCFG_CC_SOCU_DFLT - . + CC_SOCU_DFLT + no description available 0x14 32 read-write @@ -2811,8 +2823,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_DBGEN - Micro CM33 invasive debug fixed state + CPU1_DBGEN + CPU1 (Micro cortex M33) invasive debug fixed state 5 1 read-write @@ -2887,8 +2899,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_NIDEN - Micro CM33 non-invasive debug fixed state + CPU1_NIDEN + CPU1 (Micro cortex M33) non-invasive debug fixed state 9 1 read-write @@ -2915,8 +2927,8 @@ SPDX-License-Identifier: BSD-3-Clause - DAP_VENDOR_USAGE_FIXED - . + VENDOR_USAGE + no description available 0x18 32 read-write @@ -2934,7 +2946,7 @@ SPDX-License-Identifier: BSD-3-Clause SECURE_BOOT_CFG - . + Secure boot configuration flags. 0x1C 32 read-write @@ -2943,65 +2955,248 @@ SPDX-License-Identifier: BSD-3-Clause RSA4K - Use RSA4096 keys only. 00- RSA2048 keys 01, 10, 11 - RSA4096 keys + Use RSA4096 keys only. 0 2 read-write + + + VALUE_0 + Allow RSA2048 and higher + 0 + + + VALUE_1 + RSA4096 only + 0x1 + + + VALUE_2 + RSA4096 only + 0x2 + + + VALUE_3 + RSA4096 only + 0x3 + + - DICE_ENC_NXP_CFG - Include NXP area in DICE computation. 00 - not included 01, 10, 11 - included + DICE_INC_NXP_CFG + Include NXP area in DICE computation. 2 2 read-write + + + NOT_INCLUD + not included + 0 + + + INCLUD + included + 0x1 + + + VALUE_2 + included + 0x2 + + + VALUE_3 + included + 0x3 + + DICE_CUST_CFG - Include Customer factory area (including keys) in DICE computation. 00 - not included 01, 10, 11 - included + Include Customer factory area (including keys) in DICE computation. 4 2 read-write + + + NOT_INCLUD + not included + 0 + + + UNCLUD + included + 0x1 + + + VALUE_2 + included + 0x2 + + + VALUE_3 + included + 0x3 + + SKIP_DICE - Skip DICE computation. 00 - Enable DICE 01,10,11 - Disable DICE + Skip DICE computation 6 2 read-write + + + ENABLE + Enable DICE + 0 + + + DISABLE + Disable DICE + 0x1 + + + VALUE_2 + Disable DICE + 0x2 + + + VALUE_3 + Disable DICE + 0x3 + + TZM_IMAGE_TYPE - TrustZone-M mode. 00 - TZM mode in image header. 01 - Disable TZ-M. Boots to NonSecure. 10 - TZ-M enable boots to secure mode. 11 - Preset TZM checker from image header. + TrustZone-M mode 8 2 read-write + + + VALUE_0 + TZ-M image mode is taken from application image header + 0 + + + VALUE_1 + TZ-M disabled image, boots to non-secure mode + 0x1 + + + VALUE_2 + TZ-M enabled image, boots to secure mode + 0x2 + + + VALUE_3 + TZ-M enabled image with TZ-M preset, boot to secure mode TZ-M pre-configured by data from application image header + 0x3 + + BLOCK_SET_KEY - Block PUF key code generation. 00 - Enable Key code generation 01, 10, 11 - Disable key code generation + Block PUF key code generation 10 2 read-write + + + ALLOW + Allow PUF Key Code generation + 0 + + + DISABLE + Disable PUF Key Code generation + 0x1 + + + VALUE_2 + Disable PUF Key Code generation + 0x2 + + + VALUE_3 + Disable PUF Key Code generation + 0x3 + + BLOCK_ENROLL - Block PUF enrollement. 00 - Enable enrollment mode 01, 10, 11 - Disable further enrollmnet + Block PUF enrollement 12 2 read-write + + + ALLOW + Allow PUF enroll operation + 0 + + + DISABLE + Disable PUF enroll operation + 0x1 + + + VALUE_2 + Disable PUF enroll operation + 0x2 + + + VALUE_3 + Disable PUF enroll operation + 0x3 + + + + + DICE_INC_SEC_EPOCH + Include security EPOCH in DICE + 14 + 2 + read-write SEC_BOOT_EN - Secure boot enable. 00 - Plain image (internal flash with or without CRC) 01, 10, 11 - Boot signed images. (internal flash, RSA signed) + Secure boot enable 30 2 read-write + + + DISABLE + Plain image (internal flash with or without CRC) + 0 + + + ENABLE + Boot signed images. (internal flash, RSA signed) + 0x1 + + + VALUE_2 + Boot signed images. (internal flash, RSA signed) + 0x2 + + + VALUE_3 + Boot signed images. (internal flash, RSA signed) + 0x3 + + PRINCE_BASE_ADDR - . + no description available 0x20 32 read-write @@ -3010,66 +3205,169 @@ SPDX-License-Identifier: BSD-3-Clause ADDR0_PRG - Programmable portion of the base address of region 0. + Programmable portion of the base address of region 0 0 4 read-write ADDR1_PRG - Programmable portion of the base address of region 1. + Programmable portion of the base address of region 1 4 4 read-write ADDR2_PRG - Programmable portion of the base address of region 2. + Programmable portion of the base address of region 2 8 4 read-write LOCK_REG0 - Lock PRINCE region0 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. - 16 - 2 - read-write - - - LOCK_REG1 - Lock PRINCE region1 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. + Lock PRINCE region0 settings 18 2 read-write + + + UNLOCK + Region is not locked + 0 + + + LOCK + Region is locked + 0x1 + + + VALUE_2 + Region is locked + 0x2 + + + VALUE_3 + Region is locked + 0x3 + + - LOCK_REG2 - Lock PRINCE region2 settings. 00 - Region is not locked. 01, 10, 11 - Region is locked. + LOCK_REG1 + Lock PRINCE region1 settings 20 2 read-write + + + UNLOCK + Region is not locked + 0 + + + LOCK + Region is locked + 0x1 + + + VALUE_2 + Region is locked + 0x2 + + + VALUE_3 + Region is locked + 0x3 + + REG0_ERASE_CHECK_EN - For PRINCE region0 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + For PRINCE region0 enable checking whether all encrypted pages are erased together 24 2 read-write + + + DISABLE + Region is disabled + 0 + + + ENABLE + Region is enabled + 0x1 + + + VALUE_2 + Region is enabled + 0x2 + + + VALUE_3 + Region is enabled + 0x3 + + REG1_ERASE_CHECK_EN - For PRINCE region1 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + For PRINCE region1 enable checking whether all encrypted pages are erased together 26 2 read-write + + + DISABLE + Region is disabled + 0 + + + ENABLE + Region is enabled + 0x1 + + + VALUE_2 + Region is enabled + 0x2 + + + VALUE_3 + Region is enabled + 0x3 + + REG2_ERASE_CHECK_EN - For PRINCE region2 enable checking whether all encrypted pages are erased together. 00 - Check is disabled. 01, 10, 11 - Check is enabled. + For PRINCE region2 enable checking whether all encrypted pages are erased together 28 2 read-write + + + DISABLE + Region is disabled + 0 + + + ENABLE + Region is enabled + 0x1 + + + VALUE_2 + Region is enabled + 0x2 + + + VALUE_3 + Region is enabled + 0x3 + + @@ -3084,7 +3382,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -3102,7 +3400,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -3120,18 +3418,120 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write + + XTAL_32KHZ_CAPABANK_TRIM + Xtal 32kHz capabank triming. + 0x30 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIM_VALID + XTAL 32kHz capa bank trimmings + 0 + 1 + read-write + + + NOT_TRIM + Capa Bank trimmings not valid. Default trimmings value are used + 0 + + + VALID + Capa Bank trimmings valid + 0x1 + + + + + XTAL_LOAD_CAP_IEC_PF_X100 + Load capacitance, pF x 100. For example, 6pF becomes 600. + 1 + 10 + read-write + + + PCB_XIN_PARA_CAP_PF_X100 + PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 11 + 10 + read-write + + + PCB_XOUT_PARA_CAP_PF_X100 + PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 21 + 10 + read-write + + + + + XTAL_16MHZ_CAPABANK_TRIM + Xtal 16MHz capabank triming. + 0x34 + 32 + read-write + 0 + 0xFFFFFFFF + + + TRIM_VALID + XTAL 16MHz capa bank trimmings + 0 + 1 + read-write + + + NOT_TRIM + Capa Bank trimmings not valid. Default trimmings value are used + 0 + + + VALID + Capa Bank trimmings valid + 0x1 + + + + + XTAL_LOAD_CAP_IEC_PF_X100 + Load capacitance, pF x 100. For example, 6pF becomes 600. + 1 + 10 + read-write + + + PCB_XIN_PARA_CAP_PF_X100 + PCB XIN parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 11 + 10 + read-write + + + PCB_XOUT_PARA_CAP_PF_X100 + PCB XOUT parasitic capacitance, pF x 100. For example, 6pF becomes 600. + 21 + 10 + read-write + + + 8 0x4 ROTKH[%s] - ROTKH0 for Root of Trust Keys Table hash[255:224] ROTKH1 for Root of Trust Keys Table hash[223:192] ROTKH2 for Root of Trust Keys Table hash[191:160] ROTKH3 for Root of Trust Keys Table hash[159:128] ROTKH4 for Root of Trust Keys Table hash[127:96] ROTKH5 for Root of Trust Keys Table hash[95:64] ROTKH6 for Root of Trust Keys Table hash[63:32] ROTKH7 for Root of Trust Keys Table hash[31:0] + ROTKHindex for Root of Trust Keys Table hash[(((7 - index) * 32) + 31):((7 - index) * 32)] 0x50 32 read-write @@ -3140,7 +3540,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -3160,7 +3560,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -3171,7 +3571,7 @@ SPDX-License-Identifier: BSD-3-Clause 8 0x4 SHA256_DIGEST[%s] - SHA256_DIGEST0 for DIGEST[31:0] SHA256_DIGEST1 for DIGEST[63:32] SHA256_DIGEST2 for DIGEST[95:64] SHA256_DIGEST3 for DIGEST[127:96] SHA256_DIGEST4 for DIGEST[159:128] SHA256_DIGEST5 for DIGEST[191:160] SHA256_DIGEST6 for DIGEST[223:192] SHA256_DIGEST7 for DIGEST[255:224] + SHA256_DIGESTindex for DIGEST[((index * 32) + 31):(index * 32)] 0x1E0 32 read-write @@ -3180,7 +3580,7 @@ SPDX-License-Identifier: BSD-3-Clause FIELD - . + no description available 0 32 read-write @@ -6595,29 +6995,29 @@ SPDX-License-Identifier: BSD-3-Clause 0x3FFFFFF - PRI_TEAL_CBUS - Teal C-AHB bus. + PRI_CPU0_CBUS + CPU0 C-AHB bus. 0 2 read-write - PRI_TEAL_SBUS - Teal S-AHB bus. + PRI_CPU0_SBUS + CPU0 S-AHB bus. 2 2 read-write - PRI_UTEAL_CBUS - Micro Teal C-AHB bus. + PRI_CPU1_CBUS + CPU1 C-AHB bus. 4 2 read-write - PRI_UTEAL_SBUS - Micro Teal S-AHB bus. + PRI_CPU1_SBUS + CPU1 S-AHB bus. 6 2 read-write @@ -6636,20 +7036,6 @@ SPDX-License-Identifier: BSD-3-Clause 2 read-write - - PRI_EZH_B_D - EZH B data bus. - 12 - 2 - read-write - - - PRI_EZH_B_I - EZH B instruction bus. - 14 - 2 - read-write - PRI_SDIO SDIO. @@ -6659,14 +7045,14 @@ SPDX-License-Identifier: BSD-3-Clause PRI_PQ - PQ (Teal HW Accelerator). + PQ (HW Accelerator). 18 2 read-write - PRI_SHA2 - SHA-2. + PRI_HASH_AES + HASH_AES. 20 2 read-write @@ -6697,8 +7083,8 @@ SPDX-License-Identifier: BSD-3-Clause 0x3FFFFFF - CAL - System tick timer calibration value. + TENMS + Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. 0 24 read-write @@ -6712,7 +7098,7 @@ SPDX-License-Identifier: BSD-3-Clause NOREF - Initial value for the Systick timer. + Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. 25 1 read-write @@ -6729,15 +7115,15 @@ SPDX-License-Identifier: BSD-3-Clause 0x3FFFFFF - CAL - System tick timer calibration value. + TENMS + Reload value for 10 ms (100 Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. 0 24 read-write SKEW - Initial value for the Systick timer. + Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. 24 1 read-write @@ -6752,7 +7138,7 @@ SPDX-License-Identifier: BSD-3-Clause - CPU1TCKCAL + CPU1STCKCAL System tick calibration for CPU1 0x40 32 @@ -6761,22 +7147,22 @@ SPDX-License-Identifier: BSD-3-Clause 0x3FFFFFF - CAL - System tick timer calibration value. + TENMS + Reload value for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as zero, the calibration value is not known. 0 24 read-write SKEW - Initial value for the Systick timer. + Indicates whether the TENMS value is exact: 0 = TENMS value is exact; 1 = TENMS value is inexact, or not given. 24 1 read-write NOREF - Initial value for the Systick timer. + Indicates whether the device provides a reference clock to the processor: 0 = reference clock provided; 1 = no reference clock provided. 25 1 read-write @@ -6966,8 +7352,8 @@ SPDX-License-Identifier: BSD-3-Clause - MUX0_RST - Input Mux 0 reset control. + MUX_RST + Input Mux reset control. 11 1 read-write @@ -7282,8 +7668,8 @@ SPDX-License-Identifier: BSD-3-Clause - OSTIMER0_RST - OS Timer 0 reset control. + OSTIMER_RST + OS Event Timer reset control. 1 1 read-write @@ -7301,8 +7687,8 @@ SPDX-License-Identifier: BSD-3-Clause - SCT0_RST - SCT0 reset control. + SCT_RST + SCT reset control. 2 1 read-write @@ -7339,8 +7725,8 @@ SPDX-License-Identifier: BSD-3-Clause - UTICK0_RST - UTICK0 reset control. + UTICK_RST + UTICK reset control. 10 1 read-write @@ -7585,63 +7971,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PVT_RST - PVT reset control. - 28 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - EZHA_RST - EZH a reset control. - 30 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - EZHB_RST - EZH b reset control. - 31 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - @@ -7825,63 +8154,6 @@ SPDX-License-Identifier: BSD-3-Clause - - GPIO4_RST - GPIO4 reset control. - 9 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - GPIO5_RST - GPIO5 reset control. - 10 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - - - OTP_RST - OTP reset control. - 12 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - RNG_RST RNG reset control. @@ -7902,9 +8174,9 @@ SPDX-License-Identifier: BSD-3-Clause - MUX1_RST - Peripheral Input Mux 1 reset control. - 14 + SYSCTL_RST + SYSCTL Block reset. + 15 1 read-write @@ -7959,8 +8231,8 @@ SPDX-License-Identifier: BSD-3-Clause - HASH0_RST - HASH0 reset control. + HASH_AES_RST + HASH_AES reset control. 18 1 read-write @@ -8091,25 +8363,6 @@ SPDX-License-Identifier: BSD-3-Clause - - CAPT0_RST - CAPT0 reset control. - 25 - 1 - read-write - - - RELEASED - Bloc is not reset. - 0 - - - ASSERTED - Bloc is reset. - 0x1 - - - ANALOG_CTRL_RST analog control reset control. @@ -8231,7 +8484,7 @@ SPDX-License-Identifier: BSD-3-Clause 3 0x4 PRESETCTRLCLR[%s] - Peripheral reset contro clearl register + Peripheral reset control clear register 0x140 32 read-write @@ -8421,8 +8674,8 @@ SPDX-License-Identifier: BSD-3-Clause - MUX0 - Enables the clock for the Input Mux 0. + MUX + Enables the clock for the Input Mux. 11 1 read-write @@ -8737,8 +8990,8 @@ SPDX-License-Identifier: BSD-3-Clause - OSTIMER0 - Enables the clock for the OS Timer 0. + OSTIMER + Enables the clock for the OS Event Timer. 1 1 read-write @@ -8756,8 +9009,8 @@ SPDX-License-Identifier: BSD-3-Clause - SCT0 - Enables the clock for the SCT0. + SCT + Enables the clock for the SCT. 2 1 read-write @@ -8775,27 +9028,8 @@ SPDX-License-Identifier: BSD-3-Clause - SCTIPU - Enables the clock for the SCTIPU. - 6 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - UTICK0 - Enables the clock for the UTICK0. + UTICK + Enables the clock for the UTICK. 10 1 read-write @@ -9040,63 +9274,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PVT - Enables the clock for the PVT. - 28 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - EZHA - Enables the clock for the EZH a. - 30 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - EZHB - Enables the clock for the EZH b. - 31 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - @@ -9280,63 +9457,6 @@ SPDX-License-Identifier: BSD-3-Clause - - GPIO4 - Enables the clock for the GPIO4. - 9 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - GPIO5 - Enables the clock for the GPIO5. - 10 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - - - OTP - Enables the clock for the OTP. - 12 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - RNG Enables the clock for the RNG. @@ -9357,9 +9477,9 @@ SPDX-License-Identifier: BSD-3-Clause - MUX1 - Enables the clock for the Peripheral Input Mux 1. - 14 + SYSCTL + SYSCTL block clock. + 15 1 read-write @@ -9414,8 +9534,8 @@ SPDX-License-Identifier: BSD-3-Clause - HASH0 - Enables the clock for the HASH0. + HASH_AES + Enables the clock for the HASH_AES. 18 1 read-write @@ -9546,25 +9666,6 @@ SPDX-License-Identifier: BSD-3-Clause - - CAPT0 - Enables the clock for the CAPT0. - 25 - 1 - read-write - - - DISABLE - Disable Clock. - 0 - - - ENABLE - Enable Clock. - 0x1 - - - ANALOG_CTRL Enables the clock for the analog control. @@ -10358,26 +10459,6 @@ SPDX-License-Identifier: BSD-3-Clause FRO 96 MHz clock. 0x3 - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - @@ -10418,26 +10499,6 @@ SPDX-License-Identifier: BSD-3-Clause Oscillator 32 kHz clock. 0x3 - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - No clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - @@ -10653,11 +10714,6 @@ SPDX-License-Identifier: BSD-3-Clause FRO 96 MHz clock. 0x2 - - ENUM_0x3 - No clock. - 0x3 - ENUM_0x4 No clock. @@ -10742,66 +10798,6 @@ SPDX-License-Identifier: BSD-3-Clause - - USB1CLKSEL - HS USB clock source select - NOT USED - 0x2AC - 32 - read-write - 0x7 - 0x7 - - - SEL - HS USB clock source select. - 0 - 3 - read-write - - - ENUM_0x0 - Main clock. - 0 - - - ENUM_0x1 - PLL0 clock. - 0x1 - - - ENUM_0x2 - CLKIN clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - - - ENUM_0x4 - No clock. - 0x4 - - - ENUM_0x5 - PLL1 clock. - 0x5 - - - ENUM_0x6 - No clock. - 0x6 - - - ENUM_0x7 - No clock. - 0x7 - - - - - FCCLKSEL0 Flexcomm Interface 0 clock source select for Fractional Rate Divider @@ -11528,16 +11524,6 @@ SPDX-License-Identifier: BSD-3-Clause PLL0 clock. 0x1 - - ENUM_0x2 - No clock. - 0x2 - - - ENUM_0x3 - No clock. - 0x3 - ENUM_0x4 No clock. @@ -13049,115 +13035,192 @@ SPDX-License-Identifier: BSD-3-Clause FMCCR - FMC configuration register - INTERNAL USE ONLY + FMC configuration register 0x400 32 read-write - 0x3000 + 0x2000 0xFFFFFFFF - FETCHCTL - Fetch control + FETCHCFG + Instruction fetch configuration. 0 2 read-write NOBUF - No buffering (bypass always used) for Fetch cycles + Instruction fetches from flash are not buffered. 0 ONEBUF - One buffer is used for all Fetch cycles + One buffer is used for all instruction fetches. 0x1 ALLBUF - All buffers can be used for Fetch cycles + All buffers may be used for instruction fetches. 0x2 - DATACTL - Data control + DATACFG + Data read configuration. 2 2 read-write NOBUF - No buffering (bypass always used) for Data cycles + Data accesses from flash are not buffered. 0 ONEBUF - One buffer is used for all Data cycles + One buffer is used for all data accesses. 0x1 ALLBUF - All buffers can be used for Data cycles + All buffers can be used for data accesses. 0x2 ACCEL - ACCEL + Acceleration enable. 4 1 read-write + + + DISABLE + Flash acceleration is disabled. + 0 + + + ENABLE + Flash acceleration is enabled. + 0x1 + + PREFEN - Pref enable + Prefetch enable. 5 1 read-write + + + DISABLE + No instruction prefetch is performed. + 0 + + + ENABLE + Instruction prefetch is enabled. + 0x1 + + PREFOVR - Pref ovr + Prefetch override. 6 1 read-write + + + NORMAL + Any previously initiated prefetch will be completed. + 0 + + + OVERRIDE + Any previously initiated prefetch will be aborted, and the next flash line following the current execution address will be prefetched if not already buffered. + 0x1 + + - PREFCRI - Pref CRI - 8 - 3 - read-write - - - FMCTIM - TMC time + FLASHTIM + Flash memory access time. 12 - 5 - read-write - - - PFISLRU - When set, prefetch uses LRU buffer replacement policy - 17 - 1 - read-write - - - PFADAP - When set, prefetch will adaptively select between parent and LRU buffer replacement policies. - 18 - 1 + 4 read-write + + + FLASHTIM0 + 1 system clock flash access time (for system clock rates up to 11 MHz). + 0 + + + FLASHTIM1 + 2 system clocks flash access time (for system clock rates up to 22 MHz). + 0x1 + + + FLASHTIM2 + 3 system clocks flash access time (for system clock rates up to 33 MHz). + 0x2 + + + FLASHTIM3 + 4 system clocks flash access time (for system clock rates up to 44 MHz). + 0x3 + + + FLASHTIM4 + 5 system clocks flash access time (for system clock rates up to 55 MHz). + 0x4 + + + FLASHTIM5 + 6 system clocks flash access time (for system clock rates up to 66 MHz). + 0x5 + + + FLASHTIM6 + 7 system clocks flash access time (for system clock rates up to 77 MHz). + 0x6 + + + FLASHTIM7 + 8 system clocks flash access time (for system clock rates up to 88 MHz). + 0x7 + + + FLASHTIM8 + 9 system clocks flash access time (for system clock rates up to 100 MHz). + 0x8 + + + FLASHTIM9 + 10 system clocks flash access time (for system clock rates up to 115 MHz). + 0x9 + + + FLASHTIM10 + 11 system clocks flash access time (for system clock rates up to 130 MHz). + 0xA + + + FLASHTIM11 + 12 system clocks flash access time (for system clock rates up to 150 MHz). + 0xB + + - USB0CLKCTRL - USB0 clock control + USB0NEEDCLKCTRL + USB0 need clock control 0x40C 32 read-write @@ -13165,7 +13228,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x1F - AP_FS_DEV_CLK + AP_FS_DEV_NEEDCLK USB0 Device USB0_NEEDCLK signal control:. 0 1 @@ -13184,7 +13247,7 @@ SPDX-License-Identifier: BSD-3-Clause - POL_FS_DEV_CLK + POL_FS_DEV_NEEDCLK USB0 Device USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. 1 1 @@ -13203,7 +13266,7 @@ SPDX-License-Identifier: BSD-3-Clause - AP_FS_HOST_CLK + AP_FS_HOST_NEEDCLK USB0 Host USB0_NEEDCLK signal control:. 2 1 @@ -13222,7 +13285,7 @@ SPDX-License-Identifier: BSD-3-Clause - POL_FS_HOST_CLK + POL_FS_HOST_NEEDCLK USB0 Host USB0_NEEDCLK polarity for triggering the USB0 wake-up interrupt:. 3 1 @@ -13240,30 +13303,11 @@ SPDX-License-Identifier: BSD-3-Clause - - PU_DISABLE - Internal pull-up disable control. - 4 - 1 - read-write - - - ENABLE - Internal pull-up enable. - 0 - - - DISABLE - Internal pull-up disable. - 0x1 - - - - USB0CLKSTAT - USB0 clock status + USB0NEEDCLKSTAT + USB0 need clock status 0x410 32 read-write @@ -13271,7 +13315,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x3 - DEV_NEED_CLKST + DEV_NEEDCLK USB0 Device USB0_NEEDCLK signal status:. 0 1 @@ -13290,7 +13334,7 @@ SPDX-License-Identifier: BSD-3-Clause - HOST_NEED_CLKST + HOST_NEEDCLK USB0 Host USB0_NEEDCLK signal status:. 1 1 @@ -13321,10 +13365,22 @@ SPDX-License-Identifier: BSD-3-Clause FLUSH - no description available + Flush control 0 1 write-only + + + NO_FLUSH + No action is performed. + 0 + + + FLUSH + Flush the FMC buffer contents. + 0x1 + + @@ -13341,7 +13397,7 @@ SPDX-License-Identifier: BSD-3-Clause MCLKIO MCLK control. 0 - 32 + 1 read-write @@ -13359,8 +13415,8 @@ SPDX-License-Identifier: BSD-3-Clause - USB1CLKCTRL - USB1 clock control + USB1NEEDCLKCTRL + USB1 need clock control 0x424 32 read-write @@ -13368,96 +13424,96 @@ SPDX-License-Identifier: BSD-3-Clause 0x1F - AP_HS_DEV_CLK - USB1 Device need_clock signal control:. + AP_HS_DEV_NEEDCLK + USB1 Device need_clock signal control: 0 1 read-write HW_CTRL - Under hardware control. + HOST_NEEDCLK is under hardware control. 0 FORCED - Forced high. + HOST_NEEDCLK is forced high. 0x1 - POL_HS_DEV_CLK - USB1 Device need_clock polarity for triggering the USB1 wake-up interrupt:. + POL_HS_DEV_NEEDCLK + USB1 device need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt: 1 1 read-write FALLING - Falling edge of device need_clock triggers wake-up. + Falling edge of DEV_NEEDCLK triggers wake-up. 0 RISING - Rising edge of device need_clock triggers wake-up. + Rising edge of DEV_NEEDCLK triggers wake-up. 0x1 - AP_HS_HOST_CLK - USB1 Host need_clock signal control:. + AP_HS_HOST_NEEDCLK + USB1 Host need clock signal control: 2 1 read-write HW_CTRL - Under hardware control. + HOST_NEEDCLK is under hardware control. 0 FORCED - Forced high. + HOST_NEEDCLK is forced high. 0x1 - POL_HS_HOST_CLK - USB1 Host need_clock polarity for triggering the USB1 wake-up interrupt: 0 Falling edge of device need_clock triggers wake-up. + POL_HS_HOST_NEEDCLK + USB1 host need clock polarity for triggering the USB1_NEEDCLK wake-up interrupt. 3 1 read-write FALLING - Falling edge of device need_clock triggers wake-up. + Falling edge of HOST_NEEDCLK triggers wake-up. 0 RISING - Rising edge of device need_clock triggers wake-up. + Rising edge of HOST_NEEDCLK triggers wake-up. 0x1 HS_DEV_WAKEUP_N - External user wake-up signal for device mode; asserting this signal (active low) will result in exiting the low power mode; input to synchronous control logic:. + Software override of device controller PHY wake up logic. 4 1 read-write FORCE_WUP - Forces USB1 PHY to wake-up. + Forces USB1_PHY to wake-up. 0 NORMAL_WUP - Normal USB1 PHY behavior. + Normal USB1_PHY behavior. 0x1 @@ -13465,8 +13521,8 @@ SPDX-License-Identifier: BSD-3-Clause - USB1CLKSTAT - USB1 clock status + USB1NEEDCLKSTAT + USB1 need clock status 0x428 32 read-write @@ -13474,7 +13530,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x3 - DEV_NEED_CLKST + DEV_NEEDCLK USB1 Device need_clock signal status:. 0 1 @@ -13482,18 +13538,18 @@ SPDX-License-Identifier: BSD-3-Clause LOW - USB1 Device clock is low. + DEV_NEEDCLK is low. 0 HIGH - USB1 Device clock is high. + DEV_NEEDCLK is high. 0x1 - HOST_NEED_CLKST + HOST_NEEDCLK USB1 Host need_clock signal status:. 1 1 @@ -13501,86 +13557,18 @@ SPDX-License-Identifier: BSD-3-Clause LOW - USB1 Host clock is low. + HOST_NEEDCLK is low. 0 HIGH - USB1 Host clock is high. + HOST_NEEDCLK is high. 0x1 - - FLASHBANKENABLE - Flash Banks control - 0x450 - 32 - read-write - 0 - 0xFFF - - - BANK0 - Flash Bank0 control. - 0 - 4 - read-write - - - ENABLE - Flash BANK0 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - 0 - - - DISABLE - 1010: Flash BANK0 checker is disabled (all Flash pages inside this bank can be erased and programmed). - 0xA - - - - - BANK1 - Flash Bank1 control. - 4 - 4 - read-write - - - ENABLE - Flash BANK1 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - 0 - - - DISABLE - 1010: Flash BANK1 checker is disabled (all Flash pages inside this bank can be erased and programmed). - 0xA - - - - - BANK2 - Flash Bank2 control. - 8 - 4 - read-write - - - ENABLE - Flash BANK2 checker is enabled (all Flash pages inside this bank cannot be erased nor programmed). - 0 - - - DISABLE - 1010: Flash BANK2 checker is disabled (all Flash pages inside this bank can be erased and programmed). - 0xA - - - - - SDIOCLKCTRL SDIO CCLKIN phase and delay control @@ -14415,1795 +14403,45 @@ SPDX-License-Identifier: BSD-3-Clause - EFUSECLKCTRL - eFUSE controller clock enable - 0x5CC + FUNCRETENTIONCTRL + Functional retention control register + 0x704 32 read-write - 0x1 - 0xFFFFFFFF + 0x50C000 + 0xFFFFFF - EFUSECLKENA - eFUSE controller clock enable. - 0 - 1 - read-write - - - - - STARTER0 - Start logic wake-up enable register - 0x680 - 32 - read-write - 0 - 0xF97FFFFF - - - SYS - SYS interrupt wake-up. + FUNCRETENA + functional retention in power down only. 0 1 read-write DISABLE - Wake-up disabled. + disable functional retention. 0 ENABLE - Wake-up enabled. + enable functional retention. 0x1 - SDMA0 - SDMA0 interrupt wake-up. + RET_START + Start address divided by 4 inside SRAMX bank. 1 - 1 + 13 read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - GINT0 - GINT0 interrupt wake-up. - 2 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - GINT1 - GINT1 interrupt wake-up. - 3 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PIO_INT0 - PIO_INT0 interrupt wake-up. - 4 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PIO_INT1 - PIO_INT1 interrupt wake-up. - 5 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PIO_INT2 - PIO_INT2 interrupt wake-up. - 6 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PIO_INT3 - PIO_INT3 interrupt wake-up. - 7 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - UTICK0 - UTICK0 interrupt wake-up. - 8 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - MRT0 - MRT0 interrupt wake-up. - 9 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CTIMER0 - CTIMER0 interrupt wake-up. - 10 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CTIMER1 - CTIMER1 interrupt wake-up. - 11 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SCT0 - SCT0 interrupt wake-up. - 12 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CTIMER3 - CTIMER3 interrupt wake-up. - 13 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT0 - FLEXINT0 interrupt wake-up. + RET_LENTH + lenth of Scan chains to save. 14 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT1 - FLEXINT1 interrupt wake-up. - 15 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT2 - FLEXINT2 interrupt wake-up. - 16 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT3 - FLEXINT3 interrupt wake-up. - 17 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT4 - FLEXINT4 interrupt wake-up. - 18 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT5 - FLEXINT5 interrupt wake-up. - 19 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT6 - FLEXINT6 interrupt wake-up. - 20 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - FLEXINT7 - FLEXINT7 interrupt wake-up. - 21 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - ADC0 - ADC0 interrupt wake-up. - 22 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - ADC0_THCMP_OVR - ADC0_THCMP_OVR interrupt wake-up. - 24 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - USB0_NEEDCLK - USB0_NEEDCLK interrupt wake-up. - 27 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - USB0 - USB0 interrupt wake-up. - 28 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - RTC_LITE0 - RTC_LITE0 interrupt wake-up. - 29 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - EZH_ARCH_B0 - EZH_ARCH_B0 interrupt wake-up. - 30 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - WAKEUP_MAILBOX0 - WAKEUP_MAILBOX0 interrupt wake-up. - 31 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - - - STARTER1 - Start logic wake-up enable register - 0x684 - 32 - read-write - 0 - 0xFFFF847F - - - GPIO_INT04 - GPIO_INT04 interrupt wake-up. - 0 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - GPIO_INT05 - GPIO_INT05 interrupt wake-up. - 1 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - GPIO_INT06 - GPIO_INT06 interrupt wake-up. - 2 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - GPIO_INT07 - GPIO_INT07 interrupt wake-up. - 3 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CTIMER2 - CTIMER2 interrupt wake-up. - 4 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CTIMER4 - CTIMER4 interrupt wake-up. - 5 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - OS_EVENT - OS_EVENT interrupt wake-up. - 6 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SDIO - SDIO interrupt wake-up. - 10 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - USB1 - USB1 interrupt wake-up. - 15 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - USB1_NEEDCLK - USB1_NEEDCLK interrupt wake-up. - 16 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SEC_HYPERVISOR_CALL - SEC_HYPERVISOR_CALL interrupt wake-up. - 17 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SEC_GPIO_INT00 - SEC_GPIO_INT00 interrupt wake-up. - 18 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SEC_GPIO_INT01 - SEC_GPIO_INT01 interrupt wake-up. - 19 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PLU - PLU interrupt wake-up. - 20 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SEC_VIO - SEC_VIO interrupt wake-up. - 21 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SHA - SHA interrupt wake-up. - 22 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - CASER - CASER interrupt wake-up. - 23 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - QDDKEY - QDDKEY interrupt wake-up. - 24 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - PQ - PQ interrupt wake-up. - 25 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - SDMA1 - SDMA1 interrupt wake-up. - 26 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - LSPI_HS - LSPI_HS interrupt wake-up. - 27 - 1 - read-write - - - DISABLE - Wake-up disabled. - 0 - - - ENABLE - Wake-up enabled. - 0x1 - - - - - WAKEUPPADS - WAKEUPPADS interrupt wake-up. - 31 - 1 - read-write - - - - - STARTERSET0 - Set bits in STARTER - 0x6A0 - 32 - write-only - 0 - 0xF97FFFFF - - - SYS_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 0 - 1 - write-only - - - SDMA0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 1 - 1 - write-only - - - GPIO_GLOBALINT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 2 - 1 - write-only - - - GPIO_GLOBALINT1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 3 - 1 - write-only - - - GPIO_INT00_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 4 - 1 - write-only - - - GPIO_INT01_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 5 - 1 - write-only - - - GPIO_INT02_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 6 - 1 - write-only - - - GPIO_INT03_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 7 - 1 - write-only - - - UTICK0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 8 - 1 - write-only - - - MRT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 9 - 1 - write-only - - - CTIMER0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 10 - 1 - write-only - - - CTIMER1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 11 - 1 - write-only - - - SCT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 12 - 1 - write-only - - - CTIMER3_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 13 - 1 - write-only - - - FLEXINT0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 14 - 1 - write-only - - - FLEXINT1_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 15 - 1 - write-only - - - FLEXINT2_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 16 - 1 - write-only - - - FLEXINT3_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 17 - 1 - write-only - - - FLEXINT4_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 18 - 1 - write-only - - - FLEXINT5_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 19 - 1 - write-only - - - FLEXINT6_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 20 - 1 - write-only - - - FLEXINT7_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 21 - 1 - write-only - - - ADC0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 22 - 1 - write-only - - - ADC0_THCMP_OVR_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 24 - 1 - write-only - - - USB0_NEEDCLK_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 27 - 1 - write-only - - - USB0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 28 - 1 - write-only - - - RTC_LITE0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 29 - 1 - write-only - - - EZH_ARCH_B0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 30 - 1 - write-only - - - WAKEUP_MAILBOX0_SET - Writing ones to this register sets the corresponding bit in the STARTER0 register. - 31 - 1 - write-only - - - - - STARTERSET1 - Set bits in STARTER - 0x6A4 - 32 - write-only - 0 - 0x8FFF847F - - - GPIO_INT04_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 0 - 1 - write-only - - - GPIO_INT05_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 1 - 1 - write-only - - - GPIO_INT06_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 2 - 1 - write-only - - - GPIO_INT07_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 3 - 1 - write-only - - - CTIMER2_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 4 - 1 - write-only - - - CTIMER4_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 5 - 1 - write-only - - - OS_EVENT_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 6 - 1 - write-only - - - SDIO_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 10 - 1 - write-only - - - USB1_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 15 - 1 - write-only - - - USB1_NEEDCLK_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 16 - 1 - write-only - - - SEC_HYPERVISOR_CALL_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 17 - 1 - write-only - - - SEC_GPIO_INT00_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 18 - 1 - write-only - - - SEC_GPIO_INT01_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 19 - 1 - write-only - - - PLU_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 20 - 1 - write-only - - - SEC_VIO_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 21 - 1 - write-only - - - SHA_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 22 - 1 - write-only - - - CASER_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 23 - 1 - write-only - - - QDDKEY_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 24 - 1 - write-only - - - PQ_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 25 - 1 - write-only - - - SDMA1_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 26 - 1 - write-only - - - LSPI_HS_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 27 - 1 - write-only - - - WAKEUPPADS_SET - Writing ones to this register sets the corresponding bit in the STARTER1 register. - 31 - 1 - write-only - - - - - STARTERCLR0 - Clear bits in STARTER - 0x6C0 - 32 - write-only - 0 - 0xF97FFFFF - - - SYS_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 0 - 1 - write-only - - - SDMA0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 1 - 1 - write-only - - - GPIO_GLOBALINT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 2 - 1 - write-only - - - GPIO_GLOBALINT1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 3 - 1 - write-only - - - GPIO_INT00_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 4 - 1 - write-only - - - GPIO_INT01_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 5 - 1 - write-only - - - GPIO_INT02_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 6 - 1 - write-only - - - GPIO_INT03_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 7 - 1 - write-only - - - UTICK0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 8 - 1 - write-only - - - MRT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 9 - 1 - write-only - - - CTIMER0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 10 - 1 - write-only - - - CTIMER1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 11 - 1 - write-only - - - SCT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 12 - 1 - write-only - - - CTIMER3_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 13 - 1 - write-only - - - FLEXINT0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 14 - 1 - write-only - - - FLEXINT1_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 15 - 1 - write-only - - - FLEXINT2_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 16 - 1 - write-only - - - FLEXINT3_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 17 - 1 - write-only - - - FLEXINT4_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 18 - 1 - write-only - - - FLEXINT5_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 19 - 1 - write-only - - - FLEXINT6_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 20 - 1 - write-only - - - FLEXINT7_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 21 - 1 - write-only - - - ADC0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 22 - 1 - write-only - - - ADC0_THCMP_OVR_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 24 - 1 - write-only - - - USB0_NEEDCLK_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 27 - 1 - write-only - - - USB0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 28 - 1 - write-only - - - RTC_LITE0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 29 - 1 - write-only - - - EZH_ARCH_B0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 30 - 1 - write-only - - - WAKEUP_MAILBOX0_CLR - Writing ones to this register clears the corresponding bit in the STARTER0 register. - 31 - 1 - write-only - - - - - STARTERCLR1 - Clear bits in STARTER - 0x6C4 - 32 - write-only - 0 - 0x8FFF847F - - - GPIO_INT04_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 0 - 1 - write-only - - - GPIO_INT05_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 1 - 1 - write-only - - - GPIO_INT06_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 2 - 1 - write-only - - - GPIO_INT07_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 3 - 1 - write-only - - - CTIMER2_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 4 - 1 - write-only - - - CTIMER4_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 5 - 1 - write-only - - - OS_EVENT_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 6 - 1 - write-only - - - SDIO_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 10 - 1 - write-only - - - USB1_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 15 - 1 - write-only - - - USB1_NEEDCLK_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 16 - 1 - write-only - - - SEC_HYPERVISOR_CALL_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 17 - 1 - write-only - - - SEC_GPIO_INT00_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 18 - 1 - write-only - - - SEC_GPIO_INT01_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 19 - 1 - write-only - - - PLU_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 20 - 1 - write-only - - - SEC_VIO_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 21 - 1 - write-only - - - SHA_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 22 - 1 - write-only - - - CASER_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 23 - 1 - write-only - - - QDDKEY_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 24 - 1 - write-only - - - PQ_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 25 - 1 - write-only - - - SDMA1_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 26 - 1 - write-only - - - LSPI_HS_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 27 - 1 - write-only - - - WAKEUPPADS_CLR - Writing ones to this register clears the corresponding bit in the STARTER1 register. - 31 - 1 - write-only - - - - - HARDWARESLEEP - Hardware Sleep control - 0x780 - 32 - read-write - 0 - 0x2B - - - FORCED - Force peripheral clocking to stay on during Deep Sleep and Power-down modes. - 0 - 1 - read-write - - - PERIPHERALS - Wake for Flexcomms. - 1 - 1 - read-write - - - SDMA0 - Wake for DMA0. - 3 - 1 - read-write - - - SDMA1 - Wake for DMA1. - 5 - 1 + 10 read-write @@ -16275,24 +14513,6 @@ SPDX-License-Identifier: BSD-3-Clause - - CPSTACK - Coprocessor Stack Address - 0x808 - 32 - read-write - 0 - 0xFFFFFFFF - - - CPSTACK - Coprocessor Stack Address. -- NOT USED - 0 - 32 - read-write - - - CPSTAT CPU Status @@ -16380,150 +14600,6 @@ SPDX-License-Identifier: BSD-3-Clause - - DICE_REG0 - Composite Device Identifier - 0x900 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG0 - no description available - 0 - 32 - read-write - - - - - DICE_REG1 - Composite Device Identifier - 0x904 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG1 - no description available - 0 - 32 - read-write - - - - - DICE_REG2 - Composite Device Identifier - 0x908 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG2 - no description available - 0 - 32 - read-write - - - - - DICE_REG3 - Composite Device Identifier - 0x90C - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG3 - no description available - 0 - 32 - read-write - - - - - DICE_REG4 - Composite Device Identifier - 0x910 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG4 - no description available - 0 - 32 - read-write - - - - - DICE_REG5 - Composite Device Identifier - 0x914 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG5 - no description available - 0 - 32 - read-write - - - - - DICE_REG6 - Composite Device Identifier - 0x918 - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG6 - no description available - 0 - 32 - read-write - - - - - DICE_REG7 - Composite Device Identifier - 0x91C - 32 - read-write - 0 - 0xFFFFFFFF - - - DICE_REG7 - no description available - 0 - 32 - read-write - - - CLOCK_CTRL Various system clock controls : Flash clock (48 MHz) control, clocks to Frequency Measures @@ -16531,27 +14607,8 @@ SPDX-License-Identifier: BSD-3-Clause 32 read-write 0x1 - 0x7F + 0x3FF - - FLASH48MHZ_ENA - Enable Flash 48 MHz clock. - 0 - 1 - read-write - - - DISABLE - The clock is not enabled. - 0 - - - ENABLE - The clock is enabled. - 0x1 - - - XTAL32MHZ_FREQM_ENA Enable XTAL32MHz clock for Frequency Measure module. @@ -17090,44 +15147,6 @@ SPDX-License-Identifier: BSD-3-Clause - - FLASH - Control automatic clock gating of FLASH controller. - 9 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - - - FMC - Control automatic clock gating of FMC controller. - 10 - 1 - read-write - - - DISABLE - Automatic clock gating is not overridden. - 0 - - - ENABLE - Automatic clock gating is overridden (Clock gating is disabled). - 0x1 - - - CRCGEN Control automatic clock gating of CRCGEN controller. @@ -17186,7 +15205,7 @@ SPDX-License-Identifier: BSD-3-Clause - USB + USB0 Control automatic clock gating of USB controller. 14 1 @@ -17232,12 +15251,12 @@ SPDX-License-Identifier: BSD-3-Clause DISABLE - Automatic clock gating is not overridden. + Bit Fields 0 - 15 of this register are not updated 0 ENABLE - Automatic clock gating is overridden (Clock gating is disabled). + Bit Fields 0 - 15 of this register are updated 0xC0DE @@ -17276,7 +15295,7 @@ SPDX-License-Identifier: BSD-3-Clause DEBUG_LOCK_EN - Control write access to security registers -- FOR INTERNAl USE ONLY + Control write access to security registers. 0xFA0 32 read-write @@ -17285,7 +15304,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_ALL - Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CM33_DEBUG_FEATURES, MCM33_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. + Control write access to CODESECURITYPROTTEST, CODESECURITYPROTCPU0, CODESECURITYPROTCPU1, CPU0_DEBUG_FEATURES, CPU1_DEBUG_FEATURES and DBG_AUTH_SCRATCH registers. 0 4 read-write @@ -17306,7 +15325,7 @@ SPDX-License-Identifier: BSD-3-Clause DEBUG_FEATURES - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control -- FOR INTERNAl USE ONLY + Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control. 0xFA4 32 read-write @@ -17314,8 +15333,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFF - CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + CPU0_DBGEN + CPU0 Invasive debug control:. 0 2 read-write @@ -17333,8 +15352,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. + CPU0_NIDEN + CPU0 Non Invasive debug control:. 2 2 read-write @@ -17352,8 +15371,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. + CPU0_SPIDEN + CPU0 Secure Invasive debug control:. 4 2 read-write @@ -17371,8 +15390,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. + CPU0_SPNIDEN + CPU0 Secure Non Invasive debug control:. 6 2 read-write @@ -17390,8 +15409,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. + CPU1_DBGEN + CPU1 Invasive debug control:. 8 2 read-write @@ -17409,8 +15428,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. + CPU1_NIDEN + CPU1 Non Invasive debug control:. 10 2 read-write @@ -17431,7 +15450,7 @@ SPDX-License-Identifier: BSD-3-Clause DEBUG_FEATURES_DP - Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register -- FOR INTERNAl USE ONLY + Cortex M33 (CPU0) and micro Cortex M33 (CPU1) debug features control DUPLICATE register. 0xFA8 32 read-write @@ -17439,8 +15458,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFF - CM33_DBGEN - CM33 (CPU0) Invasive debug control:. + CPU0_DBGEN + CPU0 (CPU0) Invasive debug control:. 0 2 read-write @@ -17458,8 +15477,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_NIDEN - CM33 (CPU0) Non Invasive debug control:. + CPU0_NIDEN + CPU0 Non Invasive debug control:. 2 2 read-write @@ -17477,8 +15496,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_SPIDEN - CM33 (CPU0) Secure Invasive debug control:. + CPU0_SPIDEN + CPU0 Secure Invasive debug control:. 4 2 read-write @@ -17496,8 +15515,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_SPNIDEN - CM33 (CPU0) Secure Non Invasive debug control:. + CPU0_SPNIDEN + CPU0 Secure Non Invasive debug control:. 6 2 read-write @@ -17515,8 +15534,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_DBGEN - Micro-CM33 (CPU1) Invasive debug control:. + CPU1_DBGEN + CPU1 Invasive debug control:. 8 2 read-write @@ -17534,8 +15553,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_NIDEN - Micro-CM33 (CPU1) Non Invasive debug control:. + CPU1_NIDEN + CPU1 Non Invasive debug control:. 10 2 read-write @@ -17554,99 +15573,9 @@ SPDX-License-Identifier: BSD-3-Clause - - CODESECURITYPROTTEST - Security code to allow test (Design for Testability) access -- FOR INTERNAl USE ONLY - 0xFB0 - 32 - write-only - 0 - 0xFFFFFFFF - - - SEC_CODE - Security code to allow test access : 0x12345678. - 0 - 32 - write-only - - - DISABLE - test access is not allowed. - 0 - - - ENABLE - Security code to allow test access. - 0x12345678 - - - - - - - CODESECURITYPROTCPU0 - Security code to allow CPU0 (CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY - 0xFB4 - 32 - write-only - 0 - 0xFFFFFFFF - - - SEC_CODE - Security code to allow CPU0 DAP: 0x12345678. - 0 - 32 - write-only - - - DISABLE - CPU0 DAP is not allowed. - 0 - - - ENABLE - Security code to allow CPU0 DAP. - 0x12345678 - - - - - - - CODESECURITYPROTCPU1 - Security code to allow CPU1 (Micro CM33) Debug Access Port (DAP) -- FOR INTERNAl USE ONLY - 0xFB8 - 32 - write-only - 0 - 0xFFFFFFFF - - - SEC_CODE - Security code to allow CPU1 DAP: 0x12345678. - 0 - 32 - write-only - - - DISABLE - CPU1 DAP is not allowed. - 0 - - - ENABLE - Security code to allow CPU1 DAP. - 0x12345678 - - - - - KEY_BLOCK - block quiddikey/PUF all index. -- FOR INTERNAL USE ONLY + block quiddikey/PUF all index. 0xFBC 32 write-only @@ -17663,8 +15592,8 @@ SPDX-License-Identifier: BSD-3-Clause - DEBUG_AUTH_SCRATCH - Debug authentication scratch registers -- FOR INTERNAL USE ONLY + DEBUG_AUTH_BEACON + Debug authentication BEACON register 0xFC0 32 read-write @@ -17672,7 +15601,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - SCRATCH + BEACON Set by the debug authentication code in ROM to pass the debug beacons (Credential Beacon and Authentication Beacon) to application code. 0 32 @@ -17710,169 +15639,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PERIPHENCFG - peripheral enable configuration -- FOR INTERNAL USE ONLY - 0xFEC - 32 - read-write - 0x5C47 - 0x5C47 - - - SCTEN - SCT enable. - 0 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - ADCEN - ADC enable. - 1 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - USB0EN - USB0 enable. - 2 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - PUFFEN - Puff enable. - 6 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - USB1EN - USB1 enable. - 10 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - SDIOEN - SDIO enable. - 11 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - HASHEN - HASH enable. - 12 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - PRINCEEN - PRINCE enable. - 14 - 1 - read-write - - - DISABLE - peripheral is disable. - 0 - - - ENABLE - peripheral is enable. - 0x1 - - - - - DEVICE_ID0 Device ID @@ -17882,41 +15648,13 @@ SPDX-License-Identifier: BSD-3-Clause 0 0xFFFFFFFF - - PARTCONFIG - no description available - 0 - 8 - read-only - - - SRAM_SIZE - no description available - 8 - 4 - read-only - - - FLASH_SIZE - no description available - 12 - 3 - read-only - ROM_REV_MINOR - no description available + ROM revision. 20 4 read-only - - MODELNUM_EXTENTION - no description available - 24 - 3 - read-only - @@ -17937,7 +15675,7 @@ SPDX-License-Identifier: BSD-3-Clause MCO_NUM_IN_DIE_ID - Chip Number. + Chip Number 0x426B. 4 20 read-only @@ -18053,12 +15791,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18091,12 +15829,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -18122,19 +15860,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -18237,12 +15975,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18275,12 +16013,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -18402,12 +16140,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18440,12 +16178,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -18567,12 +16305,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18605,12 +16343,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -18732,12 +16470,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18770,12 +16508,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -18897,12 +16635,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -18935,12 +16673,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19062,12 +16800,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19100,12 +16838,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19227,12 +16965,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19265,12 +17003,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19392,12 +17130,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19430,12 +17168,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19557,12 +17295,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19595,12 +17333,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19626,19 +17364,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -19741,12 +17479,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19779,12 +17517,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19810,19 +17548,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -19925,12 +17663,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -19963,12 +17701,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -19994,19 +17732,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -20109,12 +17847,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -20147,12 +17885,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -20178,19 +17916,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -20293,12 +18031,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -20331,19 +18069,19 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 OD - Controls open-drain mode. + Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). 9 1 read-write @@ -20388,26 +18126,26 @@ SPDX-License-Identifier: BSD-3-Clause ENABLED - Filter enabled. Noise pulses below approximately 10 ns are filtered out. + Filter enabled. 0 DISABLED - Filter disabled. No input filtering is done. + Filter disabled. 0x1 ECS - Pull-up current source enable in IIC mode. + Pull-up current source enable in I2C mode. 13 1 read-write DISABLED - Disabled. IO is in open drain. + Disabled. IO is in open drain cell. 0 @@ -20419,7 +18157,7 @@ SPDX-License-Identifier: BSD-3-Clause EGP - Controls slew rate of I2C pad. + Switch between GPIO mode and I2C mode. 14 1 read-write @@ -20438,19 +18176,19 @@ SPDX-License-Identifier: BSD-3-Clause I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. + Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. 15 1 read-write FAST_MODE - I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. + I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. 0 STANDARD_MODE - I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. + I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. 0x1 @@ -20553,12 +18291,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -20591,19 +18329,19 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 OD - Controls open-drain mode. + Controls open-drain mode in standard GPIO mode (EGP = 1). This bit has no effect in I2C mode (EGP=0). 9 1 read-write @@ -20648,26 +18386,26 @@ SPDX-License-Identifier: BSD-3-Clause ENABLED - Filter enabled. Noise pulses below approximately 10 ns are filtered out. + Filter enabled. 0 DISABLED - Filter disabled. No input filtering is done. + Filter disabled. 0x1 ECS - Pull-up current source enable in IIC mode. + Pull-up current source enable in I2C mode. 13 1 read-write DISABLED - Disabled. IO is in open drain. + Disabled. IO is in open drain cell. 0 @@ -20679,7 +18417,7 @@ SPDX-License-Identifier: BSD-3-Clause EGP - Controls slew rate of I2C pad. + Switch between GPIO mode and I2C mode. 14 1 read-write @@ -20698,19 +18436,19 @@ SPDX-License-Identifier: BSD-3-Clause I2CFILTER - Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation. + Configures I2C features for standard mode, fast mode, and Fast Mode Plus operation and High-Speed mode operation. 15 1 read-write FAST_MODE - I2C 50 ns glitch filter enabled. Typically used for Fast-mode and Fast-mode Plus I2C. + I2C 50 ns glitch filter enabled. Typically used for Standard-mode, Fast-mode and Fast-mode Plus I2C. 0 STANDARD_MODE - I2C 10 ns glitch filter enabled. Typically used for Standard-mode I2C. + I2C 10 ns glitch filter enabled. Typically used for High-speed mode I2C. 0x1 @@ -20813,12 +18551,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -20851,12 +18589,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -20882,19 +18620,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -20997,12 +18735,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21035,12 +18773,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -21066,19 +18804,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -21181,12 +18919,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21219,12 +18957,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -21346,12 +19084,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21384,12 +19122,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -21415,19 +19153,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -21530,12 +19268,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21568,12 +19306,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -21695,12 +19433,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21733,12 +19471,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -21860,12 +19598,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -21898,12 +19636,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22025,12 +19763,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22063,12 +19801,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22190,12 +19928,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22228,12 +19966,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22259,19 +19997,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -22374,12 +20112,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22412,12 +20150,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22539,12 +20277,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22577,12 +20315,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22704,12 +20442,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22742,12 +20480,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -22869,12 +20607,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -22907,12 +20645,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23034,12 +20772,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23072,12 +20810,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23199,12 +20937,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23237,12 +20975,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23364,12 +21102,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23402,12 +21140,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23529,12 +21267,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23567,12 +21305,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23598,19 +21336,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -23713,12 +21451,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23751,12 +21489,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -23782,19 +21520,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -23897,12 +21635,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -23935,12 +21673,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24062,12 +21800,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24100,12 +21838,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24227,12 +21965,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24265,12 +22003,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24392,12 +22130,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24430,12 +22168,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24557,12 +22295,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24595,12 +22333,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24722,12 +22460,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24760,12 +22498,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -24887,12 +22625,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -24925,12 +22663,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25052,12 +22790,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25090,12 +22828,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25121,19 +22859,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -25236,12 +22974,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25274,12 +23012,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25305,19 +23043,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -25420,12 +23158,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25458,12 +23196,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25585,12 +23323,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25623,12 +23361,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25750,12 +23488,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25788,12 +23526,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -25915,12 +23653,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -25953,12 +23691,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26080,12 +23818,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26118,12 +23856,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26149,19 +23887,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -26264,12 +24002,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26302,12 +24040,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26429,12 +24167,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26467,12 +24205,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26594,12 +24332,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26632,12 +24370,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26759,12 +24497,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26797,12 +24535,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26924,12 +24662,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -26962,12 +24700,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -26993,19 +24731,19 @@ SPDX-License-Identifier: BSD-3-Clause ASW - Analog switch input control. Usable only if DIGIMODE = 0b0 + Analog switch input control. 10 1 read-write - DISABLE - Analog switch is open. + VALUE0 + For pins PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9, analog switch is closed (enabled). For the other pins, analog switch is open (disabled). 0 - ENABLE - Analog switch is closed. + VALUE1 + For all pins except PIO0_9, PIO0_11, PIO0_12, PIO0_15, PIO0_18, PIO0_31, PIO1_0 and PIO1_9 analog switch is closed (enabled) 0x1 @@ -27108,12 +24846,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27146,12 +24884,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -27273,12 +25011,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27311,12 +25049,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -27438,12 +25176,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27476,12 +25214,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -27603,12 +25341,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27641,12 +25379,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -27768,12 +25506,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27806,12 +25544,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -27933,12 +25671,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -27971,12 +25709,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28098,12 +25836,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28136,12 +25874,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28263,12 +26001,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28301,12 +26039,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28428,12 +26166,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28466,12 +26204,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28593,12 +26331,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28631,12 +26369,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28758,12 +26496,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28796,12 +26534,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -28923,12 +26661,12 @@ SPDX-License-Identifier: BSD-3-Clause STANDARD - Standard mode, output slew rate control is enabled. More outputs can be switched simultaneously. + Standard-mode, output slew rate is slower. More outputs can be switched simultaneously. 0 FAST - Fast mode, slew rate control is disabled. Refer to the appropriate specific device data sheet for details. + Fast-mode, output slew rate is faster. Refer to the appropriate specific device data sheet for details. 0x1 @@ -28961,12 +26699,12 @@ SPDX-License-Identifier: BSD-3-Clause ANALOG - Analog mode, digital input is disabled. + Disable digital mode. Digital input set to 0. 0 DIGITAL - Digital mode, digital input is enabled. + Enable Digital mode. Digital input is enabled. 0x1 @@ -30366,6 +28104,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x34 registers + + SEC_HYPERVISOR_CALL + 49 + SEC_GPIO_INT0_IRQ0 50 @@ -30374,6 +28116,10 @@ SPDX-License-Identifier: BSD-3-Clause SEC_GPIO_INT0_IRQ1 51 + + SEC_VIO + 53 + INPUTMUX @@ -30673,17 +28419,17 @@ SPDX-License-Identifier: BSD-3-Clause val17 - CT_INP17 function selected from IOCON register + None 0x11 val18 - CT_INP18 function selected from IOCON register + None 0x12 val19 - CT_INP19 function selected from IOCON register + None 0x13 @@ -30855,17 +28601,17 @@ SPDX-License-Identifier: BSD-3-Clause val17 - CT_INP17 function selected from IOCON register + None 0x11 val18 - CT_INP18 function selected from IOCON register + None 0x12 val19 - CT_INP19 function selected from IOCON register + None 0x13 @@ -31037,17 +28783,17 @@ SPDX-License-Identifier: BSD-3-Clause val17 - CT_INP17 function selected from IOCON register + None 0x11 val18 - CT_INP18 function selected from IOCON register + None 0x12 val19 - CT_INP19 function selected from IOCON register + None 0x13 @@ -31347,10 +29093,52 @@ SPDX-License-Identifier: BSD-3-Clause CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 + Clock source number (decimal value) for frequency measure function reference clock: 0 5 read-write + + + VALUE0 + External main crystal oscilator (Clock_in). + 0 + + + VALUE1 + FRO 12MHz clock. + 0x1 + + + VALUE2 + FRO 96MHz clock. + 0x2 + + + VALUE3 + Watchdog oscillator / FRO1MHz clock. + 0x3 + + + VALUE4 + 32 kHz oscillator (32k_clk) clock. + 0x4 + + + VALUE5 + main clock (main_clock). + 0x5 + + + VALUE6 + FREQME_GPIO_CLK_A. + 0x6 + + + VALUE7 + FREQME_GPIO_CLK_B. + 0x7 + + @@ -31365,10 +29153,52 @@ SPDX-License-Identifier: BSD-3-Clause CLKIN - Clock source number (decimal value) for frequency measure function target clock: 0 = CLK_IN 1 = FRO 12 MHz oscillator 2 = Watchdog oscillator 3 = 32 kHz RTC oscillator 4 = Main clock (see Section 4.5.23) 5 = PIO0_4 6 = PIO0_20 7 = PIO0_24 8 = PIO1_4 + Clock source number (decimal value) for frequency measure function target clock: 0 5 read-write + + + VALUE0 + External main crystal oscilator (Clock_in). + 0 + + + VALUE1 + FRO 12MHz clock. + 0x1 + + + VALUE2 + FRO 96MHz clock. + 0x2 + + + VALUE3 + Watchdog oscillator / FRO1MHz clock. + 0x3 + + + VALUE4 + 32 kHz oscillator (32k_clk) clock. + 0x4 + + + VALUE5 + main clock (main_clock). + 0x5 + + + VALUE6 + FREQME_GPIO_CLK_A. + 0x6 + + + VALUE7 + FREQME_GPIO_CLK_B. + 0x7 + + @@ -32909,7 +30739,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - SHADOWW + SHADOW Timer counter match shadow value. 0 32 @@ -33689,7 +31519,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x40013000 0 - 0x10C + 0x108 registers @@ -33732,20 +31562,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x50000000 0xF0003FFF - - PMU_ID - Power Management Unit (PMU) Analog macro-bloc identification number : . - 0 - 6 - read-only - - - OSC_ID - Oscillators Analog macro-bloc identification number : . - 6 - 6 - read-only - FLASH_PWRDWN Flash Power Down status. @@ -33784,13 +31600,6 @@ SPDX-License-Identifier: BSD-3-Clause - - FINAL_TEST_DONE_VECT - Indicates current status of Final Test. - 28 - 4 - read-only - @@ -33827,20 +31636,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x80D01A 0xF3FFFFBF - - BIAS_TRIM - Bias trimming bits (course frequency trimming). - 0 - 6 - read-write - - - TEMP_TRIM - Temperature coefficient trimming bits. - 7 - 7 - read-write - ENA_12MHZCLK 12 MHz clock control. @@ -33867,11 +31662,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - DISABLE - 48 MHz clock is disabled. - 0 - ENABLE 48 MHz clock is enabled. @@ -33881,7 +31671,7 @@ SPDX-License-Identifier: BSD-3-Clause DAC_TRIM - Curdac trimming bits (fine frequency trimming) This trim is used to adjust the frequency, given that the bias and temperature trim are set. + Frequency trim. 16 8 read-write @@ -33895,18 +31685,11 @@ SPDX-License-Identifier: BSD-3-Clause USBMODCHG - If this reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be reread until it is 0. + If it reads as 1 when reading the DAC_TRIM field and USBCLKADJ=1, it should be re-read until it is 0. 25 1 read-only - - ATB_CTRL - Analog Test Bus control. - 28 - 2 - read-write - ENA_96MHZCLK 96 MHz clock control. @@ -34004,20 +31787,13 @@ SPDX-License-Identifier: BSD-3-Clause XO32M_CTRL - 32 MHz Crystal Oscillator Control register + High speed Crystal Oscillator Control register 0x20 32 read-write 0x21428A 0x1FFFFFFE - - GM - Gm value for Xo. - 1 - 3 - read-write - SLAVE Xo in slave mode. @@ -34025,23 +31801,16 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - AMP - Amplitude selection , Min amp : 001, Max amp : 110. - 5 - 3 - read-write - OSC_CAP_IN - Tune capa banks of Crystal 32-MHz input pin + Tune capa banks of High speed Crystal Oscillator input pin 8 7 read-write OSC_CAP_OUT - Tune capa banks of Crystal 32-MHz output pin + Tune capa banks of High speed Crystal Oscillator output pin 15 7 read-write @@ -34067,102 +31836,38 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_PLL_USB_OUT - Enable XO 32 MHz output to USB HS PLL. + Enable High speed Crystal oscillator output to USB HS PLL. 23 1 read-write DISABLE - XO 32 MHz output to USB HS PLL is disabled. + High speed Crystal oscillator output to USB HS PLL is disabled. 0 ENABLE - XO 32 MHz output to USB HS PLL is enabled. + High speed Crystal oscillator output to USB HS PLL is enabled. 0x1 ENABLE_SYSTEM_CLK_OUT - Enable XO 32 MHz output to CPU system. + Enable High speed Crystal oscillator output to CPU system. 24 1 read-write DISABLE - XO 32 MHz output to CPU system is disabled. + High speed Crystal oscillator output to CPU system is disabled. 0 ENABLE - XO 32 MHz output to CPU system is enabled. - 0x1 - - - - - CAPTESTSTARTSRCSEL - Source selection for 'xo32k_captest_start' signal. - 25 - 1 - read-write - - - CAPTEST - Sourced from CAPTESTSTART. - 0 - - - CALIB - Sourced from calibration. - 0x1 - - - - - CAPTESTSTART - 1: Start CapTest. - 26 - 1 - read-write - - - CAPTESTENABLE - Enable signal for captest. - 27 - 1 - read-write - - - DISABLE - Captest is disabled. - 0 - - - ENABLE - Captest is enabled. - 0x1 - - - - - CAPTESTOSCINSEL - Select the input for test. - 28 - 1 - read-write - - - OSCOUT - osc_out (oscillator output) pin. - 0 - - - OSCIN - osc_in (oscillator) pin. + High speed Crystal oscillator output to CPU system is enabled. 0x1 @@ -34171,7 +31876,7 @@ SPDX-License-Identifier: BSD-3-Clause XO32M_STATUS - 32 MHz Crystal Oscillator Status register + High speed Crystal Oscillator Status register 0x24 32 read-only @@ -35238,124 +32943,74 @@ SPDX-License-Identifier: BSD-3-Clause - XO_CAL_CFG - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Configuration register - 0xC0 + AUX_BIAS + AUX_BIAS + 0xB4 32 read-write - 0 - 0x3F + 0x703A0 + 0x3FFFFE - START_INV - Polarity of the externally applied START signal - 0 - 1 - read-write - - - START_OVR - Override of the START signal. + VREF1VENABLE + Control output of 1V reference voltage. 1 1 read-write - - - START - Override value of the START signal. - 2 - 1 - read-write - - - STOP_INV - Polarity of the STOP signal. - 3 - 1 - read-write - - - STOP_CNTR_END - Generate the external DONE signal when the counter reaches its end. - 4 - 1 - read-write - - - XO32K_MODE - When 0 : High speed crystal oscillator calibration is used. When 1 : 32 kHz crystal oscillator calibration is used. - 5 - 1 - read-write - XO32MHZ - High speed crystal oscillator (12 MHz- 32 MHz) is used + DISABLE + Output of 1V reference voltage buffer is bypassed. 0 - XO32KHZ - 32 kHz crystal oscillator calibration is used. + ENABLE + Output of 1V reference voltage is enabled. 0x1 - - - - XO_CAL_CMD - All Crystal Oscillators (both the 32 KHz and the High Speed) Capacitive Banks Calibration Command register. - 0xC4 - 32 - read-write - 0 - 0x7 - - START - START signal for testing the state machine. - 0 - 1 - read-write - - - STOP - STOP signal for testing the state machine. - 1 - 1 - read-write - - - OVR - Override instructing the state machine to use the START/STOP signals from this register. + ITRIM + current trimming control word. 2 + 5 + read-write + + + PTATITRIM + current trimming control word for ptat current. + 7 + 5 + read-write + + + VREF1VTRIM + voltage trimming control word. + 12 + 5 + read-write + + + VREF1VCURVETRIM + Control bit to configure trimming state of mirror. + 17 + 3 + read-write + + + ITRIMCTRL0 + Control bit to configure trimming state of mirror. + 20 1 read-write - - - - XO_CAL_STATUS - All Crystal Oscillators (both the 32 KHz and the High speed) Capacitive Banks Calibration Status register. - 0xC8 - 32 - read-only - 0 - 0x1FFFF - - CAL_CNTR - Value of the calibration counter (result of the calibration operation). - 0 - 16 - read-only - - - DONE - Status of the calibration run. 1: Calibration is completed. - 16 + ITRIMCTRL1 + Control bit to configure trimming state of mirror. + 21 1 - read-only + read-write @@ -35382,13 +33037,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - iso_atx - . - 3 - 1 - read-write - @@ -35451,66 +33099,6 @@ SPDX-License-Identifier: BSD-3-Clause - - USBHS_PHY_STATUS - USB High Speed Phy Status - 0x108 - 32 - read-only - 0 - 0x7F - - - pfd_stable - pfd output is stable. - 0 - 1 - read-only - - - vbusvalid_3vdetect_1p8v - Can be left disconnected if not using High volt interrupts. - 1 - 1 - read-only - - - sess_vld_1p8v - Same as utmi_sessend. - 2 - 1 - read-only - - - usb2_rx_vpin_fs_1p8v - Full speed single ended receiver for 1. - 3 - 1 - read-only - - - usb2_rx_vmin_fs_1p8v - Full speed single ended receiver for 1. - 4 - 1 - read-only - - - usb2_plugged_in_1p8v - this is a proprietary mode described in the reference manual. - 5 - 1 - read-only - - - usb2_iddig_1p8v - ID value in the 1. - 6 - 1 - read-only - - - @@ -35520,10 +33108,54 @@ SPDX-License-Identifier: BSD-3-Clause 0x40020000 0 - 0xCC + 0xD8 registers + + ACMP + 24 + + + STATUS + Power Management Controller FSM (Finite State Machines) status + 0x4 + 32 + read-only + 0 + 0xF00FFFFF + + + BOOTMODE + Latest IC Boot cause:. + 18 + 2 + read-only + + + POWERUP + Latest IC boot was a Full power cycle boot sequence (PoR, Pin Reset, Brown Out Detectors Reset, Software Reset). + 0 + + + DEEPSLEEP + Latest IC boot was from DEEP SLEEP low power mode. + 0x1 + + + POWERDOWN + Latest IC boot was from POWER DOWN low power mode. + 0x2 + + + DEEPPOWERDOWN + Latest IC boot was from DEEP POWER DOWN low power mode. + 0x3 + + + + + RESETCTRL Reset Control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] @@ -35612,78 +33244,482 @@ SPDX-License-Identifier: BSD-3-Clause - RESETCAUSE - Reset Cause register [Reset by: PoR] - 0xC + DCDC0 + DCDC (first) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x10 32 read-write - 0x1 - 0x1FF + 0x10C4E68 + 0x7FFFFFF - POR - 1 : The last chip reset was caused by a Power On Reset. Write '1' to clear this bit. + RC + Constant On-Time calibration. 0 - 1 - read-write - oneToClear - - - PADRESET - 1 : The last chip reset was caused by a Pin Reset. Write '1' to clear this bit. - 1 - 1 + 6 read-write - BODRESET - 1 : The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. Write '1' to clear this bit. - 2 - 1 - read-write - - - SYSTEMRESET - 1 : The last chip reset was caused by a System Reset requested by the ARM CPU. Write '1' to clear this bit. - 3 - 1 - read-write - - - WDTRESET - 1 : The last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit. - 4 - 1 - read-write - - - SWRRESET - 1 : The last chip reset was caused by a Software. Write '1' to clear this bit. - 5 - 1 - read-write - - - DPDRESET_WAKEUPIO - 1 : The last chip reset was caused by a Wake-up I/O reset event during DEEP POWER DOWN mode. Write '1' to clear this bit. + ICOMP + Select the type of ZCD comparator. 6 + 2 + read-write + + + ISEL + Alter Internal biasing currents. + 8 + 2 + read-write + + + ICENABLE + Selection of auto scaling of COT period with variations in VDD. + 10 1 read-write - DPDRESET_RTC - 1 : The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during DEEP POWER DOWN mode. Write '1' to clear this bit. - 7 + TMOS + One-shot generator reference current trimming signal. + 11 + 5 + read-write + + + DISABLEISENSE + Disable Current sensing. + 16 1 read-write - DPDRESET_OSTIMER - 1 : The last chip reset was caused by a OS Event Timer reset eventduring DEEP POWER DOWN mode. Write '1' to clear this bit. + VOUT + Set output regulation voltage. + 17 + 4 + read-write + + + V_DCDC_0P950 + 0.95 V. + 0 + + + V_DCDC_0P975 + 0.975 V. + 0x1 + + + V_DCDC_1P000 + 1 V. + 0x2 + + + V_DCDC_1P025 + 1.025 V. + 0x3 + + + V_DCDC_1P050 + 1.05 V. + 0x4 + + + V_DCDC_1P075 + 1.075 V. + 0x5 + + + V_DCDC_1P100 + 1.1 V. + 0x6 + + + V_DCDC_1P125 + 1.125 V. + 0x7 + + + V_DCDC_1P150 + 1.15 V. + 0x8 + + + V_DCDC_1P175 + 1.175 V. + 0x9 + + + V_DCDC_1P200 + 1.2 V. + 0xA + + + + + SLICINGENABLE + Enable staggered switching of power switches. + 21 + 1 + read-write + + + INDUCTORCLAMPENABLE + Enable shorting of Inductor during PFM idle time. + 22 + 1 + read-write + + + VOUT_PWD + Set output regulation voltage during Deep Sleep. + 23 + 4 + read-write + + + + + DCDC1 + DCDC (second) control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x14 + 32 + read-write + 0x1803A98 + 0xFFFFFFFF + + + RTRIMOFFET + Adjust the offset voltage of BJT based comparator. + 0 + 4 + read-write + + + RSENSETRIM + Adjust Max inductor peak current limiting. + 4 + 4 + read-write + + + DTESTENABLE + Enable Digital test signals. 8 1 read-write + + SETCURVE + Bandgap calibration parameter. + 9 + 2 + read-write + + + SETDC + Bandgap calibration parameter. + 11 + 4 + read-write + + + DTESTSEL + Select the output signal for test. + 15 + 3 + read-write + + + ISCALEENABLE + Modify COT behavior. + 18 + 1 + read-write + + + FORCEBYPASS + Force bypass mode. + 19 + 1 + read-write + + + TRIMAUTOCOT + Change the scaling ratio of the feedforward compensation. + 20 + 4 + read-write + + + FORCEFULLCYCLE + Force full PFM PMOS and NMOS cycle. + 24 + 1 + read-write + + + LCENABLE + Change the range of the peak detector of current inside the inductor. + 25 + 1 + read-write + + + TOFF + Constant Off-Time calibration input. + 26 + 5 + read-write + + + TOFFENABLE + Enable Constant Off-Time feature. + 31 + 1 + read-write + + + + + LDOPMU + Power Management Unit (PMU) and Always-On domains LDO control [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x1C + 32 + read-write + 0x10EF718 + 0x31FFFFF + + + VADJ + Sets the Always-On domain LDO output level. + 0 + 5 + read-write + + + V_1P220 + 1.22 V. + 0 + + + V_0P700 + 0.7 V. + 0x1 + + + V_0P725 + 0.725 V. + 0x2 + + + V_0P750 + 0.75 V. + 0x3 + + + V_0P775 + 0.775 V. + 0x4 + + + V_0P800 + 0.8 V. + 0x5 + + + V_0P825 + 0.825 V. + 0x6 + + + V_0P850 + 0.85 V. + 0x7 + + + V_0P875 + 0.875 V. + 0x8 + + + V_0P900 + 0.9 V. + 0x9 + + + V_0P960 + 0.96 V. + 0xA + + + V_0P970 + 0.97 V. + 0xB + + + V_0P980 + 0.98 V. + 0xC + + + V_0P990 + 0.99 V. + 0xD + + + V_1P000 + 1 V. + 0xE + + + V_1P010 + 1.01 V. + 0xF + + + V_1P020 + 1.02 V. + 0x10 + + + V_1P030 + 1.03 V. + 0x11 + + + V_1P040 + 1.04 V. + 0x12 + + + V_1P050 + 1.05 V. + 0x13 + + + V_1P060 + 1.06 V. + 0x14 + + + V_1P070 + 1.07 V. + 0x15 + + + V_1P080 + 1.08 V. + 0x16 + + + V_1P090 + 1.09 V. + 0x17 + + + V_1P100 + 1.1 V. + 0x18 + + + V_1P110 + 1.11 V. + 0x19 + + + V_1P120 + 1.12 V. + 0x1A + + + V_1P130 + 1.13 V. + 0x1B + + + V_1P140 + 1.14 V. + 0x1C + + + V_1P150 + 1.15 V. + 0x1D + + + V_1P160 + 1.16 V. + 0x1E + + + V_1P220_1 + 1.22 V. + 0x1F + + + + + VADJ_PWD + Sets the Always-On domain LDO output level in all power down modes. + 5 + 5 + read-write + + + VADJ_BOOST + Sets the Always-On domain LDO Boost output level. + 10 + 5 + read-write + + + VADJ_BOOST_PWD + Sets the Always-On domain LDO Boost output level in all power down modes. + 15 + 5 + read-write + + + BOOST_ENA + Control the LDO AO boost mode in ACTIVE mode. + 24 + 1 + read-write + + + DISABLE + LDO AO Boost Mode is disable. + 0 + + + ENABLE + LDO AO Boost Mode is enable. + 0x1 + + + + + BOOST_ENA_PWD + Control the LDO AO boost mode in the different low power modes (DEEP SLEEP, POWERDOWN, and DEEP POWER DOWN). + 25 + 1 + read-write + + + DISABLE + LDO AO Boost Mode is disable. + 0 + + + ENABLE + LDO AO Boost Mode is enable. + 0x1 + + + @@ -35692,7 +33728,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x30 32 read-write - 0x69 + 0x47 0x7F @@ -35896,324 +33932,51 @@ SPDX-License-Identifier: BSD-3-Clause - BODCORE - Digital Core logic Brown Out Dectector control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x38 + REFFASTWKUP + Analog References fast wake-up Control register [Reset by: PoR] + 0x40 32 read-write - 0x17 - 0x37 + 0x1 + 0x3 - TRIGLVL - BoD trigger level. + LPWKUP + Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP POWER DOWN): . 0 - 3 + 1 read-write - V_0P60 - 0.60 V. + DISABLE + Analog References fast wake-up feature is disabled in case of wake-up from any Low power mode. 0 - V_0P65 - 0.65 V. + ENABLE + Analog References fast wake-up feature is enabled in case of wake-up from any Low power mode. 0x1 - - V_0P70 - 0.70 V. - 0x2 - - - V_0P75 - 0.75 V. - 0x3 - - - V_0P80 - 0.80 V. - 0x4 - - - V_0P85 - 0.85 V. - 0x5 - - - V_0P90 - 0.90 V. - 0x6 - - - V_0P95 - 0.95 V. - 0x7 - - HYST - BoD Core Hysteresis control. - 4 - 2 - read-write - - - HYST_25MV - 25 mV. - 0 - - - HYST_50MV - 50 mV. - 0x1 - - - HYST_75MV - 75 mV. - 0x2 - - - HYST_100MV - 100 mV. - 0x3 - - - - - - - FRO1M - 1 MHz Free Running Oscillator control register [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] - 0x44 - 32 - read-write - 0x50 - 0x3FFF - - - FREQSEL - Frequency trimming bits. - 0 - 7 - read-write - - - ATBCTRL - Debug control bits to set the analog/digital test modes. - 7 - 2 - read-write - - - DIVSEL - Divider selection bits. - 9 - 5 - read-write - - - DIV_2 - 2.0. - 0 - - - DIV_4 - 4.0. - 0x1 - - - DIV_6 - 6.0. - 0x2 - - - DIV_8 - 8.0. - 0x3 - - - DIV_10 - 10.0. - 0x4 - - - DIV_12 - 12.0. - 0x5 - - - DIV_14 - 14.0. - 0x6 - - - DIV_16 - 16.0. - 0x7 - - - DIV_18 - 18.0. - 0x8 - - - DIV_20 - 20.0. - 0x9 - - - DIV_22 - 22.0. - 0xA - - - DIV_24 - 24.0. - 0xB - - - DIV_26 - 26.0. - 0xC - - - DIV_28 - 28.0. - 0xD - - - DIV_30 - 30.0. - 0xE - - - DIV_32 - 32.0. - 0xF - - - DIV_34 - 34.0. - 0x10 - - - DIV_36 - 36.0. - 0x11 - - - DIV_38 - 38.0. - 0x12 - - - DIV_40 - 40.0. - 0x13 - - - DIV_42 - 42.0. - 0x14 - - - DIV_44 - 44.0. - 0x15 - - - DIV_46 - 46.0. - 0x16 - - - DIV_48 - 48.0. - 0x17 - - - DIV_50 - 50.0. - 0x18 - - - DIV_52 - 52.0. - 0x19 - - - DIV_54 - 54.0. - 0x1A - - - DIV_56 - 56.0. - 0x1B - - - DIV_58 - 58.0. - 0x1C - - - DIV_60 - 60.0. - 0x1D - - - DIV_62 - 62.0. - 0x1E - - - DIV_1 - 1.0. - 0x1F - - - - - - - FRO32K - 32 KHz Free Running Oscillator (FRO) control register [Reset by: PoR, Brown Out Detectors Reset] - 0x48 - 32 - read-write - 0x90B6 - 0x3FFFE - - - NTAT - Temperature coefficient trimming bits. + HWWKUP + Analog References fast wake-up in case of Hardware Pin reset: . 1 - 3 - read-write - - - PTAT - Bias trimming bits (course frequency trimming). - 4 - 3 - read-write - - - CAPCAL - Capacitive dac calibration bits (fine frequency trimming). - 7 - 9 - read-write - - - ATBCTRL - Debug control bits to set the analog/digital test modes. - 16 - 2 + 1 read-write + + + DISABLE + Analog References fast wake-up feature is disabled in case of Hardware Pin reset. + 0 + + + ENABLE + Analog References fast wake-up feature is enabled in case of Hardware Pin reset. + 0x1 + + @@ -36475,23 +34238,271 @@ SPDX-License-Identifier: BSD-3-Clause FILTERCGF_SAMPLEMODE - Filter Sample mode. + Control the filtering of the Analog Comparator output. 16 2 read-write + + + BYPASS + Bypass mode. + 0 + + + FILTER1CLK + Filter 1 clock period. + 0x1 + + + FILTER2CLK + Filter 2 clock period. + 0x2 + + + FILTER3CLK + Filter 3 clock period. + 0x3 + + FILTERCGF_CLKDIV - Filter Clock div . + Filter Clock divider. 18 3 read-write + + + FILTER_1CLK_PERIOD + Filter clock period duration equals 1 Analog Comparator clock period. + 0 + + + FILTER_2CLK_PERIOD + Filter clock period duration equals 2 Analog Comparator clock period. + 0x1 + + + FILTER_4CLK_PERIOD + Filter clock period duration equals 4 Analog Comparator clock period. + 0x2 + + + FILTER_8CLK_PERIOD + Filter clock period duration equals 8 Analog Comparator clock period. + 0x3 + + + FILTER_16CLK_PERIOD + Filter clock period duration equals 16 Analog Comparator clock period. + 0x4 + + + FILTER_32CLK_PERIOD + Filter clock period duration equals 32 Analog Comparator clock period. + 0x5 + + + FILTER_64CLK_PERIOD + Filter clock period duration equals 64 Analog Comparator clock period. + 0x6 + + + FILTER_128CLK_PERIOD + Filter clock period duration equals 128 Analog Comparator clock period. + 0x7 + + + + + + + WAKEUPIOCTRL + Deep Power Down wake-up source [Reset by: PoR, Pin Reset, Software Reset] + 0x64 + 32 + read-write + 0 + 0xFF + + + RISINGEDGEWAKEUP0 + Enable / disable detection of rising edge events on Wake Up 0 pin in Deep Power Down modes:. + 0 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + - PMUXCAPT - Control word for P multiplexer for Capacitive Touch Controller. - 21 - 3 + FALLINGEDGEWAKEUP0 + Enable / disable detection of falling edge events on Wake Up 0 pin in Deep Power Down modes:. + 1 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + RISINGEDGEWAKEUP1 + Enable / disable detection of rising edge events on Wake Up 1 pin in Deep Power Down modes:. + 2 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + + + + FALLINGEDGEWAKEUP1 + Enable / disable detection of falling edge events on Wake Up 1 pin in Deep Power Down modes:. + 3 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + RISINGEDGEWAKEUP2 + Enable / disable detection of rising edge events on Wake Up 2 pin in Deep Power Down modes:. + 4 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + + + + FALLINGEDGEWAKEUP2 + Enable / disable detection of falling edge events on Wake Up 2 pin in Deep Power Down modes:. + 5 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + RISINGEDGEWAKEUP3 + Enable / disable detection of rising edge events on Wake Up 3 pin in Deep Power Down modes:. + 6 + 1 + read-write + + + DISABLE + Rising edge detection is disable. + 0 + + + ENABLE + Rising edge detection is enable. + 0x1 + + + + + FALLINGEDGEWAKEUP3 + Enable / disable detection of falling edge events on Wake Up 3 pin in Deep Power Down modes:. + 7 + 1 + read-write + + + DISABLE + Falling edge detection is disable. + 0 + + + ENABLE + Falling edge detection is enable. + 0x1 + + + + + MODEWAKEUP0 + Configure wake up I/O 0 in Deep Power Down mode + 8 + 1 + read-write + + + MODEWAKEUP1 + Configure wake up I/O 1 in Deep Power Down mode + 9 + 1 + read-write + + + MODEWAKEUP2 + Configure wake up I/O 2 in Deep Power Down mode + 10 + 1 + read-write + + + MODEWAKEUP3 + Configure wake up I/O 3 in Deep Power Down mode + 11 + 1 read-write @@ -36599,13 +34610,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-only - - FRO1MCLKVALID - FRO 1 MHz CCO voltage detector output. - 1 - 1 - read-only - XTAL32KOSCFAILURE XTAL32 KHZ oscillator oscillation failure detection indicator. @@ -36615,12 +34619,12 @@ SPDX-License-Identifier: BSD-3-Clause NOFAIL - No oscillation failure has been detetced since the last time this bit has been cleared.. + No oscillation failure has been detetced since the last time this bit has been cleared. 0 FAILURE - At least one oscillation failure has been detetced since the last time this bit has been cleared.. + At least one oscillation failure has been detetced since the last time this bit has been cleared. 0x1 @@ -36637,12 +34641,211 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - DATA31_0 - General purpose always on domain data storage. - 0 - 32 + POR + The last chip reset was caused by a Power On Reset. + 4 + 1 read-write + + PADRESET + The last chip reset was caused by a Pin Reset. + 5 + 1 + read-write + + + BODRESET + The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. + 6 + 1 + read-write + + + SYSTEMRESET + The last chip reset was caused by a System Reset requested by the ARM CPU. + 7 + 1 + read-write + + + WDTRESET + The last chip reset was caused by the Watchdog Timer. + 8 + 1 + read-write + + + SWRRESET + The last chip reset was caused by a Software event. + 9 + 1 + read-write + + + DPDRESET_WAKEUPIO + The last chip reset was caused by a Wake-up I/O reset event during a Deep Power-Down mode. + 10 + 1 + read-write + + + DPDRESET_RTC + The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during a Deep Power-Down mode. + 11 + 1 + read-write + + + DPDRESET_OSTIMER + The last chip reset was caused by an OS Event Timer reset event during a Deep Power-Down mode. + 12 + 1 + read-write + + + BOOTERRORCOUNTER + ROM Boot Fatal Error Counter. + 16 + 4 + read-write + + + + + MISCCTRL + Dummy Control bus to PMU [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] + 0x90 + 32 + read-write + 0 + 0xFFFF + + + LDODEEPSLEEPREF + Select LDO Deep Sleep reference source. + 0 + 1 + read-write + + + FLASHBUFFER + LDO DEEP Sleep uses Flash buffer biasing as reference. + 0 + + + BGP0P8V + LDO DEEP Sleep uses Band Gap 0.8V as reference. + 0x1 + + + + + LDOMEMHIGHZMODE + Control the activation of LDO MEM High Z mode. + 1 + 1 + read-write + + + DISABLE + LDO MEM High Z mode is disabled. + 0 + + + ENABLE + LDO MEM High Z mode is enabled. + 0x1 + + + + + LOWPWR_FLASH_BUF + no description available + 2 + 1 + read-write + + + MISCCTRL_3_8 + Reserved. + 3 + 5 + read-write + + + MODEWAKEUP0 + Configure wake up I/O 0 in Deep Power Down mode + 8 + 1 + read-write + + + MODEWAKEUP1 + Configure wake up I/O 1 in Deep Power Down mode + 9 + 1 + read-write + + + MODEWAKEUP2 + Configure wake up I/O 2 in Deep Power Down mode + 10 + 1 + read-write + + + MODEWAKEUP3 + Configure wake up I/O 3 in Deep Power Down mode + 11 + 1 + read-write + + + DISABLE_BLEED + Controls LDO MEM bleed current. This field is expected to be controlled by the Low Power Software only in DEEP SLEEP low power mode. + 12 + 1 + read-write + + + BLEED_ENABLE + LDO_MEM bleed current is enabled. + 0 + + + BLEED_DISABLE + LDO_MEM bleed current is disabled. Should be set before entering in Deep Sleep low power mode and cleared after wake up from Deep SLeep low power mode. + 0x1 + + + + + MISCCTRL_13_14 + Reserved. + 13 + 2 + read-write + + + WAKUPIO_RST + WAKEUP IO event detector reset control. + 15 + 1 + read-write + + + RELEASED + Wakeup IO is not reset. + 0 + + + ASSERTED + Wakeup IO is reset. + 0x1 + + + @@ -36749,492 +34952,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PDSLEEPCFG0 - Controls the power to various modules during Low Power modes - DEEP SLEEP, POWER DOWN and DEEP POWER DOWN [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] - 0xB0 - 32 - read-write - 0xC0 - 0x1FFFFFF - - - PDEN_DCDC - Controls DCDC power during DEEP SLEEP (DCDC is always shut down during POWER DOWN and DEEP POWER DOWN). - 0 - 1 - read-write - - - POWEREDON - DCDC is powered on during low power mode.. - 0 - - - POWEREDOFF - DCDC is powered off during low power mode.. - 0x1 - - - - - PDEN_BIAS - Controls Analog Bias power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 1 - 1 - read-write - - - POWEREDON - Analog Bias is powered on during low power mode.. - 0 - - - POWEREDOFF - Analog Bias is powered off during low power mode.. - 0x1 - - - - - PDEN_BODCORE - Controls Core Logic BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 2 - 1 - read-write - - - POWEREDON - BOD CORE is powered on during low power mode.. - 0 - - - POWEREDOFF - BOD CORE is powered off during low power mode.. - 0x1 - - - - - PDEN_BODVBAT - Controls VBAT BoD power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 3 - 1 - read-write - - - POWEREDON - BOD VBAT is powered on during low power mode.. - 0 - - - POWEREDOFF - BOD VBAT is powered off during low power mode.. - 0x1 - - - - - PDEN_FRO1M - Controls 1 MHz Free Running Oscillator power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - 4 - 1 - read-write - - - POWEREDON - FRO 1MHz is powered on during low power mode.. - 0 - - - POWEREDOFF - FRO 1MHz is powered off during low power mode.. - 0x1 - - - - - PDEN_FRO192M - Controls 192MHz Free Running Oscillator power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 5 - 1 - read-write - - - POWEREDON - FRO 192 MHz is powered on during low power mode.. - 0 - - - POWEREDOFF - FRO 192 MHz is powered off during low power mode.. - 0x1 - - - - - PDEN_FRO32K - Controls power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - 6 - 1 - read-write - - - POWEREDON - FRO 32 KHz is powered on during low power mode.. - 0 - - - POWEREDOFF - FRO 32 KHz is powered off during low power mode.. - 0x1 - - - - - PDEN_XTAL32K - Controls crystal 32 KHz power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - 7 - 1 - read-write - - - POWEREDON - crystal 32 KHz is powered on during low power mode.. - 0 - - - POWEREDOFF - crystal 32 KHz is powered off during low power mode.. - 0x1 - - - - - PDEN_XTAL32M - Controls crystal 32 MHz power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 8 - 1 - read-write - - - POWEREDON - crystal 32 MHz is powered on during low power mode.. - 0 - - - POWEREDOFF - crystal 32 MHz is powered off during low power mode.. - 0x1 - - - - - PDEN_PLL0 - Controls System PLL (also refered as PLL0) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 9 - 1 - read-write - - - POWEREDON - System PLL (also refered as PLL0) is powered on during low power mode.. - 0 - - - POWEREDOFF - System PLL (also refered as PLL0) is powered off during low power mode.. - 0x1 - - - - - PDEN_PLL1 - Controls USB PLL (also refered as PLL1) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 10 - 1 - read-write - - - POWEREDON - USB PLL (also refered as PLL1) is powered on during low power mode.. - 0 - - - POWEREDOFF - USB PLL (also refered as PLL1) is powered off during low power mode.. - 0x1 - - - - - PDEN_USBFSPHY - Controls USB Full Speed phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 11 - 1 - read-write - - - POWEREDON - USB Full Speed phy is powered on during low power mode.. - 0 - - - POWEREDOFF - USB Full Speed phy is powered off during low power mode.. - 0x1 - - - - - PDEN_USBHSPHY - Controls USB High Speed Phy power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 12 - 1 - read-write - - - POWEREDON - USB High Speed Phy is powered on during low power mode.. - 0 - - - POWEREDOFF - USB High Speed Phy is powered off during low power mode.. - 0x1 - - - - - PDEN_COMP - Controls Analog Comparator power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 13 - 1 - read-write - - - POWEREDON - Analog Comparator is powered on during low power mode.. - 0 - - - POWEREDOFF - Analog Comparator is powered off during low power mode.. - 0x1 - - - - - PDEN_TEMPSENS - Controls Temperature Sensor power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 14 - 1 - read-write - - - POWEREDON - Temperature Sensor is powered on during low power mode.. - 0 - - - POWEREDOFF - Temperature Sensor is powered off during low power mode.. - 0x1 - - - - - PDEN_GPADC - Controls General Purpose ADC (GPADC) power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 15 - 1 - read-write - - - POWEREDON - General Purpose ADC (GPADC) is powered on during low power mode.. - 0 - - - POWEREDOFF - General Purpose ADC (GPADC) is powered off during low power mode.. - 0x1 - - - - - PDEN_LDOMEM - Controls Memories LDO power during DEEP SLEEP, POWER DOWN and DEEP POWER DOWN. - 16 - 1 - read-write - - - POWEREDON - Memories LDO is powered on during low power mode.. - 0 - - - POWEREDOFF - Memories LDO is powered off during low power mode.. - 0x1 - - - - - PDEN_LDODEEPSLEEP - Controls Deep Sleep LDO power during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 17 - 1 - read-write - - - POWEREDON - Deep Sleep LDO is powered on during low power mode.. - 0 - - - POWEREDOFF - Deep Sleep LDO is powered off during low power mode.. - 0x1 - - - - - PDEN_LDOUSBHS - Controls USB high speed LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 18 - 1 - read-write - - - POWEREDON - USB high speed LDO is powered on during low power mode.. - 0 - - - POWEREDOFF - USB high speed LDO is powered off during low power mode.. - 0x1 - - - - - PDEN_AUXBIAS - during DEEP SLEEP and POWER DOWN (always shut down during DEEP POWER DOWN). - 19 - 1 - read-write - - - POWEREDON - is powered on during low power mode.. - 0 - - - POWEREDOFF - is powered off during low power mode.. - 0x1 - - - - - PDEN_LDOXO32M - Controls crystal 32 MHz LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 20 - 1 - read-write - - - POWEREDON - crystal 32 MHz LDO is powered on during low power mode.. - 0 - - - POWEREDOFF - crystal 32 MHz LDO is powered off during low power mode.. - 0x1 - - - - - PDEN_LDOFLASHNV - Controls Flash NV (high voltage) LDO power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 21 - 1 - read-write - - - POWEREDON - Flash NV (high voltage) is powered on during low power mode.. - 0 - - - POWEREDOFF - Flash NV (high voltage) is powered off during low power mode.. - 0x1 - - - - - PDEN_RNG - Controls True Random Number Genetaor (TRNG) clock sources power during DEEP SLEEP (always shut down during POWER DOWN and DEEP POWER DOWN). - 22 - 1 - read-write - - - POWEREDON - True Random Number Genetaor (TRNG) clock sources are powered on during low power mode.. - 0 - - - POWEREDOFF - True Random Number Genetaor (TRNG) clock sources are powered off during low power mode.. - 0x1 - - - - - PDEN_PLL0_SSCG - Controls PLL0 Spread Sprectrum module power during DEEP SLEEP (PLL0 Spread Spectrum is always shut down during POWER DOWN and DEEP POWER DOWN). - 23 - 1 - read-write - - - POWEREDON - PLL0 Spread Sprectrum module is powered on during low power mode.. - 0 - - - POWEREDOFF - PLL0 Spread Sprectrum module is powered off during low power mode.. - 0x1 - - - - - PDEN_ROM - Controls ROM power during DEEP SLEEP (ROM is always shut down during POWER DOWN and DEEP POWER DOWN). - 24 - 1 - read-write - - - POWEREDON - ROM is powered on during low power mode.. - 0 - - - POWEREDOFF - ROM is powered off during low power mode.. - 0x1 - - - - - PDRUNCFG0 Controls the power to various analog blocks [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Deep Power Down Reset, Software Reset] @@ -37244,63 +34961,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xDEFFC4 0xFFFFEF - - PDEN_DCDC - Controls power to Bulk DCDC Converter. - 0 - 1 - read-write - - - POWEREDON - DCDC is powered. - 0 - - - POWEREDOFF - DCDC is powered down. - 0x1 - - - - - PDEN_BIAS - Controls power to . - 1 - 1 - read-write - - - POWEREDON - Analog Bias is powered. - 0 - - - POWEREDOFF - Analog Bias is powered down. - 0x1 - - - - - PDEN_BODCORE - Controls power to Core Brown Out Detector (BOD). - 2 - 1 - read-write - - - POWEREDON - BOD CORE is powered. - 0 - - - POWEREDOFF - BOD CORE is powered down. - 0x1 - - - PDEN_BODVBAT Controls power to VBAT Brown Out Detector (BOD). @@ -37320,25 +34980,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PDEN_FRO192M - Controls power to the Free Running Oscillator (FRO) 192 MHz; The 12MHz, 48 MHz and 96 MHz clocks are derived from this FRO. - 5 - 1 - read-write - - - POWEREDON - FRO 192MHz is powered. - 0 - - - POWEREDOFF - FRO 192MHz is powered down. - 0x1 - - - PDEN_FRO32K Controls power to the Free Running Oscillator (FRO) 32 KHz. @@ -37379,19 +35020,19 @@ SPDX-License-Identifier: BSD-3-Clause PDEN_XTAL32M - Controls power to crystal 32 MHz. + Controls power to high speed crystal. 8 1 read-write POWEREDON - Crystal 32MHz is powered. + High speed crystal is powered. 0 POWEREDOFF - Crystal 32MHz is powered down. + High speed crystal is powered down. 0x1 @@ -37491,82 +35132,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PDEN_TEMPSENS - Controls power to Temperature Sensor. - 14 - 1 - read-write - - - POWEREDON - Temperature Sensor is powered. - 0 - - - POWEREDOFF - Temperature Sensor is powered down. - 0x1 - - - - - PDEN_GPADC - Controls power to General Purpose ADC (GPADC). - 15 - 1 - read-write - - - POWEREDON - GPADC is powered. - 0 - - - POWEREDOFF - GPADC is powered down. - 0x1 - - - - - PDEN_LDOMEM - Controls power to Memories LDO. - 16 - 1 - read-write - - - POWEREDON - Memories LDO is powered. - 0 - - - POWEREDOFF - Memories LDO is powered down. - 0x1 - - - - - PDEN_LDODEEPSLEEP - Controls power to Deep Sleep LDO. - 17 - 1 - read-write - - - POWEREDON - Deep Sleep LDO is powered. - 0 - - - POWEREDOFF - Deep Sleep LDO is powered down. - 0x1 - - - PDEN_LDOUSBHS Controls power to USB high speed LDO. @@ -37607,38 +35172,19 @@ SPDX-License-Identifier: BSD-3-Clause PDEN_LDOXO32M - Controls power to crystal 32 MHz LDO. + Controls power to high speed crystal LDO. 20 1 read-write POWEREDON - crystal 32 MHz LDO is powered. + High speed crystal LDO is powered. 0 POWEREDOFF - crystal 32 MHz LDO is powered down. - 0x1 - - - - - PDEN_LDOFLASHNV - Controls power to Flasn NV (high voltage) LDO. - 21 - 1 - read-write - - - POWEREDON - Flash NV LDO is powered. - 0 - - - POWEREDOFF - Flash NV LDO is powered down. + High speed crystal LDO is powered down. 0x1 @@ -37719,6 +35265,67 @@ SPDX-License-Identifier: BSD-3-Clause + + SRAMCTRL + All SRAMs common control signals [Reset by: PoR, Pin Reset, Brown Out Detectors Reset, Software Reset] + 0xD4 + 32 + read-write + 0x1 + 0x1FF + + + SMB + Source Biasing voltage. + 0 + 2 + read-write + + + LOW + Low leakage. + 0 + + + MEDIUM + Medium leakage. + 0x1 + + + HIGHEST + Highest leakage. + 0x2 + + + DISABLE + Disable. + 0x3 + + + + + RM + Read Margin control settings. + 2 + 3 + read-write + + + WM + Write Margin control settings. + 5 + 3 + read-write + + + WRME + Write read margin enable. + 8 + 1 + read-write + + + @@ -37767,7 +35374,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x4 0,1,2,3,4,5,6,7 FCCTRLSEL%s - Selects the source for SCK going into Flexcomm 0 + Selects the source for SCK going into Flexcomm index 0x40 32 read-write @@ -37877,7 +35484,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x4 0,1 SHAREDCTRLSET%s - Selects sources and data combinations for shared signal set 0. + Selects sources and data combinations for shared signal set index. 0x80 32 read-write @@ -38070,7 +35677,7 @@ SPDX-License-Identifier: BSD-3-Clause - F20DATAOUTEN + FC2DATAOUTEN Controls FC2 contribution to SHAREDDATAOUT for this shared set. 18 1 @@ -38088,25 +35695,6 @@ SPDX-License-Identifier: BSD-3-Clause - - FC3DATAOUTEN - Controls FC3 contribution to SHAREDDATAOUT for this shared set. - 19 - 1 - read-write - - - INPUT - Data output from FC3 does not contribute to this shared set. - 0 - - - OUTPUT - Data output from FC3 does contribute to this shared set. - 0x1 - - - FC4DATAOUTEN Controls FC4 contribution to SHAREDDATAOUT for this shared set. @@ -38190,7 +35778,7 @@ SPDX-License-Identifier: BSD-3-Clause Status register for USB HS 0x100 32 - read-write + read-only 0 0x1C0FF00 @@ -38239,7 +35827,7 @@ SPDX-License-Identifier: BSD-3-Clause 32 read-write 0x1 - 0x3FD + 0x7FD SWRESET @@ -38489,16 +36077,16 @@ SPDX-License-Identifier: BSD-3-Clause SUBSEC - RTC Sub-second Counter register + Sub-second counter register 0x10 32 read-write 0 - 0xFFFFFFFF + 0xFFFF SUBSEC - A read reflects the current value of the 32Khz sub-second counter. This counter will be cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32 KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep_powerdown mode or after the main RTC module has been disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes. + A read reflects the current value of the 32KHz sub-second counter. This counter is cleared whenever the SUBSEC_ENA bit in the RTC_CONTROL register is low. Up-counting at a 32KHz rate commences at the start of the next one-second interval after the SUBSEC_ENA bit is set. This counter must be re-enabled after exiting deep power-down mode or after the main RTC module is disabled and re-enabled. On modules not equipped with a sub-second counter, this register will read-back as all zeroes. 0 15 read-only @@ -38553,7 +36141,7 @@ SPDX-License-Identifier: BSD-3-Clause EVTIMER_COUNT_VALUE - A read reflects the current value of the lower 32 bits of the EVTIMER. Note there is physically only one EVTimer, readable from all domains. + A read reflects the current value of the lower 32 bits of the 42-bits EVTIMER. Note: There is only one EVTIMER, readable from all domains. 0 32 read-only @@ -38565,22 +36153,22 @@ SPDX-License-Identifier: BSD-3-Clause EVTIMER High Register 0x4 32 - read-only + read-write 0 0xFFFFFFFF EVTIMER_COUNT_VALUE - A read reflects the current value of the upper 32 bits of the EVTIMER. Note there is physically only one EVTimer, readable from all domains. + A read reflects the current value of the upper 10 bits of the 42-bits EVTIMER. Note there is only one EVTIMER, readable from all domains. 0 - 32 + 10 read-only - CAPTUREn_L - Local Capture Low Register for CPUn + CAPTURE_L + Capture Low Register 0x8 32 read-only @@ -38588,8 +36176,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - CAPTUREn_VALUE - A read reflects the value of the lower 32 bits of the central EVTIMER at the time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses. + CAPTURE_VALUE + A read reflects the value of the lower 32 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). 0 32 read-only @@ -38597,26 +36185,26 @@ SPDX-License-Identifier: BSD-3-Clause - CAPTUREn_H - Local Capture High Register for CPUn + CAPTURE_H + Capture High Register 0xC 32 - read-only + read-write 0 0xFFFFFFFF - CAPTUREn_VALUE - A read reflects the value of the upper 32 bits of the central EVTIMER at the time the last capture signal was generated by the CPU. A separate pair of CAPTURE registers are implemented for each CPU. Each CPU reads its own capture value at the same pair of addresses. + CAPTURE_VALUE + A read reflects the value of the upper 10 bits of the central 42-bits EVTIMER at the time the last capture signal was generated by the CPU (using CMSIS C function "__SEV();"). 0 - 32 + 10 read-only - MATCHn_L - Local Match Low Register for CPUn + MATCH_L + Match Low Register 0x10 32 read-write @@ -38624,8 +36212,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - MATCHn_VALUE - The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses. + MATCH_VALUE + The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. 0 32 read-write @@ -38633,8 +36221,8 @@ SPDX-License-Identifier: BSD-3-Clause - MATCHn_H - Match High Register for CPUn + MATCH_H + Match High Register 0x14 32 read-write @@ -38642,37 +36230,44 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - MATCHn_VALUE - The value written to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. A separate pair of MATCH registers are implemented for each CPU. Each CPU reads its own local value at the same pair of addresses. + MATCH_VALUE + The value written (upper 10 bits) to the MATCH (L/H) register pair is compared against the central EVTIMER. When a match occurs, an interrupt request is generated if enabled. 0 - 32 + 10 read-write OSEVENT_CTRL - OS_EVENT TIMER Control Register for CPUn + OS_EVENT TIMER Control Register 0x1C 32 read-write 0 - 0x3 + 0x7 OSTIMER_INTRFLAG - This bit is set when a match occurs between the central 64-bit EVTIMER and the value programmed in the Match-register pair for the associated CPU This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. This should be done before a new match value is written into the MATCH_L/H registers + This bit is set when a match occurs between the central 42-bits EVTIMER and the value programmed in the match-register pair. This bit is cleared by writing a '1'. Writes to clear this bit are asynchronous. It should be done before a new match value is written into the MATCH_L/H registers. 0 1 read-write OSTIMER_INTENA - When this bit is '1' an interrupt/wakeup request to the Domainn processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked.A separate OSEVENT_CTRL register is implemented for each CPU. Each CPU reads its own local value at the same address. + When this bit is '1' an interrupt/wakeup request to the domain processor will be asserted when the OSTIMER_INTR flag is set. When this bit is '0', interrupt/wakeup requests due to the OSTIMER_INTR flag are blocked. 1 1 read-write + + MATCH_WR_RDY + This bit will be low when it is safe to write to reload the Match Registers. In typical applications it should not be necessary to test this bit. [1] + 2 + 1 + read-only + @@ -38738,45 +36333,6 @@ SPDX-License-Identifier: BSD-3-Clause - - BURST - read burst register - 0x8 - 32 - read-write - 0x80000000 - 0xFFFFFFFF - - - XOR_MASK - burst 2 XOR mask. - 0 - 20 - read-write - - - DESCR1 - Burst 1 descriptor. - 20 - 4 - read-write - - - DESCR2 - Burst 2 descriptor. - 24 - 4 - read-write - - - DESCR3 - Burst 3 descriptor. - 28 - 4 - read-write - - - STARTA start (or only) address for next flash command @@ -38814,7 +36370,7 @@ SPDX-License-Identifier: BSD-3-Clause - 8 + 4 0x4 DATAW[%s] data register, word 0-7; Memory data, or command parameter, or command result. @@ -39137,12 +36693,12 @@ SPDX-License-Identifier: BSD-3-Clause DISABLED - Encryption of writes to the flash controller DATAW* registers is disabled.. + Encryption of writes to the flash controller DATAW* registers is disabled. 0 ENABLED - Encryption of writes to the flash controller DATAW* registers is enabled.. + Encryption of writes to the flash controller DATAW* registers is enabled. 0x1 @@ -39521,6 +37077,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x110 registers + + USB1_PHY + 46 + PWD @@ -40718,6 +38278,13 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode @@ -40745,16 +38312,37 @@ SPDX-License-Identifier: BSD-3-Clause - DEVPLUGIN_IRQ - Indicates that the device is connected - 12 + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 1 read-write - DATA_ON_LRADC - Data on LR ADC: Enables the LRADC to monitor USB_DP and USB_DM - 13 + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + + + DEVPLUGIN_IRQ + Indicates that the device is connected + 12 1 read-write @@ -40772,6 +38360,20 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) @@ -40794,16 +38396,30 @@ SPDX-License-Identifier: BSD-3-Clause read-write - FSDLL_RST_EN - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. - 24 + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 1 read-write - OTG_ID_VALUE - Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle - 27 + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 1 read-write @@ -40853,6 +38469,13 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode @@ -40879,6 +38502,34 @@ SPDX-License-Identifier: BSD-3-Clause + + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + DEVPLUGIN_IRQ Indicates that the device is connected @@ -40900,6 +38551,20 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) @@ -40922,16 +38587,30 @@ SPDX-License-Identifier: BSD-3-Clause read-write - FSDLL_RST_EN - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. - 24 + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 1 read-write - OTG_ID_VALUE - Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle - 27 + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 1 read-write @@ -40947,7 +38626,7 @@ SPDX-License-Identifier: BSD-3-Clause Used by the PHY to indicate a powered-down state 29 1 - read-write + read-only CLKGATE @@ -40981,6 +38660,13 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode @@ -41007,6 +38693,34 @@ SPDX-License-Identifier: BSD-3-Clause + + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + DEVPLUGIN_IRQ Indicates that the device is connected @@ -41028,6 +38742,20 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) @@ -41050,16 +38778,30 @@ SPDX-License-Identifier: BSD-3-Clause read-write - FSDLL_RST_EN - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. - 24 + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 1 read-write - OTG_ID_VALUE - Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle - 27 + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 1 read-write @@ -41109,6 +38851,13 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQHOSTDISCON + Enable IRQ for Host disconnect: Enables interrupt for detection of disconnection to Device when in high-speed host mode + 2 + 1 + read-write + HOSTDISCONDETECT_IRQ Indicates that the device has disconnected in High-Speed mode @@ -41135,6 +38884,34 @@ SPDX-License-Identifier: BSD-3-Clause + + DEVPLUGIN_POLARITY + Device plugin polarity: For device mode, if this bit is cleared to 0, then it trips the interrupt if the device is plugged in + 5 + 1 + read-write + + + RESUMEIRQSTICKY + Resume IRQ: Set to 1 will make RESUME_IRQ bit a sticky bit until software clear it + 8 + 1 + read-write + + + ENIRQRESUMEDETECT + Enable IRQ Resume detect: Enables interrupt for detection of a non-J state on the USB line + 9 + 1 + read-write + + + RESUME_IRQ + Resume IRQ: Indicates that the host is sending a wake-up after suspend + 10 + 1 + read-write + DEVPLUGIN_IRQ Indicates that the device is connected @@ -41156,6 +38933,20 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write + + ENIRQWAKEUP + Enable wake-up IRQ: Enables interrupt for the wake-up events. + 16 + 1 + read-write + + + WAKEUP_IRQ + Wake-up IRQ: Indicates that there is a wak-eup event + 17 + 1 + read-write + AUTORESUME_EN Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only) @@ -41178,16 +38969,30 @@ SPDX-License-Identifier: BSD-3-Clause read-write - FSDLL_RST_EN - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet. - 24 + ENDPDMCHG_WKUP + Enable DP DM change wake-up: Not for customer use + 21 1 read-write - OTG_ID_VALUE - Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle - 27 + ENVBUSCHG_WKUP + Enable VBUS change wake-up: Enables the feature to wake-up USB if VBUS is toggled when USB is suspended + 23 + 1 + read-write + + + ENAUTOCLR_USBCLKGATE + Enable auto-clear USB Clock gate: Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit in HW_DIGCTL_CTRL if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 25 + 1 + read-write + + + ENAUTOSET_USBCLKS + Enable auto-set of USB clocks: Enables the feature to auto-clear the EN_USB_CLKS register bits in HW_CLKCTRL_PLL1CTRL0/HW_CLKCTRL_P LL1CTRL1 if there is wake-up event on USB0/USB1 while USB0/USB1 is suspended + 26 1 read-write @@ -41230,12 +39035,19 @@ SPDX-License-Identifier: BSD-3-Clause 0 0xFFFFFFFF + + OK_STATUS_3V + Indicates the USB 3v power rails are in range. + 0 + 1 + read-only + HOSTDISCONDETECT_STATUS Indicates at the local host (downstream) port that the remote device has disconnected while in High-Speed mode 3 1 - read-write + read-only value0 @@ -41254,7 +39066,7 @@ SPDX-License-Identifier: BSD-3-Clause Status indicator for non-standard resistive plugged-in detection Indicates that the device has been connected on the USB_DP and USB_DM lines using the nonstandard resistive plugged-in detection method controlled by CTRL[4] 6 1 - read-write + read-only value0 @@ -41268,618 +39080,11 @@ SPDX-License-Identifier: BSD-3-Clause - - OTGID_STATUS - Indicates the results of USB_ID pin on the USB cable plugged into the local Micro- or Mini-AB receptacle - 8 - 1 - read-write - RESUME_STATUS Indicates that the host is sending a wake-up after Suspend and has triggered an interrupt. 10 1 - read-write - - - - - DEBUG0 - USB PHY Debug Register 0 - 0x50 - 32 - read-write - 0x7F180000 - 0xFFFFFFFF - - - OTGIDPIOLOCK - Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value - 0 - 1 - read-write - - - DEBUG_INTERFACE_HOLD - Use holding registers to assist in timing for external UTMI interface. - 1 - 1 - read-write - - - HSTPULLDOWN - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line - 2 - 2 - read-write - - - ENHSTPULLDOWN - This bit field selects host pulldown overdrive mode - 4 - 2 - read-write - - - TX2RXCOUNT - Delay in between the end of transmit to the beginning of receive - 8 - 4 - read-write - - - ENTX2RXCOUNT - Set this bit to allow a countdown to transition in between TX and RX. - 12 - 1 - read-write - - - SQUELCHRESETCOUNT - Delay in between the detection of squelch to the reset of high-speed RX. - 16 - 5 - read-write - - - ENSQUELCHRESET - Set bit to allow squelch to reset high-speed receive. - 24 - 1 - read-write - - - SQUELCHRESETLENGTH - Duration of RESET in terms of the number of 480-MHz cycles. - 25 - 4 - read-write - - - HOST_RESUME_DEBUG - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. - 29 - 1 - read-write - - - CLKGATE - Gate Test Clocks - 30 - 1 - read-write - - - - - DEBUG0_SET - USB PHY Debug Register 0 - 0x54 - 32 - read-write - 0x7F180000 - 0xFFFFFFFF - - - OTGIDPIOLOCK - Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value - 0 - 1 - read-write - - - DEBUG_INTERFACE_HOLD - Use holding registers to assist in timing for external UTMI interface. - 1 - 1 - read-write - - - HSTPULLDOWN - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line - 2 - 2 - read-write - - - ENHSTPULLDOWN - This bit field selects host pulldown overdrive mode - 4 - 2 - read-write - - - TX2RXCOUNT - Delay in between the end of transmit to the beginning of receive - 8 - 4 - read-write - - - ENTX2RXCOUNT - Set this bit to allow a countdown to transition in between TX and RX. - 12 - 1 - read-write - - - SQUELCHRESETCOUNT - Delay in between the detection of squelch to the reset of high-speed RX. - 16 - 5 - read-write - - - ENSQUELCHRESET - Set bit to allow squelch to reset high-speed receive. - 24 - 1 - read-write - - - SQUELCHRESETLENGTH - Duration of RESET in terms of the number of 480-MHz cycles. - 25 - 4 - read-write - - - HOST_RESUME_DEBUG - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. - 29 - 1 - read-write - - - CLKGATE - Gate Test Clocks - 30 - 1 - read-write - - - - - DEBUG0_CLR - USB PHY Debug Register 0 - 0x58 - 32 - read-write - 0x7F180000 - 0xFFFFFFFF - - - OTGIDPIOLOCK - Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value - 0 - 1 - read-write - - - DEBUG_INTERFACE_HOLD - Use holding registers to assist in timing for external UTMI interface. - 1 - 1 - read-write - - - HSTPULLDOWN - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line - 2 - 2 - read-write - - - ENHSTPULLDOWN - This bit field selects host pulldown overdrive mode - 4 - 2 - read-write - - - TX2RXCOUNT - Delay in between the end of transmit to the beginning of receive - 8 - 4 - read-write - - - ENTX2RXCOUNT - Set this bit to allow a countdown to transition in between TX and RX. - 12 - 1 - read-write - - - SQUELCHRESETCOUNT - Delay in between the detection of squelch to the reset of high-speed RX. - 16 - 5 - read-write - - - ENSQUELCHRESET - Set bit to allow squelch to reset high-speed receive. - 24 - 1 - read-write - - - SQUELCHRESETLENGTH - Duration of RESET in terms of the number of 480-MHz cycles. - 25 - 4 - read-write - - - HOST_RESUME_DEBUG - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. - 29 - 1 - read-write - - - CLKGATE - Gate Test Clocks - 30 - 1 - read-write - - - - - DEBUG0_TOG - USB PHY Debug Register 0 - 0x5C - 32 - read-write - 0x7F180000 - 0xFFFFFFFF - - - OTGIDPIOLOCK - Once OTG ID from STATUS_OTGID_STATUS is sampled, use this to hold the value - 0 - 1 - read-write - - - DEBUG_INTERFACE_HOLD - Use holding registers to assist in timing for external UTMI interface. - 1 - 1 - read-write - - - HSTPULLDOWN - This bit field selects whether to connect pulldown resistors on the USB_DP/USB_DM pins if the corresponding pulldown overdrive mode is enabled through DEBUG[5:4} Set bit 3 to value 1'b1 to connect the 15ohm pulldown on USB_DP line - 2 - 2 - read-write - - - ENHSTPULLDOWN - This bit field selects host pulldown overdrive mode - 4 - 2 - read-write - - - TX2RXCOUNT - Delay in between the end of transmit to the beginning of receive - 8 - 4 - read-write - - - ENTX2RXCOUNT - Set this bit to allow a countdown to transition in between TX and RX. - 12 - 1 - read-write - - - SQUELCHRESETCOUNT - Delay in between the detection of squelch to the reset of high-speed RX. - 16 - 5 - read-write - - - ENSQUELCHRESET - Set bit to allow squelch to reset high-speed receive. - 24 - 1 - read-write - - - SQUELCHRESETLENGTH - Duration of RESET in terms of the number of 480-MHz cycles. - 25 - 4 - read-write - - - HOST_RESUME_DEBUG - Choose to trigger the host resume SE0 with HOST_FORCE_LS_SE0 = 0 or UTMI_SUSPEND = 1. - 29 - 1 - read-write - - - CLKGATE - Gate Test Clocks - 30 - 1 - read-write - - - - - DEBUG1 - UTMI Debug Status Register 1 - 0x70 - 32 - read-write - 0x1000 - 0xFFFFFFFF - - - ENTAILADJVD - Delay increment of the rise of squelch: - 13 - 2 - read-write - - - value0 - Delay is nominal - 0 - - - value1 - Delay is +20% - 0x1 - - - value2 - Delay is -20% - 0x2 - - - value3 - Delay is -40% - 0x3 - - - - - USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap - 18 - 3 - read-write - - - USB2_REFBIAS_TST - Bias current control for usb2_phy - 21 - 2 - read-write - - - - - DEBUG1_SET - UTMI Debug Status Register 1 - 0x74 - 32 - read-write - 0x1000 - 0xFFFFFFFF - - - ENTAILADJVD - Delay increment of the rise of squelch: - 13 - 2 - read-write - - - value0 - Delay is nominal - 0 - - - value1 - Delay is +20% - 0x1 - - - value2 - Delay is -20% - 0x2 - - - value3 - Delay is -40% - 0x3 - - - - - USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap - 18 - 3 - read-write - - - USB2_REFBIAS_TST - Bias current control for usb2_phy - 21 - 2 - read-write - - - - - DEBUG1_CLR - UTMI Debug Status Register 1 - 0x78 - 32 - read-write - 0x1000 - 0xFFFFFFFF - - - ENTAILADJVD - Delay increment of the rise of squelch: - 13 - 2 - read-write - - - value0 - Delay is nominal - 0 - - - value1 - Delay is +20% - 0x1 - - - value2 - Delay is -20% - 0x2 - - - value3 - Delay is -40% - 0x3 - - - - - USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap - 18 - 3 - read-write - - - USB2_REFBIAS_TST - Bias current control for usb2_phy - 21 - 2 - read-write - - - - - DEBUG1_TOG - UTMI Debug Status Register 1 - 0x7C - 32 - read-write - 0x1000 - 0xFFFFFFFF - - - ENTAILADJVD - Delay increment of the rise of squelch: - 13 - 2 - read-write - - - value0 - Delay is nominal - 0 - - - value1 - Delay is +20% - 0x1 - - - value2 - Delay is -20% - 0x2 - - - value3 - Delay is -40% - 0x3 - - - - - USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap - 18 - 3 - read-write - - - USB2_REFBIAS_TST - Bias current control for usb2_phy - 21 - 2 - read-write - - - - - VERSION - UTMI RTL Version - 0x80 - 32 - read-only - 0x5000000 - 0xFFFFFFFF - - - STEP - Fixed read-only value reflecting the stepping of the RTL version. - 0 - 16 - read-only - - - MINOR - Fixed read-only value reflecting the MINOR field of the RTL version - 16 - 8 - read-only - - - MAJOR - Fixed read-only value reflecting the MAJOR field of the RTL versio - 24 - 8 read-only @@ -41893,13 +39098,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xD12000 0xFFFFFFFF - - MISC2_CONTROL0 - Modifies the operation of the pll_sic_power_int signal - 5 - 1 - read-write - PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY @@ -41921,13 +39119,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - PLL_BYPASS - Bypass the USB PLL. - 16 - 1 - read-write - REFBIAS_PWD_SEL Reference bias power down select. @@ -42010,12 +39201,19 @@ SPDX-License-Identifier: BSD-3-Clause + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + PLL_LOCK USB PLL lock status indicator 31 1 - read-write + read-only value0 @@ -42040,13 +39238,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xD12000 0xFFFFFFFF - - MISC2_CONTROL0 - Modifies the operation of the pll_sic_power_int signal - 5 - 1 - read-write - PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY @@ -42068,13 +39259,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - PLL_BYPASS - Bypass the USB PLL. - 16 - 1 - read-write - REFBIAS_PWD_SEL Reference bias power down select. @@ -42157,12 +39341,19 @@ SPDX-License-Identifier: BSD-3-Clause + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + PLL_LOCK USB PLL lock status indicator 31 1 - read-write + read-only value0 @@ -42187,13 +39378,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xD12000 0xFFFFFFFF - - MISC2_CONTROL0 - Modifies the operation of the pll_sic_power_int signal - 5 - 1 - read-write - PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY @@ -42215,13 +39399,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - PLL_BYPASS - Bypass the USB PLL. - 16 - 1 - read-write - REFBIAS_PWD_SEL Reference bias power down select. @@ -42304,12 +39481,19 @@ SPDX-License-Identifier: BSD-3-Clause + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + PLL_LOCK USB PLL lock status indicator 31 1 - read-write + read-only value0 @@ -42334,13 +39518,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xD12000 0xFFFFFFFF - - MISC2_CONTROL0 - Modifies the operation of the pll_sic_power_int signal - 5 - 1 - read-write - PLL_EN_USB_CLKS Enables the USB clock from PLL to USB PHY @@ -42362,13 +39539,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - PLL_BYPASS - Bypass the USB PLL. - 16 - 1 - read-write - REFBIAS_PWD_SEL Reference bias power down select. @@ -42451,12 +39621,19 @@ SPDX-License-Identifier: BSD-3-Clause + + PLL_PREDIV + This is selection between /1 or /2 to expand the range of ref input clock. + 30 + 1 + read-write + PLL_LOCK USB PLL lock status indicator 31 1 - read-write + read-only value0 @@ -42620,6 +39797,58 @@ SPDX-License-Identifier: BSD-3-Clause + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pinmuxed value: + 13 + 1 + read-write + + + value0 + Select the Muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pinmuxed value. + 14 + 1 + read-write + + + value0 + Select the Muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator @@ -42640,11 +39869,18 @@ SPDX-License-Identifier: BSD-3-Clause - PWRUP_CMPS - Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector - 20 + VBUSVALID_5VDETECT + no description available + 19 1 read-write + + + PWRUP_CMPS + Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector + 20 + 3 + read-write value0 @@ -42654,7 +39890,7 @@ SPDX-License-Identifier: BSD-3-Clause value1 Enables the VBUS_VALID comparator (default) - 0x1 + 0x7 @@ -42677,25 +39913,6 @@ SPDX-License-Identifier: BSD-3-Clause - - EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - 31 - 1 - read-write - - - value0 - Disable resistive charger detection resistors on USB_DP and USB_DP - 0 - - - value1 - Enable resistive charger detection resistors on USB_DP and USB_DP - 0x1 - - - @@ -42846,6 +40063,58 @@ SPDX-License-Identifier: BSD-3-Clause + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pinmuxed value: + 13 + 1 + read-write + + + value0 + Select the Muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pinmuxed value. + 14 + 1 + read-write + + + value0 + Select the Muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator @@ -42866,11 +40135,18 @@ SPDX-License-Identifier: BSD-3-Clause - PWRUP_CMPS - Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector - 20 + VBUSVALID_5VDETECT + no description available + 19 1 read-write + + + PWRUP_CMPS + Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector + 20 + 3 + read-write value0 @@ -42880,7 +40156,7 @@ SPDX-License-Identifier: BSD-3-Clause value1 Enables the VBUS_VALID comparator (default) - 0x1 + 0x7 @@ -42903,25 +40179,6 @@ SPDX-License-Identifier: BSD-3-Clause - - EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - 31 - 1 - read-write - - - value0 - Disable resistive charger detection resistors on USB_DP and USB_DP - 0 - - - value1 - Enable resistive charger detection resistors on USB_DP and USB_DP - 0x1 - - - @@ -43072,6 +40329,58 @@ SPDX-License-Identifier: BSD-3-Clause + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pinmuxed value: + 13 + 1 + read-write + + + value0 + Select the Muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pin muxed value. + 14 + 1 + read-write + + + value0 + Select the muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator @@ -43092,11 +40401,18 @@ SPDX-License-Identifier: BSD-3-Clause - PWRUP_CMPS - Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector - 20 + VBUSVALID_5VDETECT + no description available + 19 1 read-write + + + PWRUP_CMPS + Enables the VBUS_VALID comparator: Powers up the comparator used for the VBUS_VALID detector + 20 + 3 + read-write value0 @@ -43106,7 +40422,7 @@ SPDX-License-Identifier: BSD-3-Clause value1 Enables the VBUS_VALID comparator (default) - 0x1 + 0x7 @@ -43129,25 +40445,6 @@ SPDX-License-Identifier: BSD-3-Clause - - EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - 31 - 1 - read-write - - - value0 - Disable resistive charger detection resistors on USB_DP and USB_DP - 0 - - - value1 - Enable resistive charger detection resistors on USB_DP and USB_DP - 0x1 - - - @@ -43298,6 +40595,58 @@ SPDX-License-Identifier: BSD-3-Clause + + ID_OVERRIDE_EN + Enable ID override using the register field. This bit is only used if EXT_ID_OVERRIDE_EN = 1'b0. + 11 + 1 + read-write + + + ID_OVERRIDE + ID override value. + 12 + 1 + read-write + + + EXT_ID_OVERRIDE_EN + Enable ID override using the pin muxed value. + 13 + 1 + read-write + + + value0 + Select the muxed value chosen using ID_OVERRIDE_EN. + 0 + + + value1 + Select the external ID value. + 0x1 + + + + + EXT_VBUS_OVERRIDE_EN + Enable VBUS override using the pin muxed value. + 14 + 1 + read-write + + + value0 + Select the Muxed value chosen using VBUS_OVERRIDE_EN. + 0 + + + value1 + Select the external VBUS VALID value. + 0x1 + + + VBUSVALID_TO_SESSVALID Selects the comparator used for VBUS_VALID This bit field controls the comparator used to report the VBUS_VALID results in USB1_VBUS_DETECT[3] between the VBUS_VALID comparator and the Session Valid comparator @@ -43317,11 +40666,18 @@ SPDX-License-Identifier: BSD-3-Clause + + VBUSVALID_5VDETECT + no description available + 19 + 1 + read-write + PWRUP_CMPS Enables the VBUS_VALID comparator Powers up the comparator used for the VBUS_VALID detector 20 - 1 + 3 read-write @@ -43332,7 +40688,7 @@ SPDX-License-Identifier: BSD-3-Clause value1 Enables the VBUS_VALID comparator (default) - 0x1 + 0x7 @@ -43355,385 +40711,6 @@ SPDX-License-Identifier: BSD-3-Clause - - EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - 31 - 1 - read-write - - - value0 - Disable resistive charger detection resistors on USB_DP and USB_DP - 0 - - - value1 - Enable resistive charger detection resistors on USB_DP and USB_DP - 0x1 - - - - - - - USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register - 0xD0 - 32 - read-only - 0 - 0xFFFFFFFF - - - SESSEND - Session End indicator Session End status, value inverted from Session Valid comparator - 0 - 1 - read-only - - - value0 - The VBUS voltage is above the Session Valid threshold - 0 - - - value1 - The VBUS voltage is below the Session Valid threshold - 0x1 - - - - - BVALID - B-Device Session Valid status B-Device Session Valid status, determined by the Session Valid comparator - 1 - 1 - read-only - - - value0 - The VBUS voltage is below the Session Valid threshold - 0 - - - value1 - The VBUS voltage is above the Session Valid threshold - 0x1 - - - - - AVALID - A-Device Session Valid status A-Device Session Valid status, determined by the Session Valid comparator - 2 - 1 - read-only - - - value0 - The VBUS voltage is below the Session Valid threshold - 0 - - - value1 - The VBUS voltage is above the Session Valid threshold - 0x1 - - - - - VBUS_VALID - VBUS voltage status This bit field shows the result of VBUS_VALID detection for the USB1_VBUS pin - 3 - 1 - read-only - - - value0 - VBUS is below the comparator threshold - 0 - - - value1 - VBUS is above the comparator threshold - 0x1 - - - - - VBUS_VALID_3V - VBUS_VALID_3V detector status The VBUS_VALID_3V detector has a lower threshold for the voltage on the USB1_VBUS pin than either the Session Valid or VBUS_VALID comparators - 4 - 1 - read-only - - - value0 - VBUS voltage is below VBUS_VALID_3V threshold - 0 - - - value1 - VBUS voltage is above VBUS_VALID_3V threshold - 0x1 - - - - - - - USB1_CHRG_DETECT - USB PHY Charger Detect Control Register - 0xE0 - 32 - read-write - 0x80180000 - 0xFFFFFFFF - - - PULLUP_DP - This bit is used to pull up DP, for digital charge detect. - 2 - 1 - read-write - - - BGR_IBIAS - USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector - 23 - 1 - read-write - - - value0 - Bias current is derived from the USB PHY internal current generator. - 0 - - - value1 - Bias current is derived from the reference generator of the bandgap. - 0x1 - - - - - - - USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register - 0xE4 - 32 - read-write - 0x80180000 - 0xFFFFFFFF - - - PULLUP_DP - This bit is used to pull up DP, for digital charge detect. - 2 - 1 - read-write - - - BGR_IBIAS - USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector - 23 - 1 - read-write - - - value0 - Bias current is derived from the USB PHY internal current generator. - 0 - - - value1 - Bias current is derived from the reference generator of the bandgap. - 0x1 - - - - - - - USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register - 0xE8 - 32 - read-write - 0x80180000 - 0xFFFFFFFF - - - PULLUP_DP - This bit is used to pull up DP, for digital charge detect. - 2 - 1 - read-write - - - BGR_IBIAS - USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector - 23 - 1 - read-write - - - value0 - Bias current is derived from the USB PHY internal current generator. - 0 - - - value1 - Bias current is derived from the reference generator of the bandgap. - 0x1 - - - - - - - USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register - 0xEC - 32 - read-write - 0x80180000 - 0xFFFFFFFF - - - PULLUP_DP - This bit is used to pull up DP, for digital charge detect. - 2 - 1 - read-write - - - BGR_IBIAS - USB charge detector bias current reference This bit determines the reference for the bias current of the USB charge detector - 23 - 1 - read-write - - - value0 - Bias current is derived from the USB PHY internal current generator. - 0 - - - value1 - Bias current is derived from the reference generator of the bandgap. - 0x1 - - - - - - - USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register - 0xF0 - 32 - read-only - 0 - 0xFFFFFFFF - - - PLUG_CONTACT - Battery Charging Data Contact Detection phase output During the Data Contact Detection phase per the USB Battery Charging Specification Revision 1 - 0 - 1 - read-only - - - value0 - No USB cable attachment has been detected - 0 - - - value1 - A USB cable attachment between the device and host has been detected - 0x1 - - - - - CHRG_DETECTED - Battery Charging Primary Detection phase output During the USB Battery Charging Primary Detection phase using the USBHSDCD module, this bit field indicates whether a Standard Downstream Port or Charging Port was detected - 1 - 1 - read-only - - - value0 - Standard Downstream Port (SDP) has been detected - 0 - - - value1 - Charging Port has been detected - 0x1 - - - - - DM_STATE - Single ended receiver output for the USB_DM pin, from charger detection circuits. - 2 - 1 - read-only - - - value0 - USB_DM pin voltage is < 0.8V - 0 - - - value1 - USB_DM pin voltage is > 2.0V - 0x1 - - - - - DP_STATE - Single ended receiver output for the USB_DP pin, from charger detection circuits. - 3 - 1 - read-only - - - value0 - USB_DP pin voltage is < 0.8V - 0 - - - value1 - USB_DP pin voltage is > 2.0V - 0x1 - - - - - SECDET_DCP - Battery Charging Secondary Detection phase output During the USB Battery Charging Secondary Detection phase using the USBHSDCD module, this bit field indicates which kind of Charging Port was detected - 4 - 1 - read-only - - - value0 - Charging Downstream Port (CDP) has been detected - 0 - - - value1 - Downstream Charging Port (DCP) has been detected - 0x1 - - - @@ -43745,6 +40722,20 @@ SPDX-License-Identifier: BSD-3-Clause 0xA000402 0xFFFFFFFF + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins @@ -43775,6 +40766,20 @@ SPDX-License-Identifier: BSD-3-Clause 0xA000402 0xFFFFFFFF + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins @@ -43805,6 +40810,20 @@ SPDX-License-Identifier: BSD-3-Clause 0xA000402 0xFFFFFFFF + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins @@ -43835,6 +40854,20 @@ SPDX-License-Identifier: BSD-3-Clause 0xA000402 0xFFFFFFFF + + LVI_EN + Vow voltage detector enable bit. + 1 + 1 + read-write + + + PFD_CLK_SEL + For normal USB operation, this bit field must remain at value 2'b00. + 2 + 2 + read-write + DEV_PULLDOWN Setting this field to 1'b1 will enable the 15kohm pulldown resistors on both USB_DP and USB_DM pins @@ -43887,24 +40920,6 @@ SPDX-License-Identifier: BSD-3-Clause - - ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed - 0x4 - 32 - read-only - 0 - 0xFFFFFFFF - - - ENCRYPTED_NUMBER - This register contains a random 32 bit number which is pre-computed. - 0 - 32 - read-only - - - COUNTER_VAL no description available @@ -43960,20 +40975,6 @@ SPDX-License-Identifier: BSD-3-Clause 3 read-write - - DIS_ENH_ENTR_REFILL - Disable 'enhanced entropy refill' feature, which is enabled by default when 'mode' > 00. - 8 - 1 - read-write - - - FORCE_ENTR_SPREADING - Forces entropy spreading (interactions between RNGs) even when 'clock_sel'>0. - 9 - 1 - read-write - @@ -44033,63 +41034,6 @@ SPDX-License-Identifier: BSD-3-Clause - - MISC_CFG - no description available - 0x18 - 32 - read-write - 0 - 0x3 - - - AES_RESEED - If set, ENCRYPTED_NUMBER generation becomes predictable, provided all secrets and current internal state are known: independant from entropy source. - 0 - 1 - read-write - - - AES_DT_CFG - Set this bit to re-seed AES. - 1 - 1 - read-write - - - - - POWERDOWN - Powerdown mode (standard but certainly useless here) - 0xFF4 - 32 - read-write - 0 - 0x80000003 - - - SOFT_RESET - Request softreset that will go low automaticaly after acknowledge from CORE. - 0 - 1 - read-write - - - FORCE_SOFT_RESET - When used with softreset it forces CORE_RESETN to low on acknowledge from CORE. - 1 - 1 - read-write - - - POWERDOWN - When set all accesses to standard registers are blocked. - 31 - 1 - read-write - - - MODULEID IP identifier @@ -44260,7 +41204,7 @@ SPDX-License-Identifier: BSD-3-Clause error - Quiddikey is in the Error state and no operations can be performed + PUF is in the Error state and no operations can be performed 2 1 read-only @@ -44452,7 +41396,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - KEYOUT + VERSION Version of the PUF module. 0 32 @@ -44655,7 +41599,7 @@ SPDX-License-Identifier: BSD-3-Clause KEY2 - "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." "10:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is allowed. 00, 01, 11:Write access to KEY3MASK, KEYENABLE.KEY3 and KEYRESET.KEY3 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." + "10:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is allowed. 00, 01, 11:Write access to KEY2MASK, KEYENABLE.KEY2 and KEYRESET.KEY2 is NOT allowed. Important Note : Once this field is written with a value different from '10', its value can no longer be modified until un Power On Reset occurs." 4 2 read-write @@ -44701,7 +41645,7 @@ SPDX-License-Identifier: BSD-3-Clause KEY3 - "10: Data coming out from PUF Index 0 interface are shifted in KEY2 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." + "10: Data coming out from PUF Index 0 interface are shifted in KEY3 register. 00, 01, 11 : Data coming out from PUF Index 0 interface are NOT shifted in KEY3 register." 6 2 read-write @@ -44756,13 +41700,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x8000AAAA 0xC000FFFF - - IDX0 - Use to block PUF index 0 - 0 - 2 - read-write - IDX1 Use to block PUF index 1 @@ -44991,13 +41928,6 @@ SPDX-License-Identifier: BSD-3-Clause 0xAAAA 0xFFFF - - IDX0 - Use to block PUF index 0 - 0 - 2 - read-write - IDX1 Use to block PUF index 1 @@ -45115,8 +42045,8 @@ SPDX-License-Identifier: BSD-3-Clause 5 0x4 0,1,2,3,4 - LUT_INP%s - LUT0 input 0 MUX + LUT_INP_MUX%s + LUTn input x MUX 0 32 read-write @@ -45124,8 +42054,8 @@ SPDX-License-Identifier: BSD-3-Clause 0x3F - LUT_INP - Selects the input source to be connected to LUT0 input0. + LUTn_INPx + Selects the input source to be connected to LUT0 input0. For each LUT, the slot associated with the output from LUTn itself is tied low. 0 6 read-write @@ -45319,7 +42249,7 @@ SPDX-License-Identifier: BSD-3-Clause 26 0x4 LUT_TRUTH[%s] - Specifies the Truth Table contents for LUT0 + Specifies the Truth Table contents for LUTLUTn 0x800 32 read-write @@ -45327,7 +42257,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - TRUTH_TABLE + LUTn_TRUTH Specifies the Truth Table contents for LUT0.. 0 32 @@ -45354,7 +42284,7 @@ SPDX-License-Identifier: BSD-3-Clause - WAKEINT + WAKEINT_CTRL Wakeup interrupt control for PLU 0x904 32 @@ -45371,7 +42301,7 @@ SPDX-License-Identifier: BSD-3-Clause FILTER_MODE - control input of the PLU, add filtering for glitch + control input of the PLU, add filtering for glitch. 8 2 read-write @@ -45400,10 +42330,27 @@ SPDX-License-Identifier: BSD-3-Clause FILTER_CLKSEL - hclk is divided by 2**filter_clksel + hclk is divided by 2**filter_clksel. 10 2 read-write + + + FRO1MHZ + Selects the 1 MHz low-power oscillator as the filter clock. + 0 + + + FRO12MHZ + Selects the 12 Mhz FRO as the filter clock. + 0x1 + + + OTHER_CLOCK + Selects a third filter clock source, if provided. + 0x2 + + LATCH_ENABLE @@ -45426,7 +42373,7 @@ SPDX-License-Identifier: BSD-3-Clause 8 0x4 OUTPUT_MUX[%s] - Selects the source to be connected to PLU Output 0 + Selects the source to be connected to PLU Output OUTPUT_n 0xC00 32 read-write @@ -45604,7 +42551,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x40082000 0 - 0x5DC + 0x56C registers @@ -45926,7 +42873,7 @@ SPDX-License-Identifier: BSD-3-Clause - 30 + 23 0x10 CHANNEL[%s] no description available @@ -46362,7 +43309,7 @@ SPDX-License-Identifier: BSD-3-Clause 0x400A7000 0 - 0x5DC + 0x49C registers @@ -47132,10 +44079,50 @@ SPDX-License-Identifier: BSD-3-Clause Falling edges on input 3. 0x7 + + INPUT_4_RISING_EDGES + Rising edges on input 4. + 0x8 + + + INPUT_4_FALLING_EDGE + Falling edges on input 4. + 0x9 + + + INPUT_5_RISING_EDGES + Rising edges on input 5. + 0xA + + + INPUT_5_FALLING_EDGE + Falling edges on input 5. + 0xB + + + INPUT_6_RISING_EDGES + Rising edges on input 6. + 0xC + + + INPUT_6_FALLING_EDGE + Falling edges on input 6. + 0xD + + + INPUT_7_RISING_EDGES + Rising edges on input 7. + 0xE + + + INPUT_7_FALLING_EDGE + Falling edges on input 7. + 0xF + - NORELAOD_L + NORELOAD_L A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Setting this bit eliminates the need to write to the reload registers MATCHREL if the match values are fixed. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set. 7 1 @@ -48589,7 +45576,7 @@ SPDX-License-Identifier: BSD-3-Clause - DMA0REQUEST + DMAREQ0 SCT DMA request 0 register 0x5C 32 @@ -48621,7 +45608,7 @@ SPDX-License-Identifier: BSD-3-Clause - DMA1REQUEST + DMAREQ1 SCT DMA request 1 register 0x60 32 @@ -48739,7 +45726,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP0 + CAP0 SCT capture register of capture channel CAP_MATCH 0x100 @@ -48765,7 +45752,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH0 + MATCH0 SCT match value register of match channels CAP_MATCH 0x100 @@ -48791,7 +45778,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP1 + CAP1 SCT capture register of capture channel CAP_MATCH 0x104 @@ -48817,7 +45804,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH1 + MATCH1 SCT match value register of match channels CAP_MATCH 0x104 @@ -48843,7 +45830,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP2 + CAP2 SCT capture register of capture channel CAP_MATCH 0x108 @@ -48869,7 +45856,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH2 + MATCH2 SCT match value register of match channels CAP_MATCH 0x108 @@ -48895,7 +45882,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP3 + CAP3 SCT capture register of capture channel CAP_MATCH 0x10C @@ -48921,7 +45908,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH3 + MATCH3 SCT match value register of match channels CAP_MATCH 0x10C @@ -48947,7 +45934,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP4 + CAP4 SCT capture register of capture channel CAP_MATCH 0x110 @@ -48973,7 +45960,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH4 + MATCH4 SCT match value register of match channels CAP_MATCH 0x110 @@ -48999,7 +45986,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP5 + CAP5 SCT capture register of capture channel CAP_MATCH 0x114 @@ -49025,7 +46012,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH5 + MATCH5 SCT match value register of match channels CAP_MATCH 0x114 @@ -49051,7 +46038,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP6 + CAP6 SCT capture register of capture channel CAP_MATCH 0x118 @@ -49077,7 +46064,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH6 + MATCH6 SCT match value register of match channels CAP_MATCH 0x118 @@ -49103,7 +46090,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP7 + CAP7 SCT capture register of capture channel CAP_MATCH 0x11C @@ -49129,7 +46116,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH7 + MATCH7 SCT match value register of match channels CAP_MATCH 0x11C @@ -49155,7 +46142,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP8 + CAP8 SCT capture register of capture channel CAP_MATCH 0x120 @@ -49181,7 +46168,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH8 + MATCH8 SCT match value register of match channels CAP_MATCH 0x120 @@ -49207,7 +46194,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP9 + CAP9 SCT capture register of capture channel CAP_MATCH 0x124 @@ -49233,7 +46220,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH9 + MATCH9 SCT match value register of match channels CAP_MATCH 0x124 @@ -49259,7 +46246,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP10 + CAP10 SCT capture register of capture channel CAP_MATCH 0x128 @@ -49285,7 +46272,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH10 + MATCH10 SCT match value register of match channels CAP_MATCH 0x128 @@ -49311,7 +46298,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP11 + CAP11 SCT capture register of capture channel CAP_MATCH 0x12C @@ -49337,7 +46324,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH11 + MATCH11 SCT match value register of match channels CAP_MATCH 0x12C @@ -49363,7 +46350,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP12 + CAP12 SCT capture register of capture channel CAP_MATCH 0x130 @@ -49389,7 +46376,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH12 + MATCH12 SCT match value register of match channels CAP_MATCH 0x130 @@ -49415,7 +46402,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP13 + CAP13 SCT capture register of capture channel CAP_MATCH 0x134 @@ -49441,7 +46428,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH13 + MATCH13 SCT match value register of match channels CAP_MATCH 0x134 @@ -49467,7 +46454,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP14 + CAP14 SCT capture register of capture channel CAP_MATCH 0x138 @@ -49493,7 +46480,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH14 + MATCH14 SCT match value register of match channels CAP_MATCH 0x138 @@ -49519,7 +46506,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAP15 + CAP15 SCT capture register of capture channel CAP_MATCH 0x13C @@ -49545,7 +46532,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCH15 + MATCH15 SCT match value register of match channels CAP_MATCH 0x13C @@ -49571,7 +46558,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL0 + CAPCTRL0 SCT capture control register CAPCTRL_MATCHREL 0x200 @@ -49597,7 +46584,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL0 + MATCHREL0 SCT match reload value register CAPCTRL_MATCHREL 0x200 @@ -49623,7 +46610,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL1 + CAPCTRL1 SCT capture control register CAPCTRL_MATCHREL 0x204 @@ -49649,7 +46636,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL1 + MATCHREL1 SCT match reload value register CAPCTRL_MATCHREL 0x204 @@ -49675,7 +46662,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL2 + CAPCTRL2 SCT capture control register CAPCTRL_MATCHREL 0x208 @@ -49701,7 +46688,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL2 + MATCHREL2 SCT match reload value register CAPCTRL_MATCHREL 0x208 @@ -49727,7 +46714,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL3 + CAPCTRL3 SCT capture control register CAPCTRL_MATCHREL 0x20C @@ -49753,7 +46740,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL3 + MATCHREL3 SCT match reload value register CAPCTRL_MATCHREL 0x20C @@ -49779,7 +46766,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL4 + CAPCTRL4 SCT capture control register CAPCTRL_MATCHREL 0x210 @@ -49805,7 +46792,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL4 + MATCHREL4 SCT match reload value register CAPCTRL_MATCHREL 0x210 @@ -49831,7 +46818,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL5 + CAPCTRL5 SCT capture control register CAPCTRL_MATCHREL 0x214 @@ -49857,7 +46844,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL5 + MATCHREL5 SCT match reload value register CAPCTRL_MATCHREL 0x214 @@ -49883,7 +46870,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL6 + CAPCTRL6 SCT capture control register CAPCTRL_MATCHREL 0x218 @@ -49909,7 +46896,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL6 + MATCHREL6 SCT match reload value register CAPCTRL_MATCHREL 0x218 @@ -49935,7 +46922,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL7 + CAPCTRL7 SCT capture control register CAPCTRL_MATCHREL 0x21C @@ -49961,7 +46948,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL7 + MATCHREL7 SCT match reload value register CAPCTRL_MATCHREL 0x21C @@ -49987,7 +46974,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL8 + CAPCTRL8 SCT capture control register CAPCTRL_MATCHREL 0x220 @@ -50013,7 +47000,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL8 + MATCHREL8 SCT match reload value register CAPCTRL_MATCHREL 0x220 @@ -50039,7 +47026,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL9 + CAPCTRL9 SCT capture control register CAPCTRL_MATCHREL 0x224 @@ -50065,7 +47052,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL9 + MATCHREL9 SCT match reload value register CAPCTRL_MATCHREL 0x224 @@ -50091,7 +47078,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL10 + CAPCTRL10 SCT capture control register CAPCTRL_MATCHREL 0x228 @@ -50117,7 +47104,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL10 + MATCHREL10 SCT match reload value register CAPCTRL_MATCHREL 0x228 @@ -50143,7 +47130,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL11 + CAPCTRL11 SCT capture control register CAPCTRL_MATCHREL 0x22C @@ -50169,7 +47156,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL11 + MATCHREL11 SCT match reload value register CAPCTRL_MATCHREL 0x22C @@ -50195,7 +47182,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL12 + CAPCTRL12 SCT capture control register CAPCTRL_MATCHREL 0x230 @@ -50221,7 +47208,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL12 + MATCHREL12 SCT match reload value register CAPCTRL_MATCHREL 0x230 @@ -50247,7 +47234,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL13 + CAPCTRL13 SCT capture control register CAPCTRL_MATCHREL 0x234 @@ -50273,7 +47260,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL13 + MATCHREL13 SCT match reload value register CAPCTRL_MATCHREL 0x234 @@ -50299,7 +47286,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL14 + CAPCTRL14 SCT capture control register CAPCTRL_MATCHREL 0x238 @@ -50325,7 +47312,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL14 + MATCHREL14 SCT match reload value register CAPCTRL_MATCHREL 0x238 @@ -50351,7 +47338,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTCAPCTRL15 + CAPCTRL15 SCT capture control register CAPCTRL_MATCHREL 0x23C @@ -50377,7 +47364,7 @@ SPDX-License-Identifier: BSD-3-Clause - SCTMATCHREL15 + MATCHREL15 SCT match reload value register CAPCTRL_MATCHREL 0x23C @@ -50405,11 +47392,11 @@ SPDX-License-Identifier: BSD-3-Clause 16 0x8 - EVENT[%s] + EV[%s] no description available 0x300 - STATE + EV_STATE SCT event state register 0 0 32 @@ -50427,7 +47414,7 @@ SPDX-License-Identifier: BSD-3-Clause - CTRL + EV_CTRL SCT event control register 0 0x4 32 @@ -50612,7 +47599,7 @@ SPDX-License-Identifier: BSD-3-Clause no description available 0x500 - SET + OUT_SET SCT output 0 set register 0 32 @@ -50630,7 +47617,7 @@ SPDX-License-Identifier: BSD-3-Clause - CLR + OUT_CLR SCT output 0 clear register 0x4 32 @@ -50828,21 +47815,21 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - Aperture - no description available + APERTURE + size aperture for the register port on the bus (APB or AHB). 0 8 read-only - Minor_Rev + MINOR_REV Minor revision of module implementation. 8 4 read-only - Major_Rev + MAJOR_REV Major revision of module implementation. 12 4 @@ -52244,9 +49231,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 - 0x4 - SLVADR[%s] + SLVADR0 Slave address register. 0x848 32 @@ -52301,6 +49286,117 @@ SPDX-License-Identifier: BSD-3-Clause + + SLVADR1 + Slave address register. + 0x84C + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + + + SLVADR2 + Slave address register. + 0x850 + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + + + SLVADR3 + Slave address register. + 0x854 + 32 + read-write + 0x1 + 0xFF + + + SADISABLE + Slave Address n Disable. + 0 + 1 + read-write + + + ENABLED + Enabled. Slave Address n is enabled. + 0 + + + DISABLED + Ignored Slave Address n is ignored. + 0x1 + + + + + SLVADR + Slave Address. Seven bit slave address that is compared to received addresses if enabled. + 1 + 7 + read-write + + + SLVQUAL0 Slave Qualification for address 0. @@ -52583,95 +49679,6 @@ SPDX-License-Identifier: BSD-3-Clause 14 - - 3 - 0x20 - SECCHANNEL[%s] - no description available - 0 - - PCFG1 - Configuration register 1 for channel pair - 0xC20 - 32 - read-write - 0 - 0x401 - - - PAIRENABLE - Enable for this channel pair.. - 0 - 1 - read-write - - - ONECHANNEL - Single channel mode. - 10 - 1 - read-write - - - - - PCFG2 - Configuration register 2 for channel pair - 0xC24 - 32 - read-write - 0 - 0x1FF0000 - - - POSITION - Data Position. - 16 - 9 - read-write - - - - - PSTAT - Status register for channel pair - 0xC28 - 32 - read-write - 0 - 0xF - - - BUSY - Busy status for this channel pair. - 0 - 1 - read-write - - - SLVFRMERR - Save Frame Error flag. - 1 - 1 - read-write - - - LR - Left/Right indication. - 2 - 1 - read-write - - - DATAPAUSED - Data Paused status flag. - 3 - 1 - read-only - - - - CFG1 Configuration register 1 for the primary channel pair. @@ -52863,25 +49870,6 @@ SPDX-License-Identifier: BSD-3-Clause - - PDMDATA - PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC55xx, this bit applies only to Flexcomm 6,7. - 11 - 1 - read-write - - - NORMAL - Normal operation, data is transferred to or from the Flexcomm FIFO. - 0 - - - DMIC_SUBSYSTEM - The data source is the D-Mic subsystem. When PDMDATA = 1, only the primary channel pair can be used in this Flexcomm. If ONECHANNEL = 1, only the PDM left data is used. the WS rate must match the Fs (sample rate) of the D-Mic decimator. A rate mismatch will at some point cause the I2S to overrun or underrun. - 0x1 - - - SCK_POL SCK polarity. @@ -53241,25 +50229,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - POPDBG - Pop FIFO for debug reads. - 18 - 1 - read-write - - - DO_NOT_POP - Debug reads of the FIFO do not pop the FIFO. - 0 - - - POP - A debug read will cause the FIFO to pop. - 0x1 - - - @@ -53679,6 +50648,24 @@ SPDX-License-Identifier: BSD-3-Clause + + FIFOSIZE + FIFO size register + 0xE48 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOSIZE + Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + 0 + 5 + read-only + + + ID I2S Module identification @@ -53689,21 +50676,21 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - Aperture + APERTURE Aperture: encoded as (aperture size/4K) -1, so 0x00 means a 4K aperture. 0 8 read-only - Minor_Rev + MINOR_REV Minor revision of module implementation, starting at 0. 8 4 read-only - Major_Rev + MAJOR_REV Major revision of module implementation, starting at 0. 12 4 @@ -54429,25 +51416,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - POPDBG - Pop FIFO for debug reads. - 18 - 1 - read-write - - - DO_NOT_POP - Debug reads of the FIFO do not pop the FIFO. - 0 - - - POP - A debug read will cause the FIFO to pop. - 0x1 - - - @@ -54764,7 +51732,7 @@ SPDX-License-Identifier: BSD-3-Clause FIFO write data. 0xE20 32 - read-write + write-only 0 0 @@ -55023,13 +51991,31 @@ SPDX-License-Identifier: BSD-3-Clause + + FIFOSIZE + FIFO size register + 0xE48 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOSIZE + Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + 0 + 5 + read-only + + + ID Peripheral identification register. 0xFFC 32 read-only - 0 + 0xE0201200 0xFFFFFFFF @@ -56193,25 +53179,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - POPDBG - Pop FIFO for debug reads. - 18 - 1 - read-write - - - DO_NOT_POP - Debug reads of the FIFO do not pop the FIFO. - 0 - - - POP - A debug read will cause the FIFO to pop. - 0x1 - - - @@ -56528,7 +53495,7 @@ SPDX-License-Identifier: BSD-3-Clause FIFO write data. 0xE20 32 - read-write + write-only 0 0 @@ -56619,6 +53586,24 @@ SPDX-License-Identifier: BSD-3-Clause + + FIFOSIZE + FIFO size register + 0xE48 + 32 + read-write + 0x8 + 0xFFFFFFFF + + + FIFOSIZE + Provides the size of the FIFO for software. The size of the SPI FIFO is 8 entries. + 0 + 5 + read-only + + + ID Peripheral identification register. @@ -56872,16 +53857,15 @@ SPDX-License-Identifier: BSD-3-Clause GPIO General Purpose I/O (GPIO) GPIO - GPIO 0x4008C000 0 - 0x2490 + 0x2488 registers - 4 + 2 0x20 B[%s] no description available @@ -56908,7 +53892,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x80 W[%s] no description available @@ -56935,7 +53919,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 DIR[%s] Direction registers for all port GPIO pins @@ -56955,7 +53939,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 MASK[%s] Mask register for all port GPIO pins @@ -56975,7 +53959,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 PIN[%s] Port pin register for all port GPIO pins @@ -56995,7 +53979,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 MPIN[%s] Masked port register for all port GPIO pins @@ -57015,7 +53999,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 SET[%s] Write: Set register for port. Read: output bits for port @@ -57035,7 +54019,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 CLR[%s] Clear port for all port GPIO pins @@ -57055,7 +54039,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 NOT[%s] Toggle port for all port GPIO pins @@ -57075,7 +54059,7 @@ SPDX-License-Identifier: BSD-3-Clause - 4 + 2 0x4 DIRSET[%s] Set pin direction bits for port @@ -57089,13 +54073,13 @@ SPDX-License-Identifier: BSD-3-Clause DIRSETP Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. 0 - 29 + 32 write-only - 4 + 2 0x4 DIRCLR[%s] Clear pin direction bits for port @@ -57109,13 +54093,13 @@ SPDX-License-Identifier: BSD-3-Clause DIRCLRP Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. 0 - 29 + 32 write-only - 4 + 2 0x4 DIRNOT[%s] Toggle pin direction bits for port @@ -57129,24 +54113,13 @@ SPDX-License-Identifier: BSD-3-Clause DIRNOTP Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. 0 - 29 + 32 write-only - - SECGPIO - General Purpose I/O (GPIO) - GPIO - 0x400A8000 - - 0 - 0x2490 - registers - - USBHSD USB1 High-speed Device Controller @@ -57154,13 +54127,9 @@ SPDX-License-Identifier: BSD-3-Clause 0x40094000 0 - 0x40 + 0x38 registers - - USB1_UTMI - 46 - USB1 47 @@ -57207,13 +54176,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - FORCE_VBUS - If this bit is set to 1, the VBUS voltage indicators from the PHY are overruled. - 10 - 1 - read-write - LPM_SUP LPM Supported:. @@ -57314,10 +54276,42 @@ SPDX-License-Identifier: BSD-3-Clause PHY_TEST_MODE - This field is written by firmware to put the PHY into a test mode as defined by the USB2. + This field is written by firmware to put the PHY into a test mode as defined by the USB2.0 specification. 29 3 read-write + + + DISABLE + Test mode disabled. + 0 + + + TEST_J + Test_J. + 0x1 + + + TEST_K + Test_K. + 0x2 + + + TEST_SE0_NAK + Test_SE0_NAK. + 0x3 + + + TEST_PACKET + Test_Packet. + 0x4 + + + TEST_FORCE_ENABLE + Test_Force_Enable. + 0x5 + + @@ -57345,14 +54339,14 @@ SPDX-License-Identifier: BSD-3-Clause read-only - Minrev + MINREV Minor revision. 16 8 read-only - Majrev + MAJREV Major revision. 24 8 @@ -57680,59 +54674,6 @@ SPDX-License-Identifier: BSD-3-Clause - - ULPIDEBUG - UTMI/ULPI debug register - 0x3C - 32 - read-write - 0 - 0x83FFFFFF - - - PHY_ADDR - ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface. - 0 - 8 - read-write - - - PHY_WDATA - UTMI+ mode: Reserved. - 8 - 8 - read-write - - - PHY_RDATA - UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+. - 16 - 8 - read-write - - - PHY_RW - UTMI+ mode: Reserved. - 24 - 1 - read-write - - - PHY_ACCESS - Software writes this bit to one to start a read or write operation. - 25 - 1 - read-write - - - PHY_MODE - This bit indicates if the interface between the controller is UTMI+ or ULPI. - 31 - 1 - read-write - - - @@ -59328,9 +56269,9 @@ SPDX-License-Identifier: BSD-3-Clause - DGBMAILBOX + DBGMAILBOX MCU Debugger Mailbox - DGBMAILBOX + DBGMAILBOX 0x4009C000 0 @@ -68423,7 +65364,7 @@ SPDX-License-Identifier: BSD-3-Clause The content of this register is updated by HC after a periodic ED is processed. 4 28 - read-write + read-only @@ -68513,7 +65454,7 @@ SPDX-License-Identifier: BSD-3-Clause DoneHead When a TD is completed, HC writes the content of HcDoneHead to the NextTD field of the TD. 4 28 - read-write + read-only @@ -68563,14 +65504,14 @@ SPDX-License-Identifier: BSD-3-Clause FrameRemaining This counter is decremented at each bit time. 0 14 - read-write + read-only FRT FrameRemainingToggle This bit is loaded from the FrameIntervalToggle field of HcFmInterval whenever FrameRemaining reaches 0. 31 1 - read-write + read-only @@ -68588,7 +65529,7 @@ SPDX-License-Identifier: BSD-3-Clause FrameNumber This is incremented when HcFmRemaining is re-loaded. 0 16 - read-write + read-only @@ -68905,10 +65846,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x54 registers - - USB1_UTMI - 46 - USB1 47 @@ -68975,24 +65912,6 @@ SPDX-License-Identifier: BSD-3-Clause - - HCCPARAMS - Host Controller Capability Parameters - 0x8 - 32 - read-only - 0x20006 - 0xFFFFFFFF - - - LPMC - Link Power Management Capability. - 17 - 1 - read-only - - - FLADJ_FRINDEX Frame Length Adjustment @@ -69019,7 +65938,7 @@ SPDX-License-Identifier: BSD-3-Clause - ATL_PTD_BASE_ADDR + ATLPTD Memory base address where ATL PTD0 is stored 0x10 32 @@ -69044,7 +65963,7 @@ SPDX-License-Identifier: BSD-3-Clause - ISO_PTD_BASE_ADDR + ISOPTD Memory base address where ISO PTD0 is stored 0x14 32 @@ -69069,7 +65988,7 @@ SPDX-License-Identifier: BSD-3-Clause - INT_PTD_BASE_ADDR + INTPTD Memory base address where INT PTD0 is stored 0x18 32 @@ -69094,7 +66013,7 @@ SPDX-License-Identifier: BSD-3-Clause - DATA_PAYLOAD_BASE_ADDR + DATAPAYLOAD Memory base address that indicates the start of the data payload buffers 0x1C 32 @@ -69169,20 +66088,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - HIRD - Host-Initiated Resume Duration. - 24 - 4 - read-write - - - LPM_RWU - bRemoteWake field. - 28 - 1 - read-write - @@ -69363,13 +66268,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - SUS_L1 - Suspend using L1 0b = Suspend using L2 1b = Suspend using L1 When this bit is set to a 1 and a non-zero value is specified in the Device Address field, the host controller will generate an LPM Token to enter the L1 state whenever software writes a one to the Suspend bit, as well as L1 exit timing during any device or host-initiated resume. - 9 - 1 - read-write - LS Line Status: This field reflects the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. @@ -69412,24 +66310,10 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - SUS_STAT - These two bits are used by software to determine whether the most recent L1 suspend request was successful: 00b: Success-state transition was successful (ACK) 01b: Not Yet - Device was unable to enter the L1 state at this time (NYET) 10b: Not supported - Device does not support the L1 state (STALL) 11b: Timeout/Error - Device failed to respond or an error occurred. - 23 - 2 - read-write - - - DEV_ADD - Device Address for LPM tokens. - 25 - 7 - read-write - - ATL_PTD_DONE_MAP + ATLPTDD Done map for each ATL PTD 0x30 32 @@ -69447,7 +66331,7 @@ SPDX-License-Identifier: BSD-3-Clause - ATL_PTD_SKIP_MAP + ATLPTDS Skip map for each ATL PTD 0x34 32 @@ -69465,7 +66349,7 @@ SPDX-License-Identifier: BSD-3-Clause - ISO_PTD_DONE_MAP + ISOPTDD Done map for each ISO PTD 0x38 32 @@ -69483,7 +66367,7 @@ SPDX-License-Identifier: BSD-3-Clause - ISO_PTD_SKIP_MAP + ISOPTDS Skip map for each ISO PTD 0x3C 32 @@ -69501,7 +66385,7 @@ SPDX-License-Identifier: BSD-3-Clause - INT_PTD_DONE_MAP + INTPTDD Done map for each INT PTD 0x40 32 @@ -69519,7 +66403,7 @@ SPDX-License-Identifier: BSD-3-Clause - INT_PTD_SKIP_MAP + INTPTDS Skip map for each INT PTD 0x44 32 @@ -69537,7 +66421,7 @@ SPDX-License-Identifier: BSD-3-Clause - LAST_PTD_INUSE + LASTPTD Marks the last PTD in the list for ISO, INT and ATL 0x48 32 @@ -69568,59 +66452,6 @@ SPDX-License-Identifier: BSD-3-Clause - - UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY - 0x4C - 32 - read-write - 0 - 0x83FFFFFF - - - PHY_ADDR - UTMI+ mode: Bits 3:0 are used to control VControl signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used as the address when doing a register access over the ULPI interface. - 0 - 8 - read-write - - - PHY_WDATA - UTMI+ mode: Reserved. - 8 - 8 - read-write - - - PHY_RDATA - UTMI+ mode: Bits 7:0 contains the value returned by the VStatus signal on Vendor Interface of UTMI+ ULPI mode: Bits 7:0 are used for the read data when reading a value to a ULPI PHY register. - 16 - 8 - read-write - - - PHY_RW - UTMI+ mode: Reserved. - 24 - 1 - read-write - - - PHY_ACCESS - Software writes this bit to one to start a read or write operation. - 25 - 1 - read-write - - - PHY_MODE - This bit indicates if the interface between the controller is UTMI+ or ULPI 0b: UTMI+ 1b: ULPI If the hardware supports both modes, this bit is RW by SW. - 31 - 1 - read-write - - - PORTMODE Controls the port if it is attached to the host block or the device block @@ -69630,20 +66461,6 @@ SPDX-License-Identifier: BSD-3-Clause 0x40000 0xD0101 - - ID0 - Port 0 ID pin value. - 0 - 1 - read-write - - - ID0_EN - Port 0 ID pin pull-up enable. - 8 - 1 - read-write - DEV_ENABLE If this bit is set to one, one of the ports will behave as a USB device. @@ -69686,12 +66503,12 @@ SPDX-License-Identifier: BSD-3-Clause CTRL - Is control register to enable and operate Hash and Crypto + Control register to enable and operate Hash and Crypto 0 32 read-write 0 - 0x1317 + 0x3317 Mode @@ -69715,11 +66532,6 @@ SPDX-License-Identifier: BSD-3-Clause SHA2-256 is enabled 0x2 - - SHA2_512 - SHA2-512 is enabled (if available) - 0x3 - AES AES if available (see also CRYPTCFG register for more controls) @@ -69730,16 +66542,6 @@ SPDX-License-Identifier: BSD-3-Clause ICB-AES if available (see also CRYPTCFG register for more controls) 0x5 - - SALSA20 - Salsa20/20 if available (including XSalsa - see also CRYPTCFG register) - 0x6 - - - CHACHA20 - ChaCha20 if available (see also CRYPTCFG register for more controls) - 0x7 - @@ -69747,7 +66549,7 @@ SPDX-License-Identifier: BSD-3-Clause Written with 1 when starting a new Hash/Crypto. It self clears. Note that the WAITING Status bit will clear for a cycle during the initialization from New=1. 4 1 - read-write + write-only START @@ -69827,7 +66629,7 @@ SPDX-License-Identifier: BSD-3-Clause - DIGEST_aka_OUTDATA + DIGEST For Hash, if 1 then a DIGEST is ready and waiting and there is no active next block already started. For Cryptographic uses, this will be set for each block processed, indicating OUTDATA (and OUTDATA2 if larger output) contains the next value to read out. This is cleared when any data is written, when New is written, for Cryptographic uses when the last word is read out, or when the block is disabled. 1 1 @@ -70026,7 +66828,7 @@ SPDX-License-Identifier: BSD-3-Clause MASTER - no description available + Enables mastering. 0 1 read-write @@ -70111,7 +66913,7 @@ SPDX-License-Identifier: BSD-3-Clause 8 0x4 - OUTDATA0[%s] + DIGEST0[%s] no description available 0x40 32 @@ -70120,7 +66922,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - DIGEST_OUTPUT + DIGEST One word of the Digest or output. Note that only 1st 4 are populated for AES and 1st 5 are populated for SHA1. 0 32 @@ -70128,26 +66930,6 @@ SPDX-License-Identifier: BSD-3-Clause - - 8 - 0x4 - OUTDATA1[%s] - no description available - 0x60 - 32 - read-only - 0 - 0xFFFFFFFF - - - OUTPUT - One word of the 2nd half of the output when used. - 0 - 32 - read-only - - - CRYPTCFG Crypto settings for AES and Salsa and ChaCha @@ -70217,7 +66999,7 @@ SPDX-License-Identifier: BSD-3-Clause read-write - AESDECRYPT_0 + ENCRYPT Encrypt 0 @@ -70241,7 +67023,7 @@ SPDX-License-Identifier: BSD-3-Clause 0 - AESSECRET_1 + HIDDEN_WAY Secret key provided in hidden way by HW 0x1 @@ -70285,13 +67067,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-write - - XSALSA - Is 1 if XSalsa 128b NONCE to be used vs. 64b - 17 - 1 - read-write - ICBSZ This sets the ICB size between 32 and 128 bits, using the following rules. Note that the counter is assumed to occupy the low order bits of the IV. @@ -70382,13 +67157,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-only - - SHA512 - 1 if SHA2-512 included - 5 - 1 - read-only - AES 1 if AES 128 included @@ -70410,20 +67178,6 @@ SPDX-License-Identifier: BSD-3-Clause 1 read-only - - SALSA - 1 if Salsa included - 9 - 1 - read-only - - - CHACHA - 1 if ChaCha included - 10 - 1 - read-only - ICB 1 if ICB over AES included @@ -70502,6 +67256,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x84 registers + + CASER + 55 + CTRL0 @@ -70535,7 +67293,7 @@ SPDX-License-Identifier: BSD-3-Clause ABOFF Word or DWord Offset of AB values, with B at [2]=0 and A at [2]=1 as far as the code sees (normally will be an interleaved bank so only sequential to AHB). Word offset only allowed if 32 bit operation. Ideally not in the same RAM as the CD values if 4-up 2 - 1 + 11 read-write @@ -71085,6 +67843,10 @@ SPDX-License-Identifier: BSD-3-Clause 0x260 registers + + PQ + 57 + OUTBASE @@ -71677,6 +68439,1351 @@ SPDX-License-Identifier: BSD-3-Clause + + SECGPIO + General Purpose I/O (GPIO) + GPIO + 0x400A8000 + + 0 + 0x2484 + registers + + + + B0_0 + Byte pin registers for all port GPIO pins + 0 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_1 + Byte pin registers for all port GPIO pins + 0x1 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_2 + Byte pin registers for all port GPIO pins + 0x2 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_3 + Byte pin registers for all port GPIO pins + 0x3 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_4 + Byte pin registers for all port GPIO pins + 0x4 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_5 + Byte pin registers for all port GPIO pins + 0x5 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_6 + Byte pin registers for all port GPIO pins + 0x6 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_7 + Byte pin registers for all port GPIO pins + 0x7 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_8 + Byte pin registers for all port GPIO pins + 0x8 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_9 + Byte pin registers for all port GPIO pins + 0x9 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_10 + Byte pin registers for all port GPIO pins + 0xA + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_11 + Byte pin registers for all port GPIO pins + 0xB + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_12 + Byte pin registers for all port GPIO pins + 0xC + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_13 + Byte pin registers for all port GPIO pins + 0xD + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_14 + Byte pin registers for all port GPIO pins + 0xE + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_15 + Byte pin registers for all port GPIO pins + 0xF + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_16 + Byte pin registers for all port GPIO pins + 0x10 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_17 + Byte pin registers for all port GPIO pins + 0x11 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_18 + Byte pin registers for all port GPIO pins + 0x12 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_19 + Byte pin registers for all port GPIO pins + 0x13 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_20 + Byte pin registers for all port GPIO pins + 0x14 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_21 + Byte pin registers for all port GPIO pins + 0x15 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_22 + Byte pin registers for all port GPIO pins + 0x16 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_23 + Byte pin registers for all port GPIO pins + 0x17 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_24 + Byte pin registers for all port GPIO pins + 0x18 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_25 + Byte pin registers for all port GPIO pins + 0x19 + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_26 + Byte pin registers for all port GPIO pins + 0x1A + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_27 + Byte pin registers for all port GPIO pins + 0x1B + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_28 + Byte pin registers for all port GPIO pins + 0x1C + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_29 + Byte pin registers for all port GPIO pins + 0x1D + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_30 + Byte pin registers for all port GPIO pins + 0x1E + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + B0_31 + Byte pin registers for all port GPIO pins + 0x1F + 8 + read-write + 0 + 0x1 + + + PBYTE + Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, except that pins configured as analog I/O always read as 0. One register for each port pin. Supported pins depends on the specific device and package. Write: loads the pin's output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 1 + read-write + + + + + W0_0 + Word pin registers for all port GPIO pins + 0x1000 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_1 + Word pin registers for all port GPIO pins + 0x1004 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_2 + Word pin registers for all port GPIO pins + 0x1008 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_3 + Word pin registers for all port GPIO pins + 0x100C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_4 + Word pin registers for all port GPIO pins + 0x1010 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_5 + Word pin registers for all port GPIO pins + 0x1014 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_6 + Word pin registers for all port GPIO pins + 0x1018 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_7 + Word pin registers for all port GPIO pins + 0x101C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_8 + Word pin registers for all port GPIO pins + 0x1020 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_9 + Word pin registers for all port GPIO pins + 0x1024 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_10 + Word pin registers for all port GPIO pins + 0x1028 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_11 + Word pin registers for all port GPIO pins + 0x102C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_12 + Word pin registers for all port GPIO pins + 0x1030 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_13 + Word pin registers for all port GPIO pins + 0x1034 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_14 + Word pin registers for all port GPIO pins + 0x1038 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_15 + Word pin registers for all port GPIO pins + 0x103C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_16 + Word pin registers for all port GPIO pins + 0x1040 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_17 + Word pin registers for all port GPIO pins + 0x1044 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_18 + Word pin registers for all port GPIO pins + 0x1048 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_19 + Word pin registers for all port GPIO pins + 0x104C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_20 + Word pin registers for all port GPIO pins + 0x1050 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_21 + Word pin registers for all port GPIO pins + 0x1054 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_22 + Word pin registers for all port GPIO pins + 0x1058 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_23 + Word pin registers for all port GPIO pins + 0x105C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_24 + Word pin registers for all port GPIO pins + 0x1060 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_25 + Word pin registers for all port GPIO pins + 0x1064 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_26 + Word pin registers for all port GPIO pins + 0x1068 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_27 + Word pin registers for all port GPIO pins + 0x106C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_28 + Word pin registers for all port GPIO pins + 0x1070 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_29 + Word pin registers for all port GPIO pins + 0x1074 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_30 + Word pin registers for all port GPIO pins + 0x1078 + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + W0_31 + Word pin registers for all port GPIO pins + 0x107C + 32 + read-write + 0 + 0xFFFFFFFF + + + PWORD + Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be read. Writing any value other than 0 will set the output bit. One register for each port pin. Supported pins depends on the specific device and package. + 0 + 32 + read-write + + + + + DIR0 + Direction registers for all port GPIO pins + 0x2000 + 32 + read-write + 0 + 0xFFFFFFFF + + + DIRP + Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = input. 1 = output. + 0 + 32 + read-write + + + + + MASK0 + Mask register for all port GPIO pins + 0x2080 + 32 + read-write + 0 + 0xFFFFFFFF + + + MASKP + Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package.0 = Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit not affected. + 0 + 32 + read-write + + + + + PIN0 + Port pin register for all port GPIO pins + 0x2100 + 32 + read-write + 0 + 0xFFFFFFFF + + + PORT + Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 1 = Read: pin is high; write: set output bit. + 0 + 32 + read-write + + + + + MPIN0 + Masked port register for all port GPIO pins + 0x2180 + 32 + read-write + 0 + 0xFFFFFFFF + + + MPORTP + Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit if the corresponding bit in the MASK register is 0. + 0 + 32 + read-write + + + + + SET0 + Write: Set register for port. Read: output bits for port + 0x2200 + 32 + read-write + 0 + 0xFFFFFFFF + + + SETP + Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output bit; write: set output bit. + 0 + 32 + read-write + + + + + CLR0 + Clear port for all port GPIO pins + 0x2280 + 32 + write-only + 0 + 0 + + + CLRP + Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear output bit. + 0 + 32 + write-only + + + + + NOT0 + Toggle port for all port GPIO pins + 0x2300 + 32 + write-only + 0 + 0 + + + NOTP + Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle output bit. + 0 + 32 + write-only + + + + + DIRSET0 + Set pin direction bits for port + 0x2380 + 32 + write-only + 0 + 0 + + + DIRSETP + Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Set direction bit. + 0 + 32 + write-only + + + + + DIRCLR0 + Clear pin direction bits for port + 0x2400 + 32 + write-only + 0 + 0 + + + DIRCLRP + Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = No operation. 1 = Clear direction bit. + 0 + 32 + write-only + + + + + DIRNOT0 + Toggle pin direction bits for port + 0x2480 + 32 + write-only + 0 + 0 + + + DIRNOTP + Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = no operation. 1 = Toggle direction bit. + 0 + 32 + write-only + + + + + AHB_SECURE_CTRL AHB secure controller @@ -74277,7 +72384,7 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - RAM0_RULE + RAM1_RULE Security access rules for the whole RAM1 : 0x2001_0000 - 0x2001_FFFF" name="0 0 2 @@ -76265,8 +74372,8 @@ SPDX-License-Identifier: BSD-3-Clause - PMUX_RULE - Peripherals mux + INPUTMUX_RULE + Peripheral input multiplexing 24 2 read-write @@ -76489,46 +74596,8 @@ SPDX-License-Identifier: BSD-3-Clause - - EFUSE_RULE - eFUSE (One Time Programmable) memory controller - 20 - 2 - read-write - - - ENUM_NS_NP - Non-secure and Non-priviledge user access allowed. - 0 - - - ENUM_NS_P - Non-secure and Privilege access allowed. - 0x1 - - - ENUM_S_NP - Secure and Non-priviledge user access allowed. - 0x2 - - - ENUM_S_P - Secure and Priviledge user access allowed. - 0x3 - - - - - SEC_CTRL_APB_BRIDGE0_MEM_CTRL3 - Security access rules for APB Bridge 0 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 0 sectors in total. - 0x10C - 32 - write-only - 0 - 0xFFFFFFFF - SEC_CTRL_APB_BRIDGE1_MEM_CTRL0 Security access rules for APB Bridge 1 peripherals. Each APB bridge sector is 4 Kbytes. There are 32 APB Bridge 1 sectors in total. @@ -76891,7 +74960,7 @@ SPDX-License-Identifier: BSD-3-Clause - PUFF_RULE + PUF_RULE PUF 12 2 @@ -76951,7 +75020,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB0_0_SLAVE_RULE + SEC_CTRL_AHB_PORT8_SLAVE0_RULE Security access rules for AHB peripherals. 0x120 32 @@ -77107,7 +75176,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB0_1_SLAVE_RULE + SEC_CTRL_AHB_PORT8_SLAVE1_RULE Security access rules for AHB peripherals. 0x124 32 @@ -77263,7 +75332,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB1_0_SLAVE_RULE + SEC_CTRL_AHB_PORT9_SLAVE0_RULE Security access rules for AHB peripherals. 0x130 32 @@ -77390,7 +75459,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB1_1_SLAVE_RULE + SEC_CTRL_AHB_PORT9_SLAVE1_RULE Security access rules for AHB peripherals. 0x134 32 @@ -77517,7 +75586,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB2_0_SLAVE_RULE + SEC_CTRL_AHB_PORT10_SLAVE0_RULE Security access rules for AHB peripherals. 0x140 32 @@ -77672,7 +75741,7 @@ SPDX-License-Identifier: BSD-3-Clause PQ_RULE - Power Quad (CM33 processor hardware accelerator) + Power Quad (CPU0 processor hardware accelerator) 24 2 read-write @@ -77731,7 +75800,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB2_1_SLAVE_RULE + SEC_CTRL_AHB_PORT10_SLAVE1_RULE Security access rules for AHB peripherals. 0x144 32 @@ -77800,7 +75869,7 @@ SPDX-License-Identifier: BSD-3-Clause - SEC_CTRL_AHB2_0_MEM_RULE + SEC_CTRL_AHB_SEC_CTRL_MEM_RULE Security access rules for AHB_SEC_CTRL_AHB. 0x150 32 @@ -78097,7 +76166,7 @@ SPDX-License-Identifier: BSD-3-Clause 12 0x4 sec_vio_addr[%s] - most recent security violation address for AHB layer n + most recent security violation address for AHB port n 0xE00 32 read-only @@ -78106,7 +76175,7 @@ SPDX-License-Identifier: BSD-3-Clause SEC_VIO_ADDR - security violation address for AHB layer + security violation address for AHB port 0 32 read-only @@ -78117,7 +76186,7 @@ SPDX-License-Identifier: BSD-3-Clause 12 0x4 sec_vio_misc_info[%s] - most recent security violation miscellaneous information for AHB layer n + most recent security violation miscellaneous information for AHB port n 0xE80 32 read-only @@ -78246,7 +76315,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID0 - violation information valid flag for AHB layer 0. Write 1 to clear. + violation information valid flag for AHB port 0. Write 1 to clear. 0 1 read-write @@ -78265,7 +76334,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID1 - violation information valid flag for AHB layer 1. Write 1 to clear. + violation information valid flag for AHB port 1. Write 1 to clear. 1 1 read-write @@ -78284,7 +76353,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID2 - violation information valid flag for AHB layer 2. Write 1 to clear. + violation information valid flag for AHB port 2. Write 1 to clear. 2 1 read-write @@ -78303,7 +76372,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID3 - violation information valid flag for AHB layer 3. Write 1 to clear. + violation information valid flag for AHB port 3. Write 1 to clear. 3 1 read-write @@ -78322,7 +76391,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID4 - violation information valid flag for AHB layer 4. Write 1 to clear. + violation information valid flag for AHB port 4. Write 1 to clear. 4 1 read-write @@ -78341,7 +76410,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID5 - violation information valid flag for AHB layer 5. Write 1 to clear. + violation information valid flag for AHB port 5. Write 1 to clear. 5 1 read-write @@ -78360,7 +76429,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID6 - violation information valid flag for AHB layer 6. Write 1 to clear. + violation information valid flag for AHB port 6. Write 1 to clear. 6 1 read-write @@ -78379,7 +76448,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID7 - violation information valid flag for AHB layer 7. Write 1 to clear. + violation information valid flag for AHB port 7. Write 1 to clear. 7 1 read-write @@ -78398,7 +76467,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID8 - violation information valid flag for AHB layer 8. Write 1 to clear. + violation information valid flag for AHB port 8. Write 1 to clear. 8 1 read-write @@ -78417,7 +76486,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID9 - violation information valid flag for AHB layer 9. Write 1 to clear. + violation information valid flag for AHB port 9. Write 1 to clear. 9 1 read-write @@ -78436,7 +76505,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID10 - violation information valid flag for AHB layer 10. Write 1 to clear. + violation information valid flag for AHB port 10. Write 1 to clear. 10 1 read-write @@ -78455,7 +76524,7 @@ SPDX-License-Identifier: BSD-3-Clause VIO_INFO_VALID11 - violation information valid flag for AHB layer 11. Write 1 to clear. + violation information valid flag for AHB port 11. Write 1 to clear. 11 1 read-write @@ -80178,7 +78247,7 @@ SPDX-License-Identifier: BSD-3-Clause - ACMP_CAPT0_IRQ + ACMP_IRQ Analog Comparator interrupt. 24 1 @@ -80255,7 +78324,7 @@ SPDX-License-Identifier: BSD-3-Clause USB0_IRQ - USB High Speed Controller interrupt. + USB Full Speed Controller interrupt. 28 1 read-write @@ -80607,8 +78676,8 @@ SPDX-License-Identifier: BSD-3-Clause - USB1_UTMI_IRQ - USB High Speed Controller UTMI interrupt. + USB1_PHY_IRQ + USB High Speed PHY Controller interrupt. 14 1 read-write @@ -80797,7 +78866,7 @@ SPDX-License-Identifier: BSD-3-Clause - QDDKEY_IRQ + PUFKEY_IRQ PUF interrupt. 24 1 @@ -80971,8 +79040,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - MCM33C - Micro-CM33 (CPU1) Code bus. + CPU1C + Micro-Cortex M33 (CPU1) Code bus. 4 2 read-write @@ -81000,8 +79069,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33S - Micro-CM33 (CPU1) System bus. + CPU1S + Micro-Cortex M33 (CPU1) System bus. 6 2 read-write @@ -81262,8 +79331,8 @@ SPDX-License-Identifier: BSD-3-Clause 0xFFFFFFFF - MCM33C - Micro-CM33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33C) + CPU1C + Micro-Cortex M33 (CPU1) Code bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1C) 4 2 read-write @@ -81291,8 +79360,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33S - Micro-CM33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.MCM33S) + CPU1S + Micro-Cortex M33 (CPU1) System bus. Must be equal to NOT(MASTER_SEC_LEVEL.CPU1S) 6 2 read-write @@ -81544,8 +79613,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_LOCK_REG - Miscalleneous control signals for in CM33 (CPU0) + CPU0_LOCK_REG + Miscalleneous control signals for in Cortex M33 (CPU0) 0xFEC 32 read-write @@ -81554,7 +79623,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_NS_VTOR - CM33 (CPU0) VTOR_NS register write-lock. + Cortex M33 (CPU0) VTOR_NS register write-lock. 0 2 read-write @@ -81573,7 +79642,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_NS_MPU - CM33 (CPU0) non-secure MPU register write-lock. + Cortex M33 (CPU0) non-secure MPU register write-lock. 2 2 read-write @@ -81592,7 +79661,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_S_VTAIRCR - CM33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. + Cortex M33 (CPU0) VTOR_S, AIRCR.PRIS, IRCR.BFHFNMINS registers write-lock. 4 2 read-write @@ -81611,7 +79680,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_S_MPU - CM33 (CPU0) Secure MPU registers write-lock. + Cortex M33 (CPU0) Secure MPU registers write-lock. 6 2 read-write @@ -81630,7 +79699,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_SAU - CM33 (CPU0) SAU registers write-lock. + Cortex M33 (CPU0) SAU registers write-lock. 8 2 read-write @@ -81648,8 +79717,8 @@ SPDX-License-Identifier: BSD-3-Clause - CM33_LOCK_REG_LOCK - CM33_LOCK_REG write-lock. + CPU0_LOCK_REG_LOCK + CPU0_LOCK_REG write-lock. 30 2 read-write @@ -81669,8 +79738,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_LOCK_REG - Miscalleneous control signals for in micro-CM33 (CPU1) + CPU1_LOCK_REG + Miscalleneous control signals for in micro-Cortex M33 (CPU1) 0xFF0 32 read-write @@ -81679,7 +79748,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_NS_VTOR - micro-CM33 (CPU1) VTOR_NS register write-lock. + micro-Cortex M33 (CPU1) VTOR_NS register write-lock. 0 2 read-write @@ -81698,7 +79767,7 @@ SPDX-License-Identifier: BSD-3-Clause LOCK_NS_MPU - micro-CM33 (CPU1) non-secure MPU register write-lock. + micro-Cortex M33 (CPU1) non-secure MPU register write-lock. 2 2 read-write @@ -81716,8 +79785,8 @@ SPDX-License-Identifier: BSD-3-Clause - MCM33_LOCK_REG_LOCK - MCM33_LOCK_REG write-lock. + CPU1_LOCK_REG_LOCK + CPU1_LOCK_REG write-lock. 30 2 read-write @@ -81747,7 +79816,7 @@ SPDX-License-Identifier: BSD-3-Clause WRITE_LOCK - write lock. + Write lock. 0 2 read-write @@ -81766,7 +79835,7 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. + Enable secure check for AHB matrix. 2 2 read-write @@ -81785,7 +79854,7 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. + Enable secure privilege check for AHB matrix. 4 2 read-write @@ -81804,7 +79873,7 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. + Enable non-secure privilege check for AHB matrix. 6 2 read-write @@ -81910,7 +79979,7 @@ SPDX-License-Identifier: BSD-3-Clause WRITE_LOCK - write lock. + Write lock. 0 2 read-write @@ -81929,14 +79998,14 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_SECURE_CHECKING - AHB bus matrix enable secure check. + Enable secure check for AHB matrix. 2 2 read-write ENABLE - Restricted mode. + Enabled (restricted mode) 0x1 @@ -81948,14 +80017,14 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_S_PRIV_CHECK - AHB bus matrix enable secure privilege check. + Enable secure privilege check for AHB matrix. 4 2 read-write ENABLE - Restricted mode. + Enabled (restricted mode) 0x1 @@ -81967,14 +80036,14 @@ SPDX-License-Identifier: BSD-3-Clause ENABLE_NS_PRIV_CHECK - AHB bus matrix enable non-secure privilege check. + Enable non-secure privilege check for AHB matrix. 6 2 read-write ENABLE - Restricted mode. + Enabled (restricted mode) 0x1 @@ -86227,7 +84296,7 @@ SPDX-License-Identifier: BSD-3-Clause Software Trigger Interrupt Register 0xE00 32 - read-write + write-only 0 0xFFFFFFFF @@ -87061,7 +85130,7 @@ SPDX-License-Identifier: BSD-3-Clause - SAU_CTRL + CTRL Security Attribution Unit Control Register 0xD0 32 @@ -87110,7 +85179,7 @@ SPDX-License-Identifier: BSD-3-Clause - SAU_TYPE + TYPE Security Attribution Unit Type Register 0xD4 32 @@ -87128,7 +85197,7 @@ SPDX-License-Identifier: BSD-3-Clause - SAU_RNR + RNR Security Attribution Unit Region Number Register 0xD8 32 @@ -87146,7 +85215,7 @@ SPDX-License-Identifier: BSD-3-Clause - SAU_RBAR + RBAR Security Attribution Unit Region Base Address Register 0xDC 32 @@ -87164,7 +85233,7 @@ SPDX-License-Identifier: BSD-3-Clause - SAU_RLAR + RLAR Security Attribution Unit Region Limit Address Register 0xE0 32 diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h index 91cf68b234..2e189cda53 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/LPC55S69_cm33_core1_features.h @@ -1,13 +1,13 @@ /* ** ################################################################### -** Version: rev. 1.0, 2018-08-22 -** Build: b190418 +** Version: rev. 1.1, 2019-05-16 +** Build: b220303 ** ** Abstract: ** Chip specific module features. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2019 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -18,6 +18,8 @@ ** Revisions: ** - rev. 1.0 (2018-08-22) ** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM ** ** ################################################################### */ @@ -73,7 +75,7 @@ #define FSL_FEATURE_SOC_POWERQUAD_COUNT (1) /* @brief PUF availability on the SoC. */ #define FSL_FEATURE_SOC_PUF_COUNT (1) -/* @brief RNG1 availability on the SoC. */ +/* @brief LPC_RNG1 availability on the SoC. */ #define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1) /* @brief RTC availability on the SoC. */ #define FSL_FEATURE_SOC_RTC_COUNT (1) @@ -136,18 +138,66 @@ #define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0) /* @brief Has offset trim (register OFSTRIM). */ #define FSL_FEATURE_LPADC_HAS_OFSTRIM (1) +/* @brief Has Trigger status register. */ +#define FSL_FEATURE_LPADC_HAS_TSTAT (1) +/* @brief Has power select (bitfield CFG[PWRSEL]). */ +#define FSL_FEATURE_LPADC_HAS_CFG_PWRSEL (1) +/* @brief Has alternate channel B scale (bitfield CMDLn[ALTB_CSCALE]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_CSCALE (0) +/* @brief Has alternate channel B select enable (bitfield CMDLn[ALTBEN]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTBEN (0) +/* @brief Has alternate channel input (bitfield CMDLn[ALTB_ADCH]). */ +#define FSL_FEATURE_LPADC_HAS_CMDL_ALTB_ADCH (0) +/* @brief Has offset calibration mode (bitfield CTRL[CALOFSMODE]). */ +#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE (0) +/* @brief Conversion averaged bitfiled width. */ +#define FSL_FEATURE_LPADC_CONVERSIONS_AVERAGED_BITFIELD_WIDTH (3) +/* @brief Has internal temperature sensor. */ +#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1) +/* @brief Temperature sensor parameter A (slope). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (744.6f) +/* @brief Temperature sensor parameter B (offset). */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (313.7f) +/* @brief Temperature sensor parameter Alpha. */ +#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (11.5f) +/* @brief the buffer size of temperature sensor. */ +#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (4U) + +/* ANALOGCTRL module features */ + +/* @brief Has PLL_USB_OUT_BIT_FIELD bitfile in XO32M_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD (1) +/* @brief Has XO32M_ADC_CLK_MODE bitfile in DUMMY_CTRL reigster. */ +#define FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD (0) +/* @brief Has auxiliary bias(register AUX_BIAS). */ +#define FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG (1) /* CASPER module features */ /* @brief Base address of the CASPER dedicated RAM */ #define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000) -/* @brief Interleaving of the CASPER dedicated RAM */ +/* @brief SW interleaving of the CASPER dedicated RAM */ #define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1) +/* @brief CASPER dedicated RAM offset */ +#define FSL_FEATURE_CASPER_RAM_OFFSET (0xE) + +/* CTIMER module features */ + +/* @brief CTIMER has no capture channel. */ +#define FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE (0) +/* @brief CTIMER has no capture 2 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT (0) +/* @brief CTIMER capture 3 interrupt. */ +#define FSL_FEATURE_CTIMER_HAS_IR_CR3INT (1) +/* @brief Has CTIMER CCR_CAP2 (register bits CCR[CAP2RE][CAP2FE][CAP2I]. */ +#define FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 (0) +/* @brief Has CTIMER CCR_CAP3 (register bits CCR[CAP3RE][CAP3FE][CAP3I]). */ +#define FSL_FEATURE_CTIMER_HAS_CCR_CAP3 (1) /* DMA module features */ /* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (23) /* @brief Align size of DMA descriptor */ #define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512) /* @brief DMA head link descriptor table align size */ @@ -155,6 +205,72 @@ /* FLEXCOMM module features */ +/* @brief FLEXCOMM0 USART INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_USART_INDEX (0) +/* @brief FLEXCOMM0 SPI INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX (0) +/* @brief FLEXCOMM0 I2C INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX (0) +/* @brief FLEXCOMM0 I2S INDEX 0 */ +#define FSL_FEATURE_FLEXCOMM0_I2S_INDEX (0) +/* @brief FLEXCOMM1 USART INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_USART_INDEX (1) +/* @brief FLEXCOMM1 SPI INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX (1) +/* @brief FLEXCOMM1 I2C INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX (1) +/* @brief FLEXCOMM1 I2S INDEX 1 */ +#define FSL_FEATURE_FLEXCOMM1_I2S_INDEX (1) +/* @brief FLEXCOMM2 USART INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_USART_INDEX (2) +/* @brief FLEXCOMM2 SPI INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX (2) +/* @brief FLEXCOMM2 I2C INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX (2) +/* @brief FLEXCOMM2 I2S INDEX 2 */ +#define FSL_FEATURE_FLEXCOMM2_I2S_INDEX (2) +/* @brief FLEXCOMM3 USART INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_USART_INDEX (3) +/* @brief FLEXCOMM3 SPI INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX (3) +/* @brief FLEXCOMM3 I2C INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX (3) +/* @brief FLEXCOMM3 I2S INDEX 3 */ +#define FSL_FEATURE_FLEXCOMM3_I2S_INDEX (3) +/* @brief FLEXCOMM4 USART INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_USART_INDEX (4) +/* @brief FLEXCOMM4 SPI INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX (4) +/* @brief FLEXCOMM4 I2C INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX (4) +/* @brief FLEXCOMM4 I2S INDEX 4 */ +#define FSL_FEATURE_FLEXCOMM4_I2S_INDEX (4) +/* @brief FLEXCOMM5 USART INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_USART_INDEX (5) +/* @brief FLEXCOMM5 SPI INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX (5) +/* @brief FLEXCOMM5 I2C INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX (5) +/* @brief FLEXCOMM5 I2S INDEX 5 */ +#define FSL_FEATURE_FLEXCOMM5_I2S_INDEX (5) +/* @brief FLEXCOMM6 USART INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_USART_INDEX (6) +/* @brief FLEXCOMM6 SPI INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX (6) +/* @brief FLEXCOMM6 I2C INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX (6) +/* @brief FLEXCOMM6 I2S INDEX 6 */ +#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX (6) +/* @brief FLEXCOMM7 USART INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_USART_INDEX (7) +/* @brief FLEXCOMM7 SPI INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX (7) +/* @brief FLEXCOMM7 I2C INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX (7) +/* @brief FLEXCOMM7 I2S INDEX 7 */ +#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX (7) +/* @brief FLEXCOMM8 SPI(HS_SPI) INDEX 8 */ +#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX (8) /* @brief I2S has DMIC interconnection */ #define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) (0) @@ -166,9 +282,9 @@ /* I2S module features */ /* @brief I2S support dual channel transfer. */ -#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1) -/* @brief I2S has DMIC interconnection. */ -#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) +#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (0) +/* @brief I2S has DMIC interconnection */ +#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION (0) /* IOCON module features */ @@ -190,10 +306,22 @@ /* @brief Number of connected outputs */ #define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) +/* PLU module features */ + +/* @brief Has WAKEINT_CTRL register. */ +#define FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG (1) + +/* PMC module features */ + +/* @brief UTICK does not support PD configure. */ +#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* @brief WDT OSC does not support PD configure. */ +#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) + /* POWERLIB module features */ -/* @brief LPC55XX's Powerlib API is different with other LPC series devices. */ -#define FSL_FEATURE_POWERLIB_LPC55XX_EXTEND (1) +/* @brief Powerlib API is different with other LPC series devices. */ +#define FSL_FEATURE_POWERLIB_EXTEND (1) /* POWERQUAD module features */ @@ -207,6 +335,10 @@ /* @brief the shift status value */ #define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1) +/* RTC module features */ + +/* No feature definitions */ + /* SCT module features */ /* @brief Number of events */ @@ -221,13 +353,13 @@ /* SDIF module features */ /* @brief FIFO depth, every location is a WORD */ -#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) +#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) /* @brief Max DMA buffer size */ -#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) +#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) /* @brief Max source clock in HZ */ -#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) +#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) /* @brief support 2 cards */ -#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) +#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1) /* SECPINT module features */ @@ -236,18 +368,22 @@ /* SYSCON module features */ -/* @brief Pointer to ROM IAP entry functions */ -#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) /* @brief Flash page size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512) /* @brief Flash sector size in bytes */ #define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) /* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592) +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (645120) /* @brief Has Power Down mode */ #define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1) /* @brief CCM_ANALOG availability on the SoC. */ #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1) +/* @brief Starter register discontinuous. */ +#define FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS (1) + +/* SYSCTL1 module features */ + +/* No feature definitions */ /* USB module features */ @@ -289,17 +425,23 @@ /* @brief USBHSH version */ #define FSL_FEATURE_USBHSH_VERSION (300) -/* UTICK module features */ +/* USBPHY module features */ -/* @brief UTICK does not support PD configure. */ -#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1) +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM (0x00004000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBPHY_USB_RAM_BASE_ADDRESS (0x40100000) +/* @brief USBHSD version */ +#define FSL_FEATURE_USBPHY_VERSION (300) +/* @brief Number of the endpoint in USB HS */ +#define FSL_FEATURE_USBPHY_EP_NUM (6) /* WWDT module features */ +/* @brief Has no RESET register. */ +#define FSL_FEATURE_WWDT_HAS_NO_RESET (1) /* @brief WWDT does not support oscillator lock. */ #define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1) -/* @brief WWDT does not support power down configure */ -#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1) #endif /* _LPC55S69_cm33_core1_FEATURES_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf index e9c4063e4a..67cd92d97b 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash.scf @@ -2,18 +2,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181008 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b210928 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -47,7 +48,7 @@ #define m_text_size 0x00071E00 #define m_core1_image_start 0x00072000 -#define m_core1_image_size 0x00026000 +#define m_core1_image_size 0x0002B800 #if (defined(__use_shmem__)) #define m_data_start 0x20000000 @@ -66,12 +67,12 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) + * (.isr_vector,+FIRST) } ER_m_text m_text_start FIXED m_text_size { ; load address = execution address * (InRoot$$Sections) - * (+RO) + .ANY (+RO) } #if (defined(__use_shmem__)) @@ -81,7 +82,7 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz #endif RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - * (+RW +ZI) + .ANY (+RW +ZI) } ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up } @@ -89,16 +90,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz } RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) + * (*m_usb_bdt) } RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) + * (*m_usb_global) } } LR_CORE1_IMAGE m_core1_image_start { CORE1_REGION m_core1_image_start m_core1_image_size { - *(M0CODE) + * (.core1_code) } } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf index 22b5cf6b6c..d3162db09f 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_ns.scf @@ -2,18 +2,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190923 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2019 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -42,18 +43,18 @@ /* The first 64kB of FLASH is used as secure memory. The rest of FLASH memory is non-secure memory. */ #define m_interrupts_start 0x00010000 -#define m_interrupts_size 0x00000140 +#define m_interrupts_size 0x00000200 -#define m_text_start 0x00010140 -#define m_text_size 0x00061EC0 +#define m_text_start 0x00010200 +#define m_text_size 0x00061E00 #define m_core1_image_start 0x00072000 -#define m_core1_image_size 0x00026000 +#define m_core1_image_size 0x0002B800 /* The first 32kB of data RAM is used as secure memory. The rest of data RAM memory is non-secure memory. */ #if (defined(__use_shmem__)) #define m_data_start 0x20008000 - #define m_data_size 0x00028000 + #define m_data_size 0x00029000 #define m_rpmsg_sh_mem_start 0x20031800 #define m_rpmsg_sh_mem_size 0x00001800 #else @@ -65,10 +66,15 @@ #define m_usb_sram_size 0x00004000 -LR_m_text m_text_start m_text_size { ; load region size_region +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address * (InRoot$$Sections) - * (+RO) + .ANY (+RO) } #if (defined(__use_shmem__)) @@ -78,34 +84,24 @@ LR_m_text m_text_start m_text_size { ; load region size_region #endif RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - * (+RW +ZI) + .ANY (+RW +ZI) } ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up } ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down } -} -LR_m_interrupts m_interrupts_start m_interrupts_size { - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (*m_usb_bdt) } -} -LR_m_usb_bdt m_usb_sram_start usb_bdt_size { - ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) - } -} - -LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) { - ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (*m_usb_global) } } LR_CORE1_IMAGE m_core1_image_start { CORE1_REGION m_core1_image_start m_core1_image_size { - *(M0CODE) + * (.core1_code) } } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf index 94fca1816f..fe8d3f6b9d 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_flash_s.scf @@ -2,18 +2,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190923 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2019 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -42,13 +43,13 @@ /* Only the first 64kB of flash is used as secure memory. */ #define m_interrupts_start 0x10000000 -#define m_interrupts_size 0x00000140 +#define m_interrupts_size 0x00000200 -#define m_text_start 0x10000140 -#define m_text_size 0x0000FCC0 +#define m_text_start 0x10000200 +#define m_text_size 0x0000FC00 #define m_core1_image_start 0x10072000 -#define m_core1_image_size 0x00026000 +#define m_core1_image_size 0x0002B800 /* Only first 32kB of data RAM is used as secure memory. */ #if (defined(__use_shmem__)) @@ -70,10 +71,15 @@ #define m_usb_sram_size 0x00004000 -LR_m_text m_text_start m_text_size { ; load region size_region +LR_m_text m_interrupts_start m_interrupts_size+m_text_size+m_veneer_table_size { ; load region size_region + + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (.isr_vector,+FIRST) + } + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address * (InRoot$$Sections) - * (+RO) + .ANY (+RO) } #if (defined(__use_shmem__)) @@ -83,40 +89,28 @@ LR_m_text m_text_start m_text_size { ; load region size_region #endif RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - * (+RW +ZI) + .ANY (+RW +ZI) } ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up } ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down } -} -LR_m_interrupts m_interrupts_start m_interrupts_size { - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } -} - -LR_m_veneer_table m_veneer_table_start m_veneer_table_size { - ER_m_veneer_table m_veneer_table_start m_veneer_table_size {; veneer table + ER_m_veneer_table m_veneer_table_start FIXED m_veneer_table_size {; veneer table *(Veneer$$CMSE) } -} -LR_m_usb_bdt m_usb_sram_start usb_bdt_size { - ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { + * (*m_usb_bdt) } -} -LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) { - ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { + * (*m_usb_global) } } LR_CORE1_IMAGE m_core1_image_start { CORE1_REGION m_core1_image_start m_core1_image_size { - *(M0CODE) + * (.core1_code) } } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf index c5a71fc764..797443048a 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core0_ram.scf @@ -2,18 +2,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181008 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b200722 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -47,7 +48,7 @@ #define m_text_size 0x00007E00 #define m_core1_image_start 0x20033000 -#define m_core1_image_size 0x00008800 +#define m_core1_image_size 0x0000C800 #if (defined(__use_shmem__)) #define m_data_start 0x20000000 @@ -66,12 +67,12 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) + * (.isr_vector,+FIRST) } ER_m_text m_text_start FIXED m_text_size { ; load address = execution address * (InRoot$$Sections) - * (+RO) + .ANY (+RO) } #if (defined(__use_shmem__)) @@ -81,7 +82,7 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz #endif RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - * (+RW +ZI) + .ANY (+RW +ZI) } ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up } @@ -89,16 +90,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz } RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) + * (*m_usb_bdt) } RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) + * (*m_usb_global) } } LR_CORE1_IMAGE m_core1_image_start { CORE1_REGION m_core1_image_start m_core1_image_size { - *(M0CODE) + * (.core1_code) } } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf index 74e2a93843..b54320ccb7 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_flash.scf @@ -2,18 +2,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181008 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b210928 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -44,7 +45,7 @@ #define m_interrupts_size 0x00000200 #define m_text_start 0x00072200 -#define m_text_size 0x00025E00 +#define m_text_size 0x0002B600 #define m_data_start 0x20033000 @@ -62,17 +63,17 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) + * (.isr_vector,+FIRST) } ER_m_text m_text_start FIXED m_text_size { ; load address = execution address * (InRoot$$Sections) - * (+RO) + .ANY (+RO) } RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - * (+RW +ZI) + .ANY (+RW +ZI) } ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up } @@ -80,11 +81,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz } RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) + * (*m_usb_bdt) } RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) + * (*m_usb_global) + } + #if (defined(__use_shmem__)) + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG + * (rpmsg_sh_mem_section) + } + #endif } -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf index 73393e3d63..f3ba53c93a 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram.scf @@ -2,18 +2,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181008 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b200722 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -44,11 +45,11 @@ #define m_interrupts_size 0x00000200 #define m_text_start 0x20033200 -#define m_text_size 0x0000B600 +#define m_text_size 0x0000C600 -#define m_data_start 0x2003E800 -#define m_data_size 0x00005800 +#define m_data_start 0x2003F800 +#define m_data_size 0x00004800 #if (defined(__use_shmem__)) #define m_rpmsg_sh_mem_start 0x20031800 @@ -62,17 +63,17 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) + * (.isr_vector,+FIRST) } ER_m_text m_text_start FIXED m_text_size { ; load address = execution address * (InRoot$$Sections) - * (+RO) + .ANY (+RO) } RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - * (+RW +ZI) + .ANY (+RW +ZI) } ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up } @@ -80,16 +81,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz } RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) + * (*m_usb_bdt) } RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) + * (*m_usb_global) } -#if (defined(__use_shmem__)) + #if (defined(__use_shmem__)) RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG * (rpmsg_sh_mem_section) } -#endif -} + #endif + } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf index a9f6e92dce..d67fdecb6e 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55S69_cm33_core1_ram_s.scf @@ -2,18 +2,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181008 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190923 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2019 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -44,11 +45,11 @@ #define m_interrupts_size 0x00000200 #define m_text_start 0x30033200 -#define m_text_size 0x0000B600 +#define m_text_size 0x0000C600 -#define m_data_start 0x3003E800 -#define m_data_size 0x00005800 +#define m_data_start 0x3003F800 +#define m_data_size 0x00004800 #if (defined(__use_shmem__)) #define m_rpmsg_sh_mem_start 0x30031800 @@ -62,17 +63,17 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) + * (.isr_vector,+FIRST) } ER_m_text m_text_start FIXED m_text_size { ; load address = execution address * (InRoot$$Sections) - * (+RO) + .ANY (+RO) } RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - * (+RW +ZI) + .ANY (+RW +ZI) } ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up } @@ -80,11 +81,11 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz } RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) + * (*m_usb_bdt) } RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) + * (*m_usb_global) } #if (defined(__use_shmem__)) RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55XX_640.FLM b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/LPC55XX_640.FLM index 9313a011e436135bc1ab9b95ce56ab8ca48321ed..167a941d8f2c6b7acf8264bf6a5687f5e163e773 100644 GIT binary patch literal 22132 zcmeHP3w%`7nLl^#+<9a|-h^Nf2aK8`84}*|&`e%1BtTxgY|_bO<|Y|4nHgs$K-AS} zp<7$E)>qw%%G$bitKEu17patVtF^k+!cS|}wMtu;vQ}FN6yu|^|L@#;?mP@u+x54< z?Q-?p@B4qRbIy0pJ@?GLH(XQS)F4R`6NibFGl6!tF?IrlnVB+|IT`8lSS}mhRXu8E zBcqJfoIK?7jIq4xQRaLSm`xiQ8_pXU+k!HjzwG3DmrGsMC(T`_rjd64=&O>{wfgAx zYST0+T0NT0V=S*@N4v*ZdC5M>IlPxSqsu71rdxTEnHokz{^fNeqjnRU_T!W49Cq~b zr1iexUCyIXx3Jf2$!hfp7Gp;{49nqNj)qjr<#mt#kzI4=KG?Tm~qi?;#%5D43t1EAKc<=D8tc)1!=#_>iWA4$D**_d*OI{hv%DZ+)^{7ooj$}67 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a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s index 9bd615d07e..9a573e0c1d 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0.s @@ -1,732 +1,801 @@ -;/***************************************************************************** -; * @file: startup_LPC55S69_cm33_core0.s -; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the -; * LPC55S69_cm33_core0 -; * @version: 1.1 -; * @date: 2019-5-16 -; * -; * Copyright 1997-2016 Freescale Semiconductor, Inc. -; * Copyright 2016-2019 NXP -; * All rights reserved. -; * -; * SPDX-License-Identifier: BSD-3-Clause -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD SecureFault_Handler - DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD Reserved39_IRQHandler ; Reserved interrupt - DCD ACMP_IRQHandler ; ACMP interrupts - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts - DCD Reserved55_IRQHandler ; Reserved interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD SDIO_IRQHandler ; SD/MMC - DCD Reserved59_IRQHandler ; Reserved interrupt - DCD Reserved60_IRQHandler ; Reserved interrupt - DCD Reserved61_IRQHandler ; Reserved interrupt - DCD USB1_UTMI_IRQHandler ; USB1_UTMI - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt - DCD PLU_IRQHandler ; PLU interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt - DCD CASER_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD PQ_IRQHandler ; PQ interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) - - - AREA |.text|, CODE, READONLY - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| - - CPSID I ; Mask interrupts - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Base| - MSR MSPLIM, R0 - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler \ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SecureFault_Handler PROC - EXPORT SecureFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -WDT_BOD_IRQHandler\ - PROC - EXPORT WDT_BOD_IRQHandler [WEAK] - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - ENDP - -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -GINT0_IRQHandler\ - PROC - EXPORT GINT0_IRQHandler [WEAK] - LDR R0, =GINT0_DriverIRQHandler - BX R0 - ENDP - -GINT1_IRQHandler\ - PROC - EXPORT GINT1_IRQHandler [WEAK] - LDR R0, =GINT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT0_IRQHandler\ - PROC - EXPORT PIN_INT0_IRQHandler [WEAK] - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - ENDP - -PIN_INT1_IRQHandler\ - PROC - EXPORT PIN_INT1_IRQHandler [WEAK] - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT2_IRQHandler\ - PROC - EXPORT PIN_INT2_IRQHandler [WEAK] - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - ENDP - -PIN_INT3_IRQHandler\ - PROC - EXPORT PIN_INT3_IRQHandler [WEAK] - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - ENDP - -UTICK0_IRQHandler\ - PROC - EXPORT UTICK0_IRQHandler [WEAK] - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - ENDP - -MRT0_IRQHandler\ - PROC - EXPORT MRT0_IRQHandler [WEAK] - LDR R0, =MRT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER0_IRQHandler\ - PROC - EXPORT CTIMER0_IRQHandler [WEAK] - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - ENDP - -CTIMER1_IRQHandler\ - PROC - EXPORT CTIMER1_IRQHandler [WEAK] - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - ENDP - -SCT0_IRQHandler\ - PROC - EXPORT SCT0_IRQHandler [WEAK] - LDR R0, =SCT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER3_IRQHandler\ - PROC - EXPORT CTIMER3_IRQHandler [WEAK] - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM0_IRQHandler\ - PROC - EXPORT FLEXCOMM0_IRQHandler [WEAK] - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM1_IRQHandler\ - PROC - EXPORT FLEXCOMM1_IRQHandler [WEAK] - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM2_IRQHandler\ - PROC - EXPORT FLEXCOMM2_IRQHandler [WEAK] - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM3_IRQHandler\ - PROC - EXPORT FLEXCOMM3_IRQHandler [WEAK] - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM4_IRQHandler\ - PROC - EXPORT FLEXCOMM4_IRQHandler [WEAK] - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM5_IRQHandler\ - PROC - EXPORT FLEXCOMM5_IRQHandler [WEAK] - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM6_IRQHandler\ - PROC - EXPORT FLEXCOMM6_IRQHandler [WEAK] - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM7_IRQHandler\ - PROC - EXPORT FLEXCOMM7_IRQHandler [WEAK] - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - ENDP - -ADC0_IRQHandler\ - PROC - EXPORT ADC0_IRQHandler [WEAK] - LDR R0, =ADC0_DriverIRQHandler - BX R0 - ENDP - -Reserved39_IRQHandler\ - PROC - EXPORT Reserved39_IRQHandler [WEAK] - LDR R0, =Reserved39_DriverIRQHandler - BX R0 - ENDP - -ACMP_IRQHandler\ - PROC - EXPORT ACMP_IRQHandler [WEAK] - LDR R0, =ACMP_DriverIRQHandler - BX R0 - ENDP - -Reserved41_IRQHandler\ - PROC - EXPORT Reserved41_IRQHandler [WEAK] - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - ENDP - -Reserved42_IRQHandler\ - PROC - EXPORT Reserved42_IRQHandler [WEAK] - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - ENDP - -USB0_NEEDCLK_IRQHandler\ - PROC - EXPORT USB0_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -USB0_IRQHandler\ - PROC - EXPORT USB0_IRQHandler [WEAK] - LDR R0, =USB0_DriverIRQHandler - BX R0 - ENDP - -RTC_IRQHandler\ - PROC - EXPORT RTC_IRQHandler [WEAK] - LDR R0, =RTC_DriverIRQHandler - BX R0 - ENDP - -Reserved46_IRQHandler\ - PROC - EXPORT Reserved46_IRQHandler [WEAK] - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - ENDP - -MAILBOX_IRQHandler\ - PROC - EXPORT MAILBOX_IRQHandler [WEAK] - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 - ENDP - -PIN_INT4_IRQHandler\ - PROC - EXPORT PIN_INT4_IRQHandler [WEAK] - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - ENDP - -PIN_INT5_IRQHandler\ - PROC - EXPORT PIN_INT5_IRQHandler [WEAK] - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - ENDP - -PIN_INT6_IRQHandler\ - PROC - EXPORT PIN_INT6_IRQHandler [WEAK] - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - ENDP - -PIN_INT7_IRQHandler\ - PROC - EXPORT PIN_INT7_IRQHandler [WEAK] - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - ENDP - -CTIMER2_IRQHandler\ - PROC - EXPORT CTIMER2_IRQHandler [WEAK] - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - ENDP - -CTIMER4_IRQHandler\ - PROC - EXPORT CTIMER4_IRQHandler [WEAK] - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - ENDP - -OS_EVENT_IRQHandler\ - PROC - EXPORT OS_EVENT_IRQHandler [WEAK] - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - ENDP - -Reserved55_IRQHandler\ - PROC - EXPORT Reserved55_IRQHandler [WEAK] - LDR R0, =Reserved55_DriverIRQHandler - BX R0 - ENDP - -Reserved56_IRQHandler\ - PROC - EXPORT Reserved56_IRQHandler [WEAK] - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - ENDP - -Reserved57_IRQHandler\ - PROC - EXPORT Reserved57_IRQHandler [WEAK] - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - ENDP - -SDIO_IRQHandler\ - PROC - EXPORT SDIO_IRQHandler [WEAK] - LDR R0, =SDIO_DriverIRQHandler - BX R0 - ENDP - -Reserved59_IRQHandler\ - PROC - EXPORT Reserved59_IRQHandler [WEAK] - LDR R0, =Reserved59_DriverIRQHandler - BX R0 - ENDP - -Reserved60_IRQHandler\ - PROC - EXPORT Reserved60_IRQHandler [WEAK] - LDR R0, =Reserved60_DriverIRQHandler - BX R0 - ENDP - -Reserved61_IRQHandler\ - PROC - EXPORT Reserved61_IRQHandler [WEAK] - LDR R0, =Reserved61_DriverIRQHandler - BX R0 - ENDP - -USB1_UTMI_IRQHandler\ - PROC - EXPORT USB1_UTMI_IRQHandler [WEAK] - LDR R0, =USB1_UTMI_DriverIRQHandler - BX R0 - ENDP - -USB1_IRQHandler\ - PROC - EXPORT USB1_IRQHandler [WEAK] - LDR R0, =USB1_DriverIRQHandler - BX R0 - ENDP - -USB1_NEEDCLK_IRQHandler\ - PROC - EXPORT USB1_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -SEC_HYPERVISOR_CALL_IRQHandler\ - PROC - EXPORT SEC_HYPERVISOR_CALL_IRQHandler [WEAK] - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - ENDP - -SEC_GPIO_INT0_IRQ0_IRQHandler\ - PROC - EXPORT SEC_GPIO_INT0_IRQ0_IRQHandler [WEAK] - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - ENDP - -SEC_GPIO_INT0_IRQ1_IRQHandler\ - PROC - EXPORT SEC_GPIO_INT0_IRQ1_IRQHandler [WEAK] - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - ENDP - -PLU_IRQHandler\ - PROC - EXPORT PLU_IRQHandler [WEAK] - LDR R0, =PLU_DriverIRQHandler - BX R0 - ENDP - -SEC_VIO_IRQHandler\ - PROC - EXPORT SEC_VIO_IRQHandler [WEAK] - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - ENDP - -HASHCRYPT_IRQHandler\ - PROC - EXPORT HASHCRYPT_IRQHandler [WEAK] - LDR R0, =HASHCRYPT_DriverIRQHandler - BX R0 - ENDP - -CASER_IRQHandler\ - PROC - EXPORT CASER_IRQHandler [WEAK] - LDR R0, =CASER_DriverIRQHandler - BX R0 - ENDP - -PUF_IRQHandler\ - PROC - EXPORT PUF_IRQHandler [WEAK] - LDR R0, =PUF_DriverIRQHandler - BX R0 - ENDP - -PQ_IRQHandler\ - PROC - EXPORT PQ_IRQHandler [WEAK] - LDR R0, =PQ_DriverIRQHandler - BX R0 - ENDP - -DMA1_IRQHandler\ - PROC - EXPORT DMA1_IRQHandler [WEAK] - LDR R0, =DMA1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM8_IRQHandler\ - PROC - EXPORT FLEXCOMM8_IRQHandler [WEAK] - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 - ENDP - -Default_Handler PROC - EXPORT WDT_BOD_DriverIRQHandler [WEAK] - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT GINT0_DriverIRQHandler [WEAK] - EXPORT GINT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT0_DriverIRQHandler [WEAK] - EXPORT PIN_INT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT2_DriverIRQHandler [WEAK] - EXPORT PIN_INT3_DriverIRQHandler [WEAK] - EXPORT UTICK0_DriverIRQHandler [WEAK] - EXPORT MRT0_DriverIRQHandler [WEAK] - EXPORT CTIMER0_DriverIRQHandler [WEAK] - EXPORT CTIMER1_DriverIRQHandler [WEAK] - EXPORT SCT0_DriverIRQHandler [WEAK] - EXPORT CTIMER3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] - EXPORT ADC0_DriverIRQHandler [WEAK] - EXPORT Reserved39_DriverIRQHandler [WEAK] - EXPORT ACMP_DriverIRQHandler [WEAK] - EXPORT Reserved41_DriverIRQHandler [WEAK] - EXPORT Reserved42_DriverIRQHandler [WEAK] - EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT USB0_DriverIRQHandler [WEAK] - EXPORT RTC_DriverIRQHandler [WEAK] - EXPORT Reserved46_DriverIRQHandler [WEAK] - EXPORT MAILBOX_DriverIRQHandler [WEAK] - EXPORT PIN_INT4_DriverIRQHandler [WEAK] - EXPORT PIN_INT5_DriverIRQHandler [WEAK] - EXPORT PIN_INT6_DriverIRQHandler [WEAK] - EXPORT PIN_INT7_DriverIRQHandler [WEAK] - EXPORT CTIMER2_DriverIRQHandler [WEAK] - EXPORT CTIMER4_DriverIRQHandler [WEAK] - EXPORT OS_EVENT_DriverIRQHandler [WEAK] - EXPORT Reserved55_DriverIRQHandler [WEAK] - EXPORT Reserved56_DriverIRQHandler [WEAK] - EXPORT Reserved57_DriverIRQHandler [WEAK] - EXPORT SDIO_DriverIRQHandler [WEAK] - EXPORT Reserved59_DriverIRQHandler [WEAK] - EXPORT Reserved60_DriverIRQHandler [WEAK] - EXPORT Reserved61_DriverIRQHandler [WEAK] - EXPORT USB1_UTMI_DriverIRQHandler [WEAK] - EXPORT USB1_DriverIRQHandler [WEAK] - EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT SEC_HYPERVISOR_CALL_DriverIRQHandler [WEAK] - EXPORT SEC_GPIO_INT0_IRQ0_DriverIRQHandler [WEAK] - EXPORT SEC_GPIO_INT0_IRQ1_DriverIRQHandler [WEAK] - EXPORT PLU_DriverIRQHandler [WEAK] - EXPORT SEC_VIO_DriverIRQHandler [WEAK] - EXPORT HASHCRYPT_DriverIRQHandler [WEAK] - EXPORT CASER_DriverIRQHandler [WEAK] - EXPORT PUF_DriverIRQHandler [WEAK] - EXPORT PQ_DriverIRQHandler [WEAK] - EXPORT DMA1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM8_DriverIRQHandler [WEAK] - -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -Reserved39_DriverIRQHandler -ACMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -MAILBOX_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -Reserved55_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -SDIO_DriverIRQHandler -Reserved59_DriverIRQHandler -Reserved60_DriverIRQHandler -Reserved61_DriverIRQHandler -USB1_UTMI_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -PLU_DriverIRQHandler -SEC_VIO_DriverIRQHandler -HASHCRYPT_DriverIRQHandler -CASER_DriverIRQHandler -PUF_DriverIRQHandler -PQ_DriverIRQHandler -DMA1_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler - - B . - - ENDP - - - ALIGN - - - END - +/* --------------------------------------------------------------------------------------- + * @file: startup_LPC55S69_cm33_core0.s + * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core0 + * @version: 1.1 + * @date: 2019-5-16 + * ---------------------------------------------------------------------------------------*/ +/* + * Copyright 1997-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + .syntax unified + .arch armv8-m.main + .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ + + .section .isr_vector, "a" + .align 2 + .globl __Vectors + +__Vectors: + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + .long DMA0_IRQHandler /* DMA0 controller */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long ADC0_IRQHandler /* ADC0 */ + .long Reserved39_IRQHandler /* Reserved interrupt */ + .long ACMP_IRQHandler /* ACMP interrupts */ + .long Reserved41_IRQHandler /* Reserved interrupt */ + .long Reserved42_IRQHandler /* Reserved interrupt */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long Reserved46_IRQHandler /* Reserved interrupt */ + .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ + .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ + .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ + .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + .long Reserved55_IRQHandler /* Reserved interrupt */ + .long Reserved56_IRQHandler /* Reserved interrupt */ + .long Reserved57_IRQHandler /* Reserved interrupt */ + .long SDIO_IRQHandler /* SD/MMC */ + .long Reserved59_IRQHandler /* Reserved interrupt */ + .long Reserved60_IRQHandler /* Reserved interrupt */ + .long Reserved61_IRQHandler /* Reserved interrupt */ + .long USB1_PHY_IRQHandler /* USB1_PHY */ + .long USB1_IRQHandler /* USB1 interrupt */ + .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ + .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ + .long PLU_IRQHandler /* PLU interrupt */ + .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ + .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ + .long CASER_IRQHandler /* CASPER interrupt */ + .long PUF_IRQHandler /* PUF interrupt */ + .long PQ_IRQHandler /* PQ interrupt */ + .long DMA1_IRQHandler /* DMA1 interrupt */ + .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + .size __Vectors, . - __Vectors + + .text + .thumb + +/* Reset Handler */ + .thumb_func + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + ldr R0, =Image$$ARM_LIB_STACK$$ZI$$Base + msr msplim, R0 + ldr r0,=SystemInit + blx r0 + cpsie i /* Unmask interrupts */ + ldr r0,=__main + bx r0 + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved39_IRQHandler + .type Reserved39_IRQHandler, %function +Reserved39_IRQHandler: + ldr r0,=Reserved39_DriverIRQHandler + bx r0 + .size Reserved39_IRQHandler, . - Reserved39_IRQHandler + + .align 1 + .thumb_func + .weak ACMP_IRQHandler + .type ACMP_IRQHandler, %function +ACMP_IRQHandler: + ldr r0,=ACMP_DriverIRQHandler + bx r0 + .size ACMP_IRQHandler, . - ACMP_IRQHandler + + .align 1 + .thumb_func + .weak Reserved41_IRQHandler + .type Reserved41_IRQHandler, %function +Reserved41_IRQHandler: + ldr r0,=Reserved41_DriverIRQHandler + bx r0 + .size Reserved41_IRQHandler, . - Reserved41_IRQHandler + + .align 1 + .thumb_func + .weak Reserved42_IRQHandler + .type Reserved42_IRQHandler, %function +Reserved42_IRQHandler: + ldr r0,=Reserved42_DriverIRQHandler + bx r0 + .size Reserved42_IRQHandler, . - Reserved42_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak Reserved46_IRQHandler + .type Reserved46_IRQHandler, %function +Reserved46_IRQHandler: + ldr r0,=Reserved46_DriverIRQHandler + bx r0 + .size Reserved46_IRQHandler, . - Reserved46_IRQHandler + + .align 1 + .thumb_func + .weak MAILBOX_IRQHandler + .type MAILBOX_IRQHandler, %function +MAILBOX_IRQHandler: + ldr r0,=MAILBOX_DriverIRQHandler + bx r0 + .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT4_IRQHandler + .type PIN_INT4_IRQHandler, %function +PIN_INT4_IRQHandler: + ldr r0,=PIN_INT4_DriverIRQHandler + bx r0 + .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT5_IRQHandler + .type PIN_INT5_IRQHandler, %function +PIN_INT5_IRQHandler: + ldr r0,=PIN_INT5_DriverIRQHandler + bx r0 + .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT6_IRQHandler + .type PIN_INT6_IRQHandler, %function +PIN_INT6_IRQHandler: + ldr r0,=PIN_INT6_DriverIRQHandler + bx r0 + .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT7_IRQHandler + .type PIN_INT7_IRQHandler, %function +PIN_INT7_IRQHandler: + ldr r0,=PIN_INT7_DriverIRQHandler + bx r0 + .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved55_IRQHandler + .type Reserved55_IRQHandler, %function +Reserved55_IRQHandler: + ldr r0,=Reserved55_DriverIRQHandler + bx r0 + .size Reserved55_IRQHandler, . - Reserved55_IRQHandler + + .align 1 + .thumb_func + .weak Reserved56_IRQHandler + .type Reserved56_IRQHandler, %function +Reserved56_IRQHandler: + ldr r0,=Reserved56_DriverIRQHandler + bx r0 + .size Reserved56_IRQHandler, . - Reserved56_IRQHandler + + .align 1 + .thumb_func + .weak Reserved57_IRQHandler + .type Reserved57_IRQHandler, %function +Reserved57_IRQHandler: + ldr r0,=Reserved57_DriverIRQHandler + bx r0 + .size Reserved57_IRQHandler, . - Reserved57_IRQHandler + + .align 1 + .thumb_func + .weak SDIO_IRQHandler + .type SDIO_IRQHandler, %function +SDIO_IRQHandler: + ldr r0,=SDIO_DriverIRQHandler + bx r0 + .size SDIO_IRQHandler, . - SDIO_IRQHandler + + .align 1 + .thumb_func + .weak Reserved59_IRQHandler + .type Reserved59_IRQHandler, %function +Reserved59_IRQHandler: + ldr r0,=Reserved59_DriverIRQHandler + bx r0 + .size Reserved59_IRQHandler, . - Reserved59_IRQHandler + + .align 1 + .thumb_func + .weak Reserved60_IRQHandler + .type Reserved60_IRQHandler, %function +Reserved60_IRQHandler: + ldr r0,=Reserved60_DriverIRQHandler + bx r0 + .size Reserved60_IRQHandler, . - Reserved60_IRQHandler + + .align 1 + .thumb_func + .weak Reserved61_IRQHandler + .type Reserved61_IRQHandler, %function +Reserved61_IRQHandler: + ldr r0,=Reserved61_DriverIRQHandler + bx r0 + .size Reserved61_IRQHandler, . - Reserved61_IRQHandler + + .align 1 + .thumb_func + .weak USB1_PHY_IRQHandler + .type USB1_PHY_IRQHandler, %function +USB1_PHY_IRQHandler: + ldr r0,=USB1_PHY_DriverIRQHandler + bx r0 + .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler + + .align 1 + .thumb_func + .weak USB1_IRQHandler + .type USB1_IRQHandler, %function +USB1_IRQHandler: + ldr r0,=USB1_DriverIRQHandler + bx r0 + .size USB1_IRQHandler, . - USB1_IRQHandler + + .align 1 + .thumb_func + .weak USB1_NEEDCLK_IRQHandler + .type USB1_NEEDCLK_IRQHandler, %function +USB1_NEEDCLK_IRQHandler: + ldr r0,=USB1_NEEDCLK_DriverIRQHandler + bx r0 + .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ0_IRQHandler + .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function +SEC_GPIO_INT0_IRQ0_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ1_IRQHandler + .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function +SEC_GPIO_INT0_IRQ1_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak PLU_IRQHandler + .type PLU_IRQHandler, %function +PLU_IRQHandler: + ldr r0,=PLU_DriverIRQHandler + bx r0 + .size PLU_IRQHandler, . - PLU_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak HASHCRYPT_IRQHandler + .type HASHCRYPT_IRQHandler, %function +HASHCRYPT_IRQHandler: + ldr r0,=HASHCRYPT_DriverIRQHandler + bx r0 + .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler + + .align 1 + .thumb_func + .weak CASER_IRQHandler + .type CASER_IRQHandler, %function +CASER_IRQHandler: + ldr r0,=CASER_DriverIRQHandler + bx r0 + .size CASER_IRQHandler, . - CASER_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak PQ_IRQHandler + .type PQ_IRQHandler, %function +PQ_IRQHandler: + ldr r0,=PQ_DriverIRQHandler + bx r0 + .size PQ_IRQHandler, . - PQ_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM8_IRQHandler + .type FLEXCOMM8_IRQHandler, %function +FLEXCOMM8_IRQHandler: + ldr r0,=FLEXCOMM8_DriverIRQHandler + bx r0 + .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ + def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ + def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ + def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ + def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ + def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ + def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ + def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ + def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ + def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ + def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ + def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ + def_irq_handler USB0_DriverIRQHandler /* USB device */ + def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ + def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler MAILBOX_DriverIRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ + def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ + def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ + def_irq_handler OS_EVENT_DriverIRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */ + def_irq_handler Reserved59_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved60_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */ + def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */ + def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */ + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ + def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ + def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */ + def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ + def_irq_handler HASHCRYPT_DriverIRQHandler /* HASHCRYPT interrupt */ + def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */ + def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ + def_irq_handler PQ_DriverIRQHandler /* PQ interrupt */ + def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ + def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + + .end diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0_ns.s b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0_ns.s deleted file mode 100644 index 575e0dda6b..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core0_ns.s +++ /dev/null @@ -1,732 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC55S69_cm33_core0.s -; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the -; * LPC55S69_cm33_core0 -; * @version: 1.1 -; * @date: 2019-5-16 -; * -; * Copyright 1997-2016 Freescale Semiconductor, Inc. -; * Copyright 2016-2019 NXP -; * All rights reserved. -; * -; * SPDX-License-Identifier: BSD-3-Clause -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD SecureFault_Handler - DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD Reserved39_IRQHandler ; Reserved interrupt - DCD ACMP_IRQHandler ; ACMP interrupts - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts - DCD Reserved55_IRQHandler ; Reserved interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD SDIO_IRQHandler ; SD/MMC - DCD Reserved59_IRQHandler ; Reserved interrupt - DCD Reserved60_IRQHandler ; Reserved interrupt - DCD Reserved61_IRQHandler ; Reserved interrupt - DCD USB1_UTMI_IRQHandler ; USB1_UTMI - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt - DCD PLU_IRQHandler ; PLU interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt - DCD CASER_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD PQ_IRQHandler ; PQ interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) - - - AREA |.text|, CODE, READONLY - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| - - CPSID I ; Mask interrupts - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Base| - MSR MSPLIM, R0 - ;LDR R0, =SystemInit - ;BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler \ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SecureFault_Handler PROC - EXPORT SecureFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -WDT_BOD_IRQHandler\ - PROC - EXPORT WDT_BOD_IRQHandler [WEAK] - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - ENDP - -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -GINT0_IRQHandler\ - PROC - EXPORT GINT0_IRQHandler [WEAK] - LDR R0, =GINT0_DriverIRQHandler - BX R0 - ENDP - -GINT1_IRQHandler\ - PROC - EXPORT GINT1_IRQHandler [WEAK] - LDR R0, =GINT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT0_IRQHandler\ - PROC - EXPORT PIN_INT0_IRQHandler [WEAK] - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - ENDP - -PIN_INT1_IRQHandler\ - PROC - EXPORT PIN_INT1_IRQHandler [WEAK] - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT2_IRQHandler\ - PROC - EXPORT PIN_INT2_IRQHandler [WEAK] - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - ENDP - -PIN_INT3_IRQHandler\ - PROC - EXPORT PIN_INT3_IRQHandler [WEAK] - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - ENDP - -UTICK0_IRQHandler\ - PROC - EXPORT UTICK0_IRQHandler [WEAK] - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - ENDP - -MRT0_IRQHandler\ - PROC - EXPORT MRT0_IRQHandler [WEAK] - LDR R0, =MRT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER0_IRQHandler\ - PROC - EXPORT CTIMER0_IRQHandler [WEAK] - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - ENDP - -CTIMER1_IRQHandler\ - PROC - EXPORT CTIMER1_IRQHandler [WEAK] - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - ENDP - -SCT0_IRQHandler\ - PROC - EXPORT SCT0_IRQHandler [WEAK] - LDR R0, =SCT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER3_IRQHandler\ - PROC - EXPORT CTIMER3_IRQHandler [WEAK] - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM0_IRQHandler\ - PROC - EXPORT FLEXCOMM0_IRQHandler [WEAK] - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM1_IRQHandler\ - PROC - EXPORT FLEXCOMM1_IRQHandler [WEAK] - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM2_IRQHandler\ - PROC - EXPORT FLEXCOMM2_IRQHandler [WEAK] - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM3_IRQHandler\ - PROC - EXPORT FLEXCOMM3_IRQHandler [WEAK] - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM4_IRQHandler\ - PROC - EXPORT FLEXCOMM4_IRQHandler [WEAK] - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM5_IRQHandler\ - PROC - EXPORT FLEXCOMM5_IRQHandler [WEAK] - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM6_IRQHandler\ - PROC - EXPORT FLEXCOMM6_IRQHandler [WEAK] - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM7_IRQHandler\ - PROC - EXPORT FLEXCOMM7_IRQHandler [WEAK] - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - ENDP - -ADC0_IRQHandler\ - PROC - EXPORT ADC0_IRQHandler [WEAK] - LDR R0, =ADC0_DriverIRQHandler - BX R0 - ENDP - -Reserved39_IRQHandler\ - PROC - EXPORT Reserved39_IRQHandler [WEAK] - LDR R0, =Reserved39_DriverIRQHandler - BX R0 - ENDP - -ACMP_IRQHandler\ - PROC - EXPORT ACMP_IRQHandler [WEAK] - LDR R0, =ACMP_DriverIRQHandler - BX R0 - ENDP - -Reserved41_IRQHandler\ - PROC - EXPORT Reserved41_IRQHandler [WEAK] - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - ENDP - -Reserved42_IRQHandler\ - PROC - EXPORT Reserved42_IRQHandler [WEAK] - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - ENDP - -USB0_NEEDCLK_IRQHandler\ - PROC - EXPORT USB0_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -USB0_IRQHandler\ - PROC - EXPORT USB0_IRQHandler [WEAK] - LDR R0, =USB0_DriverIRQHandler - BX R0 - ENDP - -RTC_IRQHandler\ - PROC - EXPORT RTC_IRQHandler [WEAK] - LDR R0, =RTC_DriverIRQHandler - BX R0 - ENDP - -Reserved46_IRQHandler\ - PROC - EXPORT Reserved46_IRQHandler [WEAK] - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - ENDP - -MAILBOX_IRQHandler\ - PROC - EXPORT MAILBOX_IRQHandler [WEAK] - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 - ENDP - -PIN_INT4_IRQHandler\ - PROC - EXPORT PIN_INT4_IRQHandler [WEAK] - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - ENDP - -PIN_INT5_IRQHandler\ - PROC - EXPORT PIN_INT5_IRQHandler [WEAK] - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - ENDP - -PIN_INT6_IRQHandler\ - PROC - EXPORT PIN_INT6_IRQHandler [WEAK] - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - ENDP - -PIN_INT7_IRQHandler\ - PROC - EXPORT PIN_INT7_IRQHandler [WEAK] - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - ENDP - -CTIMER2_IRQHandler\ - PROC - EXPORT CTIMER2_IRQHandler [WEAK] - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - ENDP - -CTIMER4_IRQHandler\ - PROC - EXPORT CTIMER4_IRQHandler [WEAK] - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - ENDP - -OS_EVENT_IRQHandler\ - PROC - EXPORT OS_EVENT_IRQHandler [WEAK] - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - ENDP - -Reserved55_IRQHandler\ - PROC - EXPORT Reserved55_IRQHandler [WEAK] - LDR R0, =Reserved55_DriverIRQHandler - BX R0 - ENDP - -Reserved56_IRQHandler\ - PROC - EXPORT Reserved56_IRQHandler [WEAK] - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - ENDP - -Reserved57_IRQHandler\ - PROC - EXPORT Reserved57_IRQHandler [WEAK] - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - ENDP - -SDIO_IRQHandler\ - PROC - EXPORT SDIO_IRQHandler [WEAK] - LDR R0, =SDIO_DriverIRQHandler - BX R0 - ENDP - -Reserved59_IRQHandler\ - PROC - EXPORT Reserved59_IRQHandler [WEAK] - LDR R0, =Reserved59_DriverIRQHandler - BX R0 - ENDP - -Reserved60_IRQHandler\ - PROC - EXPORT Reserved60_IRQHandler [WEAK] - LDR R0, =Reserved60_DriverIRQHandler - BX R0 - ENDP - -Reserved61_IRQHandler\ - PROC - EXPORT Reserved61_IRQHandler [WEAK] - LDR R0, =Reserved61_DriverIRQHandler - BX R0 - ENDP - -USB1_UTMI_IRQHandler\ - PROC - EXPORT USB1_UTMI_IRQHandler [WEAK] - LDR R0, =USB1_UTMI_DriverIRQHandler - BX R0 - ENDP - -USB1_IRQHandler\ - PROC - EXPORT USB1_IRQHandler [WEAK] - LDR R0, =USB1_DriverIRQHandler - BX R0 - ENDP - -USB1_NEEDCLK_IRQHandler\ - PROC - EXPORT USB1_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -SEC_HYPERVISOR_CALL_IRQHandler\ - PROC - EXPORT SEC_HYPERVISOR_CALL_IRQHandler [WEAK] - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - ENDP - -SEC_GPIO_INT0_IRQ0_IRQHandler\ - PROC - EXPORT SEC_GPIO_INT0_IRQ0_IRQHandler [WEAK] - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - ENDP - -SEC_GPIO_INT0_IRQ1_IRQHandler\ - PROC - EXPORT SEC_GPIO_INT0_IRQ1_IRQHandler [WEAK] - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - ENDP - -PLU_IRQHandler\ - PROC - EXPORT PLU_IRQHandler [WEAK] - LDR R0, =PLU_DriverIRQHandler - BX R0 - ENDP - -SEC_VIO_IRQHandler\ - PROC - EXPORT SEC_VIO_IRQHandler [WEAK] - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - ENDP - -HASHCRYPT_IRQHandler\ - PROC - EXPORT HASHCRYPT_IRQHandler [WEAK] - LDR R0, =HASHCRYPT_DriverIRQHandler - BX R0 - ENDP - -CASER_IRQHandler\ - PROC - EXPORT CASER_IRQHandler [WEAK] - LDR R0, =CASER_DriverIRQHandler - BX R0 - ENDP - -PUF_IRQHandler\ - PROC - EXPORT PUF_IRQHandler [WEAK] - LDR R0, =PUF_DriverIRQHandler - BX R0 - ENDP - -PQ_IRQHandler\ - PROC - EXPORT PQ_IRQHandler [WEAK] - LDR R0, =PQ_DriverIRQHandler - BX R0 - ENDP - -DMA1_IRQHandler\ - PROC - EXPORT DMA1_IRQHandler [WEAK] - LDR R0, =DMA1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM8_IRQHandler\ - PROC - EXPORT FLEXCOMM8_IRQHandler [WEAK] - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 - ENDP - -Default_Handler PROC - EXPORT WDT_BOD_DriverIRQHandler [WEAK] - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT GINT0_DriverIRQHandler [WEAK] - EXPORT GINT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT0_DriverIRQHandler [WEAK] - EXPORT PIN_INT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT2_DriverIRQHandler [WEAK] - EXPORT PIN_INT3_DriverIRQHandler [WEAK] - EXPORT UTICK0_DriverIRQHandler [WEAK] - EXPORT MRT0_DriverIRQHandler [WEAK] - EXPORT CTIMER0_DriverIRQHandler [WEAK] - EXPORT CTIMER1_DriverIRQHandler [WEAK] - EXPORT SCT0_DriverIRQHandler [WEAK] - EXPORT CTIMER3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] - EXPORT ADC0_DriverIRQHandler [WEAK] - EXPORT Reserved39_DriverIRQHandler [WEAK] - EXPORT ACMP_DriverIRQHandler [WEAK] - EXPORT Reserved41_DriverIRQHandler [WEAK] - EXPORT Reserved42_DriverIRQHandler [WEAK] - EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT USB0_DriverIRQHandler [WEAK] - EXPORT RTC_DriverIRQHandler [WEAK] - EXPORT Reserved46_DriverIRQHandler [WEAK] - EXPORT MAILBOX_DriverIRQHandler [WEAK] - EXPORT PIN_INT4_DriverIRQHandler [WEAK] - EXPORT PIN_INT5_DriverIRQHandler [WEAK] - EXPORT PIN_INT6_DriverIRQHandler [WEAK] - EXPORT PIN_INT7_DriverIRQHandler [WEAK] - EXPORT CTIMER2_DriverIRQHandler [WEAK] - EXPORT CTIMER4_DriverIRQHandler [WEAK] - EXPORT OS_EVENT_DriverIRQHandler [WEAK] - EXPORT Reserved55_DriverIRQHandler [WEAK] - EXPORT Reserved56_DriverIRQHandler [WEAK] - EXPORT Reserved57_DriverIRQHandler [WEAK] - EXPORT SDIO_DriverIRQHandler [WEAK] - EXPORT Reserved59_DriverIRQHandler [WEAK] - EXPORT Reserved60_DriverIRQHandler [WEAK] - EXPORT Reserved61_DriverIRQHandler [WEAK] - EXPORT USB1_UTMI_DriverIRQHandler [WEAK] - EXPORT USB1_DriverIRQHandler [WEAK] - EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT SEC_HYPERVISOR_CALL_DriverIRQHandler [WEAK] - EXPORT SEC_GPIO_INT0_IRQ0_DriverIRQHandler [WEAK] - EXPORT SEC_GPIO_INT0_IRQ1_DriverIRQHandler [WEAK] - EXPORT PLU_DriverIRQHandler [WEAK] - EXPORT SEC_VIO_DriverIRQHandler [WEAK] - EXPORT HASHCRYPT_DriverIRQHandler [WEAK] - EXPORT CASER_DriverIRQHandler [WEAK] - EXPORT PUF_DriverIRQHandler [WEAK] - EXPORT PQ_DriverIRQHandler [WEAK] - EXPORT DMA1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM8_DriverIRQHandler [WEAK] - -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -Reserved39_DriverIRQHandler -ACMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -MAILBOX_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -Reserved55_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -SDIO_DriverIRQHandler -Reserved59_DriverIRQHandler -Reserved60_DriverIRQHandler -Reserved61_DriverIRQHandler -USB1_UTMI_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -PLU_DriverIRQHandler -SEC_VIO_DriverIRQHandler -HASHCRYPT_DriverIRQHandler -CASER_DriverIRQHandler -PUF_DriverIRQHandler -PQ_DriverIRQHandler -DMA1_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler - - B . - - ENDP - - - ALIGN - - - END - diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s index 08696146b0..116a16b56a 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/arm/startup_LPC55S69_cm33_core1.s @@ -1,732 +1,795 @@ -;/***************************************************************************** -; * @file: startup_LPC55S69_cm33_core1.s -; * @purpose: CMSIS Cortex-M33 Core Device Startup File for the -; * LPC55S69_cm33_core1 -; * @version: 1.1 -; * @date: 2019-5-16 -; * -; * Copyright 1997-2016 Freescale Semiconductor, Inc. -; * Copyright 2016-2019 NXP -; * All rights reserved. -; * -; * SPDX-License-Identifier: BSD-3-Clause -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD SecureFault_Handler - DCD 0 - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect, Flash interrupt - DCD DMA0_IRQHandler ; DMA0 controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) - DCD ADC0_IRQHandler ; ADC0 - DCD Reserved39_IRQHandler ; Reserved interrupt - DCD ACMP_IRQHandler ; ACMP interrupts - DCD Reserved41_IRQHandler ; Reserved interrupt - DCD Reserved42_IRQHandler ; Reserved interrupt - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD MAILBOX_IRQHandler ; WAKEUP,Mailbox interrupt (present on selected devices) - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD OS_EVENT_IRQHandler ; OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts - DCD Reserved55_IRQHandler ; Reserved interrupt - DCD Reserved56_IRQHandler ; Reserved interrupt - DCD Reserved57_IRQHandler ; Reserved interrupt - DCD SDIO_IRQHandler ; SD/MMC - DCD Reserved59_IRQHandler ; Reserved interrupt - DCD Reserved60_IRQHandler ; Reserved interrupt - DCD Reserved61_IRQHandler ; Reserved interrupt - DCD USB1_UTMI_IRQHandler ; USB1_UTMI - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD SEC_HYPERVISOR_CALL_IRQHandler ; SEC_HYPERVISOR_CALL interrupt - DCD SEC_GPIO_INT0_IRQ0_IRQHandler ; SEC_GPIO_INT0_IRQ0 interrupt - DCD SEC_GPIO_INT0_IRQ1_IRQHandler ; SEC_GPIO_INT0_IRQ1 interrupt - DCD PLU_IRQHandler ; PLU interrupt - DCD SEC_VIO_IRQHandler ; SEC_VIO interrupt - DCD HASHCRYPT_IRQHandler ; HASHCRYPT interrupt - DCD CASER_IRQHandler ; CASPER interrupt - DCD PUF_IRQHandler ; PUF interrupt - DCD PQ_IRQHandler ; PQ interrupt - DCD DMA1_IRQHandler ; DMA1 interrupt - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (SPI, , FLEXCOMM) - - - AREA |.text|, CODE, READONLY - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base| - - CPSID I ; Mask interrupts - LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Base| - MSR MSPLIM, R0 - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler \ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SecureFault_Handler PROC - EXPORT SecureFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -WDT_BOD_IRQHandler\ - PROC - EXPORT WDT_BOD_IRQHandler [WEAK] - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - ENDP - -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -GINT0_IRQHandler\ - PROC - EXPORT GINT0_IRQHandler [WEAK] - LDR R0, =GINT0_DriverIRQHandler - BX R0 - ENDP - -GINT1_IRQHandler\ - PROC - EXPORT GINT1_IRQHandler [WEAK] - LDR R0, =GINT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT0_IRQHandler\ - PROC - EXPORT PIN_INT0_IRQHandler [WEAK] - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - ENDP - -PIN_INT1_IRQHandler\ - PROC - EXPORT PIN_INT1_IRQHandler [WEAK] - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT2_IRQHandler\ - PROC - EXPORT PIN_INT2_IRQHandler [WEAK] - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - ENDP - -PIN_INT3_IRQHandler\ - PROC - EXPORT PIN_INT3_IRQHandler [WEAK] - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - ENDP - -UTICK0_IRQHandler\ - PROC - EXPORT UTICK0_IRQHandler [WEAK] - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - ENDP - -MRT0_IRQHandler\ - PROC - EXPORT MRT0_IRQHandler [WEAK] - LDR R0, =MRT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER0_IRQHandler\ - PROC - EXPORT CTIMER0_IRQHandler [WEAK] - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - ENDP - -CTIMER1_IRQHandler\ - PROC - EXPORT CTIMER1_IRQHandler [WEAK] - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - ENDP - -SCT0_IRQHandler\ - PROC - EXPORT SCT0_IRQHandler [WEAK] - LDR R0, =SCT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER3_IRQHandler\ - PROC - EXPORT CTIMER3_IRQHandler [WEAK] - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM0_IRQHandler\ - PROC - EXPORT FLEXCOMM0_IRQHandler [WEAK] - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM1_IRQHandler\ - PROC - EXPORT FLEXCOMM1_IRQHandler [WEAK] - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM2_IRQHandler\ - PROC - EXPORT FLEXCOMM2_IRQHandler [WEAK] - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM3_IRQHandler\ - PROC - EXPORT FLEXCOMM3_IRQHandler [WEAK] - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM4_IRQHandler\ - PROC - EXPORT FLEXCOMM4_IRQHandler [WEAK] - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM5_IRQHandler\ - PROC - EXPORT FLEXCOMM5_IRQHandler [WEAK] - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM6_IRQHandler\ - PROC - EXPORT FLEXCOMM6_IRQHandler [WEAK] - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM7_IRQHandler\ - PROC - EXPORT FLEXCOMM7_IRQHandler [WEAK] - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - ENDP - -ADC0_IRQHandler\ - PROC - EXPORT ADC0_IRQHandler [WEAK] - LDR R0, =ADC0_DriverIRQHandler - BX R0 - ENDP - -Reserved39_IRQHandler\ - PROC - EXPORT Reserved39_IRQHandler [WEAK] - LDR R0, =Reserved39_DriverIRQHandler - BX R0 - ENDP - -ACMP_IRQHandler\ - PROC - EXPORT ACMP_IRQHandler [WEAK] - LDR R0, =ACMP_DriverIRQHandler - BX R0 - ENDP - -Reserved41_IRQHandler\ - PROC - EXPORT Reserved41_IRQHandler [WEAK] - LDR R0, =Reserved41_DriverIRQHandler - BX R0 - ENDP - -Reserved42_IRQHandler\ - PROC - EXPORT Reserved42_IRQHandler [WEAK] - LDR R0, =Reserved42_DriverIRQHandler - BX R0 - ENDP - -USB0_NEEDCLK_IRQHandler\ - PROC - EXPORT USB0_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -USB0_IRQHandler\ - PROC - EXPORT USB0_IRQHandler [WEAK] - LDR R0, =USB0_DriverIRQHandler - BX R0 - ENDP - -RTC_IRQHandler\ - PROC - EXPORT RTC_IRQHandler [WEAK] - LDR R0, =RTC_DriverIRQHandler - BX R0 - ENDP - -Reserved46_IRQHandler\ - PROC - EXPORT Reserved46_IRQHandler [WEAK] - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - ENDP - -MAILBOX_IRQHandler\ - PROC - EXPORT MAILBOX_IRQHandler [WEAK] - LDR R0, =MAILBOX_DriverIRQHandler - BX R0 - ENDP - -PIN_INT4_IRQHandler\ - PROC - EXPORT PIN_INT4_IRQHandler [WEAK] - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - ENDP - -PIN_INT5_IRQHandler\ - PROC - EXPORT PIN_INT5_IRQHandler [WEAK] - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - ENDP - -PIN_INT6_IRQHandler\ - PROC - EXPORT PIN_INT6_IRQHandler [WEAK] - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - ENDP - -PIN_INT7_IRQHandler\ - PROC - EXPORT PIN_INT7_IRQHandler [WEAK] - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - ENDP - -CTIMER2_IRQHandler\ - PROC - EXPORT CTIMER2_IRQHandler [WEAK] - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - ENDP - -CTIMER4_IRQHandler\ - PROC - EXPORT CTIMER4_IRQHandler [WEAK] - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - ENDP - -OS_EVENT_IRQHandler\ - PROC - EXPORT OS_EVENT_IRQHandler [WEAK] - LDR R0, =OS_EVENT_DriverIRQHandler - BX R0 - ENDP - -Reserved55_IRQHandler\ - PROC - EXPORT Reserved55_IRQHandler [WEAK] - LDR R0, =Reserved55_DriverIRQHandler - BX R0 - ENDP - -Reserved56_IRQHandler\ - PROC - EXPORT Reserved56_IRQHandler [WEAK] - LDR R0, =Reserved56_DriverIRQHandler - BX R0 - ENDP - -Reserved57_IRQHandler\ - PROC - EXPORT Reserved57_IRQHandler [WEAK] - LDR R0, =Reserved57_DriverIRQHandler - BX R0 - ENDP - -SDIO_IRQHandler\ - PROC - EXPORT SDIO_IRQHandler [WEAK] - LDR R0, =SDIO_DriverIRQHandler - BX R0 - ENDP - -Reserved59_IRQHandler\ - PROC - EXPORT Reserved59_IRQHandler [WEAK] - LDR R0, =Reserved59_DriverIRQHandler - BX R0 - ENDP - -Reserved60_IRQHandler\ - PROC - EXPORT Reserved60_IRQHandler [WEAK] - LDR R0, =Reserved60_DriverIRQHandler - BX R0 - ENDP - -Reserved61_IRQHandler\ - PROC - EXPORT Reserved61_IRQHandler [WEAK] - LDR R0, =Reserved61_DriverIRQHandler - BX R0 - ENDP - -USB1_UTMI_IRQHandler\ - PROC - EXPORT USB1_UTMI_IRQHandler [WEAK] - LDR R0, =USB1_UTMI_DriverIRQHandler - BX R0 - ENDP - -USB1_IRQHandler\ - PROC - EXPORT USB1_IRQHandler [WEAK] - LDR R0, =USB1_DriverIRQHandler - BX R0 - ENDP - -USB1_NEEDCLK_IRQHandler\ - PROC - EXPORT USB1_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -SEC_HYPERVISOR_CALL_IRQHandler\ - PROC - EXPORT SEC_HYPERVISOR_CALL_IRQHandler [WEAK] - LDR R0, =SEC_HYPERVISOR_CALL_DriverIRQHandler - BX R0 - ENDP - -SEC_GPIO_INT0_IRQ0_IRQHandler\ - PROC - EXPORT SEC_GPIO_INT0_IRQ0_IRQHandler [WEAK] - LDR R0, =SEC_GPIO_INT0_IRQ0_DriverIRQHandler - BX R0 - ENDP - -SEC_GPIO_INT0_IRQ1_IRQHandler\ - PROC - EXPORT SEC_GPIO_INT0_IRQ1_IRQHandler [WEAK] - LDR R0, =SEC_GPIO_INT0_IRQ1_DriverIRQHandler - BX R0 - ENDP - -PLU_IRQHandler\ - PROC - EXPORT PLU_IRQHandler [WEAK] - LDR R0, =PLU_DriverIRQHandler - BX R0 - ENDP - -SEC_VIO_IRQHandler\ - PROC - EXPORT SEC_VIO_IRQHandler [WEAK] - LDR R0, =SEC_VIO_DriverIRQHandler - BX R0 - ENDP - -HASHCRYPT_IRQHandler\ - PROC - EXPORT HASHCRYPT_IRQHandler [WEAK] - LDR R0, =HASHCRYPT_DriverIRQHandler - BX R0 - ENDP - -CASER_IRQHandler\ - PROC - EXPORT CASER_IRQHandler [WEAK] - LDR R0, =CASER_DriverIRQHandler - BX R0 - ENDP - -PUF_IRQHandler\ - PROC - EXPORT PUF_IRQHandler [WEAK] - LDR R0, =PUF_DriverIRQHandler - BX R0 - ENDP - -PQ_IRQHandler\ - PROC - EXPORT PQ_IRQHandler [WEAK] - LDR R0, =PQ_DriverIRQHandler - BX R0 - ENDP - -DMA1_IRQHandler\ - PROC - EXPORT DMA1_IRQHandler [WEAK] - LDR R0, =DMA1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM8_IRQHandler\ - PROC - EXPORT FLEXCOMM8_IRQHandler [WEAK] - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 - ENDP - -Default_Handler PROC - EXPORT WDT_BOD_DriverIRQHandler [WEAK] - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT GINT0_DriverIRQHandler [WEAK] - EXPORT GINT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT0_DriverIRQHandler [WEAK] - EXPORT PIN_INT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT2_DriverIRQHandler [WEAK] - EXPORT PIN_INT3_DriverIRQHandler [WEAK] - EXPORT UTICK0_DriverIRQHandler [WEAK] - EXPORT MRT0_DriverIRQHandler [WEAK] - EXPORT CTIMER0_DriverIRQHandler [WEAK] - EXPORT CTIMER1_DriverIRQHandler [WEAK] - EXPORT SCT0_DriverIRQHandler [WEAK] - EXPORT CTIMER3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] - EXPORT ADC0_DriverIRQHandler [WEAK] - EXPORT Reserved39_DriverIRQHandler [WEAK] - EXPORT ACMP_DriverIRQHandler [WEAK] - EXPORT Reserved41_DriverIRQHandler [WEAK] - EXPORT Reserved42_DriverIRQHandler [WEAK] - EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT USB0_DriverIRQHandler [WEAK] - EXPORT RTC_DriverIRQHandler [WEAK] - EXPORT Reserved46_DriverIRQHandler [WEAK] - EXPORT MAILBOX_DriverIRQHandler [WEAK] - EXPORT PIN_INT4_DriverIRQHandler [WEAK] - EXPORT PIN_INT5_DriverIRQHandler [WEAK] - EXPORT PIN_INT6_DriverIRQHandler [WEAK] - EXPORT PIN_INT7_DriverIRQHandler [WEAK] - EXPORT CTIMER2_DriverIRQHandler [WEAK] - EXPORT CTIMER4_DriverIRQHandler [WEAK] - EXPORT OS_EVENT_DriverIRQHandler [WEAK] - EXPORT Reserved55_DriverIRQHandler [WEAK] - EXPORT Reserved56_DriverIRQHandler [WEAK] - EXPORT Reserved57_DriverIRQHandler [WEAK] - EXPORT SDIO_DriverIRQHandler [WEAK] - EXPORT Reserved59_DriverIRQHandler [WEAK] - EXPORT Reserved60_DriverIRQHandler [WEAK] - EXPORT Reserved61_DriverIRQHandler [WEAK] - EXPORT USB1_UTMI_DriverIRQHandler [WEAK] - EXPORT USB1_DriverIRQHandler [WEAK] - EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT SEC_HYPERVISOR_CALL_DriverIRQHandler [WEAK] - EXPORT SEC_GPIO_INT0_IRQ0_DriverIRQHandler [WEAK] - EXPORT SEC_GPIO_INT0_IRQ1_DriverIRQHandler [WEAK] - EXPORT PLU_DriverIRQHandler [WEAK] - EXPORT SEC_VIO_DriverIRQHandler [WEAK] - EXPORT HASHCRYPT_DriverIRQHandler [WEAK] - EXPORT CASER_DriverIRQHandler [WEAK] - EXPORT PUF_DriverIRQHandler [WEAK] - EXPORT PQ_DriverIRQHandler [WEAK] - EXPORT DMA1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM8_DriverIRQHandler [WEAK] - -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_DriverIRQHandler -Reserved39_DriverIRQHandler -ACMP_DriverIRQHandler -Reserved41_DriverIRQHandler -Reserved42_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -MAILBOX_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -OS_EVENT_DriverIRQHandler -Reserved55_DriverIRQHandler -Reserved56_DriverIRQHandler -Reserved57_DriverIRQHandler -SDIO_DriverIRQHandler -Reserved59_DriverIRQHandler -Reserved60_DriverIRQHandler -Reserved61_DriverIRQHandler -USB1_UTMI_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -SEC_HYPERVISOR_CALL_DriverIRQHandler -SEC_GPIO_INT0_IRQ0_DriverIRQHandler -SEC_GPIO_INT0_IRQ1_DriverIRQHandler -PLU_DriverIRQHandler -SEC_VIO_DriverIRQHandler -HASHCRYPT_DriverIRQHandler -CASER_DriverIRQHandler -PUF_DriverIRQHandler -PQ_DriverIRQHandler -DMA1_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler - - B . - - ENDP - - - ALIGN - - - END - +/* --------------------------------------------------------------------------------------- + * @file: startup_LPC55S69_cm33_core1.s + * @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core1 + * @version: 1.1 + * @date: 2019-5-16 + * ---------------------------------------------------------------------------------------*/ +/* + * Copyright 1997-2016 Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + + .syntax unified + .arch armv8-m.main + .eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */ + + .section .isr_vector, "a" + .align 2 + .globl __Vectors + +__Vectors: + .long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler*/ + .long HardFault_Handler /* Hard Fault Handler*/ + .long MemManage_Handler /* MPU Fault Handler*/ + .long BusFault_Handler /* Bus Fault Handler*/ + .long UsageFault_Handler /* Usage Fault Handler*/ + .long SecureFault_Handler /* Secure Fault Handler*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long 0 /* Reserved*/ + .long SVC_Handler /* SVCall Handler*/ + .long DebugMon_Handler /* Debug Monitor Handler*/ + .long 0 /* Reserved*/ + .long PendSV_Handler /* PendSV Handler*/ + .long SysTick_Handler /* SysTick Handler*/ + + /* External Interrupts*/ + .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + .long DMA0_IRQHandler /* DMA0 controller */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + .long ADC0_IRQHandler /* ADC0 */ + .long Reserved39_IRQHandler /* Reserved interrupt */ + .long ACMP_IRQHandler /* ACMP interrupts */ + .long Reserved41_IRQHandler /* Reserved interrupt */ + .long Reserved42_IRQHandler /* Reserved interrupt */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long Reserved46_IRQHandler /* Reserved interrupt */ + .long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ + .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ + .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ + .long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + .long Reserved55_IRQHandler /* Reserved interrupt */ + .long Reserved56_IRQHandler /* Reserved interrupt */ + .long Reserved57_IRQHandler /* Reserved interrupt */ + .long SDIO_IRQHandler /* SD/MMC */ + .long Reserved59_IRQHandler /* Reserved interrupt */ + .long Reserved60_IRQHandler /* Reserved interrupt */ + .long Reserved61_IRQHandler /* Reserved interrupt */ + .long USB1_PHY_IRQHandler /* USB1_PHY */ + .long USB1_IRQHandler /* USB1 interrupt */ + .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ + .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + .long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ + .long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ + .long PLU_IRQHandler /* PLU interrupt */ + .long SEC_VIO_IRQHandler /* SEC_VIO interrupt */ + .long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */ + .long CASER_IRQHandler /* CASPER interrupt */ + .long PUF_IRQHandler /* PUF interrupt */ + .long PQ_IRQHandler /* PQ interrupt */ + .long DMA1_IRQHandler /* DMA1 interrupt */ + .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + .size __Vectors, . - __Vectors + + .text + .thumb + +/* Reset Handler */ + .thumb_func + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + cpsid i /* mask interrupts */ + ldr r0, =Image$$ARM_LIB_STACK$$ZI$$Base + msr msplim, r0 + ldr r0,=SystemInit + blx r0 + cpsie i /* Unmask interrupts */ + ldr r0,=__main + bx r0 + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_IRQHandler + .type ADC0_IRQHandler, %function +ADC0_IRQHandler: + ldr r0,=ADC0_DriverIRQHandler + bx r0 + .size ADC0_IRQHandler, . - ADC0_IRQHandler + + .align 1 + .thumb_func + .weak Reserved39_IRQHandler + .type Reserved39_IRQHandler, %function +Reserved39_IRQHandler: + ldr r0,=Reserved39_DriverIRQHandler + bx r0 + .size Reserved39_IRQHandler, . - Reserved39_IRQHandler + + .align 1 + .thumb_func + .weak ACMP_IRQHandler + .type ACMP_IRQHandler, %function +ACMP_IRQHandler: + ldr r0,=ACMP_DriverIRQHandler + bx r0 + .size ACMP_IRQHandler, . - ACMP_IRQHandler + + .align 1 + .thumb_func + .weak Reserved41_IRQHandler + .type Reserved41_IRQHandler, %function +Reserved41_IRQHandler: + ldr r0,=Reserved41_DriverIRQHandler + bx r0 + .size Reserved41_IRQHandler, . - Reserved41_IRQHandler + + .align 1 + .thumb_func + .weak Reserved42_IRQHandler + .type Reserved42_IRQHandler, %function +Reserved42_IRQHandler: + ldr r0,=Reserved42_DriverIRQHandler + bx r0 + .size Reserved42_IRQHandler, . - Reserved42_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak Reserved46_IRQHandler + .type Reserved46_IRQHandler, %function +Reserved46_IRQHandler: + ldr r0,=Reserved46_DriverIRQHandler + bx r0 + .size Reserved46_IRQHandler, . - Reserved46_IRQHandler + + .align 1 + .thumb_func + .weak MAILBOX_IRQHandler + .type MAILBOX_IRQHandler, %function +MAILBOX_IRQHandler: + ldr r0,=MAILBOX_DriverIRQHandler + bx r0 + .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT4_IRQHandler + .type PIN_INT4_IRQHandler, %function +PIN_INT4_IRQHandler: + ldr r0,=PIN_INT4_DriverIRQHandler + bx r0 + .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT5_IRQHandler + .type PIN_INT5_IRQHandler, %function +PIN_INT5_IRQHandler: + ldr r0,=PIN_INT5_DriverIRQHandler + bx r0 + .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT6_IRQHandler + .type PIN_INT6_IRQHandler, %function +PIN_INT6_IRQHandler: + ldr r0,=PIN_INT6_DriverIRQHandler + bx r0 + .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT7_IRQHandler + .type PIN_INT7_IRQHandler, %function +PIN_INT7_IRQHandler: + ldr r0,=PIN_INT7_DriverIRQHandler + bx r0 + .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak OS_EVENT_IRQHandler + .type OS_EVENT_IRQHandler, %function +OS_EVENT_IRQHandler: + ldr r0,=OS_EVENT_DriverIRQHandler + bx r0 + .size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler + + .align 1 + .thumb_func + .weak Reserved55_IRQHandler + .type Reserved55_IRQHandler, %function +Reserved55_IRQHandler: + ldr r0,=Reserved55_DriverIRQHandler + bx r0 + .size Reserved55_IRQHandler, . - Reserved55_IRQHandler + + .align 1 + .thumb_func + .weak Reserved56_IRQHandler + .type Reserved56_IRQHandler, %function +Reserved56_IRQHandler: + ldr r0,=Reserved56_DriverIRQHandler + bx r0 + .size Reserved56_IRQHandler, . - Reserved56_IRQHandler + + .align 1 + .thumb_func + .weak Reserved57_IRQHandler + .type Reserved57_IRQHandler, %function +Reserved57_IRQHandler: + ldr r0,=Reserved57_DriverIRQHandler + bx r0 + .size Reserved57_IRQHandler, . - Reserved57_IRQHandler + + .align 1 + .thumb_func + .weak SDIO_IRQHandler + .type SDIO_IRQHandler, %function +SDIO_IRQHandler: + ldr r0,=SDIO_DriverIRQHandler + bx r0 + .size SDIO_IRQHandler, . - SDIO_IRQHandler + + .align 1 + .thumb_func + .weak Reserved59_IRQHandler + .type Reserved59_IRQHandler, %function +Reserved59_IRQHandler: + ldr r0,=Reserved59_DriverIRQHandler + bx r0 + .size Reserved59_IRQHandler, . - Reserved59_IRQHandler + + .align 1 + .thumb_func + .weak Reserved60_IRQHandler + .type Reserved60_IRQHandler, %function +Reserved60_IRQHandler: + ldr r0,=Reserved60_DriverIRQHandler + bx r0 + .size Reserved60_IRQHandler, . - Reserved60_IRQHandler + + .align 1 + .thumb_func + .weak Reserved61_IRQHandler + .type Reserved61_IRQHandler, %function +Reserved61_IRQHandler: + ldr r0,=Reserved61_DriverIRQHandler + bx r0 + .size Reserved61_IRQHandler, . - Reserved61_IRQHandler + + .align 1 + .thumb_func + .weak USB1_PHY_IRQHandler + .type USB1_PHY_IRQHandler, %function +USB1_PHY_IRQHandler: + ldr r0,=USB1_PHY_DriverIRQHandler + bx r0 + .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler + + .align 1 + .thumb_func + .weak USB1_IRQHandler + .type USB1_IRQHandler, %function +USB1_IRQHandler: + ldr r0,=USB1_DriverIRQHandler + bx r0 + .size USB1_IRQHandler, . - USB1_IRQHandler + + .align 1 + .thumb_func + .weak USB1_NEEDCLK_IRQHandler + .type USB1_NEEDCLK_IRQHandler, %function +USB1_NEEDCLK_IRQHandler: + ldr r0,=USB1_NEEDCLK_DriverIRQHandler + bx r0 + .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak SEC_HYPERVISOR_CALL_IRQHandler + .type SEC_HYPERVISOR_CALL_IRQHandler, %function +SEC_HYPERVISOR_CALL_IRQHandler: + ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler + bx r0 + .size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ0_IRQHandler + .type SEC_GPIO_INT0_IRQ0_IRQHandler, %function +SEC_GPIO_INT0_IRQ0_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak SEC_GPIO_INT0_IRQ1_IRQHandler + .type SEC_GPIO_INT0_IRQ1_IRQHandler, %function +SEC_GPIO_INT0_IRQ1_IRQHandler: + ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler + bx r0 + .size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak PLU_IRQHandler + .type PLU_IRQHandler, %function +PLU_IRQHandler: + ldr r0,=PLU_DriverIRQHandler + bx r0 + .size PLU_IRQHandler, . - PLU_IRQHandler + + .align 1 + .thumb_func + .weak SEC_VIO_IRQHandler + .type SEC_VIO_IRQHandler, %function +SEC_VIO_IRQHandler: + ldr r0,=SEC_VIO_DriverIRQHandler + bx r0 + .size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler + + .align 1 + .thumb_func + .weak HASHCRYPT_IRQHandler + .type HASHCRYPT_IRQHandler, %function +HASHCRYPT_IRQHandler: + ldr r0,=HASHCRYPT_DriverIRQHandler + bx r0 + .size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler + + .align 1 + .thumb_func + .weak CASER_IRQHandler + .type CASER_IRQHandler, %function +CASER_IRQHandler: + ldr r0,=CASER_DriverIRQHandler + bx r0 + .size CASER_IRQHandler, . - CASER_IRQHandler + + .align 1 + .thumb_func + .weak PUF_IRQHandler + .type PUF_IRQHandler, %function +PUF_IRQHandler: + ldr r0,=PUF_DriverIRQHandler + bx r0 + .size PUF_IRQHandler, . - PUF_IRQHandler + + .align 1 + .thumb_func + .weak PQ_IRQHandler + .type PQ_IRQHandler, %function +PQ_IRQHandler: + ldr r0,=PQ_DriverIRQHandler + bx r0 + .size PQ_IRQHandler, . - PQ_IRQHandler + + .align 1 + .thumb_func + .weak DMA1_IRQHandler + .type DMA1_IRQHandler, %function +DMA1_IRQHandler: + ldr r0,=DMA1_DriverIRQHandler + bx r0 + .size DMA1_IRQHandler, . - DMA1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM8_IRQHandler + .type FLEXCOMM8_IRQHandler, %function +FLEXCOMM8_IRQHandler: + ldr r0,=FLEXCOMM8_DriverIRQHandler + bx r0 + .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm +/* Exception Handlers */ + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler + def_irq_handler DebugMon_Handler + def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */ + def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */ + def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ + def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ + def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ + def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ + def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ + def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ + def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ + def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ + def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */ + def_irq_handler ADC0_DriverIRQHandler /* ADC0 */ + def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */ + def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ + def_irq_handler USB0_DriverIRQHandler /* USB device */ + def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ + def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler MAILBOX_DriverIRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */ + def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ + def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ + def_irq_handler OS_EVENT_DriverIRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */ + def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */ + def_irq_handler Reserved59_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved60_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */ + def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */ + def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */ + def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */ + def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */ + def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */ + def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */ + def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */ + def_irq_handler HASHCRYPT_DriverIRQHandler /* HASHCRYPT interrupt */ + def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */ + def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */ + def_irq_handler PQ_DriverIRQHandler /* PQ interrupt */ + def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */ + def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */ + + .end diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_i2c_LPC55S69_cm33_core0.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_i2c_LPC55S69_cm33_core0.cmake new file mode 100644 index 0000000000..d64968d1ac --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_i2c_LPC55S69_cm33_core0.cmake @@ -0,0 +1,17 @@ +include_guard() +message("driver_cmsis_flexcomm_i2c component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_i2c_cmsis.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_flexcomm_i2c_dma_LPC55S69_cm33_core0) + +include(CMSIS_Driver_Include_I2C_LPC55S69_cm33_core0) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_spi_LPC55S69_cm33_core0.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_spi_LPC55S69_cm33_core0.cmake new file mode 100644 index 0000000000..13dd220b2b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_spi_LPC55S69_cm33_core0.cmake @@ -0,0 +1,17 @@ +include_guard() +message("driver_cmsis_flexcomm_spi component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_spi_cmsis.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_flexcomm_spi_dma_LPC55S69_cm33_core0) + +include(CMSIS_Driver_Include_SPI_LPC55S69_cm33_core0) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_usart_LPC55S69_cm33_core0.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_usart_LPC55S69_cm33_core0.cmake new file mode 100644 index 0000000000..6779f5cd76 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/driver_cmsis_flexcomm_usart_LPC55S69_cm33_core0.cmake @@ -0,0 +1,17 @@ +include_guard() +message("driver_cmsis_flexcomm_usart component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_usart_cmsis.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(driver_flexcomm_usart_dma_LPC55S69_cm33_core0) + +include(CMSIS_Driver_Include_USART_LPC55S69_cm33_core0) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.c new file mode 100644 index 0000000000..b3e7d9199a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.c @@ -0,0 +1,3279 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2020,2022 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_i2c_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_cmsis" +#endif + +#if ((defined(RTE_I2C0) && RTE_I2C0) || (defined(RTE_I2C1) && RTE_I2C1) || (defined(RTE_I2C2) && RTE_I2C2) || \ + (defined(RTE_I2C3) && RTE_I2C3) || (defined(RTE_I2C4) && RTE_I2C4) || (defined(RTE_I2C5) && RTE_I2C5) || \ + (defined(RTE_I2C6) && RTE_I2C6) || (defined(RTE_I2C7) && RTE_I2C7) || (defined(RTE_I2C8) && RTE_I2C8) || \ + (defined(RTE_I2C9) && RTE_I2C9) || (defined(RTE_I2C10) && RTE_I2C10) || (defined(RTE_I2C11) && RTE_I2C11) || \ + (defined(RTE_I2C12) && RTE_I2C12) || (defined(RTE_I2C13) && RTE_I2C13)) + +#define ARM_I2C_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (3)) + +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +typedef const struct _cmsis_i2c_resource +{ + I2C_Type *base; /*!< I2C peripheral base address. */ + uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ + +} cmsis_i2c_resource_t; + +typedef union _cmsis_i2c_handle +{ + i2c_master_handle_t master_handle; /*!< master Interupt transfer handle. */ + i2c_slave_handle_t slave_handle; /*!< slave Interupt transfer handle. */ +} cmsis_i2c_handle_t; + +typedef struct _cmsis_i2c_interrupt_driver_state +{ + cmsis_i2c_resource_t *resource; /*!< Basic I2C resource. */ + cmsis_i2c_handle_t *handle; + ARM_I2C_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_i2c_interrupt_driver_state_t; + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +typedef const struct _cmsis_i2c_dma_resource +{ + DMA_Type *i2cDmaBase; /*!< DMA peripheral base address for i2c. */ + uint32_t i2cDmaChannel; /*!< DMA channel for i2c. */ +} cmsis_i2c_dma_resource_t; + +typedef struct _cmsis_i2c_dma_driver_state +{ + cmsis_i2c_resource_t *resource; /*!< i2c basic resource. */ + cmsis_i2c_dma_resource_t *dmaResource; /*!< i2c DMA resource. */ + i2c_master_dma_handle_t *master_dma_handle; /*!< i2c DMA transfer handle. */ + dma_handle_t *dmaHandle; /*!< DMA i2c handle. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_i2c_dma_driver_state_t; +#endif + +static const ARM_DRIVER_VERSION s_i2cDriverVersion = {ARM_I2C_API_VERSION, ARM_I2C_DRV_VERSION}; + +static const ARM_I2C_CAPABILITIES s_i2cDriverCapabilities = { + 0, /*< supports 10-bit addressing*/ +}; + +static ARM_DRIVER_VERSION I2Cx_GetVersion(void) +{ + return s_i2cDriverVersion; +} + +static ARM_I2C_CAPABILITIES I2Cx_GetCapabilities(void) +{ + return s_i2cDriverCapabilities; +} + +#endif + +#if ((defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN) || (defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN) || \ + (defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN) || (defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN) || \ + (defined(RTE_I2C4_DMA_EN) && RTE_I2C4_DMA_EN) || (defined(RTE_I2C5_DMA_EN) && RTE_I2C5_DMA_EN) || \ + (defined(RTE_I2C6_DMA_EN) && RTE_I2C6_DMA_EN) || (defined(RTE_I2C7_DMA_EN) && RTE_I2C7_DMA_EN) || \ + (defined(RTE_I2C8_DMA_EN) && RTE_I2C8_DMA_EN) || (defined(RTE_I2C9_DMA_EN) && RTE_I2C9_DMA_EN) || \ + (defined(RTE_I2C10_DMA_EN) && RTE_I2C10_DMA_EN) || (defined(RTE_I2C11_DMA_EN) && RTE_I2C11_DMA_EN) || \ + (defined(RTE_I2C12_DMA_EN) && RTE_I2C12_DMA_EN) || (defined(RTE_I2C13_DMA_EN) && RTE_I2C13_DMA_EN)) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +static void KSDK_I2C_MASTER_DmaCallback(I2C_Type *base, + i2c_master_dma_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event = 0U; + + if (status == kStatus_Success) /* Occurs after Master Transmit/Receive operation has finished. */ + { + event = ARM_I2C_EVENT_TRANSFER_DONE; + } + else if (status == kStatus_I2C_Nak) /* Slave nacks master before all data are transmitted */ + { + event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; + } + else if (status == kStatus_I2C_Addr_Nak) /* Failed during slave probing */ + { + event = ARM_I2C_EVENT_ADDRESS_NACK; + } + else if (status == kStatus_I2C_ArbitrationLost) /* Arbitration lost */ + { + event = ARM_I2C_EVENT_ARBITRATION_LOST; + } + else /* kStatus_I2C_UnexpectedState, kStatus_I2C_Busy and kStatus_I2C_StartStopError */ + { + event = ARM_I2C_EVENT_BUS_ERROR; + } + + if (userData != NULL) + { + ((ARM_I2C_SignalEvent_t)userData)(event); + } +} + +static int32_t I2C_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_dma_driver_state_t *i2c) +{ + if (0U == (i2c->flags & (uint8_t)I2C_FLAG_INIT)) + { + DMA_EnableChannel(i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); + DMA_CreateHandle(i2c->dmaHandle, i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); + + I2C_MasterTransferCreateHandleDMA(i2c->resource->base, i2c->master_dma_handle, KSDK_I2C_MASTER_DmaCallback, + (void *)cb_event, i2c->dmaHandle); + i2c->flags = (uint8_t)I2C_FLAG_INIT; + } + return ARM_DRIVER_OK; +} + +static int32_t I2C_Master_DmaUninitialize(cmsis_i2c_dma_driver_state_t *i2c) +{ + i2c->flags = (uint8_t)I2C_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t I2C_Master_DmaTransmit( + uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + i2c_master_transfer_t masterXfer; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (i2c->master_dma_handle->state != 0U) + { + return ARM_DRIVER_ERROR_BUSY; + } + + masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/ + masterXfer.direction = kI2C_Write; /*Transfer direction.*/ + masterXfer.subaddress = 0U; /*Sub address*/ + masterXfer.subaddressSize = 0U; /*Size of command buffer.*/ + masterXfer.data = (void *)data; /*Transfer buffer.*/ + masterXfer.dataSize = num; /*Transfer size.*/ + masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ + + if (xfer_pending) + { + masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag; + } + + status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer); + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t I2C_Master_DmaReceive( + uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_dma_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + i2c_master_transfer_t masterXfer; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (i2c->master_dma_handle->state != 0U) + { + return ARM_DRIVER_ERROR_BUSY; + } + + masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/ + masterXfer.direction = kI2C_Read; /*Transfer direction.*/ + masterXfer.subaddress = 0U; /*Sub address*/ + masterXfer.subaddressSize = 0U; /*Size of command buffer.*/ + masterXfer.data = (uint8_t *)data; /*Transfer buffer.*/ + masterXfer.dataSize = num; /*Transfer size.*/ + masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ + + if (xfer_pending) + { + masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag; + } + + status = I2C_MasterTransferDMA(i2c->resource->base, i2c->master_dma_handle, &masterXfer); + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t I2C_Master_DmaGetDataCount(cmsis_i2c_dma_driver_state_t *i2c) +{ + size_t cnt; /*the number of currently transferred data bytes*/ + + (void)I2C_MasterTransferGetCountDMA(i2c->resource->base, i2c->master_dma_handle, &cnt); + return (int32_t)cnt; +} + +static int32_t I2C_Master_DmaControl(uint32_t control, uint32_t arg, cmsis_i2c_dma_driver_state_t *i2c) +{ + uint32_t baudRate_Bps = 0; + int32_t result = ARM_DRIVER_OK; + switch (control) + { + /* Not supported */ + case ARM_I2C_OWN_ADDRESS: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + /*Set Bus Speed; arg = bus speed*/ + case ARM_I2C_BUS_SPEED: + switch (arg) + { + case ARM_I2C_BUS_SPEED_STANDARD: + baudRate_Bps = 100000; + break; + case ARM_I2C_BUS_SPEED_FAST: + baudRate_Bps = 400000; + break; + case ARM_I2C_BUS_SPEED_FAST_PLUS: + baudRate_Bps = 1000000; + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq()); + break; + /* Not supported */ + case ARM_I2C_BUS_CLEAR: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + /*Aborts the data transfer when Master for Transmit or Receive*/ + case ARM_I2C_ABORT_TRANSFER: + /*disable dma*/ + I2C_MasterTransferAbortDMA(i2c->resource->base, i2c->master_dma_handle); + + i2c->master_dma_handle->transferCount = 0; + i2c->master_dma_handle->transfer.data = NULL; + i2c->master_dma_handle->transfer.dataSize = 0; + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + return result; +} + +static int32_t I2C_Master_DmaPowerControl(ARM_POWER_STATE state, cmsis_i2c_dma_driver_state_t *i2c) +{ + int32_t result = ARM_DRIVER_OK; + switch (state) + { + /*terminates any pending data transfers, disable i2c moduole and i2c clock and related dma*/ + case ARM_POWER_OFF: + if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U) + { + (void)I2C_Master_DmaControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); + I2C_MasterDeinit(i2c->resource->base); + DMA_DisableChannel(i2c->dmaResource->i2cDmaBase, i2c->dmaResource->i2cDmaChannel); + i2c->flags = (uint8_t)I2C_FLAG_INIT; + } + break; + /* Not supported */ + case ARM_POWER_LOW: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + /*enable i2c moduole and i2c clock*/ + case ARM_POWER_FULL: + if (i2c->flags == (uint8_t)I2C_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U) + { + /* Driver already powered */ + break; + } + (void)FLEXCOMM_Init(i2c->resource->base, FLEXCOMM_PERIPH_I2C); + I2C_MasterEnable(i2c->resource->base, true); + i2c->flags |= (uint8_t)I2C_FLAG_POWER; + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + return result; +} + +static ARM_I2C_STATUS I2C_Master_DmaGetStatus(cmsis_i2c_dma_driver_state_t *i2c) +{ + ARM_I2C_STATUS stat = {0}; + uint32_t ksdk_i2c_status = I2C_GetStatusFlags(i2c->resource->base); + + stat.busy = (uint32_t)(0UL == (ksdk_i2c_status & (uint32_t)I2C_STAT_MSTPENDING_MASK)); /*Busy flag.*/ + stat.direction = (uint32_t)i2c->master_dma_handle->transfer.direction; /*Direction: 0=Transmitter, 1=Receiver.*/ + stat.mode = 1UL; /*Mode: 0=Slave, 1=Master.*/ + stat.arbitration_lost = (uint32_t)((ksdk_i2c_status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U); + /*Master lost arbitration (cleared on start of next Master operation)*/ + + return stat; +} + +#endif + +#endif + +#if ((defined(RTE_I2C0) && RTE_I2C0 && !(defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN)) || \ + (defined(RTE_I2C1) && RTE_I2C1 && !(defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN)) || \ + (defined(RTE_I2C2) && RTE_I2C2 && !(defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN)) || \ + (defined(RTE_I2C3) && RTE_I2C3 && !(defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN)) || \ + (defined(RTE_I2C4) && RTE_I2C4 && !(defined(RTE_I2C4_DMA_EN) && RTE_I2C4_DMA_EN)) || \ + (defined(RTE_I2C5) && RTE_I2C5 && !(defined(RTE_I2C5_DMA_EN) && RTE_I2C5_DMA_EN)) || \ + (defined(RTE_I2C6) && RTE_I2C6 && !(defined(RTE_I2C6_DMA_EN) && RTE_I2C6_DMA_EN)) || \ + (defined(RTE_I2C7) && RTE_I2C7 && !(defined(RTE_I2C7_DMA_EN) && RTE_I2C7_DMA_EN)) || \ + (defined(RTE_I2C8) && RTE_I2C8 && !(defined(RTE_I2C8_DMA_EN) && RTE_I2C8_DMA_EN)) || \ + (defined(RTE_I2C9) && RTE_I2C9 && !(defined(RTE_I2C9_DMA_EN) && RTE_I2C9_DMA_EN)) || \ + (defined(RTE_I2C10) && RTE_I2C10 && !(defined(RTE_I2C10_DMA_EN) && RTE_I2C10_DMA_EN)) || \ + (defined(RTE_I2C11) && RTE_I2C11 && !(defined(RTE_I2C11_DMA_EN) && RTE_I2C11_DMA_EN)) || \ + (defined(RTE_I2C12) && RTE_I2C12 && !(defined(RTE_I2C12_DMA_EN) && RTE_I2C12_DMA_EN)) || \ + (defined(RTE_I2C13) && RTE_I2C13 && !(defined(RTE_I2C13_DMA_EN) && RTE_I2C13_DMA_EN))) + +static void KSDK_I2C_SLAVE_InterruptCallback(I2C_Type *base, volatile i2c_slave_transfer_t *xfer, void *param) +{ + uint32_t event; + + switch (xfer->event) + { + case kI2C_SlaveCompletionEvent: /* Occurs after Slave Transmit/Receive operation has finished. */ + event = ARM_I2C_EVENT_TRANSFER_DONE; + break; + default: + event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; + break; + } + + if (param != NULL) + { + ((ARM_I2C_SignalEvent_t)param)(event); + } +} + +static void KSDK_I2C_MASTER_InterruptCallback(I2C_Type *base, + i2c_master_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event; + + switch (status) + { + case kStatus_Success: /* Occurs after Master Transmit/Receive operation has finished. */ + event = ARM_I2C_EVENT_TRANSFER_DONE; + break; + case kStatus_I2C_ArbitrationLost: /*Occurs in master mode when arbitration is lost.*/ + event = ARM_I2C_EVENT_ARBITRATION_LOST; + break; + case kStatus_I2C_Nak: /* Slave nacks master before all data are transmitted */ + event = ARM_I2C_EVENT_TRANSFER_INCOMPLETE; + break; + case kStatus_I2C_Addr_Nak: /* Failed during slave probing */ + event = ARM_I2C_EVENT_ADDRESS_NACK; + break; + default: + event = ARM_I2C_EVENT_BUS_ERROR; + break; + } + + /* User data is actually CMSIS driver callback. */ + if (userData != NULL) + { + ((ARM_I2C_SignalEvent_t)userData)(event); + } +} + +static int32_t I2C_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + if (0U == (i2c->flags & (uint8_t)I2C_FLAG_INIT)) + { + i2c->cb_event = cb_event; /* cb_event is CMSIS driver callback. */ + i2c->flags = (uint8_t)I2C_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t I2C_InterruptUninitialize(cmsis_i2c_interrupt_driver_state_t *i2c) +{ + i2c->flags = (uint8_t)I2C_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t I2C_Master_InterruptTransmit( + uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + i2c_master_transfer_t masterXfer; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (i2c->handle->master_handle.state != 0U) + { + return ARM_DRIVER_ERROR_BUSY; + } + + I2C_MasterEnable(i2c->resource->base, true); + + /*create master_handle*/ + I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), + KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); + + masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/ + masterXfer.direction = kI2C_Write; /*Transfer direction.*/ + masterXfer.subaddress = 0U; /*Sub address*/ + masterXfer.subaddressSize = 0U; /*Size of command buffer.*/ + masterXfer.data = (uint8_t *)data; /*Transfer buffer.*/ + masterXfer.dataSize = num; /*Transfer size.*/ + masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ + + if (xfer_pending) + { + masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag; + } + + status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t I2C_Master_InterruptReceive( + uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + i2c_master_transfer_t masterXfer; + + /* Check if the I2C bus is idle - if not return busy status. */ + if (i2c->handle->master_handle.state != 0U) + { + return ARM_DRIVER_ERROR_BUSY; + } + + I2C_MasterEnable(i2c->resource->base, true); + + /*create master_handle*/ + I2C_MasterTransferCreateHandle(i2c->resource->base, &(i2c->handle->master_handle), + KSDK_I2C_MASTER_InterruptCallback, (void *)i2c->cb_event); + + masterXfer.slaveAddress = (uint8_t)addr; /*7-bit slave address.*/ + masterXfer.direction = kI2C_Read; /*Transfer direction.*/ + masterXfer.subaddress = 0U; /*Sub address*/ + masterXfer.subaddressSize = 0U; /*Size of command buffer.*/ + masterXfer.data = data; /*Transfer buffer.*/ + masterXfer.dataSize = num; /*Transfer size.*/ + masterXfer.flags = (uint32_t)kI2C_TransferDefaultFlag; /*Transfer flag which controls the transfer.*/ + + if (xfer_pending) + { + masterXfer.flags |= (uint32_t)kI2C_TransferNoStopFlag; + } + + status = I2C_MasterTransferNonBlocking(i2c->resource->base, &(i2c->handle->master_handle), &masterXfer); + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t I2C_Slave_InterruptTransmit(const uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + + /* set Slave enable */ + I2C_SlaveEnable(i2c->resource->base, true); + + /*create slave_handle*/ + I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, + (void *)i2c->cb_event); + + status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), + (uint32_t)kI2C_SlaveCompletionEvent); + + i2c->handle->slave_handle.transfer.txData = + (uint8_t *)data; /*Pointer to buffer with data to transmit to I2C Master*/ + i2c->handle->slave_handle.transfer.txSize = num; /*Number of data bytes to transmit*/ + i2c->handle->slave_handle.transfer.transferredCount = + 0U; /*Number of bytes actually transferred since start or last repeated start. */ + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t I2C_Slave_InterruptReceive(uint8_t *data, uint32_t num, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t status; + int32_t ret; + + /* set Slave enable */ + I2C_SlaveEnable(i2c->resource->base, true); + + /*create slave_handle*/ + I2C_SlaveTransferCreateHandle(i2c->resource->base, &(i2c->handle->slave_handle), KSDK_I2C_SLAVE_InterruptCallback, + (void *)i2c->cb_event); + + status = I2C_SlaveTransferNonBlocking(i2c->resource->base, &(i2c->handle->slave_handle), + (uint32_t)kI2C_SlaveCompletionEvent); + + i2c->handle->slave_handle.transfer.rxData = data; /*Pointer to buffer with data to transmit to I2C Master*/ + i2c->handle->slave_handle.transfer.rxSize = num; /*Number of data bytes to transmit*/ + i2c->handle->slave_handle.transfer.transferredCount = + 0U; /*Number of bytes actually transferred since start or last repeated start. */ + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_I2C_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t I2C_InterruptGetDataCount(cmsis_i2c_interrupt_driver_state_t *i2c) +{ + uint32_t cnt = 0; /*the number of currently transferred data bytes*/ + + if ((i2c->resource->base->CFG & (uint8_t)I2C_CFG_MSTEN_MASK) != 0U) + { + cnt = i2c->handle->master_handle.transferCount; + } + else + { + cnt = i2c->handle->slave_handle.transfer.transferredCount; + } + + return (int32_t)cnt; +} + +static int32_t I2C_InterruptControl(uint32_t control, uint32_t arg, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + uint32_t baudRate_Bps; + uint32_t clkDiv; + int32_t result = ARM_DRIVER_OK; + switch (control) + { + /*Set Own Slave Address; arg = slave address*/ + case ARM_I2C_OWN_ADDRESS: + /* Use as slave, set CLKDIV for clock stretching, ensure data set up time for standard mode 250ns. */ + /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ + clkDiv = i2c->resource->GetFreq() / 1000U; + clkDiv = (clkDiv * 250U) / 1000000U; + i2c->resource->base->CLKDIV = clkDiv & I2C_CLKDIV_DIVVAL_MASK; + + /* Set slave address. */ + I2C_SlaveSetAddress(i2c->resource->base, kI2C_SlaveAddressRegister0, (uint8_t)arg, false); + /* set Slave address 0 qual */ + i2c->resource->base->SLVQUAL0 = I2C_SLVQUAL0_QUALMODE0(0) | I2C_SLVQUAL0_SLVQUAL0(0); + break; + /*Set Bus Speed; arg = bus speed*/ + case ARM_I2C_BUS_SPEED: + switch (arg) + { + case ARM_I2C_BUS_SPEED_STANDARD: + baudRate_Bps = 100000; + break; + case ARM_I2C_BUS_SPEED_FAST: + baudRate_Bps = 400000; + break; + case ARM_I2C_BUS_SPEED_FAST_PLUS: + baudRate_Bps = 1000000; + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + if (result == ARM_DRIVER_OK) + { + I2C_MasterSetBaudRate(i2c->resource->base, baudRate_Bps, i2c->resource->GetFreq()); + } + break; + // Not supported + case ARM_I2C_BUS_CLEAR: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + /*Aborts the data transfer between Master and Slave for Transmit or Receive*/ + case ARM_I2C_ABORT_TRANSFER: + if ((i2c->resource->base->CFG & (uint8_t)I2C_CFG_MSTEN_MASK) != 0U) + { + /*disable master interrupt and send STOP signal*/ + (void)I2C_MasterTransferAbort(i2c->resource->base, &(i2c->handle->master_handle)); + + i2c->handle->master_handle.transferCount = 0; + i2c->handle->master_handle.transfer.data = NULL; + i2c->handle->master_handle.transfer.dataSize = 0; + } + /*if slave receive*/ + if (((i2c->resource->base->CFG & (uint32_t)I2C_CFG_SLVEN_MASK) != 0U) && + ((i2c->handle->slave_handle.slaveFsm) == kI2C_SlaveFsmReceive)) + { + /*disable slave interrupt*/ + I2C_SlaveTransferAbort(i2c->resource->base, &(i2c->handle->slave_handle)); + + i2c->handle->slave_handle.transfer.transferredCount = 0; + i2c->handle->slave_handle.transfer.txData = NULL; + i2c->handle->slave_handle.transfer.rxData = NULL; + } + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + return result; +} + +static int32_t I2C_InterruptPowerControl(ARM_POWER_STATE state, cmsis_i2c_interrupt_driver_state_t *i2c) +{ + int32_t result = ARM_DRIVER_OK; + switch (state) + { + /*terminates any pending data transfers, disable i2c moduole and i2c clock*/ + case ARM_POWER_OFF: + if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U) + { + (void)I2C_InterruptControl(ARM_I2C_ABORT_TRANSFER, 0, i2c); + I2C_MasterDeinit(i2c->resource->base); + I2C_SlaveDeinit(i2c->resource->base); + i2c->flags = (uint8_t)I2C_FLAG_INIT; + } + break; + /* Not supported */ + case ARM_POWER_LOW: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + /*enable i2c moduole and i2c clock*/ + case ARM_POWER_FULL: + if (i2c->flags == (uint8_t)I2C_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if ((i2c->flags & (uint8_t)I2C_FLAG_POWER) != 0U) + { + /* Driver already powered */ + break; + } + (void)FLEXCOMM_Init(i2c->resource->base, FLEXCOMM_PERIPH_I2C); + i2c->flags |= (uint8_t)I2C_FLAG_POWER; + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + return result; +} + +static ARM_I2C_STATUS I2C_InterruptGetStatus(cmsis_i2c_interrupt_driver_state_t *i2c) +{ + ARM_I2C_STATUS stat = {0}; + uint32_t ksdk_i2c_status = I2C_GetStatusFlags(i2c->resource->base); + + if ((i2c->resource->base->CFG & (uint32_t)I2C_CFG_MSTEN_MASK) != 0U) + { + stat.busy = (uint32_t)(0UL == (ksdk_i2c_status & (uint32_t)I2C_STAT_MSTPENDING_MASK)); /*Busy flag.*/ + stat.direction = + (uint32_t)i2c->handle->master_handle.transfer.direction; /*Direction: 0=Transmitter, 1=Receiver.*/ + stat.mode = 1UL; /*Mode: 0=Slave, 1=Master.*/ + stat.arbitration_lost = (uint32_t)((ksdk_i2c_status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U); + /*Master lost arbitration (cleared on start of next Master operation)*/ + } + + if ((i2c->resource->base->CFG & (uint32_t)I2C_CFG_SLVEN_MASK) != 0U) + { + stat.busy = (uint32_t)(0UL == (ksdk_i2c_status & (uint32_t)I2C_STAT_SLVPENDING_MASK)); /*Busy flag.*/ + if (i2c->handle->slave_handle.slaveFsm == kI2C_SlaveFsmReceive) + { + stat.direction = 1; /*Direction: 0=Transmitter, 1=Receiver.*/ + } + else + { + stat.direction = 0; /*Direction: 0=Transmitter, 1=Receiver.*/ + } + stat.mode = 0; /*Mode: 0=Slave, 1=Master.*/ + } + + return stat; +} + +#endif + +#if defined(I2C0) && defined(RTE_I2C0) && RTE_I2C0 +/* User needs to provide the implementation for I2C0_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C0_GetFreq(void); + +static cmsis_i2c_resource_t I2C0_Resource = {I2C0, I2C0_GetFreq}; + +#if (defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C0_DmaResource = {RTE_I2C0_Master_DMA_BASE, RTE_I2C0_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C0_DmaHandle; +static dma_handle_t I2C0_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c0_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C0_DmaDriverState = { +#endif + &I2C0_Resource, + &I2C0_DmaResource, + &I2C0_DmaHandle, + &I2C0_DmaTxRxHandle, +}; + +static int32_t I2C0_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C0_PIN_INIT + RTE_I2C0_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C0_DmaDriverState); +} + +static int32_t I2C0_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C0_PIN_DEINIT + RTE_I2C0_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C0_DmaDriverState); +} + +static int32_t I2C0_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C0_DmaDriverState); +} + +static int32_t I2C0_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C0_DmaDriverState); +} + +static int32_t I2C0_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C0_DmaDriverState); +} + +static int32_t I2C0_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C0_DmaDriverState); +} + +static int32_t I2C0_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C0_DmaDriverState); +} + +static ARM_I2C_STATUS I2C0_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C0_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C0_handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c0_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C0_InterruptDriverState = { +#endif + &I2C0_Resource, + &I2C0_handle, + +}; + +static int32_t I2C0_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C0_PIN_INIT + RTE_I2C0_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_InterruptUninitialize(void) +{ +#ifdef RTE_I2C0_PIN_DEINIT + RTE_I2C0_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C0_InterruptDriverState); +} + +static int32_t I2C0_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C0_InterruptDriverState); +} + +static int32_t I2C0_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C0_InterruptDriverState); +} + +static int32_t I2C0_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C0_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C0_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C0_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C0 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C0_DMA_EN) && RTE_I2C0_DMA_EN + I2C0_Master_DmaInitialize, + I2C0_Master_DmaUninitialize, + I2C0_Master_DmaPowerControl, + I2C0_Master_DmaTransmit, + I2C0_Master_DmaReceive, + NULL, + NULL, + I2C0_Master_DmaGetDataCount, + I2C0_Master_DmaControl, + I2C0_Master_DmaGetStatus +#else + I2C0_InterruptInitialize, + I2C0_InterruptUninitialize, + I2C0_InterruptPowerControl, + I2C0_Master_InterruptTransmit, + I2C0_Master_InterruptReceive, + I2C0_Slave_InterruptTransmit, + I2C0_Slave_InterruptReceive, + I2C0_InterruptGetDataCount, + I2C0_InterruptControl, + I2C0_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C1) && defined(RTE_I2C1) && RTE_I2C1 + +/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C1_GetFreq(void); + +static cmsis_i2c_resource_t I2C1_Resource = {I2C1, I2C1_GetFreq}; + +#if (defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C1_DmaResource = {RTE_I2C1_Master_DMA_BASE, RTE_I2C1_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C1_DmaHandle; +static dma_handle_t I2C1_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c1_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C1_DmaDriverState = { +#endif + &I2C1_Resource, + &I2C1_DmaResource, + &I2C1_DmaHandle, + &I2C1_DmaTxRxHandle, +}; + +static int32_t I2C1_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C1_PIN_INIT + RTE_I2C1_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C1_DmaDriverState); +} + +static int32_t I2C1_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C1_PIN_DEINIT + RTE_I2C1_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C1_DmaDriverState); +} + +static int32_t I2C1_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C1_DmaDriverState); +} + +static int32_t I2C1_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C1_DmaDriverState); +} + +static int32_t I2C1_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C1_DmaDriverState); +} + +static int32_t I2C1_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C1_DmaDriverState); +} + +static int32_t I2C1_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C1_DmaDriverState); +} + +static ARM_I2C_STATUS I2C1_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C1_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C1_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c1_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C1_InterruptDriverState = { +#endif + &I2C1_Resource, + &I2C1_Handle, +}; + +static int32_t I2C1_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C1_PIN_INIT + RTE_I2C1_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_InterruptUninitialize(void) +{ +#ifdef RTE_I2C1_PIN_DEINIT + RTE_I2C1_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C1_InterruptDriverState); +} + +static int32_t I2C1_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C1_InterruptDriverState); +} + +static int32_t I2C1_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C1_InterruptDriverState); +} + +static int32_t I2C1_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C1_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C1_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C1_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C1 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C1_DMA_EN) && RTE_I2C1_DMA_EN + I2C1_Master_DmaInitialize, + I2C1_Master_DmaUninitialize, + I2C1_Master_DmaPowerControl, + I2C1_Master_DmaTransmit, + I2C1_Master_DmaReceive, + NULL, + NULL, + I2C1_Master_DmaGetDataCount, + I2C1_Master_DmaControl, + I2C1_Master_DmaGetStatus +#else + I2C1_InterruptInitialize, + I2C1_InterruptUninitialize, + I2C1_InterruptPowerControl, + I2C1_Master_InterruptTransmit, + I2C1_Master_InterruptReceive, + I2C1_Slave_InterruptTransmit, + I2C1_Slave_InterruptReceive, + I2C1_InterruptGetDataCount, + I2C1_InterruptControl, + I2C1_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C2) && defined(RTE_I2C2) && RTE_I2C2 + +/* User needs to provide the implementation for I2C2_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C2_GetFreq(void); + +static cmsis_i2c_resource_t I2C2_Resource = {I2C2, I2C2_GetFreq}; + +#if (defined(RTE_I2C2_DMA_EN) && RTE_I2C2_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C2_DmaResource = {RTE_I2C2_Master_DMA_BASE, RTE_I2C2_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C2_DmaHandle; +static dma_handle_t I2C2_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c2_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C2_DmaDriverState = { +#endif + &I2C2_Resource, + &I2C2_DmaResource, + &I2C2_DmaHandle, + &I2C2_DmaTxRxHandle, +}; + +static int32_t I2C2_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C2_PIN_INIT + RTE_I2C2_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C2_DmaDriverState); +} + +static int32_t I2C2_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C2_PIN_DEINIT + RTE_I2C2_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C2_DmaDriverState); +} + +static int32_t I2C2_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C2_DmaDriverState); +} + +static int32_t I2C2_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C2_DmaDriverState); +} + +static int32_t I2C2_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C2_DmaDriverState); +} + +static int32_t I2C2_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C2_DmaDriverState); +} + +static int32_t I2C2_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C2_DmaDriverState); +} + +static ARM_I2C_STATUS I2C2_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C2_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C2_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c2_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C2_InterruptDriverState = { +#endif + &I2C2_Resource, + &I2C2_Handle, + +}; + +static int32_t I2C2_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C2_PIN_INIT + RTE_I2C2_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_InterruptUninitialize(void) +{ +#ifdef RTE_I2C2_PIN_DEINIT + RTE_I2C2_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C2_InterruptDriverState); +} + +static int32_t I2C2_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C2_InterruptDriverState); +} + +static int32_t I2C2_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C2_InterruptDriverState); +} + +static int32_t I2C2_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C2_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C2_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C2_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C2 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C2_DMA_EN) && (RTE_I2C2_DMA_EN) + I2C2_Master_DmaInitialize, + I2C2_Master_DmaUninitialize, + I2C2_Master_DmaPowerControl, + I2C2_Master_DmaTransmit, + I2C2_Master_DmaReceive, + NULL, + NULL, + I2C2_Master_DmaGetDataCount, + I2C2_Master_DmaControl, + I2C2_Master_DmaGetStatus +#else + I2C2_InterruptInitialize, + I2C2_InterruptUninitialize, + I2C2_InterruptPowerControl, + I2C2_Master_InterruptTransmit, + I2C2_Master_InterruptReceive, + I2C2_Slave_InterruptTransmit, + I2C2_Slave_InterruptReceive, + I2C2_InterruptGetDataCount, + I2C2_InterruptControl, + I2C2_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C3) && defined(RTE_I2C3) && RTE_I2C3 + +/* User needs to provide the implementation for I2C3_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C3_GetFreq(void); + +static cmsis_i2c_resource_t I2C3_Resource = {I2C3, I2C3_GetFreq}; + +#if (defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C3_DmaResource = {RTE_I2C3_Master_DMA_BASE, RTE_I2C3_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C3_DmaHandle; +static dma_handle_t I2C3_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c3_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C3_DmaDriverState = { +#endif + &I2C3_Resource, + &I2C3_DmaResource, + &I2C3_DmaHandle, + &I2C3_DmaTxRxHandle, +}; + +static int32_t I2C3_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C3_PIN_INIT + RTE_I2C3_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C3_DmaDriverState); +} + +static int32_t I2C3_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C3_PIN_DEINIT + RTE_I2C3_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C3_DmaDriverState); +} + +static int32_t I2C3_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C3_DmaDriverState); +} + +static int32_t I2C3_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C3_DmaDriverState); +} + +static int32_t I2C3_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C3_DmaDriverState); +} + +static int32_t I2C3_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C3_DmaDriverState); +} + +static int32_t I2C3_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C3_DmaDriverState); +} + +static ARM_I2C_STATUS I2C3_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C3_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C3_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c3_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C3_InterruptDriverState = { +#endif + &I2C3_Resource, + &I2C3_Handle, +}; + +static int32_t I2C3_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C3_PIN_INIT + RTE_I2C3_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_InterruptUninitialize(void) +{ +#ifdef RTE_I2C3_PIN_DEINIT + RTE_I2C3_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C3_InterruptDriverState); +} + +static int32_t I2C3_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C3_InterruptDriverState); +} + +static int32_t I2C3_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C3_InterruptDriverState); +} + +static int32_t I2C3_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C3_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C3_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C3_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C3 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C3_DMA_EN) && RTE_I2C3_DMA_EN + I2C3_Master_DmaInitialize, + I2C3_Master_DmaUninitialize, + I2C3_Master_DmaPowerControl, + I2C3_Master_DmaTransmit, + I2C3_Master_DmaReceive, + NULL, + NULL, + I2C3_Master_DmaGetDataCount, + I2C3_Master_DmaControl, + I2C3_Master_DmaGetStatus +#else + I2C3_InterruptInitialize, + I2C3_InterruptUninitialize, + I2C3_InterruptPowerControl, + I2C3_Master_InterruptTransmit, + I2C3_Master_InterruptReceive, + I2C3_Slave_InterruptTransmit, + I2C3_Slave_InterruptReceive, + I2C3_InterruptGetDataCount, + I2C3_InterruptControl, + I2C3_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C4) && defined(RTE_I2C4) && RTE_I2C4 +/* User needs to provide the implementation for I2C4_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C4_GetFreq(void); + +static cmsis_i2c_resource_t I2C4_Resource = {I2C4, I2C4_GetFreq}; + +#if (defined(RTE_I2C4_DMA_EN) && RTE_I2C4_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C4_DmaResource = {RTE_I2C4_Master_DMA_BASE, RTE_I2C4_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C4_DmaHandle; +static dma_handle_t I2C4_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c4_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C4_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C4_DmaDriverState = { +#endif + &I2C4_Resource, + &I2C4_DmaResource, + &I2C4_DmaHandle, + &I2C4_DmaTxRxHandle, +}; + +static int32_t I2C4_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C4_PIN_INIT + RTE_I2C4_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C4_DmaDriverState); +} + +static int32_t I2C4_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C4_PIN_DEINIT + RTE_I2C4_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C4_DmaDriverState); +} + +static int32_t I2C4_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C4_DmaDriverState); +} + +static int32_t I2C4_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C4_DmaDriverState); +} + +static int32_t I2C4_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C4_DmaDriverState); +} + +static int32_t I2C4_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C4_DmaDriverState); +} + +static int32_t I2C4_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C4_DmaDriverState); +} + +static ARM_I2C_STATUS I2C4_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C4_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C4_handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c4_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C4_InterruptDriverState = { +#endif + &I2C4_Resource, + &I2C4_handle, + +}; + +static int32_t I2C4_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C4_PIN_INIT + RTE_I2C4_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_InterruptUninitialize(void) +{ +#ifdef RTE_I2C4_PIN_DEINIT + RTE_I2C4_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C4_InterruptDriverState); +} + +static int32_t I2C4_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C4_InterruptDriverState); +} + +static int32_t I2C4_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C4_InterruptDriverState); +} + +static int32_t I2C4_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C4_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C4_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C4_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C4 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C4_DMA_EN) && RTE_I2C4_DMA_EN + I2C4_Master_DmaInitialize, + I2C4_Master_DmaUninitialize, + I2C4_Master_DmaPowerControl, + I2C4_Master_DmaTransmit, + I2C4_Master_DmaReceive, + NULL, + NULL, + I2C4_Master_DmaGetDataCount, + I2C4_Master_DmaControl, + I2C4_Master_DmaGetStatus +#else + I2C4_InterruptInitialize, + I2C4_InterruptUninitialize, + I2C4_InterruptPowerControl, + I2C4_Master_InterruptTransmit, + I2C4_Master_InterruptReceive, + I2C4_Slave_InterruptTransmit, + I2C4_Slave_InterruptReceive, + I2C4_InterruptGetDataCount, + I2C4_InterruptControl, + I2C4_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C5) && defined(RTE_I2C5) && RTE_I2C5 +/* User needs to provide the implementation for I2C5_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C5_GetFreq(void); + +static cmsis_i2c_resource_t I2C5_Resource = {I2C5, I2C5_GetFreq}; + +#if (defined(RTE_I2C5_DMA_EN) && RTE_I2C5_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C5_DmaResource = {RTE_I2C5_Master_DMA_BASE, RTE_I2C5_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C5_DmaHandle; +static dma_handle_t I2C5_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c5_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C5_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C5_DmaDriverState = { +#endif + &I2C5_Resource, + &I2C5_DmaResource, + &I2C5_DmaHandle, + &I2C5_DmaTxRxHandle, +}; + +static int32_t I2C5_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C5_PIN_INIT + RTE_I2C5_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C5_DmaDriverState); +} + +static int32_t I2C5_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C5_PIN_DEINIT + RTE_I2C5_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C5_DmaDriverState); +} + +static int32_t I2C5_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C5_DmaDriverState); +} + +static int32_t I2C5_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C5_DmaDriverState); +} + +static int32_t I2C5_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C5_DmaDriverState); +} + +static int32_t I2C5_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C5_DmaDriverState); +} + +static int32_t I2C5_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C5_DmaDriverState); +} + +static ARM_I2C_STATUS I2C5_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C5_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C5_handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c5_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C5_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C5_InterruptDriverState = { +#endif + &I2C5_Resource, + &I2C5_handle, + +}; + +static int32_t I2C5_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C5_PIN_INIT + RTE_I2C5_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C5_InterruptDriverState); +} + +static int32_t I2C5_InterruptUninitialize(void) +{ +#ifdef RTE_I2C5_PIN_DEINIT + RTE_I2C5_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C5_InterruptDriverState); +} + +static int32_t I2C5_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C5_InterruptDriverState); +} + +static int32_t I2C5_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C5_InterruptDriverState); +} + +static int32_t I2C5_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C5_InterruptDriverState); +} + +static int32_t I2C5_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C5_InterruptDriverState); +} + +static int32_t I2C5_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C5_InterruptDriverState); +} + +static int32_t I2C5_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C5_InterruptDriverState); +} + +static int32_t I2C5_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C5_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C5_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C5_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C5 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C5_DMA_EN) && RTE_I2C5_DMA_EN + I2C5_Master_DmaInitialize, + I2C5_Master_DmaUninitialize, + I2C5_Master_DmaPowerControl, + I2C5_Master_DmaTransmit, + I2C5_Master_DmaReceive, + NULL, + NULL, + I2C5_Master_DmaGetDataCount, + I2C5_Master_DmaControl, + I2C5_Master_DmaGetStatus +#else + I2C5_InterruptInitialize, + I2C5_InterruptUninitialize, + I2C5_InterruptPowerControl, + I2C5_Master_InterruptTransmit, + I2C5_Master_InterruptReceive, + I2C5_Slave_InterruptTransmit, + I2C5_Slave_InterruptReceive, + I2C5_InterruptGetDataCount, + I2C5_InterruptControl, + I2C5_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C6) && defined(RTE_I2C6) && RTE_I2C6 +/* User needs to provide the implementation for I2C6_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C6_GetFreq(void); + +static cmsis_i2c_resource_t I2C6_Resource = {I2C6, I2C6_GetFreq}; + +#if (defined(RTE_I2C6_DMA_EN) && RTE_I2C6_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C6_DmaResource = {RTE_I2C6_Master_DMA_BASE, RTE_I2C6_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C6_DmaHandle; +static dma_handle_t I2C6_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c6_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C6_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C6_DmaDriverState = { +#endif + &I2C6_Resource, + &I2C6_DmaResource, + &I2C6_DmaHandle, + &I2C6_DmaTxRxHandle, +}; + +static int32_t I2C6_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C6_PIN_INIT + RTE_I2C6_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C6_DmaDriverState); +} + +static int32_t I2C6_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C6_PIN_DEINIT + RTE_I2C6_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C6_DmaDriverState); +} + +static int32_t I2C6_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C6_DmaDriverState); +} + +static int32_t I2C6_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C6_DmaDriverState); +} + +static int32_t I2C6_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C6_DmaDriverState); +} + +static int32_t I2C6_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C6_DmaDriverState); +} + +static int32_t I2C6_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C6_DmaDriverState); +} + +static ARM_I2C_STATUS I2C6_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C6_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C6_handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c6_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C6_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C6_InterruptDriverState = { +#endif + &I2C6_Resource, + &I2C6_handle, + +}; + +static int32_t I2C6_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C6_PIN_INIT + RTE_I2C6_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C6_InterruptDriverState); +} + +static int32_t I2C6_InterruptUninitialize(void) +{ +#ifdef RTE_I2C6_PIN_DEINIT + RTE_I2C6_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C6_InterruptDriverState); +} + +static int32_t I2C6_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C6_InterruptDriverState); +} + +static int32_t I2C6_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C6_InterruptDriverState); +} + +static int32_t I2C6_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C6_InterruptDriverState); +} + +static int32_t I2C6_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C6_InterruptDriverState); +} + +static int32_t I2C6_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C6_InterruptDriverState); +} + +static int32_t I2C6_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C6_InterruptDriverState); +} + +static int32_t I2C6_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C6_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C6_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C6_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C6 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C6_DMA_EN) && RTE_I2C6_DMA_EN + I2C6_Master_DmaInitialize, + I2C6_Master_DmaUninitialize, + I2C6_Master_DmaPowerControl, + I2C6_Master_DmaTransmit, + I2C6_Master_DmaReceive, + NULL, + NULL, + I2C6_Master_DmaGetDataCount, + I2C6_Master_DmaControl, + I2C6_Master_DmaGetStatus +#else + I2C6_InterruptInitialize, + I2C6_InterruptUninitialize, + I2C6_InterruptPowerControl, + I2C6_Master_InterruptTransmit, + I2C6_Master_InterruptReceive, + I2C6_Slave_InterruptTransmit, + I2C6_Slave_InterruptReceive, + I2C6_InterruptGetDataCount, + I2C6_InterruptControl, + I2C6_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C7) && defined(RTE_I2C7) && RTE_I2C7 +/* User needs to provide the implementation for I2C7_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C7_GetFreq(void); + +static cmsis_i2c_resource_t I2C7_Resource = {I2C7, I2C7_GetFreq}; + +#if (defined(RTE_I2C7_DMA_EN) && RTE_I2C7_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C7_DmaResource = {RTE_I2C7_Master_DMA_BASE, RTE_I2C7_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C7_DmaHandle; +static dma_handle_t I2C7_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c7_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C7_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C7_DmaDriverState = { +#endif + &I2C7_Resource, + &I2C7_DmaResource, + &I2C7_DmaHandle, + &I2C7_DmaTxRxHandle, +}; + +static int32_t I2C7_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C7_PIN_INIT + RTE_I2C7_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C7_DmaDriverState); +} + +static int32_t I2C7_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C7_PIN_DEINIT + RTE_I2C7_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C7_DmaDriverState); +} + +static int32_t I2C7_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C7_DmaDriverState); +} + +static int32_t I2C7_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C7_DmaDriverState); +} + +static int32_t I2C7_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C7_DmaDriverState); +} + +static int32_t I2C7_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C7_DmaDriverState); +} + +static int32_t I2C7_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C7_DmaDriverState); +} + +static ARM_I2C_STATUS I2C7_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C7_DmaDriverState); +} + +#endif + +#else +static cmsis_i2c_handle_t I2C7_handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c7_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C7_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C7_InterruptDriverState = { +#endif + &I2C7_Resource, + &I2C7_handle, + +}; + +static int32_t I2C7_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C7_PIN_INIT + RTE_I2C7_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C7_InterruptDriverState); +} + +static int32_t I2C7_InterruptUninitialize(void) +{ +#ifdef RTE_I2C7_PIN_DEINIT + RTE_I2C7_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C7_InterruptDriverState); +} + +static int32_t I2C7_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C7_InterruptDriverState); +} + +static int32_t I2C7_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C7_InterruptDriverState); +} + +static int32_t I2C7_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C7_InterruptDriverState); +} + +static int32_t I2C7_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C7_InterruptDriverState); +} + +static int32_t I2C7_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C7_InterruptDriverState); +} + +static int32_t I2C7_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C7_InterruptDriverState); +} + +static int32_t I2C7_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C7_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C7_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C7_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C7 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C7_DMA_EN) && RTE_I2C7_DMA_EN + I2C7_Master_DmaInitialize, + I2C7_Master_DmaUninitialize, + I2C7_Master_DmaPowerControl, + I2C7_Master_DmaTransmit, + I2C7_Master_DmaReceive, + NULL, + NULL, + I2C7_Master_DmaGetDataCount, + I2C7_Master_DmaControl, + I2C7_Master_DmaGetStatus +#else + I2C7_InterruptInitialize, + I2C7_InterruptUninitialize, + I2C7_InterruptPowerControl, + I2C7_Master_InterruptTransmit, + I2C7_Master_InterruptReceive, + I2C7_Slave_InterruptTransmit, + I2C7_Slave_InterruptReceive, + I2C7_InterruptGetDataCount, + I2C7_InterruptControl, + I2C7_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C8) && defined(RTE_I2C8) && RTE_I2C8 +/* User needs to provide the implementation for I2C8_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C8_GetFreq(void); + +static cmsis_i2c_resource_t I2C8_Resource = {I2C8, I2C8_GetFreq}; + +#if (defined(RTE_I2C8_DMA_EN) && RTE_I2C8_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C8_DmaResource = {RTE_I2C8_Master_DMA_BASE, RTE_I2C8_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C8_DmaHandle; +static dma_handle_t I2C8_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c8_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C8_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C8_DmaDriverState = { +#endif + &I2C8_Resource, + &I2C8_DmaResource, + &I2C8_DmaHandle, + &I2C8_DmaTxRxHandle, +}; + +static int32_t I2C8_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C8_PIN_INIT + RTE_I2C8_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C8_DmaDriverState); +} + +static int32_t I2C8_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C8_PIN_DEINIT + RTE_I2C8_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C8_DmaDriverState); +} + +static int32_t I2C8_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C8_DmaDriverState); +} + +static int32_t I2C8_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C8_DmaDriverState); +} + +static int32_t I2C8_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C8_DmaDriverState); +} + +static int32_t I2C8_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C8_DmaDriverState); +} + +static int32_t I2C8_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C8_DmaDriverState); +} + +static ARM_I2C_STATUS I2C8_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C8_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C8_handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c8_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C8_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C8_InterruptDriverState = { +#endif + &I2C8_Resource, + &I2C8_handle, + +}; + +static int32_t I2C8_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C8_PIN_INIT + RTE_I2C8_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C8_InterruptDriverState); +} + +static int32_t I2C8_InterruptUninitialize(void) +{ +#ifdef RTE_I2C8_PIN_DEINIT + RTE_I2C8_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C8_InterruptDriverState); +} + +static int32_t I2C8_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C8_InterruptDriverState); +} + +static int32_t I2C8_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C8_InterruptDriverState); +} + +static int32_t I2C8_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C8_InterruptDriverState); +} + +static int32_t I2C8_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C8_InterruptDriverState); +} + +static int32_t I2C8_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C8_InterruptDriverState); +} + +static int32_t I2C8_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C8_InterruptDriverState); +} + +static int32_t I2C8_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C8_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C8_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C8_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C8 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C8_DMA_EN) && RTE_I2C8_DMA_EN + I2C8_Master_DmaInitialize, + I2C8_Master_DmaUninitialize, + I2C8_Master_DmaPowerControl, + I2C8_Master_DmaTransmit, + I2C8_Master_DmaReceive, + NULL, + NULL, + I2C8_Master_DmaGetDataCount, + I2C8_Master_DmaControl, + I2C8_Master_DmaGetStatus +#else + I2C8_InterruptInitialize, + I2C8_InterruptUninitialize, + I2C8_InterruptPowerControl, + I2C8_Master_InterruptTransmit, + I2C8_Master_InterruptReceive, + I2C8_Slave_InterruptTransmit, + I2C8_Slave_InterruptReceive, + I2C8_InterruptGetDataCount, + I2C8_InterruptControl, + I2C8_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C9) && defined(RTE_I2C9) && RTE_I2C9 +/* User needs to provide the implementation for I2C9_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C9_GetFreq(void); + +static cmsis_i2c_resource_t I2C9_Resource = {I2C9, I2C9_GetFreq}; + +#if (defined(RTE_I2C9_DMA_EN) && RTE_I2C9_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C9_DmaResource = {RTE_I2C9_Master_DMA_BASE, RTE_I2C9_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C9_DmaHandle; +static dma_handle_t I2C9_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c9_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C9_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C9_DmaDriverState = { +#endif + &I2C9_Resource, + &I2C9_DmaResource, + &I2C9_DmaHandle, + &I2C9_DmaTxRxHandle, +}; + +static int32_t I2C9_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C9_PIN_INIT + RTE_I2C9_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C9_DmaDriverState); +} + +static int32_t I2C9_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C9_PIN_DEINIT + RTE_I2C9_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C9_DmaDriverState); +} + +static int32_t I2C9_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C9_DmaDriverState); +} + +static int32_t I2C9_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C9_DmaDriverState); +} + +static int32_t I2C9_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C9_DmaDriverState); +} + +static int32_t I2C9_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C9_DmaDriverState); +} + +static int32_t I2C9_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C9_DmaDriverState); +} + +static ARM_I2C_STATUS I2C9_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C9_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C9_handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c9_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C9_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C9_InterruptDriverState = { +#endif + &I2C9_Resource, + &I2C9_handle, + +}; + +static int32_t I2C9_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C9_PIN_INIT + RTE_I2C9_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C9_InterruptDriverState); +} + +static int32_t I2C9_InterruptUninitialize(void) +{ +#ifdef RTE_I2C9_PIN_DEINIT + RTE_I2C9_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C9_InterruptDriverState); +} + +static int32_t I2C9_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C9_InterruptDriverState); +} + +static int32_t I2C9_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C9_InterruptDriverState); +} + +static int32_t I2C9_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C9_InterruptDriverState); +} + +static int32_t I2C9_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C9_InterruptDriverState); +} + +static int32_t I2C9_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C9_InterruptDriverState); +} + +static int32_t I2C9_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C9_InterruptDriverState); +} + +static int32_t I2C9_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C9_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C9_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C9_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C9 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C9_DMA_EN) && RTE_I2C9_DMA_EN + I2C9_Master_DmaInitialize, + I2C9_Master_DmaUninitialize, + I2C9_Master_DmaPowerControl, + I2C9_Master_DmaTransmit, + I2C9_Master_DmaReceive, + NULL, + NULL, + I2C9_Master_DmaGetDataCount, + I2C9_Master_DmaControl, + I2C9_Master_DmaGetStatus +#else + I2C9_InterruptInitialize, + I2C9_InterruptUninitialize, + I2C9_InterruptPowerControl, + I2C9_Master_InterruptTransmit, + I2C9_Master_InterruptReceive, + I2C9_Slave_InterruptTransmit, + I2C9_Slave_InterruptReceive, + I2C9_InterruptGetDataCount, + I2C9_InterruptControl, + I2C9_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C10) && defined(RTE_I2C10) && RTE_I2C10 + +/* User needs to provide the implementation for I2C10_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C10_GetFreq(void); + +static cmsis_i2c_resource_t I2C10_Resource = {I2C10, I2C10_GetFreq}; + +#if (defined(RTE_I2C10_DMA_EN) && RTE_I2C10_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C10_DmaResource = {RTE_I2C10_Master_DMA_BASE, RTE_I2C10_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C10_DmaHandle; +static dma_handle_t I2C10_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c10_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C10_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C10_DmaDriverState = { +#endif + &I2C10_Resource, + &I2C10_DmaResource, + &I2C10_DmaHandle, + &I2C10_DmaTxRxHandle, +}; + +static int32_t I2C10_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C10_PIN_INIT + RTE_I2C10_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C10_DmaDriverState); +} + +static int32_t I2C10_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C10_PIN_DEINIT + RTE_I2C10_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C10_DmaDriverState); +} + +static int32_t I2C10_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C10_DmaDriverState); +} + +static int32_t I2C10_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C10_DmaDriverState); +} + +static int32_t I2C10_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C10_DmaDriverState); +} + +static int32_t I2C10_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C10_DmaDriverState); +} + +static int32_t I2C10_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C10_DmaDriverState); +} + +static ARM_I2C_STATUS I2C10_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C10_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C10_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c10_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C10_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C10_InterruptDriverState = { +#endif + &I2C10_Resource, + &I2C10_Handle, +}; + +static int32_t I2C10_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C10_PIN_INIT + RTE_I2C10_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C10_InterruptDriverState); +} + +static int32_t I2C10_InterruptUninitialize(void) +{ +#ifdef RTE_I2C10_PIN_DEINIT + RTE_I2C10_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C10_InterruptDriverState); +} + +static int32_t I2C10_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C10_InterruptDriverState); +} + +static int32_t I2C10_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C10_InterruptDriverState); +} + +static int32_t I2C10_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C10_InterruptDriverState); +} + +static int32_t I2C10_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C10_InterruptDriverState); +} + +static int32_t I2C10_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C10_InterruptDriverState); +} + +static int32_t I2C10_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C10_InterruptDriverState); +} + +static int32_t I2C10_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C10_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C10_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C10_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C10 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C10_DMA_EN) && RTE_I2C10_DMA_EN + I2C10_Master_DmaInitialize, + I2C10_Master_DmaUninitialize, + I2C10_Master_DmaPowerControl, + I2C10_Master_DmaTransmit, + I2C10_Master_DmaReceive, + NULL, + NULL, + I2C10_Master_DmaGetDataCount, + I2C10_Master_DmaControl, + I2C10_Master_DmaGetStatus +#else + I2C10_InterruptInitialize, + I2C10_InterruptUninitialize, + I2C10_InterruptPowerControl, + I2C10_Master_InterruptTransmit, + I2C10_Master_InterruptReceive, + I2C10_Slave_InterruptTransmit, + I2C10_Slave_InterruptReceive, + I2C10_InterruptGetDataCount, + I2C10_InterruptControl, + I2C10_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C11) && defined(RTE_I2C11) && RTE_I2C11 + +/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C11_GetFreq(void); + +static cmsis_i2c_resource_t I2C11_Resource = {I2C11, I2C11_GetFreq}; + +#if (defined(RTE_I2C11_DMA_EN) && RTE_I2C11_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C11_DmaResource = {RTE_I2C11_Master_DMA_BASE, RTE_I2C11_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C11_DmaHandle; +static dma_handle_t I2C11_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c11_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C11_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C11_DmaDriverState = { +#endif + &I2C11_Resource, + &I2C11_DmaResource, + &I2C11_DmaHandle, + &I2C11_DmaTxRxHandle, +}; + +static int32_t I2C11_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C11_PIN_INIT + RTE_I2C11_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C11_DmaDriverState); +} + +static int32_t I2C11_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C11_PIN_DEINIT + RTE_I2C11_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C11_DmaDriverState); +} + +static int32_t I2C11_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C11_DmaDriverState); +} + +static int32_t I2C11_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C11_DmaDriverState); +} + +static int32_t I2C11_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C11_DmaDriverState); +} + +static int32_t I2C11_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C11_DmaDriverState); +} + +static int32_t I2C11_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C11_DmaDriverState); +} + +static ARM_I2C_STATUS I2C11_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C11_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C11_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c11_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C11_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C11_InterruptDriverState = { +#endif + &I2C11_Resource, + &I2C11_Handle, +}; + +static int32_t I2C11_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C11_PIN_INIT + RTE_I2C11_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C11_InterruptDriverState); +} + +static int32_t I2C11_InterruptUninitialize(void) +{ +#ifdef RTE_I2C11_PIN_DEINIT + RTE_I2C11_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C11_InterruptDriverState); +} + +static int32_t I2C11_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C11_InterruptDriverState); +} + +static int32_t I2C11_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C11_InterruptDriverState); +} + +static int32_t I2C11_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C11_InterruptDriverState); +} + +static int32_t I2C11_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C11_InterruptDriverState); +} + +static int32_t I2C11_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C11_InterruptDriverState); +} + +static int32_t I2C11_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C11_InterruptDriverState); +} + +static int32_t I2C11_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C11_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C11_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C11_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C11 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C11_DMA_EN) && RTE_I2C11_DMA_EN + I2C11_Master_DmaInitialize, + I2C11_Master_DmaUninitialize, + I2C11_Master_DmaPowerControl, + I2C11_Master_DmaTransmit, + I2C11_Master_DmaReceive, + NULL, + NULL, + I2C11_Master_DmaGetDataCount, + I2C11_Master_DmaControl, + I2C11_Master_DmaGetStatus +#else + I2C11_InterruptInitialize, + I2C11_InterruptUninitialize, + I2C11_InterruptPowerControl, + I2C11_Master_InterruptTransmit, + I2C11_Master_InterruptReceive, + I2C11_Slave_InterruptTransmit, + I2C11_Slave_InterruptReceive, + I2C11_InterruptGetDataCount, + I2C11_InterruptControl, + I2C11_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C12) && defined(RTE_I2C12) && RTE_I2C12 + +/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C12_GetFreq(void); + +static cmsis_i2c_resource_t I2C12_Resource = {I2C12, I2C12_GetFreq}; + +#if (defined(RTE_I2C12_DMA_EN) && RTE_I2C12_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C12_DmaResource = {RTE_I2C12_Master_DMA_BASE, RTE_I2C12_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C12_DmaHandle; +static dma_handle_t I2C12_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c12_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C12_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C12_DmaDriverState = { +#endif + &I2C12_Resource, + &I2C12_DmaResource, + &I2C12_DmaHandle, + &I2C12_DmaTxRxHandle, +}; + +static int32_t I2C12_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C12_PIN_INIT + RTE_I2C12_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C12_DmaDriverState); +} + +static int32_t I2C12_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C12_PIN_DEINIT + RTE_I2C12_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C12_DmaDriverState); +} + +static int32_t I2C12_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C12_DmaDriverState); +} + +static int32_t I2C12_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C12_DmaDriverState); +} + +static int32_t I2C12_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C12_DmaDriverState); +} + +static int32_t I2C12_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C12_DmaDriverState); +} + +static int32_t I2C12_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C12_DmaDriverState); +} + +static ARM_I2C_STATUS I2C12_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C12_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C12_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c12_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C12_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C12_InterruptDriverState = { +#endif + &I2C12_Resource, + &I2C12_Handle, +}; + +static int32_t I2C12_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C12_PIN_INIT + RTE_I2C12_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C12_InterruptDriverState); +} + +static int32_t I2C12_InterruptUninitialize(void) +{ +#ifdef RTE_I2C12_PIN_DEINIT + RTE_I2C12_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C12_InterruptDriverState); +} + +static int32_t I2C12_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C12_InterruptDriverState); +} + +static int32_t I2C12_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C12_InterruptDriverState); +} + +static int32_t I2C12_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C12_InterruptDriverState); +} + +static int32_t I2C12_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C12_InterruptDriverState); +} + +static int32_t I2C12_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C12_InterruptDriverState); +} + +static int32_t I2C12_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C12_InterruptDriverState); +} + +static int32_t I2C12_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C12_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C12_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C12_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C12 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C12_DMA_EN) && RTE_I2C12_DMA_EN + I2C12_Master_DmaInitialize, + I2C12_Master_DmaUninitialize, + I2C12_Master_DmaPowerControl, + I2C12_Master_DmaTransmit, + I2C12_Master_DmaReceive, + NULL, + NULL, + I2C12_Master_DmaGetDataCount, + I2C12_Master_DmaControl, + I2C12_Master_DmaGetStatus +#else + I2C12_InterruptInitialize, + I2C12_InterruptUninitialize, + I2C12_InterruptPowerControl, + I2C12_Master_InterruptTransmit, + I2C12_Master_InterruptReceive, + I2C12_Slave_InterruptTransmit, + I2C12_Slave_InterruptReceive, + I2C12_InterruptGetDataCount, + I2C12_InterruptControl, + I2C12_InterruptGetStatus +#endif +}; + +#endif + +#if defined(I2C13) && defined(RTE_I2C13) && RTE_I2C13 + +/* User needs to provide the implementation for I2C1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t I2C13_GetFreq(void); + +static cmsis_i2c_resource_t I2C13_Resource = {I2C13, I2C13_GetFreq}; + +#if (defined(RTE_I2C13_DMA_EN) && RTE_I2C13_DMA_EN) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_i2c_dma_resource_t I2C13_DmaResource = {RTE_I2C13_Master_DMA_BASE, RTE_I2C13_Master_DMA_CH}; + +static i2c_master_dma_handle_t I2C13_DmaHandle; +static dma_handle_t I2C13_DmaTxRxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c13_dma_driver_state") +static cmsis_i2c_dma_driver_state_t I2C13_DmaDriverState = { +#else +static cmsis_i2c_dma_driver_state_t I2C13_DmaDriverState = { +#endif + &I2C13_Resource, + &I2C13_DmaResource, + &I2C13_DmaHandle, + &I2C13_DmaTxRxHandle, +}; + +static int32_t I2C13_Master_DmaInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C13_PIN_INIT + RTE_I2C13_PIN_INIT(); +#endif + return I2C_Master_DmaInitialize(cb_event, &I2C13_DmaDriverState); +} + +static int32_t I2C13_Master_DmaUninitialize(void) +{ +#ifdef RTE_I2C13_PIN_DEINIT + RTE_I2C13_PIN_DEINIT(); +#endif + return I2C_Master_DmaUninitialize(&I2C13_DmaDriverState); +} + +static int32_t I2C13_Master_DmaPowerControl(ARM_POWER_STATE state) +{ + return I2C_Master_DmaPowerControl(state, &I2C13_DmaDriverState); +} + +static int32_t I2C13_Master_DmaTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaTransmit(addr, data, num, xfer_pending, &I2C13_DmaDriverState); +} + +static int32_t I2C13_Master_DmaReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_DmaReceive(addr, data, num, xfer_pending, &I2C13_DmaDriverState); +} + +static int32_t I2C13_Master_DmaGetDataCount(void) +{ + return I2C_Master_DmaGetDataCount(&I2C13_DmaDriverState); +} + +static int32_t I2C13_Master_DmaControl(uint32_t control, uint32_t arg) +{ + return I2C_Master_DmaControl(control, arg, &I2C13_DmaDriverState); +} + +static ARM_I2C_STATUS I2C13_Master_DmaGetStatus(void) +{ + return I2C_Master_DmaGetStatus(&I2C13_DmaDriverState); +} + +#endif + +#else + +static cmsis_i2c_handle_t I2C13_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("i2c13_interrupt_driver_state") +static cmsis_i2c_interrupt_driver_state_t I2C13_InterruptDriverState = { +#else +static cmsis_i2c_interrupt_driver_state_t I2C13_InterruptDriverState = { +#endif + &I2C13_Resource, + &I2C13_Handle, +}; + +static int32_t I2C13_InterruptInitialize(ARM_I2C_SignalEvent_t cb_event) +{ +#ifdef RTE_I2C13_PIN_INIT + RTE_I2C13_PIN_INIT(); +#endif + return I2C_InterruptInitialize(cb_event, &I2C13_InterruptDriverState); +} + +static int32_t I2C13_InterruptUninitialize(void) +{ +#ifdef RTE_I2C13_PIN_DEINIT + RTE_I2C13_PIN_DEINIT(); +#endif + return I2C_InterruptUninitialize(&I2C13_InterruptDriverState); +} + +static int32_t I2C13_InterruptPowerControl(ARM_POWER_STATE state) +{ + return I2C_InterruptPowerControl(state, &I2C13_InterruptDriverState); +} + +static int32_t I2C13_Master_InterruptTransmit(uint32_t addr, const uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptTransmit(addr, data, num, xfer_pending, &I2C13_InterruptDriverState); +} + +static int32_t I2C13_Master_InterruptReceive(uint32_t addr, uint8_t *data, uint32_t num, bool xfer_pending) +{ + return I2C_Master_InterruptReceive(addr, data, num, xfer_pending, &I2C13_InterruptDriverState); +} + +static int32_t I2C13_Slave_InterruptTransmit(const uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptTransmit(data, num, &I2C13_InterruptDriverState); +} + +static int32_t I2C13_Slave_InterruptReceive(uint8_t *data, uint32_t num) +{ + return I2C_Slave_InterruptReceive(data, num, &I2C13_InterruptDriverState); +} + +static int32_t I2C13_InterruptGetDataCount(void) +{ + return I2C_InterruptGetDataCount(&I2C13_InterruptDriverState); +} + +static int32_t I2C13_InterruptControl(uint32_t control, uint32_t arg) +{ + return I2C_InterruptControl(control, arg, &I2C13_InterruptDriverState); +} + +static ARM_I2C_STATUS I2C13_InterruptGetStatus(void) +{ + return I2C_InterruptGetStatus(&I2C13_InterruptDriverState); +} + +#endif + +ARM_DRIVER_I2C Driver_I2C13 = {I2Cx_GetVersion, + I2Cx_GetCapabilities, +#if defined(RTE_I2C13_DMA_EN) && RTE_I2C13_DMA_EN + I2C13_Master_DmaInitialize, + I2C13_Master_DmaUninitialize, + I2C13_Master_DmaPowerControl, + I2C13_Master_DmaTransmit, + I2C13_Master_DmaReceive, + NULL, + NULL, + I2C13_Master_DmaGetDataCount, + I2C13_Master_DmaControl, + I2C13_Master_DmaGetStatus +#else + I2C13_InterruptInitialize, + I2C13_InterruptUninitialize, + I2C13_InterruptPowerControl, + I2C13_Master_InterruptTransmit, + I2C13_Master_InterruptReceive, + I2C13_Slave_InterruptTransmit, + I2C13_Slave_InterruptReceive, + I2C13_InterruptGetDataCount, + I2C13_InterruptControl, + I2C13_InterruptGetStatus +#endif +}; + +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.h new file mode 100644 index 0000000000..d43c6c4d50 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_i2c_cmsis.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2020 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _FSL_I2C_CMSIS_H_ +#define _FSL_I2C_CMSIS_H_ +#include "fsl_common.h" +#include "Driver_I2C.h" +#include "RTE_Device.h" +#include "fsl_i2c.h" +#include "fsl_flexcomm.h" +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +#include "fsl_i2c_dma.h" +#endif + +#if defined(I2C0) && defined(RTE_I2C0) && RTE_I2C0 +extern ARM_DRIVER_I2C Driver_I2C0; +#endif + +#if defined(I2C1) && defined(RTE_I2C1) && RTE_I2C1 +extern ARM_DRIVER_I2C Driver_I2C1; +#endif + +#if defined(I2C2) && defined(RTE_I2C2) && RTE_I2C2 +extern ARM_DRIVER_I2C Driver_I2C2; +#endif + +#if defined(I2C3) && defined(RTE_I2C3) && RTE_I2C3 +extern ARM_DRIVER_I2C Driver_I2C3; +#endif + +#if defined(I2C4) && defined(RTE_I2C4) && RTE_I2C4 +extern ARM_DRIVER_I2C Driver_I2C4; +#endif + +#if defined(I2C5) && defined(RTE_I2C5) && RTE_I2C5 +extern ARM_DRIVER_I2C Driver_I2C5; +#endif + +#if defined(I2C6) && defined(RTE_I2C6) && RTE_I2C6 +extern ARM_DRIVER_I2C Driver_I2C6; +#endif + +#if defined(I2C7) && defined(RTE_I2C7) && RTE_I2C7 +extern ARM_DRIVER_I2C Driver_I2C7; +#endif + +#if defined(I2C8) && defined(RTE_I2C8) && RTE_I2C8 +extern ARM_DRIVER_I2C Driver_I2C8; +#endif + +#if defined(I2C9) && defined(RTE_I2C9) && RTE_I2C9 +extern ARM_DRIVER_I2C Driver_I2C9; +#endif + +#if defined(I2C10) && defined(RTE_I2C10) && RTE_I2C10 +extern ARM_DRIVER_I2C Driver_I2C10; +#endif + +#if defined(I2C11) && defined(RTE_I2C11) && RTE_I2C11 +extern ARM_DRIVER_I2C Driver_I2C11; +#endif + +#if defined(I2C12) && defined(RTE_I2C12) && RTE_I2C12 +extern ARM_DRIVER_I2C Driver_I2C12; +#endif + +#if defined(I2C13) && defined(RTE_I2C13) && RTE_I2C13 +extern ARM_DRIVER_I2C Driver_I2C13; +#endif + +/* I2C Driver state flags */ +#define I2C_FLAG_UNINIT (0UL) +#define I2C_FLAG_INIT (1UL << 0) +#define I2C_FLAG_POWER (1UL << 1) + +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.c new file mode 100644 index 0000000000..2b9a7e76e7 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.c @@ -0,0 +1,3712 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2020 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_spi_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_cmsis" +#endif + +#if ((defined(RTE_SPI0) && RTE_SPI0) || (defined(RTE_SPI1) && RTE_SPI1) || (defined(RTE_SPI2) && RTE_SPI2) || \ + (defined(RTE_SPI3) && RTE_SPI3) || (defined(RTE_SPI4) && RTE_SPI4) || (defined(RTE_SPI5) && RTE_SPI5) || \ + (defined(RTE_SPI6) && RTE_SPI6) || (defined(RTE_SPI7) && RTE_SPI7) || (defined(RTE_SPI8) && RTE_SPI8) || \ + (defined(RTE_SPI9) && RTE_SPI9) || (defined(RTE_SPI10) && RTE_SPI10) || (defined(RTE_SPI11) && RTE_SPI11) || \ + (defined(RTE_SPI12) && RTE_SPI12) || (defined(RTE_SPI13) && RTE_SPI13)) + +#define ARM_SPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 4) /* driver version */ + +/*! @brief IDs of clock for each FLEXCOMM module */ +static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +typedef const struct _cmsis_spi_resource +{ + SPI_Type *base; + uint32_t instance; + uint32_t (*GetFreq)(void); +} cmsis_spi_resource_t; + +typedef union _cmsis_spi_handle +{ + spi_master_handle_t masterHandle; + spi_slave_handle_t slaveHandle; +} cmsis_spi_handle_t; + +typedef struct _cmsis_spi_interrupt_driver_state +{ + cmsis_spi_resource_t *resource; + cmsis_spi_handle_t *handle; + ARM_SPI_SignalEvent_t cb_event; + uint32_t baudRate_Bps; + uint8_t flags; /*!< Control and state flags. */ +} cmsis_spi_interrupt_driver_state_t; + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +typedef const struct _cmsis_spi_dma_resource +{ + DMA_Type *txdmaBase; + uint32_t txdmaChannel; + + DMA_Type *rxdmaBase; + uint32_t rxdmaChannel; +} cmsis_spi_dma_resource_t; + +typedef union _cmsis_spi_dma_handle +{ + spi_dma_handle_t masterHandle; + spi_dma_handle_t slaveHandle; +} cmsis_spi_dma_handle_t; + +typedef struct _cmsis_spi_dma_driver_state +{ + cmsis_spi_resource_t *resource; + cmsis_spi_dma_resource_t *dmaResource; + cmsis_spi_dma_handle_t *handle; + dma_handle_t *dmaRxDataHandle; + dma_handle_t *dmaTxDataHandle; + + uint32_t baudRate_Bps; + ARM_SPI_SignalEvent_t cb_event; + uint8_t flags; /*!< Control and state flags. */ +} cmsis_spi_dma_driver_state_t; +#endif + +/* Driver Version */ +static const ARM_DRIVER_VERSION s_SPIDriverVersion = {ARM_SPI_API_VERSION, ARM_SPI_DRV_VERSION}; + +/* Driver Capabilities */ +static const ARM_SPI_CAPABILITIES s_SPIDriverCapabilities = { + 1, /* Simplex Mode (Master and Slave) */ + 0, /* TI Synchronous Serial Interface */ + 0, /* Microwire Interface */ + 0 /* Signal Mode Fault event: \ref ARM_SPI_EVENT_MODE_FAULT */ +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void SPI_MasterCommonControl(uint32_t control, + cmsis_spi_resource_t *resource, + uint8_t *status, + spi_master_config_t *masterConfig) +{ + switch (resource->instance) + { + case 0: +#if defined(RTE_SPI0_SSEL_NUM) + masterConfig->sselNum = RTE_SPI0_SSEL_NUM; +#endif +#if defined(RTE_SPI0_SSEL_POL) + masterConfig->sselPol = RTE_SPI0_SSEL_POL; +#endif + break; + + case 1: +#if defined(RTE_SPI1_SSEL_NUM) + masterConfig->sselNum = RTE_SPI1_SSEL_NUM; +#endif +#if defined(RTE_SPI1_SSEL_POL) + masterConfig->sselPol = RTE_SPI1_SSEL_POL; +#endif + break; + case 2: +#if defined(RTE_SPI2_SSEL_NUM) + masterConfig->sselNum = RTE_SPI2_SSEL_NUM; +#endif +#if defined(RTE_SPI2_SSEL_POL) + masterConfig->sselPol = RTE_SPI2_SSEL_POL; +#endif + break; + + case 3: +#if defined(RTE_SPI3_SSEL_NUM) + masterConfig->sselNum = RTE_SPI3_SSEL_NUM; +#endif +#if defined(RTE_SPI3_SSEL_POL) + masterConfig->sselPol = RTE_SPI3_SSEL_POL; +#endif + break; + + case 4: +#if defined(RTE_SPI4_SSEL_NUM) + masterConfig->sselNum = RTE_SPI4_SSEL_NUM; +#endif +#if defined(RTE_SPI4_SSEL_POL) + masterConfig->sselPol = RTE_SPI4_SSEL_POL; +#endif + break; + + case 5: +#if defined(RTE_SPI5_SSEL_NUM) + masterConfig->sselNum = RTE_SPI5_SSEL_NUM; +#endif +#if defined(RTE_SPI5_SSEL_POL) + masterConfig->sselPol = RTE_SPI5_SSEL_POL; +#endif + break; + + case 6: +#if defined(RTE_SPI6_SSEL_NUM) + masterConfig->sselNum = RTE_SPI6_SSEL_NUM; +#endif +#if defined(RTE_SPI6_SSEL_POL) + masterConfig->sselPol = RTE_SPI6_SSEL_POL; +#endif + break; + + case 7: +#if defined(RTE_SPI7_SSEL_NUM) + masterConfig->sselNum = RTE_SPI7_SSEL_NUM; +#endif +#if defined(RTE_SPI7_SSEL_POL) + masterConfig->sselPol = RTE_SPI7_SSEL_POL; +#endif + break; + + case 8: +#if defined(RTE_SPI8_SSEL_NUM) + masterConfig->sselNum = RTE_SPI8_SSEL_NUM; +#endif +#if defined(RTE_SPI8_SSEL_POL) + masterConfig->sselPol = RTE_SPI8_SSEL_POL; +#endif + break; + + case 9: +#if defined(RTE_SPI9_SSEL_NUM) + masterConfig->sselNum = RTE_SPI9_SSEL_NUM; +#endif +#if defined(RTE_SPI9_SSEL_POL) + masterConfig->sselPol = RTE_SPI9_SSEL_POL; +#endif + break; + + case 10: +#if defined(RTE_SPI10_SSEL_NUM) + masterConfig->sselNum = RTE_SPI10_SSEL_NUM; +#endif +#if defined(RTE_SPI10_SSEL_POL) + masterConfig->sselPol = RTE_SPI10_SSEL_POL; +#endif + break; + + case 11: +#if defined(RTE_SPI11_SSEL_NUM) + masterConfig->sselNum = RTE_SPI11_SSEL_NUM; +#endif +#if defined(RTE_SPI11_SSEL_POL) + masterConfig->sselPol = RTE_SPI11_SSEL_POL; +#endif + break; + + case 12: +#if defined(RTE_SPI12_SSEL_NUM) + masterConfig->sselNum = RTE_SPI12_SSEL_NUM; +#endif +#if defined(RTE_SPI12_SSEL_POL) + masterConfig->sselPol = RTE_SPI12_SSEL_POL; +#endif + break; + + case 13: +#if defined(RTE_SPI13_SSEL_NUM) + masterConfig->sselNum = RTE_SPI13_SSEL_NUM; +#endif +#if defined(RTE_SPI13_SSEL_POL) + masterConfig->sselPol = RTE_SPI13_SSEL_POL; +#endif + break; + + default: + /* Avoid MISRA 16.4 violation */ + break; + } + + switch (control & ARM_SPI_FRAME_FORMAT_Msk) + { + case ARM_SPI_CPOL0_CPHA0: + masterConfig->polarity = kSPI_ClockPolarityActiveHigh; + masterConfig->phase = kSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL0_CPHA1: + masterConfig->polarity = kSPI_ClockPolarityActiveHigh; + masterConfig->phase = kSPI_ClockPhaseSecondEdge; + break; + + case ARM_SPI_CPOL1_CPHA0: + masterConfig->polarity = kSPI_ClockPolarityActiveLow; + masterConfig->phase = kSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL1_CPHA1: + masterConfig->polarity = kSPI_ClockPolarityActiveLow; + masterConfig->phase = kSPI_ClockPhaseSecondEdge; + break; + + default: + /* Avoid MISRA 16.4 violation */ + break; + } + + if ((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) != 0U) /* setting Number of Data bits */ + { + if ((((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4U) && + (((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16U)) + { + masterConfig->dataWidth = + (spi_data_width_t)(((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1U); + } + } + + switch (control & ARM_SPI_BIT_ORDER_Msk) + { + case ARM_SPI_LSB_MSB: + masterConfig->direction = kSPI_LsbFirst; + break; + case ARM_SPI_MSB_LSB: + masterConfig->direction = kSPI_MsbFirst; + break; + + default: + /* Avoid MISRA 16.4 violation */ + break; + } +} + +static void SPI_SlaveCommonControl(uint32_t control, + cmsis_spi_resource_t *resource, + uint8_t *status, + spi_slave_config_t *slaveConfig) +{ + switch (resource->instance) + { + case 0: +#if defined(RTE_SPI0_SSEL_POL) + slaveConfig->sselPol = RTE_SPI0_SSEL_POL; +#endif + break; + + case 1: +#if defined(RTE_SPI1_SSEL_POL) + slaveConfig->sselPol = RTE_SPI1_SSEL_POL; +#endif + break; + case 2: +#if defined(RTE_SPI2_SSEL_POL) + slaveConfig->sselPol = RTE_SPI2_SSEL_POL; +#endif + break; + + case 3: +#if defined(RTE_SPI3_SSEL_POL) + slaveConfig->sselPol = RTE_SPI3_SSEL_POL; +#endif + break; + + case 4: +#if defined(RTE_SPI4_SSEL_POL) + slaveConfig->sselPol = RTE_SPI4_SSEL_POL; +#endif + break; + + case 5: +#if defined(RTE_SPI5_SSEL_POL) + slaveConfig->sselPol = RTE_SPI5_SSEL_POL; +#endif + break; + + case 6: +#if defined(RTE_SPI6_SSEL_POL) + slaveConfig->sselPol = RTE_SPI6_SSEL_POL; +#endif + break; + + case 7: +#if defined(RTE_SPI7_SSEL_POL) + slaveConfig->sselPol = RTE_SPI7_SSEL_POL; +#endif + break; + + case 8: +#if defined(RTE_SPI8_SSEL_POL) + slaveConfig->sselPol = RTE_SPI8_SSEL_POL; +#endif + break; + + case 9: +#if defined(RTE_SPI9_SSEL_POL) + slaveConfig->sselPol = RTE_SPI9_SSEL_POL; +#endif + break; + + case 10: +#if defined(RTE_SPI10_SSEL_POL) + slaveConfig->sselPol = RTE_SPI10_SSEL_POL; +#endif + break; + + case 11: +#if defined(RTE_SPI11_SSEL_POL) + slaveConfig->sselPol = RTE_SPI11_SSEL_POL; +#endif + break; + + case 12: +#if defined(RTE_SPI12_SSEL_POL) + slaveConfig->sselPol = RTE_SPI12_SSEL_POL; +#endif + break; + + case 13: +#if defined(RTE_SPI13_SSEL_POL) + slaveConfig->sselPol = RTE_SPI13_SSEL_POL; +#endif + break; + + default: + /* Avoid MISRA 16.4 violation */ + break; + } + + switch (control & ARM_SPI_FRAME_FORMAT_Msk) + { + case ARM_SPI_CPOL0_CPHA0: + slaveConfig->polarity = kSPI_ClockPolarityActiveHigh; + slaveConfig->phase = kSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL0_CPHA1: + slaveConfig->polarity = kSPI_ClockPolarityActiveHigh; + slaveConfig->phase = kSPI_ClockPhaseSecondEdge; + break; + + case ARM_SPI_CPOL1_CPHA0: + slaveConfig->polarity = kSPI_ClockPolarityActiveLow; + slaveConfig->phase = kSPI_ClockPhaseFirstEdge; + break; + + case ARM_SPI_CPOL1_CPHA1: + slaveConfig->polarity = kSPI_ClockPolarityActiveLow; + slaveConfig->phase = kSPI_ClockPhaseSecondEdge; + break; + + default: + /* Avoid MISRA 16.4 violation */ + break; + } + if ((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) != 0U) /* setting Number of Data bits */ + { + if ((((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) >= 4U) && + (((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) <= 16U)) + { + slaveConfig->dataWidth = + (spi_data_width_t)(((control & (uint32_t)ARM_SPI_DATA_BITS_Msk) >> ARM_SPI_DATA_BITS_Pos) - 1U); + } + } + switch (control & ARM_SPI_BIT_ORDER_Msk) + { + case ARM_SPI_LSB_MSB: + slaveConfig->direction = kSPI_LsbFirst; + break; + case ARM_SPI_MSB_LSB: + slaveConfig->direction = kSPI_MsbFirst; + break; + + default: + /* Avoid MISRA 16.4 violation */ + break; + } +} + +static ARM_DRIVER_VERSION SPIx_GetVersion(void) +{ + return s_SPIDriverVersion; +} + +static ARM_SPI_CAPABILITIES SPIx_GetCapabilities(void) +{ + return s_SPIDriverCapabilities; +} + +#endif + +#if ((defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN) || (defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN) || \ + (defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN) || (defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN) || \ + (defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN) || (defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN) || \ + (defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN) || (defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN) || \ + (defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN) || (defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN) || \ + (defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN) || (defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN) || \ + (defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN) || (defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN)) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static void KSDK_SPI_MasterDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + if (kStatus_SPI_Error == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + + if (userData != NULL) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} +static void KSDK_SPI_SlaveDMACallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0; + + if (kStatus_Success == status) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + if (kStatus_SPI_Error == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + /* User data is actually CMSIS driver callback. */ + if (userData != NULL) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +static int32_t SPI_DMAInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_dma_driver_state_t *spi) +{ + if (0U == (spi->flags & (uint8_t)SPI_FLAG_INIT)) + { + spi->cb_event = cb_event; + spi->flags = (uint8_t)SPI_FLAG_INIT; + } + return ARM_DRIVER_OK; +} + +static int32_t SPI_DMAUninitialize(cmsis_spi_dma_driver_state_t *spi) +{ + spi->flags = (uint8_t)SPI_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t SPI_DMAPowerControl(ARM_POWER_STATE state, cmsis_spi_dma_driver_state_t *spi) +{ + int32_t result = ARM_DRIVER_OK; + switch (state) + { + case ARM_POWER_OFF: + if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U) + { + SPI_Deinit(spi->resource->base); + + DMA_DisableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); + DMA_DisableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + DMA_Deinit(spi->dmaResource->txdmaBase); + DMA_Deinit(spi->dmaResource->rxdmaBase); + + spi->flags = (uint8_t)SPI_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + case ARM_POWER_FULL: + if (spi->flags == (uint8_t)SPI_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U) + { + /* Driver already powered */ + break; + } + + /* Enable flexcomm clock gate */ + CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]); + /* Init DMA */ + DMA_Init(spi->dmaResource->rxdmaBase); + DMA_Init(spi->dmaResource->txdmaBase); + spi->flags |= (uint8_t)SPI_FLAG_POWER; + break; + default: + /* Avoid MISRA 16.4 violation */ + break; + } + return result; +} + +static int32_t SPI_DMASend(const void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base); + + xfer.rxData = NULL; + xfer.txData = (uint8_t *)data; + xfer.dataSize = num * (((uint32_t)spi_config_p->dataWidth + 8UL) / 8UL); + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + xfer.configFlags |= (uint32_t)kSPI_FrameAssert; + } + + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t SPI_DMAReceive(void *data, uint32_t num, cmsis_spi_dma_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base); + + xfer.txData = NULL; + xfer.rxData = (uint8_t *)data; + xfer.dataSize = num * (((uint32_t)spi_config_p->dataWidth + 8UL) / 8UL); + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + xfer.configFlags |= (uint32_t)kSPI_FrameAssert; + } + + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t SPI_DMATransfer(const void *data_out, void *data_in, uint32_t num, cmsis_spi_dma_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base); + + xfer.txData = (uint8_t *)data_out; + xfer.rxData = (uint8_t *)data_in; + xfer.dataSize = num * (((uint32_t)spi_config_p->dataWidth + 8UL) / 8UL); + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + xfer.configFlags |= (uint32_t)kSPI_FrameAssert; + } + + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + status = SPI_MasterTransferDMA(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + status = SPI_SlaveTransferDMA(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} +static uint32_t SPI_DMAGetCount(cmsis_spi_dma_driver_state_t *spi) +{ + uint32_t cnt; + size_t bytes; + spi_config_t *spi_config_p = (spi_config_t *)SPI_GetConfig(spi->resource->base); + + bytes = DMA_GetRemainingBytes(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + cnt = spi->handle->masterHandle.transferSize - bytes; + } + else + { + cnt = spi->handle->slaveHandle.transferSize - bytes; + } + cnt /= (((uint32_t)spi_config_p->dataWidth + 8U) / 8U); + + return cnt; +} + +static int32_t SPI_DMAControl(uint32_t control, uint32_t arg, cmsis_spi_dma_driver_state_t *spi) +{ + int32_t result = ARM_DRIVER_OK; + bool isContinue = false; + if (0U == (spi->flags & (uint8_t)SPI_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + switch (control & ARM_SPI_CONTROL_Msk) + { + case ARM_SPI_MODE_INACTIVE: + SPI_Enable(spi->resource->base, false); + isContinue = true; + break; + + case ARM_SPI_MODE_MASTER: + spi->baudRate_Bps = arg; + spi->flags |= (uint8_t)SPI_FLAG_MASTER; + isContinue = true; + break; + + case ARM_SPI_MODE_SLAVE: + spi->flags &= ~(uint8_t)SPI_FLAG_MASTER; + isContinue = true; + break; + + case ARM_SPI_SET_BUS_SPEED: + if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + (void)SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq()); + spi->baudRate_Bps = arg; + break; + + case ARM_SPI_GET_BUS_SPEED: /* Set Bus Speed in bps; arg = value */ + if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + result = (int32_t)spi->baudRate_Bps; + break; + + case ARM_SPI_CONTROL_SS: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + case ARM_SPI_ABORT_TRANSFER: + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + SPI_MasterTransferAbortDMA(spi->resource->base, &spi->handle->masterHandle); + } + else + { + SPI_SlaveTransferAbortDMA(spi->resource->base, &spi->handle->slaveHandle); + } + break; + + case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */ + SPI_SetDummyData(spi->resource->base, (uint8_t)arg); + result = ARM_DRIVER_OK; + break; + + case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */ + /* Mode is not supported by current driver. */ + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */ + /* Mode is not supported by current driver. */ + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + default: + isContinue = true; + /* Avoid MISRA 16.4 violation */ + break; + } + + if (!isContinue) + { + return result; + } + + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + switch (control & ARM_SPI_SS_MASTER_MODE_Msk) + { + /* + * Note: + * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or + * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured + * by user in extern file. Besides, ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver. + */ + case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */ + break; + case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */ + break; + case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */ + break; + case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */ + break; + default: + /* Avoid MISRA 16.4 violation */ + break; + } + spi_master_config_t masterConfig; + SPI_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = spi->baudRate_Bps; + SPI_MasterCommonControl(control, spi->resource, &spi->flags, &masterConfig); + + if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U) + { + SPI_Deinit(spi->resource->base); + } + (void)SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq()); + + DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); + DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority3); + DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority2); + DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); + DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + + (void)SPI_MasterTransferCreateHandleDMA(spi->resource->base, &(spi->handle->masterHandle), + KSDK_SPI_MasterDMACallback, (void *)spi->cb_event, spi->dmaTxDataHandle, + spi->dmaRxDataHandle); + spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED; + } + else + { + /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */ + switch (control & ARM_SPI_SS_SLAVE_MODE_Msk) + { + case ARM_SPI_SS_SLAVE_HW: + break; + case ARM_SPI_SS_SLAVE_SW: + break; + default: + /* Avoid MISRA 16.4 violation */ + break; + } + + spi_slave_config_t slaveConfig; + SPI_SlaveGetDefaultConfig(&slaveConfig); + SPI_SlaveCommonControl(control, spi->resource, &spi->flags, &slaveConfig); + + if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U) + { + SPI_Deinit(spi->resource->base); + } + (void)SPI_SlaveInit(spi->resource->base, &slaveConfig); + + DMA_EnableChannel(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); + DMA_EnableChannel(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + DMA_SetChannelPriority(spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel, kDMA_ChannelPriority0); + DMA_SetChannelPriority(spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel, kDMA_ChannelPriority1); + DMA_CreateHandle(spi->dmaTxDataHandle, spi->dmaResource->txdmaBase, spi->dmaResource->txdmaChannel); + DMA_CreateHandle(spi->dmaRxDataHandle, spi->dmaResource->rxdmaBase, spi->dmaResource->rxdmaChannel); + + (void)SPI_SlaveTransferCreateHandleDMA(spi->resource->base, &(spi->handle->slaveHandle), + KSDK_SPI_SlaveDMACallback, (void *)spi->cb_event, spi->dmaTxDataHandle, + spi->dmaRxDataHandle); + + spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED; + } + + return ARM_DRIVER_OK; +} + +static ARM_SPI_STATUS SPI_DMAGetStatus(cmsis_spi_dma_driver_state_t *spi) +{ + ARM_SPI_STATUS stat = {0}; + + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + stat.busy = + ((spi->handle->masterHandle.txInProgress == true) || (spi->handle->masterHandle.rxInProgress == true)) ? + (0U) : + (1U); + stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U); + } + else + { + stat.busy = + ((spi->handle->slaveHandle.txInProgress == true) || (spi->handle->slaveHandle.rxInProgress == true)) ? + (0U) : + (1U); + stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U); + } + stat.mode_fault = 0U; + stat.reserved = 0U; + + return stat; +} +#endif /* defined(FSL_FEATURE_SOC_DMA_COUNT) */ + +#endif + +#if ((defined(RTE_SPI0) && RTE_SPI0 && !(defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN)) || \ + (defined(RTE_SPI1) && RTE_SPI1 && !(defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN)) || \ + (defined(RTE_SPI2) && RTE_SPI2 && !(defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN)) || \ + (defined(RTE_SPI3) && RTE_SPI3 && !(defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN)) || \ + (defined(RTE_SPI4) && RTE_SPI4 && !(defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN)) || \ + (defined(RTE_SPI5) && RTE_SPI5 && !(defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN)) || \ + (defined(RTE_SPI6) && RTE_SPI6 && !(defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN)) || \ + (defined(RTE_SPI7) && RTE_SPI7 && !(defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN)) || \ + (defined(RTE_SPI8) && RTE_SPI8 && !(defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN)) || \ + (defined(RTE_SPI9) && RTE_SPI9 && !(defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN)) || \ + (defined(RTE_SPI10) && RTE_SPI10 && !(defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN)) || \ + (defined(RTE_SPI11) && RTE_SPI11 && !(defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN)) || \ + (defined(RTE_SPI12) && RTE_SPI12 && !(defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN)) || \ + (defined(RTE_SPI13) && RTE_SPI13 && !(defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN))) + +static void KSDK_SPI_MasterInterruptCallback(SPI_Type *base, + spi_master_handle_t *handle, + status_t status, + void *userData) +{ + uint32_t event = 0; + + if ((kStatus_Success == status) || (kStatus_SPI_Idle == status)) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + if (kStatus_SPI_Error == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + + /* User data is actually CMSIS driver callback. */ + if (userData != NULL) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +static void KSDK_SPI_SlaveInterruptCallback(SPI_Type *base, spi_slave_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0; + + if ((kStatus_Success == status) || (kStatus_SPI_Idle == status)) + { + event = ARM_SPI_EVENT_TRANSFER_COMPLETE; + } + + if (kStatus_SPI_Error == status) + { + event = ARM_SPI_EVENT_DATA_LOST; + } + + /* User data is actually CMSIS driver callback. */ + if (userData != NULL) + { + ((ARM_SPI_SignalEvent_t)userData)(event); + } +} + +static int32_t SPI_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event, cmsis_spi_interrupt_driver_state_t *spi) +{ + if (0U == (spi->flags & (uint8_t)SPI_FLAG_INIT)) + { + spi->cb_event = cb_event; + spi->flags = (uint8_t)SPI_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t SPI_InterruptUninitialize(cmsis_spi_interrupt_driver_state_t *spi) +{ + spi->flags = (uint8_t)SPI_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t SPI_InterruptPowerControl(ARM_POWER_STATE state, cmsis_spi_interrupt_driver_state_t *spi) +{ + int32_t result = ARM_DRIVER_OK; + switch (state) + { + case ARM_POWER_OFF: + if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U) + { + SPI_Deinit(spi->resource->base); + spi->flags = (uint8_t)SPI_FLAG_INIT; + } + break; + + case ARM_POWER_LOW: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + case ARM_POWER_FULL: + if (spi->flags == (uint8_t)SPI_FLAG_UNINIT) + { + return ARM_DRIVER_ERROR; + } + + if ((spi->flags & (uint8_t)SPI_FLAG_POWER) != 0U) + { + /* Driver already powered */ + break; + } + + /* Enable flexcomm clock gate */ + CLOCK_EnableClock(s_flexcommClocks[spi->resource->instance]); + spi->flags |= (uint8_t)SPI_FLAG_POWER; + break; + default: + /* Avoid MISRA 16.4 violation */ + break; + } + + return result; +} + +static int32_t SPI_InterruptSend(const void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + + xfer.rxData = NULL; + xfer.txData = (uint8_t *)data; + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + xfer.configFlags |= (uint32_t)kSPI_FrameAssert; + } + + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + xfer.dataSize = num * (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL); + status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + xfer.dataSize = num * (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL); + status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t SPI_InterruptReceive(void *data, uint32_t num, cmsis_spi_interrupt_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + + xfer.txData = NULL; + xfer.rxData = (uint8_t *)data; + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + xfer.configFlags |= (uint32_t)kSPI_FrameAssert; + } + + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + xfer.dataSize = num * (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL); + status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + xfer.dataSize = num * (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL); + status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t SPI_InterruptTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_spi_interrupt_driver_state_t *spi) +{ + int32_t ret; + status_t status; + spi_transfer_t xfer = {0}; + + xfer.txData = (uint8_t *)data_out; + xfer.rxData = (uint8_t *)data_in; + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + xfer.configFlags |= (uint32_t)kSPI_FrameAssert; + } + + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + xfer.dataSize = num * (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL); + status = SPI_MasterTransferNonBlocking(spi->resource->base, &spi->handle->masterHandle, &xfer); + } + else + { + xfer.dataSize = num * (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL); + status = SPI_SlaveTransferNonBlocking(spi->resource->base, &spi->handle->slaveHandle, &xfer); + } + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_SPI_Busy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} +static uint32_t SPI_InterruptGetCount(cmsis_spi_interrupt_driver_state_t *spi) +{ + uint32_t cnt; + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + cnt = spi->handle->masterHandle.totalByteCount - spi->handle->masterHandle.rxRemainingBytes; + cnt /= (((uint32_t)spi->handle->masterHandle.dataWidth + 8UL) / 8UL); + } + else + { + cnt = spi->handle->slaveHandle.totalByteCount - spi->handle->slaveHandle.rxRemainingBytes; + cnt /= (((uint32_t)spi->handle->slaveHandle.dataWidth + 8UL) / 8UL); + } + + return cnt; +} + +static int32_t SPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_spi_interrupt_driver_state_t *spi) +{ + int32_t result = ARM_DRIVER_OK; + bool isContinue = false; + if (0U == (spi->flags & (uint8_t)SPI_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + switch (control & ARM_SPI_CONTROL_Msk) + { + case ARM_SPI_MODE_INACTIVE: /* SPI mode Inactive */ + (void)FLEXCOMM_Init(spi->resource->base, FLEXCOMM_PERIPH_NONE); + isContinue = true; + break; + + case ARM_SPI_MODE_MASTER: /* SPI Master (Output on MOSI, Input on MISO); arg = Bus Speed in bps */ + spi->baudRate_Bps = arg; + spi->flags |= (uint8_t)SPI_FLAG_MASTER; + isContinue = true; + break; + + case ARM_SPI_MODE_SLAVE: /* SPI Slave (Output on MISO, Input on MOSI) */ + spi->flags &= ~(uint8_t)SPI_FLAG_MASTER; + isContinue = true; + break; + + case ARM_SPI_GET_BUS_SPEED: /* Get Bus Speed in bps */ + if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + result = (int32_t)spi->baudRate_Bps; + break; + + case ARM_SPI_SET_BUS_SPEED: /* Set Bus Speed in bps; */ + if (0U == (spi->flags & (uint8_t)SPI_FLAG_MASTER)) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + (void)SPI_MasterSetBaud(spi->resource->base, arg, spi->resource->GetFreq()); + spi->baudRate_Bps = arg; + break; + + case ARM_SPI_CONTROL_SS: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + case ARM_SPI_ABORT_TRANSFER: /* Abort current data transfer */ + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + SPI_MasterTransferAbort(spi->resource->base, &spi->handle->masterHandle); + } + else + { + SPI_SlaveTransferAbort(spi->resource->base, &spi->handle->slaveHandle); + } + break; + + case ARM_SPI_SET_DEFAULT_TX_VALUE: /* Set default Transmit value; arg = value */ + SPI_SetDummyData(spi->resource->base, (uint8_t)arg); + break; + + case ARM_SPI_MODE_MASTER_SIMPLEX: /* SPI Master (Output/Input on MOSI); arg = Bus Speed in bps */ + /* Mode is not supported by current driver. */ + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + case ARM_SPI_MODE_SLAVE_SIMPLEX: /* SPI Slave (Output/Input on MISO) */ + /* Mode is not supported by current driver. */ + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + + default: + isContinue = true; + /* Avoid MISRA 16.4 violation */ + break; + } + + if (!isContinue) + { + return result; + } + + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + switch (control & ARM_SPI_SS_MASTER_MODE_Msk) + { + /* + * Note: + * ARM_SPI_SS_MASTER_HW_OUTPUT is default configuration in driver, if ARM_SPI_SS_MASTER_UNUSED or + * ARM_SPI_SS_MASTER_SW is wanted, please disable pin function in SPIx_InitPins() which is configured + * by user in extern file. Besides ARM_SPI_SS_MASTER_HW_INPUT is not supported in this driver. + */ + case ARM_SPI_SS_MASTER_UNUSED: /*!< SPI Slave Select when Master: Not used */ + break; + case ARM_SPI_SS_MASTER_SW: /*!< SPI Slave Select when Master: Software controlled. */ + break; + case ARM_SPI_SS_MASTER_HW_OUTPUT: /*!< SPI Slave Select when Master: Hardware controlled Output */ + break; + case ARM_SPI_SS_MASTER_HW_INPUT: /*!< SPI Slave Select when Master: Hardware monitored Input */ + break; + default: + /* Avoid MISRA 16.4 violation */ + break; + } + + spi_master_config_t masterConfig; + SPI_MasterGetDefaultConfig(&masterConfig); + masterConfig.baudRate_Bps = spi->baudRate_Bps; + + SPI_MasterCommonControl(control, spi->resource, &spi->flags, &masterConfig); + + if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U) + { + SPI_Deinit(spi->resource->base); + } + (void)SPI_MasterInit(spi->resource->base, &masterConfig, spi->resource->GetFreq()); + (void)SPI_MasterTransferCreateHandle(spi->resource->base, &spi->handle->masterHandle, + KSDK_SPI_MasterInterruptCallback, (void *)spi->cb_event); + spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED; + } + else + { + /* The SPI slave select is controlled by hardware, software mode is not supported by current driver. */ + switch (control & ARM_SPI_SS_SLAVE_MODE_Msk) + { + case ARM_SPI_SS_SLAVE_HW: + break; + case ARM_SPI_SS_SLAVE_SW: + break; + default: + /* Avoid MISRA 16.4 violation */ + break; + } + + spi_slave_config_t slaveConfig; + SPI_SlaveGetDefaultConfig(&slaveConfig); + + SPI_SlaveCommonControl(control, spi->resource, &spi->flags, &slaveConfig); + + if ((spi->flags & (uint8_t)SPI_FLAG_CONFIGURED) != 0U) + { + SPI_Deinit(spi->resource->base); + } + (void)SPI_SlaveInit(spi->resource->base, &slaveConfig); + (void)SPI_SlaveTransferCreateHandle(spi->resource->base, &spi->handle->slaveHandle, + KSDK_SPI_SlaveInterruptCallback, (void *)spi->cb_event); + spi->flags |= (uint8_t)SPI_FLAG_CONFIGURED; + } + + return ARM_DRIVER_OK; +} + +static ARM_SPI_STATUS SPI_InterruptGetStatus(cmsis_spi_interrupt_driver_state_t *spi) +{ + ARM_SPI_STATUS stat = {0}; + + if ((spi->flags & (uint8_t)SPI_FLAG_MASTER) != 0U) + { + stat.busy = + ((spi->handle->masterHandle.txRemainingBytes > 0U) || (spi->handle->masterHandle.rxRemainingBytes > 0U)) ? + (0U) : + (1U); + stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->masterHandle.state) ? (1U) : (0U); + } + else + { + stat.busy = + ((spi->handle->slaveHandle.txRemainingBytes > 0U) || (spi->handle->slaveHandle.rxRemainingBytes > 0U)) ? + (0U) : + (1U); + stat.data_lost = ((uint8_t)kStatus_SPI_Error == spi->handle->slaveHandle.state) ? (1U) : (0U); + } + stat.mode_fault = 0U; + stat.reserved = 0U; + + return stat; +} + +#endif + +#if defined(SPI0) && defined(RTE_SPI0) && RTE_SPI0 + +/* User needs to provide the implementation for SPI0_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI0_GetFreq(void); + +static cmsis_spi_resource_t SPI0_Resource = {SPI0, 0, SPI0_GetFreq}; + +#if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI0_DMAResource = {RTE_SPI0_DMA_TX_DMA_BASE, RTE_SPI0_DMA_TX_CH, + RTE_SPI0_DMA_RX_DMA_BASE, RTE_SPI0_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI0_DmaHandle; +static dma_handle_t SPI0_DmaTxDataHandle; +static dma_handle_t SPI0_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi0_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI0_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI0_DMADriverState = { +#endif + &SPI0_Resource, &SPI0_DMAResource, &SPI0_DmaHandle, &SPI0_DmaTxDataHandle, &SPI0_DmaRxDataHandle, + +}; + +static int32_t SPI0_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI0_PIN_INIT + RTE_SPI0_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI0_DMADriverState); +} + +static int32_t SPI0_DMAUninitialize(void) +{ +#ifdef RTE_SPI0_PIN_DEINIT + RTE_SPI0_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI0_DMADriverState); +} + +static int32_t SPI0_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI0_DMADriverState); +} + +static int32_t SPI0_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI0_DMADriverState); +} + +static int32_t SPI0_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI0_DMADriverState); +} + +static int32_t SPI0_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI0_DMADriverState); +} + +static uint32_t SPI0_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI0_DMADriverState); +} + +static int32_t SPI0_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI0_DMADriverState); +} + +static ARM_SPI_STATUS SPI0_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI0_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI0_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi0_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI0_InterruptDriverState = { +#endif + &SPI0_Resource, + &SPI0_Handle, +}; + +static int32_t SPI0_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI0_PIN_INIT + RTE_SPI0_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptUninitialize(void) +{ +#ifdef RTE_SPI0_PIN_DEINIT + RTE_SPI0_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI0_InterruptDriverState); +} + +static uint32_t SPI0_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI0_InterruptDriverState); +} + +static int32_t SPI0_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI0_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI0_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI0_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI0 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI0_DMA_EN) && RTE_SPI0_DMA_EN + SPI0_DMAInitialize, SPI0_DMAUninitialize, SPI0_DMAPowerControl, SPI0_DMASend, + SPI0_DMAReceive, SPI0_DMATransfer, SPI0_DMAGetCount, SPI0_DMAControl, + SPI0_DMAGetStatus +#else + SPI0_InterruptInitialize, + SPI0_InterruptUninitialize, + SPI0_InterruptPowerControl, + SPI0_InterruptSend, + SPI0_InterruptReceive, + SPI0_InterruptTransfer, + SPI0_InterruptGetCount, + SPI0_InterruptControl, + SPI0_InterruptGetStatus +#endif +}; + +#endif /* SPI0 */ + +#if defined(SPI1) && defined(RTE_SPI1) && RTE_SPI1 +/* User needs to provide the implementation for SPI1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI1_GetFreq(void); +static cmsis_spi_resource_t SPI1_Resource = {SPI1, 1, SPI1_GetFreq}; + +#if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI1_DMAResource = {RTE_SPI1_DMA_TX_DMA_BASE, RTE_SPI1_DMA_TX_CH, + RTE_SPI1_DMA_RX_DMA_BASE, RTE_SPI1_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI1_DmaHandle; +static dma_handle_t SPI1_DmaTxDataHandle; +static dma_handle_t SPI1_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi1_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI1_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI1_DMADriverState = { +#endif + &SPI1_Resource, &SPI1_DMAResource, &SPI1_DmaHandle, &SPI1_DmaRxDataHandle, &SPI1_DmaTxDataHandle, +}; + +static int32_t SPI1_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI1_PIN_INIT + RTE_SPI1_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI1_DMADriverState); +} + +static int32_t SPI1_DMAUninitialize(void) +{ +#ifdef RTE_SPI1_PIN_DEINIT + RTE_SPI1_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI1_DMADriverState); +} + +static int32_t SPI1_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI1_DMADriverState); +} + +static int32_t SPI1_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI1_DMADriverState); +} + +static int32_t SPI1_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI1_DMADriverState); +} + +static int32_t SPI1_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI1_DMADriverState); +} + +static uint32_t SPI1_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI1_DMADriverState); +} + +static int32_t SPI1_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI1_DMADriverState); +} + +static ARM_SPI_STATUS SPI1_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI1_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI1_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi1_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI1_InterruptDriverState = { +#endif + &SPI1_Resource, + &SPI1_Handle, +}; + +static int32_t SPI1_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI1_PIN_INIT + RTE_SPI1_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptUninitialize(void) +{ +#ifdef RTE_SPI1_PIN_DEINIT + RTE_SPI1_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI1_InterruptDriverState); +} + +static uint32_t SPI1_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI1_InterruptDriverState); +} + +static int32_t SPI1_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI1_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI1_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI1_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI1 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI1_DMA_EN) && RTE_SPI1_DMA_EN + SPI1_DMAInitialize, SPI1_DMAUninitialize, SPI1_DMAPowerControl, SPI1_DMASend, + SPI1_DMAReceive, SPI1_DMATransfer, SPI1_DMAGetCount, SPI1_DMAControl, + SPI1_DMAGetStatus +#else + SPI1_InterruptInitialize, + SPI1_InterruptUninitialize, + SPI1_InterruptPowerControl, + SPI1_InterruptSend, + SPI1_InterruptReceive, + SPI1_InterruptTransfer, + SPI1_InterruptGetCount, + SPI1_InterruptControl, + SPI1_InterruptGetStatus +#endif +}; + +#endif /* SPI1 */ + +#if defined(SPI2) && defined(RTE_SPI2) && RTE_SPI2 + +/* User needs to provide the implementation for SPI2_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI2_GetFreq(void); + +static cmsis_spi_resource_t SPI2_Resource = {SPI2, 2, SPI2_GetFreq}; + +#if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI2_DMAResource = {RTE_SPI2_DMA_TX_DMA_BASE, RTE_SPI2_DMA_TX_CH, + RTE_SPI2_DMA_RX_DMA_BASE, RTE_SPI2_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI2_DmaHandle; +static dma_handle_t SPI2_DmaTxDataHandle; +static dma_handle_t SPI2_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi2_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI2_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI2_DMADriverState = { +#endif + &SPI2_Resource, &SPI2_DMAResource, &SPI2_DmaHandle, &SPI2_DmaRxDataHandle, &SPI2_DmaTxDataHandle, +}; + +static int32_t SPI2_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI2_PIN_INIT + RTE_SPI2_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI2_DMADriverState); +} + +static int32_t SPI2_DMAUninitialize(void) +{ +#ifdef RTE_SPI2_PIN_DEINIT + RTE_SPI2_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI2_DMADriverState); +} + +static int32_t SPI2_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI2_DMADriverState); +} + +static int32_t SPI2_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI2_DMADriverState); +} + +static int32_t SPI2_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI2_DMADriverState); +} + +static int32_t SPI2_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI2_DMADriverState); +} + +static uint32_t SPI2_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI2_DMADriverState); +} + +static int32_t SPI2_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI2_DMADriverState); +} + +static ARM_SPI_STATUS SPI2_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI2_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI2_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi2_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI2_InterruptDriverState = { +#endif + &SPI2_Resource, + &SPI2_Handle, +}; + +static int32_t SPI2_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI2_PIN_INIT + RTE_SPI2_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptUninitialize(void) +{ +#ifdef RTE_SPI2_PIN_DEINIT + RTE_SPI2_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI2_InterruptDriverState); +} + +static uint32_t SPI2_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI2_InterruptDriverState); +} + +static int32_t SPI2_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI2_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI2_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI2_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI2 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI2_DMA_EN) && RTE_SPI2_DMA_EN + SPI2_DMAInitialize, SPI2_DMAUninitialize, SPI2_DMAPowerControl, SPI2_DMASend, + SPI2_DMAReceive, SPI2_DMATransfer, SPI2_DMAGetCount, SPI2_DMAControl, + SPI2_DMAGetStatus +#else + SPI2_InterruptInitialize, + SPI2_InterruptUninitialize, + SPI2_InterruptPowerControl, + SPI2_InterruptSend, + SPI2_InterruptReceive, + SPI2_InterruptTransfer, + SPI2_InterruptGetCount, + SPI2_InterruptControl, + SPI2_InterruptGetStatus +#endif +}; + +#endif /* SPI2 */ + +#if defined(SPI3) && defined(RTE_SPI3) && RTE_SPI3 + +/* User needs to provide the implementation for SPI3_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI3_GetFreq(void); + +static cmsis_spi_resource_t SPI3_Resource = {SPI3, 3, SPI3_GetFreq}; + +#if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI3_DMAResource = {RTE_SPI3_DMA_TX_DMA_BASE, RTE_SPI3_DMA_TX_CH, + RTE_SPI3_DMA_RX_DMA_BASE, RTE_SPI3_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI3_DmaHandle; +static dma_handle_t SPI3_DmaTxDataHandle; +static dma_handle_t SPI3_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi3_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI3_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI3_DMADriverState = { +#endif + &SPI3_Resource, &SPI3_DMAResource, &SPI3_DmaHandle, &SPI3_DmaRxDataHandle, &SPI3_DmaTxDataHandle, +}; + +static int32_t SPI3_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI3_PIN_INIT + RTE_SPI3_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI3_DMADriverState); +} + +static int32_t SPI3_DMAUninitialize(void) +{ +#ifdef RTE_SPI3_PIN_DEINIT + RTE_SPI3_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI3_DMADriverState); +} + +static int32_t SPI3_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI3_DMADriverState); +} + +static int32_t SPI3_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI3_DMADriverState); +} + +static int32_t SPI3_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI3_DMADriverState); +} + +static int32_t SPI3_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI3_DMADriverState); +} + +static uint32_t SPI3_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI3_DMADriverState); +} + +static int32_t SPI3_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI3_DMADriverState); +} + +static ARM_SPI_STATUS SPI3_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI3_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI3_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi3_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI3_InterruptDriverState = { +#endif + &SPI3_Resource, + &SPI3_Handle, +}; + +static int32_t SPI3_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI3_PIN_INIT + RTE_SPI3_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptUninitialize(void) +{ +#ifdef RTE_SPI3_PIN_DEINIT + RTE_SPI3_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI3_InterruptDriverState); +} + +static uint32_t SPI3_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI3_InterruptDriverState); +} + +static int32_t SPI3_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI3_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI3_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI3_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI3 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI3_DMA_EN) && RTE_SPI3_DMA_EN + SPI3_DMAInitialize, SPI3_DMAUninitialize, SPI3_DMAPowerControl, SPI3_DMASend, + SPI3_DMAReceive, SPI3_DMATransfer, SPI3_DMAGetCount, SPI3_DMAControl, + SPI3_DMAGetStatus +#else + SPI3_InterruptInitialize, + SPI3_InterruptUninitialize, + SPI3_InterruptPowerControl, + SPI3_InterruptSend, + SPI3_InterruptReceive, + SPI3_InterruptTransfer, + SPI3_InterruptGetCount, + SPI3_InterruptControl, + SPI3_InterruptGetStatus +#endif +}; + +#endif /* SPI3 */ + +#if defined(SPI4) && defined(RTE_SPI4) && RTE_SPI4 + +/* User needs to provide the implementation for SPI4_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI4_GetFreq(void); + +static cmsis_spi_resource_t SPI4_Resource = {SPI4, 4, SPI4_GetFreq}; + +#if defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI4_DMAResource = {RTE_SPI4_DMA_TX_DMA_BASE, RTE_SPI4_DMA_TX_CH, + RTE_SPI4_DMA_RX_DMA_BASE, RTE_SPI4_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI4_DmaHandle; +static dma_handle_t SPI4_DmaTxDataHandle; +static dma_handle_t SPI4_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi4_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI4_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI4_DMADriverState = { +#endif + &SPI4_Resource, &SPI4_DMAResource, &SPI4_DmaHandle, &SPI4_DmaRxDataHandle, &SPI4_DmaTxDataHandle, +}; + +static int32_t SPI4_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI4_PIN_INIT + RTE_SPI4_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI4_DMADriverState); +} + +static int32_t SPI4_DMAUninitialize(void) +{ +#ifdef RTE_SPI4_PIN_DEINIT + RTE_SPI4_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI4_DMADriverState); +} + +static int32_t SPI4_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI4_DMADriverState); +} + +static int32_t SPI4_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI4_DMADriverState); +} + +static int32_t SPI4_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI4_DMADriverState); +} + +static int32_t SPI4_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI4_DMADriverState); +} + +static uint32_t SPI4_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI4_DMADriverState); +} + +static int32_t SPI4_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI4_DMADriverState); +} + +static ARM_SPI_STATUS SPI4_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI4_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI4_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi4_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI4_InterruptDriverState = { +#endif + &SPI4_Resource, + &SPI4_Handle, +}; + +static int32_t SPI4_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI4_PIN_INIT + RTE_SPI4_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptUninitialize(void) +{ +#ifdef RTE_SPI4_PIN_DEINIT + RTE_SPI4_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI4_InterruptDriverState); +} + +static uint32_t SPI4_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI4_InterruptDriverState); +} + +static int32_t SPI4_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI4_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI4_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI4_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI4 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI4_DMA_EN) && RTE_SPI4_DMA_EN + SPI4_DMAInitialize, SPI4_DMAUninitialize, SPI4_DMAPowerControl, SPI4_DMASend, + SPI4_DMAReceive, SPI4_DMATransfer, SPI4_DMAGetCount, SPI4_DMAControl, + SPI4_DMAGetStatus +#else + SPI4_InterruptInitialize, + SPI4_InterruptUninitialize, + SPI4_InterruptPowerControl, + SPI4_InterruptSend, + SPI4_InterruptReceive, + SPI4_InterruptTransfer, + SPI4_InterruptGetCount, + SPI4_InterruptControl, + SPI4_InterruptGetStatus +#endif +}; + +#endif /* SPI4 */ + +#if defined(SPI5) && defined(RTE_SPI5) && RTE_SPI5 + +/* User needs to provide the implementation for SPI5_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI5_GetFreq(void); + +static cmsis_spi_resource_t SPI5_Resource = {SPI5, 5, SPI5_GetFreq}; + +#if defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI5_DMAResource = {RTE_SPI5_DMA_TX_DMA_BASE, RTE_SPI5_DMA_TX_CH, + RTE_SPI5_DMA_RX_DMA_BASE, RTE_SPI5_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI5_DmaHandle; +static dma_handle_t SPI5_DmaTxDataHandle; +static dma_handle_t SPI5_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi5_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI5_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI5_DMADriverState = { +#endif + &SPI5_Resource, &SPI5_DMAResource, &SPI5_DmaHandle, &SPI5_DmaRxDataHandle, &SPI5_DmaTxDataHandle, +}; + +static int32_t SPI5_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI5_PIN_INIT + RTE_SPI5_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI5_DMADriverState); +} + +static int32_t SPI5_DMAUninitialize(void) +{ +#ifdef RTE_SPI5_PIN_DEINIT + RTE_SPI5_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI5_DMADriverState); +} + +static int32_t SPI5_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI5_DMADriverState); +} + +static int32_t SPI5_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI5_DMADriverState); +} + +static int32_t SPI5_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI5_DMADriverState); +} + +static int32_t SPI5_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI5_DMADriverState); +} + +static uint32_t SPI5_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI5_DMADriverState); +} + +static int32_t SPI5_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI5_DMADriverState); +} + +static ARM_SPI_STATUS SPI5_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI5_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI5_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi5_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI5_InterruptDriverState = { +#endif + &SPI5_Resource, + &SPI5_Handle, +}; + +static int32_t SPI5_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI5_PIN_INIT + RTE_SPI5_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptUninitialize(void) +{ +#ifdef RTE_SPI5_PIN_DEINIT + RTE_SPI5_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI5_InterruptDriverState); +} + +static uint32_t SPI5_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI5_InterruptDriverState); +} + +static int32_t SPI5_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI5_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI5_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI5_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI5 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI5_DMA_EN) && RTE_SPI5_DMA_EN + SPI5_DMAInitialize, SPI5_DMAUninitialize, SPI5_DMAPowerControl, SPI5_DMASend, + SPI5_DMAReceive, SPI5_DMATransfer, SPI5_DMAGetCount, SPI5_DMAControl, + SPI5_DMAGetStatus +#else + SPI5_InterruptInitialize, + SPI5_InterruptUninitialize, + SPI5_InterruptPowerControl, + SPI5_InterruptSend, + SPI5_InterruptReceive, + SPI5_InterruptTransfer, + SPI5_InterruptGetCount, + SPI5_InterruptControl, + SPI5_InterruptGetStatus +#endif +}; + +#endif /* SPI5 */ + +#if defined(SPI6) && defined(RTE_SPI6) && RTE_SPI6 + +/* User needs to provide the implementation for SPI6_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI6_GetFreq(void); + +static cmsis_spi_resource_t SPI6_Resource = {SPI6, 6, SPI6_GetFreq}; + +#if defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI6_DMAResource = {RTE_SPI6_DMA_TX_DMA_BASE, RTE_SPI6_DMA_TX_CH, + RTE_SPI6_DMA_RX_DMA_BASE, RTE_SPI6_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI6_DmaHandle; +static dma_handle_t SPI6_DmaTxDataHandle; +static dma_handle_t SPI6_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi6_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI6_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI6_DMADriverState = { +#endif + &SPI6_Resource, &SPI6_DMAResource, &SPI6_DmaHandle, &SPI6_DmaRxDataHandle, &SPI6_DmaTxDataHandle, +}; + +static int32_t SPI6_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI6_PIN_INIT + RTE_SPI6_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI6_DMADriverState); +} + +static int32_t SPI6_DMAUninitialize(void) +{ +#ifdef RTE_SPI6_PIN_DEINIT + RTE_SPI6_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI6_DMADriverState); +} + +static int32_t SPI6_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI6_DMADriverState); +} + +static int32_t SPI6_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI6_DMADriverState); +} + +static int32_t SPI6_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI6_DMADriverState); +} + +static int32_t SPI6_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI6_DMADriverState); +} + +static uint32_t SPI6_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI6_DMADriverState); +} + +static int32_t SPI6_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI6_DMADriverState); +} + +static ARM_SPI_STATUS SPI6_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI6_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI6_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi6_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI6_InterruptDriverState = { +#endif + &SPI6_Resource, + &SPI6_Handle, +}; + +static int32_t SPI6_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI6_PIN_INIT + RTE_SPI6_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptUninitialize(void) +{ +#ifdef RTE_SPI6_PIN_DEINIT + RTE_SPI6_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI6_InterruptDriverState); +} + +static uint32_t SPI6_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI6_InterruptDriverState); +} + +static int32_t SPI6_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI6_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI6_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI6_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI6 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI6_DMA_EN) && RTE_SPI6_DMA_EN + SPI6_DMAInitialize, SPI6_DMAUninitialize, SPI6_DMAPowerControl, SPI6_DMASend, + SPI6_DMAReceive, SPI6_DMATransfer, SPI6_DMAGetCount, SPI6_DMAControl, + SPI6_DMAGetStatus +#else + SPI6_InterruptInitialize, + SPI6_InterruptUninitialize, + SPI6_InterruptPowerControl, + SPI6_InterruptSend, + SPI6_InterruptReceive, + SPI6_InterruptTransfer, + SPI6_InterruptGetCount, + SPI6_InterruptControl, + SPI6_InterruptGetStatus +#endif +}; + +#endif /* SPI6 */ + +#if defined(SPI7) && defined(RTE_SPI7) && RTE_SPI7 + +/* User needs to provide the implementation for SPI7_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI7_GetFreq(void); + +static cmsis_spi_resource_t SPI7_Resource = {SPI7, 7, SPI7_GetFreq}; + +#if defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI7_DMAResource = {RTE_SPI7_DMA_TX_DMA_BASE, RTE_SPI7_DMA_TX_CH, + RTE_SPI7_DMA_RX_DMA_BASE, RTE_SPI7_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI7_DmaHandle; +static dma_handle_t SPI7_DmaTxDataHandle; +static dma_handle_t SPI7_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi7_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI7_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI7_DMADriverState = { +#endif + &SPI7_Resource, &SPI7_DMAResource, &SPI7_DmaHandle, &SPI7_DmaRxDataHandle, &SPI7_DmaTxDataHandle, +}; + +static int32_t SPI7_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI7_PIN_INIT + RTE_SPI7_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI7_DMADriverState); +} + +static int32_t SPI7_DMAUninitialize(void) +{ +#ifdef RTE_SPI7_PIN_DEINIT + RTE_SPI7_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI7_DMADriverState); +} + +static int32_t SPI7_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI7_DMADriverState); +} + +static int32_t SPI7_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI7_DMADriverState); +} + +static int32_t SPI7_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI7_DMADriverState); +} + +static int32_t SPI7_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI7_DMADriverState); +} + +static uint32_t SPI7_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI7_DMADriverState); +} + +static int32_t SPI7_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI7_DMADriverState); +} + +static ARM_SPI_STATUS SPI7_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI7_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI7_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi7_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI7_InterruptDriverState = { +#endif + &SPI7_Resource, + &SPI7_Handle, +}; + +static int32_t SPI7_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI7_PIN_INIT + RTE_SPI7_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptUninitialize(void) +{ +#ifdef RTE_SPI7_PIN_DEINIT + RTE_SPI7_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI7_InterruptDriverState); +} + +static uint32_t SPI7_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI7_InterruptDriverState); +} + +static int32_t SPI7_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI7_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI7_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI7_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI7 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI7_DMA_EN) && RTE_SPI7_DMA_EN + SPI7_DMAInitialize, SPI7_DMAUninitialize, SPI7_DMAPowerControl, SPI7_DMASend, + SPI7_DMAReceive, SPI7_DMATransfer, SPI7_DMAGetCount, SPI7_DMAControl, + SPI7_DMAGetStatus +#else + SPI7_InterruptInitialize, + SPI7_InterruptUninitialize, + SPI7_InterruptPowerControl, + SPI7_InterruptSend, + SPI7_InterruptReceive, + SPI7_InterruptTransfer, + SPI7_InterruptGetCount, + SPI7_InterruptControl, + SPI7_InterruptGetStatus +#endif +}; + +#endif /* SPI7 */ + +#if defined(SPI8) && defined(RTE_SPI8) && RTE_SPI8 + +/* User needs to provide the implementation for SPI8_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI8_GetFreq(void); + +static cmsis_spi_resource_t SPI8_Resource = {SPI8, 8, SPI8_GetFreq}; + +#if defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI8_DMAResource = {RTE_SPI8_DMA_TX_DMA_BASE, RTE_SPI8_DMA_TX_CH, + RTE_SPI8_DMA_RX_DMA_BASE, RTE_SPI8_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI8_DmaHandle; +static dma_handle_t SPI8_DmaTxDataHandle; +static dma_handle_t SPI8_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi8_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI8_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI8_DMADriverState = { +#endif + &SPI8_Resource, &SPI8_DMAResource, &SPI8_DmaHandle, &SPI8_DmaRxDataHandle, &SPI8_DmaTxDataHandle, +}; + +static int32_t SPI8_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI8_PIN_INIT + RTE_SPI8_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI8_DMADriverState); +} + +static int32_t SPI8_DMAUninitialize(void) +{ +#ifdef RTE_SPI8_PIN_DEINIT + RTE_SPI8_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI8_DMADriverState); +} + +static int32_t SPI8_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI8_DMADriverState); +} + +static int32_t SPI8_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI8_DMADriverState); +} + +static int32_t SPI8_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI8_DMADriverState); +} + +static int32_t SPI8_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI8_DMADriverState); +} + +static uint32_t SPI8_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI8_DMADriverState); +} + +static int32_t SPI8_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI8_DMADriverState); +} + +static ARM_SPI_STATUS SPI8_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI8_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI8_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi8_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI8_InterruptDriverState = { +#endif + &SPI8_Resource, + &SPI8_Handle, +}; + +static int32_t SPI8_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI8_PIN_INIT + RTE_SPI8_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptUninitialize(void) +{ +#ifdef RTE_SPI8_PIN_DEINIT + RTE_SPI8_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI8_InterruptDriverState); +} + +static uint32_t SPI8_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI8_InterruptDriverState); +} + +static int32_t SPI8_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI8_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI8_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI8_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI8 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI8_DMA_EN) && RTE_SPI8_DMA_EN + SPI8_DMAInitialize, SPI8_DMAUninitialize, SPI8_DMAPowerControl, SPI8_DMASend, + SPI8_DMAReceive, SPI8_DMATransfer, SPI8_DMAGetCount, SPI8_DMAControl, + SPI8_DMAGetStatus +#else + SPI8_InterruptInitialize, + SPI8_InterruptUninitialize, + SPI8_InterruptPowerControl, + SPI8_InterruptSend, + SPI8_InterruptReceive, + SPI8_InterruptTransfer, + SPI8_InterruptGetCount, + SPI8_InterruptControl, + SPI8_InterruptGetStatus +#endif +}; + +#endif /* SPI8 */ + +#if defined(SPI9) && defined(RTE_SPI9) && RTE_SPI9 + +/* User needs to provide the implementation for SPI9_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI9_GetFreq(void); + +static cmsis_spi_resource_t SPI9_Resource = {SPI9, 9, SPI9_GetFreq}; + +#if defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI9_DMAResource = {RTE_SPI9_DMA_TX_DMA_BASE, RTE_SPI9_DMA_TX_CH, + RTE_SPI9_DMA_RX_DMA_BASE, RTE_SPI9_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI9_DmaHandle; +static dma_handle_t SPI9_DmaTxDataHandle; +static dma_handle_t SPI9_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi9_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI9_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI9_DMADriverState = { +#endif + &SPI9_Resource, &SPI9_DMAResource, &SPI9_DmaHandle, &SPI9_DmaRxDataHandle, &SPI9_DmaTxDataHandle, +}; + +static int32_t SPI9_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI9_PIN_INIT + RTE_SPI9_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI9_DMADriverState); +} + +static int32_t SPI9_DMAUninitialize(void) +{ +#ifdef RTE_SPI9_PIN_DEINIT + RTE_SPI9_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI9_DMADriverState); +} + +static int32_t SPI9_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI9_DMADriverState); +} + +static int32_t SPI9_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI9_DMADriverState); +} + +static int32_t SPI9_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI9_DMADriverState); +} + +static int32_t SPI9_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI9_DMADriverState); +} + +static uint32_t SPI9_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI9_DMADriverState); +} + +static int32_t SPI9_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI9_DMADriverState); +} + +static ARM_SPI_STATUS SPI9_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI9_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI9_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi9_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI9_InterruptDriverState = { +#endif + &SPI9_Resource, + &SPI9_Handle, +}; + +static int32_t SPI9_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI9_PIN_INIT + RTE_SPI9_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptUninitialize(void) +{ +#ifdef RTE_SPI9_PIN_DEINIT + RTE_SPI9_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI9_InterruptDriverState); +} + +static uint32_t SPI9_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI9_InterruptDriverState); +} + +static int32_t SPI9_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI9_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI9_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI9_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI9 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI9_DMA_EN) && RTE_SPI9_DMA_EN + SPI9_DMAInitialize, SPI9_DMAUninitialize, SPI9_DMAPowerControl, SPI9_DMASend, + SPI9_DMAReceive, SPI9_DMATransfer, SPI9_DMAGetCount, SPI9_DMAControl, + SPI9_DMAGetStatus +#else + SPI9_InterruptInitialize, + SPI9_InterruptUninitialize, + SPI9_InterruptPowerControl, + SPI9_InterruptSend, + SPI9_InterruptReceive, + SPI9_InterruptTransfer, + SPI9_InterruptGetCount, + SPI9_InterruptControl, + SPI9_InterruptGetStatus +#endif +}; + +#endif /* SPI9 */ + +#if defined(SPI10) && defined(RTE_SPI10) && RTE_SPI10 +/* User needs to provide the implementation for SPI10_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI10_GetFreq(void); +static cmsis_spi_resource_t SPI10_Resource = {SPI10, 1, SPI10_GetFreq}; + +#if RTE_SPI10_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI10_DMAResource = {RTE_SPI10_DMA_TX_DMA_BASE, RTE_SPI10_DMA_TX_CH, + RTE_SPI10_DMA_RX_DMA_BASE, RTE_SPI10_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI10_DmaHandle; +static dma_handle_t SPI10_DmaTxDataHandle; +static dma_handle_t SPI10_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi10_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI10_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI10_DMADriverState = { +#endif + &SPI10_Resource, &SPI10_DMAResource, &SPI10_DmaHandle, &SPI10_DmaRxDataHandle, &SPI10_DmaTxDataHandle, +}; + +static int32_t SPI10_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI10_PIN_INIT + RTE_SPI10_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI10_DMADriverState); +} + +static int32_t SPI10_DMAUninitialize(void) +{ +#ifdef RTE_SPI10_PIN_DEINIT + RTE_SPI10_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI10_DMADriverState); +} + +static int32_t SPI10_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI10_DMADriverState); +} + +static int32_t SPI10_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI10_DMADriverState); +} + +static int32_t SPI10_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI10_DMADriverState); +} + +static int32_t SPI10_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI10_DMADriverState); +} + +static uint32_t SPI10_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI10_DMADriverState); +} + +static int32_t SPI10_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI10_DMADriverState); +} + +static ARM_SPI_STATUS SPI10_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI10_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI10_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi10_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI10_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI10_InterruptDriverState = { +#endif + &SPI10_Resource, + &SPI10_Handle, +}; + +static int32_t SPI10_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI10_PIN_INIT + RTE_SPI10_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI10_InterruptDriverState); +} + +static int32_t SPI10_InterruptUninitialize(void) +{ +#ifdef RTE_SPI10_PIN_DEINIT + RTE_SPI10_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI10_InterruptDriverState); +} + +static int32_t SPI10_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI10_InterruptDriverState); +} + +static int32_t SPI10_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI10_InterruptDriverState); +} + +static int32_t SPI10_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI10_InterruptDriverState); +} + +static int32_t SPI10_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI10_InterruptDriverState); +} + +static uint32_t SPI10_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI10_InterruptDriverState); +} + +static int32_t SPI10_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI10_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI10_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI10_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI10 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI10_DMA_EN) && RTE_SPI10_DMA_EN + SPI10_DMAInitialize, SPI10_DMAUninitialize, SPI10_DMAPowerControl, SPI10_DMASend, + SPI10_DMAReceive, SPI10_DMATransfer, SPI10_DMAGetCount, SPI10_DMAControl, + SPI10_DMAGetStatus +#else + SPI10_InterruptInitialize, + SPI10_InterruptUninitialize, + SPI10_InterruptPowerControl, + SPI10_InterruptSend, + SPI10_InterruptReceive, + SPI10_InterruptTransfer, + SPI10_InterruptGetCount, + SPI10_InterruptControl, + SPI10_InterruptGetStatus +#endif +}; + +#endif /* SPI10 */ + +#if defined(SPI11) && defined(RTE_SPI11) && RTE_SPI11 +/* User needs to provide the implementation for SPI11_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI11_GetFreq(void); +static cmsis_spi_resource_t SPI11_Resource = {SPI11, 1, SPI11_GetFreq}; + +#if defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI11_DMAResource = {RTE_SPI11_DMA_TX_DMA_BASE, RTE_SPI11_DMA_TX_CH, + RTE_SPI11_DMA_RX_DMA_BASE, RTE_SPI11_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI11_DmaHandle; +static dma_handle_t SPI11_DmaTxDataHandle; +static dma_handle_t SPI11_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi11_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI11_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI11_DMADriverState = { +#endif + &SPI11_Resource, &SPI11_DMAResource, &SPI11_DmaHandle, &SPI11_DmaRxDataHandle, &SPI11_DmaTxDataHandle, +}; + +static int32_t SPI11_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI11_PIN_INIT + RTE_SPI11_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI11_DMADriverState); +} + +static int32_t SPI11_DMAUninitialize(void) +{ +#ifdef RTE_SPI11_PIN_DEINIT + RTE_SPI11_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI11_DMADriverState); +} + +static int32_t SPI11_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI11_DMADriverState); +} + +static int32_t SPI11_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI11_DMADriverState); +} + +static int32_t SPI11_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI11_DMADriverState); +} + +static int32_t SPI11_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI11_DMADriverState); +} + +static uint32_t SPI11_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI11_DMADriverState); +} + +static int32_t SPI11_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI11_DMADriverState); +} + +static ARM_SPI_STATUS SPI11_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI11_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI11_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi11_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI11_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI11_InterruptDriverState = { +#endif + &SPI11_Resource, + &SPI11_Handle, +}; + +static int32_t SPI11_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI11_PIN_INIT + RTE_SPI11_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI11_InterruptDriverState); +} + +static int32_t SPI11_InterruptUninitialize(void) +{ +#ifdef RTE_SPI11_PIN_DEINIT + RTE_SPI11_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI11_InterruptDriverState); +} + +static int32_t SPI11_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI11_InterruptDriverState); +} + +static int32_t SPI11_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI11_InterruptDriverState); +} + +static int32_t SPI11_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI11_InterruptDriverState); +} + +static int32_t SPI11_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI11_InterruptDriverState); +} + +static uint32_t SPI11_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI11_InterruptDriverState); +} + +static int32_t SPI11_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI11_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI11_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI11_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI11 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI11_DMA_EN) && RTE_SPI11_DMA_EN + SPI11_DMAInitialize, SPI11_DMAUninitialize, SPI11_DMAPowerControl, SPI11_DMASend, + SPI11_DMAReceive, SPI11_DMATransfer, SPI11_DMAGetCount, SPI11_DMAControl, + SPI11_DMAGetStatus +#else + SPI11_InterruptInitialize, + SPI11_InterruptUninitialize, + SPI11_InterruptPowerControl, + SPI11_InterruptSend, + SPI11_InterruptReceive, + SPI11_InterruptTransfer, + SPI11_InterruptGetCount, + SPI11_InterruptControl, + SPI11_InterruptGetStatus +#endif +}; + +#endif /* SPI11 */ + +#if defined(SPI12) && defined(RTE_SPI12) && RTE_SPI12 +/* User needs to provide the implementation for SPI12_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI12_GetFreq(void); +static cmsis_spi_resource_t SPI12_Resource = {SPI12, 1, SPI12_GetFreq}; + +#if defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI12_DMAResource = {RTE_SPI12_DMA_TX_DMA_BASE, RTE_SPI12_DMA_TX_CH, + RTE_SPI12_DMA_RX_DMA_BASE, RTE_SPI12_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI12_DmaHandle; +static dma_handle_t SPI12_DmaTxDataHandle; +static dma_handle_t SPI12_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi12_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI12_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI12_DMADriverState = { +#endif + &SPI12_Resource, &SPI12_DMAResource, &SPI12_DmaHandle, &SPI12_DmaRxDataHandle, &SPI12_DmaTxDataHandle, +}; + +static int32_t SPI12_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI12_PIN_INIT + RTE_SPI12_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI12_DMADriverState); +} + +static int32_t SPI12_DMAUninitialize(void) +{ +#ifdef RTE_SPI12_PIN_DEINIT + RTE_SPI12_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI12_DMADriverState); +} + +static int32_t SPI12_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI12_DMADriverState); +} + +static int32_t SPI12_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI12_DMADriverState); +} + +static int32_t SPI12_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI12_DMADriverState); +} + +static int32_t SPI12_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI12_DMADriverState); +} + +static uint32_t SPI12_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI12_DMADriverState); +} + +static int32_t SPI12_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI12_DMADriverState); +} + +static ARM_SPI_STATUS SPI12_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI12_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI12_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi12_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI12_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI12_InterruptDriverState = { +#endif + &SPI12_Resource, + &SPI12_Handle, +}; + +static int32_t SPI12_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI12_PIN_INIT + RTE_SPI12_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI12_InterruptDriverState); +} + +static int32_t SPI12_InterruptUninitialize(void) +{ +#ifdef RTE_SPI12_PIN_DEINIT + RTE_SPI12_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI12_InterruptDriverState); +} + +static int32_t SPI12_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI12_InterruptDriverState); +} + +static int32_t SPI12_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI12_InterruptDriverState); +} + +static int32_t SPI12_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI12_InterruptDriverState); +} + +static int32_t SPI12_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI12_InterruptDriverState); +} + +static uint32_t SPI12_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI12_InterruptDriverState); +} + +static int32_t SPI12_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI12_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI12_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI12_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI12 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI12_DMA_EN) && RTE_SPI12_DMA_EN + SPI12_DMAInitialize, SPI12_DMAUninitialize, SPI12_DMAPowerControl, SPI12_DMASend, + SPI12_DMAReceive, SPI12_DMATransfer, SPI12_DMAGetCount, SPI12_DMAControl, + SPI12_DMAGetStatus +#else + SPI12_InterruptInitialize, + SPI12_InterruptUninitialize, + SPI12_InterruptPowerControl, + SPI12_InterruptSend, + SPI12_InterruptReceive, + SPI12_InterruptTransfer, + SPI12_InterruptGetCount, + SPI12_InterruptControl, + SPI12_InterruptGetStatus +#endif +}; + +#endif /* SPI12 */ + +#if defined(SPI13) && defined(RTE_SPI13) && RTE_SPI13 +/* User needs to provide the implementation for SPI13_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t SPI13_GetFreq(void); +static cmsis_spi_resource_t SPI13_Resource = {SPI13, 1, SPI13_GetFreq}; + +#if defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_spi_dma_resource_t SPI13_DMAResource = {RTE_SPI13_DMA_TX_DMA_BASE, RTE_SPI13_DMA_TX_CH, + RTE_SPI13_DMA_RX_DMA_BASE, RTE_SPI13_DMA_RX_CH}; + +static cmsis_spi_dma_handle_t SPI13_DmaHandle; +static dma_handle_t SPI13_DmaTxDataHandle; +static dma_handle_t SPI13_DmaRxDataHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi13_dma_driver_state") +static cmsis_spi_dma_driver_state_t SPI13_DMADriverState = { +#else +static cmsis_spi_dma_driver_state_t SPI13_DMADriverState = { +#endif + &SPI13_Resource, &SPI13_DMAResource, &SPI13_DmaHandle, &SPI13_DmaRxDataHandle, &SPI13_DmaTxDataHandle, +}; + +static int32_t SPI13_DMAInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI13_PIN_INIT + RTE_SPI13_PIN_INIT(); +#endif + return SPI_DMAInitialize(cb_event, &SPI13_DMADriverState); +} + +static int32_t SPI13_DMAUninitialize(void) +{ +#ifdef RTE_SPI13_PIN_DEINIT + RTE_SPI13_PIN_DEINIT(); +#endif + return SPI_DMAUninitialize(&SPI13_DMADriverState); +} + +static int32_t SPI13_DMAPowerControl(ARM_POWER_STATE state) +{ + return SPI_DMAPowerControl(state, &SPI13_DMADriverState); +} + +static int32_t SPI13_DMASend(const void *data, uint32_t num) +{ + return SPI_DMASend(data, num, &SPI13_DMADriverState); +} + +static int32_t SPI13_DMAReceive(void *data, uint32_t num) +{ + return SPI_DMAReceive(data, num, &SPI13_DMADriverState); +} + +static int32_t SPI13_DMATransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_DMATransfer(data_out, data_in, num, &SPI13_DMADriverState); +} + +static uint32_t SPI13_DMAGetCount(void) +{ + return SPI_DMAGetCount(&SPI13_DMADriverState); +} + +static int32_t SPI13_DMAControl(uint32_t control, uint32_t arg) +{ + return SPI_DMAControl(control, arg, &SPI13_DMADriverState); +} + +static ARM_SPI_STATUS SPI13_DMAGetStatus(void) +{ + return SPI_DMAGetStatus(&SPI13_DMADriverState); +} + +#endif + +#else + +static cmsis_spi_handle_t SPI13_Handle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("spi13_interrupt_driver_state") +static cmsis_spi_interrupt_driver_state_t SPI13_InterruptDriverState = { +#else +static cmsis_spi_interrupt_driver_state_t SPI13_InterruptDriverState = { +#endif + &SPI13_Resource, + &SPI13_Handle, +}; + +static int32_t SPI13_InterruptInitialize(ARM_SPI_SignalEvent_t cb_event) +{ +#ifdef RTE_SPI13_PIN_INIT + RTE_SPI13_PIN_INIT(); +#endif + return SPI_InterruptInitialize(cb_event, &SPI13_InterruptDriverState); +} + +static int32_t SPI13_InterruptUninitialize(void) +{ +#ifdef RTE_SPI13_PIN_DEINIT + RTE_SPI13_PIN_DEINIT(); +#endif + return SPI_InterruptUninitialize(&SPI13_InterruptDriverState); +} + +static int32_t SPI13_InterruptPowerControl(ARM_POWER_STATE state) +{ + return SPI_InterruptPowerControl(state, &SPI13_InterruptDriverState); +} + +static int32_t SPI13_InterruptSend(const void *data, uint32_t num) +{ + return SPI_InterruptSend(data, num, &SPI13_InterruptDriverState); +} + +static int32_t SPI13_InterruptReceive(void *data, uint32_t num) +{ + return SPI_InterruptReceive(data, num, &SPI13_InterruptDriverState); +} + +static int32_t SPI13_InterruptTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return SPI_InterruptTransfer(data_out, data_in, num, &SPI13_InterruptDriverState); +} + +static uint32_t SPI13_InterruptGetCount(void) +{ + return SPI_InterruptGetCount(&SPI13_InterruptDriverState); +} + +static int32_t SPI13_InterruptControl(uint32_t control, uint32_t arg) +{ + return SPI_InterruptControl(control, arg, &SPI13_InterruptDriverState); +} + +static ARM_SPI_STATUS SPI13_InterruptGetStatus(void) +{ + return SPI_InterruptGetStatus(&SPI13_InterruptDriverState); +} + +#endif + +ARM_DRIVER_SPI Driver_SPI13 = {SPIx_GetVersion, SPIx_GetCapabilities, +#if defined(RTE_SPI13_DMA_EN) && RTE_SPI13_DMA_EN + SPI13_DMAInitialize, SPI13_DMAUninitialize, SPI13_DMAPowerControl, SPI13_DMASend, + SPI13_DMAReceive, SPI13_DMATransfer, SPI13_DMAGetCount, SPI13_DMAControl, + SPI13_DMAGetStatus +#else + SPI13_InterruptInitialize, + SPI13_InterruptUninitialize, + SPI13_InterruptPowerControl, + SPI13_InterruptSend, + SPI13_InterruptReceive, + SPI13_InterruptTransfer, + SPI13_InterruptGetCount, + SPI13_InterruptControl, + SPI13_InterruptGetStatus +#endif +}; + +#endif /* SPI13 */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.h new file mode 100644 index 0000000000..b1a3defb7b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_spi_cmsis.h @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2020 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _FSL_SPI_CMSIS_H_ +#define _FSL_SPI_CMSIS_H_ + +#include "fsl_spi.h" +#include "RTE_Device.h" +#include "Driver_SPI.h" +#if defined(FSL_FEATURE_SOC_DMA_COUNT) && (FSL_FEATURE_SOC_DMA_COUNT) +#include "fsl_spi_dma.h" +#endif + +#if defined(SPI0) && defined(RTE_SPI0) && RTE_SPI0 +extern ARM_DRIVER_SPI Driver_SPI0; +#endif /* SPI0 */ + +#if defined(SPI1) && defined(RTE_SPI1) && RTE_SPI1 +extern ARM_DRIVER_SPI Driver_SPI1; +#endif /* SPI1 */ + +#if defined(SPI2) && defined(RTE_SPI2) && RTE_SPI2 +extern ARM_DRIVER_SPI Driver_SPI2; +#endif /* SPI2 */ + +#if defined(SPI3) && defined(RTE_SPI3) && RTE_SPI3 +extern ARM_DRIVER_SPI Driver_SPI3; +#endif /* SPI3 */ + +#if defined(SPI4) && defined(RTE_SPI4) && RTE_SPI4 +extern ARM_DRIVER_SPI Driver_SPI4; +#endif /* SPI4 */ + +#if defined(SPI5) && defined(RTE_SPI5) && RTE_SPI5 +extern ARM_DRIVER_SPI Driver_SPI5; +#endif /* SPI5 */ + +#if defined(SPI6) && defined(RTE_SPI6) && RTE_SPI6 +extern ARM_DRIVER_SPI Driver_SPI6; +#endif /* SPI6 */ + +#if defined(SPI7) && defined(RTE_SPI7) && RTE_SPI7 +extern ARM_DRIVER_SPI Driver_SPI7; +#endif /* SPI7 */ + +#if defined(SPI8) && defined(RTE_SPI8) && RTE_SPI8 +extern ARM_DRIVER_SPI Driver_SPI8; +#endif /* SPI8 */ + +#if defined(SPI9) && defined(RTE_SPI9) && RTE_SPI9 +extern ARM_DRIVER_SPI Driver_SPI9; +#endif /* SPI9 */ + +#if defined(SPI10) && defined(RTE_SPI10) && RTE_SPI10 +extern ARM_DRIVER_SPI Driver_SPI10; +#endif /* SPI10 */ + +#if defined(SPI11) && defined(RTE_SPI11) && RTE_SPI11 +extern ARM_DRIVER_SPI Driver_SPI11; +#endif /* SPI11 */ + +#if defined(SPI12) && defined(RTE_SPI12) && RTE_SPI12 +extern ARM_DRIVER_SPI Driver_SPI12; +#endif /* SPI12 */ + +#if defined(SPI13) && defined(RTE_SPI13) && RTE_SPI13 +extern ARM_DRIVER_SPI Driver_SPI13; +#endif /* SPI13 */ + +#define SPI_FLAG_UNINIT (0UL) +#define SPI_FLAG_INIT (1UL << 0) +#define SPI_FLAG_POWER (1UL << 1) +#define SPI_FLAG_CONFIGURED (1UL << 2) +#define SPI_FLAG_MASTER (1UL << 3) + +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_usart_cmsis.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_usart_cmsis.c new file mode 100644 index 0000000000..5573b259de --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_usart_cmsis.c @@ -0,0 +1,3743 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017, 2020 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "fsl_usart_cmsis.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_cmsis" +#endif + +#if ((defined(RTE_USART0) && RTE_USART0) || (defined(RTE_USART1) && RTE_USART1) || \ + (defined(RTE_USART2) && RTE_USART2) || (defined(RTE_USART3) && RTE_USART3) || \ + (defined(RTE_USART4) && RTE_USART4) || (defined(RTE_USART5) && RTE_USART5) || \ + (defined(RTE_USART6) && RTE_USART6) || (defined(RTE_USART7) && RTE_USART7) || \ + (defined(RTE_USART8) && RTE_USART8) || (defined(RTE_USART9) && RTE_USART9) || \ + (defined(RTE_USART10) && RTE_USART10) || (defined(RTE_USART11) && RTE_USART11) || \ + (defined(RTE_USART12) && RTE_USART12) || (defined(RTE_USART13) && RTE_USART13)) + +#define ARM_USART_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR((2), (3)) + +/* + * ARMCC does not support split the data section automatically, so the driver + * needs to split the data to separate sections explicitly, to reduce codesize. + */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#define ARMCC_SECTION(section_name) __attribute__((section(section_name))) +#endif + +typedef const struct _cmsis_usart_resource +{ + USART_Type *base; /*!< usart peripheral base address. */ + uint32_t (*GetFreq)(void); /*!< Function to get the clock frequency. */ +} cmsis_usart_resource_t; + +typedef struct _cmsis_usart_non_blocking_driver_state +{ + cmsis_usart_resource_t *resource; /*!< Basic usart resource. */ + usart_handle_t *handle; /*!< Interupt transfer handle. */ + ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_usart_non_blocking_driver_state_t; + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +typedef const struct _cmsis_usart_dma_resource +{ + DMA_Type *txDmaBase; /*!< DMA peripheral base address for TX. */ + uint32_t txDmaChannel; /*!< DMA channel for usart TX. */ + + DMA_Type *rxDmaBase; /*!< DMA peripheral base address for RX. */ + uint32_t rxDmaChannel; /*!< DMA channel for usart RX. */ +} cmsis_usart_dma_resource_t; + +typedef struct _cmsis_usart_dma_driver_state +{ + cmsis_usart_resource_t *resource; /*!< usart basic resource. */ + cmsis_usart_dma_resource_t *dmaResource; /*!< usart DMA resource. */ + usart_dma_handle_t *handle; /*!< usart DMA transfer handle. */ + dma_handle_t *rxHandle; /*!< DMA RX handle. */ + dma_handle_t *txHandle; /*!< DMA TX handle. */ + ARM_USART_SignalEvent_t cb_event; /*!< Callback function. */ + uint8_t flags; /*!< Control and state flags. */ +} cmsis_usart_dma_driver_state_t; +#endif + +enum _usart_transfer_states +{ + kUSART_TxIdle, /*!< TX idle. */ + kUSART_TxBusy, /*!< TX busy. */ + kUSART_RxIdle, /*!< RX idle. */ + kUSART_RxBusy /*!< RX busy. */ +}; + +/* Driver Version */ +static const ARM_DRIVER_VERSION s_usartDriverVersion = {ARM_USART_API_VERSION, ARM_USART_DRV_VERSION}; + +static const ARM_USART_CAPABILITIES s_usartDriverCapabilities = { + 1, /* supports usart (Asynchronous) mode */ + 0, /* supports Synchronous Master mode */ + 0, /* supports Synchronous Slave mode */ + 0, /* supports usart Single-wire mode */ + 0, /* supports usart IrDA mode */ + 0, /* supports usart Smart Card mode */ + 0, /* Smart Card Clock generator */ + 0, /* RTS Flow Control available */ + 0, /* CTS Flow Control available */ + 0, /* Transmit completed event: \ref ARM_USART_EVENT_TX_COMPLETE */ + 0, /* Signal receive character timeout event: \ref ARM_USART_EVENT_RX_TIMEOUT */ + 0, /* RTS Line: 0=not available, 1=available */ + 0, /* CTS Line: 0=not available, 1=available */ + 0, /* DTR Line: 0=not available, 1=available */ + 0, /* DSR Line: 0=not available, 1=available */ + 0, /* DCD Line: 0=not available, 1=available */ + 0, /* RI Line: 0=not available, 1=available */ + 0, /* Signal CTS change event: \ref ARM_USART_EVENT_CTS */ + 0, /* Signal DSR change event: \ref ARM_USART_EVENT_DSR */ + 0, /* Signal DCD change event: \ref ARM_USART_EVENT_DCD */ + 0, /* Signal RI change event: \ref ARM_USART_EVENT_RI */ +}; + +/* + * Common control function used by usart_NonBlockingControl/usart_DmaControl/usart_EdmaControl + */ +static int32_t USART_CommonControl(uint32_t control, + uint32_t arg, + cmsis_usart_resource_t *resource, + uint8_t *isConfigured) +{ + usart_config_t config; + + USART_GetDefaultConfig(&config); + int32_t result = ARM_DRIVER_OK; + bool isContinue = false; + + switch (control & ARM_USART_CONTROL_Msk) + { + case ARM_USART_MODE_ASYNCHRONOUS: + /* USART Baudrate */ + config.baudRate_Bps = arg; + isContinue = true; + break; + + /* TX/RX IO is controlled in application layer. */ + case ARM_USART_CONTROL_TX: + if (arg != 0U) + { + config.enableTx = true; + } + else + { + config.enableTx = false; + } + result = ARM_DRIVER_OK; + break; + + case ARM_USART_CONTROL_RX: + if (arg != 0U) + { + config.enableRx = true; + } + else + { + config.enableRx = false; + } + + result = ARM_DRIVER_OK; + break; + + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + if (!isContinue) + { + return result; + } + + switch (control & ARM_USART_PARITY_Msk) + { + case ARM_USART_PARITY_NONE: + config.parityMode = kUSART_ParityDisabled; + break; + case ARM_USART_PARITY_EVEN: + config.parityMode = kUSART_ParityEven; + break; + case ARM_USART_PARITY_ODD: + config.parityMode = kUSART_ParityOdd; + break; + default: + result = ARM_USART_ERROR_PARITY; + break; + } + + if (result == ARM_USART_ERROR_PARITY) + { + return result; + } + + switch (control & ARM_USART_STOP_BITS_Msk) + { + case ARM_USART_STOP_BITS_1: + /* The GetDefaultConfig has already set for this case. */ + break; + case ARM_USART_STOP_BITS_2: + config.stopBitCount = kUSART_TwoStopBit; + break; + default: + result = ARM_USART_ERROR_STOP_BITS; + break; + } + if (result == ARM_USART_ERROR_STOP_BITS) + { + return result; + } + + /* If usart is already configured, deinit it first. */ + if (((*isConfigured) & (uint8_t)USART_FLAG_CONFIGURED) != 0U) + { + USART_Deinit(resource->base); + *isConfigured &= ~(uint8_t)USART_FLAG_CONFIGURED; + } + + config.enableTx = true; + config.enableRx = true; + + if (kStatus_USART_BaudrateNotSupport == USART_Init(resource->base, &config, resource->GetFreq())) + { + result = ARM_USART_ERROR_BAUDRATE; + } + else + { + *isConfigured |= (uint8_t)USART_FLAG_CONFIGURED; + } + + return result; +} + +static ARM_DRIVER_VERSION USARTx_GetVersion(void) +{ + return s_usartDriverVersion; +} + +static ARM_USART_CAPABILITIES USARTx_GetCapabilities(void) +{ + return s_usartDriverCapabilities; +} + +static int32_t USARTx_SetModemControl(ARM_USART_MODEM_CONTROL control) +{ + return ARM_DRIVER_ERROR_UNSUPPORTED; +} + +static ARM_USART_MODEM_STATUS USARTx_GetModemStatus(void) +{ + ARM_USART_MODEM_STATUS modem_status = {0}; + + modem_status.cts = 0U; + modem_status.dsr = 0U; + modem_status.ri = 0U; + modem_status.dcd = 0U; + modem_status.reserved = 0U; + + return modem_status; +} + +#endif + +#if ((defined(RTE_USART0_DMA_EN) && RTE_USART0_DMA_EN) || (defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN) || \ + (defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN) || (defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN) || \ + (defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN) || (defined(RTE_USART5_DMA_EN) && RTE_USART5_DMA_EN) || \ + (defined(RTE_USART6_DMA_EN) && RTE_USART6_DMA_EN) || (defined(RTE_USART7_DMA_EN) && RTE_USART7_DMA_EN) || \ + (defined(RTE_USART8_DMA_EN) && RTE_USART8_DMA_EN) || (defined(RTE_USART9_DMA_EN) && RTE_USART9_DMA_EN) || \ + (defined(RTE_USART10_DMA_EN) && RTE_USART10_DMA_EN) || (defined(RTE_USART11_DMA_EN) && RTE_USART11_DMA_EN) || \ + (defined(RTE_USART12_DMA_EN) && RTE_USART12_DMA_EN) || (defined(RTE_USART13_DMA_EN) && RTE_USART13_DMA_EN)) + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +static void KSDK_USART_DmaCallback(USART_Type *base, usart_dma_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + if (kStatus_USART_TxIdle == status) + { + event = ARM_USART_EVENT_SEND_COMPLETE; + } + + if (kStatus_USART_RxIdle == status) + { + event = ARM_USART_EVENT_RECEIVE_COMPLETE; + } + else + { + /* Avoid MISRA 2012 15.7 violation */ + } + + /* User data is actually CMSIS driver callback. */ + if (userData != NULL) + { + ((ARM_USART_SignalEvent_t)userData)(event); + } +} + +static int32_t USART_DmaInitialize(ARM_USART_SignalEvent_t cb_event, cmsis_usart_dma_driver_state_t *usart) +{ + if (0U == (usart->flags & USART_FLAG_INIT)) + { + usart->cb_event = cb_event; + usart->flags = (uint8_t)USART_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t USART_DmaUninitialize(cmsis_usart_dma_driver_state_t *usart) +{ + usart->flags = (uint8_t)USART_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t USART_DmaPowerControl(ARM_POWER_STATE state, cmsis_usart_dma_driver_state_t *usart) +{ + usart_config_t config; + int32_t result = ARM_DRIVER_OK; + + switch (state) + { + case ARM_POWER_OFF: + if ((usart->flags & (uint8_t)USART_FLAG_POWER) != 0U) + { + USART_Deinit(usart->resource->base); + DMA_DisableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); + DMA_DisableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); + usart->flags = (uint8_t)USART_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + case ARM_POWER_FULL: + /* Must be initialized first. */ + if (usart->flags == (uint8_t)USART_FLAG_UNINIT) + { + result = ARM_DRIVER_ERROR; + break; + } + + if ((usart->flags & (uint8_t)USART_FLAG_POWER) != 0U) + { + /* Driver already powered */ + break; + } + + USART_GetDefaultConfig(&config); + config.enableTx = true; + config.enableRx = true; + + /* Set up DMA setting. */ + DMA_EnableChannel(usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); + DMA_EnableChannel(usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); + + DMA_CreateHandle(usart->rxHandle, usart->dmaResource->rxDmaBase, usart->dmaResource->rxDmaChannel); + DMA_CreateHandle(usart->txHandle, usart->dmaResource->txDmaBase, usart->dmaResource->txDmaChannel); + + /* Setup the usart. */ + (void)USART_Init(usart->resource->base, &config, usart->resource->GetFreq()); + (void)USART_TransferCreateHandleDMA(usart->resource->base, usart->handle, KSDK_USART_DmaCallback, + (void *)usart->cb_event, usart->txHandle, usart->rxHandle); + + usart->flags |= ((uint8_t)USART_FLAG_POWER | (uint8_t)USART_FLAG_CONFIGURED); + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + + return result; +} + +static int32_t USART_DmaSend(const void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.txData = (const uint8_t *)data; + xfer.dataSize = num; + + status = USART_TransferSendDMA(usart->resource->base, usart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_TxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_DmaReceive(void *data, uint32_t num, cmsis_usart_dma_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.rxData = (uint8_t *)data; + xfer.dataSize = num; + + status = USART_TransferReceiveDMA(usart->resource->base, usart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_RxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_DmaTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_usart_dma_driver_state_t *usart) +{ + /* Only in synchronous mode */ + return ARM_DRIVER_ERROR; +} + +static uint32_t USART_DmaGetTxCount(cmsis_usart_dma_driver_state_t *usart) +{ + uint32_t cnt; + + /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */ + if (kStatus_NoTransferInProgress == USART_TransferGetSendCountDMA(usart->resource->base, usart->handle, &cnt)) + { + cnt = usart->handle->txDataSizeAll; + } + + return cnt; +} + +static uint32_t USART_DmaGetRxCount(cmsis_usart_dma_driver_state_t *usart) +{ + uint32_t cnt; + + if (kStatus_NoTransferInProgress == USART_TransferGetReceiveCountDMA(usart->resource->base, usart->handle, &cnt)) + { + cnt = usart->handle->rxDataSizeAll; + } + + return cnt; +} + +static int32_t USART_DmaControl(uint32_t control, uint32_t arg, cmsis_usart_dma_driver_state_t *usart) +{ + int32_t result = ARM_DRIVER_OK; + bool isContinue = false; + /* Must be power on. */ + if (0U == (usart->flags & (uint8_t)USART_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + /* Does not support these features. */ + if ((control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) != 0U) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_CONTROL_Msk) + { + /* Abort Send */ + case ARM_USART_ABORT_SEND: + USART_EnableTxDMA(usart->resource->base, false); + DMA_AbortTransfer(usart->handle->txDmaHandle); + usart->handle->txState = (uint8_t)kUSART_TxIdle; + result = ARM_DRIVER_OK; + break; + + /* Abort receive */ + case ARM_USART_ABORT_RECEIVE: + USART_EnableRxDMA(usart->resource->base, false); + DMA_AbortTransfer(usart->handle->rxDmaHandle); + usart->handle->rxState = (uint8_t)kUSART_RxIdle; + result = ARM_DRIVER_OK; + break; + + default: + isContinue = true; + break; + } + if (isContinue) + { + result = USART_CommonControl(control, arg, usart->resource, &usart->flags); + } + return result; +} + +static ARM_USART_STATUS USART_DmaGetStatus(cmsis_usart_dma_driver_state_t *usart) +{ + ARM_USART_STATUS stat = {0}; + uint32_t ksdk_usart_status = usart->resource->base->STAT; + + stat.tx_busy = (((uint8_t)kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U)); + stat.rx_busy = (((uint8_t)kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U)); + + stat.tx_underflow = 0U; + stat.rx_overflow = 0U; + + stat.rx_break = (uint32_t)(((ksdk_usart_status & USART_STAT_RXBRK_MASK)) != 0U); + + stat.rx_framing_error = (uint32_t)(((ksdk_usart_status & USART_STAT_FRAMERRINT_MASK)) != 0U); + stat.rx_parity_error = (uint32_t)(((ksdk_usart_status & USART_STAT_PARITYERRINT_MASK)) != 0U); + stat.reserved = 0U; + + return stat; +} +#endif + +#endif + +#if ((defined(RTE_USART0) && RTE_USART0 && !(defined(RTE_USART0_DMA_EN) && RTE_USART0_DMA_EN)) || \ + (defined(RTE_USART1) && RTE_USART1 && !(defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN)) || \ + (defined(RTE_USART2) && RTE_USART2 && !(defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN)) || \ + (defined(RTE_USART3) && RTE_USART3 && !(defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN)) || \ + (defined(RTE_USART4) && RTE_USART4 && !(defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN)) || \ + (defined(RTE_USART5) && RTE_USART5 && !(defined(RTE_USART5_DMA_EN) && RTE_USART5_DMA_EN)) || \ + (defined(RTE_USART6) && RTE_USART6 && !(defined(RTE_USART6_DMA_EN) && RTE_USART6_DMA_EN)) || \ + (defined(RTE_USART7) && RTE_USART7 && !(defined(RTE_USART7_DMA_EN) && RTE_USART7_DMA_EN)) || \ + (defined(RTE_USART8) && RTE_USART8 && !(defined(RTE_USART8_DMA_EN) && RTE_USART8_DMA_EN)) || \ + (defined(RTE_USART9) && RTE_USART9 && !(defined(RTE_USART9_DMA_EN) && RTE_USART9_DMA_EN)) || \ + (defined(RTE_USART10) && RTE_USART10 && !(defined(RTE_USART10_DMA_EN) && RTE_USART10_DMA_EN)) || \ + (defined(RTE_USART11) && RTE_USART11 && !(defined(RTE_USART11_DMA_EN) && RTE_USART11_DMA_EN)) || \ + (defined(RTE_USART12) && RTE_USART12 && !(defined(RTE_USART12_DMA_EN) && RTE_USART12_DMA_EN)) || \ + (defined(RTE_USART13) && RTE_USART13 && !(defined(RTE_USART13_DMA_EN) && RTE_USART13_DMA_EN))) + +static void KSDK_USART_NonBlockingCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *userData) +{ + uint32_t event = 0U; + + switch (status) + { + case kStatus_USART_TxIdle: + event = ARM_USART_EVENT_SEND_COMPLETE; + break; + case kStatus_USART_RxIdle: + event = ARM_USART_EVENT_RECEIVE_COMPLETE; + break; + case kStatus_USART_RxError: + event = ARM_USART_EVENT_RX_OVERFLOW; + break; + case kStatus_USART_TxError: + event = ARM_USART_EVENT_TX_UNDERFLOW; + break; + case kStatus_USART_FramingError: + event = ARM_USART_EVENT_RX_FRAMING_ERROR; + break; + case kStatus_USART_ParityError: + event = ARM_USART_EVENT_RX_PARITY_ERROR; + break; + default: + /* Avoid MISRA 16.4. */ + break; + } + + /* User data is actually CMSIS driver callback. */ + if (userData != NULL) + { + ((ARM_USART_SignalEvent_t)userData)(event); + } +} + +static int32_t USART_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event, + cmsis_usart_non_blocking_driver_state_t *usart) +{ + if (0U == (usart->flags & (uint8_t)USART_FLAG_INIT)) + { + usart->cb_event = cb_event; + usart->flags = (uint8_t)USART_FLAG_INIT; + } + + return ARM_DRIVER_OK; +} + +static int32_t USART_NonBlockingUninitialize(cmsis_usart_non_blocking_driver_state_t *usart) +{ + usart->flags = (uint8_t)USART_FLAG_UNINIT; + return ARM_DRIVER_OK; +} + +static int32_t USART_NonBlockingPowerControl(ARM_POWER_STATE state, cmsis_usart_non_blocking_driver_state_t *usart) +{ + usart_config_t config; + int32_t result = ARM_DRIVER_OK; + + switch (state) + { + case ARM_POWER_OFF: + if ((usart->flags & (uint8_t)USART_FLAG_POWER) != 0U) + { + USART_Deinit(usart->resource->base); + usart->flags = (uint8_t)USART_FLAG_INIT; + } + break; + case ARM_POWER_LOW: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + case ARM_POWER_FULL: + /* Must be initialized first. */ + if (usart->flags == (uint8_t)USART_FLAG_UNINIT) + { + result = ARM_DRIVER_ERROR; + break; + } + + if ((usart->flags & (uint8_t)USART_FLAG_POWER) != 0U) + { + /* Driver already powered */ + break; + } + + USART_GetDefaultConfig(&config); + config.enableTx = true; + config.enableRx = true; + + (void)USART_Init(usart->resource->base, &config, usart->resource->GetFreq()); + (void)USART_TransferCreateHandle(usart->resource->base, usart->handle, KSDK_USART_NonBlockingCallback, + (void *)usart->cb_event); + usart->flags |= ((uint8_t)USART_FLAG_POWER | (uint8_t)USART_FLAG_CONFIGURED); + + break; + default: + result = ARM_DRIVER_ERROR_UNSUPPORTED; + break; + } + + return result; +} + +static int32_t USART_NonBlockingSend(const void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.txData = (const uint8_t *)data; + xfer.dataSize = num; + + status = USART_TransferSendNonBlocking(usart->resource->base, usart->handle, &xfer); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_TxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_NonBlockingReceive(void *data, uint32_t num, cmsis_usart_non_blocking_driver_state_t *usart) +{ + int32_t ret; + status_t status; + usart_transfer_t xfer; + + xfer.rxData = (uint8_t *)data; + xfer.dataSize = num; + + status = USART_TransferReceiveNonBlocking(usart->resource->base, usart->handle, &xfer, NULL); + + switch (status) + { + case kStatus_Success: + ret = ARM_DRIVER_OK; + break; + case kStatus_InvalidArgument: + ret = ARM_DRIVER_ERROR_PARAMETER; + break; + case kStatus_USART_RxBusy: + ret = ARM_DRIVER_ERROR_BUSY; + break; + default: + ret = ARM_DRIVER_ERROR; + break; + } + + return ret; +} + +static int32_t USART_NonBlockingTransfer(const void *data_out, + void *data_in, + uint32_t num, + cmsis_usart_non_blocking_driver_state_t *usart) +{ + /* Only in synchronous mode */ + return ARM_DRIVER_ERROR; +} + +static uint32_t USART_NonBlockingGetTxCount(cmsis_usart_non_blocking_driver_state_t *usart) +{ + uint32_t cnt; + + /* If TX not in progress, then the TX count is txDataSizeAll saved in handle. */ + if ((uint8_t)kUSART_TxIdle == usart->handle->txState) + { + cnt = usart->handle->txDataSizeAll; + } + else + { + cnt = usart->handle->txDataSizeAll - usart->handle->txDataSize; + } + + return cnt; +} + +static uint32_t USART_NonBlockingGetRxCount(cmsis_usart_non_blocking_driver_state_t *usart) +{ + uint32_t cnt; + + if ((uint8_t)kUSART_RxIdle == usart->handle->rxState) + { + cnt = usart->handle->rxDataSizeAll; + } + else + { + cnt = usart->handle->rxDataSizeAll - usart->handle->rxDataSize; + } + + return cnt; +} + +static int32_t USART_NonBlockingControl(uint32_t control, uint32_t arg, cmsis_usart_non_blocking_driver_state_t *usart) +{ + int32_t result = ARM_DRIVER_OK; + bool isContinue = false; + /* Must be power on. */ + if (0U == (usart->flags & (uint8_t)USART_FLAG_POWER)) + { + return ARM_DRIVER_ERROR; + } + + /* Does not support these features. */ + if ((control & (ARM_USART_FLOW_CONTROL_Msk | ARM_USART_CPOL_Msk | ARM_USART_CPHA_Msk)) != 0U) + { + return ARM_DRIVER_ERROR_UNSUPPORTED; + } + + switch (control & ARM_USART_CONTROL_Msk) + { + /* Abort Send */ + case ARM_USART_ABORT_SEND: + usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_TXLVL_MASK; + usart->handle->txDataSize = 0; + usart->handle->txState = (uint8_t)kUSART_TxIdle; + result = ARM_DRIVER_OK; + break; + + /* Abort receive */ + case ARM_USART_ABORT_RECEIVE: + usart->resource->base->FIFOINTENSET &= ~USART_FIFOINTENSET_RXLVL_MASK; + usart->handle->rxDataSize = 0U; + usart->handle->rxState = (uint8_t)kUSART_RxIdle; + result = ARM_DRIVER_OK; + break; + + default: + isContinue = true; + break; + } + + if (isContinue) + { + result = USART_CommonControl(control, arg, usart->resource, &usart->flags); + } + return result; +} + +static ARM_USART_STATUS USART_NonBlockingGetStatus(cmsis_usart_non_blocking_driver_state_t *usart) +{ + ARM_USART_STATUS stat = {0}; + uint32_t ksdk_usart_status = usart->resource->base->STAT; + + stat.tx_busy = (((uint8_t)kUSART_TxBusy == usart->handle->txState) ? (1U) : (0U)); + stat.rx_busy = (((uint8_t)kUSART_RxBusy == usart->handle->rxState) ? (1U) : (0U)); + + stat.tx_underflow = 0U; + stat.rx_overflow = 0U; + + stat.rx_break = (uint32_t)(((ksdk_usart_status & (uint32_t)USART_STAT_RXBRK_MASK)) != 0U); + + stat.rx_framing_error = (uint32_t)(((ksdk_usart_status & USART_STAT_FRAMERRINT_MASK)) != 0U); + stat.rx_parity_error = (uint32_t)(((ksdk_usart_status & USART_STAT_PARITYERRINT_MASK)) != 0U); + stat.reserved = 0U; + + return stat; +} + +#endif + +#if defined(USART0) && defined(RTE_USART0) && RTE_USART0 + +/* User needs to provide the implementation for USART0_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART0_GetFreq(void); + +static cmsis_usart_resource_t usart0_Resource = {USART0, USART0_GetFreq}; + +/* usart0 Driver Control Block */ + +#if defined(RTE_USART0_DMA_EN) && RTE_USART0_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +static cmsis_usart_dma_resource_t usart0_DmaResource = { + RTE_USART0_DMA_TX_DMA_BASE, + RTE_USART0_DMA_TX_CH, + RTE_USART0_DMA_RX_DMA_BASE, + RTE_USART0_DMA_RX_CH, +}; + +static usart_dma_handle_t USART0_DmaHandle; +static dma_handle_t USART0_DmaRxHandle; +static dma_handle_t USART0_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart0_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart0_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart0_DmaDriverState = { +#endif + &usart0_Resource, &usart0_DmaResource, &USART0_DmaHandle, &USART0_DmaRxHandle, &USART0_DmaTxHandle, +}; + +static int32_t USART0_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART0_PIN_INIT + RTE_USART0_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaUninitialize(void) +{ +#ifdef RTE_USART0_PIN_DEINIT + RTE_USART0_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart0_DmaDriverState); +} + +static int32_t USART0_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart0_DmaDriverState); +} + +static int32_t USART0_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart0_DmaDriverState); +} + +static uint32_t USART0_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart0_DmaDriverState); +} + +static uint32_t USART0_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart0_DmaDriverState); +} + +static int32_t USART0_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart0_DmaDriverState); +} + +static ARM_USART_STATUS USART0_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart0_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART0_Handle; +#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) +static uint8_t usart0_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart0_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart0_NonBlockingDriverState = { +#endif + &usart0_Resource, + &USART0_Handle, +}; + +static int32_t USART0_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART0_PIN_INIT + RTE_USART0_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART0_PIN_DEINIT + RTE_USART0_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + int32_t result; + + result = USART_NonBlockingPowerControl(state, &usart0_NonBlockingDriverState); +#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart0_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart0_NonBlockingDriverState.resource->base, + usart0_NonBlockingDriverState.handle, usart0_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART0_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart0_NonBlockingDriverState); +} + +static uint32_t USART0_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart0_NonBlockingDriverState); +} + +static uint32_t USART0_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart0_NonBlockingDriverState); +} + +static int32_t USART0_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart0_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART0_RX_BUFFER_ENABLE) && (USART0_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart0_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART0_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart0_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART0 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART0_DMA_EN + USART0_DmaInitialize, USART0_DmaUninitialize, USART0_DmaPowerControl, USART0_DmaSend, USART0_DmaReceive, + USART0_DmaTransfer, USART0_DmaGetTxCount, USART0_DmaGetRxCount, USART0_DmaControl, USART0_DmaGetStatus, +#else + USART0_NonBlockingInitialize, + USART0_NonBlockingUninitialize, + USART0_NonBlockingPowerControl, + USART0_NonBlockingSend, + USART0_NonBlockingReceive, + USART0_NonBlockingTransfer, + USART0_NonBlockingGetTxCount, + USART0_NonBlockingGetRxCount, + USART0_NonBlockingControl, + USART0_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart0 */ + +#if defined(USART1) && defined(RTE_USART1) && RTE_USART1 + +/* User needs to provide the implementation for USART1_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART1_GetFreq(void); + +static cmsis_usart_resource_t usart1_Resource = {USART1, USART1_GetFreq}; + +#if defined(RTE_USART1_DMA_EN) && RTE_USART1_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart1_DmaResource = { + RTE_USART1_DMA_TX_DMA_BASE, + RTE_USART1_DMA_TX_CH, + RTE_USART1_DMA_RX_DMA_BASE, + RTE_USART1_DMA_RX_CH, +}; + +static usart_dma_handle_t USART1_DmaHandle; +static dma_handle_t USART1_DmaRxHandle; +static dma_handle_t USART1_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart1_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart1_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart1_DmaDriverState = { +#endif + &usart1_Resource, &usart1_DmaResource, &USART1_DmaHandle, &USART1_DmaRxHandle, &USART1_DmaTxHandle, +}; + +static int32_t USART1_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART1_PIN_INIT + RTE_USART1_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaUninitialize(void) +{ +#ifdef RTE_USART1_PIN_DEINIT + RTE_USART1_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart1_DmaDriverState); +} + +static int32_t USART1_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart1_DmaDriverState); +} + +static int32_t USART1_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart1_DmaDriverState); +} + +static uint32_t USART1_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart1_DmaDriverState); +} + +static uint32_t USART1_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart1_DmaDriverState); +} + +static int32_t USART1_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart1_DmaDriverState); +} + +static ARM_USART_STATUS USART1_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart1_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART1_Handle; +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) +static uint8_t usart1_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart1_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart1_NonBlockingDriverState = { +#endif + &usart1_Resource, + &USART1_Handle, +}; + +static int32_t USART1_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART1_PIN_INIT + RTE_USART1_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART1_PIN_DEINIT + RTE_USART1_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + int32_t result; + + result = USART_NonBlockingPowerControl(state, &usart1_NonBlockingDriverState); +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart1_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart1_NonBlockingDriverState.resource->base, + usart1_NonBlockingDriverState.handle, usart1_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART1_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart1_NonBlockingDriverState); +} + +static uint32_t USART1_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart1_NonBlockingDriverState); +} + +static uint32_t USART1_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart1_NonBlockingDriverState); +} + +static int32_t USART1_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart1_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART1_RX_BUFFER_ENABLE) && (USART1_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart1_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART1_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart1_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART1 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART1_DMA_EN + USART1_DmaInitialize, USART1_DmaUninitialize, USART1_DmaPowerControl, USART1_DmaSend, USART1_DmaReceive, + USART1_DmaTransfer, USART1_DmaGetTxCount, USART1_DmaGetRxCount, USART1_DmaControl, USART1_DmaGetStatus, +#else + USART1_NonBlockingInitialize, + USART1_NonBlockingUninitialize, + USART1_NonBlockingPowerControl, + USART1_NonBlockingSend, + USART1_NonBlockingReceive, + USART1_NonBlockingTransfer, + USART1_NonBlockingGetTxCount, + USART1_NonBlockingGetRxCount, + USART1_NonBlockingControl, + USART1_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart1 */ + +#if defined(USART2) && defined(RTE_USART2) && RTE_USART2 + +/* User needs to provide the implementation for USART2_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART2_GetFreq(void); + +static cmsis_usart_resource_t usart2_Resource = {USART2, USART2_GetFreq}; + +/* usart2 Driver Control Block */ + +#if defined(RTE_USART2_DMA_EN) && RTE_USART2_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart2_DmaResource = { + RTE_USART2_DMA_TX_DMA_BASE, + RTE_USART2_DMA_TX_CH, + RTE_USART2_DMA_RX_DMA_BASE, + RTE_USART2_DMA_RX_CH, +}; + +static usart_dma_handle_t USART2_DmaHandle; +static dma_handle_t USART2_DmaRxHandle; +static dma_handle_t USART2_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart2_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart2_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart2_DmaDriverState = { +#endif + &usart2_Resource, &usart2_DmaResource, &USART2_DmaHandle, &USART2_DmaRxHandle, &USART2_DmaTxHandle, +}; + +static int32_t USART2_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART2_PIN_INIT + RTE_USART2_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaUninitialize(void) +{ +#ifdef RTE_USART2_PIN_DEINIT + RTE_USART2_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart2_DmaDriverState); +} + +static int32_t USART2_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart2_DmaDriverState); +} + +static int32_t USART2_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart2_DmaDriverState); +} + +static uint32_t USART2_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart2_DmaDriverState); +} + +static uint32_t USART2_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart2_DmaDriverState); +} + +static int32_t USART2_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart2_DmaDriverState); +} + +static ARM_USART_STATUS USART2_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart2_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART2_Handle; +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) +static uint8_t usart2_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart2_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart2_NonBlockingDriverState = { +#endif + &usart2_Resource, + &USART2_Handle, +}; + +static int32_t USART2_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART2_PIN_INIT + RTE_USART2_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART2_PIN_DEINIT + RTE_USART2_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + int32_t result; + + result = USART_NonBlockingPowerControl(state, &usart2_NonBlockingDriverState); +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart2_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart2_NonBlockingDriverState.resource->base, + usart2_NonBlockingDriverState.handle, usart2_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART2_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart2_NonBlockingDriverState); +} + +static uint32_t USART2_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart2_NonBlockingDriverState); +} + +static uint32_t USART2_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart2_NonBlockingDriverState); +} + +static int32_t USART2_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart2_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART2_RX_BUFFER_ENABLE) && (USART2_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart2_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART2_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart2_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART2 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART2_DMA_EN + USART2_DmaInitialize, USART2_DmaUninitialize, USART2_DmaPowerControl, USART2_DmaSend, USART2_DmaReceive, + USART2_DmaTransfer, USART2_DmaGetTxCount, USART2_DmaGetRxCount, USART2_DmaControl, USART2_DmaGetStatus, +#else + USART2_NonBlockingInitialize, + USART2_NonBlockingUninitialize, + USART2_NonBlockingPowerControl, + USART2_NonBlockingSend, + USART2_NonBlockingReceive, + USART2_NonBlockingTransfer, + USART2_NonBlockingGetTxCount, + USART2_NonBlockingGetRxCount, + USART2_NonBlockingControl, + USART2_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart2 */ + +#if defined(USART3) && defined(RTE_USART3) && RTE_USART3 + +/* User needs to provide the implementation for USART3_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART3_GetFreq(void); + +static cmsis_usart_resource_t usart3_Resource = {USART3, USART3_GetFreq}; + +/* usart3 Driver Control Block */ +#if defined(RTE_USART3_DMA_EN) && RTE_USART3_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart3_DmaResource = { + RTE_USART3_DMA_TX_DMA_BASE, + RTE_USART3_DMA_TX_CH, + RTE_USART3_DMA_RX_DMA_BASE, + RTE_USART3_DMA_RX_CH, +}; + +static usart_dma_handle_t USART3_DmaHandle; +static dma_handle_t USART3_DmaRxHandle; +static dma_handle_t USART3_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart3_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart3_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart3_DmaDriverState = { +#endif + &usart3_Resource, &usart3_DmaResource, &USART3_DmaHandle, &USART3_DmaRxHandle, &USART3_DmaTxHandle, +}; + +static int32_t USART3_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART3_PIN_INIT + RTE_USART3_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaUninitialize(void) +{ +#ifdef RTE_USART3_PIN_DEINIT + RTE_USART3_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart3_DmaDriverState); +} + +static int32_t USART3_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart3_DmaDriverState); +} + +static int32_t USART3_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart3_DmaDriverState); +} + +static uint32_t USART3_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart3_DmaDriverState); +} + +static uint32_t USART3_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart3_DmaDriverState); +} + +static int32_t USART3_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart3_DmaDriverState); +} + +static ARM_USART_STATUS USART3_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart3_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART3_Handle; +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) +static uint8_t usart3_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart3_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart3_NonBlockingDriverState = { +#endif + &usart3_Resource, + &USART3_Handle, +}; + +static int32_t USART3_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART3_PIN_INIT + RTE_USART3_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART3_PIN_DEINIT + RTE_USART3_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + int32_t result; + + result = USART_NonBlockingPowerControl(state, &usart3_NonBlockingDriverState); +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart3_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart3_NonBlockingDriverState.resource->base, + usart3_NonBlockingDriverState.handle, usart3_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART3_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart3_NonBlockingDriverState); +} + +static uint32_t USART3_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart3_NonBlockingDriverState); +} + +static uint32_t USART3_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart3_NonBlockingDriverState); +} + +static int32_t USART3_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart3_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART3_RX_BUFFER_ENABLE) && (USART3_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart3_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART3_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart3_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART3 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART3_DMA_EN + USART3_DmaInitialize, USART3_DmaUninitialize, USART3_DmaPowerControl, USART3_DmaSend, USART3_DmaReceive, + USART3_DmaTransfer, USART3_DmaGetTxCount, USART3_DmaGetRxCount, USART3_DmaControl, USART3_DmaGetStatus, +#else + USART3_NonBlockingInitialize, + USART3_NonBlockingUninitialize, + USART3_NonBlockingPowerControl, + USART3_NonBlockingSend, + USART3_NonBlockingReceive, + USART3_NonBlockingTransfer, + USART3_NonBlockingGetTxCount, + USART3_NonBlockingGetRxCount, + USART3_NonBlockingControl, + USART3_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart3 */ + +#if defined(USART4) && defined(RTE_USART4) && RTE_USART4 + +/* User needs to provide the implementation for USART4_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART4_GetFreq(void); + +static cmsis_usart_resource_t usart4_Resource = {USART4, USART4_GetFreq}; + +#if defined(RTE_USART4_DMA_EN) && RTE_USART4_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart4_DmaResource = { + RTE_USART4_DMA_TX_DMA_BASE, + RTE_USART4_DMA_TX_CH, + RTE_USART4_DMA_RX_DMA_BASE, + RTE_USART4_DMA_RX_CH, +}; + +static usart_dma_handle_t USART4_DmaHandle; +static dma_handle_t USART4_DmaRxHandle; +static dma_handle_t USART4_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart4_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart4_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart4_DmaDriverState = { +#endif + &usart4_Resource, &usart4_DmaResource, &USART4_DmaHandle, &USART4_DmaRxHandle, &USART4_DmaTxHandle, +}; + +static int32_t USART4_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART4_PIN_INIT + RTE_USART4_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaUninitialize(void) +{ +#ifdef RTE_USART4_PIN_DEINIT + RTE_USART4_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart4_DmaDriverState); +} + +static int32_t USART4_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart4_DmaDriverState); +} + +static int32_t USART4_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart4_DmaDriverState); +} + +static uint32_t USART4_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart4_DmaDriverState); +} + +static uint32_t USART4_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart4_DmaDriverState); +} + +static int32_t USART4_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart4_DmaDriverState); +} + +static ARM_USART_STATUS USART4_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart4_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART4_Handle; +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) +static uint8_t usart4_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart4_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart4_NonBlockingDriverState = { +#endif + &usart4_Resource, + &USART4_Handle, +}; + +static int32_t USART4_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART4_PIN_INIT + RTE_USART4_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART4_PIN_DEINIT + RTE_USART4_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart4_NonBlockingDriverState); +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart4_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart4_NonBlockingDriverState.resource->base, + usart4_NonBlockingDriverState.handle, usart4_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART4_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart4_NonBlockingDriverState); +} + +static uint32_t USART4_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart4_NonBlockingDriverState); +} + +static uint32_t USART4_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart4_NonBlockingDriverState); +} + +static int32_t USART4_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart4_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART4_RX_BUFFER_ENABLE) && (USART4_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart4_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART4_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart4_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART4 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART4_DMA_EN + USART4_DmaInitialize, USART4_DmaUninitialize, USART4_DmaPowerControl, USART4_DmaSend, USART4_DmaReceive, + USART4_DmaTransfer, USART4_DmaGetTxCount, USART4_DmaGetRxCount, USART4_DmaControl, USART4_DmaGetStatus, +#else + USART4_NonBlockingInitialize, + USART4_NonBlockingUninitialize, + USART4_NonBlockingPowerControl, + USART4_NonBlockingSend, + USART4_NonBlockingReceive, + USART4_NonBlockingTransfer, + USART4_NonBlockingGetTxCount, + USART4_NonBlockingGetRxCount, + USART4_NonBlockingControl, + USART4_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart4 */ + +#if defined(USART5) && defined(RTE_USART5) && RTE_USART5 + +/* User needs to provide the implementation for USART5_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART5_GetFreq(void); + +static cmsis_usart_resource_t usart5_Resource = {USART5, USART5_GetFreq}; + +#if defined(RTE_USART5_DMA_EN) && RTE_USART5_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart5_DmaResource = { + RTE_USART5_DMA_TX_DMA_BASE, + RTE_USART5_DMA_TX_CH, + RTE_USART5_DMA_RX_DMA_BASE, + RTE_USART5_DMA_RX_CH, +}; + +static usart_dma_handle_t USART5_DmaHandle; +static dma_handle_t USART5_DmaRxHandle; +static dma_handle_t USART5_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart5_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart5_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart5_DmaDriverState = { +#endif + &usart5_Resource, &usart5_DmaResource, &USART5_DmaHandle, &USART5_DmaRxHandle, &USART5_DmaTxHandle, +}; + +static int32_t USART5_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART5_PIN_INIT + RTE_USART5_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaUninitialize(void) +{ +#ifdef RTE_USART5_PIN_DEINIT + RTE_USART5_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart5_DmaDriverState); +} + +static int32_t USART5_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart5_DmaDriverState); +} + +static int32_t USART5_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart5_DmaDriverState); +} + +static uint32_t USART5_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart5_DmaDriverState); +} + +static uint32_t USART5_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart5_DmaDriverState); +} + +static int32_t USART5_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart5_DmaDriverState); +} + +static ARM_USART_STATUS USART5_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart5_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART5_Handle; +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) +static uint8_t usart5_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart5_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart5_NonBlockingDriverState = { +#endif + &usart5_Resource, + &USART5_Handle, +}; + +static int32_t USART5_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART5_PIN_INIT + RTE_USART5_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART5_PIN_DEINIT + RTE_USART5_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + int32_t result; + + result = USART_NonBlockingPowerControl(state, &usart5_NonBlockingDriverState); +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart5_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart5_NonBlockingDriverState.resource->base, + usart5_NonBlockingDriverState.handle, usart5_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART5_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart5_NonBlockingDriverState); +} + +static uint32_t USART5_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart5_NonBlockingDriverState); +} + +static uint32_t USART5_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart5_NonBlockingDriverState); +} + +static int32_t USART5_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart5_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART5_RX_BUFFER_ENABLE) && (USART5_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart5_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART5_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart5_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART5 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART5_DMA_EN + USART5_DmaInitialize, USART5_DmaUninitialize, USART5_DmaPowerControl, USART5_DmaSend, USART5_DmaReceive, + USART5_DmaTransfer, USART5_DmaGetTxCount, USART5_DmaGetRxCount, USART5_DmaControl, USART5_DmaGetStatus, +#else + USART5_NonBlockingInitialize, + USART5_NonBlockingUninitialize, + USART5_NonBlockingPowerControl, + USART5_NonBlockingSend, + USART5_NonBlockingReceive, + USART5_NonBlockingTransfer, + USART5_NonBlockingGetTxCount, + USART5_NonBlockingGetRxCount, + USART5_NonBlockingControl, + USART5_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart5 */ + +#if defined(USART6) && defined(RTE_USART6) && RTE_USART6 + +/* User needs to provide the implementation for USART6_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART6_GetFreq(void); + +static cmsis_usart_resource_t usart6_Resource = {USART6, USART6_GetFreq}; + +#if defined(RTE_USART6_DMA_EN) && RTE_USART6_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart6_DmaResource = { + RTE_USART6_DMA_TX_DMA_BASE, + RTE_USART6_DMA_TX_CH, + RTE_USART6_DMA_RX_DMA_BASE, + RTE_USART6_DMA_RX_CH, +}; + +static usart_dma_handle_t USART6_DmaHandle; +static dma_handle_t USART6_DmaRxHandle; +static dma_handle_t USART6_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart6_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart6_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart6_DmaDriverState = { +#endif + &usart6_Resource, &usart6_DmaResource, &USART6_DmaHandle, &USART6_DmaRxHandle, &USART6_DmaTxHandle, +}; + +static int32_t USART6_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART6_PIN_INIT + RTE_USART6_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaUninitialize(void) +{ +#ifdef RTE_USART6_PIN_DEINIT + RTE_USART6_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart6_DmaDriverState); +} + +static int32_t USART6_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart6_DmaDriverState); +} + +static int32_t USART6_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart6_DmaDriverState); +} + +static uint32_t USART6_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart6_DmaDriverState); +} + +static uint32_t USART6_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart6_DmaDriverState); +} + +static int32_t USART6_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart6_DmaDriverState); +} + +static ARM_USART_STATUS USART6_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart6_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART6_Handle; +#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) +static uint8_t usart6_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart6_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart6_NonBlockingDriverState = { +#endif + &usart6_Resource, + &USART6_Handle, +}; + +static int32_t USART6_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART6_PIN_INIT + RTE_USART6_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART6_PIN_DEINIT + RTE_USART6_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart6_NonBlockingDriverState); +#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart6_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart6_NonBlockingDriverState.resource->base, + usart6_NonBlockingDriverState.handle, usart6_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART6_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart6_NonBlockingDriverState); +} + +static uint32_t USART6_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart6_NonBlockingDriverState); +} + +static uint32_t USART6_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart6_NonBlockingDriverState); +} + +static int32_t USART6_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart6_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART6_RX_BUFFER_ENABLE) && (USART6_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart6_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART6_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart6_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART6 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART6_DMA_EN + USART6_DmaInitialize, USART6_DmaUninitialize, USART6_DmaPowerControl, USART6_DmaSend, USART6_DmaReceive, + USART6_DmaTransfer, USART6_DmaGetTxCount, USART6_DmaGetRxCount, USART6_DmaControl, USART6_DmaGetStatus, +#else + USART6_NonBlockingInitialize, + USART6_NonBlockingUninitialize, + USART6_NonBlockingPowerControl, + USART6_NonBlockingSend, + USART6_NonBlockingReceive, + USART6_NonBlockingTransfer, + USART6_NonBlockingGetTxCount, + USART6_NonBlockingGetRxCount, + USART6_NonBlockingControl, + USART6_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart6 */ + +#if defined(USART7) && defined(RTE_USART7) && RTE_USART7 + +/* User needs to provide the implementation for USART7_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART7_GetFreq(void); + +static cmsis_usart_resource_t usart7_Resource = {USART7, USART7_GetFreq}; + +#if defined(RTE_USART7_DMA_EN) && RTE_USART7_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart7_DmaResource = { + RTE_USART7_DMA_TX_DMA_BASE, + RTE_USART7_DMA_TX_CH, + RTE_USART7_DMA_RX_DMA_BASE, + RTE_USART7_DMA_RX_CH, +}; + +static usart_dma_handle_t USART7_DmaHandle; +static dma_handle_t USART7_DmaRxHandle; +static dma_handle_t USART7_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart7_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart7_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart7_DmaDriverState = { +#endif + &usart7_Resource, &usart7_DmaResource, &USART7_DmaHandle, &USART7_DmaRxHandle, &USART7_DmaTxHandle, +}; + +static int32_t USART7_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART7_PIN_INIT + RTE_USART7_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaUninitialize(void) +{ +#ifdef RTE_USART7_PIN_DEINIT + RTE_USART7_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart7_DmaDriverState); +} + +static int32_t USART7_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart7_DmaDriverState); +} + +static int32_t USART7_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart7_DmaDriverState); +} + +static uint32_t USART7_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart7_DmaDriverState); +} + +static uint32_t USART7_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart7_DmaDriverState); +} + +static int32_t USART7_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart7_DmaDriverState); +} + +static ARM_USART_STATUS USART7_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart7_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART7_Handle; +#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) +static uint8_t usart7_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart7_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart7_NonBlockingDriverState = { +#endif + &usart7_Resource, + &USART7_Handle, +}; + +static int32_t USART7_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART7_PIN_INIT + RTE_USART7_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART7_PIN_DEINIT + RTE_USART7_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart7_NonBlockingDriverState); +#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart7_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart7_NonBlockingDriverState.resource->base, + usart7_NonBlockingDriverState.handle, usart7_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART7_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart7_NonBlockingDriverState); +} + +static uint32_t USART7_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart7_NonBlockingDriverState); +} + +static uint32_t USART7_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart7_NonBlockingDriverState); +} + +static int32_t USART7_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart7_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART7_RX_BUFFER_ENABLE) && (USART7_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart7_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART7_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart7_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART7 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART7_DMA_EN + USART7_DmaInitialize, USART7_DmaUninitialize, USART7_DmaPowerControl, USART7_DmaSend, USART7_DmaReceive, + USART7_DmaTransfer, USART7_DmaGetTxCount, USART7_DmaGetRxCount, USART7_DmaControl, USART7_DmaGetStatus, +#else + USART7_NonBlockingInitialize, + USART7_NonBlockingUninitialize, + USART7_NonBlockingPowerControl, + USART7_NonBlockingSend, + USART7_NonBlockingReceive, + USART7_NonBlockingTransfer, + USART7_NonBlockingGetTxCount, + USART7_NonBlockingGetRxCount, + USART7_NonBlockingControl, + USART7_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart7 */ + +#if defined(USART8) && defined(RTE_USART8) && RTE_USART8 + +/* User needs to provide the implementation for USART8_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART8_GetFreq(void); + +static cmsis_usart_resource_t usart8_Resource = {USART8, USART8_GetFreq}; + +#if defined(RTE_USART8_DMA_EN) RTE_USART8_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart8_DmaResource = { + RTE_USART8_DMA_TX_DMA_BASE, + RTE_USART8_DMA_TX_CH, + RTE_USART8_DMA_RX_DMA_BASE, + RTE_USART8_DMA_RX_CH, +}; + +static usart_dma_handle_t USART8_DmaHandle; +static dma_handle_t USART8_DmaRxHandle; +static dma_handle_t USART8_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart8_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart8_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart8_DmaDriverState = { +#endif + &usart8_Resource, &usart8_DmaResource, &USART8_DmaHandle, &USART8_DmaRxHandle, &USART8_DmaTxHandle, +}; + +static int32_t USART8_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART8_PIN_INIT + RTE_USART8_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaUninitialize(void) +{ +#ifdef RTE_USART8_PIN_DEINIT + RTE_USART8_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart8_DmaDriverState); +} + +static int32_t USART8_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart8_DmaDriverState); +} + +static int32_t USART8_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart8_DmaDriverState); +} + +static uint32_t USART8_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart8_DmaDriverState); +} + +static uint32_t USART8_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart8_DmaDriverState); +} + +static int32_t USART8_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart8_DmaDriverState); +} + +static ARM_USART_STATUS USART8_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart8_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART8_Handle; +#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) +static uint8_t usart8_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart8_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart8_NonBlockingDriverState = { +#endif + &usart8_Resource, + &USART8_Handle, +}; + +static int32_t USART8_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART8_PIN_INIT + RTE_USART8_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART8_PIN_DEINIT + RTE_USART8_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart8_NonBlockingDriverState); +#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart8_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart8_NonBlockingDriverState.resource->base, + usart8_NonBlockingDriverState.handle, usart8_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t USART8_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart8_NonBlockingDriverState); +} + +static uint32_t USART8_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart8_NonBlockingDriverState); +} + +static uint32_t USART8_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart8_NonBlockingDriverState); +} + +static int32_t USART8_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart8_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART8_RX_BUFFER_ENABLE) && (USART8_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart8_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART8_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart8_NonBlockingDriverState); +} + +#endif + +/* usart8 Driver Control Block */ +ARM_DRIVER_USART Driver_USART8 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART8_DMA_EN + USART8_DmaInitialize, USART8_DmaUninitialize, USART8_DmaPowerControl, USART8_DmaSend, USART8_DmaReceive, + USART8_DmaTransfer, USART8_DmaGetTxCount, USART8_DmaGetRxCount, USART8_DmaControl, USART8_DmaGetStatus, +#else + USART8_NonBlockingInitialize, + USART8_NonBlockingUninitialize, + USART8_NonBlockingPowerControl, + USART8_NonBlockingSend, + USART8_NonBlockingReceive, + USART8_NonBlockingTransfer, + USART8_NonBlockingGetTxCount, + USART8_NonBlockingGetRxCount, + USART8_NonBlockingControl, + USART8_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart8 */ + +#if defined(USART9) && defined(RTE_USART9) && RTE_USART9 + +/* User needs to provide the implementation for USART9_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART9_GetFreq(void); + +static cmsis_usart_resource_t usart9_Resource = {USART9, USART9_GetFreq}; + +#if defined(RTE_USART9_DMA_EN) && RTE_USART9_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart9_DmaResource = { + RTE_USART9_DMA_TX_DMA_BASE, + RTE_USART9_DMA_TX_CH, + RTE_USART9_DMA_RX_DMA_BASE, + RTE_USART9_DMA_RX_CH, +}; + +static usart_dma_handle_t USART9_DmaHandle; +static dma_handle_t USART9_DmaRxHandle; +static dma_handle_t USART9_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart9_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart9_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart9_DmaDriverState = { +#endif + &usart9_Resource, &usart9_DmaResource, &USART9_DmaHandle, &USART9_DmaRxHandle, &USART9_DmaTxHandle, +}; + +static int32_t USART9_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART9_PIN_INIT + RTE_USART9_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaUninitialize(void) +{ +#ifdef RTE_USART9_PIN_DEINIT + RTE_USART9_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart9_DmaDriverState); +} + +static int32_t USART9_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart9_DmaDriverState); +} + +static int32_t USART9_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart9_DmaDriverState); +} + +static uint32_t USART9_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart9_DmaDriverState); +} + +static uint32_t USART9_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart9_DmaDriverState); +} + +static int32_t USART9_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart9_DmaDriverState); +} + +static ARM_USART_STATUS USART9_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart9_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART9_Handle; +#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) +static uint8_t usart9_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart9_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart9_NonBlockingDriverState = { +#endif + &usart9_Resource, + &USART9_Handle, +}; + +static int32_t USART9_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART9_PIN_INIT + RTE_USART9_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART9_PIN_DEINIT + RTE_USART9_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart9_NonBlockingDriverState); +#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart9_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart9_NonBlockingDriverState.resource->base, + usart9_NonBlockingDriverState.handle, usart9_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + + return result; +} + +static int32_t USART9_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart9_NonBlockingDriverState); +} + +static uint32_t USART9_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart9_NonBlockingDriverState); +} + +static uint32_t USART9_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart9_NonBlockingDriverState); +} + +static int32_t USART9_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart9_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART9_RX_BUFFER_ENABLE) && (USART9_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart9_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART9_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart9_NonBlockingDriverState); +} + +#endif + +/* usart9 Driver Control Block */ +ARM_DRIVER_USART Driver_USART9 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART9_DMA_EN + USART9_DmaInitialize, USART9_DmaUninitialize, USART9_DmaPowerControl, USART9_DmaSend, USART9_DmaReceive, + USART9_DmaTransfer, USART9_DmaGetTxCount, USART9_DmaGetRxCount, USART9_DmaControl, USART9_DmaGetStatus, +#else + USART9_NonBlockingInitialize, + USART9_NonBlockingUninitialize, + USART9_NonBlockingPowerControl, + USART9_NonBlockingSend, + USART9_NonBlockingReceive, + USART9_NonBlockingTransfer, + USART9_NonBlockingGetTxCount, + USART9_NonBlockingGetRxCount, + USART9_NonBlockingControl, + USART9_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart9 */ + +#if defined(USART10) && defined(RTE_USART10) && RTE_USART10 + +/* User needs to provide the implementation for USART10_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART10_GetFreq(void); + +static cmsis_usart_resource_t usart10_Resource = {USART10, USART10_GetFreq}; + +#if defined(RTE_USART10_DMA_EN) && RTE_USART10_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart10_DmaResource = { + RTE_USART10_DMA_TX_DMA_BASE, + RTE_USART10_DMA_TX_CH, + RTE_USART10_DMA_RX_DMA_BASE, + RTE_USART10_DMA_RX_CH, +}; + +static usart_dma_handle_t USART10_DmaHandle; +static dma_handle_t USART10_DmaRxHandle; +static dma_handle_t USART10_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart10_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart10_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart10_DmaDriverState = { +#endif + &usart10_Resource, &usart10_DmaResource, &USART10_DmaHandle, &USART10_DmaRxHandle, &USART10_DmaTxHandle, +}; + +static int32_t USART10_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART10_PIN_INIT + RTE_USART10_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart10_DmaDriverState); +} + +static int32_t USART10_DmaUninitialize(void) +{ +#ifdef RTE_USART10_PIN_DEINIT + RTE_USART10_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart10_DmaDriverState); +} + +static int32_t USART10_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart10_DmaDriverState); +} + +static int32_t USART10_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart10_DmaDriverState); +} + +static int32_t USART10_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart10_DmaDriverState); +} + +static int32_t USART10_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart10_DmaDriverState); +} + +static uint32_t USART10_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart10_DmaDriverState); +} + +static uint32_t USART10_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart10_DmaDriverState); +} + +static int32_t USART10_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart10_DmaDriverState); +} + +static ARM_USART_STATUS USART10_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart10_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART10_Handle; +#if defined(USART10_RX_BUFFER_ENABLE) && (USART10_RX_BUFFER_ENABLE == 1) +static uint8_t usart10_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart10_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart10_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart10_NonBlockingDriverState = { +#endif + &usart10_Resource, + &USART10_Handle, +}; + +static int32_t USART10_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART10_PIN_INIT + RTE_USART10_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart10_NonBlockingDriverState); +} + +static int32_t USART10_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART10_PIN_DEINIT + RTE_USART10_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart10_NonBlockingDriverState); +} + +static int32_t USART10_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart10_NonBlockingDriverState); +#if defined(USART10_RX_BUFFER_ENABLE) && (USART10_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart10_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart10_NonBlockingDriverState.resource->base, + usart10_NonBlockingDriverState.handle, usart10_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART10_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart10_NonBlockingDriverState); +} + +static int32_t USART10_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart10_NonBlockingDriverState); +} + +static int32_t USART10_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart10_NonBlockingDriverState); +} + +static uint32_t USART10_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart10_NonBlockingDriverState); +} + +static uint32_t USART10_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart10_NonBlockingDriverState); +} + +static int32_t USART10_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart10_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART10_RX_BUFFER_ENABLE) && (USART10_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart10_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART10_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart10_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART10 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART10_DMA_EN + USART10_DmaInitialize, USART10_DmaUninitialize, USART10_DmaPowerControl, USART10_DmaSend, USART10_DmaReceive, + USART10_DmaTransfer, USART10_DmaGetTxCount, USART10_DmaGetRxCount, USART10_DmaControl, USART10_DmaGetStatus, +#else + USART10_NonBlockingInitialize, + USART10_NonBlockingUninitialize, + USART10_NonBlockingPowerControl, + USART10_NonBlockingSend, + USART10_NonBlockingReceive, + USART10_NonBlockingTransfer, + USART10_NonBlockingGetTxCount, + USART10_NonBlockingGetRxCount, + USART10_NonBlockingControl, + USART10_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart10 */ + +#if defined(USART11) && defined(RTE_USART11) && RTE_USART11 + +/* User needs to provide the implementation for USART11_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART11_GetFreq(void); + +static cmsis_usart_resource_t usart11_Resource = {USART11, USART11_GetFreq}; + +#if defined(RTE_USART11_DMA_EN) && RTE_USART11_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart11_DmaResource = { + RTE_USART11_DMA_TX_DMA_BASE, + RTE_USART11_DMA_TX_CH, + RTE_USART11_DMA_RX_DMA_BASE, + RTE_USART11_DMA_RX_CH, +}; + +static usart_dma_handle_t USART11_DmaHandle; +static dma_handle_t USART11_DmaRxHandle; +static dma_handle_t USART11_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart11_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart11_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart11_DmaDriverState = { +#endif + &usart11_Resource, &usart11_DmaResource, &USART11_DmaHandle, &USART11_DmaRxHandle, &USART11_DmaTxHandle, +}; + +static int32_t USART11_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART11_PIN_INIT + RTE_USART11_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart11_DmaDriverState); +} + +static int32_t USART11_DmaUninitialize(void) +{ +#ifdef RTE_USART11_PIN_DEINIT + RTE_USART11_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart11_DmaDriverState); +} + +static int32_t USART11_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart11_DmaDriverState); +} + +static int32_t USART11_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart11_DmaDriverState); +} + +static int32_t USART11_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart11_DmaDriverState); +} + +static int32_t USART11_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart11_DmaDriverState); +} + +static uint32_t USART11_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart11_DmaDriverState); +} + +static uint32_t USART11_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart11_DmaDriverState); +} + +static int32_t USART11_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart11_DmaDriverState); +} + +static ARM_USART_STATUS USART11_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart11_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART11_Handle; +#if defined(USART11_RX_BUFFER_ENABLE) && (USART11_RX_BUFFER_ENABLE == 1) +static uint8_t usart11_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart11_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart11_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart11_NonBlockingDriverState = { +#endif + &usart11_Resource, + &USART11_Handle, +}; + +static int32_t USART11_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART11_PIN_INIT + RTE_USART11_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart11_NonBlockingDriverState); +} + +static int32_t USART11_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART11_PIN_DEINIT + RTE_USART11_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart11_NonBlockingDriverState); +} + +static int32_t USART11_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart11_NonBlockingDriverState); +#if defined(USART11_RX_BUFFER_ENABLE) && (USART11_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart11_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart11_NonBlockingDriverState.resource->base, + usart11_NonBlockingDriverState.handle, usart11_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART11_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart11_NonBlockingDriverState); +} + +static int32_t USART11_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart11_NonBlockingDriverState); +} + +static int32_t USART11_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart11_NonBlockingDriverState); +} + +static uint32_t USART11_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart11_NonBlockingDriverState); +} + +static uint32_t USART11_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart11_NonBlockingDriverState); +} + +static int32_t USART11_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart11_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART11_RX_BUFFER_ENABLE) && (USART11_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart11_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART11_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart11_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART11 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART11_DMA_EN + USART11_DmaInitialize, USART11_DmaUninitialize, USART11_DmaPowerControl, USART11_DmaSend, USART11_DmaReceive, + USART11_DmaTransfer, USART11_DmaGetTxCount, USART11_DmaGetRxCount, USART11_DmaControl, USART11_DmaGetStatus, +#else + USART11_NonBlockingInitialize, + USART11_NonBlockingUninitialize, + USART11_NonBlockingPowerControl, + USART11_NonBlockingSend, + USART11_NonBlockingReceive, + USART11_NonBlockingTransfer, + USART11_NonBlockingGetTxCount, + USART11_NonBlockingGetRxCount, + USART11_NonBlockingControl, + USART11_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart11 */ + +#if defined(USART12) && defined(RTE_USART12) && RTE_USART12 + +/* User needs to provide the implementation for USART12_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART12_GetFreq(void); + +static cmsis_usart_resource_t usart12_Resource = {USART12, USART12_GetFreq}; + +#if defined(RTE_USART12_DMA_EN) && RTE_USART12_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart12_DmaResource = { + RTE_USART12_DMA_TX_DMA_BASE, + RTE_USART12_DMA_TX_CH, + RTE_USART12_DMA_RX_DMA_BASE, + RTE_USART12_DMA_RX_CH, +}; + +static usart_dma_handle_t USART12_DmaHandle; +static dma_handle_t USART12_DmaRxHandle; +static dma_handle_t USART12_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart12_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart12_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart12_DmaDriverState = { +#endif + &usart12_Resource, &usart12_DmaResource, &USART12_DmaHandle, &USART12_DmaRxHandle, &USART12_DmaTxHandle, +}; + +static int32_t USART12_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART12_PIN_INIT + RTE_USART12_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart12_DmaDriverState); +} + +static int32_t USART12_DmaUninitialize(void) +{ +#ifdef RTE_USART12_PIN_DEINIT + RTE_USART12_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart12_DmaDriverState); +} + +static int32_t USART12_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart12_DmaDriverState); +} + +static int32_t USART12_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart12_DmaDriverState); +} + +static int32_t USART12_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart12_DmaDriverState); +} + +static int32_t USART12_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart12_DmaDriverState); +} + +static uint32_t USART12_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart12_DmaDriverState); +} + +static uint32_t USART12_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart12_DmaDriverState); +} + +static int32_t USART12_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart12_DmaDriverState); +} + +static ARM_USART_STATUS USART12_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart12_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART12_Handle; +#if defined(USART12_RX_BUFFER_ENABLE) && (USART12_RX_BUFFER_ENABLE == 1) +static uint8_t usart12_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart12_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart12_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart12_NonBlockingDriverState = { +#endif + &usart12_Resource, + &USART12_Handle, +}; + +static int32_t USART12_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART12_PIN_INIT + RTE_USART12_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart12_NonBlockingDriverState); +} + +static int32_t USART12_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART12_PIN_DEINIT + RTE_USART12_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart12_NonBlockingDriverState); +} + +static int32_t USART12_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart12_NonBlockingDriverState); +#if defined(USART12_RX_BUFFER_ENABLE) && (USART12_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart12_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart12_NonBlockingDriverState.resource->base, + usart12_NonBlockingDriverState.handle, usart12_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART12_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart12_NonBlockingDriverState); +} + +static int32_t USART12_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart12_NonBlockingDriverState); +} + +static int32_t USART12_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart12_NonBlockingDriverState); +} + +static uint32_t USART12_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart12_NonBlockingDriverState); +} + +static uint32_t USART12_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart12_NonBlockingDriverState); +} + +static int32_t USART12_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart12_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART12_RX_BUFFER_ENABLE) && (USART12_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart12_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART12_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart12_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART12 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART12_DMA_EN + USART12_DmaInitialize, USART12_DmaUninitialize, USART12_DmaPowerControl, USART12_DmaSend, USART12_DmaReceive, + USART12_DmaTransfer, USART12_DmaGetTxCount, USART12_DmaGetRxCount, USART12_DmaControl, USART12_DmaGetStatus, +#else + USART12_NonBlockingInitialize, + USART12_NonBlockingUninitialize, + USART12_NonBlockingPowerControl, + USART12_NonBlockingSend, + USART12_NonBlockingReceive, + USART12_NonBlockingTransfer, + USART12_NonBlockingGetTxCount, + USART12_NonBlockingGetRxCount, + USART12_NonBlockingControl, + USART12_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart12 */ + +#if defined(USART13) && defined(RTE_USART13) && RTE_USART13 + +/* User needs to provide the implementation for USART13_GetFreq/InitPins/DeinitPins +in the application for enabling according instance. */ +extern uint32_t USART13_GetFreq(void); + +static cmsis_usart_resource_t usart13_Resource = {USART13, USART13_GetFreq}; + +#if defined(RTE_USART13_DMA_EN) && RTE_USART13_DMA_EN + +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) + +cmsis_usart_dma_resource_t usart13_DmaResource = { + RTE_USART13_DMA_TX_DMA_BASE, + RTE_USART13_DMA_TX_CH, + RTE_USART13_DMA_RX_DMA_BASE, + RTE_USART13_DMA_RX_CH, +}; + +static usart_dma_handle_t USART13_DmaHandle; +static dma_handle_t USART13_DmaRxHandle; +static dma_handle_t USART13_DmaTxHandle; + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart13_dma_driver_state") +static cmsis_usart_dma_driver_state_t usart13_DmaDriverState = { +#else +static cmsis_usart_dma_driver_state_t usart13_DmaDriverState = { +#endif + &usart13_Resource, &usart13_DmaResource, &USART13_DmaHandle, &USART13_DmaRxHandle, &USART13_DmaTxHandle, +}; + +static int32_t USART13_DmaInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART13_PIN_INIT + RTE_USART13_PIN_INIT(); +#endif + return USART_DmaInitialize(cb_event, &usart13_DmaDriverState); +} + +static int32_t USART13_DmaUninitialize(void) +{ +#ifdef RTE_USART13_PIN_DEINIT + RTE_USART13_PIN_DEINIT(); +#endif + return USART_DmaUninitialize(&usart13_DmaDriverState); +} + +static int32_t USART13_DmaPowerControl(ARM_POWER_STATE state) +{ + return USART_DmaPowerControl(state, &usart13_DmaDriverState); +} + +static int32_t USART13_DmaSend(const void *data, uint32_t num) +{ + return USART_DmaSend(data, num, &usart13_DmaDriverState); +} + +static int32_t USART13_DmaReceive(void *data, uint32_t num) +{ + return USART_DmaReceive(data, num, &usart13_DmaDriverState); +} + +static int32_t USART13_DmaTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_DmaTransfer(data_out, data_in, num, &usart13_DmaDriverState); +} + +static uint32_t USART13_DmaGetTxCount(void) +{ + return USART_DmaGetTxCount(&usart13_DmaDriverState); +} + +static uint32_t USART13_DmaGetRxCount(void) +{ + return USART_DmaGetRxCount(&usart13_DmaDriverState); +} + +static int32_t USART13_DmaControl(uint32_t control, uint32_t arg) +{ + return USART_DmaControl(control, arg, &usart13_DmaDriverState); +} + +static ARM_USART_STATUS USART13_DmaGetStatus(void) +{ + return USART_DmaGetStatus(&usart13_DmaDriverState); +} + +#endif + +#else + +static usart_handle_t USART13_Handle; +#if defined(USART13_RX_BUFFER_ENABLE) && (USART13_RX_BUFFER_ENABLE == 1) +static uint8_t usart13_rxRingBuffer[USART_RX_BUFFER_LEN]; +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +ARMCC_SECTION("usart13_non_blocking_driver_state") +static cmsis_usart_non_blocking_driver_state_t usart13_NonBlockingDriverState = { +#else +static cmsis_usart_non_blocking_driver_state_t usart13_NonBlockingDriverState = { +#endif + &usart13_Resource, + &USART13_Handle, +}; + +static int32_t USART13_NonBlockingInitialize(ARM_USART_SignalEvent_t cb_event) +{ +#ifdef RTE_USART13_PIN_INIT + RTE_USART13_PIN_INIT(); +#endif + return USART_NonBlockingInitialize(cb_event, &usart13_NonBlockingDriverState); +} + +static int32_t USART13_NonBlockingUninitialize(void) +{ +#ifdef RTE_USART13_PIN_DEINIT + RTE_USART13_PIN_DEINIT(); +#endif + return USART_NonBlockingUninitialize(&usart13_NonBlockingDriverState); +} + +static int32_t USART13_NonBlockingPowerControl(ARM_POWER_STATE state) +{ + uint32_t result; + + result = USART_NonBlockingPowerControl(state, &usart13_NonBlockingDriverState); +#if defined(USART13_RX_BUFFER_ENABLE) && (USART13_RX_BUFFER_ENABLE == 1) + if ((state == ARM_POWER_FULL) && (usart13_NonBlockingDriverState.handle->rxRingBuffer == NULL)) + { + USART_TransferStartRingBuffer(usart13_NonBlockingDriverState.resource->base, + usart13_NonBlockingDriverState.handle, usart13_rxRingBuffer, USART_RX_BUFFER_LEN); + } +#endif + return result; +} + +static int32_t USART13_NonBlockingSend(const void *data, uint32_t num) +{ + return USART_NonBlockingSend(data, num, &usart13_NonBlockingDriverState); +} + +static int32_t USART13_NonBlockingReceive(void *data, uint32_t num) +{ + return USART_NonBlockingReceive(data, num, &usart13_NonBlockingDriverState); +} + +static int32_t USART13_NonBlockingTransfer(const void *data_out, void *data_in, uint32_t num) +{ + return USART_NonBlockingTransfer(data_out, data_in, num, &usart13_NonBlockingDriverState); +} + +static uint32_t USART13_NonBlockingGetTxCount(void) +{ + return USART_NonBlockingGetTxCount(&usart13_NonBlockingDriverState); +} + +static uint32_t USART13_NonBlockingGetRxCount(void) +{ + return USART_NonBlockingGetRxCount(&usart13_NonBlockingDriverState); +} + +static int32_t USART13_NonBlockingControl(uint32_t control, uint32_t arg) +{ + int32_t result; + + result = USART_NonBlockingControl(control, arg, &usart13_NonBlockingDriverState); + if (ARM_DRIVER_OK != result) + { + return result; + } +#if defined(USART13_RX_BUFFER_ENABLE) && (USART13_RX_BUFFER_ENABLE == 1) + /* Start receiving interrupts */ + usart13_NonBlockingDriverState.resource->base->FIFOINTENSET |= + USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; +#endif + return ARM_DRIVER_OK; +} + +static ARM_USART_STATUS USART13_NonBlockingGetStatus(void) +{ + return USART_NonBlockingGetStatus(&usart13_NonBlockingDriverState); +} + +#endif + +ARM_DRIVER_USART Driver_USART13 = { + USARTx_GetVersion, USARTx_GetCapabilities, +#if RTE_USART13_DMA_EN + USART13_DmaInitialize, USART13_DmaUninitialize, USART13_DmaPowerControl, USART13_DmaSend, USART13_DmaReceive, + USART13_DmaTransfer, USART13_DmaGetTxCount, USART13_DmaGetRxCount, USART13_DmaControl, USART13_DmaGetStatus, +#else + USART13_NonBlockingInitialize, + USART13_NonBlockingUninitialize, + USART13_NonBlockingPowerControl, + USART13_NonBlockingSend, + USART13_NonBlockingReceive, + USART13_NonBlockingTransfer, + USART13_NonBlockingGetTxCount, + USART13_NonBlockingGetRxCount, + USART13_NonBlockingControl, + USART13_NonBlockingGetStatus, +#endif + USARTx_SetModemControl, USARTx_GetModemStatus}; + +#endif /* usart13 */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_usart_cmsis.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_usart_cmsis.h new file mode 100644 index 0000000000..30fee3a0a3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/cmsis_drivers/fsl_usart_cmsis.h @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * Copyright (c) 2016, Freescale Semiconductor, Inc. Not a Contribution. + * Copyright 2016-2017 NXP. Not a Contribution. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef _FSL_USART_CMSIS_H_ +#define _FSL_USART_CMSIS_H_ + +#include "fsl_common.h" +#include "Driver_USART.h" +#include "RTE_Device.h" +#include "fsl_usart.h" +#if (defined(FSL_FEATURE_SOC_DMA_COUNT) && FSL_FEATURE_SOC_DMA_COUNT) +#include "fsl_usart_dma.h" +#endif + +#if defined(USART0) && defined(RTE_USART0) && RTE_USART0 +extern ARM_DRIVER_USART Driver_USART0; +#endif /* USART0 */ + +#if defined(USART1) && defined(RTE_USART1) && RTE_USART1 +extern ARM_DRIVER_USART Driver_USART1; +#endif /* USART1 */ + +#if defined(USART2) && defined(RTE_USART2) && RTE_USART2 +extern ARM_DRIVER_USART Driver_USART2; +#endif /* USART2 */ + +#if defined(USART3) && defined(RTE_USART3) && RTE_USART3 +extern ARM_DRIVER_USART Driver_USART3; +#endif /* USART3 */ + +#if defined(USART4) && defined(RTE_USART4) && RTE_USART4 +extern ARM_DRIVER_USART Driver_USART4; +#endif /* USART4 */ + +#if defined(USART5) && defined(RTE_USART5) && RTE_USART5 +extern ARM_DRIVER_USART Driver_USART5; +#endif /* USART5 */ + +#if defined(USART6) && defined(RTE_USART6) && RTE_USART6 +extern ARM_DRIVER_USART Driver_USART6; +#endif /* USART6 */ + +#if defined(USART7) && defined(RTE_USART7) && RTE_USART7 +extern ARM_DRIVER_USART Driver_USART7; +#endif /* USART7 */ + +#if defined(USART8) && defined(RTE_USART8) && RTE_USART8 +extern ARM_DRIVER_USART Driver_USART8; +#endif /* USART8 */ + +#if defined(USART9) && defined(RTE_USART9) && RTE_USART9 +extern ARM_DRIVER_USART Driver_USART9; +#endif /* USART9 */ + +#if defined(USART10) && defined(RTE_USART10) && RTE_USART10 +extern ARM_DRIVER_USART Driver_USART10; +#endif /* USART10 */ + +#if defined(USART11) && defined(RTE_USART11) && RTE_USART11 +extern ARM_DRIVER_USART Driver_USART11; +#endif /* USART11 */ + +#if defined(USART12) && defined(RTE_USART12) && RTE_USART12 +extern ARM_DRIVER_USART Driver_USART12; +#endif /* USART12 */ + +#if defined(USART13) && defined(RTE_USART13) && RTE_USART13 +extern ARM_DRIVER_USART Driver_USART13; +#endif /* USART13 */ + +/* USART Driver state flags */ +#define USART_FLAG_UNINIT (0UL) +#define USART_FLAG_INIT (1UL << 0) +#define USART_FLAG_POWER (1UL << 1) +#define USART_FLAG_CONFIGURED (1UL << 2) + +#endif /* _FSL_USART_CMSIS_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c index 08eb3b738f..68175b880a 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.c @@ -1,5 +1,5 @@ /* - * Copyright 2018, NXP + * Copyright 2018-2021, NXP * All rights reserved. * * @@ -60,9 +60,9 @@ static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base) } /*! - * @brief Enable the access to ANACTRL registers and initialize ANACTRL module. + * brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. * - * @param base ANACTRL peripheral base address. + * param base ANACTRL peripheral base address. */ void ANACTRL_Init(ANACTRL_Type *base) { @@ -75,9 +75,9 @@ void ANACTRL_Init(ANACTRL_Type *base) } /*! - * @brief De-initialize ANACTRL module. + * brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. * - * @param base ANACTRL peripheral base address. + * param base ANACTRL peripheral base address. */ void ANACTRL_Deinit(ANACTRL_Type *base) { @@ -90,214 +90,144 @@ void ANACTRL_Deinit(ANACTRL_Type *base) } /*! - * @brief Set the on-chip high-speed Free Running Oscillator. + * brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock output + * and enable/disable 96MHZ clock output. * - * @param base ANACTRL peripheral base address. - * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. + * param base ANACTRL peripheral base address. + * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config) +void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config) { assert(NULL != config); - uint32_t tmp32 = 0; + uint32_t tmp32 = base->FRO192M_CTRL; - /* Set FRO trim values. */ - base->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_WRTRIM_MASK; - tmp32 |= ANACTRL_FRO192M_CTRL_BIAS_TRIM(config->biasTrim) | ANACTRL_FRO192M_CTRL_TEMP_TRIM(config->tempTrim) | - ANACTRL_FRO192M_CTRL_DAC_TRIM(config->dacTrim); + tmp32 &= ~(ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK); if (config->enable12MHzClk) { tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK; } - if (config->enable48MhzClk) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK; - } if (config->enable96MHzClk) { tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; } - if (config->enableAnalogTestBus) - { - tmp32 |= ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK; - } - base->FRO192M_CTRL |= tmp32; } /*! - * @brief Get the default configuration of FRO192M. + * brief Gets the default configuration of FRO192M. * The default values are: * code - * config->biasTrim = 0x1AU; - * config->tempTrim = 0x20U; - * config->enable12MHzClk = true; - * config->enable48MhzClk = true; - * config->dacTrim = 0x80U; - * config->enableAnalogTestBus = false; - * config->enable96MHzClk = false; - * encode - * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. + config->enable12MHzClk = true; + config->enable96MHzClk = false; + endcode + * param config Pointer to FRO192M configuration structure. Refer to anactrl_fro192M_config_t structure. */ void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config) { assert(NULL != config); /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); - config->biasTrim = 0x1AU; - config->tempTrim = 0x20U; - config->enable12MHzClk = true; - config->enable48MhzClk = true; - config->dacTrim = 0x80U; - config->enableAnalogTestBus = false; - config->enable96MHzClk = false; + config->enable12MHzClk = true; + config->enable96MHzClk = false; } /*! - * @brief Set the 32 MHz Crystal oscillator. + * brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU + * system, and so on. * - * @param base ANACTRL peripheral base address. - * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. + * param base ANACTRL peripheral base address. + * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config) +void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config) { assert(NULL != config); - uint32_t tmp32 = 0U; + uint32_t tmp32 = base->XO32M_CTRL; + + tmp32 &= ~(ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK | ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK); /* Set XO32M CTRL. */ - if (config->enableACBufferBypass) - { - tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; - } +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) + tmp32 &= ~ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; if (config->enablePllUsbOutput) { tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK; } +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ + + if (config->enableACBufferBypass) + { + tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; + } + if (config->enableSysCLkOutput) { tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; } base->XO32M_CTRL = tmp32; - /* Set LDO XO32M. */ - tmp32 = ANACTRL_LDO_XO32M_HIGHZ(config->LDOOutputMode) | ANACTRL_LDO_XO32M_VOUT(config->LDOOutputLevel) | - ANACTRL_LDO_XO32M_IBIAS(config->bias) | ANACTRL_LDO_XO32M_STABMODE(config->stability); - if (config->enableLDOBypass) +#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) + if (config->enableADCOutput) { - tmp32 |= ANACTRL_LDO_XO32M_BYPASS_MASK; + base->DUMMY_CTRL |= ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; } - - base->LDO_XO32M = tmp32; + else + { + base->DUMMY_CTRL &= ~ANACTRL_DUMMY_CTRL_XO32M_ADC_CLK_MODE_MASK; + } +#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ } /*! - * @brief Get the default configuration of XO32M. + * brief Gets the default configuration of XO32M. * The default values are: * code - * config->enableACBufferBypass = false; - * config->enablePllUsbOutput = false; - * config->enableSysCLkOutput = false; - * config->enableLDOBypass = false; - * config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode; - * config->LDOOutputLevel = kANACTRL_LDOOutputLevel4; - * config->bias = 2U; - * config->stability = 3U; - * encode - * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. + config->enableSysCLkOutput = false; + config->enableACBufferBypass = false; + endcode + * param config Pointer to XO32M configuration structure. Refer to anactrl_xo32M_config_t structure. */ void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config) { assert(NULL != config); /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); - config->enableACBufferBypass = false; - config->enablePllUsbOutput = false; +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) + config->enablePllUsbOutput = false; +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ config->enableSysCLkOutput = false; - config->enableLDOBypass = false; - config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode; - config->LDOOutputLevel = kANACTRL_LDOOutputLevel4; - config->bias = 2U; - config->stability = 3U; + config->enableACBufferBypass = false; +#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) + config->enableADCOutput = true; +#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ } +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) /*! - * @brief Set the ring oscillators. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure. - */ -void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config) -{ - assert(NULL != config); - - uint32_t tmp32 = 0U; - - /* Configure the first ring oscillator. */ - tmp32 = ANACTRL_RINGO0_CTRL_SL(config->ringOscSel) | ANACTRL_RINGO0_CTRL_FS(config->ringOscFreqOutputDiv) | - ANACTRL_RINGO0_CTRL_SWN_SWP(config->pnRingOscMode) | ANACTRL_RINGO0_CTRL_E_ND0_MASK | - ANACTRL_RINGO0_CTRL_E_ND1_MASK | ANACTRL_RINGO0_CTRL_E_NR0_MASK | ANACTRL_RINGO0_CTRL_E_NR1_MASK | - ANACTRL_RINGO0_CTRL_E_IV0_MASK | ANACTRL_RINGO0_CTRL_E_IV1_MASK | ANACTRL_RINGO0_CTRL_E_PN0_MASK | - ANACTRL_RINGO0_CTRL_E_PN1_MASK | ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK | - ANACTRL_RINGO0_CTRL_DIVISOR(config->ringOscOutClkDiv); - base->RINGO0_CTRL = tmp32; - - /* Configure the second and third ring oscillator. */ - tmp32 = ANACTRL_RINGO1_CTRL_S(config->ringOscSel) | ANACTRL_RINGO1_CTRL_FS(config->ringOscFreqOutputDiv) | - ANACTRL_RINGO1_CTRL_E_R24_MASK | ANACTRL_RINGO1_CTRL_E_R35_MASK | ANACTRL_RINGO1_CTRL_E_M2_MASK | - ANACTRL_RINGO1_CTRL_E_M3_MASK | ANACTRL_RINGO1_CTRL_E_M4_MASK | ANACTRL_RINGO1_CTRL_E_M5_MASK | - ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK | ANACTRL_RINGO1_CTRL_DIVISOR(config->ringOscOutClkDiv); - base->RINGO1_CTRL = tmp32; - base->RINGO2_CTRL = tmp32; - - /* Ensure the Riongo module is enabled. */ - base->RINGO0_CTRL &= ~ANACTRL_RINGO0_CTRL_PD_MASK; - base->RINGO1_CTRL &= ~ANACTRL_RINGO1_CTRL_PD_MASK; - base->RINGO2_CTRL &= ~ANACTRL_RINGO2_CTRL_PD_MASK; -} - -/*! - * @brief Get the default configuration of ring oscillators. - * The default values are: - * code - * config->ringOscSel = kANACTRL_ShortRingOsc; - * config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput; - * config->pnRingOscMode = kANACTRL_NormalMode; - * config->ringOscOutClkDiv = 0U; - * encode - * @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure. - */ -void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config) -{ - assert(NULL != config); - - /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); - - config->ringOscSel = kANACTRL_ShortRingOsc; - config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput; - config->pnRingOscMode = kANACTRL_NormalMode; - config->ringOscOutClkDiv = 0U; -} - -/*! - * @brief Measure Frequency + * brief Measures the frequency of the target clock source. * * This function measures target frequency according to a accurate reference frequency.The formula is: * Ftarget = (CAPVAL * Freference) / ((1<FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK); - targetClkFreq = (capval * refClkFreq) / ((1 << scale) - 1); + targetClkFreq = (capval * refClkFreq) / ((1UL << scale) - 1UL); return targetClkFreq; } +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h index bf55295bfd..4ca845b5a9 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_anactrl.h @@ -1,5 +1,5 @@ /* - * Copyright 2018, NXP + * Copyright 2018-2021, NXP * All rights reserved. * * @@ -20,31 +20,41 @@ * Definitions ******************************************************************************/ /*! @brief ANACTRL driver version. */ -#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */` +#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */` /*! * @brief ANACTRL interrupt flags */ enum _anactrl_interrupt_flags { - kANACTRL_BodVbatFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before Interrupt Enable. */ - kANACTRL_BodVbatInterruptFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status after Interrupt Enable. */ - kANACTRL_BodVbatPowerFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power status output. */ - kANACTRL_BodCoreFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before Interrupt Enable. */ - kANACTRL_BodCoreInterruptFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status after Interrupt Enable. */ - kANACTRL_BodCorePowerFlag = - ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power status output. */ - kANACTRL_DcdcFlag = - ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before Interrupt Enable. */ - kANACTRL_DcdcInterruptFlag = - ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after Interrupt Enable. */ - kANACTRL_DcdcPowerFlag = - ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power status output. */ +#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) + kANACTRL_BodVDDMainFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status + before Interrupt Enable. */ + kANACTRL_BodVDDMainInterruptFlag = + ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_INT_STATUS_MASK, /*!< BOD VDDMAIN Interrupt status + after Interrupt Enable. */ + kANACTRL_BodVDDMainPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVDDMAIN_VAL_MASK, /*!< Current value of BOD VDDMAIN + power status output. */ +#else + kANACTRL_BodVbatFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before + Interrupt Enable. */ + kANACTRL_BodVbatInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status + after Interrupt Enable. */ + kANACTRL_BodVbatPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power + status output. */ +#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ + kANACTRL_BodCoreFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before + Interrupt Enable. */ + kANACTRL_BodCoreInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status + after Interrupt Enable. */ + kANACTRL_BodCorePowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power + status output. */ + kANACTRL_DcdcFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before + Interrupt Enable. */ + kANACTRL_DcdcInterruptFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after + Interrupt Enable. */ + kANACTRL_DcdcPowerFlag = ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power + status output. */ }; /*! @@ -52,19 +62,16 @@ enum _anactrl_interrupt_flags */ enum _anactrl_interrupt { - kANACTRL_BodVbatInterruptEnable = - ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt control. */ - kANACTRL_BodCoreInterruptEnable = - ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt control. */ - kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */ - kANACTRL_BodVbatInterruptClear = - ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK, /*!< BOD VBAT interrupt clear.1: Clear the interrupt. - Self-cleared bit. */ - kANACTRL_BodCoreInterruptClear = - ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK, /*!< BOD CORE interrupt clear.1: Clear the interrupt. - Self-cleared bit. */ - kANACTRL_DcdcInterruptClear = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK, /*!< DCDC interrupt clear.1: Clear the - interrupt. Self-cleared bit. */ +#if (defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) + kANACTRL_BodVDDMainInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVDDMAIN_INT_ENABLE_MASK, /*!< BOD VDDMAIN + interrupt control. */ +#else + kANACTRL_BodVbatInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt + control. */ +#endif /* defined(FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN) && FSL_FEATURE_ANACTRL_CONTROL_VDD_MAIN */ + kANACTRL_BodCoreInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt + control. */ + kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */ }; /*! @@ -72,15 +79,9 @@ enum _anactrl_interrupt */ enum _anactrl_flags { - kANACTRL_PMUId = ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK, /*!< Power Management Unit (PMU) analog macro-bloc - identification number. */ - kANACTRL_OSCId = - ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK, /*!< Oscillators analog macro-bloc identification number. */ - kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */ - kANACTRL_FlashInitErrorFlag = - ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization error status. */ - kANACTRL_FinalTestFlag = - ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK, /*!< Indicates current status of final test. */ + kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */ + kANACTRL_FlashInitErrorFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization + error status. */ }; /*! @@ -88,68 +89,15 @@ enum _anactrl_flags */ enum _anactrl_osc_flags { - kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */ - kANACTRL_CCOThresholdVoltageFlag = - ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector output (signal vcco_ok). */ - kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK - << 16U, /*!< Indicates XO out frequency statibilty. */ + kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */ + kANACTRL_CCOThresholdVoltageFlag = ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector + output (signal vcco_ok). */ + kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK << 16U, /*!< Indicates XO out + frequency statibilty. */ }; /*! - * @brief LDO output mode - */ -typedef enum _anactrl_ldo_output_mode -{ - kANACTRL_LDOOutputHighNormalMode = 0U, /*!< Output in High normal state. */ - kANACTRL_LDOOutputHighImpedanceMode = 1U, /*!< Output in High Impedance state. */ -} anactrl_ldo_output_mode_t; - -/*! - * @brief LDO output level - */ -typedef enum _anactrl_ldo_output_level -{ - kANACTRL_LDOOutputLevel0 = 0U, /*!< Output level 0.750 V. */ - kANACTRL_LDOOutputLevel1, /*!< Output level 0.775 V. */ - kANACTRL_LDOOutputLevel2, /*!< Output level 0.800 V. */ - kANACTRL_LDOOutputLevel3, /*!< Output level 0.825 V. */ - kANACTRL_LDOOutputLevel4, /*!< Output level 0.850 V. */ - kANACTRL_LDOOutputLevel5, /*!< Output level 0.875 V. */ - kANACTRL_LDOOutputLevel6, /*!< Output level 0.900 V. */ - kANACTRL_LDOOutputLevel7, /*!< Output level 0.925 V. */ -} anactrl_ldo_output_level_t; - -/*! - * @brief Select short or long ring osc - */ -typedef enum _anactrl_ring_osc_selector -{ - kANACTRL_ShortRingOsc = 0U, /*!< Select short ring osc (few elements). */ - kANACTRL_LongRingOsc = 1U, /*!< Select long ring osc (many elements). */ -} anactrl_ring_osc_selector_t; - -/*! - * @brief Ring osc frequency output divider - */ -typedef enum _anactrl_ring_osc_freq_output_divider -{ - kANACTRL_HighFreqOutput = 0U, /*!< High frequency output (frequency lower than 100 MHz). */ - kANACTRL_LowFreqOutput = 1U, /*!< Low frequency output (frequency lower than 10 MHz). */ -} anactrl_ring_osc_freq_output_divider_t; - -/*! - * @brief PN-Ring osc (P-Transistor and N-Transistor processing) control. - */ -typedef enum _anactrl_pn_ring_osc_mode -{ - kANACTRL_NormalMode = 0U, /*!< Normal mode. */ - kANACTRL_PMonitorPTransistorMode = 1U, /*!< P-Monitor mode. Measure with weak P transistor. */ - kANACTRL_PMonitorNTransistorMode = 2U, /*!< P-Monitor mode. Measure with weak N transistor. */ - kANACTRL_NotUse = 3U, /*!< Do not use. */ -} anactrl_pn_ring_osc_mode_t; - -/*! - * @breif Configuration for FRO192M + * @brief Configuration for FRO192M * * This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize * this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a @@ -157,18 +105,12 @@ typedef enum _anactrl_pn_ring_osc_mode */ typedef struct _anactrl_fro192M_config { - uint8_t biasTrim; /*!< Set bias trimming value (course frequency trimming). */ - uint8_t tempTrim; /*!< Set temperature coefficient trimming value. */ - uint8_t dacTrim; /*!< Set curdac trimming value (fine frequency trimming) This trim is used to - adjust the frequency, given that the bias and temperature trim are set. */ - bool enable12MHzClk; /*!< Enable 12MHz clock. */ - bool enable48MhzClk; /*!< Enable 48MHz clock. */ - bool enable96MHzClk; /*!< Enable 96MHz clock. */ - bool enableAnalogTestBus; /*!< Enable analog test bus. */ + bool enable12MHzClk; /*!< Enable 12MHz clock. */ + bool enable96MHzClk; /*!< Enable 96MHz clock. */ } anactrl_fro192M_config_t; /*! - * @breif Configuration for XO32M + * @brief Configuration for XO32M * * This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this * structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a @@ -176,30 +118,18 @@ typedef struct _anactrl_fro192M_config */ typedef struct _anactrl_xo32M_config { - bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */ - bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */ - bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */ - bool enableLDOBypass; /*!< Activate LDO bypass. */ - anactrl_ldo_output_mode_t LDOOutputMode; /*!< Set LDO output mode. */ - anactrl_ldo_output_level_t LDOOutputLevel; /*!< Set LDO output level. */ - uint8_t bias; /*!< Adjust the biasing current. */ - uint8_t stability; /*!< Stability configuration. */ + bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */ +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD) + bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */ +#endif /* FSL_FEATURE_ANACTRL_HAS_NO_ENABLE_PLL_USB_OUT_BIT_FIELD */ + bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */ +#if (defined(FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) && \ + FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD) + bool enableADCOutput; /*!< Enable High speed crystal oscillator output to ADC. */ +#endif /* FSL_FEATURE_ANACTRL_HAS_XO32M_ADC_CLK_MODE_BIF_FIELD */ } anactrl_xo32M_config_t; -/*! - * @breif Configuration for ring oscillator - * - * This structure holds the configuration settings for the three ring oscillators. To initialize this - * structure to reasonable defaults, call the ANACTRL_GetDefaultRingOscConfig() function and pass a - * pointer to your config structure instance. - */ -typedef struct _anactrl_ring_osc_config -{ - anactrl_ring_osc_selector_t ringOscSel; - anactrl_ring_osc_freq_output_divider_t ringOscFreqOutputDiv; - anactrl_pn_ring_osc_mode_t pnRingOscMode; - uint8_t ringOscOutClkDiv; -} anactrl_ring_osc_config_t; /******************************************************************************* * API ******************************************************************************/ @@ -214,14 +144,14 @@ extern "C" { */ /*! - * @brief Enable the access to ANACTRL registers and initialize ANACTRL module. + * @brief Initializes the ANACTRL mode, the module's clock will be enabled by invoking this function. * * @param base ANACTRL peripheral base address. */ void ANACTRL_Init(ANACTRL_Type *base); /*! - * @brief De-initialize ANACTRL module. + * @brief De-initializes ANACTRL module, the module's clock will be disabled by invoking this function. * * @param base ANACTRL peripheral base address. */ @@ -234,120 +164,71 @@ void ANACTRL_Deinit(ANACTRL_Type *base); */ /*! - * @brief Set the on-chip high-speed Free Running Oscillator. + * @brief Configs the on-chip high-speed Free Running Oscillator(FRO192M), such as enabling/disabling 12 MHZ clock + * output and enable/disable 96MHZ clock output. * * @param base ANACTRL peripheral base address. - * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. + * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. */ -void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config); +void ANACTRL_SetFro192M(ANACTRL_Type *base, const anactrl_fro192M_config_t *config); /*! - * @brief Get the default configuration of FRO192M. + * @brief Gets the default configuration of FRO192M. * The default values are: - * code - * config->biasTrim = 0x1AU; - * config->tempTrim = 0x20U; - * config->enable12MHzClk = true; - * config->enable48MhzClk = true; - * config->dacTrim = 0x80U; - * config->enableAnalogTestBus = false; - * config->enable96MHzClk = false; - * encode - * @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure. + * @code + config->enable12MHzClk = true; + config->enable96MHzClk = false; + @endcode + * @param config Pointer to FRO192M configuration structure. Refer to @ref anactrl_fro192M_config_t structure. */ void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config); /*! - * @brief Set the 32 MHz Crystal oscillator. + * @brief Configs the 32 MHz Crystal oscillator(High-speed crystal oscillator), such as enable/disable output to CPU + * system, and so on. * * @param base ANACTRL peripheral base address. - * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. + * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. */ -void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config); +void ANACTRL_SetXo32M(ANACTRL_Type *base, const anactrl_xo32M_config_t *config); /*! - * @brief Get the default configuration of XO32M. + * @brief Gets the default configuration of XO32M. * The default values are: - * code - * config->enableACBufferBypass = false; - * config->enablePllUsbOutput = false; - * config->enableSysCLkOutput = false; - * config->enableLDOBypass = false; - * config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode; - * config->LDOOutputLevel = kANACTRL_LDOOutputLevel4; - * config->bias = 2U; - * config->stability = 3U; - * encode - * @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure. + * @code + config->enableSysCLkOutput = false; + config->enableACBufferBypass = false; + @endcode + * @param config Pointer to XO32M configuration structure. Refer to @ref anactrl_xo32M_config_t structure. */ void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config); -/*! - * @brief Set the ring oscillators. - * - * @param base ANACTRL peripheral base address. - * @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure. - */ -void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config); - -/*! - * @brief Get the default configuration of ring oscillators. - * The default values are: - * code - * config->ringOscSel = kANACTRL_ShortRingOsc; - * config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput; - * config->pnRingOscMode = kANACTRL_NormalMode; - * config->ringOscOutClkDiv = 0U; - * encode - * @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure. - */ -void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config); -/* @} */ - -/*! - * @name ADC control - * @{ - */ - -/*! - * @brief Enable VBAT divider branch. - * - * @param base ANACTRL peripheral base address. - * @param enable switcher to the function. - */ -static inline void ANACTRL_EnableAdcVBATDivider(ANACTRL_Type *base, bool enable) -{ - if (enable) - { - base->ADC_CTRL |= ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK; - } - else - { - base->ADC_CTRL &= ~ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK; - } -} /* @} */ +#if !(defined(FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) && FSL_FEATURE_ANACTRL_HAS_NO_FREQ_ME_CTRL) /*! * @name Measure Frequency * @{ */ /*! - * @brief Measure Frequency + * @brief Measures the frequency of the target clock source. * * This function measures target frequency according to a accurate reference frequency.The formula is: * Ftarget = (CAPVAL * Freference) / ((1<BOD_DCDC_INT_CTRL |= (0x15U & mask); } /*! - * @brief Disable the ANACTRL interrupts. + * @brief Disables the ANACTRL interrupts. * - * @param bas ANACTRL peripheral base address. + * @param base ANACTRL peripheral base address. * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. */ -static inline void ANACTRL_DisableInterrupt(ANACTRL_Type *base, uint32_t mask) +static inline void ANACTRL_DisableInterrupts(ANACTRL_Type *base, uint32_t mask) { - base->BOD_DCDC_INT_CTRL = (base->BOD_DCDC_INT_CTRL & ~0x2AU) | (mask & 0x2AU); + base->BOD_DCDC_INT_CTRL &= ~(0x15U & mask); +} + +/*! + * @brief Clears the ANACTRL interrupts. + * + * @param base ANACTRL peripheral base address. + * @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration. + */ +static inline void ANACTRL_ClearInterrupts(ANACTRL_Type *base, uint32_t mask) +{ + base->BOD_DCDC_INT_CTRL |= (uint32_t)(mask << 1UL); } /* @} */ @@ -383,7 +275,7 @@ static inline void ANACTRL_DisableInterrupt(ANACTRL_Type *base, uint32_t mask) */ /*! - * @brief Get ANACTRL status flags. + * @brief Gets ANACTRL status flags. * * This function gets Analog control status flags. The flags are returned as the logical * OR value of the enumerators @ref _anactrl_flags. To check for a specific status, @@ -405,7 +297,7 @@ static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base) } /*! - * @brief Get ANACTRL oscillators status flags. + * @brief Gets ANACTRL oscillators status flags. * * This function gets Anactrl oscillators status flags. The flags are returned as the logical * OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status, @@ -427,7 +319,7 @@ static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base) } /*! - * @brief Get ANACTRL interrupt status flags. + * @brief Gets ANACTRL interrupt status flags. * * This function gets Anactrl interrupt status flags. The flags are returned as the logical * OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status, @@ -449,6 +341,33 @@ static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base) } /* @} */ +#if (defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) && (FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG == 1U)) +/*! + * @brief Aux_Bias Control Interfaces + * @{ + */ + +/*! + * @brief Enables/disabless 1V reference voltage buffer. + * + * @param base ANACTRL peripheral base address. + * @param enable Used to enable or disable 1V reference voltage buffer. + */ +static inline void ANACTRL_EnableVref1V(ANACTRL_Type *base, bool enable) +{ + if (enable) + { + base->AUX_BIAS |= ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; + } + else + { + base->AUX_BIAS &= ~ANACTRL_AUX_BIAS_VREF1VENABLE_MASK; + } +} + +/* @} */ +#endif /* defined(FSL_FEATURE_ANACTRL_HAS_AUX_BIAS_REG) */ + #if defined(__cplusplus) } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.c index 543869bd8a..ed3770fa8b 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * All rights reserved. * * @@ -18,169 +18,200 @@ #define FSL_COMPONENT_ID "platform.drivers.casper" #endif +/* Recoding length for the secure scalar multiplication: + * Use n=256 and w=4 --> compute ciel(384/3) = 86 + 1 digits + * Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits + * Use n=521 and w=4 --> compute ciel(521/3) = 174 + 1 digits + */ + +/*!< Recoding length for the secure scalar multiplication */ +enum _casper_ecc_recode_len +{ + kCASPER_ECC_P256_recode_len = 87u, + kCASPER_ECC_P384_recode_len = 129u, + kCASPER_ECC_P521_recode_len = 175u, +}; + +enum _casper_ecc_N_bitlen +{ + kCASPER_ECC_P256_N_bitlen = 256u, + kCASPER_ECC_P384_N_bitlen = 384u, + kCASPER_ECC_P521_N_bitlen = 576u, +}; + +enum _casper_ecc_N_wordlen +{ + kCASPER_ECC_P256_wordlen = 256U / 32U, + kCASPER_ECC_P384_wordlen = 384u / 32U, + kCASPER_ECC_P521_wordlen = 576u / 32U, +}; + +#if defined(__GNUC__) +/* Enforce O1 optimize level, specifically to remove strict-aliasing option. + (-fno-strict-aliasing is required for this driver). */ +#pragma GCC push_options +#pragma GCC optimize("-O1") +#endif + +#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +/* Enforce optimization off for clang, specifically to remove strict-aliasing option. +(-fno-strict-aliasing is required for this driver). */ +#pragma clang optimize off +#endif + +/* CASPER driver allows usage of 256, 384 and 521 ECC */ +#define CASPER_MAX_ECC_SIZE_WORDLEN (576u / 32U) +#define CASPER_RECODE_LENGTH_MAX 175 + #define CASPER_RAM_BASE_NS (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS) #if defined(FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED) && FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED -#define CASPER_RAM_OFFSET (0xE) -#define INTERLEAVE(addr) \ - (((((((addr) >> 2) & 0x00000001) << CASPER_RAM_OFFSET) + (((addr) >> 3) << 2) + ((addr)&0x00000003)) & 0xFFFF) | \ +#define CASPER_RAM_OFFSET (FSL_FEATURE_CASPER_RAM_OFFSET) +#define INTERLEAVE(addr) \ + (((((((addr) >> 2U) & 0x00000001U) << CASPER_RAM_OFFSET) + (((addr) >> 3U) << 2U) + ((addr)&0x00000003U)) & \ + 0xFFFFU) | \ s_casperRamBase) -#define DEINTERLEAVE(addr) INTERLEAVE(addr) -#define GET_WORD(addr) (*((uint32_t *)DEINTERLEAVE((uint32_t)(addr)))) -#define GET_DWORD(addr) (((uint64_t)GET_WORD(addr)) | (((uint64_t)GET_WORD(((uint32_t)(addr)) + 4)) << 32)) +#define DEINTERLEAVE(addr) INTERLEAVE(addr) +#define GET_WORD(addr) (*((uint32_t *)DEINTERLEAVE((uint32_t)(addr)))) +#define GET_DWORD(addr) (((uint64_t)GET_WORD(addr)) | (((uint64_t)GET_WORD(((uint32_t)(addr)) + 4U)) << 32U)) #define SET_WORD(addr, value) *((uint32_t *)INTERLEAVE((uint32_t)(addr))) = ((uint32_t)(value)) -#define SET_DWORD(addr, value) \ - do \ - { \ - SET_WORD(addr, (uint32_t)(value & 0xFFFFFFFF)); \ - SET_WORD(((uint32_t)(addr)) + 4, (uint32_t)((value & 0xFFFFFFFF00000000) >> 32)); \ - } while (0) +#define SET_DWORD(addr, value) \ + do \ + { \ + SET_WORD(addr, (uint32_t)(value & 0xFFFFFFFFU)); \ + SET_WORD(((uint32_t)(addr)) + 4U, (uint32_t)((value & 0xFFFFFFFF00000000U) >> 32U)); \ + } while (false) /* memcopy is always word aligned */ /* interleaved to interleaved static void CASPER_MEMCPY_I2I(void *dst, const void *src, size_t siz) */ -#define CASPER_MEMCPY_I2I(dst, src, siz) \ - \ -{ \ - uint32_t *dst32 = (uint32_t *)dst, *src32 = (uint32_t *)src; \ - int i; \ - for (i = 0; i < siz / 4; i++) \ - { \ - SET_WORD(&dst32[i], GET_WORD(&src32[i])); \ - } \ - \ -} +#define CASPER_MEMCPY_I2I(dst, src, siz) \ + \ + { \ + uint32_t *dst32 = (uint32_t *)(dst); \ + const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ + uint32_t i; \ + for (i = 0U; i < (siz) / 4U; i++) \ + { \ + SET_WORD(&dst32[i], GET_WORD(&src32[i])); \ + } \ + } /* interleaved to non-interleaved static void CASPER_MEMCPY_I2N(void *dst, const void *src, size_t siz) */ -#define CASPER_MEMCPY_I2N(dst, src, siz) \ - \ -{ \ - uint32_t *dst32 = (uint32_t *)dst, *src32 = (uint32_t *)src; \ - int i; \ - for (i = 0; i < siz / 4; i++) \ - { \ - dst32[i] = GET_WORD(&src32[i]); \ - } \ - \ -} +#define CASPER_MEMCPY_I2N(dst, src, siz) \ + \ + { \ + uint32_t *dst32 = (uint32_t *)(dst); \ + const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ + uint32_t i; \ + for (i = 0U; i < (siz) / 4U; i++) \ + { \ + dst32[i] = GET_WORD(&src32[i]); \ + } \ + } /* non-interleaved to interleaved static void CASPER_MEMCPY_N2I(void *dst, const void *src, size_t siz) */ #define CASPER_MEMCPY_N2I(dst, src, siz) \ - \ -{ \ - volatile uint32_t *dst32 = (uint32_t *)dst, *src32 = (uint32_t *)src; \ - volatile int i; \ - for (i = 0; i < siz / 4; i++) \ + \ + { \ + volatile uint32_t *dst32 = (uint32_t *)(dst); \ + const uint32_t *src32 = (const uint32_t *)(const uint32_t *)(src); \ + uint32_t i; \ + for (i = 0U; i < (siz) / 4U; i++) \ { \ SET_WORD(&dst32[i], src32[i]); \ } \ - \ -} + } #else -#define GET_WORD(addr) (*((uint32_t *)(addr))) -#define GET_DWORD(addr) (*((uint64_t *)(addr))) -#define SET_WORD(addr, value) *((uint32_t *)(addr)) = ((uint32_t)(value)) +#define GET_WORD(addr) (*((uint32_t *)(uint32_t)(addr))) +#define GET_DWORD(addr) (*((uint64_t *)(addr))) +#define SET_WORD(addr, value) *((uint32_t *)(uint32_t)(addr)) = ((uint32_t)(value)) #define SET_DWORD(addr, value) *((uint64_t *)(addr)) = ((uint64_t)(value)) -#define CASPER_MEMCPY_I2I(dst, src, siz) memcpy(dst, src, siz) -#define CASPER_MEMCPY_I2N(dst, src, siz) memcpy(dst, src, siz) -#define CASPER_MEMCPY_N2I(dst, src, siz) memcpy(dst, src, siz) +#define CASPER_MEMCPY_I2I(dst, src, siz) (void)memcpy(dst, src, siz) +#define CASPER_MEMCPY_I2N(dst, src, siz) (void)memcpy(dst, src, siz) +#define CASPER_MEMCPY_N2I(dst, src, siz) (void)memcpy(dst, src, siz) #endif #define WORK_BUFF_MUL4 (N_wordlen_max * 4 + 2) /* ! working buffer is 4xN_wordlen to allow in place math */ -#define N_bytelen (N_wordlen * 4) /* for memory copy and the like */ -#define N_dwordlen (N_wordlen / 2) +#define N_bytelen (N_wordlen * 4U) /* for memory copy and the like */ +#define N_dwordlen (unsigned)(N_wordlen / 2U) -#define PreZeroW(i, w_out) \ - for (i = 0; i < N_wordlen; i += 4) \ - { \ - SET_WORD(&w_out[i + 0], 0); \ - SET_WORD(&w_out[i + 1], 0); \ - SET_WORD(&w_out[i + 2], 0); \ - SET_WORD(&w_out[i + 3], 0); \ +#define PreZeroW(i, w_out) \ + for ((i) = 0U; (i) < N_wordlen; (i) += 4U) \ + { \ + SET_WORD(&(w_out)[(i) + 0U], 0U); \ + SET_WORD(&(w_out)[(i) + 1U], 0U); \ + SET_WORD(&(w_out)[(i) + 2U], 0U); \ + SET_WORD(&(w_out)[(i) + 3U], 0U); \ } /* unrolled partly */ -#define PreZeroW2up(i, w_out) \ - for (i = N_wordlen; i <= N_wordlen * 2; i += 4) \ - { \ - SET_WORD(&w_out[i + 0], 0); \ - SET_WORD(&w_out[i + 1], 0); \ - SET_WORD(&w_out[i + 2], 0); \ - SET_WORD(&w_out[i + 3], 0); \ +#define PreZeroW2up(i, w_out) \ + for (i = N_wordlen; i <= N_wordlen * 2U; i += 4U) \ + { \ + SET_WORD(&w_out[i + 0U], 0U); \ + SET_WORD(&w_out[i + 1U], 0U); \ + SET_WORD(&w_out[i + 2U], 0U); \ + SET_WORD(&w_out[i + 3U], 0U); \ } /* unrolled partly */ /* Macros for the ECC component in Casper */ /* CASPER memory layout for ECC */ -#define CASPER_NUM_LIMBS (NUM_LIMBS + 4) // number of limbs needed by CASPER is 2 double words longer #define CASPER_MEM ((uint32_t *)msg_ret) -#define CASPER_OFFSET CASPER_NUM_LIMBS // offset in the CASPER memory where we can start writing - -#define MOD_SCRATCH_START (CASPER_OFFSET) -#define MOD_SCRATCH_SIZE (1 * CASPER_NUM_LIMBS) - -#define INOUT_SCRATCH_START (MOD_SCRATCH_START + MOD_SCRATCH_SIZE) -#define INOUT_SCRATCH_SIZE ((3 * 3) * CASPER_NUM_LIMBS) - -#define ECC_SCRATCH_START (INOUT_SCRATCH_START + INOUT_SCRATCH_SIZE) -#define ECC_SCRATCH_SIZE (9 * CASPER_NUM_LIMBS) - -#define LUT_SCRATCH_START (ECC_SCRATCH_START + ECC_SCRATCH_SIZE) -#define LUT_SCRATCH_SIZE (48 * NUM_LIMBS + 3 * CASPER_NUM_LIMBS) /* Currently these macros work on 32-bit platforms */ -#define add(c1, c0, a, b) \ - \ -do \ - { \ - uint32_t _t; \ - _t = a + b; \ - c1 = (_t < a); \ - c0 = _t; \ - \ -} \ - while (0) +#define add(c1, c0, a, b) \ + \ + do \ + { \ + uint32_t _t; \ + _t = a + b; \ + c1 = (uint32_t)(_t < a); \ + c0 = _t; \ + \ + } while (false) -#define add_cout(carry, c, a, b) add(carry, c, a, b) +#define add_cout(carry, c, a, b) add((carry), (c), (a), (b)) -#define add_cout_cin(carryout, c, a, b, carryin) \ - do \ - { \ - uint64_t _t = (uint64_t)a + b + carryin; \ - c = (uint32_t)_t; \ - carryout = (uint32_t)(_t >> 32); \ - } while (0) +#define add_cout_cin(carryout, c, a, b, carryin) \ + do \ + { \ + uint64_t _t = (uint64_t)(a) + (b) + (carryin); \ + (c) = (uint32_t)_t; \ + (carryout) = (uint32_t)(_t >> 32); \ + } while (false) -#define sub_borrowout(borrow, c, a, b) \ - do \ - { \ - uint32_t _b = (b > a); \ - c = a - b; \ - borrow = _b; \ - } while (0) +#define sub_borrowout(borrow, c, a, b) \ + do \ + { \ + uint32_t _b = (uint32_t)((b) > (a)); \ + (c) = (a) - (b); \ + (borrow) = _b; \ + } while (false) #define sub_borrowin_borrowout(borrowout, c, a, b, borrowin) \ do \ { \ uint32_t _t, _borrow1, _borrow2; \ - sub_borrowout(_borrow1, _t, a, b); \ - sub_borrowout(_borrow2, c, _t, borrowin); \ - borrowout = _borrow1 + _borrow2; \ - } while (0) + sub_borrowout(_borrow1, _t, (a), (b)); \ + sub_borrowout(_borrow2, (c), _t, (borrowin)); \ + (borrowout) = _borrow1 + _borrow2; \ + } while (false) #define sub_borrowout_1(borrow, c, a) \ do \ { \ uint32_t _b = 0; \ - c = a - b; \ - borrow = _b; \ - } while (0) + c = a - b; \ + borrow = _b; \ + } while (false) #define sub_borrowin_borrowout_1(borrowout, c, a, borrowin) \ do \ @@ -189,44 +220,42 @@ do \ sub_borrowout_1(_borrow1, _t, a); \ sub_borrowout(_borrow2, c, _t, borrowin); \ borrowout = _borrow1 + _borrow2; \ - } while (0) + } while (false) /* 32 x 32 --> 64-bit multiplication -* (c1,c0) = a * b -*/ -#define mul(c1, c0, a, b) \ - \ -do \ - { \ - uint64_t __m; \ - __m = (uint64_t)a * (uint64_t)b; \ - c0 = (uint32_t)__m; \ - c1 = (uint32_t)(__m >> (uint64_t)32); \ - \ -} \ - while (0) + * (c1,c0) = a * b + */ +#define mul(c1, c0, a, b) \ + \ + do \ + { \ + uint64_t __m; \ + __m = (uint64_t)a * (uint64_t)b; \ + c0 = (uint32_t)__m; \ + c1 = (uint32_t)(__m >> (uint64_t)32); \ + \ + } while (false) /* Multiply-and-accumulate -* (c1,c0) = a*b+c0 + * (c1,c0) = a*b+c0 */ #define muladd(c1, c0, a, b) \ - \ -do \ + \ + do \ { \ uint32_t __ma = c0; \ mul(c1, c0, a, b); \ c0 = c0 + __ma; \ c1 = c1 + (c0 < __ma); \ - \ -} \ - while (0) + \ + } while (0) /* Multiply-and-accumulate-accumulate -* (c1,c0) = a*b+c0+c1 -*/ + * (c1,c0) = a*b+c0+c1 + */ #define muladdadd(c1, c0, a, b) \ - \ -do \ + \ + do \ { \ uint32_t __maa0 = c0, __maa1 = c1; \ mul(c1, c0, a, b); \ @@ -234,72 +263,14 @@ do \ c1 = c1 + (c0 < __maa0); \ c0 = c0 + __maa1; \ c1 = c1 + (c0 < __maa1); \ - \ -} \ - while (0) - -#if CASPER_ECC_P256 - -/* Recoding length for the secure scalar multiplication: -* Use n=256 and w=4 --> compute ciel(384/3) = 86 + 1 digits -*/ -#define CASPER_RECODE_LENGTH 87 -#define invert(c, a) invert_mod_p256(c, a) -#define ONE NISTr256 - -/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ -#define shiftrightSysram(z, x, c) \ - do \ - { \ - z[0] = (x[1] << (32 - (c))) | (x[0] >> (c)); \ - z[1] = (x[2] << (32 - (c))) | (x[1] >> (c)); \ - z[2] = (x[3] << (32 - (c))) | (x[2] >> (c)); \ - z[3] = (x[4] << (32 - (c))) | (x[3] >> (c)); \ - z[4] = (x[5] << (32 - (c))) | (x[4] >> (c)); \ - z[5] = (x[6] << (32 - (c))) | (x[5] >> (c)); \ - z[6] = (x[7] << (32 - (c))) | (x[6] >> (c)); \ - z[7] = (x[7] >> (c)); \ + \ } while (0) -#elif CASPER_ECC_P384 - -/* Recoding length for the secure scalar multiplication: - * Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits - */ -#define CASPER_RECODE_LENGTH 129 -#define invert(c, a) invert_mod_p384(c, a) -#define ONE NISTr384 - -/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ -#define shiftrightSysram(z, x, c) \ - do \ - { \ - z[0] = (x[1] << (32 - (c))) | (x[0] >> (c)); \ - z[1] = (x[2] << (32 - (c))) | (x[1] >> (c)); \ - z[2] = (x[3] << (32 - (c))) | (x[2] >> (c)); \ - z[3] = (x[4] << (32 - (c))) | (x[3] >> (c)); \ - z[4] = (x[5] << (32 - (c))) | (x[4] >> (c)); \ - z[5] = (x[6] << (32 - (c))) | (x[5] >> (c)); \ - z[6] = (x[7] << (32 - (c))) | (x[6] >> (c)); \ - z[7] = (x[8] << (32 - (c))) | (x[7] >> (c)); \ - z[8] = (x[9] << (32 - (c))) | (x[8] >> (c)); \ - z[9] = (x[10] << (32 - (c))) | (x[9] >> (c)); \ - z[10] = (x[11] << (32 - (c))) | (x[10] >> (c)); \ - z[11] = (x[11] >> (c)); \ - } while (0) - -#else -#error "Define proper NIST curve" -#endif - -#define multiply_casper(c, a, b) MultprecCiosMul_ct(c, a, b, &CASPER_MEM[MOD_SCRATCH_START], Np) #define square_casper(c, a) multiply_casper(c, a, a) -#define sub_casper(c, a, b) CASPER_montsub(c, a, b, &CASPER_MEM[MOD_SCRATCH_START]) -#define add_casper(c, a, b) CASPER_montadd(c, a, b, &CASPER_MEM[MOD_SCRATCH_START]) -#define mul2_casper(c, a) add_casper(c, a, a) -#define half(c, a, b) CASPER_half(c, a, b) -#define copy(c, a) CASPER_MEMCPY(c, a, NUM_LIMBS * sizeof(uint32_t)) - +#define sub_casper(c, a, b) CASPER_montsub(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) +#define add_casper(c, a, b) CASPER_montadd(c, a, b, &CASPER_MEM[(N_wordlen + 4U)]) +#define mul2_casper(c, a) add_casper(c, a, a) +#define half(c, a, b) CASPER_half(c, a, b) /******************************************************************************* * Variables ******************************************************************************/ @@ -309,42 +280,54 @@ do \ /* it will be slower by a bit. */ /* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ /* #define N_bitlen 2048 */ -static size_t N_wordlen = 0; /* ! number of words (e.g. 4096/32 is 128 words) */ +static size_t N_wordlen = 0U; /* ! number of words (e.g. 4096/32 is 128 words) */ static uint32_t s_casperRamBase = CASPER_RAM_BASE_NS; -static unsigned *msg_ret = (unsigned *)CASPER_RAM_BASE_NS; +static uint32_t *msg_ret = (uint32_t *)CASPER_RAM_BASE_NS; -#if CASPER_ECC_P256 /* NISTp-256 = 2^256-2^224+2^192+2^96-1 */ -static uint32_t NISTp256[NUM_LIMBS] = {0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, - 0x00000000, 0x00000000, 0x00000001, 0xffffffff}; +static uint32_t NISTp256[256 / 32u] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0x00000000, + 0x00000000, 0x00000000, 0x00000001, 0xffffffffU}; /* The cardinality of the curve E(F_p) */ -static uint32_t NISTp256_q[NUM_LIMBS] = {0xfc632551, 0xf3b9cac2, 0xa7179e84, 0xbce6faad, - 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff}; +static uint32_t NISTp256_q[256 / 32u] = {0xfc632551U, 0xf3b9cac2U, 0xa7179e84U, 0xbce6faadU, + 0xffffffffU, 0xffffffffU, 0x00000000, 0xffffffffU}; /* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr256[NUM_LIMBS] = {0x00000001, 0x00000000, 0x00000000, 0xffffffff, - 0xffffffff, 0xffffffff, 0xfffffffe, 0x00000000}; +static uint32_t NISTr256[256 / 32u] = {0x00000001, 0x00000000, 0x00000000, 0xffffffffU, + 0xffffffffU, 0xffffffffU, 0xfffffffeU, 0x00000000}; -static uint32_t Np[2] = {1, 0}; -#endif /* CASPER_ECC_P256 */ +static uint32_t Np256[2] = {1, 0}; -#if CASPER_ECC_P384 /* NISTp-384 = 2^384 - 2^128 - 2^96 + 2^32 - 1 */ -static uint32_t NISTp384[NUM_LIMBS] = {0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xfffffffe, 0xffffffff, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}; +static uint32_t NISTp384[384 / 32u] = {0xffffffffU, 0x00000000, 0x00000000, 0xffffffffU, 0xfffffffeU, 0xffffffffU, + 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; /* The cardinality of the curve E(F_p) */ -static uint32_t NISTp384_q[NUM_LIMBS] = {0xccc52973, 0xecec196a, 0x48b0a77a, 0x581a0db2, 0xf4372ddf, 0xc7634d81, - 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}; +static uint32_t NISTp384_q[384 / 32u] = {0xccc52973U, 0xecec196aU, 0x48b0a77aU, 0x581a0db2U, 0xf4372ddfU, 0xc7634d81U, + 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU}; /* R = 2^256 mod p, the value "1" in Montgomery form. */ -static uint32_t NISTr384[NUM_LIMBS] = {0x00000001, 0xffffffff, 0xffffffff, 0x00000000, 0x1, 0, 0, 0, 0, 0, 0, 0}; +static uint32_t NISTr384[384 / 32u] = {0x00000001, 0xffffffffU, 0xffffffffU, 0x00000000, 0x1, 0, 0, 0, 0, 0, 0, 0}; // -p^-1 mod 2^64 = 0x100000001 -static uint32_t Np[2] = {1, 1}; -#endif /* CASPER_ECC_P384 */ +static uint32_t Np384[2] = {1, 1}; + +/* NISTp-521 = 2^521 - 1 */ +static uint32_t NISTp521[576 / 32U] = {0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, + 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, + 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; + +/* The cardinality of the curve E(F_p) */ +static uint32_t NISTp521_q[576 / 32U] = {0x91386409U, 0xbb6fb71eU, 0x899c47aeU, 0x3bb5c9b8U, 0xf709a5d0U, 0x7fcc0148U, + 0xbf2f966bU, 0x51868783U, 0xfffffffaU, 0xffffffffU, 0xffffffffU, 0xffffffffU, + 0xffffffffU, 0xffffffffU, 0xffffffffU, 0xffffffffU, 0x1ffU, 0}; + +/* R = 2^576 mod p, the value "1" in Montgomery form. */ +static uint32_t NISTr521[576 / 32U] = {0, 0x800000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +/* -p^-1 mod 2^64 = 1 */ +static uint32_t Np521[2] = {1, 0}; /******************************************************************************* * Prototypes @@ -356,12 +339,6 @@ static uint32_t Np[2] = {1, 1}; */ void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1); -/* Return 1 if (X1: Y1: Z1) is on the curve -* Y^2 = X^3 -3XZ^4 + bZ^6 -* and return 0 otherwise. -*/ -int Jac_oncurve(uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *b); - /* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) * where (X1: Y1: Z1) != (X2 : Y2 : Z2) * (X3 : Y3: Z3) may be the same as one of the inputs. @@ -379,12 +356,12 @@ void Jac_addition(uint32_t *X3, /* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) * where (X1: Y1: Z1) != (X2, Y2) * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson–Menezes–Vanstone, page 91. + * Source: 2004 Hankerson?Menezes?Vanstone, page 91. */ void Jac_add_affine( uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2); -/* Point doubling from: 2004 Hankerson–Menezes–Vanstone, page 91. +/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) * (X3 : Y3: Z3) may be the same as the input. */ @@ -401,11 +378,11 @@ void Jac_scalar_multiplication( uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q); /* Compute the double scalar multiplication -* (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) -* Using Shamir's trick and precomputing 16 points. -* This code is *not* constant time since this is used -* for verification only. -*/ + * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) + * Using Shamir's trick and precomputing 16 points. + * This code is *not* constant time since this is used + * for verification only. + */ void double_scalar_multiplication(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, @@ -416,7 +393,6 @@ void double_scalar_multiplication(uint32_t *X3, uint32_t *Y2, uint32_t *k2); -#if CASPER_ECC_P384 /* Compute inversion modulo NIST-p384 using Fermats little theorem. * Using c = a^(p-2) = a^(-1) mod p. * This computes the modular inversion if all arithmetic is "regular" @@ -424,15 +400,17 @@ void double_scalar_multiplication(uint32_t *X3, * if all arithmetic is Montgomery arithmetic. */ static void invert_mod_p384(uint32_t *c, uint32_t *a); -#endif /* CASPER_ECC_P384 */ -#if CASPER_ECC_P256 /* Modular inversion for NIST-P256 */ static void invert_mod_p256(uint32_t *c, uint32_t *a); -#endif /* CASPER_ECC_P256 */ + +/* Modular inversion for NIST-P521 */ +static void invert_mod_p521(uint32_t *c, uint32_t *a); // A and C do not need to be in Casper memory -static void toMontgomery(uint32_t *C, uint32_t *A); +static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A); +static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A); +static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A); static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod); @@ -440,12 +418,16 @@ static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) /* Compute c = a/2 mod p where b is scratch space. */ static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b); +void CASPER_MEMCPY(void *dst, const void *src, size_t siz); + +static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]); + static uint8_t int8abs(int8_t v); /* Constant time select c = a if m = 0 or -* c = b if m = 1 -* a, b, c are n words -*/ + * c = b if m = 1 + * a, b, c are n words + */ static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n); /* Dumb n-limb addition of c=a+b, return carry. */ @@ -462,11 +444,34 @@ static uint32_t sub_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n); /* Dumb n-limb subtraction of c=a-b, return borrow. */ static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n); +int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], + const unsigned exp_pubkey, + const unsigned pubkey[N_wordlen_max], + unsigned MsgRet[WORK_BUFF_MUL4]); + +int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max], + const unsigned exp_pubkey, + const unsigned pubkey[N_wordlen_max], + unsigned MsgRet[WORK_BUFF_MUL4]); + +void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]); + +void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret); +void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]); +void MultprecModulo(unsigned r_out[], const unsigned v[], int top); +void MultprecCiosMul( + unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np); +void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]); + static void MultprecCiosMul_ct( uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); -static void shiftright(uint32_t *z, uint32_t *x, int c); -static void shiftleft(uint32_t *z, uint32_t *x, int c); +static void MultprecCiosMul521_ct( + uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np); + +static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c); +static void shiftright(uint32_t *z, uint32_t *x, uint32_t c); +static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c); /******************************************************************************* * Code @@ -474,7 +479,7 @@ static void shiftleft(uint32_t *z, uint32_t *x, int c); __STATIC_FORCEINLINE uint32_t CA_MK_OFF(const void *addr) { - return ((uint32_t)addr - s_casperRamBase); + return ((uint32_t)(const uint32_t *)addr - s_casperRamBase); } #if 1 @@ -484,7 +489,7 @@ __STATIC_FORCEINLINE void Accel_done(void) do { status = CASPER->STATUS; - } while (0 == (status & CASPER_STATUS_DONE_MASK)); + } while (0U == (status & CASPER_STATUS_DONE_MASK)); } __STATIC_FORCEINLINE void Accel_SetABCD_Addr(uint32_t ab, uint32_t cd) @@ -517,7 +522,7 @@ __STATIC_FORCEINLINE void Accel_done(void) } #endif #define Accel_SetABCD_Addr(ab, cd) CASPER_Wr32b((uint32_t)ab | ((uint32_t)cd << 16), CASPER_CP_CTRL0); -#define Accel_crypto_mul(ctrl1) CASPER_Wr32b((uint32_t)ctrl1, CASPER_CP_CTRL1); +#define Accel_crypto_mul(ctrl1) CASPER_Wr32b((uint32_t)ctrl1, CASPER_CP_CTRL1); #endif __STATIC_FORCEINLINE uint32_t Accel_IterOpcodeResaddr(uint32_t iter, uint32_t opcode, uint32_t resAddr) @@ -527,11 +532,15 @@ __STATIC_FORCEINLINE uint32_t Accel_IterOpcodeResaddr(uint32_t iter, uint32_t op void CASPER_MEMCPY(void *dst, const void *src, size_t siz) { - bool bdst = ((((uint32_t)dst) | 0x10000000u) >= (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)dst) | 0x10000000u) < (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); + bool bdst = + ((((uint32_t)(uint32_t *)dst) | 0x10000000u) >= ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && + (((uint32_t)(uint32_t *)dst) | 0x10000000u) < + ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); - bool bsrc = ((((uint32_t)src) | 0x10000000u) >= (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && - (((uint32_t)src) | 0x10000000u) < (FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); + bool bsrc = ((((uint32_t)(const uint32_t *)src) | 0x10000000u) >= + ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) && + (((uint32_t)(const uint32_t *)src) | 0x10000000u) < + ((unsigned)FSL_FEATURE_CASPER_RAM_BASE_ADDRESS | 0x10000000u) + 8u * 1024u); if (bdst && bsrc) { @@ -547,7 +556,7 @@ void CASPER_MEMCPY(void *dst, const void *src, size_t siz) } else { - memcpy(dst, src, siz); + (void)memcpy(dst, src, siz); } } @@ -557,7 +566,7 @@ void CASPER_MEMCPY(void *dst, const void *src, size_t siz) */ static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n) { - uint32_t m1 = 0 - m, m2 = ~m1; + uint32_t m1 = 0U - (uint32_t)m, m2 = ~m1; int i; for (i = 0; i < n; i++) @@ -571,14 +580,14 @@ static void casper_select(uint32_t *c, uint32_t *a, uint32_t *b, int m, int n) /* Exp-pubkey only used to optimize for exp=3 */ void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned Nmod[]) { - int i; + uint32_t i; /* R is 2^n where n is 1 bit longer than Nmod, so 1 followed by 32 or 64 0 words for example */ /* Note that Nmod's upper most bit has to be 1 by definition, so one subtract is enough. We */ /* do not set the 1 since it is "borrowed" so no point */ PreZeroW(i, Rp); Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpSub64, CA_MK_OFF(Rp))); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(Rp))); Accel_done(); /* final borrow cannot happen since we know we started with a larger number */ } @@ -587,7 +596,7 @@ void MultprecMontCalcRp(unsigned Rp[], const unsigned exp_pubkey, const unsigned /* w_out is 2x the size of u and v */ void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]) { - int i, j; + uint32_t i, j; /* Knuth 4.3.1 - Algorithm M */ /* Compute w = u * v */ @@ -600,17 +609,19 @@ void MultprecMultiply(unsigned w_out[], const unsigned u[], const unsigned v[]) /* We do 1st pass NOSUM so we do not have to 0 output */ Accel_SetABCD_Addr(CA_MK_OFF(&v[0]), CA_MK_OFF(u)); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2 - 1, kCASPER_OpMul6464NoSum, CA_MK_OFF(&w_out[0]))); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464NoSum, CA_MK_OFF(&w_out[0]))); Accel_done(); /* Step 2. iterate over N words of v using j */ - for (j = 2; j < N_wordlen; j += 2) + for (j = 2U; j < N_wordlen; j += 2U) { /* Step 2b. Check for 0 on v word - skip if so since we 0ed already */ /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ - if (GET_WORD(&v[j]) || GET_WORD(&v[j + 1])) + if (0U != (GET_WORD(&v[j])) || 0U != (GET_WORD(&v[j + 1U]))) { Accel_SetABCD_Addr(CA_MK_OFF(&v[j]), CA_MK_OFF(u)); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2 - 1, kCASPER_OpMul6464Sum, CA_MK_OFF(&w_out[j]))); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpMul6464Sum, CA_MK_OFF(&w_out[j]))); Accel_done(); } } @@ -629,7 +640,8 @@ void MultprecModulo(unsigned r_out[], const unsigned v[], int top) unsigned vl16, vh16, v_Nm1; unsigned q_hat, r_hat, q_over; unsigned borrow, carry; - int i, j, tmp; + uint32_t i; + int j, tmp; /* Knuth 4.3.1 - Algorithm D */ /* Compute q = u / v giving remainder r = u mod v */ @@ -644,22 +656,22 @@ void MultprecModulo(unsigned r_out[], const unsigned v[], int top) /* For u, we have it in r_out. u[n] holds any overflow */ /* Since divide on CM3/4 is 32/32=32, we break into 16 bit halves, but */ /* multiply can be 32x32=64. */ - u_n = 0; + u_n = 0; u_shft = r_out; /* u (shifted) is in r_out */ - v_Nm1 = GET_WORD(&v[N_wordlen - 1]); /* MSw of public key */ - vl16 = v_Nm1 & 0xFFFF; /* lower 16 */ - vh16 = v_Nm1 >> 16; /* upper 16 */ + v_Nm1 = GET_WORD(&v[N_wordlen - 1U]); /* MSw of public key */ + vl16 = v_Nm1 & 0xFFFFU; /* lower 16 */ + vh16 = v_Nm1 >> 16; /* upper 16 */ /* Step 2. Iterate j from m-n down to 0 (M selected per Knuth as 2*N) */ for (j = top; j >= 0; j--) { /* Step 3. estimate q_hat as (U[j+n]*B + U[j+n-1]) / V[n-1] */ /* Note: using subset of Knuth algo since v is 1/2 len of u (which is */ /* from multiply or x^2 leading into this). */ - u32 = u_n; /* pickup u4u3u2, knowing u4 is 0 */ - u64 = ((uint64_t)u_n << 32) | GET_WORD(&u_shft[j + N_wordlen - 1]); - ul16 = u64 & 0xFFFF; /* lower 16 */ - uh16 = (u64 >> 16) & 0xFFFF; /* upper 16 */ + u32 = u_n; /* pickup u4u3u2, knowing u4 is 0 */ + u64 = ((uint64_t)u_n << 32) | GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 1U]); + ul16 = (unsigned int)(u64 & 0xFFFFU); /* lower 16 */ + uh16 = (unsigned int)((u64 >> 16) & 0xFFFFU); /* upper 16 */ /* we see if even possible (u large enough relative to v) */ if ((u32 - v_Nm1) <= u32) @@ -668,86 +680,96 @@ void MultprecModulo(unsigned r_out[], const unsigned v[], int top) q_over = 1; /* overflow from the sub */ } else + { q_over = 0; - + } /* q_hat = u32 / vh16 -- is the upper partial value */ /* estimate; if too much, then back down by 1 or 2 */ q_hat = u32 / vh16; r_hat = u32 - (q_hat * vh16); /* see if Q is more than 16 bits or remainder is too large (over div) */ - if ((q_hat == 0x10000) || ((q_hat * vl16) > ((r_hat << 16) | uh16))) + if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | uh16))) { /* too much - undo a division */ q_hat--; r_hat += vh16; /* check if still too much */ - if ((r_hat < 0x10000) && ((q_hat * vl16) > ((r_hat << 16) | uh16))) + if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | uh16))) + { q_hat--; /* yes, so undo a 2nd */ + } } /* compose u3u2uh16, then sub q_hat*v if OK */ u64 = (((uint64_t)u32 << 16) | uh16) - ((uint64_t)q_hat * v_Nm1); - if (u64 >> 48) + if (0U != (u64 >> 48)) { /* no, so add v back */ u32 = (unsigned)(u64 + v_Nm1); q_hat--; } else + { u32 = (unsigned)u64; - - tmp = q_hat << 16; /* quotient upper part */ + } + tmp = (int32_t)(uint32_t)(q_hat << 16); /* quotient upper part */ /* divide lower part: q = u2uh16ul16 / v. */ /* estimate and add back if over divdied */ q_hat = u32 / vh16; r_hat = u32 - (q_hat * vh16); - if ((q_hat == 0x10000) || ((q_hat * vl16) > ((r_hat << 16) | ul16))) + if ((q_hat == 0x10000U) || ((q_hat * vl16) > ((r_hat << 16) | ul16))) { /* too much - undo a division */ q_hat--; r_hat += vh16; /* check if still too much */ - if ((r_hat < 0x10000) && ((q_hat * vl16) > ((r_hat << 16) | ul16))) + if ((r_hat < 0x10000U) && ((q_hat * vl16) > ((r_hat << 16) | ul16))) + { q_hat--; /* yes, so undo a 2nd */ + } } /* compose u2uh16ul16, then sub q_hat*v if OK */ u64 = (((uint64_t)u32 << 16) | ul16) - ((uint64_t)q_hat * v_Nm1); - if (u64 >> 48) + if (0U != (u64 >> 48)) { /* no, so add v back */ r_hat = (unsigned)(u64 + v_Nm1); q_hat--; } else + { r_hat = (unsigned)u64; - - q_hat |= tmp; /* other half of the quotient */ - while (q_over || - ((uint64_t)q_hat * GET_WORD(&v[N_wordlen - 2])) > - ((1LL << 32) * r_hat) + (uint64_t)GET_WORD(&u_shft[j + N_wordlen - 2])) + } + q_hat |= (unsigned)tmp; /* other half of the quotient */ + while ((q_over != 0U) || ((uint64_t)q_hat * GET_WORD(&v[N_wordlen - 2U])) > + ((1ULL << 32) * r_hat) + (uint64_t)GET_WORD(&u_shft[(uint32_t)j + N_wordlen - 2U])) { /* if Qhat>b, then reduce to b-1, then adjust up Rhat */ q_hat--; r_hat += v_Nm1; if (r_hat < v_Nm1) + { break; /* no overflow */ /* else repeat since Rhat >= b */ + } } /* Step 4. Multiply and subtract. We know the amount, */ /* so we do the schoolboy math. Have to do on */ /* the large value. */ - if (q_hat) + if (q_hat != 0U) { borrow = 0; for (i = 0; i < N_wordlen; i++) { - u64 = (uint64_t)q_hat * GET_WORD(&v[i]) + borrow; + u64 = (uint64_t)q_hat * GET_WORD(&v[i]) + borrow; borrow = (unsigned)(u64 >> 32); - if (GET_WORD(&u_shft[i + j]) < (unsigned)u64) + if (GET_WORD(&u_shft[i + (unsigned)j]) < (unsigned)u64) + { borrow++; /* carry the overflow */ - SET_WORD(&u_shft[i + j], GET_WORD(&u_shft[i + j]) - (unsigned)u64); + } + SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) - (unsigned)u64); } u_n -= borrow; /* overflow from shift left does not fit otherwise */ } @@ -755,19 +777,22 @@ void MultprecModulo(unsigned r_out[], const unsigned v[], int top) /* Store 5. (update Q - we don't), and add back V to remainder if we over-subtracted */ /* That restores remainder to correct (we could only be off by 1) */ /* This should happen very rarely. */ - if (u_n) + if (u_n != 0U) { carry = 0; for (i = 0; i < N_wordlen; i++) { - SET_WORD(&u_shft[i + j], GET_WORD(&u_shft[i + j]) + carry); - carry = (GET_WORD(&u_shft[i + j]) < carry) ? 1 : 0; - SET_WORD(&u_shft[i + j], GET_WORD(&u_shft[i + j]) + GET_WORD(&v[i])); - if (GET_WORD(&u_shft[i + j]) < GET_WORD(&v[i])) + SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + carry); + carry = (GET_WORD(&u_shft[i + (unsigned)j]) < carry) ? 1U : 0U; + SET_WORD(&u_shft[i + (unsigned)j], GET_WORD(&u_shft[i + (unsigned)j]) + GET_WORD(&v[i])); + if (GET_WORD(&u_shft[i + (unsigned)j]) < GET_WORD(&v[i])) + { carry++; + } } } - u_n = GET_WORD(&u_shft[j + N_wordlen - 1]); /* hold upper part of u to catch overflow (to borrow from) */ + u_n = GET_WORD( + &u_shft[(uint32_t)j + N_wordlen - 1U]); /* hold upper part of u to catch overflow (to borrow from) */ } /* low N bits of r are valid as remainder */ } @@ -779,7 +804,7 @@ void MultprecModulo(unsigned r_out[], const unsigned v[], int top) void MultprecMontPrepareX(unsigned Xmont_out[], const unsigned x[], const unsigned Rp[], const unsigned Nmod[]) { MultprecMultiply(Xmont_out, x, Rp); - MultprecModulo(Xmont_out, Nmod, N_wordlen); + MultprecModulo(Xmont_out, Nmod, (int32_t)N_wordlen); } void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret) /* only pass the low order double word */ @@ -787,14 +812,14 @@ void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret) /* only pass the uint64_t nprime, Nmod_0; Nmod_0 = GET_WORD(&Nmod[0]) | ((uint64_t)GET_WORD(&Nmod[1]) << 32); -#define COMP_NPN_1 ((2 - Nmod_0 * nprime) * nprime) /* computes N`*N0=1 mod 2^P where P is the partial built up */ - nprime = (((2 + Nmod_0) & 4) << 1) + Nmod_0; /* mod 2^4 */ +#define COMP_NPN_1 ((2U - Nmod_0 * nprime) * nprime) /* computes N`*N0=1 mod 2^P where P is the partial built up */ + nprime = (((2U + Nmod_0) & 4U) << 1) + Nmod_0; /* mod 2^4 */ nprime = COMP_NPN_1; nprime = COMP_NPN_1; nprime = COMP_NPN_1; nprime = COMP_NPN_1; /* 8 multiplies of uint64_t */ - *((uint64_t *)np64_ret) = (~0LL - nprime) + 1LL; + *((uint64_t *)(uintptr_t)np64_ret) = (~0ULL - nprime) + 1ULL; } /* CIOS Multiply. This is the Coarse Integrated form where the values are */ @@ -804,25 +829,26 @@ void MultprecGenNp64(const unsigned *Nmod, unsigned *np64_ret) /* only pass the void MultprecCiosMul( unsigned w_out[], const unsigned a[], const unsigned b[], const unsigned Nmod[], const unsigned *Np) { - int i, j; - uint64_t *m64 = (uint64_t *)&msg_ret[kCASPER_RamOffset_M64]; + int j; + uint32_t i; + uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; uint64_t Np64; uint64_t carry; uint64_t *a64, *b64, *w64, *N64; - Np64 = *(uint64_t *)Np; + Np64 = *(uint64_t *)(uintptr_t)Np; - a64 = (uint64_t *)a; - b64 = (uint64_t *)b; - w64 = (uint64_t *)w_out; - N64 = (uint64_t *)Nmod; + a64 = (uint64_t *)(uintptr_t)a; + b64 = (uint64_t *)(uintptr_t)b; + w64 = (uint64_t *)(uintptr_t)w_out; + N64 = (uint64_t *)(uintptr_t)Nmod; - if (a) + if (a != NULL) { /* if !a, we are reducing only */ PreZeroW(i, w_out); } - SET_DWORD(&w64[N_dwordlen], 0); - SET_DWORD(&w64[N_dwordlen + 1], 0); + SET_DWORD(&w64[N_dwordlen], 0ULL); + SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); /* with accelerator */ /* loop i and then reduce after each j round */ @@ -830,18 +856,19 @@ void MultprecCiosMul( { /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a) + if (a != NULL) { /* if mul&reduce vs. reduce only */ carry = GET_DWORD(&w64[N_dwordlen]); Accel_SetABCD_Addr(CA_MK_OFF(&b64[i]), CA_MK_OFF(a64)); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); Accel_done(); /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ /* w64[N_dwordlen+1] = g_carry; */ - carry = (GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1], carry); + carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); + SET_DWORD(&w64[N_dwordlen + 1U], carry); } SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ @@ -850,34 +877,41 @@ void MultprecCiosMul( /* do this "reduce" since it is natural */ carry = GET_DWORD(&w64[N_dwordlen]); Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); Accel_done(); - carry = (GET_DWORD(&w64[N_dwordlen]) < carry); + carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1]) + carry)); + SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); } /* now check if need to subtract Nmod */ - if (GET_WORD(&w_out[N_wordlen])) + if (0U != (GET_WORD(&w_out[N_wordlen]))) + { j = 1; /* we have to subtract for sure if carry up */ + } else { j = 0; - for (i = N_wordlen - 1; i >= 0; i--) + for (i = N_wordlen - 1U; i > 0U; i--) + { if (GET_WORD(&w_out[i]) != GET_WORD(&Nmod[i])) { - j = GET_WORD(&w_out[i]) > GET_WORD(&Nmod[i]); /* if larger sub */ + j = (int32_t)(GET_WORD(&w_out[i]) > GET_WORD(&Nmod[i])); /* if larger sub */ break; /* we would remove the break if worrying about side channel */ } + } } - if (!j) + if (0 == j) + { return; /* Is smaller than Nmod, so done. */ + } Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpSub64, CA_MK_OFF(w_out))); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); Accel_done(); /* last borrow is OK since we know it could only be <2N and */ } @@ -907,9 +941,10 @@ int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max /* N*2..N*4+2 = temp working area for Mont mul */ /* 1. Copy sig into MsgRet so we have one working result buffer */ - CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], mont_signature, N_bytelen); - MultprecGenNp64(pubkey, np64); /* Generate N` from LSW of N (LSW being lowest 64b word) */ - bitpos = 31 - __CLZ(exp_pubkey); /* count of bits after the left most 1 */ + CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], + (const uint32_t *)(uintptr_t)mont_signature, N_bytelen); + MultprecGenNp64(pubkey, np64); /* Generate N` from LSW of N (LSW being lowest 64b word) */ + bitpos = (int8_t)(uint8_t)(31U - __CLZ(exp_pubkey)); /* count of bits after the left most 1 */ while (--bitpos >= 0) { /* This operates on: */ @@ -931,26 +966,29 @@ int RSA_MontSignatureToPlaintextFast(const unsigned mont_signature[N_wordlen_max /* */ /* Next we have the problem that CIOS mul needs a separate dest buffer. So, we bounce */ /* base between base and temp, and likewise for result. */ - MultprecCiosMul(&MsgRet[bidx ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], - &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], - &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], pubkey, np64); - if (exp_pubkey & (1 << bitpos)) /* where e is 1 */ + MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], + &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], + &MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], pubkey, np64); + if (0U != (exp_pubkey & (uint32_t)(uint8_t)(1U << (uint8_t)bitpos))) /* where e is 1 */ { /* result has result, so we need to work into other temp area */ - MultprecCiosMul(&MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], + MultprecCiosMul(&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], &MsgRet[kCASPER_RamOffset_Result], - &MsgRet[bidx ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], pubkey, np64); + &MsgRet[(bidx != 0) ? kCASPER_RamOffset_Base : kCASPER_RamOffset_TempBase], pubkey, np64); /* we have to copy back to result */ // CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], // &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], N_bytelen); } else - bidx = ~bidx; + { + bidx = (int32_t)(uint32_t) ~(unsigned)bidx; + } } - CASPER_MEMCPY_I2I(&MsgRet[kCASPER_RamOffset_Result], - &MsgRet[bidx ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], N_bytelen); + CASPER_MEMCPY_I2I((uint32_t *)(uintptr_t)&MsgRet[kCASPER_RamOffset_Result], + (uint32_t *)(uintptr_t)&MsgRet[(bidx != 0) ? kCASPER_RamOffset_TempBase : kCASPER_RamOffset_Base], + N_bytelen); /* final step is one more reduction to get back to normal form (ie. divide R out) */ MultprecCiosMul(&MsgRet[kCASPER_RamOffset_Result], NULL, NULL, pubkey, np64); @@ -998,15 +1036,16 @@ int RSA_SignatureToPlaintextFast(const unsigned signature[N_wordlen_max], void CASPER_ModExp( CASPER_Type *base, const uint8_t *signature, const uint8_t *pubN, size_t wordLen, uint32_t pubE, uint8_t *plaintext) { -#define PK_LOC &msg_ret[kCASPER_RamOffset_Modulus] -#define SIG_LOC &msg_ret[kCASPER_RamOffset_Modulus + N_wordlen_max] +#define PK_LOC &msg_ret[kCASPER_RamOffset_Modulus] +#define SIG_LOC &msg_ret[(unsigned)kCASPER_RamOffset_Modulus + N_wordlen_max] N_wordlen = wordLen; /* set global variable for key length - used by RSA_SignatureToPlaintextFast() */ - CASPER_MEMCPY_N2I(PK_LOC, pubN, N_bytelen); - CASPER_MEMCPY_N2I(SIG_LOC, signature, N_bytelen); - RSA_SignatureToPlaintextFast((const unsigned *)(SIG_LOC), pubE, (const unsigned *)(PK_LOC), msg_ret); + CASPER_MEMCPY_N2I(PK_LOC, (const uint32_t *)(uintptr_t)pubN, N_bytelen); + CASPER_MEMCPY_N2I(SIG_LOC, (const uint32_t *)(uintptr_t)signature, N_bytelen); + (void)RSA_SignatureToPlaintextFast((const unsigned *)(uintptr_t)(SIG_LOC), pubE, + (const unsigned *)(uintptr_t)(PK_LOC), (unsigned int *)(uintptr_t)msg_ret); - CASPER_MEMCPY_I2N(plaintext, msg_ret, N_bytelen); + CASPER_MEMCPY_I2N((uint32_t *)(uintptr_t)plaintext, msg_ret, N_bytelen); } /*! @@ -1019,12 +1058,20 @@ void CASPER_ModExp( void CASPER_Init(CASPER_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(CASPER_CLOCKS) CLOCK_EnableClock(kCLOCK_Casper); +#endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if defined(CASPER_RSTS) RESET_PeripheralReset(kCASPER_RST_SHIFT_RSTn); +#endif +#if defined(FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE) && (FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE > 0) + /* Enable hardware interleaving to RAMX0 and RAMX1 for CASPER */ + SYSCON->CASPER_CTRL = SYSCON_CASPER_CTRL_INTERLEAVE(1); +#endif /* FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE */ /* If Casper init is called with secure address, use secure addres also for accessing Casper RAM. */ - s_casperRamBase = CASPER_RAM_BASE_NS | ((uint32_t)base & 0x10000000u); - msg_ret = (unsigned *)s_casperRamBase; + s_casperRamBase = (unsigned)CASPER_RAM_BASE_NS | ((uint32_t)base & 0x10000000u); + msg_ret = (uint32_t *)s_casperRamBase; } /*! @@ -1036,9 +1083,13 @@ void CASPER_Init(CASPER_Type *base) */ void CASPER_Deinit(CASPER_Type *base) { +#if defined(CASPER_RSTS) RESET_SetPeripheralReset(kCASPER_RST_SHIFT_RSTn); +#endif #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(CASPER_CLOCKS) CLOCK_DisableClock(kCLOCK_Casper); +#endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } @@ -1046,99 +1097,128 @@ void CASPER_Deinit(CASPER_Type *base) /* Set the prime modulus mod in Casper memory. */ -void CASPER_ecc_init(void) +void CASPER_ecc_init(casper_algo_t curve) { -#if CASPER_ECC_P256 - N_wordlen = 256 / 32; - uint32_t *mod = NISTp256; -#elif CASPER_ECC_P384 - N_wordlen = 384 / 32; - uint32_t *mod = NISTp384; -#endif - CASPER_MEMCPY(&CASPER_MEM[MOD_SCRATCH_START], mod, NUM_LIMBS * sizeof(uint32_t)); - uint8_t a[(CASPER_NUM_LIMBS - NUM_LIMBS) * sizeof(uint32_t)] = {0}; - CASPER_MEMCPY(&CASPER_MEM[MOD_SCRATCH_START + NUM_LIMBS], a, (CASPER_NUM_LIMBS - NUM_LIMBS) * sizeof(uint32_t)); + uint32_t *mod; + + if (curve == kCASPER_ECC_P256) + { + N_wordlen = 256U / 32U; + mod = NISTp256; + } + + if (curve == kCASPER_ECC_P384) + { + N_wordlen = 384U / 32U; + mod = NISTp384; + } + + if (curve == kCASPER_ECC_P521) + { + N_wordlen = 576U / 32U; + mod = NISTp521; + } + + CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U)], mod, N_wordlen * sizeof(uint32_t)); + uint8_t a[((CASPER_MAX_ECC_SIZE_WORDLEN + 4U) - CASPER_MAX_ECC_SIZE_WORDLEN) * sizeof(uint32_t)] = {0}; + CASPER_MEMCPY(&CASPER_MEM[(N_wordlen + 4U) + N_wordlen], a, ((N_wordlen + 4U) - N_wordlen) * sizeof(uint32_t)); } void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2) { - uint32_t a[NUM_LIMBS]; - uint32_t b[NUM_LIMBS]; - int c = 0; - CASPER_MEMCPY(a, op1, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(b, op2, NUM_LIMBS * sizeof(uint32_t)); + uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; + uint32_t b[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; + uint32_t c = 0; + CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(b, op2, N_wordlen * sizeof(uint32_t)); do { - int _i; - c = a[0] ^ b[0]; - for (_i = 1; _i < NUM_LIMBS; _i++) + uint32_t _i; + c = (a[0] ^ b[0]); + for (_i = 1; _i < N_wordlen; _i++) { c |= (a[_i] ^ b[_i]); } - } while (0); + } while (false); - *res = c; + *res = (int32_t)c; } void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1) { - uint32_t a[NUM_LIMBS]; - int c = 0; - CASPER_MEMCPY(a, op1, NUM_LIMBS * sizeof(uint32_t)); + uint32_t a[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; + uint32_t c = 0; + CASPER_MEMCPY(a, op1, N_wordlen * sizeof(uint32_t)); do { - int _i; + uint32_t _i; c = a[0]; - for (_i = 1; _i < NUM_LIMBS; _i++) + for (_i = 1; _i < N_wordlen; _i++) { c |= a[_i]; } - } while (0); + } while (false); - *res = c; + *res = (int32_t)c; } -#if CASPER_ECC_P256 void CASPER_ECC_SECP256R1_Mul( CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]) { uint32_t X1[8] = {0}; uint32_t Y1[8] = {0}; - toMontgomery(X1, X); - toMontgomery(Y1, Y); + toMontgomery_ECC_P256(X1, X); + toMontgomery_ECC_P256(Y1, Y); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - Jac_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar, NISTp256, NISTp256_q); + Jac_scalar_multiplication( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + scalar, NISTp256, NISTp256_q); - Jac_toAffine(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS]); + Jac_toAffine( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); /* Montgomery to Normal */ /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ - uint32_t one[CASPER_NUM_LIMBS] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, CASPER_NUM_LIMBS * sizeof(uint32_t)); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; + one[0] = 0x1u; + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); /* copy out to result */ - CASPER_MEMCPY(resX, &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(resY, &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY( + resX, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + resY, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); } void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, @@ -1151,93 +1231,140 @@ void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base, uint32_t Y2[8], uint32_t scalar2[8]) { - uint32_t zeroes[CASPER_NUM_LIMBS] = {0}; + uint32_t zeroes[(kCASPER_ECC_P256_wordlen + 4U)] = {0}; - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], X2, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], Y2, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + X2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + Y2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS]); + toMontgomery_ECC_P256( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + toMontgomery_ECC_P256( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + toMontgomery_ECC_P256( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + toMontgomery_ECC_P256( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], zeroes, CASPER_NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], zeroes, CASPER_NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], zeroes, CASPER_NUM_LIMBS * sizeof(uint32_t)); - double_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar1, - &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], scalar2); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); + double_scalar_multiplication( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + scalar1, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + scalar2); - Jac_toAffine(&CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS]); + Jac_toAffine( + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - uint32_t one[CASPER_NUM_LIMBS] = {0x0}; - one[0] = 0x1u; - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, CASPER_NUM_LIMBS * sizeof(uint32_t)); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + uint32_t one[(kCASPER_ECC_P256_wordlen + 4U)] = {0x0}; + one[0] = 0x1u; + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + one, ((uint32_t)kCASPER_ECC_P256_wordlen + 4U) * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P256_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]); - CASPER_MEMCPY(resX, (&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(resY, (&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(resX, + (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(resY, + (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); } -#endif /* CASPER_ECC_P256 */ -#if CASPER_ECC_P384 void CASPER_ECC_SECP384R1_Mul( CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]) { uint32_t X1[12] = {0}; uint32_t Y1[12] = {0}; - toMontgomery(X1, X); - toMontgomery(Y1, Y); + toMontgomery_ECC_P384(X1, X); + toMontgomery_ECC_P384(Y1, Y); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - Jac_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar, NISTp384, NISTp384_q); + Jac_scalar_multiplication( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + scalar, NISTp384, NISTp384_q); - Jac_toAffine(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS]); + Jac_toAffine( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); /* Montgomery to Normal */ /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, NUM_LIMBS * sizeof(uint32_t)); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); /* copy out to result */ - CASPER_MEMCPY(resX, &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(resY, &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY( + resX, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + resY, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); } void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, @@ -1250,48 +1377,241 @@ void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, uint32_t Y2[12], uint32_t scalar2[12]) { - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], X1, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], Y1, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], X2, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], Y2, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + X2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + Y2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]); - toMontgomery(&CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS]); + toMontgomery_ECC_P384( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + toMontgomery_ECC_P384( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + toMontgomery_ECC_P384( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + toMontgomery_ECC_P384( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - double_scalar_multiplication(&CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], scalar1, - &CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS], scalar2); + double_scalar_multiplication( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + scalar1, + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + scalar2); - Jac_toAffine(&CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS]); + Jac_toAffine( + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); uint32_t one[12] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; - CASPER_MEMCPY(&CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], one, NUM_LIMBS * sizeof(uint32_t)); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); - multiply_casper(&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS], - &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS], - &CASPER_MEM[INOUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]); + CASPER_MEMCPY( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + one, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)], + &CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]); - CASPER_MEMCPY(resX, (&CASPER_MEM[INOUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(resY, (&CASPER_MEM[INOUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]), NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(resX, + (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(resY, + (&CASPER_MEM[(2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); +} + +void CASPER_ECC_SECP521R1_Mul( + CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]) +{ + uint32_t X1[18] = {0}; + uint32_t Y1[18] = {0}; + toMontgomery_ECC_P521(X1, X); + toMontgomery_ECC_P521(Y1, Y); + + CASPER_MEMCPY( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + + Jac_scalar_multiplication( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + scalar, NISTp521, NISTp521_q); + + Jac_toAffine( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 7U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 8U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + + /* Montgomery to Normal */ + /* X_normal = 1 * X_montgomery; Y_normal = 1 * Y_montgomery */ + uint32_t one[18] = {0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; + CASPER_MEMCPY( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + one, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + + /* copy out to result */ + CASPER_MEMCPY( + resX, + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + resY, + &CASPER_MEM[(((uint32_t)kCASPER_ECC_P521_wordlen + 4U) + (1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U))) + + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); +} + +void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, + uint32_t resX[18], + uint32_t resY[18], + uint32_t X1[18], + uint32_t Y1[18], + uint32_t scalar1[18], + uint32_t X2[18], + uint32_t Y2[18], + uint32_t scalar2[18]) +{ + uint32_t zeroes[(kCASPER_ECC_P521_wordlen + 4U)] = {0}; + + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + X1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + Y1, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + X2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + Y2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + + toMontgomery_ECC_P521( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + toMontgomery_ECC_P521( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + toMontgomery_ECC_P521( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + toMontgomery_ECC_P521( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + zeroes, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); + double_scalar_multiplication( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + scalar1, + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + scalar2); + + Jac_toAffine( + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 6U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + + uint32_t one[(kCASPER_ECC_P521_wordlen + 4U)] = {0x0}; + one[0] = 0x1u; + CASPER_MEMCPY( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + one, ((uint32_t)kCASPER_ECC_P521_wordlen + 4U) * sizeof(uint32_t)); + multiply_casper( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + multiply_casper( + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + + 2U * ((uint32_t)(uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)], + &CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]); + + CASPER_MEMCPY( + resX, + (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY( + resY, + (&CASPER_MEM[(2U * (uint32_t)kCASPER_ECC_P521_wordlen + 8U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]), + (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); } -#endif /* CASPER_ECC_P384 */ // CIOS Multiply. This is the Coarse Integrated form where the values are // multiplied and reduced for each step of "i". This uses less memory and @@ -1300,45 +1620,46 @@ void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, static void MultprecCiosMul_ct( uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) { - int i; - uint64_t *m64 = (uint64_t *)&msg_ret[kCASPER_RamOffset_M64]; + uint32_t j; + uint64_t *m64 = (uint64_t *)(uintptr_t)&msg_ret[kCASPER_RamOffset_M64]; uint64_t Np64; uint64_t carry; uint64_t *a64, *b64, *w64, *N64; uint32_t *T1 = &CASPER_MEM[0], borrow; - Np64 = *(uint64_t *)Np; + Np64 = *(uint64_t *)(uintptr_t)Np; - a64 = (uint64_t *)a; - b64 = (uint64_t *)b; - w64 = (uint64_t *)w_out; - N64 = (uint64_t *)Nmod; + a64 = (uint64_t *)(uintptr_t)a; + b64 = (uint64_t *)(uintptr_t)b; + w64 = (uint64_t *)(uintptr_t)w_out; + N64 = (uint64_t *)(uintptr_t)Nmod; - if (a) + if (a != NULL) { /* if !a, we are reducing only */ - PreZeroW(i, w_out); + PreZeroW(j, w_out); } - SET_DWORD(&w64[N_dwordlen], 0); - SET_DWORD(&w64[N_dwordlen + 1], 0); + SET_DWORD(&w64[N_dwordlen], 0ULL); + SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); /* with accelerator */ - /* loop i and then reduce after each j round */ - for (i = 0; i < N_dwordlen; i++) + /* loop j and then reduce after each j round */ + for (j = 0; j < N_dwordlen; j++) { - /* Step 3. Iterate over N words of u using i - perform Multiply-accumulate */ + /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ /* push-pull: we do a*b and then separately m*n (reduce) */ - if (a) + if (a != NULL) { /* if mul&reduce vs. reduce only */ carry = GET_DWORD(&w64[N_dwordlen]); - Accel_SetABCD_Addr(CA_MK_OFF(&b64[i]), CA_MK_OFF(a64)); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); + Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); Accel_done(); /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ /* w64[N_dwordlen+1] = g_carry; */ - carry = (GET_DWORD(&w64[N_dwordlen]) < carry); - SET_DWORD(&w64[N_dwordlen + 1], carry); + carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); + SET_DWORD(&w64[N_dwordlen + 1U], carry); } SET_DWORD(&m64[0], GET_DWORD(&w64[0]) * Np64); /* prime for 1st; modulo a double-word */ @@ -1347,123 +1668,123 @@ static void MultprecCiosMul_ct( /* do this "reduce" since it is natural */ carry = GET_DWORD(&w64[N_dwordlen]); Accel_SetABCD_Addr(CA_MK_OFF(m64), CA_MK_OFF(&N64[0])); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(&w64[0]))); Accel_done(); - carry = (GET_DWORD(&w64[N_dwordlen]) < carry); + carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); Accel_SetABCD_Addr(CA_MK_OFF(&w64[1]), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1, kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpCopy, CA_MK_OFF(&w64[0]))); Accel_done(); - SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1]) + carry)); + SET_DWORD(&w64[N_dwordlen], (GET_DWORD(&w64[N_dwordlen + 1U]) + carry)); } /* now check if need to subtract Nmod */ - CASPER_MEMCPY_I2I(T1, w_out, (NUM_LIMBS + 1) * sizeof(uint32_t)); + CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); /* Compute w = w - N */ Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, kCASPER_OpSub64, CA_MK_OFF(w_out))); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); Accel_done(); // if w_out > T1 then there was a borrow - borrow = (GET_WORD(&((uint32_t *)w_out)[NUM_LIMBS]) > GET_WORD(&T1[NUM_LIMBS])); + borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); - SET_WORD(&w_out[NUM_LIMBS + 1], 0); - SET_WORD(&w_out[NUM_LIMBS], 0); - casper_select(w_out, w_out, T1, borrow, NUM_LIMBS); + SET_WORD(&w_out[N_wordlen + 1U], 0); + SET_WORD(&w_out[N_wordlen], 0); + casper_select(w_out, w_out, T1, (int32_t)borrow, (int16_t)(uint16_t)N_wordlen); } /* Compute C = A - B % mod -* Assumes all operand have two extra limbs to store carry. -*/ -void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) + * Assumes all operand have two extra limbs to store carry. + */ +static void CASPER_montsub(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) { uint64_t *b64, *c64, *m64, *tmp; int borrow; - b64 = (uint64_t *)B; - c64 = (uint64_t *)C; - m64 = (uint64_t *)mod; + b64 = (uint64_t *)(uintptr_t)B; + c64 = (uint64_t *)(uintptr_t)C; + m64 = (uint64_t *)(uintptr_t)mod; - tmp = (uint64_t *)&CASPER_MEM[0]; + tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; - CASPER_MEMCPY(tmp, A, NUM_LIMBS * sizeof(uint32_t)); - // uint32_t temp32 = GET_WORD(&tmp[NUM_LIMBS - 1]); + CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); /* Compute tmp = A - B. */ Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2 - 1, kCASPER_OpSub64, CA_MK_OFF(tmp))); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(tmp))); Accel_done(); - // borrow = (GET_WORD(&((uint32_t*)tmp)[NUM_LIMBS - 1]) > temp32); - borrow = ((GET_WORD(&((uint32_t *)tmp)[NUM_LIMBS - 1])) > GET_WORD(&A[NUM_LIMBS - 1])); - CASPER_MEMCPY(c64, tmp, NUM_LIMBS * sizeof(uint32_t)); + borrow = (int32_t)((GET_WORD(&((uint32_t *)(uintptr_t)tmp)[N_wordlen - 1U])) > GET_WORD(&A[N_wordlen - 1U])); + CASPER_MEMCPY(c64, tmp, N_wordlen * sizeof(uint32_t)); /* Compute C = Mod + tmp */ Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2 - 1, kCASPER_OpAdd64, CA_MK_OFF(c64))); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U - 1U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(c64))); Accel_done(); - casper_select(C, (uint32_t *)tmp, C, borrow, NUM_LIMBS); + casper_select(C, (uint32_t *)(uintptr_t)tmp, C, borrow, (int16_t)(uint16_t)N_wordlen); } /* Compute C = A + B % mod -* Assumes all operand have two extra limbs to store carry. -*/ -void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) + * Assumes all operand have two extra limbs to store carry. + */ +static void CASPER_montadd(uint32_t *C, uint32_t *A, uint32_t *B, uint32_t *mod) { uint64_t *b64, *c64, *m64, *tmp; int borrow; - b64 = (uint64_t *)B; - c64 = (uint64_t *)C; - m64 = (uint64_t *)mod; + b64 = (uint64_t *)(uintptr_t)B; + c64 = (uint64_t *)(uintptr_t)C; + m64 = (uint64_t *)(uintptr_t)mod; - tmp = (uint64_t *)&CASPER_MEM[0]; + tmp = (uint64_t *)(uintptr_t)&CASPER_MEM[0]; - CASPER_MEMCPY(tmp, A, NUM_LIMBS * sizeof(uint32_t)); - SET_DWORD(&tmp[NUM_LIMBS / 2], 0); - SET_DWORD(&b64[NUM_LIMBS / 2], 0); - SET_DWORD(&m64[NUM_LIMBS / 2], 0); + CASPER_MEMCPY(tmp, A, N_wordlen * sizeof(uint32_t)); + SET_DWORD(&tmp[N_wordlen / 2U], 0ULL); + SET_DWORD(&b64[N_wordlen / 2U], 0ULL); + SET_DWORD(&m64[N_wordlen / 2U], 0ULL); /* Compute tmp = A + B using one additonal double-length limb. */ Accel_SetABCD_Addr(CA_MK_OFF(b64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2, kCASPER_OpAdd64, CA_MK_OFF(tmp))); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(tmp))); Accel_done(); - CASPER_MEMCPY(c64, tmp, (NUM_LIMBS + 2) * sizeof(uint32_t)); + CASPER_MEMCPY(c64, tmp, (N_wordlen + 2U) * sizeof(uint32_t)); /* Compute C = Mod - tmp */ Accel_SetABCD_Addr(CA_MK_OFF(m64), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2, kCASPER_OpSub64, CA_MK_OFF(c64))); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(c64))); Accel_done(); // borrow = g_carry; - borrow = (GET_WORD(&C[NUM_LIMBS]) > GET_WORD(&(((uint32_t *)tmp)[NUM_LIMBS]))); - casper_select(C, C, (uint32_t *)tmp, borrow, NUM_LIMBS); + borrow = (int32_t)(GET_WORD(&C[N_wordlen]) > GET_WORD(&(((uint32_t *)(uintptr_t)tmp)[N_wordlen]))); + casper_select(C, C, (uint32_t *)(uintptr_t)tmp, borrow, (int16_t)(uint16_t)N_wordlen); } /* Compute c = a/2 mod p where b is scratch space. */ -void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b) +static void CASPER_half(uint32_t *c, uint32_t *a, uint32_t *b) { - shiftright(b, a, 1); /* Compute a/2 and (a+p)/2 */ + shiftright(b, a, 1U); /* Compute a/2 and (a+p)/2 */ /* Compute tmp = a + p using one additonal double-length limb. */ - CASPER_MEMCPY(c, a, NUM_LIMBS * sizeof(uint32_t)); - SET_WORD(&c[NUM_LIMBS], 0); - SET_WORD(&c[NUM_LIMBS + 1], 0); + CASPER_MEMCPY(c, a, N_wordlen * sizeof(uint32_t)); + SET_WORD(&c[N_wordlen], 0); + SET_WORD(&c[N_wordlen + 1U], 0U); - Accel_SetABCD_Addr(CA_MK_OFF(((uint64_t *)&CASPER_MEM[MOD_SCRATCH_START])), 0); - Accel_crypto_mul(Accel_IterOpcodeResaddr(NUM_LIMBS / 2, kCASPER_OpAdd64, CA_MK_OFF(((uint64_t *)c)))); + Accel_SetABCD_Addr(CA_MK_OFF(((uint64_t *)(uintptr_t)&CASPER_MEM[(N_wordlen + 4U)])), 0); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_wordlen / 2U, (uint32_t)kCASPER_OpAdd64, CA_MK_OFF(((uint64_t *)(uintptr_t)c)))); Accel_done(); - shiftright(c, c, 1); - SET_WORD(&c[NUM_LIMBS - 1], GET_WORD(&c[NUM_LIMBS - 1]) | (GET_WORD(&c[NUM_LIMBS]) << 31)); - SET_WORD(&c[NUM_LIMBS], 0); - casper_select(c, b, c, (GET_WORD(&a[0]) & 1), NUM_LIMBS); + shiftright(c, c, 1U); + SET_WORD(&c[N_wordlen - 1U], GET_WORD(&c[N_wordlen - 1U]) | (GET_WORD(&c[N_wordlen]) << 31)); + SET_WORD(&c[N_wordlen], 0U); + casper_select(c, b, c, (int32_t)(uint32_t)(GET_WORD(&a[0]) & 1U), (int16_t)(uint16_t)(N_wordlen)); } static uint32_t casper_get_word(uint32_t *addr) @@ -1471,81 +1792,137 @@ static uint32_t casper_get_word(uint32_t *addr) return GET_WORD(addr); } -#if CASPER_ECC_P256 -/* Shift right by 1 <= c <= 31. */ -static void shiftright(uint32_t *z, uint32_t *x, int c) +/* Shift right by 1 <= c <= 31. z[] and x[] in system RAM, no interleaving macros used. */ +static void shiftrightSysram(uint32_t *z, uint32_t *x, uint32_t c) { - do - { - SET_WORD((&z[0]), (GET_WORD(&x[1]) << (32 - (c))) | (GET_WORD(&x[0]) >> (c))); - SET_WORD((&z[1]), (GET_WORD(&x[2]) << (32 - (c))) | (GET_WORD(&x[1]) >> (c))); - SET_WORD((&z[2]), (GET_WORD(&x[3]) << (32 - (c))) | (GET_WORD(&x[2]) >> (c))); - SET_WORD((&z[3]), (GET_WORD(&x[4]) << (32 - (c))) | (GET_WORD(&x[3]) >> (c))); - SET_WORD((&z[4]), (GET_WORD(&x[5]) << (32 - (c))) | (GET_WORD(&x[4]) >> (c))); - SET_WORD((&z[5]), (GET_WORD(&x[6]) << (32 - (c))) | (GET_WORD(&x[5]) >> (c))); - SET_WORD((&z[6]), (GET_WORD(&x[7]) << (32 - (c))) | (GET_WORD(&x[6]) >> (c))); - SET_WORD((&z[7]), (GET_WORD(&x[7]) >> (c))); + z[0] = (x[1] << (32U - (c))) | (x[0] >> (c)); + z[1] = (x[2] << (32U - (c))) | (x[1] >> (c)); + z[2] = (x[3] << (32U - (c))) | (x[2] >> (c)); + z[3] = (x[4] << (32U - (c))) | (x[3] >> (c)); + z[4] = (x[5] << (32U - (c))) | (x[4] >> (c)); + z[5] = (x[6] << (32U - (c))) | (x[5] >> (c)); + z[6] = (x[7] << (32U - (c))) | (x[6] >> (c)); - } while (0); -} + if (N_wordlen == 18U) + { + z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); + z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); + z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); + z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); + z[11] = (x[12] << (32U - (c))) | (x[11] >> (c)); + z[12] = (x[13] << (32U - (c))) | (x[12] >> (c)); + z[13] = (x[14] << (32U - (c))) | (x[13] >> (c)); + z[14] = (x[15] << (32U - (c))) | (x[14] >> (c)); + z[15] = (x[16] << (32U - (c))) | (x[15] >> (c)); + z[16] = (x[17] << (32U - (c))) | (x[16] >> (c)); + z[17] = (x[17] >> (c)); + } -/* Shift left by 1 <= c <= 31. */ -static void shiftleft(uint32_t *z, uint32_t *x, int c) -{ - do + if (N_wordlen == 12U) { - SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32 - (c))); - SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32 - (c))); - SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32 - (c))); - SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32 - (c))); - SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32 - (c))); - SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32 - (c))); - SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32 - (c))); - SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); - } while (0); + z[7] = (x[8] << (32U - (c))) | (x[7] >> (c)); + z[8] = (x[9] << (32U - (c))) | (x[8] >> (c)); + z[9] = (x[10] << (32U - (c))) | (x[9] >> (c)); + z[10] = (x[11] << (32U - (c))) | (x[10] >> (c)); + z[11] = (x[11] >> (c)); + } + if (N_wordlen == 8U) + { + z[7] = (x[7] >> (c)); + } } -#else /* Shift right by 1 <= c <= 31. */ -static void shiftright(uint32_t *z, uint32_t *x, int c) +static void shiftright(uint32_t *z, uint32_t *x, uint32_t c) { - do + SET_WORD(&z[0], (GET_WORD(&x[1]) << (32U - (c))) | (GET_WORD(&x[0]) >> (c))); + SET_WORD(&z[1], (GET_WORD(&x[2]) << (32U - (c))) | (GET_WORD(&x[1]) >> (c))); + SET_WORD(&z[2], (GET_WORD(&x[3]) << (32U - (c))) | (GET_WORD(&x[2]) >> (c))); + SET_WORD(&z[3], (GET_WORD(&x[4]) << (32U - (c))) | (GET_WORD(&x[3]) >> (c))); + SET_WORD(&z[4], (GET_WORD(&x[5]) << (32U - (c))) | (GET_WORD(&x[4]) >> (c))); + SET_WORD(&z[5], (GET_WORD(&x[6]) << (32U - (c))) | (GET_WORD(&x[5]) >> (c))); + SET_WORD(&z[6], (GET_WORD(&x[7]) << (32U - (c))) | (GET_WORD(&x[6]) >> (c))); + + if (N_wordlen == 18U) { - SET_WORD(&z[0], (GET_WORD(&x[1]) << (32 - (c))) | (GET_WORD(&x[0]) >> (c))); - SET_WORD(&z[1], (GET_WORD(&x[2]) << (32 - (c))) | (GET_WORD(&x[1]) >> (c))); - SET_WORD(&z[2], (GET_WORD(&x[3]) << (32 - (c))) | (GET_WORD(&x[2]) >> (c))); - SET_WORD(&z[3], (GET_WORD(&x[4]) << (32 - (c))) | (GET_WORD(&x[3]) >> (c))); - SET_WORD(&z[4], (GET_WORD(&x[5]) << (32 - (c))) | (GET_WORD(&x[4]) >> (c))); - SET_WORD(&z[5], (GET_WORD(&x[6]) << (32 - (c))) | (GET_WORD(&x[5]) >> (c))); - SET_WORD(&z[6], (GET_WORD(&x[7]) << (32 - (c))) | (GET_WORD(&x[6]) >> (c))); - SET_WORD(&z[7], (GET_WORD(&x[8]) << (32 - (c))) | (GET_WORD(&x[7]) >> (c))); - SET_WORD(&z[8], (GET_WORD(&x[9]) << (32 - (c))) | (GET_WORD(&x[8]) >> (c))); - SET_WORD(&z[9], (GET_WORD(&x[10]) << (32 - (c))) | (GET_WORD(&x[9]) >> (c))); - SET_WORD(&z[10], (GET_WORD(&x[11]) << (32 - (c))) | (GET_WORD(&x[10]) >> (c))); + SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); + SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); + SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); + SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); + SET_WORD(&z[11], (GET_WORD(&x[12]) << (32U - (c))) | (GET_WORD(&x[11]) >> (c))); + SET_WORD(&z[12], (GET_WORD(&x[13]) << (32U - (c))) | (GET_WORD(&x[12]) >> (c))); + SET_WORD(&z[13], (GET_WORD(&x[14]) << (32U - (c))) | (GET_WORD(&x[13]) >> (c))); + SET_WORD(&z[14], (GET_WORD(&x[15]) << (32U - (c))) | (GET_WORD(&x[14]) >> (c))); + SET_WORD(&z[15], (GET_WORD(&x[16]) << (32U - (c))) | (GET_WORD(&x[15]) >> (c))); + SET_WORD(&z[16], (GET_WORD(&x[17]) << (32U - (c))) | (GET_WORD(&x[16]) >> (c))); + SET_WORD(&z[17], (GET_WORD(&x[17]) >> (c))); + } + if (N_wordlen == 12U) + { + SET_WORD(&z[7], (GET_WORD(&x[8]) << (32U - (c))) | (GET_WORD(&x[7]) >> (c))); + SET_WORD(&z[8], (GET_WORD(&x[9]) << (32U - (c))) | (GET_WORD(&x[8]) >> (c))); + SET_WORD(&z[9], (GET_WORD(&x[10]) << (32U - (c))) | (GET_WORD(&x[9]) >> (c))); + SET_WORD(&z[10], (GET_WORD(&x[11]) << (32U - (c))) | (GET_WORD(&x[10]) >> (c))); SET_WORD(&z[11], (GET_WORD(&x[11]) >> (c))); - } while (0); -} - -/* Shift left by 1 <= c <= 31. */ -static void shiftleft(uint32_t *z, uint32_t *x, int c) -{ - do + } + if (N_wordlen == 8U) { - SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32 - (c))); - SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32 - (c))); - SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32 - (c))); - SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32 - (c))); - SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32 - (c))); - SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32 - (c))); - SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32 - (c))); - SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32 - (c))); - SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32 - (c))); - SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32 - (c))); - SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32 - (c))); - SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); - } while (0); + SET_WORD((&z[7]), (GET_WORD(&x[7]) >> (c))); + } +} +/* Shift left by 1 <= c <= 31. */ +static void shiftleft(uint32_t *z, uint32_t *x, uint32_t c) +{ + if (N_wordlen == 18U) + { + SET_WORD(&z[17], (GET_WORD(&x[17]) << (c)) | GET_WORD(&z[16]) >> (32U - (c))); + SET_WORD(&z[16], (GET_WORD(&x[16]) << (c)) | GET_WORD(&z[15]) >> (32U - (c))); + SET_WORD(&z[15], (GET_WORD(&x[15]) << (c)) | GET_WORD(&z[14]) >> (32U - (c))); + SET_WORD(&z[14], (GET_WORD(&x[14]) << (c)) | GET_WORD(&z[13]) >> (32U - (c))); + SET_WORD(&z[13], (GET_WORD(&x[13]) << (c)) | GET_WORD(&z[12]) >> (32U - (c))); + SET_WORD(&z[12], (GET_WORD(&x[12]) << (c)) | GET_WORD(&z[11]) >> (32U - (c))); + SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); + SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); + SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); + SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); + } + if (N_wordlen == 12U) + { + SET_WORD(&z[11], (GET_WORD(&x[11]) << (c)) | GET_WORD(&z[10]) >> (32U - (c))); + SET_WORD(&z[10], (GET_WORD(&x[10]) << (c)) | GET_WORD(&z[9]) >> (32U - (c))); + SET_WORD(&z[9], (GET_WORD(&x[9]) << (c)) | GET_WORD(&z[8]) >> (32U - (c))); + SET_WORD(&z[8], (GET_WORD(&x[8]) << (c)) | GET_WORD(&z[7]) >> (32U - (c))); + } + SET_WORD(&z[7], (GET_WORD(&x[7]) << (c)) | GET_WORD(&z[6]) >> (32U - (c))); + SET_WORD(&z[6], (GET_WORD(&x[6]) << (c)) | GET_WORD(&z[5]) >> (32U - (c))); + SET_WORD(&z[5], (GET_WORD(&x[5]) << (c)) | GET_WORD(&z[4]) >> (32U - (c))); + SET_WORD(&z[4], (GET_WORD(&x[4]) << (c)) | GET_WORD(&z[3]) >> (32U - (c))); + SET_WORD(&z[3], (GET_WORD(&x[3]) << (c)) | GET_WORD(&z[2]) >> (32U - (c))); + SET_WORD(&z[2], (GET_WORD(&x[2]) << (c)) | GET_WORD(&z[1]) >> (32U - (c))); + SET_WORD(&z[1], (GET_WORD(&x[1]) << (c)) | GET_WORD(&z[0]) >> (32U - (c))); + SET_WORD(&z[0], (GET_WORD(&x[0]) << (c))); } -#endif +static void multiply_casper(uint32_t w_out[], const uint32_t a[], const uint32_t b[]) +{ + uint32_t *Np; + + if (N_wordlen == 8U) + { + Np = Np256; + MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); + } + if (N_wordlen == 12U) + { + Np = Np384; + MultprecCiosMul_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); + } + + if (N_wordlen == 18U) + { + Np = Np521; + MultprecCiosMul521_ct(w_out, a, b, &CASPER_MEM[(N_wordlen + 4U)], Np); + } +} /* Convert a projective point (X1 : Y1 : Z1) * to the affine point (X3, Y3) = (X1/Z1^2,Y1/Z1^3) * The memory of (X3, Y3) and (X1 : Y1 : Z1) should not overlap @@ -1554,61 +1931,33 @@ void Jac_toAffine(uint32_t *X3, uint32_t *Y3, uint32_t *X1, uint32_t *Y1, uint32 { uint32_t *T1, *T2; - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; + T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; + T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; square_casper(T1, Z1); // Z^2 multiply_casper(T2, T1, Z1); // Z^3 // Montgomery inverse - invert(T1, T2); // Z^-3 + if (N_wordlen == 8U) + { + invert_mod_p256(T1, T2); + } + + if (N_wordlen == 12U) + { + invert_mod_p384(T1, T2); + } + + if (N_wordlen == 18U) + { + invert_mod_p521(T1, T2); + } multiply_casper(Y3, Y1, T1); // Y3 = Y/Z^3 multiply_casper(T2, T1, Z1); // Z^-2 multiply_casper(X3, X1, T2); // X3 = X/Z^2 } -/* Return 1 if (X1: Y1: Z1) is on the curve - * Y^2 = X^3 -3XZ^4 + bZ^6 - * and return 0 otherwise. - */ -int Jac_oncurve(uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *b) -{ - uint32_t *T1, *T2, *T3, *T4, *T5, *T6; - int m; - - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - T4 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - T5 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; - T6 = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; - - square_casper(T1, Y1); // Y^2 - square_casper(T6, X1); // X^2 - multiply_casper(T2, T6, X1); // X^3 - - square_casper(T3, Z1); // Z^2 - square_casper(T4, T3); // Z^4 - multiply_casper(T6, T4, T3); // Z^6 - multiply_casper(T3, b, T6); // bZ^6 - - multiply_casper(T6, T4, X1); // XZ^4 - - mul2_casper(T5, T6); - add_casper(T4, T5, T6); // 3XZ^4 - - sub_casper(T2, T2, T4); // X^3-3XZ^4 - add_casper(T2, T2, T3); // X^3-3XZ^4+bZ^6 - - CASPER_ECC_equal(&m, T1, T2); - if (m != 0) - { - return 0; - } - return 1; -} - /* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2 : Y2 : Z2) * where (X1: Y1: Z1) != (X2 : Y2 : Z2) * (X3 : Y3: Z3) may be the same as one of the inputs. @@ -1626,30 +1975,30 @@ void Jac_addition(uint32_t *X3, uint32_t *Z1Z1, *Z2Z2, *U1, *S1, *J, *H, *V, *t0, *t1; int m1, m2; - Z1Z1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - Z2Z2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - U1 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - S1 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - J = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; - H = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; - V = &CASPER_MEM[ECC_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; - t0 = &CASPER_MEM[ECC_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; - t1 = &CASPER_MEM[ECC_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; + Z1Z1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; + Z2Z2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; + U1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; + S1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; + J = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; + H = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; + V = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; + t0 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; + t1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; CASPER_ECC_equal_to_zero(&m1, Z1); CASPER_ECC_equal_to_zero(&m2, Z2); if (m1 == 0) { - CASPER_MEMCPY(X3, X2, NUM_LIMBS * 4); - CASPER_MEMCPY(Y3, Y2, NUM_LIMBS * 4); - CASPER_MEMCPY(Z3, Z2, NUM_LIMBS * 4); + CASPER_MEMCPY(X3, X2, N_wordlen * 4U); + CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); + CASPER_MEMCPY(Z3, Z2, N_wordlen * 4U); return; } if (m2 == 0) { - CASPER_MEMCPY(X3, X1, NUM_LIMBS * 4); - CASPER_MEMCPY(Y3, Y1, NUM_LIMBS * 4); - CASPER_MEMCPY(Z3, Z1, NUM_LIMBS * 4); + CASPER_MEMCPY(X3, X1, N_wordlen * 4U); + CASPER_MEMCPY(Y3, Y1, N_wordlen * 4U); + CASPER_MEMCPY(Z3, Z1, N_wordlen * 4U); return; } @@ -1703,30 +2052,44 @@ void Jac_addition(uint32_t *X3, /* Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X2, Y2) * where (X1: Y1: Z1) != (X2, Y2) * (X3 : Y3: Z3) may not overlap with (X1: Y1: Z1). - * Source: 2004 Hankerson–Menezes–Vanstone, page 91. + * Source: 2004 Hankerson?Menezes?Vanstone, page 91. */ void Jac_add_affine( uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *Z1, uint32_t *X2, uint32_t *Y2) { uint32_t *T1, *T2, *T3, *T4, *T5; + uint32_t *ONE = NULL; int m1, m2; - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - T4 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - T5 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; + if (N_wordlen == 8U) + { + ONE = NISTr256; + } + if (N_wordlen == 12U) + { + ONE = NISTr384; + } + if (N_wordlen == 18U) + { + ONE = NISTr521; + } + + T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; + T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; + T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; + T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; + T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; CASPER_ECC_equal_to_zero(&m1, Z1); if (m1 == 0) { - CASPER_MEMCPY(X3, X2, NUM_LIMBS * 4); - CASPER_MEMCPY(Y3, Y2, NUM_LIMBS * 4); - CASPER_MEMCPY(Z3, ONE, NUM_LIMBS * 4); + CASPER_MEMCPY(X3, X2, N_wordlen * 4U); + CASPER_MEMCPY(Y3, Y2, N_wordlen * 4U); + CASPER_MEMCPY(Z3, ONE, N_wordlen * 4U); return; } - copy(T5, Z1); + CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); square_casper(T3, Z1); multiply_casper(T2, T3, Z1); multiply_casper(T4, T3, X2); @@ -1763,9 +2126,9 @@ void Jac_add_affine( sub_casper(Y3, T1, T2); } -extern uint32_t casper_get_word(uint32_t *addr); +static uint32_t casper_get_word(uint32_t *addr); -/* Point doubling from: 2004 Hankerson–Menezes–Vanstone, page 91. +/* Point doubling from: 2004 Hankerson?Menezes?Vanstone, page 91. * Compute (X3 : Y3: Z3) = (X1: Y1: Z1) + (X1 : Y1 : Z1) * (X3 : Y3: Z3) may be the same as the input. */ @@ -1773,11 +2136,11 @@ void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t { uint32_t *T1, *T2, *T3, *T4, *T5; - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - T4 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - T5 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; + T1 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 0U * (N_wordlen + 4U)]; + T2 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 1U * (N_wordlen + 4U)]; + T3 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 2U * (N_wordlen + 4U)]; + T4 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 3U * (N_wordlen + 4U)]; + T5 = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 4U * (N_wordlen + 4U)]; square_casper(T1, Z1); sub_casper(T3, X1, T1); @@ -1790,7 +2153,7 @@ void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t mul2_casper(Y3, Y1); - copy(T5, Z1); + CASPER_MEMCPY(T5, Z1, N_wordlen * sizeof(uint32_t)); multiply_casper(Z3, Y3, T5); square_casper(T5, Y3); @@ -1824,16 +2187,17 @@ void Jac_double(uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t static void recode(int8_t *c, uint32_t *k, int n, int w) { int i, t; - uint32_t K[NUM_LIMBS] = {0}; - memcpy(K, k, (size_t)ceil(n / 8.)); + uint32_t K[CASPER_MAX_ECC_SIZE_WORDLEN] = {0}; + (void)memcpy(K, k, (size_t)ceil(((float)n / 8.))); t = (n + (w - 2)) / (w - 1); for (i = 0; i < t; i++) { - c[i] = (K[0] & ((1 << w) - 1)) - (1 << (w - 1)); - shiftrightSysram(K, K, w - 1); - add_n_1(K, K, (uint32_t)c[i] >> 31, NUM_LIMBS); + c[i] = (int8_t)(uint8_t)((K[0] & ((uint32_t)(uint32_t)(1UL << (uint32_t)w) - 1UL)) - + (uint32_t)(uint32_t)(1UL << ((uint32_t)w - 1UL))); + shiftrightSysram(K, K, (unsigned)w - 1U); + (void)add_n_1(K, K, (uint32_t)c[i] >> 31, (int16_t)(uint16_t)N_wordlen); } - c[t] = K[0]; + c[t] = (int8_t)K[0]; } static uint32_t sub_n(uint32_t *c, uint32_t *a, uint32_t *b, int n) @@ -1880,16 +2244,14 @@ static uint32_t add_n_1(uint32_t *c, uint32_t *a, uint32_t b, int n) add_cout(carry, c[0], a[0], b); for (i = 1; i < n; i++) { - add_cout_cin(carry, c[i], a[i], 0, carry); + add_cout_cin(carry, c[i], a[i], 0U, carry); } return carry; } -// http://graphics.stanford.edu/~seander/bithacks.html#IntegerAbs static uint8_t int8abs(int8_t v) { - int8_t const mask = v >> 7; - return (v + mask) ^ mask; + return ((v < 0) ? ((uint8_t)-v) : ((uint8_t)v)); } /* Constant time elliptic curve scalar multiplication. @@ -1903,120 +2265,143 @@ void Jac_scalar_multiplication( uint32_t *X3, uint32_t *Y3, uint32_t *Z3, uint32_t *X1, uint32_t *Y1, uint32_t *k, uint32_t *p, uint32_t *q) { uint32_t *scalar, *M, *X, *Y, *Z, *mem; + uint32_t *ONE = NULL; int i, sign, odd; - // int8_t *rec; uint8_t index; + size_t recodeLength = 175u; + size_t bitlen = 0u; + int8_t rec[CASPER_RECODE_LENGTH_MAX] = {0}; + + if (N_wordlen == 8U) + { + recodeLength = (size_t)kCASPER_ECC_P256_recode_len; + bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; + ONE = NISTr256; + } + + if (N_wordlen == 12U) + { + recodeLength = (size_t)kCASPER_ECC_P384_recode_len; + bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; + ONE = NISTr384; + } + + if (N_wordlen == 18U) + { + recodeLength = (size_t)kCASPER_ECC_P521_recode_len; + bitlen = (size_t)521U; + ONE = NISTr521; + } /* Point to the start of the LUT table space. */ - mem = &CASPER_MEM[LUT_SCRATCH_START]; + mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - scalar = &CASPER_MEM[LUT_SCRATCH_START + 12 * CASPER_NUM_LIMBS]; - X = &CASPER_MEM[LUT_SCRATCH_START + 13 * CASPER_NUM_LIMBS]; - Y = &CASPER_MEM[LUT_SCRATCH_START + 14 * CASPER_NUM_LIMBS]; - Z = &CASPER_MEM[LUT_SCRATCH_START + 15 * CASPER_NUM_LIMBS]; - M = &CASPER_MEM[LUT_SCRATCH_START + 16 * CASPER_NUM_LIMBS]; + scalar = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * (N_wordlen + 4U)]; + X = &CASPER_MEM[(20U * N_wordlen + 80U) + 13U * (N_wordlen + 4U)]; + Y = &CASPER_MEM[(20U * N_wordlen + 80U) + 14U * (N_wordlen + 4U)]; + Z = &CASPER_MEM[(20U * N_wordlen + 80U) + 15U * (N_wordlen + 4U)]; + M = &CASPER_MEM[(20U * N_wordlen + 80U) + 16U * (N_wordlen + 4U)]; /* Point to memory the recoded scalar. - * CASPER_RECODE_LENGTH bytes is needed. */ - // rec = (int8_t*)&CASPER_MEM[LUT_SCRATCH_START + 17 * CASPER_NUM_LIMBS]; - int8_t rec[CASPER_RECODE_LENGTH]; - - CASPER_MEMCPY(scalar, k, sizeof(uint32_t) * NUM_LIMBS); + CASPER_MEMCPY(scalar, k, sizeof(uint32_t) * N_wordlen); /* Precomputation: compute 1*P, 3*P, 5*P, and 7*P */ -#define LUT(P, x) (mem + (3 * ((P)-1) / 2 + (x)) * CASPER_NUM_LIMBS) +#define FSL_CASPER_LUT(P, x) (mem + (3U * ((P)-1U) / 2U + (x)) * (N_wordlen + 4U)) /* Set 1*P */ - copy(Z3, ONE); - copy(LUT(1, 0), X1); - copy(LUT(1, 1), Y1); - copy(LUT(1, 2), Z3); + CASPER_MEMCPY(Z3, ONE, N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(FSL_CASPER_LUT(1U, 0U), X1, N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(FSL_CASPER_LUT(1U, 1U), Y1, N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(FSL_CASPER_LUT(1U, 2U), Z3, N_wordlen * sizeof(uint32_t)); /* Compute 2*P */ Jac_double(X3, Y3, Z3, X1, Y1, Z3); /* Compute 3*P = 2P + P */ - Jac_add_affine(LUT(3, 0), LUT(3, 1), LUT(3, 2), X3, Y3, Z3, X1, Y1); + Jac_add_affine(FSL_CASPER_LUT(3U, 0U), FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3, X1, Y1); /* Compute 5*P = 3P + 2P */ - Jac_addition(LUT(5, 0), LUT(5, 1), LUT(5, 2), LUT(3, 0), LUT(3, 1), LUT(3, 2), X3, Y3, Z3); + Jac_addition(FSL_CASPER_LUT(5U, 0U), FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), FSL_CASPER_LUT(3U, 0U), + FSL_CASPER_LUT(3U, 1U), FSL_CASPER_LUT(3U, 2U), X3, Y3, Z3); /* Compute 7*P = 5P + 2P */ - Jac_addition(LUT(7, 0), LUT(7, 1), LUT(7, 2), LUT(5, 0), LUT(5, 1), LUT(5, 2), X3, Y3, Z3); + Jac_addition(FSL_CASPER_LUT(7U, 0U), FSL_CASPER_LUT(7U, 1U), FSL_CASPER_LUT(7U, 2U), FSL_CASPER_LUT(5U, 0U), + FSL_CASPER_LUT(5U, 1U), FSL_CASPER_LUT(5U, 2U), X3, Y3, Z3); /* Recode the scalar */ - odd = casper_get_word(&scalar[0]) & 1u; - sub_n(M, q, scalar, NUM_LIMBS); // todo!!! - casper_select(scalar, M, scalar, odd, NUM_LIMBS); + odd = (int32_t)((uint32_t)(casper_get_word(&scalar[0]) & 1U)); + (void)sub_n(M, q, scalar, (int16_t)(uint16_t)N_wordlen); // todo!!! + casper_select(scalar, M, scalar, odd, (int16_t)(uint16_t)N_wordlen); /* Use n=384 and w=4 --> compute ciel(384/3) = 128 + 1 digits */ - uint32_t scalarSysram[/*CASPER_*/ NUM_LIMBS]; - CASPER_MEMCPY(scalarSysram, scalar, /*CASPER_*/ NUM_LIMBS * sizeof(uint32_t)); - recode(rec, scalarSysram, N_bitlen, 4); + uint32_t scalarSysram[CASPER_MAX_ECC_SIZE_WORDLEN]; + CASPER_MEMCPY(scalarSysram, scalar, /*CASPER_*/ N_wordlen * sizeof(uint32_t)); + recode(rec, scalarSysram, (int32_t)bitlen, 4); /* Set the first value. */ - index = int8abs(rec[CASPER_RECODE_LENGTH - 1]); - sign = ((uint8_t)rec[CASPER_RECODE_LENGTH - 1]) >> 7; - copy(X3, LUT(index, 0)); - copy(Y3, LUT(index, 1)); - copy(Z3, LUT(index, 2)); + index = int8abs(rec[recodeLength - 1U]); + sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[recodeLength - 1U]) >> 7); -/* Get the correct LUT element in constant time by touching - * all elements and masking out the correct one. - */ + CASPER_MEMCPY(X3, FSL_CASPER_LUT((uint32_t)index, 0U), N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Y3, FSL_CASPER_LUT((uint32_t)index, 1U), N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Z3, FSL_CASPER_LUT((uint32_t)index, 2U), N_wordlen * sizeof(uint32_t)); -#define GET_LUT(x, y, z, index) \ - do \ - { \ - int m; \ - copy(x, LUT(1, 0)); \ - copy(y, LUT(1, 1)); \ - copy(z, LUT(1, 2)); \ - m = (index == 3); \ - casper_select(x, x, LUT(3, 0), m, NUM_LIMBS); \ - casper_select(y, y, LUT(3, 1), m, NUM_LIMBS); \ - casper_select(z, z, LUT(3, 2), m, NUM_LIMBS); \ - m = (index == 5); \ - casper_select(x, x, LUT(5, 0), m, NUM_LIMBS); \ - casper_select(y, y, LUT(5, 1), m, NUM_LIMBS); \ - casper_select(z, z, LUT(5, 2), m, NUM_LIMBS); \ - m = (index == 7); \ - casper_select(x, x, LUT(7, 0), m, NUM_LIMBS); \ - casper_select(y, y, LUT(7, 1), m, NUM_LIMBS); \ - casper_select(z, z, LUT(7, 2), m, NUM_LIMBS); \ - } while (0) + /* Get the correct LUT element in constant time by touching + * all elements and masking out the correct one. + */ + +#define GET_LUT(x, y, z, index) \ + do \ + { \ + int m; \ + CASPER_MEMCPY((x), FSL_CASPER_LUT(1U, 0U), N_wordlen * sizeof(uint32_t)); \ + CASPER_MEMCPY((y), FSL_CASPER_LUT(1U, 1U), N_wordlen * sizeof(uint32_t)); \ + CASPER_MEMCPY((z), FSL_CASPER_LUT(1U, 2U), N_wordlen * sizeof(uint32_t)); \ + m = (int32_t)((index) == 3U); \ + casper_select((x), (x), FSL_CASPER_LUT(3U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((y), (y), FSL_CASPER_LUT(3U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((z), (z), FSL_CASPER_LUT(3U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ + m = (int32_t)((index) == 5U); \ + casper_select((x), (x), FSL_CASPER_LUT(5U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((y), (y), FSL_CASPER_LUT(5U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((z), (z), FSL_CASPER_LUT(5U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ + m = (int32_t)((index) == 7U); \ + casper_select((x), (x), FSL_CASPER_LUT(7U, 0U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((y), (y), FSL_CASPER_LUT(7U, 1U), m, (int16_t)(uint16_t)N_wordlen); \ + casper_select((z), (z), FSL_CASPER_LUT(7U, 2U), m, (int16_t)(uint16_t)N_wordlen); \ + } while (false) GET_LUT(X3, Y3, Z3, index); /* Compute -y and select the positive or negative point. */ - sub_n(M, p, Y3, NUM_LIMBS); // todo!!! - casper_select(Y3, Y3, M, sign, NUM_LIMBS); + (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! + casper_select(Y3, Y3, M, sign, (int16_t)(uint16_t)N_wordlen); - for (i = CASPER_RECODE_LENGTH - 2; i >= 0; i--) + for (i = (int)(uint32_t)(recodeLength - 2U); i >= 0; i--) { Jac_double(X3, Y3, Z3, X3, Y3, Z3); Jac_double(X3, Y3, Z3, X3, Y3, Z3); Jac_double(X3, Y3, Z3, X3, Y3, Z3); index = int8abs(rec[i]); - sign = ((uint8_t)rec[i]) >> 7; + sign = (int32_t)(uint32_t)(uint8_t)(((uint8_t)rec[i]) >> 7); GET_LUT(X, Y, Z, index); /* Compute -y and select the positive or negative point. */ - sub_n(scalar, p, Y, NUM_LIMBS); // todo!!! - casper_select(scalar, Y, scalar, sign, NUM_LIMBS); + (void)sub_n(scalar, p, Y, (int16_t)(uint16_t)N_wordlen); // todo!!! + casper_select(scalar, Y, scalar, sign, (int16_t)(uint16_t)N_wordlen); Jac_addition(X3, Y3, Z3, X3, Y3, Z3, X, scalar, Z); } - sub_n(M, p, Y3, NUM_LIMBS); // todo!!! + (void)sub_n(M, p, Y3, (int16_t)(uint16_t)N_wordlen); // todo!!! - casper_select(Y3, M, Y3, odd, NUM_LIMBS); + casper_select(Y3, M, Y3, odd, (int16_t)(uint16_t)N_wordlen); } -#undef LUT +#undef FSL_CASPER_LUT #undef GET_LUT /* @@ -2048,140 +2433,198 @@ void Jac_scalar_multiplication( * Output: mem, memory location for the LUT. */ -#define LUT_LIMBS NUM_LIMBS - -static void precompute_double_scalar_LUT(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) +static void precompute_double_scalar_LUT16(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) { uint32_t *Q2x, *Q2y, *Q2z, *P2x, *P2y, *P2z, *Z, *mem; - int index = 0; + uint32_t *ONE = NULL; + uint32_t index = 0; - Q2x = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 0 * CASPER_NUM_LIMBS]; - Q2y = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 1 * CASPER_NUM_LIMBS]; - Q2z = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 2 * CASPER_NUM_LIMBS]; + if (N_wordlen == 8U) + { + ONE = NISTr256; + } + + if (N_wordlen == 12U) + { + ONE = NISTr384; + } + + Q2x = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 0U * (N_wordlen + 4U)]; + Q2y = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; + Q2z = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; /* Re-use memory from different scratch space since no - * projective point addition is used below. */ - P2x = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; - P2z = &CASPER_MEM[ECC_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; - P2y = &CASPER_MEM[ECC_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; - Z = &CASPER_MEM[ECC_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; + * projective point addition is used below. */ + P2x = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 5U * (N_wordlen + 4U)]; + P2z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 6U * (N_wordlen + 4U)]; + P2y = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 7U * (N_wordlen + 4U)]; + Z = &CASPER_MEM[((2U * (N_wordlen + 4U)) + (9U * (N_wordlen + 4U))) + 8U * (N_wordlen + 4U)]; - mem = &CASPER_MEM[LUT_SCRATCH_START]; + mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; - copy(Z, ONE); + CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); // 00 10 = 0*P + 2*Q Jac_double(Q2x, Q2y, Q2z, Qx, Qy, Z); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; // 00 11 = 0*P + 3*Q Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Qx, Qy); - copy(&mem[index], P2x); - index += LUT_LIMBS; - copy(&mem[index], P2y); - index += LUT_LIMBS; - copy(&mem[index], P2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; // 01 10 = 1*P + 2*Q Jac_add_affine(P2x, P2y, P2z, Q2x, Q2y, Q2z, Px, Py); - copy(&mem[index], P2x); - index += LUT_LIMBS; - copy(&mem[index], P2y); - index += LUT_LIMBS; - copy(&mem[index], P2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; // 01 11 = 1*P + 3*Q Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Qx, Qy); - copy(&mem[index], P2x); - index += LUT_LIMBS; - copy(&mem[index], P2y); - index += LUT_LIMBS; - copy(&mem[index], P2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; // 10 00 = 2*P + 0*Q Jac_double(P2x, P2y, P2z, Px, Py, Z); - copy(&mem[index], P2x); - index += LUT_LIMBS; - copy(&mem[index], P2y); - index += LUT_LIMBS; - copy(&mem[index], P2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; // 10 01 = 2*P + 1*Q Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; // 10 10 = 2*P + 2*Q Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; // 10 11 = 2*P + 3*Q Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; // 11 00 = 3*P + 0*Q Jac_add_affine(P2x, P2y, P2z, P2x, P2y, P2z, Px, Py); - copy(&mem[index], P2x); - index += LUT_LIMBS; - copy(&mem[index], P2y); - index += LUT_LIMBS; - copy(&mem[index], P2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], P2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], P2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; // 11 01 = 3*P + 1*Q Jac_add_affine(Q2x, Q2y, Q2z, P2x, P2y, P2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; // 11 10 = 3*P + 2*Q Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; // 11 11 = 3*P + 3*Q Jac_add_affine(Q2x, Q2y, Q2z, Q2x, Q2y, Q2z, Qx, Qy); - copy(&mem[index], Q2x); - index += LUT_LIMBS; - copy(&mem[index], Q2y); - index += LUT_LIMBS; - copy(&mem[index], Q2z); - index += LUT_LIMBS; + CASPER_MEMCPY(&mem[index], Q2x, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2y, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Q2z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; } -#define GETLUTX(x) (3 * (x)*LUT_LIMBS) -#define GETLUTY(x) (3 * (x)*LUT_LIMBS + 1 * LUT_LIMBS) -#define GETLUTZ(x) (3 * (x)*LUT_LIMBS + 2 * LUT_LIMBS) +/* + * Pre-compute the following 4 points: + * 0 0 = 0*P + 0*Q <-- Not needed when using sliding windows + * 0 1 = 0*P + 1*Q + * + * 1 0 = 1*P + 0*Q + * 1 1 = 1*P + 1*Q + * + * index = (bitsj+1) & (0-bitsi) + * + * Input: P = (X1 : Y1 : Z1) and + * Q = (X2 : Y2 : Z2) + * Output: mem, memory location for the LUT. + */ + +static void precompute_double_scalar_LUT4(uint32_t *Px, uint32_t *Py, uint32_t *Qx, uint32_t *Qy) +{ + uint32_t *Z, *mem, *ONE; + uint32_t index = 0; + + ONE = NISTr521; + + /* Re-use memory from different scratch space since no + * projective point addition is used below. */ + Z = &CASPER_MEM[(11U * N_wordlen + 4U) + 5U * (N_wordlen + 4U)]; + mem = &CASPER_MEM[(20U * N_wordlen + 80U)]; + + CASPER_MEMCPY(Z, ONE, N_wordlen * sizeof(uint32_t)); + + // 0*P + 1*Q + CASPER_MEMCPY(&mem[index], Qx, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Qy, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 1*P + 0*Q + CASPER_MEMCPY(&mem[index], Px, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Py, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + CASPER_MEMCPY(&mem[index], Z, N_wordlen * sizeof(uint32_t)); + index += N_wordlen; + + // 1*P + 1*Q + Jac_add_affine(&mem[index], &mem[index + N_wordlen], &mem[index + 2U * N_wordlen], Px, Py, Z, Qx, Qy); +} + +#define GETLUTX(x) (3U * (x)*N_wordlen) +#define GETLUTY(x) (3U * (x)*N_wordlen + 1U * N_wordlen) +#define GETLUTZ(x) (3U * (x)*N_wordlen + 2U * N_wordlen) /* Compute the double scalar multiplication * (X3 : Y3 : Z3) = k1 * (X1, Y1) + k2 * (X2, Y2) @@ -2199,131 +2642,197 @@ void double_scalar_multiplication(uint32_t *X3, uint32_t *Y2, uint32_t *k2) { - uint32_t index, c = 0; - uint32_t *p1, *p2, x1, x2, *lut, *Tx, *Ty, *Tz; + uint32_t index = 0, c = 0; + uint32_t *p1 = NULL, *p2 = NULL, x1, x2, *lut, *Tx = NULL, *Ty = NULL, *Tz = NULL; + size_t bitlen, shiftr, shiftl = 0u; - precompute_double_scalar_LUT(X1, Y1, X2, Y2); + if (N_wordlen == 8U) + { + bitlen = (size_t)kCASPER_ECC_P256_N_bitlen; + precompute_double_scalar_LUT16(X1, Y1, X2, Y2); + shiftr = 30U; + shiftl = 2U; + } - lut = &CASPER_MEM[LUT_SCRATCH_START]; - p1 = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS]; - p2 = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 1 * CASPER_NUM_LIMBS]; + if (N_wordlen == 12U) + { + bitlen = (size_t)kCASPER_ECC_P384_N_bitlen; + precompute_double_scalar_LUT16(X1, Y1, X2, Y2); + shiftr = 30U; + shiftl = 2U; + } - Tx = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 2 * CASPER_NUM_LIMBS]; - Ty = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 3 * CASPER_NUM_LIMBS]; - Tz = &CASPER_MEM[LUT_SCRATCH_START + 48 * LUT_LIMBS + 4 * CASPER_NUM_LIMBS]; + if (N_wordlen == 18U) + { + bitlen = (size_t)kCASPER_ECC_P521_N_bitlen; + precompute_double_scalar_LUT4(X1, Y1, X2, Y2); + shiftr = 31U; + shiftl = 1U; + } - CASPER_MEMCPY(p1, k1, sizeof(uint32_t) * NUM_LIMBS); - CASPER_MEMCPY(p2, k2, sizeof(uint32_t) * NUM_LIMBS); + lut = &CASPER_MEM[(20U * N_wordlen + 80U)]; + + if (N_wordlen == 8U || N_wordlen == 12U) + { + p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen]; + p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 1U * (N_wordlen + 4U)]; + + Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 2U * (N_wordlen + 4U)]; + Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 3U * (N_wordlen + 4U)]; + Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 48U * N_wordlen + 4U * (N_wordlen + 4U)]; + } + + if (N_wordlen == 18U) + { + p1 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen]; + p2 = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 1U * (N_wordlen + 4U)]; + + Tx = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 2U * (N_wordlen + 4U)]; + Ty = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 3U * (N_wordlen + 4U)]; + Tz = &CASPER_MEM[(20U * N_wordlen + 80U) + 12U * N_wordlen + 4U * (N_wordlen + 4U)]; + } + + CASPER_MEMCPY(p1, k1, sizeof(uint32_t) * N_wordlen); + CASPER_MEMCPY(p2, k2, sizeof(uint32_t) * N_wordlen); /* Check if we can slide. */ - while (((casper_get_word(&p1[NUM_LIMBS - 1]) | casper_get_word(&p2[NUM_LIMBS - 1])) >> 31) == 0 && c < 256) + while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && c < bitlen) { - shiftleft(p1, p1, 1); - shiftleft(p2, p2, 1); + shiftleft(p1, p1, 1U); + shiftleft(p2, p2, 1U); c++; /* No doubling needed. */ } /* Set the first value. */ - x1 = casper_get_word(&p1[NUM_LIMBS - 1]) >> 30; - x2 = casper_get_word(&p2[NUM_LIMBS - 1]) >> 30; - index = (x2 | (x1 << 2)) - 2 - (x1 != 0) * 2; - shiftleft(p1, p1, 2); - shiftleft(p2, p2, 2); - - copy(X3, &lut[GETLUTX(index)]); - copy(Y3, &lut[GETLUTY(index)]); - copy(Z3, &lut[GETLUTZ(index)]); - c += 2; - -// todo: create an is_zero function -#if CASPER_ECC_P256 - while ((casper_get_word(&p1[0]) | casper_get_word(&p1[1]) | casper_get_word(&p1[2]) | casper_get_word(&p1[3]) | - casper_get_word(&p1[4]) | casper_get_word(&p1[5]) | casper_get_word(&p1[6]) | casper_get_word(&p1[7]) | - casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | - casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | casper_get_word(&p2[6]) | casper_get_word(&p2[7])) != 0) + x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; + x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; + if (N_wordlen == 8U || N_wordlen == 12U) { -#elif CASPER_ECC_P384 + index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; + } + + if (N_wordlen == 18U) + { + index = (((x2) + 1U) & (0U - (x1))); + } + shiftleft(p1, p1, shiftl); + shiftleft(p2, p2, shiftl); + + CASPER_MEMCPY(X3, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Y3, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Z3, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); + c += shiftl; + + // todo: create an is_zero function + while ((casper_get_word(&p1[0]) | casper_get_word(&p1[1]) | casper_get_word(&p1[2]) | casper_get_word(&p1[3]) | casper_get_word(&p1[4]) | casper_get_word(&p1[5]) | casper_get_word(&p1[6]) | casper_get_word(&p1[7]) | casper_get_word(&p1[8]) | casper_get_word(&p1[9]) | casper_get_word(&p1[10]) | casper_get_word(&p1[11]) | - casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | - casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | casper_get_word(&p2[6]) | casper_get_word(&p2[7]) | - casper_get_word(&p2[8]) | casper_get_word(&p2[9]) | casper_get_word(&p2[10]) | casper_get_word(&p2[11])) != - 0) + casper_get_word(&p1[12]) | casper_get_word(&p1[13]) | casper_get_word(&p1[14]) | casper_get_word(&p1[15]) | + casper_get_word(&p1[16]) | casper_get_word(&p1[17]) | casper_get_word(&p2[0]) | casper_get_word(&p2[1]) | + casper_get_word(&p2[2]) | casper_get_word(&p2[3]) | casper_get_word(&p2[4]) | casper_get_word(&p2[5]) | + casper_get_word(&p2[6]) | casper_get_word(&p2[7]) | casper_get_word(&p2[8]) | casper_get_word(&p2[9]) | + casper_get_word(&p2[10]) | casper_get_word(&p2[11]) | casper_get_word(&p2[12]) | casper_get_word(&p2[13]) | + casper_get_word(&p2[14]) | casper_get_word(&p2[15]) | casper_get_word(&p2[16]) | + casper_get_word(&p2[17])) != 0U) { -#endif /* Check if we can slide. */ - while (((casper_get_word(&p1[NUM_LIMBS - 1]) | casper_get_word(&p2[NUM_LIMBS - 1])) >> 31) == 0 && c < N_bitlen) + while (((casper_get_word(&p1[N_wordlen - 1U]) | casper_get_word(&p2[N_wordlen - 1U])) >> 31) == 0U && + c < bitlen) { - shiftleft(p1, p1, 1); - shiftleft(p2, p2, 1); + shiftleft(p1, p1, 1U); + shiftleft(p2, p2, 1U); Jac_double(X3, Y3, Z3, X3, Y3, Z3); c++; } - if (c >= (N_bitlen - 1)) + if (c >= (bitlen - 1U)) + { break; + } - /* Double twice. */ - Jac_double(X3, Y3, Z3, X3, Y3, Z3); - Jac_double(X3, Y3, Z3, X3, Y3, Z3); + for (uint32_t i = 0; i < shiftl; i++) + { + Jac_double(X3, Y3, Z3, X3, Y3, Z3); + } - /* Add in the correct value. */ - x1 = casper_get_word(&p1[NUM_LIMBS - 1]) >> 30; - x2 = casper_get_word(&p2[NUM_LIMBS - 1]) >> 30; - index = (x2 | (x1 << 2)) - 2 - (x1 != 0) * 2; + x1 = casper_get_word(&p1[N_wordlen - 1U]) >> shiftr; + x2 = casper_get_word(&p2[N_wordlen - 1U]) >> shiftr; - shiftleft(p1, p1, 2); - shiftleft(p2, p2, 2); + if (N_wordlen == 8U || N_wordlen == 12U) + { + index = (x2 | (x1 << 2)) - 2U - (uint32_t)(x1 != 0U) * 2U; + } - copy(Tx, &lut[GETLUTX(index)]); - copy(Ty, &lut[GETLUTY(index)]); - copy(Tz, &lut[GETLUTZ(index)]); + if (N_wordlen == 18U) + { + index = (((x2) + 1U) & (0U - (x1))); + } + + shiftleft(p1, p1, shiftl); + shiftleft(p2, p2, shiftl); + + CASPER_MEMCPY(Tx, &lut[GETLUTX(index)], N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Ty, &lut[GETLUTY(index)], N_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(Tz, &lut[GETLUTZ(index)], N_wordlen * sizeof(uint32_t)); Jac_addition(X3, Y3, Z3, X3, Y3, Z3, Tx, Ty, Tz); //&lut[GETLUTX(index)], &lut[GETLUTY(index)], &lut[GETLUTZ(index)]); - c += 2; + c += shiftl; } /* Special case in the end. */ - if (c == (N_bitlen - 1)) + if (c == (bitlen - 1U)) { Jac_double(X3, Y3, Z3, X3, Y3, Z3); - x1 = casper_get_word(&p1[NUM_LIMBS - 1]) >> 31; - x2 = casper_get_word(&p2[NUM_LIMBS - 1]) >> 31; - if (x1) + x1 = casper_get_word(&p1[N_wordlen - 1U]) >> 31; + x2 = casper_get_word(&p2[N_wordlen - 1U]) >> 31; + if (0U != x1) { Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X1, Y1); } - if (x2) + if (x2 != 0U) { Jac_add_affine(X3, Y3, Z3, X3, Y3, Z3, X2, Y2); } c++; } - while (c < N_bitlen) + while (c < bitlen) { Jac_double(X3, Y3, Z3, X3, Y3, Z3); c++; } } -#if CASPER_ECC_P256 static void invert_mod_p256(uint32_t *c, uint32_t *a) { int i; uint32_t *t, *t2, *s1, *s2, *s4, *s8, *tmp; /* Assuming it is safe to use the ECC scratch size. */ - t = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - t2 = &CASPER_MEM[ECC_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - s1 = &CASPER_MEM[ECC_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; - s2 = &CASPER_MEM[ECC_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; - s4 = &CASPER_MEM[ECC_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; - s8 = &CASPER_MEM[ECC_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; - tmp = &CASPER_MEM[ECC_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; + t = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + t2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 3U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + s1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 4U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + s2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 5U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + s4 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 6U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + s8 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 7U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + tmp = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 8U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; // t2 = n^(2^1)*n # 11 square_casper(tmp, a); @@ -2424,22 +2933,28 @@ static void invert_mod_p256(uint32_t *c, uint32_t *a) } // A and C do not need to be in Casper memory -static void toMontgomery(uint32_t *C, uint32_t *A) +static void toMontgomery_ECC_P256(uint32_t *C, uint32_t *A) { /* R^2 = 2^512 mod p, used to convert values to Montgomery form. */ - uint32_t R2[NUM_LIMBS] = {0x00000003, 0x00000000, 0xffffffff, 0xfffffffb, 0xfffffffe, 0xffffffff, 0xfffffffd, 0x4}; + uint32_t R2[kCASPER_ECC_P256_wordlen] = {0x00000003, 0x00000000, 0xffffffffU, 0xfffffffbU, + 0xfffffffeU, 0xffffffffU, 0xfffffffdU, 0x4}; uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; + T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 1U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; + T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U))) + + 2U * ((uint32_t)kCASPER_ECC_P256_wordlen + 4U)]; - CASPER_MEMCPY(T1, R2, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P256_wordlen * sizeof(uint32_t)); } -#endif /* CASPER_ECC_P256 */ /* Compute inversion modulo NIST-p384 using Fermats little theorem. * Using c = a^(p-2) = a^(-1) mod p. @@ -2447,7 +2962,7 @@ static void toMontgomery(uint32_t *C, uint32_t *A) * modular arithmetic or computes automatically the Montgomery inverse * if all arithmetic is Montgomery arithmetic. */ -#if CASPER_ECC_P384 + static void invert_mod_p384(uint32_t *c, uint32_t *a) { int i; @@ -2456,16 +2971,17 @@ static void invert_mod_p384(uint32_t *c, uint32_t *a) /* Assuming it is safe to use the LUT scratch size. * Hence, do not invert while elements in the LUT are needed. */ - e = &CASPER_MEM[LUT_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - d = &CASPER_MEM[LUT_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - tmp = &CASPER_MEM[LUT_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; - t0 = &CASPER_MEM[LUT_SCRATCH_START + 3 * CASPER_NUM_LIMBS]; - t1 = &CASPER_MEM[LUT_SCRATCH_START + 4 * CASPER_NUM_LIMBS]; - t2 = &CASPER_MEM[LUT_SCRATCH_START + 5 * CASPER_NUM_LIMBS]; - t3 = &CASPER_MEM[LUT_SCRATCH_START + 6 * CASPER_NUM_LIMBS]; - t4 = &CASPER_MEM[LUT_SCRATCH_START + 7 * CASPER_NUM_LIMBS]; - t5 = &CASPER_MEM[LUT_SCRATCH_START + 8 * CASPER_NUM_LIMBS]; - t6 = &CASPER_MEM[LUT_SCRATCH_START + 9 * CASPER_NUM_LIMBS]; + e = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + d = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + tmp = + &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t0 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 6U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 7U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t5 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 8U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + t6 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P384_wordlen + 80U) + 9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; square_casper(tmp, a); // 2 square_casper(t1, tmp); // 4 @@ -2643,20 +3159,275 @@ static void invert_mod_p384(uint32_t *c, uint32_t *a) } // A and C do not need to be in Casper memory -static void toMontgomery(uint32_t *C, uint32_t *A) +static void toMontgomery_ECC_P384(uint32_t *C, uint32_t *A) { /* R^2 = 2^768 mod p, used to convert values to Montgomery form. */ - uint32_t R2[NUM_LIMBS] = {0x00000001, 0xfffffffe, 0x00000000, 0x00000002, 0x00000000, 0xfffffffe, - 0x00000000, 0x00000002, 0x1, 0x0, 0x0, 0x0}; + uint32_t R2[kCASPER_ECC_P384_wordlen] = {0x00000001, 0xfffffffeU, 0x00000000, 0x00000002, 0x00000000, 0xfffffffeU, + 0x00000000, 0x00000002, 0x1, 0x0, 0x0, 0x0}; uint32_t *T1, *T2, *T3; - T1 = &CASPER_MEM[ECC_SCRATCH_START + 0 * CASPER_NUM_LIMBS]; - T2 = &CASPER_MEM[ECC_SCRATCH_START + 1 * CASPER_NUM_LIMBS]; - T3 = &CASPER_MEM[ECC_SCRATCH_START + 2 * CASPER_NUM_LIMBS]; + T1 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + + 0U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + T2 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + + 1U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; + T3 = &CASPER_MEM[((2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)) + + (9U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U))) + + 2U * ((uint32_t)kCASPER_ECC_P384_wordlen + 4U)]; - CASPER_MEMCPY(T1, R2, NUM_LIMBS * sizeof(uint32_t)); - CASPER_MEMCPY(T2, A, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); multiply_casper(T3, T2, T1); - CASPER_MEMCPY(C, T3, NUM_LIMBS * sizeof(uint32_t)); + CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P384_wordlen * sizeof(uint32_t)); } -#endif /* CASPER_ECC_P384 */ + +static void invert_mod_p521(uint32_t *c, uint32_t *a) +{ + int i; + uint32_t *e3, *d2, *d3, *d4, *T2, *T4; // 6 residues needed + + /* Assuming it is safe to use the LUT scratch size. + * Hence, do not invert while elements in the LUT are needed. + */ + e3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + d2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + d3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + d4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 3U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 4U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + T4 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 5U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + + square_casper(d2, a); + multiply_casper(T2, d2, a); + + // d3 = 2^2 * T2 + square_casper(d3, T2); + square_casper(e3, d3); + multiply_casper(T4, e3, T2); + + // d3 = 2^4 * T4 + square_casper(d3, T4); + square_casper(e3, d3); + square_casper(d3, e3); + square_casper(e3, d3); + multiply_casper(d2, e3, T4); + + // d3 = 2^8 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + for (i = 0; i < 3; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d4, e3, d2); + + // d3 = 2^16 * d2 + square_casper(d3, d4); + square_casper(e3, d3); + for (i = 0; i < 7; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d2, e3, d4); + + // d3 = 2^32 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + for (i = 0; i < 15; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d4, e3, d2); + + // d3 = 2^64 * d2 + square_casper(d3, d4); + square_casper(e3, d3); + for (i = 0; i < 31; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d2, e3, d4); + + // d3 = 2^128 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + for (i = 0; i < 63; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d4, e3, d2); + + // d3 = 2^256 * d2 + square_casper(d3, d4); + square_casper(e3, d3); + for (i = 0; i < 127; i++) + { + square_casper(d3, e3); + square_casper(e3, d3); + } + multiply_casper(d2, e3, d4); + + // d3 = 2^2 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + multiply_casper(d2, e3, T2); + + // d3 = 2^4 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + square_casper(d3, e3); + square_casper(e3, d3); + multiply_casper(d2, e3, T4); + + square_casper(d3, d2); + multiply_casper(d2, d3, a); + + // d3 = 2 ^ 2 * d2 + square_casper(d3, d2); + square_casper(e3, d3); + multiply_casper(c, e3, a); +} + +static void toMontgomery_ECC_P521(uint32_t *C, uint32_t *A) +{ + /* R^2 = 2^1088 mod p, used to convert values to Montgomery form. */ + // uint32_t R2[NUM_LIMBS] = { 0x00000000, 0x4000, 0, 0, + // 0, 0, 0, 0, + // 0, 0, 0, 0, + // 0 }; + /* R^2 = 2^1152 mod p, used to convert values to Montgomery form. */ + uint32_t R2[kCASPER_ECC_P521_wordlen] = {0, 0, 0, 0x4000, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + uint32_t *T1, *T2, *T3; + T1 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 0U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + T2 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 1U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + T3 = &CASPER_MEM[(20U * (uint32_t)kCASPER_ECC_P521_wordlen + 80U) + 2U * ((uint32_t)kCASPER_ECC_P521_wordlen + 4U)]; + + CASPER_MEMCPY(T1, R2, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + CASPER_MEMCPY(T2, A, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); + + multiply_casper(T3, T2, T1); + CASPER_MEMCPY(C, T3, (uint32_t)kCASPER_ECC_P521_wordlen * sizeof(uint32_t)); +} + +static void MultprecCiosMul521_ct( + uint32_t w_out[], const uint32_t a[], const uint32_t b[], const uint32_t Nmod[], const uint32_t *Np) +{ + uint32_t j; + uint64_t carry; + uint64_t *a64, *b64, *w64; + + uint32_t *T1 = &CASPER_MEM[0], borrow; + + a64 = (uint64_t *)(uintptr_t)a; + b64 = (uint64_t *)(uintptr_t)b; + w64 = (uint64_t *)(uintptr_t)w_out; + + if (a != NULL) + { /* if !a, we are reducing only */ + PreZeroW(j, w_out); + } + SET_DWORD(&w64[N_dwordlen], 0ULL); + SET_DWORD(&w64[N_dwordlen + 1U], 0ULL); + /* with accelerator */ + + /* loop j and then reduce after each j round */ + for (j = 0; j < N_dwordlen; j++) + { + /* Step 3. Iterate over N words of u using j - perform Multiply-accumulate */ + /* push-pull: we do a*b and then separately m*n (reduce) */ + if (a != NULL) + { /* if mul&reduce vs. reduce only */ + carry = GET_DWORD(&w64[N_dwordlen]); + Accel_SetABCD_Addr(CA_MK_OFF(&b64[j]), CA_MK_OFF(a64)); + Accel_crypto_mul( + Accel_IterOpcodeResaddr(N_dwordlen - 1U, (uint32_t)kCASPER_OpMul6464FullSum, CA_MK_OFF(w64))); + Accel_done(); + /* max carry is contained since ~0*~0=0xFFFE0001+0xFFFF=0xFFFF0000, */ + /* so max carry is 0xFFFF and 0xFFFF0000+0xFFFF=0xFFFFFFFF */ + /* accel took care of w_out[N_wordlen] & +1, so we just take care of the next double word if carry=1 */ + /* w64[N_dwordlen+1] = g_carry; */ + carry = (uint64_t)(GET_DWORD(&w64[N_dwordlen]) < carry); + SET_DWORD(&w64[N_dwordlen + 1U], carry); + } + + /* Fast reduction using only shifts for this special shape: + * (c - (-p^-1*c mod 2^64) * p)/2^64 = + * (c - c_0 * p)/2^64 = + * (\sum_{j=0}^9 c_i*2^64 - c_0 * p)/2^64 = + * (\sum_{j=0}^9 c_i*2^64 - c_0 * (2^521-1))/2^64 = + * (\sum_{j=0}^9 c_i*2^64 - c_0 * 2^521 - c_0)/2^64 = + * c_1 + c_2*2^64 + c_3*2^128 + c_4*2^192 + c_5*2^256 + c_6*2^320 + c_7*2^384 + c_8*2^448 + c_9*2^512 + c_0 * + * 2^{448 + 9} so one only needs to compute this 128-bit addition: [c_8, c_9] + c_0 * 2^9 + */ + + uint64_t *p64 = (uint64_t *)(uintptr_t)T1; + + /* p64[0] = w64[0] << 9;*/ + SET_DWORD(&p64[0], GET_DWORD(&w64[0]) << 9U); + /* p64[1] = w64[0] >> (64 - 9); */ + SET_DWORD(&p64[1], GET_DWORD(&w64[0]) >> (64 - 9)); + /* w64[0] = w64[1]; */ + SET_DWORD(&w64[0], GET_DWORD(&w64[1])); + /* w64[1] = w64[2]; */ + SET_DWORD(&w64[1], GET_DWORD(&w64[2])); + /* w64[2] = w64[3]; */ + SET_DWORD(&w64[2], GET_DWORD(&w64[3])); + /* w64[3] = w64[4]; */ + SET_DWORD(&w64[3], GET_DWORD(&w64[4])); + /* w64[4] = w64[5]; */ + SET_DWORD(&w64[4], GET_DWORD(&w64[5])); + /* w64[5] = w64[6]; */ + SET_DWORD(&w64[5], GET_DWORD(&w64[6])); + /* w64[6] = w64[7]; */ + SET_DWORD(&w64[6], GET_DWORD(&w64[7])); + + /* Compute p64 = p64 + {w64[8], w64[9]} using one additonal double-length limb, + * where p64 = w64[0] * 2^9. + */ + Accel_SetABCD_Addr(CA_MK_OFF(&w64[8]), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(2, (uint32_t)kCASPER_OpAdd64, /* kCASPER_OpAdd64, */ + CA_MK_OFF(p64))); + Accel_done(); + + /* w64[7] = p64[0]; */ + SET_DWORD(&w64[7], GET_DWORD(&p64[0])); + /* w64[8] = p64[1]; */ + SET_DWORD(&w64[8], GET_DWORD(&p64[1])); + /* w64[9] = 0; */ + SET_DWORD(&w64[9], (uint64_t)0U); + } + + /* memcpy(T1, w_out, (NUM_LIMBS + 1) * sizeof(uint32_t)); */ + /* now check if need to subtract Nmod */ + CASPER_MEMCPY_I2I(T1, w_out, (N_wordlen + 1U) * sizeof(uint32_t)); + + /* Compute w = w - N */ + Accel_SetABCD_Addr(CA_MK_OFF(Nmod), 0); + Accel_crypto_mul(Accel_IterOpcodeResaddr(N_dwordlen, (uint32_t)kCASPER_OpSub64, CA_MK_OFF(w_out))); + Accel_done(); + + /* if w_out > T1 then there was a borrow */ + /* borrow = (((uint32_t*)w_out)[NUM_LIMBS] > T1[NUM_LIMBS]); */ + borrow = (uint32_t)(GET_WORD(&((uint32_t *)w_out)[N_wordlen]) > GET_WORD(&T1[N_wordlen])); + SET_WORD(&w_out[N_wordlen + 1U], 0); + SET_WORD(&w_out[N_wordlen], 0); + /* w_out[NUM_LIMBS + 1] = 0; */ + /* w_out[NUM_LIMBS] = 0; */ + casper_select(w_out, w_out, T1, (int32_t)borrow, (int32_t)N_wordlen); +} + +#if defined(__GNUC__) +/* End of enforcing O1 optimize level for gcc*/ +#pragma GCC pop_options +#endif + +#if (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +// End of enforcing optimize off for clang +#pragma clang optimize on +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.h index b7cc9dbe06..328dc10111 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_casper.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * All rights reserved. * * @@ -23,9 +23,9 @@ */ /*! @name Driver version */ /*@{*/ -/*! @brief CASPER driver version. Version 2.0.2. +/*! @brief CASPER driver version. Version 2.2.3. * - * Current version: 2.0.2 + * Current version: 2.2.3 * * Change log: * - Version 2.0.0 @@ -33,9 +33,38 @@ * - Version 2.0.1 * - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input * - Version 2.0.2 - * - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of CASPER_RAM + * - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of + * CASPER_RAM + * - Version 2.0.3 + * - Bug fix KPSDK-28107 RSUB, FILL and ZERO operations not implemented in enum _casper_operation. + * - Version 2.0.4 + * - For GCC compiler, enforce O1 optimize level, specifically to remove strict-aliasing option. + * This driver is very specific and requires -fno-strict-aliasing. + * - Version 2.0.5 + * - Fix sign-compare warning. + * - Version 2.0.6 + * - Fix IAR Pa082 warning. + * - Version 2.0.7 + * - Fix MISRA-C 2012 issue. + * - Version 2.0.8 + * - Add feature macro for CASPER_RAM_OFFSET. + * - Version 2.0.9 + * - Remove unused function Jac_oncurve(). + * - Fix ECC384 build. + * - Version 2.0.10 + * - Fix MISRA-C 2012 issue. + * - Version 2.1.0 + * - Add ECC NIST P-521 elliptic curve. + * - Version 2.2.0 + * - Rework driver to support multiple curves at once. + * - Version 2.2.1 + * - Fix MISRA-C 2012 issue. + * - Version 2.2.2 + * - Enable hardware interleaving to RAMX0 and RAMX1 for CASPER by feature macro FSL_FEATURE_CASPER_RAM_HW_INTERLEAVE + * - Version 2.2.3 + * - Added macro into CASPER_Init and CASPER_Deinit to support devices without clock and reset control. */ -#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) /*@}*/ /*! @brief CASPER operation @@ -51,40 +80,51 @@ typedef enum _casper_operation kCASPER_OpMul6464Reduce = 0x04, /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/ kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/ - kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a uding 64-64=64, with last + kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a using 64-64=64, with last borrow implicit if any*/ kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/ - kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/ + kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/ + kCASPER_OpRSub64 = 0x0C, /*! Walking subtract with off_AB, and in/out off_RES using r=a-r */ kCASPER_OpShiftLeft32 = 0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/ kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by app (off_CD not used) and off_RES starts at MSW*/ - kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/ - kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/ - kCASPER_OpCompare = 0x16, /*! Compare two arrays, running all the way to the end*/ - kCASPER_OpCompareFast = 0x17, /*! Compare two arrays, stopping on 1st !=*/ + kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/ + kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/ + kCASPER_OpFill = 0x16, /*! Fill RESOFF using 64 bits at a time with value in A and B */ + kCASPER_OpZero = 0x17, /*! Fill RESOFF using 64 bits at a time of 0s */ + kCASPER_OpCompare = 0x18, /*! Compare two arrays, running all the way to the end*/ + kCASPER_OpCompareFast = 0x19, /*! Compare two arrays, stopping on 1st !=*/ } casper_operation_t; -#define CASPER_CP 1 -#define CASPER_CP_CTRL0 (0x0 >> 2) -#define CASPER_CP_CTRL1 (0x4 >> 2) -#define CASPER_CP_LOADER (0x8 >> 2) -#define CASPER_CP_STATUS (0xC >> 2) +/*! @brief Algorithm used for CASPER operation */ +typedef enum _casper_algo_t +{ + kCASPER_ECC_P256 = 0x01, /*!< ECC_P256*/ + kCASPER_ECC_P384 = 0x02, /*!< ECC_P384 */ + kCASPER_ECC_P521 = 0x03, /*!< ECC_P521 */ +} casper_algo_t; + +#define CASPER_CP 1 +#define CASPER_CP_CTRL0 (0x0 >> 2) +#define CASPER_CP_CTRL1 (0x4 >> 2) +#define CASPER_CP_LOADER (0x8 >> 2) +#define CASPER_CP_STATUS (0xC >> 2) #define CASPER_CP_INTENSET (0x10 >> 2) #define CASPER_CP_INTENCLR (0x14 >> 2) -#define CASPER_CP_INTSTAT (0x18 >> 2) -#define CASPER_CP_AREG (0x20 >> 2) -#define CASPER_CP_BREG (0x24 >> 2) -#define CASPER_CP_CREG (0x28 >> 2) -#define CASPER_CP_DREG (0x2C >> 2) -#define CASPER_CP_RES0 (0x30 >> 2) -#define CASPER_CP_RES1 (0x34 >> 2) -#define CASPER_CP_RES2 (0x38 >> 2) -#define CASPER_CP_RES3 (0x3C >> 2) -#define CASPER_CP_MASK (0x60 >> 2) -#define CASPER_CP_REMASK (0x64 >> 2) -#define CASPER_CP_LOCK (0x80 >> 2) -#define CASPER_CP_ID (0xFFC >> 2) +#define CASPER_CP_INTSTAT (0x18 >> 2) +#define CASPER_CP_AREG (0x20 >> 2) +#define CASPER_CP_BREG (0x24 >> 2) +#define CASPER_CP_CREG (0x28 >> 2) +#define CASPER_CP_DREG (0x2C >> 2) +#define CASPER_CP_RES0 (0x30 >> 2) +#define CASPER_CP_RES1 (0x34 >> 2) +#define CASPER_CP_RES2 (0x38 >> 2) +#define CASPER_CP_RES3 (0x3C >> 2) +#define CASPER_CP_MASK (0x60 >> 2) +#define CASPER_CP_REMASK (0x64 >> 2) +#define CASPER_CP_LOCK (0x80 >> 2) +#define CASPER_CP_ID (0xFFC >> 2) /* mcr (cp, opc1, value, CRn, CRm, opc2) */ #define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0) /* mcrr(coproc, opc1, value, CRm) */ @@ -97,28 +137,15 @@ typedef enum _casper_operation /* it will be slower by a bit. */ /* The file is compiled with N_bitlen passed in as number of bits of the RSA key */ /* #define N_bitlen 2048 */ -#define N_wordlen_max (4096 / 32) - -#define CASPER_ECC_P256 1 -#define CASPER_ECC_P384 0 - -#if CASPER_ECC_P256 -#define N_bitlen 256 -#endif /* CASPER_ECC_P256 */ - -#if CASPER_ECC_P384 -#define N_bitlen 384 -#endif /* CASPER_ECC_P256 */ - -#define NUM_LIMBS (N_bitlen / 32) +#define N_wordlen_max (4096U / 32U) enum { - kCASPER_RamOffset_Result = 0x0u, - kCASPER_RamOffset_Base = (N_wordlen_max + 8u), + kCASPER_RamOffset_Result = 0x0u, + kCASPER_RamOffset_Base = (N_wordlen_max + 8u), kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u), - kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u), - kCASPER_RamOffset_M64 = 1022, + kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u), + kCASPER_RamOffset_M64 = 1022U, }; /*! @} */ @@ -185,7 +212,15 @@ void CASPER_ModExp(CASPER_Type *base, uint32_t pubE, uint8_t *plaintext); -void CASPER_ecc_init(void); +/*! + * @brief Initialize prime modulus mod in Casper memory . + * + * Set the prime modulus mod in Casper memory and set N_wordlen + * according to selected algorithm. + * + * @param curve elliptic curve algoritm + */ +void CASPER_ecc_init(casper_algo_t curve); /*! * @brief Performs ECC secp256r1 point single scalar multiplication @@ -287,6 +322,56 @@ void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base, uint32_t Y2[12], uint32_t scalar2[12]); +/*! + * @brief Performs ECC secp521r1 point single scalar multiplication + * + * This function performs ECC secp521r1 point single scalar multiplication + * [resX; resY] = scalar * [X; Y] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate in normal form, little endian. + * @param[out] resY Output Y affine coordinate in normal form, little endian. + * @param X Input X affine coordinate in normal form, little endian. + * @param Y Input Y affine coordinate in normal form, little endian. + * @param scalar Input scalar integer, in normal form, little endian. + */ +void CASPER_ECC_SECP521R1_Mul( + CASPER_Type *base, uint32_t resX[18], uint32_t resY[18], uint32_t X[18], uint32_t Y[18], uint32_t scalar[18]); + +/*! + * @brief Performs ECC secp521r1 point double scalar multiplication + * + * This function performs ECC secp521r1 point double scalar multiplication + * [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2] + * Coordinates are affine in normal form, little endian. + * Scalars are little endian. + * All arrays are little endian byte arrays, uint32_t type is used + * only to enforce the 32-bit alignment (0-mod-4 address). + * + * @param base CASPER base address + * @param[out] resX Output X affine coordinate. + * @param[out] resY Output Y affine coordinate. + * @param X1 Input X1 affine coordinate. + * @param Y1 Input Y1 affine coordinate. + * @param scalar1 Input scalar1 integer. + * @param X2 Input X2 affine coordinate. + * @param Y2 Input Y2 affine coordinate. + * @param scalar2 Input scalar2 integer. + */ +void CASPER_ECC_SECP521R1_MulAdd(CASPER_Type *base, + uint32_t resX[18], + uint32_t resY[18], + uint32_t X1[18], + uint32_t Y1[18], + uint32_t scalar1[18], + uint32_t X2[18], + uint32_t Y2[18], + uint32_t scalar2[18]); + void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2); void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1); diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.c index b221bd7e2a..80460c0905 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.c @@ -1,5 +1,5 @@ /* - * Copyright 2017 - 2019 , NXP + * Copyright 2017 - 2021 , NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -24,18 +24,18 @@ !!! If required these #defines can be moved to chip library file ----------------------------------------------------------------------------*/ -#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 16 downto 0 */ -#define PLL_SSCG1_MDEC_VAL_M (0x3FFFC00ULL << PLL_SSCG1_MDEC_VAL_P) /* NDEC is in bits 9 downto 0 */ -#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ -#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) -#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ -#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) +#define PLL_SSCG1_MDEC_VAL_P (10U) /* MDEC is in bits 25 downto 10 */ +#define PLL_SSCG1_MDEC_VAL_M (0xFFFFULL << PLL_SSCG1_MDEC_VAL_P) +#define PLL_NDEC_VAL_P (0U) /* NDEC is in bits 9:0 */ +#define PLL_NDEC_VAL_M (0xFFUL << PLL_NDEC_VAL_P) +#define PLL_PDEC_VAL_P (0U) /*!< PDEC is in bits 6:0 */ +#define PLL_PDEC_VAL_M (0x1FUL << PLL_PDEC_VAL_P) #define PLL_MIN_CCO_FREQ_MHZ (275000000U) #define PLL_MAX_CCO_FREQ_MHZ (550000000U) -#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ -#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ -#define PLL_MIN_IN_SSMODE (3000000U) +#define PLL_LOWER_IN_LIMIT (2000U) /*!< Minimum PLL input rate */ +#define PLL_HIGHER_IN_LIMIT (150000000U) /*!< Maximum PLL input rate */ +#define PLL_MIN_IN_SSMODE (3000000U) #define PLL_MAX_IN_SSMODE \ (100000000U) /*!< Not find the value in UM, Just use the maximum frequency which device support */ @@ -43,17 +43,17 @@ #define PLL_NDEC_VAL_SET(value) (((unsigned long)(value) << PLL_NDEC_VAL_P) & PLL_NDEC_VAL_M) /* PLL PDEC reg */ #define PLL_PDEC_VAL_SET(value) (((unsigned long)(value) << PLL_PDEC_VAL_P) & PLL_PDEC_VAL_M) -/* SSCG control0 */ -#define PLL_SSCG1_MDEC_VAL_SET(value) (((unsigned long)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) +/* SSCG control1 */ +#define PLL_SSCG1_MDEC_VAL_SET(value) (((uint64_t)(value) << PLL_SSCG1_MDEC_VAL_P) & PLL_SSCG1_MDEC_VAL_M) /* PLL0 SSCG control1 */ #define PLL0_SSCG_MD_FRACT_P 0U -#define PLL0_SSCG_MD_INT_P 25U +#define PLL0_SSCG_MD_INT_P 25U #define PLL0_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL0_SSCG_MD_FRACT_P) -#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) +#define PLL0_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL0_SSCG_MD_INT_P) #define PLL0_SSCG_MD_FRACT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_FRACT_P) & PLL0_SSCG_MD_FRACT_M) -#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) +#define PLL0_SSCG_MD_INT_SET(value) (((uint64_t)(value) << PLL0_SSCG_MD_INT_P) & PLL0_SSCG_MD_INT_M) /* Saved value of PLL output rate, computed whenever needed to save run-time computation on each call to retrive the PLL rate. */ @@ -63,8 +63,9 @@ static uint32_t s_Pll1_Freq; /** External clock rate on the CLKIN pin in Hz. If not used, set this to 0. Otherwise, set it to the exact rate in Hz this pin is being driven at. */ -static uint32_t s_Ext_Clk_Freq = 16000000U; -static uint32_t s_I2S_Mclk_Freq = 0U; +static uint32_t s_Ext_Clk_Freq = 16000000U; +static uint32_t s_I2S_Mclk_Freq = 0U; +static uint32_t s_PLU_ClkIn_Freq = 0U; /******************************************************************************* * Variables @@ -120,7 +121,7 @@ void CLOCK_AttachClk(clock_attach_id_t connection) break; } item = (uint16_t)GET_ID_ITEM(tmp32); - if (item) + if (item != 0U) { mux = GET_ID_ITEM_MUX(item); sel = GET_ID_ITEM_SEL(item); @@ -166,15 +167,15 @@ clock_attach_id_t CLOCK_GetClockAttachId(clock_attach_id_t attachId) for (i = 0U; i < 2U; i++) { mux = GET_ID_ITEM_MUX(tmp32); - if (tmp32) + if (tmp32 != 0UL) { if (mux == CM_RTCOSC32KCLKSEL) { - actualSel = PMC->RTCOSC32K; + actualSel = (uint8_t)(PMC->RTCOSC32K); } else { - actualSel = pClkSel[mux]; + actualSel = (uint8_t)(pClkSel[mux]); } /* Consider the combination of two registers */ @@ -201,17 +202,26 @@ void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool volatile uint32_t *pClkDiv; pClkDiv = &(SYSCON->SYSTICKCLKDIV0); - if (reset) + if ((div_name >= kCLOCK_DivFlexFrg0) && (div_name <= kCLOCK_DivFlexFrg7)) { - pClkDiv[div_name] = 1U << 29U; - } - if (divided_by_value == 0U) /*!< halt */ - { - pClkDiv[div_name] = 1U << 30U; + /*!< Flexcomm Interface function clock = (clock selected via FCCLKSEL) / (1+ MULT /DIV), DIV = 0xFF */ + ((volatile uint32_t *)pClkDiv)[(uint8_t)div_name] = + SYSCON_FLEXFRG0CTRL_DIV_MASK | SYSCON_FLEXFRG0CTRL_MULT(divided_by_value); } else { - pClkDiv[div_name] = (divided_by_value - 1U); + if (reset) + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 29U; + } + if (divided_by_value == 0U) /*!< halt */ + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = 1UL << 30U; + } + else + { + ((volatile uint32_t *)pClkDiv)[(uint32_t)div_name] = (divided_by_value - 1U); + } } } @@ -236,7 +246,7 @@ void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value) { if (divided_by_value == 0U) /*!< halt */ { - PMC->RTCOSC32K |= (1U << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); + PMC->RTCOSC32K |= (1UL << PMC_RTCOSC32K_CLK1HZDIVHALT_SHIFT); } else { @@ -260,7 +270,7 @@ status_t CLOCK_SetupFROClocking(uint32_t iFreq) return kStatus_Fail; } /* Enable Analog Control module */ - SYSCON->PRESETCTRLCLR[2] = (1U << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); + SYSCON->PRESETCTRLCLR[2] = (1UL << SYSCON_PRESETCTRL2_ANALOG_CTRL_RST_SHIFT); SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL_MASK; /* Power up the FRO192M */ POWER_DisablePD(kPDRUNCFG_PD_FRO192M); @@ -269,115 +279,123 @@ status_t CLOCK_SetupFROClocking(uint32_t iFreq) { ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK(1); } + /* always enable else if (iFreq == 48000000U) { ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK(1); - } + }*/ else { ANACTRL->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK(1); } - return 0U; + return kStatus_Success; } /* Set the FLASH wait states for the passed frequency */ /** - * brief Set the flash wait states for the input freuqency. - * param iFreq : Input frequency - * return Nothing + * brief Set the flash wait states for the input freuqency. + * param iFreq: Input frequency + * return Nothing */ void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq) { uint32_t num_wait_states; /* Flash Controller & FMC internal number of Wait States (minus 1) */ - if (iFreq <= 11000000) + if (iFreq <= 11000000UL) { - /* [0 - 11 MHz] */ - num_wait_states = 0; + /* [0 - 11 MHz] */ + num_wait_states = 0UL; } - else if (iFreq <= 22000000) + else if (iFreq <= 22000000UL) { - /* [11 MHz - 22 MHz] */ - num_wait_states = 1; + /* [11 MHz - 22 MHz] */ + num_wait_states = 1UL; } - else if (iFreq <= 33000000) + else if (iFreq <= 33000000UL) { - /* [22 MHz - 33 MHz] */ - num_wait_states = 2; + /* [22 MHz - 33 MHz] */ + num_wait_states = 2UL; } - else if (iFreq <= 44000000) + else if (iFreq <= 44000000UL) { - /* [33 MHz - 44 MHz] */ - num_wait_states = 3; + /* [33 MHz - 44 MHz] */ + num_wait_states = 3UL; } - else if (iFreq <= 55000000) + else if (iFreq <= 55000000UL) { - /* [44 MHz - 55 MHz] */ - num_wait_states = 4; + /* [44 MHz - 55 MHz] */ + num_wait_states = 4UL; } - else if (iFreq <= 66000000) + else if (iFreq <= 66000000UL) { - /* [55 MHz - 662 MHz] */ - num_wait_states = 5; + /* [55 MHz - 662 MHz] */ + num_wait_states = 5UL; } - else if (iFreq <= 77000000) + else if (iFreq <= 77000000UL) { - /* [66 MHz - 77 MHz] */ - num_wait_states = 6; + /* [66 MHz - 77 MHz] */ + num_wait_states = 6UL; } - else if (iFreq <= 88000000) + else if (iFreq <= 88000000UL) { - /* [77 MHz - 88 MHz] */ - num_wait_states = 7; + /* [77 MHz - 88 MHz] */ + num_wait_states = 7UL; } - else if (iFreq <= 100000000) + else if (iFreq <= 100000000UL) { - /* [88 MHz - 100 MHz] */ - num_wait_states = 8; + /* [88 MHz - 100 MHz] */ + num_wait_states = 8UL; } - else if (iFreq <= 115000000) + else if (iFreq <= 115000000UL) { - /* [100 MHz - 115 MHz] */ - num_wait_states = 9; + /* [100 MHz - 115 MHz] */ + num_wait_states = 9UL; } - else if (iFreq <= 130000000) + else if (iFreq <= 130000000UL) { - /* [115 MHz - 130 MHz] */ - num_wait_states = 10; + /* [115 MHz - 130 MHz] */ + num_wait_states = 10UL; } - else if (iFreq <= 150000000) + else if (iFreq <= 150000000UL) { - /* [130 MHz - 150 MHz] */ - num_wait_states = 11; + /* [130 MHz - 150 MHz] */ + num_wait_states = 11UL; } else { - /* Above 150 MHz */ - num_wait_states = 12; + /* Above 150 MHz */ + num_wait_states = 12UL; } - FLASH->INT_CLR_STATUS = 0x1F; /* Clear all status flags */ + FLASH->INT_CLR_STATUS = 0x1FUL; /* Clear all status flags */ - FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0) | ( num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT)); + FLASH->DATAW[0] = (FLASH->DATAW[0] & 0xFFFFFFF0UL) | + (num_wait_states & (SYSCON_FMCCR_FLASHTIM_MASK >> SYSCON_FMCCR_FLASHTIM_SHIFT)); FLASH->CMD = 0x2; /* CMD_SET_READ_MODE */ /* Wait until the cmd is completed (without error) */ - while ( !(FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK) ); + while (0UL == (FLASH->INT_STATUS & FLASH_INT_STATUS_DONE_MASK)) + { + ; + } /* Adjust FMC waiting time cycles (num_wait_states) */ - SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) | ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK); + SYSCON->FMCCR = (SYSCON->FMCCR & ~SYSCON_FMCCR_FLASHTIM_MASK) | + ((num_wait_states << SYSCON_FMCCR_FLASHTIM_SHIFT) & SYSCON_FMCCR_FLASHTIM_MASK); } /* Set EXT OSC Clk */ /** * brief Initialize the external osc clock to given frequency. + * Crystal oscillator with an operating frequency of 12 MHz to 32 MHz. + * Option for external clock input (bypass mode) for clock frequencies of up to 25 MHz. * param iFreq : Desired frequency (must be equal to exact rate in Hz) * return returns success or fail status. */ status_t CLOCK_SetupExtClocking(uint32_t iFreq) { - if (iFreq >= 32000000U) + if (iFreq > 32000000U) { return kStatus_Fail; } @@ -388,7 +406,7 @@ status_t CLOCK_SetupExtClocking(uint32_t iFreq) SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; s_Ext_Clk_Freq = iFreq; - return 0U; + return kStatus_Success; } /* Set I2S MCLK Clk */ @@ -400,7 +418,19 @@ status_t CLOCK_SetupExtClocking(uint32_t iFreq) status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq) { s_I2S_Mclk_Freq = iFreq; - return 0U; + return kStatus_Success; +} + +/* Set PLU CLKIN Clk */ +/** + * brief Initialize the PLU CLKIN clock to given frequency. + * param iFreq : Desired frequency (must be equal to exact rate in Hz) + * return returns success or fail status. + */ +status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq) +{ + s_PLU_ClkIn_Freq = iFreq; + return kStatus_Success; } /* Get CLOCK OUT Clk */ @@ -446,6 +476,7 @@ uint32_t CLOCK_GetClockOutClkFreq(void) break; default: + assert(false); break; } return freq / ((SYSCON->CLKOUTDIV & 0xffU) + 1U); @@ -475,6 +506,7 @@ uint32_t CLOCK_GetAdcClkFreq(void) break; default: + assert(false); break; } @@ -508,6 +540,7 @@ uint32_t CLOCK_GetUsb0ClkFreq(void) break; default: + assert(false); break; } @@ -520,7 +553,7 @@ uint32_t CLOCK_GetUsb0ClkFreq(void) */ uint32_t CLOCK_GetUsb1ClkFreq(void) { - return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) ? s_Ext_Clk_Freq : 0U; + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; } /* Get MCLK Clk */ @@ -544,6 +577,7 @@ uint32_t CLOCK_GetMclkClkFreq(void) break; default: + assert(false); break; } @@ -580,6 +614,7 @@ uint32_t CLOCK_GetSctClkFreq(void) break; default: + assert(false); break; } @@ -612,6 +647,7 @@ uint32_t CLOCK_GetSdioClkFreq(void) freq = 0U; break; default: + assert(false); break; } @@ -624,9 +660,7 @@ uint32_t CLOCK_GetSdioClkFreq(void) */ uint32_t CLOCK_GetFro12MFreq(void) { - return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? - 0 : - (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U; + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; } /* Get FRO 1M Clk */ @@ -635,7 +669,7 @@ uint32_t CLOCK_GetFro12MFreq(void) */ uint32_t CLOCK_GetFro1MFreq(void) { - return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U; + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; } /* Get EXT OSC Clk */ @@ -644,7 +678,7 @@ uint32_t CLOCK_GetFro1MFreq(void) */ uint32_t CLOCK_GetExtClkFreq(void) { - return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? s_Ext_Clk_Freq : 0U; + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? s_Ext_Clk_Freq : 0U; } /* Get WATCH DOG Clk */ @@ -662,9 +696,7 @@ uint32_t CLOCK_GetWdtClkFreq(void) */ uint32_t CLOCK_GetFroHfFreq(void) { - return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? - 0 : - (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U; + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; } /* Get SYSTEM PLL Clk */ @@ -691,9 +723,11 @@ uint32_t CLOCK_GetPll1OutFreq(void) */ uint32_t CLOCK_GetOsc32KFreq(void) { - return ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (!(PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && + (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? CLK_RTC_32K_CLK : - ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK)) ? + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && + (0UL != (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? CLK_RTC_32K_CLK : 0U; } @@ -727,6 +761,7 @@ uint32_t CLOCK_GetCoreSysClkFreq(void) } else { + /* Add comments to prevent the case of MISRA C-2012 rule 15.7. */ } break; case 1U: @@ -741,6 +776,7 @@ uint32_t CLOCK_GetCoreSysClkFreq(void) break; default: + freq = 0U; break; } @@ -756,6 +792,15 @@ uint32_t CLOCK_GetI2SMClkFreq(void) return s_I2S_Mclk_Freq; } +/* Get PLU CLKIN Clk */ +/*! brief Return Frequency of PLU CLKIN Clock + * return Frequency of PLU CLKIN Clock + */ +uint32_t CLOCK_GetPLUClkInFreq(void) +{ + return s_PLU_ClkIn_Freq; +} + /* Get FLEXCOMM input clock */ /*! brief Return Frequency of flexcomm input clock * param id : flexcomm instance id @@ -793,6 +838,7 @@ uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) break; default: + assert(false); break; } @@ -802,11 +848,14 @@ uint32_t CLOCK_GetFlexCommInputClock(uint32_t id) /* Get FLEXCOMM Clk */ uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id) { - uint32_t freq = 0U; + uint32_t freq = 0U; + uint32_t frgMul = 0U; + uint32_t frgDiv = 0U; - freq = CLOCK_GetFlexCommInputClock(id); - return freq / (1 + (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) / - ((SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK) + 1U)); + freq = CLOCK_GetFlexCommInputClock(id); + frgMul = (SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_MULT_MASK) >> 8U; + frgDiv = SYSCON->FLEXFRGXCTRL[id] & SYSCON_FLEXFRG0CTRL_DIV_MASK; + return (uint32_t)(((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL)); } /* Get HS_LPSI Clk */ @@ -839,6 +888,7 @@ uint32_t CLOCK_GetHsLspiClkFreq(void) break; default: + assert(false); break; } @@ -878,6 +928,7 @@ uint32_t CLOCK_GetCTimerClkFreq(uint32_t id) break; default: + assert(false); break; } @@ -897,7 +948,7 @@ uint32_t CLOCK_GetSystickClkFreq(uint32_t id) switch (SYSCON->SYSTICKCLKSELX[id]) { case 0U: - freq = CLOCK_GetCoreSysClkFreq() / ((pSystickClkDiv[id] & 0xffU) + 1U); + freq = CLOCK_GetCoreSysClkFreq() / ((((volatile uint32_t *)pSystickClkDiv)[(uint32_t)id] & 0xffU) + 1U); break; case 1U: freq = CLOCK_GetFro1MFreq(); @@ -910,6 +961,7 @@ uint32_t CLOCK_GetSystickClkFreq(uint32_t id) break; default: + freq = 0U; break; } @@ -929,16 +981,16 @@ uint32_t CLOCK_SetFlexCommClock(uint32_t id, uint32_t freq) uint32_t input = CLOCK_GetFlexCommClkFreq(id); uint32_t mul; - if ((freq > 48000000) || (freq > input) || (input / freq >= 2)) + if ((freq > 48000000UL) || (freq > input) || (input / freq >= 2UL)) { /* FRG output frequency should be less than equal to 48MHz */ - return 0; + return 0UL; } else { - mul = ((uint64_t)(input - freq) * 256) / ((uint64_t)freq); + mul = (uint32_t)((((uint64_t)input - freq) * 256ULL) / ((uint64_t)freq)); SYSCON->FLEXFRGXCTRL[id] = (mul << 8U) | 0xFFU; - return 1; + return 1UL; } } @@ -960,15 +1012,6 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) case kCLOCK_ClockOut: freq = CLOCK_GetClockOutClkFreq(); break; - case kCLOCK_Adc: - freq = CLOCK_GetAdcClkFreq(); - break; - case kCLOCK_Usb0: - freq = CLOCK_GetUsb0ClkFreq(); - break; - case kCLOCK_Usb1: - freq = CLOCK_GetUsb1ClkFreq(); - break; case kCLOCK_Pll1Out: freq = CLOCK_GetPll1OutFreq(); break; @@ -987,66 +1030,9 @@ uint32_t CLOCK_GetFreq(clock_name_t clockName) case kCLOCK_Pll0Out: freq = CLOCK_GetPll0OutFreq(); break; - case kCLOCK_WdtClk: - freq = CLOCK_GetWdtClkFreq(); - break; - case kCLOCK_Sct: - freq = CLOCK_GetSctClkFreq(); - break; - case kCLOCK_SDio: - freq = CLOCK_GetSdioClkFreq(); - break; case kCLOCK_FlexI2S: freq = CLOCK_GetI2SMClkFreq(); break; - case kCLOCK_Flexcomm0: - freq = CLOCK_GetFlexCommClkFreq(0U); - break; - case kCLOCK_Flexcomm1: - freq = CLOCK_GetFlexCommClkFreq(1U); - break; - case kCLOCK_Flexcomm2: - freq = CLOCK_GetFlexCommClkFreq(2U); - break; - case kCLOCK_Flexcomm3: - freq = CLOCK_GetFlexCommClkFreq(3U); - break; - case kCLOCK_Flexcomm4: - freq = CLOCK_GetFlexCommClkFreq(4U); - break; - case kCLOCK_Flexcomm5: - freq = CLOCK_GetFlexCommClkFreq(5U); - break; - case kCLOCK_Flexcomm6: - freq = CLOCK_GetFlexCommClkFreq(6U); - break; - case kCLOCK_Flexcomm7: - freq = CLOCK_GetFlexCommClkFreq(7U); - break; - case kCLOCK_HsLspi: - freq = CLOCK_GetHsLspiClkFreq(); - break; - case kCLOCK_CTimer0: - freq = CLOCK_GetCTimerClkFreq(0U); - break; - case kCLOCK_CTimer1: - freq = CLOCK_GetCTimerClkFreq(1U); - break; - case kCLOCK_CTimer2: - freq = CLOCK_GetCTimerClkFreq(2U); - break; - case kCLOCK_CTimer3: - freq = CLOCK_GetCTimerClkFreq(3U); - break; - case kCLOCK_CTimer4: - freq = CLOCK_GetCTimerClkFreq(4U); - break; - case kCLOCK_Systick0: - freq = CLOCK_GetSystickClkFreq(0U); - break; - case kCLOCK_Systick1: - freq = CLOCK_GetSystickClkFreq(1U); - break; default: freq = 0U; break; @@ -1059,7 +1045,7 @@ static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *p { uint32_t seli, selp; /* bandwidth: compute selP from Multiplier */ - if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ { selp = (M >> 2U) + 1U; if (selp >= 31U) @@ -1068,34 +1054,22 @@ static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *p } *pSelP = selp; - if (M >= 32768) + if (M >= 8000UL) { - seli = 1; + seli = 1UL; } - else if (M >= 16384) + else if (M >= 122UL) { - seli = 2; - } - else if (M >= 4096) - { - seli = 4; - } - else if (M >= 1002) - { - seli = 8; - } - else if (M >= 120) - { - seli = 4 * ((1024 / (M / 2 + 9)) + 1); + seli = (uint32_t)(8000UL / M); /*floor(8000/M) */ } else { - seli = 4 * (M / 8 + 1); + seli = 2UL * ((uint32_t)(M / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ } - if (seli >= 63) + if (seli >= 63UL) { - seli = 63; + seli = 63UL; } *pSelI = seli; @@ -1103,6 +1077,7 @@ static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *p } else { + /* Note: If the spread spectrum mode, choose N to ensure 3 MHz < Fin/N < 5 MHz */ *pSelP = 3U; *pSelI = 4U; *pSelR = 4U; @@ -1112,15 +1087,15 @@ static void pllFindSel(uint32_t M, uint32_t *pSelP, uint32_t *pSelI, uint32_t *p /* Get predivider (N) from PLL0 NDEC setting */ static uint32_t findPll0PreDiv(void) { - uint32_t preDiv = 1; + uint32_t preDiv = 1UL; /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0) + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) { preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0) + if (preDiv == 0UL) { - preDiv = 1; + preDiv = 1UL; } } return preDiv; @@ -1129,15 +1104,15 @@ static uint32_t findPll0PreDiv(void) /* Get predivider (N) from PLL1 NDEC setting */ static uint32_t findPll1PreDiv(void) { - uint32_t preDiv = 1; + uint32_t preDiv = 1UL; /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0) + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) { preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0) + if (preDiv == 0UL) { - preDiv = 1; + preDiv = 1UL; } } return preDiv; @@ -1146,21 +1121,21 @@ static uint32_t findPll1PreDiv(void) /* Get postdivider (P) from PLL0 PDEC setting */ static uint32_t findPll0PostDiv(void) { - uint32_t postDiv = 1; + uint32_t postDiv = 1UL; - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0) + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) { - if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) { postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; } else { - postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); } - if (postDiv == 0) + if (postDiv == 0UL) { - postDiv = 2; + postDiv = 2UL; } } return postDiv; @@ -1169,24 +1144,26 @@ static uint32_t findPll0PostDiv(void) /* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ static float findPll0MMult(void) { - float mMult = 1; + float mMult = 1.0F; float mMult_fract; uint32_t mMult_int; - if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) { - mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT; + mMult = + (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); } else { - mMult_int = - ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); - mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / (1 << PLL0_SSCG_MD_INT_P)); + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL0_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL0_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL0_SSCG_MD_INT_P)); mMult = (float)mMult_int + mMult_fract; } - if (mMult == 0) + if(0ULL == ((uint64_t)mMult)) { - mMult = 1; + mMult = 1.0F; } return mMult; } @@ -1330,24 +1307,27 @@ static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, uplimoff = 0U; /* Get encoded value for M (mult) and use manual filter, disable SS mode */ - pSetup->pllsscg[1] = (PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1U << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT); + pSetup->pllsscg[1] = + (uint32_t)((PLL_SSCG1_MDEC_VAL_SET(pllMultiplier)) | (1UL << SYSCON_PLL0SSCG1_SEL_EXT_SHIFT)); } else { uint64_t fc; /* Filtering will be handled by SSC */ - pllSelR = pllSelI = pllSelP = 0U; - uplimoff = 1U; + pllSelR = 0U; + pllSelI = 0U; + pllSelP = 0U; + uplimoff = 1U; /* The PLL multiplier will get very close and slightly under the desired target frequency. A small fractional component can be added to fine tune the frequency upwards to the target. */ - fc = ((uint64_t)(fccoHz % nDivOutHz) << 25U) / nDivOutHz; + fc = (((uint64_t)fccoHz % (uint64_t)nDivOutHz) << 25U) / nDivOutHz; /* Set multiplier */ pSetup->pllsscg[0] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) | PLL0_SSCG_MD_FRACT_SET((uint32_t)fc)); - pSetup->pllsscg[1] = PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U; + pSetup->pllsscg[1] = (uint32_t)(PLL0_SSCG_MD_INT_SET(pllMultiplier) >> 32U); } /* Get encoded values for N (prediv) and P (postdiv) */ @@ -1358,11 +1338,11 @@ static pll_error_t CLOCK_GetPll0ConfigInternal(uint32_t finHz, uint32_t foutHz, pSetup->pllctrl = (pllSelR << SYSCON_PLL0CTRL_SELR_SHIFT) | /* Filter coefficient */ (pllSelI << SYSCON_PLL0CTRL_SELI_SHIFT) | /* Filter coefficient */ (pllSelP << SYSCON_PLL0CTRL_SELP_SHIFT) | /* Filter coefficient */ - (0 << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ + (0UL << SYSCON_PLL0CTRL_BYPASSPLL_SHIFT) | /* PLL bypass mode disabled */ (uplimoff << SYSCON_PLL0CTRL_LIMUPOFF_SHIFT) | /* SS/fractional mode disabled */ (pllDirectInput << SYSCON_PLL0CTRL_BYPASSPREDIV_SHIFT) | /* Bypass pre-divider? */ (pllDirectOutput << SYSCON_PLL0CTRL_BYPASSPOSTDIV_SHIFT) | /* Bypass post-divider? */ - (1 << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ + (1UL << SYSCON_PLL0CTRL_CLKEN_SHIFT); /* Ensure the PLL clock output */ return kStatus_PLL_Success; } @@ -1506,14 +1486,15 @@ uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) { uint32_t clkRate = 0; uint32_t prediv, postdiv; - float workRate = 0; + float workRate = 0.0F; /* Get the input clock frequency of PLL. */ clkRate = CLOCK_GetPLL0InClockRate(); - if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && - ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0)) + if (((pSetup->pllctrl & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && + ((pSetup->pllctrl & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && + ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) { prediv = findPll0PreDiv(); postdiv = findPll0PostDiv(); @@ -1521,7 +1502,7 @@ uint32_t CLOCK_GetPLL0OutFromSetup(pll_setup_t *pSetup) clkRate = clkRate / prediv; /* MDEC used for rate */ workRate = (float)clkRate * (float)findPll0MMult(); - clkRate = (uint32_t)(workRate / ((float)postdiv)); + workRate /= (float)postdiv; } return (uint32_t)workRate; @@ -1577,7 +1558,7 @@ uint32_t CLOCK_GetPLL0OutClockRate(bool recompute) pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) { uint32_t inRate; - bool useSS = (bool)((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); + bool useSS = ((pControl->flags & PLL_CONFIGFLAG_FORCENOFRACT) == 0U); pll_error_t pllError; @@ -1599,7 +1580,7 @@ pll_error_t CLOCK_SetupPLL0Data(pll_config_t *pControl, pll_setup_t *pSetup) pSetup->pllsscg[1] |= (uint32_t)pControl->ss_mf | (uint32_t)pControl->ss_mr | (uint32_t)pControl->ss_mc; if (pControl->mfDither) { - pSetup->pllsscg[1] |= (1U << SYSCON_PLL0SSCG1_DITHER_SHIFT); + pSetup->pllsscg[1] |= (1UL << SYSCON_PLL0SSCG1_DITHER_SHIFT); } } @@ -1630,29 +1611,44 @@ pll_error_t CLOCK_SetupPLL0Prec(pll_setup_t *pSetup, uint32_t flagcfg) /* Write PLL setup data */ SYSCON->PLL0CTRL = pSetup->pllctrl; SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT); /* latch */ POWER_DisablePD(kPDRUNCFG_PD_PLL0); POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000) && (clkRate <= 20000000)) + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ { - while (CLOCK_IsPLL0Locked() == false) + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) { + while (CLOCK_IsPLL0Locked() == false) + { + } } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ } } @@ -1689,29 +1685,44 @@ pll_error_t CLOCK_SetPLL0Freq(const pll_setup_t *pSetup) /* Write PLL setup data */ SYSCON->PLL0CTRL = pSetup->pllctrl; SYSCON->PLL0NDEC = pSetup->pllndec; - SYSCON->PLL0NDEC = pSetup->pllndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL0NDEC = pSetup->pllndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* latch */ SYSCON->PLL0PDEC = pSetup->pllpdec; - SYSCON->PLL0PDEC = pSetup->pllpdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL0PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* latch */ SYSCON->PLL0SSCG0 = pSetup->pllsscg[0]; SYSCON->PLL0SSCG1 = pSetup->pllsscg[1]; SYSCON->PLL0SSCG1 = - pSetup->pllsscg[1] | (1U << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ + pSetup->pllsscg[1] | (1UL << SYSCON_PLL0SSCG1_MD_REQ_SHIFT) | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* latch */ POWER_DisablePD(kPDRUNCFG_PD_PLL0); POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U) { - inRate = CLOCK_GetPLL0InClockRate(); - prediv = findPll0PreDiv(); - /* Adjust input clock */ - clkRate = inRate / prediv; - /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000) && (clkRate <= 20000000)) + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) != 0UL) /* normal mode */ { - while (CLOCK_IsPLL0Locked() == false) + inRate = CLOCK_GetPLL0InClockRate(); + prediv = findPll0PreDiv(); + /* Adjust input clock */ + clkRate = inRate / prediv; + /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) { + while (CLOCK_IsPLL0Locked() == false) + { + } } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval + to insure the PLL will be stable */ + } + } + else /* spread spectrum mode */ + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ } } @@ -1741,11 +1752,11 @@ pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) /* Write PLL setup data */ SYSCON->PLL1CTRL = pSetup->pllctrl; SYSCON->PLL1NDEC = pSetup->pllndec; - SYSCON->PLL1NDEC = pSetup->pllndec | (1U << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ + SYSCON->PLL1NDEC = pSetup->pllndec | (1UL << SYSCON_PLL1NDEC_NREQ_SHIFT); /* latch */ SYSCON->PLL1PDEC = pSetup->pllpdec; - SYSCON->PLL1PDEC = pSetup->pllpdec | (1U << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ + SYSCON->PLL1PDEC = pSetup->pllpdec | (1UL << SYSCON_PLL1PDEC_PREQ_SHIFT); /* latch */ SYSCON->PLL1MDEC = pSetup->pllmdec; - SYSCON->PLL1MDEC = pSetup->pllmdec | (1U << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ + SYSCON->PLL1MDEC = pSetup->pllmdec | (1UL << SYSCON_PLL1MDEC_MREQ_SHIFT); /* latch */ POWER_DisablePD(kPDRUNCFG_PD_PLL1); @@ -1756,16 +1767,22 @@ pll_error_t CLOCK_SetPLL1Freq(const pll_setup_t *pSetup) /* Adjust input clock */ clkRate = inRate / prediv; /* The lock signal is only reliable between fref[2] :100 kHz to 20 MHz. */ - if ((clkRate >= 100000) && (clkRate <= 20000000)) + if ((clkRate >= 100000UL) && (clkRate <= 20000000UL)) { while (CLOCK_IsPLL1Locked() == false) { } } + else + { + SDK_DelayAtLeastUs(6000U, + SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* software should use a 6 ms time interval to + insure the PLL will be stable */ + } } /* Update current programmed PLL rate var */ - s_Pll0_Freq = pSetup->pllRate; + s_Pll1_Freq = pSetup->pllRate; return kStatus_PLL_Success; } @@ -1800,36 +1817,24 @@ void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) selr = 0U; - if (multiply_by >= 32768) + if (multiply_by >= 8000UL) { - seli = 1; + seli = 1UL; } - else if (multiply_by >= 16384) + else if (multiply_by >= 122UL) { - seli = 2; - } - else if (multiply_by >= 4096) - { - seli = 4; - } - else if (multiply_by >= 1002) - { - seli = 8; - } - else if (multiply_by >= 120) - { - seli = 4 * ((1024 / (multiply_by / 2 + 9)) + 1); + seli = (uint32_t)(8000UL / multiply_by); /*floor(8000/M) */ } else { - seli = 4 * (multiply_by / 8 + 1); + seli = 2UL * ((uint32_t)(multiply_by / 4UL)) + 3UL; /* 2*floor(M/4) + 3 */ } if (seli >= 63U) { seli = 63U; } - selp = (multiply_by >> 2U) + 1U; + { selp = 31U; } @@ -1840,16 +1845,16 @@ void CLOCK_SetupPLL0Mult(uint32_t multiply_by, uint32_t input_freq) /* Translate P value */ } - mdec = PLL_SSCG1_MDEC_VAL_SET(multiply_by); + mdec = (uint32_t)PLL_SSCG1_MDEC_VAL_SET(multiply_by); ndec = 0x1U; /* pre divide by 1 (hardcoded) */ SYSCON->PLL0CTRL = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_BYPASSPOSTDIV(0) | SYSCON_PLL0CTRL_BYPASSPOSTDIV2(0) | (selr << SYSCON_PLL0CTRL_SELR_SHIFT) | (seli << SYSCON_PLL0CTRL_SELI_SHIFT) | (selp << SYSCON_PLL0CTRL_SELP_SHIFT); - SYSCON->PLL0PDEC = pdec | (1U << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ - SYSCON->PLL0NDEC = ndec | (1U << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0PDEC = pdec | (1UL << SYSCON_PLL0PDEC_PREQ_SHIFT); /* set Pdec value and assert preq */ + SYSCON->PLL0NDEC = ndec | (1UL << SYSCON_PLL0NDEC_NREQ_SHIFT); /* set Pdec value and assert preq */ SYSCON->PLL0SSCG1 = - mdec | (1U << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ + mdec | (1UL << SYSCON_PLL0SSCG1_MREQ_SHIFT); /* select non sscg MDEC value, assert mreq and select mdec value */ } /* Enable USB DEVICE FULL SPEED clock */ @@ -1879,39 +1884,35 @@ bool CLOCK_EnableUsbfs0DeviceClock(clock_usbfs_src_t src, uint32_t freq) /* Turn ON FRO HF */ POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /* Enable FRO 96MHz output */ - ANACTRL->FRO192M_CTRL = ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK; + ANACTRL->FRO192M_CTRL = + ANACTRL->FRO192M_CTRL | ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK | ANACTRL_FRO192M_CTRL_USBCLKADJ_MASK; /* Select FRO 96 or 48 MHz */ CLOCK_AttachClk(kFRO_HF_to_USB0_CLK); } else { - /*Set the USB PLL as the Usb0 CLK*/ + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ POWER_DisablePD(kPDRUNCFG_PD_PLL1); - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; - - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */ - + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U), + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(4U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(24U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK, - }; - - CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); CLOCK_AttachClk(kPLL1_to_USB0_CLK); - uint32_t delay = 100000; - while (delay--) - { - __asm("nop"); - } + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); } CLOCK_EnableClock(kCLOCK_Usbd0); CLOCK_EnableClock(kCLOCK_UsbRam1); @@ -1953,33 +1954,28 @@ bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) } else { - /*Set the USB PLL as the Usb0 CLK*/ + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + (void)CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + /*!< Set up PLL1 */ POWER_DisablePD(kPDRUNCFG_PD_PLL1); - POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /*!< Ensure XTAL32K is on */ - POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /*!< Ensure XTAL32K is on */ - SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /*!< Ensure CLK_IN is on */ - ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; - - CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL0 clock source selector to XTAL16M */ - + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ const pll_setup_t pll1Setup = { - .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(16U) | SYSCON_PLL1CTRL_SELP(7U), + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(19U) | SYSCON_PLL1CTRL_SELP(9U), .pllndec = SYSCON_PLL1NDEC_NDIV(1U), - .pllpdec = SYSCON_PLL1PDEC_PDIV(4U), - .pllmdec = SYSCON_PLL1MDEC_MDIV(24U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(5U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(30U), .pllRate = 48000000U, - .flags = PLL_SETUPFLAG_WAITLOCK, - }; - - CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + .flags = PLL_SETUPFLAG_WAITLOCK}; + (void)CLOCK_SetPLL1Freq(&pll1Setup); CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); CLOCK_AttachClk(kPLL1_to_USB0_CLK); - uint32_t delay = 100000; - while (delay--) - { - __asm("nop"); - } + SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); } CLOCK_EnableClock(kCLOCK_Usbhmr0); CLOCK_EnableClock(kCLOCK_Usbhsl0); @@ -1992,6 +1988,9 @@ bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq) bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) { volatile uint32_t i; + uint32_t phyPllDiv = 0U; + uint16_t multiplier = 0U; + bool ret = true; POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); @@ -2001,28 +2000,76 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) POWER_DisablePD(kPDRUNCFG_PD_LDOUSBHS); /*!< Ensure xtal32k is on */ /* wait to make sure PHY power is fully up */ - i = 100000; - while (i--) + i = 100000U; + while ((i--) != 0U) { - __asm("nop"); + __ASM("nop"); } SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_ANALOG_CTRL(1); SYSCON->AHBCLKCTRLSET[2] = SYSCON_AHBCLKCTRL2_USB1_PHY(1); - USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; - USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | USBPHY_PLL_SIC_PLL_DIV_SEL(0x06); - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; - USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK; - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; - USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; - USBPHY->PLL_SIC_SET = - USBPHY_PLL_SIC_SET_MISC2_CONTROL0_MASK; /* enables auto power down of PHY PLL during suspend */ + USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; - USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; - USBPHY->PWD_SET = 0x0; + multiplier = (uint16_t)(480000000UL / freq); - return true; + switch (multiplier) + { + case 15U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U); + break; + } + case 16U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U); + break; + } + case 20U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U); + break; + } + case 24U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U); + break; + } + case 25U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U); + break; + } + case 30U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U); + break; + } + case 40U: + { + phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U); + break; + } + default: + { + ret = false; + break; + } + } + + if (ret) + { + USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~USBPHY_PLL_SIC_PLL_DIV_SEL(0x7)) | phyPllDiv; + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK; + USBPHY->PLL_SIC_CLR = (1UL << 16U); // Reserved. User must set this bit to 0x0 + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_POWER_MASK; + USBPHY->PLL_SIC_SET = USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK; + + USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; + USBPHY->PWD_SET = 0x0; + } + + return ret; } /* Enable USB DEVICE HIGH SPEED clock */ @@ -2050,50 +2097,10 @@ bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq) return true; } -/*! - * brief Use DWT to delay at least for some time. - * Please note that, this API will calculate the microsecond period with the maximum devices - * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise - * delay count was needed, please implement a new timer count to achieve this function. - * - * param delay_us Delay time in unit of microsecond. +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing */ -__attribute__((weak)) void SDK_DelayAtLeastUs(uint32_t delay_us) +void CLOCK_EnableOstimer32kClock(void) { - assert(0U != delay_us); - uint64_t count = 0U; - uint32_t period = SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY / 1000000; - - /* Make sure the DWT trace fucntion is enabled. */ - if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) - { - CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; - } - - /* CYCCNT not supported on this device. */ - assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); - - /* If CYCCENT has already been enabled, read directly, otherwise, need enable it. */ - if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) - { - DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; - } - - /* Calculate the count ticks. */ - count = DWT->CYCCNT; - count += (uint64_t)period * delay_us; - - if (count > 0xFFFFFFFFUL) - { - count -= 0xFFFFFFFFUL; - /* wait for cyccnt overflow. */ - while (count < DWT->CYCCNT) - { - } - } - - /* Wait for cyccnt reach count value. */ - while (count > DWT->CYCCNT) - { - } + PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK; } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.h index 95799bcabb..8ad899be1f 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2017 - 2019 , NXP + * Copyright 2017 - 2021 , NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CLOCK driver version 2.1.0. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @brief CLOCK driver version 2.3.6. */ +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 6)) /*@}*/ /*! @brief Configure whether driver controls clock @@ -52,7 +52,7 @@ /* Definition for delay API in clock driver, users can redefine it to the real application. */ #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY -#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (100000000UL) +#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (150000000UL) #endif /*! @brief Clock ip name array for ROM. */ @@ -76,9 +76,9 @@ kCLOCK_Fmc \ } /*! @brief Clock ip name array for INPUTMUX. */ -#define INPUTMUX_CLOCKS \ - { \ - kCLOCK_InputMux0, kCLOCK_InputMux1 \ +#define INPUTMUX_CLOCKS \ + { \ + kCLOCK_InputMux0 \ } /*! @brief Clock ip name array for IOCON. */ #define IOCON_CLOCKS \ @@ -86,9 +86,9 @@ kCLOCK_Iocon \ } /*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \ +#define GPIO_CLOCKS \ + { \ + kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3 \ } /*! @brief Clock ip name array for PINT. */ #define PINT_CLOCKS \ @@ -145,11 +145,6 @@ { \ kCLOCK_Sct0 \ } -/*! @brief Clock ip name array for SCTIPU. */ -#define SCTIPU_CLOCKS \ - { \ - kCLOCK_Sctipu \ - } /*! @brief Clock ip name array for UTICK. */ #define UTICK_CLOCKS \ { \ @@ -184,31 +179,11 @@ kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \ kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \ } -/*! @brief Clock ip name array for USBTYPC. */ -#define USBTYPC_CLOCKS \ - { \ - kCLOCK_UsbTypc \ - } /*! @brief Clock ip name array for CTIMER. */ #define CTIMER_CLOCKS \ { \ kCLOCK_Timer0, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \ } -/*! @brief Clock ip name array for PVT */ -#define PVT_CLOCKS \ - { \ - kCLOCK_Pvt \ - } -/*! @brief Clock ip name array for EZHA */ -#define EZHA_CLOCKS \ - { \ - kCLOCK_Ezha \ - } -/*! @brief Clock ip name array for EZHB */ -#define EZHB_CLOCKS \ - { \ - kCLOCK_Ezhb \ - } /*! @brief Clock ip name array for COMP */ #define COMP_CLOCKS \ { \ @@ -234,11 +209,6 @@ { \ kCLOCK_UsbRam1 \ } -/*! @brief Clock ip name array for OTP. */ -#define OTP_CLOCKS \ - { \ - kCLOCK_Otp \ - } /*! @brief Clock ip name array for RNG. */ #define RNG_CLOCKS \ { \ @@ -323,9 +293,9 @@ ------------------------------------------------------------------------------*/ #define CLK_GATE_REG_OFFSET_SHIFT 8U -#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U -#define CLK_GATE_BIT_SHIFT_SHIFT 0U -#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU +#define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U +#define CLK_GATE_BIT_SHIFT_SHIFT 0U +#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU #define CLK_GATE_DEFINE(reg_offset, bit_shift) \ ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \ @@ -341,108 +311,198 @@ /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */ typedef enum _clock_ip_name { - kCLOCK_IpInvalid = 0U, - kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), - kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), - kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), - kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), - kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), - kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), - kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), - kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), - kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), - kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), - kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), - kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), - kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), - kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), - kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), - kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), - kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), - kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), - kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), - kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), - kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), - kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), - kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), - kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), - kCLOCK_Sctipu = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6), - kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), - kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), - kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), - kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), - kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), - kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), - kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), - kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), - kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), - kCLOCK_UsbTypc = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 20), - kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), - kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), - kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), - kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), - kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), - kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), - kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), - kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), - kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), - kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), - kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), - kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), - kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), - kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), - kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), - kCLOCK_Gpio4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 9), - kCLOCK_Gpio5 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 10), - kCLOCK_Otp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 12), - kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), - kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), - kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), - kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), - kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), - kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), - kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), - kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), - kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), - kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), - kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), - kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), - kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), - kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), - kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), - kCLOCK_Gpio_sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) + kCLOCK_IpInvalid = 0U, /*!< Invalid Ip Name. */ + kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1), /*!< Clock gate name: Rom. */ + + kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3), /*!< Clock gate name: Sram1. */ + + kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4), /*!< Clock gate name: Sram2. */ + + kCLOCK_Sram3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 5), /*!< Clock gate name: Sram3. */ + + kCLOCK_Sram4 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6), /*!< Clock gate name: Sram4. */ + + kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7), /*!< Clock gate name: Flash. */ + + kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8), /*!< Clock gate name: Fmc. */ + + kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11), /*!< Clock gate name: InputMux. */ + + kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13), /*!< Clock gate name: Iocon. */ + + kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14), /*!< Clock gate name: Gpio0. */ + + kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15), /*!< Clock gate name: Gpio1. */ + + kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16), /*!< Clock gate name: Gpio2. */ + + kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17), /*!< Clock gate name: Gpio3. */ + + kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18), /*!< Clock gate name: Pint. */ + + kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /*!< Clock gate name: Gint. */ + + kCLOCK_Dma0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20), /*!< Clock gate name: Dma0. */ + + kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21), /*!< Clock gate name: Crc. */ + + kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22), /*!< Clock gate name: Wwdt. */ + + kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23), /*!< Clock gate name: Rtc. */ + + kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26), /*!< Clock gate name: Mailbox. */ + + kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27), /*!< Clock gate name: Adc0. */ + + kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0), /*!< Clock gate name: Mrt. */ + + kCLOCK_OsTimer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 1), /*!< Clock gate name: OsTimer0. */ + + kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2), /*!< Clock gate name: Sct0. */ + + kCLOCK_Utick0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10), /*!< Clock gate name: Utick0. */ + + kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexComm0. */ + + kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexComm1. */ + + kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexComm2. */ + + kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexComm3. */ + + kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexComm4. */ + + kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexComm5. */ + + kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexComm6. */ + + kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexComm7. */ + + kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: MinUart0. */ + + kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: MinUart1. */ + + kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: MinUart2. */ + + kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: MinUart3. */ + + kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: MinUart4. */ + + kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: MinUart5. */ + + kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: MinUart6. */ + + kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: MinUart7. */ + + kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: LSpi0. */ + + kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: LSpi1. */ + + kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: LSpi2. */ + + kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: LSpi3. */ + + kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: LSpi4. */ + + kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: LSpi5. */ + + kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: LSpi6. */ + + kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: LSpi7. */ + + kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: BI2c0. */ + + kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: BI2c1. */ + + kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: BI2c2. */ + + kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: BI2c3. */ + + kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: BI2c4. */ + + kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: BI2c5. */ + + kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: BI2c6. */ + + kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: BI2c7. */ + + kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11), /*!< Clock gate name: FlexI2s0. */ + + kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12), /*!< Clock gate name: FlexI2s1. */ + + kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13), /*!< Clock gate name: FlexI2s2. */ + + kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14), /*!< Clock gate name: FlexI2s3. */ + + kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15), /*!< Clock gate name: FlexI2s4. */ + + kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16), /*!< Clock gate name: FlexI2s5. */ + + kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17), /*!< Clock gate name: FlexI2s6. */ + + kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18), /*!< Clock gate name: FlexI2s7. */ + + kCLOCK_Timer2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22), /*!< Clock gate name: Timer2. */ + + kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25), /*!< Clock gate name: Usbd0. */ + + kCLOCK_Timer0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26), /*!< Clock gate name: Timer0. */ + + kCLOCK_Timer1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27), /*!< Clock gate name: Timer1. */ + + kCLOCK_Pvt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28), /*!< Clock gate name: Pvt. */ + + kCLOCK_Ezha = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 30), /*!< Clock gate name: Ezha. */ + + kCLOCK_Ezhb = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31), /*!< Clock gate name: Ezhb. */ + + kCLOCK_Dma1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 1), /*!< Clock gate name: Dma1. */ + + kCLOCK_Comp = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 2), /*!< Clock gate name: Comp. */ + + kCLOCK_Sdio = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 3), /*!< Clock gate name: Sdio. */ + + kCLOCK_Usbh1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 4), /*!< Clock gate name: Usbh1. */ + + kCLOCK_Usbd1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 5), /*!< Clock gate name: Usbd1. */ + + kCLOCK_UsbRam1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 6), /*!< Clock gate name: UsbRam1. */ + + kCLOCK_Usb1Clk = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 7), /*!< Clock gate name: Usb1Clk. */ + + kCLOCK_Freqme = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 8), /*!< Clock gate name: Freqme. */ + + kCLOCK_Rng = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 13), /*!< Clock gate name: Rng. */ + + kCLOCK_InputMux1 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 14), /*!< Clock gate name: InputMux1. */ + + kCLOCK_Sysctl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 15), /*!< Clock gate name: Sysctl. */ + + kCLOCK_Usbhmr0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 16), /*!< Clock gate name: Usbhmr0. */ + + kCLOCK_Usbhsl0 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 17), /*!< Clock gate name: Usbhsl0. */ + + kCLOCK_HashCrypt = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 18), /*!< Clock gate name: HashCrypt. */ + + kCLOCK_PowerQuad = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 19), /*!< Clock gate name: PowerQuad. */ + + kCLOCK_PluLut = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 20), /*!< Clock gate name: PluLut. */ + + kCLOCK_Timer3 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 21), /*!< Clock gate name: Timer3. */ + + kCLOCK_Timer4 = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 22), /*!< Clock gate name: Timer4. */ + + kCLOCK_Puf = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 23), /*!< Clock gate name: Puf. */ + + kCLOCK_Casper = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 24), /*!< Clock gate name: Casper. */ + + kCLOCK_AnalogCtrl = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 27), /*!< Clock gate name: AnalogCtrl. */ + + kCLOCK_Hs_Lspi = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 28), /*!< Clock gate name: Lspi. */ + + kCLOCK_Gpio_Sec = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 29), /*!< Clock gate name: GPIO Sec. */ + + kCLOCK_Gpio_Sec_Int = CLK_GATE_DEFINE(AHB_CLK_CTRL2, 30) /*!< Clock gate name: GPIO SEC Int. */ } clock_ip_name_t; /*! @brief Peripherals clock source definition. */ @@ -457,34 +517,12 @@ typedef enum _clock_name kCLOCK_BusClk, /*!< Bus clock (AHB clock) */ kCLOCK_ClockOut, /*!< CLOCKOUT */ kCLOCK_FroHf, /*!< FRO48/96 */ - kCLOCK_Adc, /*!< ADC */ - kCLOCK_Usb0, /*!< USB0 */ - kCLOCK_Usb1, /*!< USB1 */ kCLOCK_Pll1Out, /*!< PLL1 Output */ kCLOCK_Mclk, /*!< MCLK */ - kCLOCK_Sct, /*!< SCT */ - kCLOCK_SDio, /*!< SDIO */ kCLOCK_Fro12M, /*!< FRO12M */ kCLOCK_ExtClk, /*!< External Clock */ kCLOCK_Pll0Out, /*!< PLL0 Output */ - kCLOCK_WdtClk, /*!< Watchdog clock */ kCLOCK_FlexI2S, /*!< FlexI2S clock */ - kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */ - kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */ - kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */ - kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */ - kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */ - kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */ - kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */ - kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */ - kCLOCK_HsLspi, /*!< HS LPSPI Clock */ - kCLOCK_CTimer0, /*!< CTimer0Clock */ - kCLOCK_CTimer1, /*!< CTimer1Clock */ - kCLOCK_CTimer2, /*!< CTimer2Clock */ - kCLOCK_CTimer3, /*!< CTimer3Clock */ - kCLOCK_CTimer4, /*!< CTimer4Clock */ - kCLOCK_Systick0, /*!< System Tick 0 Clock */ - kCLOCK_Systick1, /*!< System Tick 1 Clock */ } clock_name_t; @@ -496,273 +534,437 @@ typedef enum _clock_name * */ -#define CLK_ATTACH_ID(mux, sel, pos) (((mux << 0U) | ((sel + 1) & 0xFU) << 8U) << (pos * 12U)) -#define MUX_A(mux, sel) CLK_ATTACH_ID(mux, sel, 0U) -#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID(mux, sel, 1U) | (selector << 24U)) +#define CLK_ATTACH_ID(mux, sel, pos) \ + ((((uint32_t)(mux) << 0U) | (((uint32_t)(sel) + 1U) & 0xFU) << 8U) << ((uint32_t)(pos)*12U)) +#define MUX_A(mux, sel) CLK_ATTACH_ID((mux), (sel), 0U) +#define MUX_B(mux, sel, selector) (CLK_ATTACH_ID((mux), (sel), 1U) | ((selector) << 24U)) -#define GET_ID_ITEM(connection) ((connection)&0xFFFU) +#define GET_ID_ITEM(connection) ((connection)&0xFFFU) #define GET_ID_NEXT_ITEM(connection) ((connection) >> 12U) -#define GET_ID_ITEM_MUX(connection) ((connection)&0xFFU) -#define GET_ID_ITEM_SEL(connection) ((((connection)&0xF00U) >> 8U) - 1U) -#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) +#define GET_ID_ITEM_MUX(connection) (((uint8_t)connection) & 0xFFU) +#define GET_ID_ITEM_SEL(connection) ((uint8_t)((((uint32_t)(connection)&0xF00U) >> 8U) - 1U)) +#define GET_ID_SELECTOR(connection) ((connection)&0xF000000U) -#define CM_SYSTICKCLKSEL0 0 -#define CM_SYSTICKCLKSEL1 1 -#define CM_TRACECLKSEL 2 -#define CM_CTIMERCLKSEL0 3 -#define CM_CTIMERCLKSEL1 4 -#define CM_CTIMERCLKSEL2 5 -#define CM_CTIMERCLKSEL3 6 -#define CM_CTIMERCLKSEL4 7 -#define CM_MAINCLKSELA 8 -#define CM_MAINCLKSELB 9 -#define CM_CLKOUTCLKSEL 10 -#define CM_PLL0CLKSEL 12 -#define CM_PLL1CLKSEL 13 -#define CM_ADCASYNCCLKSEL 17 -#define CM_USB0CLKSEL 18 -#define CM_FXCOMCLKSEL0 20 -#define CM_FXCOMCLKSEL1 21 -#define CM_FXCOMCLKSEL2 22 -#define CM_FXCOMCLKSEL3 23 -#define CM_FXCOMCLKSEL4 24 -#define CM_FXCOMCLKSEL5 25 -#define CM_FXCOMCLKSEL6 26 -#define CM_FXCOMCLKSEL7 27 -#define CM_HSLSPICLKSEL 28 -#define CM_MCLKCLKSEL 32 -#define CM_SCTCLKSEL 36 -#define CM_SDIOCLKSEL 38 +#define CM_SYSTICKCLKSEL0 0U +#define CM_SYSTICKCLKSEL1 1U +#define CM_TRACECLKSEL 2U +#define CM_CTIMERCLKSEL0 3U +#define CM_CTIMERCLKSEL1 4U +#define CM_CTIMERCLKSEL2 5U +#define CM_CTIMERCLKSEL3 6U +#define CM_CTIMERCLKSEL4 7U +#define CM_MAINCLKSELA 8U +#define CM_MAINCLKSELB 9U +#define CM_CLKOUTCLKSEL 10U +#define CM_PLL0CLKSEL 12U +#define CM_PLL1CLKSEL 13U +#define CM_ADCASYNCCLKSEL 17U +#define CM_USB0CLKSEL 18U +#define CM_FXCOMCLKSEL0 20U +#define CM_FXCOMCLKSEL1 21U +#define CM_FXCOMCLKSEL2 22U +#define CM_FXCOMCLKSEL3 23U +#define CM_FXCOMCLKSEL4 24U +#define CM_FXCOMCLKSEL5 25U +#define CM_FXCOMCLKSEL6 26U +#define CM_FXCOMCLKSEL7 27U +#define CM_HSLSPICLKSEL 28U +#define CM_MCLKCLKSEL 32U +#define CM_SCTCLKSEL 36U +#define CM_SDIOCLKSEL 38U -#define CM_RTCOSC32KCLKSEL 63 +#define CM_RTCOSC32KCLKSEL 63U +/*! + * @brief The enumerator of clock attach Id. + */ typedef enum _clock_attach_id { - kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), - kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), - kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), - kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), - kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), - kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), - kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), + kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO12M to MAIN_CLK. */ - kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), - kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), - kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), - kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), - kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), - kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), - kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), - kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), + kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach EXT_CLK to MAIN_CLK. */ - kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), - kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), - kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), - kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), - kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), + kFRO1M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO1M to MAIN_CLK. */ - kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), - kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), - kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), - kFRO1M_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 3), /* Need confirm */ - kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), + kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0, 0), /*!< Attach FRO_HF to MAIN_CLK. */ - kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), - kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), - kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), - kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), - kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), + kPLL0_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 1, 0), /*!< Attach PLL0 to MAIN_CLK. */ - kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), - kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), - kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), - kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), - kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), - kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), - kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), - kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), + kPLL1_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 2, 0), /*!< Attach PLL1 to MAIN_CLK. */ - kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), - kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), - kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), - kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), - kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), - kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), - kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), - kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), + kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 3, 0), /*!< Attach OSC32K to MAIN_CLK. */ - kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), - kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), - kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), - kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), - kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), - kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), - kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), - kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), + kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 0), /*!< Attach MAIN_CLK to CLKOUT. */ - kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), - kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), - kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), - kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), - kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), - kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), - kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), - kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), + kPLL0_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 1), /*!< Attach PLL0 to CLKOUT. */ - kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), - kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), - kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), - kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), - kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), - kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), - kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), - kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), + kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 2), /*!< Attach EXT_CLK to CLKOUT. */ - kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), - kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), - kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), - kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), - kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), - kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), - kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), - kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), + kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 3), /*!< Attach FRO_HF to CLKOUT. */ - kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), - kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), - kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), - kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), - kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), - kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), - kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), - kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), + kFRO1M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 4), /*!< Attach FRO1M to CLKOUT. */ - kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), - kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), - kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), - kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), - kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), - kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), - kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), - kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), + kPLL1_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 5), /*!< Attach PLL1 to CLKOUT. */ - kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), - kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), - kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), - kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), - kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), - kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), - kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), + kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 6), /*!< Attach OSC32K to CLKOUT. */ - kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), - kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), - kFRO1M_to_MCLK = MUX_A(CM_MCLKCLKSEL, 2), /* Need confirm */ - kMAIN_CLK_to_MCLK = MUX_A(CM_MCLKCLKSEL, 3), /* Need confirm */ - kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), + kNONE_to_SYS_CLKOUT = MUX_A(CM_CLKOUTCLKSEL, 7), /*!< Attach NONE to SYS_CLKOUT. */ - kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), - kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), - kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), - kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), - kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), - kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), + kFRO12M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 0), /*!< Attach FRO12M to PLL0. */ - kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), - kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), - kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), - kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5), - kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), + kEXT_CLK_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 1), /*!< Attach EXT_CLK to PLL0. */ - kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), - kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), + kFRO1M_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 2), /*!< Attach FRO1M to PLL0. */ - kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), - kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), - kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), - kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), + kOSC32K_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 3), /*!< Attach OSC32K to PLL0. */ - kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), - kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), - kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), - kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), + kNONE_to_PLL0 = MUX_A(CM_PLL0CLKSEL, 7), /*!< Attach NONE to PLL0. */ - kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), - kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), - kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), - kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), + kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0), /*!< Attach MAIN_CLK to ADC_CLK. */ - kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), - kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), - kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), - kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), - kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), + kPLL0_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1), /*!< Attach PLL0 to ADC_CLK. */ - kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), - kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), - kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), - kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), - kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), - kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), - kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), + kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2), /*!< Attach FRO_HF to ADC_CLK. */ - kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), - kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), - kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), - kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), - kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), - kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), - kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), + kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7), /*!< Attach NONE to ADC_CLK. */ - kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), - kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), - kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), - kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), - kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), - kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), - kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), + kMAIN_CLK_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 0), /*!< Attach MAIN_CLK to USB0_CLK. */ - kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), - kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), - kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), - kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), - kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), - kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), - kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), + kPLL0_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 1), /*!< Attach PLL0 to USB0_CLK. */ + + kFRO_HF_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 3), /*!< Attach FRO_HF to USB0_CLK. */ + + kPLL1_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 5), /*!< Attach PLL1 to USB0_CLK. */ + + kNONE_to_USB0_CLK = MUX_A(CM_USB0CLKSEL, 7), /*!< Attach NONE to USB0_CLK. */ + + kMAIN_CLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0), /*!< Attach MAIN_CLK to FLEXCOMM0. */ + + kPLL0_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1), /*!< Attach PLL0_DIV to FLEXCOMM0. */ + + kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2), /*!< Attach FRO12M to FLEXCOMM0. */ + + kFRO_HF_DIV_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM0. */ + + kFRO1M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4), /*!< Attach FRO1M to FLEXCOMM0. */ + + kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 5), /*!< Attach MCLK to FLEXCOMM0. */ + + kOSC32K_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 6), /*!< Attach OSC32K to FLEXCOMM0. */ + + kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7), /*!< Attach NONE to FLEXCOMM0. */ + + kMAIN_CLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0), /*!< Attach MAIN_CLK to FLEXCOMM1. */ + + kPLL0_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1), /*!< Attach PLL0_DIV to FLEXCOMM1. */ + + kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2), /*!< Attach FRO12M to FLEXCOMM1. */ + + kFRO_HF_DIV_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM1. */ + + kFRO1M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4), /*!< Attach FRO1M to FLEXCOMM1. */ + + kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 5), /*!< Attach MCLK to FLEXCOMM1. */ + + kOSC32K_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 6), /*!< Attach OSC32K to FLEXCOMM1. */ + + kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7), /*!< Attach NONE to FLEXCOMM1. */ + + kMAIN_CLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0), /*!< Attach MAIN_CLK to FLEXCOMM2. */ + + kPLL0_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1), /*!< Attach PLL0_DIV to FLEXCOMM2. */ + + kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2), /*!< Attach FRO12M to FLEXCOMM2. */ + + kFRO_HF_DIV_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM2. */ + + kFRO1M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4), /*!< Attach FRO1M to FLEXCOMM2. */ + + kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 5), /*!< Attach MCLK to FLEXCOMM2. */ + + kOSC32K_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 6), /*!< Attach OSC32K to FLEXCOMM2. */ + + kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7), /*!< Attach NONE to FLEXCOMM2. */ + + kMAIN_CLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0), /*!< Attach MAIN_CLK to FLEXCOMM3. */ + + kPLL0_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1), /*!< Attach PLL0_DIV to FLEXCOMM3. */ + + kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2), /*!< Attach FRO12M to FLEXCOMM3. */ + + kFRO_HF_DIV_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM3. */ + + kFRO1M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4), /*!< Attach FRO1M to FLEXCOMM3. */ + + kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 5), /*!< Attach MCLK to FLEXCOMM3. */ + + kOSC32K_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 6), /*!< Attach OSC32K to FLEXCOMM3. */ + + kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7), /*!< Attach NONE to FLEXCOMM3. */ + + kMAIN_CLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0), /*!< Attach MAIN_CLK to FLEXCOMM4. */ + + kPLL0_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1), /*!< Attach PLL0_DIV to FLEXCOMM4. */ + + kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2), /*!< Attach FRO12M to FLEXCOMM4. */ + + kFRO_HF_DIV_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM4. */ + + kFRO1M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4), /*!< Attach FRO1M to FLEXCOMM4. */ + + kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 5), /*!< Attach MCLK to FLEXCOMM4. */ + + kOSC32K_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 6), /*!< Attach OSC32K to FLEXCOMM4. */ + + kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7), /*!< Attach NONE to FLEXCOMM4. */ + + kMAIN_CLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0), /*!< Attach MAIN_CLK to FLEXCOMM5. */ + + kPLL0_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1), /*!< Attach PLL0_DIV to FLEXCOMM5. */ + + kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2), /*!< Attach FRO12M to FLEXCOMM5. */ + + kFRO_HF_DIV_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM5. */ + + kFRO1M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4), /*!< Attach FRO1M to FLEXCOMM5. */ + + kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 5), /*!< Attach MCLK to FLEXCOMM5. */ + + kOSC32K_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 6), /*!< Attach OSC32K to FLEXCOMM5. */ + + kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7), /*!< Attach NONE to FLEXCOMM5. */ + + kMAIN_CLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0), /*!< Attach MAIN_CLK to FLEXCOMM6. */ + + kPLL0_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1), /*!< Attach PLL0_DIV to FLEXCOMM6. */ + + kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2), /*!< Attach FRO12M to FLEXCOMM6. */ + + kFRO_HF_DIV_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM6. */ + + kFRO1M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4), /*!< Attach FRO1M to FLEXCOMM6. */ + + kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 5), /*!< Attach MCLK to FLEXCOMM6. */ + + kOSC32K_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 6), /*!< Attach OSC32K to FLEXCOMM6. */ + + kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7), /*!< Attach NONE to FLEXCOMM6. */ + + kMAIN_CLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0), /*!< Attach MAIN_CLK to FLEXCOMM7. */ + + kPLL0_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1), /*!< Attach PLL0_DIV to FLEXCOMM7. */ + + kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2), /*!< Attach FRO12M to FLEXCOMM7. */ + + kFRO_HF_DIV_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3), /*!< Attach FRO_HF_DIV to FLEXCOMM7. */ + + kFRO1M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4), /*!< Attach FRO1M to FLEXCOMM7. */ + + kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 5), /*!< Attach MCLK to FLEXCOMM7. */ + + kOSC32K_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 6), /*!< Attach OSC32K to FLEXCOMM7. */ + + kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7), /*!< Attach NONE to FLEXCOMM7. */ + + kMAIN_CLK_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 0), /*!< Attach MAIN_CLK to HSLSPI. */ + + kPLL0_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 1), /*!< Attach PLL0_DIV to HSLSPI. */ + + kFRO12M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 2), /*!< Attach FRO12M to HSLSPI. */ + + kFRO_HF_DIV_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 3), /*!< Attach FRO_HF_DIV to HSLSPI. */ + + kFRO1M_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 4), /*!< Attach FRO1M to HSLSPI. */ + + kOSC32K_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 6), /*!< Attach OSC32K to HSLSPI. */ + + kNONE_to_HSLSPI = MUX_A(CM_HSLSPICLKSEL, 7), /*!< Attach NONE to HSLSPI. */ + + kFRO_HF_to_MCLK = MUX_A(CM_MCLKCLKSEL, 0), /*!< Attach FRO_HF to MCLK. */ + + kPLL0_to_MCLK = MUX_A(CM_MCLKCLKSEL, 1), /*!< Attach PLL0 to MCLK. */ + + kNONE_to_MCLK = MUX_A(CM_MCLKCLKSEL, 7), /*!< Attach NONE to MCLK. */ + + kMAIN_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 0), /*!< Attach MAIN_CLK to SCT_CLK. */ + + kPLL0_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 1), /*!< Attach PLL0 to SCT_CLK. */ + + kEXT_CLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 2), /*!< Attach EXT_CLK to SCT_CLK. */ + + kFRO_HF_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 3), /*!< Attach FRO_HF to SCT_CLK. */ + + kMCLK_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 5), /*!< Attach MCLK to SCT_CLK. */ + + kNONE_to_SCT_CLK = MUX_A(CM_SCTCLKSEL, 7), /*!< Attach NONE to SCT_CLK. */ + + kMAIN_CLK_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 0), /*!< Attach MAIN_CLK to SDIO_CLK. */ + + kPLL0_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 1), /*!< Attach PLL0 to SDIO_CLK. */ + + kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3), /*!< Attach FRO_HF to SDIO_CLK. */ + + kPLL1_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 5), /*!< Attach PLL1 to SDIO_CLK. */ + + kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7), /*!< Attach NONE to SDIO_CLK. */ + + kFRO32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 0), /*!< Attach FRO32K to OSC32K. */ + + kXTAL32K_to_OSC32K = MUX_A(CM_RTCOSC32KCLKSEL, 1), /*!< Attach XTAL32K to OSC32K. */ + + kTRACE_DIV_to_TRACE = MUX_A(CM_TRACECLKSEL, 0), /*!< Attach TRACE_DIV to TRACE. */ + + kFRO1M_to_TRACE = MUX_A(CM_TRACECLKSEL, 1), /*!< Attach FRO1M to TRACE. */ + + kOSC32K_to_TRACE = MUX_A(CM_TRACECLKSEL, 2), /*!< Attach OSC32K to TRACE. */ + + kNONE_to_TRACE = MUX_A(CM_TRACECLKSEL, 7), /*!< Attach NONE to TRACE. */ + + kSYSTICK_DIV0_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 0), /*!< Attach SYSTICK_DIV0 to SYSTICK0. */ + + kFRO1M_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 1), /*!< Attach FRO1M to SYSTICK0. */ + + kOSC32K_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 2), /*!< Attach OSC32K to SYSTICK0. */ + + kNONE_to_SYSTICK0 = MUX_A(CM_SYSTICKCLKSEL0, 7), /*!< Attach NONE to SYSTICK0. */ + + kSYSTICK_DIV1_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 0), /*!< Attach SYSTICK_DIV1 to SYSTICK1. */ + + kFRO1M_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 1), /*!< Attach FRO1M to SYSTICK1. */ + + kOSC32K_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 2), /*!< Attach OSC32K to SYSTICK1. */ + + kNONE_to_SYSTICK1 = MUX_A(CM_SYSTICKCLKSEL1, 7), /*!< Attach NONE to SYSTICK1. */ + + kFRO12M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 0), /*!< Attach FRO12M to PLL1. */ + + kEXT_CLK_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 1), /*!< Attach EXT_CLK to PLL1. */ + + kFRO1M_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 2), /*!< Attach FRO1M to PLL1. */ + + kOSC32K_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 3), /*!< Attach OSC32K to PLL1. */ + + kNONE_to_PLL1 = MUX_A(CM_PLL1CLKSEL, 7), /*!< Attach NONE to PLL1. */ + + kMAIN_CLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 0), /*!< Attach MAIN_CLK to CTIMER0. */ + + kPLL0_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 1), /*!< Attach PLL0 to CTIMER0. */ + + kFRO_HF_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 3), /*!< Attach FRO_HF to CTIMER0. */ + + kFRO1M_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 4), /*!< Attach FRO1M to CTIMER0. */ + + kMCLK_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 5), /*!< Attach MCLK to CTIMER0. */ + + kOSC32K_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 6), /*!< Attach OSC32K to CTIMER0. */ + + kNONE_to_CTIMER0 = MUX_A(CM_CTIMERCLKSEL0, 7), /*!< Attach NONE to CTIMER0. */ + + kMAIN_CLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 0), /*!< Attach MAIN_CLK to CTIMER1. */ + + kPLL0_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 1), /*!< Attach PLL0 to CTIMER1. */ + + kFRO_HF_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 3), /*!< Attach FRO_HF to CTIMER1. */ + + kFRO1M_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 4), /*!< Attach FRO1M to CTIMER1. */ + + kMCLK_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 5), /*!< Attach MCLK to CTIMER1. */ + + kOSC32K_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 6), /*!< Attach OSC32K to CTIMER1. */ + + kNONE_to_CTIMER1 = MUX_A(CM_CTIMERCLKSEL1, 7), /*!< Attach NONE to CTIMER1. */ + + kMAIN_CLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 0), /*!< Attach MAIN_CLK to CTIMER2. */ + + kPLL0_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 1), /*!< Attach PLL0 to CTIMER2. */ + + kFRO_HF_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 3), /*!< Attach FRO_HF to CTIMER2. */ + + kFRO1M_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 4), /*!< Attach FRO1M to CTIMER2. */ + + kMCLK_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 5), /*!< Attach MCLK to CTIMER2. */ + + kOSC32K_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 6), /*!< Attach OSC32K to CTIMER2. */ + + kNONE_to_CTIMER2 = MUX_A(CM_CTIMERCLKSEL2, 7), /*!< Attach NONE to CTIMER2. */ + + kMAIN_CLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 0), /*!< Attach MAIN_CLK to CTIMER3. */ + + kPLL0_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 1), /*!< Attach PLL0 to CTIMER3. */ + + kFRO_HF_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 3), /*!< Attach FRO_HF to CTIMER3. */ + + kFRO1M_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 4), /*!< Attach FRO1M to CTIMER3. */ + + kMCLK_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 5), /*!< Attach MCLK to CTIMER3. */ + + kOSC32K_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 6), /*!< Attach OSC32K to CTIMER3. */ + + kNONE_to_CTIMER3 = MUX_A(CM_CTIMERCLKSEL3, 7), /*!< Attach NONE to CTIMER3. */ + + kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), /*!< Attach MAIN_CLK to CTIMER4. */ + + kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), /*!< Attach PLL0 to CTIMER4. */ + + kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), /*!< Attach FRO_HF to CTIMER4. */ + + kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), /*!< Attach FRO1M to CTIMER4. */ + + kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), /*!< Attach MCLK to CTIMER4. */ + + kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), /*!< Attach OSC32K to CTIMER4. */ + + kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), /*!< Attach NONE to CTIMER4. */ + + kNONE_to_NONE = (int)0x80000000U, /*!< Attach NONE to NONE. */ - kMAIN_CLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 0), - kPLL0_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 1), - kFRO_HF_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 3), - kFRO1M_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 4), - kMCLK_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 5), - kOSC32K_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 6), - kNONE_to_CTIMER4 = MUX_A(CM_CTIMERCLKSEL4, 7), - kNONE_to_NONE = (int)0x80000000U, } clock_attach_id_t; -/* Clock dividers */ +/*! @brief Clock dividers */ typedef enum _clock_div_name { - kCLOCK_DivSystickClk0 = 0, - kCLOCK_DivSystickClk1 = 1, - kCLOCK_DivArmTrClkDiv = 2, - kCLOCK_DivFlexFrg0 = 8, - kCLOCK_DivFlexFrg1 = 9, - kCLOCK_DivFlexFrg2 = 10, - kCLOCK_DivFlexFrg3 = 11, - kCLOCK_DivFlexFrg4 = 12, - kCLOCK_DivFlexFrg5 = 13, - kCLOCK_DivFlexFrg6 = 14, - kCLOCK_DivFlexFrg7 = 15, - kCLOCK_DivAhbClk = 32, - kCLOCK_DivClkOut = 33, - kCLOCK_DivFrohfClk = 34, - kCLOCK_DivWdtClk = 35, - kCLOCK_DivAdcAsyncClk = 37, - kCLOCK_DivUsb0Clk = 38, - kCLOCK_DivMClk = 43, - kCLOCK_DivSctClk = 45, - kCLOCK_DivSdioClk = 47, - kCLOCK_DivPll0Clk = 49 + kCLOCK_DivSystickClk0 = 0, /*!< Systick Clk0 Divider. */ + + kCLOCK_DivSystickClk1 = 1, /*!< Systick Clk1 Divider. */ + + kCLOCK_DivArmTrClkDiv = 2, /*!< Arm Tr Clk Div Divider. */ + + kCLOCK_DivFlexFrg0 = 8, /*!< Flex Frg0 Divider. */ + + kCLOCK_DivFlexFrg1 = 9, /*!< Flex Frg1 Divider. */ + + kCLOCK_DivFlexFrg2 = 10, /*!< Flex Frg2 Divider. */ + + kCLOCK_DivFlexFrg3 = 11, /*!< Flex Frg3 Divider. */ + + kCLOCK_DivFlexFrg4 = 12, /*!< Flex Frg4 Divider. */ + + kCLOCK_DivFlexFrg5 = 13, /*!< Flex Frg5 Divider. */ + + kCLOCK_DivFlexFrg6 = 14, /*!< Flex Frg6 Divider. */ + + kCLOCK_DivFlexFrg7 = 15, /*!< Flex Frg7 Divider. */ + + kCLOCK_DivAhbClk = 32, /*!< Ahb Clock Divider. */ + + kCLOCK_DivClkOut = 33, /*!< Clk Out Divider. */ + + kCLOCK_DivFrohfClk = 34, /*!< Frohf Clock Divider. */ + + kCLOCK_DivWdtClk = 35, /*!< Wdt Clock Divider. */ + + kCLOCK_DivAdcAsyncClk = 37, /*!< Adc Async Clock Divider. */ + + kCLOCK_DivUsb0Clk = 38, /*!< Usb0 Clock Divider. */ + + kCLOCK_DivMClk = 43, /*!< I2S MCLK Clock Divider. */ + + kCLOCK_DivSctClk = 45, /*!< Sct Clock Divider. */ + + kCLOCK_DivSdioClk = 47, /*!< Sdio Clock Divider. */ + + kCLOCK_DivPll0Clk = 49 /*!< PLL clock divider. */ } clock_div_name_t; /******************************************************************************* @@ -775,29 +977,29 @@ extern "C" { /** * @brief Enable the clock for specific IP. - * @param name : Clock to be enabled. + * @param clk : Clock to be enabled. * @return Nothing */ static inline void CLOCK_EnableClock(clock_ip_name_t clk) { uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + SYSCON->AHBCLKCTRLSET[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); } /** * @brief Disable the clock for specific IP. - * @param name : Clock to be Disabled. + * @param clk : Clock to be Disabled. * @return Nothing */ static inline void CLOCK_DisableClock(clock_ip_name_t clk) { uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk); - SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); + SYSCON->AHBCLKCTRLCLR[index] = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk)); } /** * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz). * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is * enabled. - * @param iFreq : Desired frequency (must be one of #CLK_FRO_12MHZ or #CLK_FRO_48MHZ or #CLK_FRO_96MHZ) + * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ) * @return returns success or fail status. */ status_t CLOCK_SetupFROClocking(uint32_t iFreq); @@ -819,6 +1021,12 @@ status_t CLOCK_SetupExtClocking(uint32_t iFreq); * @return returns success or fail status. */ status_t CLOCK_SetupI2SMClkClocking(uint32_t iFreq); +/** + * @brief Initialize the PLU CLKIN clock to given frequency. + * @param iFreq : Desired frequency (must be equal to exact rate in Hz) + * @return returns success or fail status. + */ +status_t CLOCK_SetupPLUClkInClocking(uint32_t iFreq); /** * @brief Configure the clock selection muxes. * @param connection : Clock to be configured. @@ -857,7 +1065,7 @@ void CLOCK_SetRtc1hzClkDiv(uint32_t divided_by_value); /** * @brief Set the flexcomm output frequency. * @param id : flexcomm instance id - * freq : output frequency + * @param freq : output frequency * @return 0 : the frequency range is out of range. * 1 : switch successfully. */ @@ -941,6 +1149,18 @@ uint32_t CLOCK_GetCoreSysClkFreq(void); * @return Frequency of I2S MCLK Clock */ uint32_t CLOCK_GetI2SMClkFreq(void); +/*! @brief Return Frequency of PLU CLKIN Clock + * @return Frequency of PLU CLKIN Clock + */ +uint32_t CLOCK_GetPLUClkInFreq(void); +/*! @brief Return Frequency of FlexComm Clock + * @return Frequency of FlexComm Clock + */ +uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id); +/*! @brief Return Frequency of High speed SPI Clock + * @return Frequency of High speed SPI Clock + */ +uint32_t CLOCK_GetHsLspiClkFreq(void); /*! @brief Return Frequency of CTimer functional Clock * @return Frequency of CTimer functional Clock */ @@ -969,15 +1189,6 @@ uint32_t CLOCK_GetPLL1InClockRate(void); */ uint32_t CLOCK_GetPLL0OutClockRate(bool recompute); -/*! @brief Return PLL1 output clock rate - * @param recompute : Forces a PLL rate recomputation if true - * @return PLL1 output clock rate - * @note The PLL rate is cached in the driver in a variable as - * the rate computation function can take some time to perform. It - * is recommended to use 'false' with the 'recompute' parameter. - */ -uint32_t CLOCK_GetPLL1OutClockRate(bool recompute); - /*! @brief Enables and disables PLL0 bypass mode * @brief bypass : true to bypass PLL0 (PLL0 output = PLL0 input, false to disable bypass * @return PLL0 output clock rate @@ -1015,7 +1226,7 @@ __STATIC_INLINE void CLOCK_SetBypassPLL1(bool bypass) */ __STATIC_INLINE bool CLOCK_IsPLL0Locked(void) { - return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0); + return (bool)((SYSCON->PLL0STAT & SYSCON_PLL0STAT_LOCK_MASK) != 0UL); } /*! @brief Check if PLL1 is locked or not @@ -1023,7 +1234,7 @@ __STATIC_INLINE bool CLOCK_IsPLL0Locked(void) */ __STATIC_INLINE bool CLOCK_IsPLL1Locked(void) { - return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0); + return (bool)((SYSCON->PLL1STAT & SYSCON_PLL1STAT_LOCK_MASK) != 0UL); } /*! @brief Store the current PLL0 rate @@ -1046,8 +1257,8 @@ void CLOCK_SetStoredPLL0ClockRate(uint32_t rate); * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider * are not used.
*/ -#define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */ -#define PLL_CONFIGFLAG_FORCENOFRACT (1 << 2) +#define PLL_CONFIGFLAG_USEINRATE (1U << 0U) /*!< Flag to use InputRate in PLL configuration structure for setup */ +#define PLL_CONFIGFLAG_FORCENOFRACT (1U << 2U) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS hardware */ /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency @@ -1117,10 +1328,10 @@ typedef struct _pll_config /*! @brief PLL setup structure flags for 'flags' field * These flags control how the PLL setup function sets up the PLL */ -#define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */ -#define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ -#define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */ -#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1 << 3) /*!< Use feedback divider by 2 in divider path */ +#define PLL_SETUPFLAG_POWERUP (1U << 0U) /*!< Setup will power on the PLL after setup */ +#define PLL_SETUPFLAG_WAITLOCK (1U << 1U) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */ +#define PLL_SETUPFLAG_ADGVOLT (1U << 2U) /*!< Optimize system voltage for the new PLL rate */ +#define PLL_SETUPFLAG_USEFEEDBACKDIV2 (1U << 3U) /*!< Use feedback divider by 2 in divider path */ /*! @brief PLL0 setup structure * This structure can be used to pre-build a PLL setup configuration @@ -1281,15 +1492,10 @@ bool CLOCK_EnableUsbhs0DeviceClock(clock_usbhs_src_t src, uint32_t freq); */ bool CLOCK_EnableUsbhs0HostClock(clock_usbhs_src_t src, uint32_t freq); -/*! - * @brief Use DWT to delay at least for some time. - * Please note that, this API will calculate the microsecond period with the maximum devices - * supported CPU frequency, so this API will only delay for at least the given microseconds, if precise - * delay count was needed, please implement a new timer count to achieve this function. - * - * @param delay_us Delay time in unit of microsecond. +/*! @brief Enable the OSTIMER 32k clock. + * @return Nothing */ -void SDK_DelayAtLeastUs(uint32_t delay_us); +void CLOCK_EnableOstimer32kClock(void); #if defined(__cplusplus) } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.c index d5496aecd3..c7069e5c13 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.c @@ -1,9 +1,9 @@ /* - * Copyright 2018 NXP -* All rights reserved. -* -* SPDX-License-Identifier: BSD-3-Clause -*/ + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ #include "fsl_cmp.h" @@ -23,33 +23,106 @@ /******************************************************************************* * Code ******************************************************************************/ -void CMP_Init(cmp_config_t *config) + +/*! + * @brief CMP initialization. + * + * This function enables the CMP module and do necessary settings. + * + * @param config Pointer to the configuration structure. + */ +void CMP_Init(const cmp_config_t *config) { assert(NULL != config); -/*enable the clock to the register interface*/ + uint32_t tmpReg = 0U; + #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ CLOCK_EnableClock(kCLOCK_Comp); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -/*Clear reset to peripheral cmp*/ #if !(defined(FSL_FEATURE_CMP_HAS_NO_RESET) && FSL_TEATURE_CMP_HAS_NO_RESET) - RESET_ClearPeripheralReset(kCMP_RST_SHIFT_RSTn); -#endif + /* Reset the CMP module. */ + RESET_PeripheralReset(kCMP_RST_SHIFT_RSTn); +#endif /* FSL_FEATURE_CMP_HAS_NO_RESET */ - /*clear COMP bits*/ - PMC->COMP &= ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK); + tmpReg = (PMC->COMP & ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_FILTERCGF_CLKDIV_MASK | + PMC_COMP_FILTERCGF_SAMPLEMODE_MASK)); - PMC->COMP |= (config->enLowPower << PMC_COMP_LOWPOWER_SHIFT) /*Select if enter low power mode*/ - | (config->enHysteris << PMC_COMP_HYST_SHIFT) /*select if enable hysteresis*/ - | config->pmuxInput /*pmux input source select*/ - | config->nmuxInput; /*nmux input source select */ + if (true == config->enableLowPower) + { + tmpReg |= PMC_COMP_LOWPOWER_MASK; + } + else + { + tmpReg &= ~PMC_COMP_LOWPOWER_MASK; + } + + if (true == config->enableHysteresis) + { + tmpReg |= PMC_COMP_HYST_MASK; + } + else + { + tmpReg &= ~PMC_COMP_HYST_MASK; + } + + tmpReg |= (PMC_COMP_FILTERCGF_CLKDIV(config->filterClockDivider) | + PMC_COMP_FILTERCGF_SAMPLEMODE(config->filterSampleMode)); + + PMC->COMP = tmpReg; } +/*! + * @brief CMP deinitialization. + * + * This function gates the clock for CMP module. + */ void CMP_Deinit(void) { -/*disable the clock to the register interface*/ #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Disable the clock. */ CLOCK_DisableClock(kCLOCK_Comp); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } + +/*! + * @brief Initializes the CMP user configuration structure. + * + * This function initializes the user configuration structure to these default values. + * @code + * config->enableHysteresis = true; + * config->enableLowPower = true; + * config->filterClockDivider = kCMP_FilterClockDivide1; + * config->filterSampleMode = kCMP_FilterSampleMode0; + * @endcode + * @param config Pointer to the configuration structure. + */ +void CMP_GetDefaultConfig(cmp_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->enableHysteresis = true; + config->enableLowPower = true; + config->filterClockDivider = kCMP_FilterClockDivide1; + config->filterSampleMode = kCMP_FilterSampleMode0; +} + +/*! + * @brief Configures the VREFINPUT. + * + * @param config Pointer to the configuration structure. + */ +void CMP_SetVREF(const cmp_vref_config_t *config) +{ + assert(NULL != config); + assert(config->vrefValue < 32U); + + uint32_t tmpReg = PMC->COMP & ~(PMC_COMP_VREF_MASK | PMC_COMP_VREFINPUT_MASK); + + tmpReg |= PMC_COMP_VREFINPUT(config->vrefSource) | PMC_COMP_VREF(config->vrefValue); + + PMC->COMP = tmpReg; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.h index f0990cf668..1afdc97280 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_cmp.h @@ -1,9 +1,9 @@ /* - * Copyright 2018 NXP -* All rights reserved. -* -* SPDX-License-Identifier: BSD-3-Clause -*/ + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ #ifndef __FSL_CMP_H_ #define __FSL_CMP_H_ @@ -20,61 +20,79 @@ *****************************************************************************/ /*! @name Driver version */ /*@{*/ -/*! @brief Driver version 2.0.0. */ -#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U)) +/*! @brief Driver version 2.2.1. */ +#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 1U)) /*@}*/ -/*! @brief VREF select */ -enum _cmp_vref_select +/*! @brief CMP input mux for positive and negative sides. */ +enum _cmp_input_mux { - KCMP_VREFSelectVDDA = 1U, /*!< Select VDDA as VREF*/ - KCMP_VREFSelectInternalVREF = 0U, /*!< select internal VREF as VREF*/ + kCMP_InputVREF = 0U, /*!< Cmp input from VREF. */ + kCMP_Input1 = 1U, /*!< Cmp input source 1. */ + kCMP_Input2 = 2U, /*!< Cmp input source 2. */ + kCMP_Input3 = 3U, /*!< Cmp input source 3. */ + kCMP_Input4 = 4U, /*!< Cmp input source 4. */ + kCMP_Input5 = 5U, /*!< Cmp input source 5. */ }; -/*! @brief cmp interrupt type */ -typedef enum _cmp_interrupt_type +/*! @brief CMP interrupt type. */ +enum _cmp_interrupt_type { - kCMP_EdgeDisable = 0U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable edge sensitive */ - kCMP_EdgeRising = 2U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, falling edge */ - kCMP_EdgeFalling = 4U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, rising edge */ - kCMP_EdgeRisingFalling = 6U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, rising and falling edge */ + kCMP_EdgeDisable = 0U, /*!< Disable edge interupt. */ + kCMP_EdgeRising = 2U, /*!< Interrupt on falling edge. */ + kCMP_EdgeFalling = 4U, /*!< Interrupt on rising edge. */ + kCMP_EdgeRisingFalling = 6U, /*!< Interrupt on both rising and falling edges. */ - kCMP_LevelDisable = 1U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable level sensitive */ - kCMP_LevelHigh = 3U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Level sensitive, high level */ - kCMP_LevelLow = 5U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Level sensitive, low level */ - kCMP_LevelDisable1 = 7U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable level sensitive */ -} cmp_interrupt_type_t; + kCMP_LevelDisable = 1U, /*!< Disable level interupt. */ + kCMP_LevelHigh = 3U, /*!< Interrupt on high level. */ + kCMP_LevelLow = 5U, /*!< Interrupt on low level. */ +}; -/*! @brief cmp Pmux input source */ -typedef enum _cmp_pmux_input +/*! @brief CMP Voltage Reference source. */ +typedef enum _cmp_vref_source { - kCMP_PInputVREF = 0U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from VREF */ - kCMP_PInputP0_0 = 1U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_0 */ - kCMP_PInputP0_9 = 2U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_9 */ - kCMP_PInputP0_18 = 3U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_18 */ - kCMP_PInputP1_14 = 4U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P1_14 */ - kCMP_PInputP2_23 = 5U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P2_23 */ -} cmp_pmux_input_t; + KCMP_VREFSourceVDDA = 1U, /*!< Select VDDA as VREF. */ + KCMP_VREFSourceInternalVREF = 0U, /*!< Select internal VREF as VREF. */ +} cmp_vref_source_t; -/*! @brief cmp Nmux input source */ -typedef enum _cmp_nmux_input +typedef struct _cmp_vref_config { - kCMP_NInputVREF = 0U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from VREF */ - kCMP_NInputP0_0 = 1U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_0 */ - kCMP_NInputP0_9 = 2U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_9 */ - kCMP_NInputP0_18 = 3U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_18 */ - kCMP_NInputP1_14 = 4U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P1_14 */ - kCMP_NInputP2_23 = 5U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P2_23 */ -} cmp_nmux_input_t; + cmp_vref_source_t vrefSource; /*!< Reference voltage source. */ + uint8_t vrefValue; /*!< Reference voltage step. Available range is 0-31. Per step equals to VREFINPUT/31. */ +} cmp_vref_config_t; -/*! @brief cmp configurataions */ +/*! @brief CMP Filter sample mode. */ +typedef enum _cmp_filtercgf_samplemode +{ + kCMP_FilterSampleMode0 = 0U, /*!< Bypass mode. Filtering is disabled. */ + kCMP_FilterSampleMode1 = 1U, /*!< Filter 1 clock period. */ + kCMP_FilterSampleMode2 = 2U, /*!< Filter 2 clock period. */ + kCMP_FilterSampleMode3 = 3U /*!< Filter 3 clock period. */ +} cmp_filtercgf_samplemode_t; + +/*! @brief CMP Filter clock divider. */ +typedef enum _cmp_filtercgf_clkdiv +{ + kCMP_FilterClockDivide1 = 0U, /*!< Filter clock period duration equals 1 analog comparator clock period. */ + kCMP_FilterClockDivide2 = 1U, /*!< Filter clock period duration equals 2 analog comparator clock period. */ + kCMP_FilterClockDivide4 = 2U, /*!< Filter clock period duration equals 4 analog comparator clock period. */ + kCMP_FilterClockDivide8 = 3U, /*!< Filter clock period duration equals 8 analog comparator clock period. */ + kCMP_FilterClockDivide16 = 4U, /*!< Filter clock period duration equals 16 analog comparator clock period. */ + kCMP_FilterClockDivide32 = 5U, /*!< Filter clock period duration equals 32 analog comparator clock period. */ + kCMP_FilterClockDivide64 = 6U /*!< Filter clock period duration equals 64 analog comparator clock period. */ +} cmp_filtercgf_clkdiv_t; + +/*! @brief CMP configuration structure. */ typedef struct _cmp_config { - bool enHysteris; /*!< low hysteresis */ - bool enLowPower; /*!enableHysteresis = true; + * config->enableLowPower = true; + * config->filterClockDivider = kCMP_FilterClockDivide1; + * config->filterSampleMode = kCMP_FilterSampleMode0; + * @endcode + * @param config Pointer to the configuration structure. + */ +void CMP_GetDefaultConfig(cmp_config_t *config); + /* @} */ /*! - * @name cmp functionality + * @name Compare Interface * @{ */ -/*! - * @brief select input source for pmux. +/* + * @brief Set the input channels for the comparator. * - * @param pmux_select_source reference cmp_pmux_input_t above. + * @param positiveChannel Positive side input channel number. See "_cmp_input_mux". + * @param negativeChannel Negative side input channel number. See "_cmp_input_mux". */ -static inline void CMP_PmuxSelect(cmp_pmux_input_t pmux_select_source) +static inline void CMP_SetInputChannels(uint8_t positiveChannel, uint8_t negativeChannel) { - PMC->COMP &= ~PMC_COMP_PMUX_MASK; - PMC->COMP |= pmux_select_source; + PMC->COMP &= ~(PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK); + PMC->COMP |= (PMC_COMP_PMUX(positiveChannel) | PMC_COMP_NMUX(negativeChannel)); } /*! - * @brief select input source for nmux. + * @brief Configures the VREFINPUT. * - * @param nmux_select_source reference cmp_nmux_input_t above. + * @param config Pointer to the configuration structure. */ -static inline void CMP_NmuxSelect(cmp_nmux_input_t nmux_select_source) -{ - PMC->COMP &= ~PMC_COMP_NMUX_MASK; - PMC->COMP |= nmux_select_source; -} +void CMP_SetVREF(const cmp_vref_config_t *config); /*! - * @brief switch cmp work mode. + * @brief Get CMP compare output. * - * @param enable true is enter low power mode, false is enter fast mode + * @return The output result. true: voltage on positive side is greater than negative side. + * false: voltage on positive side is lower than negative side. */ -static inline void CMP_EnableLowePowerMode(bool enable) +static inline bool CMP_GetOutput(void) { - if (enable) - { - PMC->COMP |= PMC_COMP_LOWPOWER_MASK; - } - else - { - PMC->COMP &= ~PMC_COMP_LOWPOWER_MASK; - } -} - -/*! - * @brief Control reference voltage step, per steps of (VREFINPUT/31). - * - * @param step reference voltage step, per steps of (VREFINPUT/31). - */ -static inline void CMP_SetRefStep(uint32_t step) -{ - PMC->COMP |= step << PMC_COMP_VREF_SHIFT; -} - -/*! - * @brief cmp enable hysteresis. - * - */ -static inline void CMP_EnableHysteresis(bool enable) -{ - if (enable) - { - PMC->COMP |= PMC_COMP_HYST_MASK; - } - else - { - PMC->COMP &= ~PMC_COMP_HYST_MASK; - } -} - -/*! - * @brief VREF select between internal VREF and VDDA (for the resistive ladder). - * - * @param select 1 is Select VDDA, 0 is Select internal VREF. - */ -static inline void CMP_VREFSelect(uint32_t select) -{ - if (select) - { - PMC->COMP |= PMC_COMP_VREFINPUT_MASK; - } - else - { - PMC->COMP &= ~PMC_COMP_VREFINPUT_MASK; - } -} - -/*! - * @brief comparator analog output. - * - * @return 1 indicates p is greater than n, 0 indicates n is greater than p. - */ -static inline uint32_t CMP_GetOutput(void) -{ - return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK) ? 1 : 0; + return SYSCON_COMP_INT_STATUS_VAL_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK); } /* @} */ /*! - * @name cmp interrupt + * @name Interrupt Interface * @{ */ /*! - * @brief cmp enable interrupt. + * @brief CMP enable interrupt. * + * @param type CMP interrupt type. See "_cmp_interrupt_type". */ -static inline void CMP_EnableInterrupt(void) +static inline void CMP_EnableInterrupt(uint32_t type) { - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK; + SYSCON->COMP_INT_CTRL |= (SYSCON_COMP_INT_CTRL_INT_CTRL(type) | SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK); } /*! - * @brief cmp disable interrupt. + * @brief CMP disable interrupt. * */ static inline void CMP_DisableInterrupt(void) @@ -227,61 +199,87 @@ static inline void CMP_DisableInterrupt(void) } /*! - * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection. - * - * @param enable true is Select Analog Comparator raw output (unfiltered) as input for interrupt detection. - * false is Select Analog Comparator filtered output as input for interrupt detection. - */ -static inline void CMP_InterruptSourceSelect(bool enable) -{ - if (enable) - { - SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } - else - { - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; - } -} - -/*! - * @brief cmp get status. - * - * @return true is interrupt pending, false is no interrupt pending. - */ -static inline bool CMP_GetStatus(void) -{ - return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK) ? true : false; -} - -/*! - * @brief cmp clear interrupt status. + * @brief CMP clear interrupt. * */ -static inline void CMP_ClearStatus(void) +static inline void CMP_ClearInterrupt(void) { SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK; } /*! - * @brief Comparator interrupt type select. + * @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection. * - * @param type reference cmp_interrupt_type_t. + * @param enable false: Select Analog Comparator raw output (unfiltered) as input for interrupt detection. + * true: Select Analog Comparator filtered output as input for interrupt detection. + * + * @note: When CMP is configured as the wakeup source in power down mode, this function must use the raw output as the + * interupt source, that is, call this function and set parameter enable to false. */ -static inline void CMP_InterruptTypeSelect(cmp_interrupt_type_t cmp_interrupt_type) +static inline void CMP_EnableFilteredInterruptSource(bool enable) { - SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_CTRL_MASK; - SYSCON->COMP_INT_CTRL |= cmp_interrupt_type; + if (enable) + { + SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; + } + else + { + SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK; + } +} +/* @} */ + +/*! + * @name Status Interface + * @{ + */ + +/*! + * @brief Get CMP interrupt status before interupt enable. + * + * @return Interrupt status. true: interrupt pending, + * false: no interrupt pending. + */ +static inline bool CMP_GetPreviousInterruptStatus(void) +{ + return SYSCON_COMP_INT_STATUS_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK); } /*! - * @brief cmp get interrupt status. + * @brief Get CMP interrupt status after interupt enable. * - * @return true is interrupt pending, false is no interrupt pending. + * @return Interrupt status. true: interrupt pending, + * false: no interrupt pending. */ static inline bool CMP_GetInterruptStatus(void) { - return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) ? true : false; + return SYSCON_COMP_INT_STATUS_INT_STATUS_MASK == (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK); +} +/* @} */ + +/*! + * @name Filter Interface + * @{ + */ + +/*! + * @brief CMP Filter Sample Config. + * + * This function allows the users to configure the sampling mode and clock divider of the CMP Filter. + * + * @param filterSampleMode CMP Select filter sample mode + * @param filterClockDivider CMP Set fileter clock divider + */ +static inline void CMP_FilterSampleConfig(cmp_filtercgf_samplemode_t filterSampleMode, + cmp_filtercgf_clkdiv_t filterClockDivider) +{ + uint32_t comp = PMC->COMP; + + comp &= ~(PMC_COMP_FILTERCGF_CLKDIV_MASK | PMC_COMP_FILTERCGF_SAMPLEMODE_MASK); + comp |= (((uint32_t)filterClockDivider << PMC_COMP_FILTERCGF_CLKDIV_SHIFT) | + ((uint32_t)filterSampleMode << PMC_COMP_FILTERCGF_SAMPLEMODE_SHIFT)); + + PMC->COMP = comp; } /* @} */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.c index deca9c626e..d3af9fdfc6 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.c @@ -1,13 +1,13 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2021 NXP * All rights reserved. * - * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_common.h" + #define SDK_MEM_MAGIC_NUMBER 12345U typedef struct _mem_align_control_block @@ -21,127 +21,65 @@ typedef struct _mem_align_control_block #define FSL_COMPONENT_ID "platform.drivers.common" #endif -#ifndef __GIC_PRIO_BITS -#if defined(ENABLE_RAM_VECTOR_TABLE) -uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) -{ -/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) - extern uint32_t Image$$VECTOR_ROM$$Base[]; - extern uint32_t Image$$VECTOR_RAM$$Base[]; - extern uint32_t Image$$RW_m_data$$Base[]; - -#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base -#define __VECTOR_RAM Image$$VECTOR_RAM$$Base -#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) -#elif defined(__ICCARM__) - extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; -#elif defined(__GNUC__) - extern uint32_t __VECTOR_TABLE[]; - extern uint32_t __VECTOR_RAM[]; - extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; - uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); -#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ - uint32_t n; - uint32_t ret; - uint32_t irqMaskValue; - - irqMaskValue = DisableGlobalIRQ(); - if (SCB->VTOR != (uint32_t)__VECTOR_RAM) - { - /* Copy the vector table from ROM to RAM */ - for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) - { - __VECTOR_RAM[n] = __VECTOR_TABLE[n]; - } - /* Point the VTOR to the position of vector table */ - SCB->VTOR = (uint32_t)__VECTOR_RAM; - } - - ret = __VECTOR_RAM[irq + 16]; - /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[irq + 16] = irqHandler; - - EnableGlobalIRQ(irqMaskValue); - -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif - - return ret; -} -#endif /* ENABLE_RAM_VECTOR_TABLE. */ -#endif /* __GIC_PRIO_BITS. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) -#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) - -void EnableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERSET[index] = 1u << intNumber; - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ -} - -void DisableDeepSleepIRQ(IRQn_Type interrupt) -{ - uint32_t intNumber = (uint32_t)interrupt; - - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ - uint32_t index = 0; - - while (intNumber >= 32u) - { - index++; - intNumber -= 32u; - } - - SYSCON->STARTERCLR[index] = 1u << intNumber; -} -#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - +#if !((defined(__DSC__) && defined(__CW__))) void *SDK_Malloc(size_t size, size_t alignbytes) { mem_align_cb_t *p_cb = NULL; - uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); - void *p_align_addr, *p_addr = malloc(alignedsize); + uint32_t alignedsize; - if (!p_addr) + /* Check overflow. */ + alignedsize = (uint32_t)(unsigned int)SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) { return NULL; } - p_align_addr = (void *)SDK_SIZEALIGN((uint32_t)p_addr + sizeof(mem_align_cb_t), alignbytes); + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } - p_cb = (mem_align_cb_t *)((uint32_t)p_align_addr - 4U); + alignedsize += alignbytes + (uint32_t)sizeof(mem_align_cb_t); + + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_align_addr, p_addr; + + p_addr.pointer_value = malloc((size_t)alignedsize); + + if (p_addr.pointer_value == NULL) + { + return NULL; + } + + p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes); + + p_cb = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U); p_cb->identifier = SDK_MEM_MAGIC_NUMBER; - p_cb->offset = (uint32_t)p_align_addr - (uint32_t)p_addr; + p_cb->offset = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value); - return (void *)p_align_addr; + return p_align_addr.pointer_value; } void SDK_Free(void *ptr) { - mem_align_cb_t *p_cb = (mem_align_cb_t *)((uint32_t)ptr - 4U); + union + { + void *pointer_value; + uintptr_t unsigned_value; + } p_free; + p_free.pointer_value = ptr; + mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U); if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER) { return; } - free((void *)((uint32_t)ptr - p_cb->offset)); + p_free.unsigned_value = p_free.unsigned_value - p_cb->offset; + + free(p_free.pointer_value); } +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.h index 65bc0acce1..d9cb304f2f 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -15,7 +15,7 @@ #include #include -#if defined(__ICCARM__) +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) #include #endif @@ -26,159 +26,202 @@ * @{ */ +/******************************************************************************* + * Configurations + ******************************************************************************/ + +/*! @brief Macro to use the default weak IRQ handler in drivers. */ +#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ +#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 +#endif + /******************************************************************************* * Definitions ******************************************************************************/ /*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) +#define MAKE_STATUS(group, code) ((((group)*100L) + (code))) -/*! @brief Construct the version number for drivers. */ -#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix)) +/*! @brief Construct the version number for drivers. + * + * The driver version is a 32-bit number, for both 32-bit platforms(such as Cortex M) + * and 16-bit platforms(such as DSC). + * + * @verbatim + + | Unused || Major Version || Minor Version || Bug Fix | + 31 25 24 17 16 9 8 0 + + @endverbatim + */ +#define MAKE_VERSION(major, minor, bugfix) (((major) * 65536L) + ((minor) * 256L) + (bugfix)) /*! @name Driver version */ /*@{*/ -/*! @brief common driver version 2.0.1. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @brief common driver version. */ +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 3, 2)) /*@}*/ /* Debug console type definition. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ -#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console based on UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U /*!< Debug console based on LPUART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U /*!< Debug console based on LPSCI. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console based on USBCDC. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console based on FLEXCOMM. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console based on i.MX UART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console based on LPC_VUSART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U /*!< Debug console based on LPC_USART. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_SWO 9U /*!< Debug console based on SWO. */ +#define DEBUG_CONSOLE_DEVICE_TYPE_QSCI 10U /*!< Debug console based on QSCI. */ /*! @brief Status group numbers. */ enum _status_groups { - kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ - kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ - kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ - kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ - kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ - kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ - kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ - kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ - kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ - kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ - kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ - kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ - kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ - kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ - kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ - kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ - kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ - kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ - kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ - kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ - kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ - kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ - kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ - kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ - kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ - kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ - kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ - kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ - kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ - kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ - kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ - kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ - kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ - kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ - kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ - kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ - kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ - kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ - kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ - kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ - kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ - kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ - kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ - kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ - kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ - kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ - kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ - kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ - kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ - kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ - kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ - kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ - kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ - kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ - kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ - kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ - kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ - kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ - kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ - kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ - kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ - kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ - kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ - kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ - kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ - kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ - kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ - kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ - kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ - kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ + kStatusGroup_Generic = 0, /*!< Group number for generic status codes. */ + kStatusGroup_FLASH = 1, /*!< Group number for FLASH status codes. */ + kStatusGroup_LPSPI = 4, /*!< Group number for LPSPI status codes. */ + kStatusGroup_FLEXIO_SPI = 5, /*!< Group number for FLEXIO SPI status codes. */ + kStatusGroup_DSPI = 6, /*!< Group number for DSPI status codes. */ + kStatusGroup_FLEXIO_UART = 7, /*!< Group number for FLEXIO UART status codes. */ + kStatusGroup_FLEXIO_I2C = 8, /*!< Group number for FLEXIO I2C status codes. */ + kStatusGroup_LPI2C = 9, /*!< Group number for LPI2C status codes. */ + kStatusGroup_UART = 10, /*!< Group number for UART status codes. */ + kStatusGroup_I2C = 11, /*!< Group number for UART status codes. */ + kStatusGroup_LPSCI = 12, /*!< Group number for LPSCI status codes. */ + kStatusGroup_LPUART = 13, /*!< Group number for LPUART status codes. */ + kStatusGroup_SPI = 14, /*!< Group number for SPI status code.*/ + kStatusGroup_XRDC = 15, /*!< Group number for XRDC status code.*/ + kStatusGroup_SEMA42 = 16, /*!< Group number for SEMA42 status code.*/ + kStatusGroup_SDHC = 17, /*!< Group number for SDHC status code */ + kStatusGroup_SDMMC = 18, /*!< Group number for SDMMC status code */ + kStatusGroup_SAI = 19, /*!< Group number for SAI status code */ + kStatusGroup_MCG = 20, /*!< Group number for MCG status codes. */ + kStatusGroup_SCG = 21, /*!< Group number for SCG status codes. */ + kStatusGroup_SDSPI = 22, /*!< Group number for SDSPI status codes. */ + kStatusGroup_FLEXIO_I2S = 23, /*!< Group number for FLEXIO I2S status codes */ + kStatusGroup_FLEXIO_MCULCD = 24, /*!< Group number for FLEXIO LCD status codes */ + kStatusGroup_FLASHIAP = 25, /*!< Group number for FLASHIAP status codes */ + kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */ + kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */ + kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */ + kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */ + kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */ + kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */ + kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */ + kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */ + kStatusGroup_PHY = 41, /*!< Group number for PHY status codes. */ + kStatusGroup_TRGMUX = 42, /*!< Group number for TRGMUX status codes. */ + kStatusGroup_SMARTCARD = 43, /*!< Group number for SMARTCARD status codes. */ + kStatusGroup_LMEM = 44, /*!< Group number for LMEM status codes. */ + kStatusGroup_QSPI = 45, /*!< Group number for QSPI status codes. */ + kStatusGroup_DMA = 50, /*!< Group number for DMA status codes. */ + kStatusGroup_EDMA = 51, /*!< Group number for EDMA status codes. */ + kStatusGroup_DMAMGR = 52, /*!< Group number for DMAMGR status codes. */ + kStatusGroup_FLEXCAN = 53, /*!< Group number for FlexCAN status codes. */ + kStatusGroup_LTC = 54, /*!< Group number for LTC status codes. */ + kStatusGroup_FLEXIO_CAMERA = 55, /*!< Group number for FLEXIO CAMERA status codes. */ + kStatusGroup_LPC_SPI = 56, /*!< Group number for LPC_SPI status codes. */ + kStatusGroup_LPC_USART = 57, /*!< Group number for LPC_USART status codes. */ + kStatusGroup_DMIC = 58, /*!< Group number for DMIC status codes. */ + kStatusGroup_SDIF = 59, /*!< Group number for SDIF status codes.*/ + kStatusGroup_SPIFI = 60, /*!< Group number for SPIFI status codes. */ + kStatusGroup_OTP = 61, /*!< Group number for OTP status codes. */ + kStatusGroup_MCAN = 62, /*!< Group number for MCAN status codes. */ + kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */ + kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */ + kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/ + kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/ + kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/ + kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/ + kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */ + kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */ + kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */ + kStatusGroup_PDM = 72, /*!< Group number for MIC status codes. */ + kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */ + kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */ + kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */ + kStatusGroup_LPC_MINISPI = 76, /*!< Group number for LPC_MINISPI status codes. */ + kStatusGroup_HASHCRYPT = 77, /*!< Group number for Hashcrypt status codes */ + kStatusGroup_LPC_SPI_SSP = 78, /*!< Group number for LPC_SPI_SSP status codes. */ + kStatusGroup_I3C = 79, /*!< Group number for I3C status codes */ + kStatusGroup_LPC_I2C_1 = 97, /*!< Group number for LPC_I2C_1 status codes. */ + kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */ + kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */ + kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */ - kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_IAP = 102, /*!< Group number for IAP status codes */ + kStatusGroup_SFA = 103, /*!< Group number for SFA status codes*/ + kStatusGroup_SPC = 104, /*!< Group number for SPC status codes. */ + kStatusGroup_PUF = 105, /*!< Group number for PUF status codes. */ + kStatusGroup_TOUCH_PANEL = 106, /*!< Group number for touch panel status codes */ - kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ - kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ - kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ - kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ - kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ - kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ - kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ - kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ - kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ - kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ - kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ - kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ - kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ - kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ - kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ - kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ - kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ - kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ - kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ - kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ - kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ - kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_HAL_GPIO = 121, /*!< Group number for HAL GPIO status codes. */ + kStatusGroup_HAL_UART = 122, /*!< Group number for HAL UART status codes. */ + kStatusGroup_HAL_TIMER = 123, /*!< Group number for HAL TIMER status codes. */ + kStatusGroup_HAL_SPI = 124, /*!< Group number for HAL SPI status codes. */ + kStatusGroup_HAL_I2C = 125, /*!< Group number for HAL I2C status codes. */ + kStatusGroup_HAL_FLASH = 126, /*!< Group number for HAL FLASH status codes. */ + kStatusGroup_HAL_PWM = 127, /*!< Group number for HAL PWM status codes. */ + kStatusGroup_HAL_RNG = 128, /*!< Group number for HAL RNG status codes. */ + kStatusGroup_HAL_I2S = 129, /*!< Group number for HAL I2S status codes. */ + kStatusGroup_TIMERMANAGER = 135, /*!< Group number for TiMER MANAGER status codes. */ + kStatusGroup_SERIALMANAGER = 136, /*!< Group number for SERIAL MANAGER status codes. */ + kStatusGroup_LED = 137, /*!< Group number for LED status codes. */ + kStatusGroup_BUTTON = 138, /*!< Group number for BUTTON status codes. */ + kStatusGroup_EXTERN_EEPROM = 139, /*!< Group number for EXTERN EEPROM status codes. */ + kStatusGroup_SHELL = 140, /*!< Group number for SHELL status codes. */ + kStatusGroup_MEM_MANAGER = 141, /*!< Group number for MEM MANAGER status codes. */ + kStatusGroup_LIST = 142, /*!< Group number for List status codes. */ + kStatusGroup_OSA = 143, /*!< Group number for OSA status codes. */ + kStatusGroup_COMMON_TASK = 144, /*!< Group number for Common task status codes. */ + kStatusGroup_MSG = 145, /*!< Group number for messaging status codes. */ + kStatusGroup_SDK_OCOTP = 146, /*!< Group number for OCOTP status codes. */ + kStatusGroup_SDK_FLEXSPINOR = 147, /*!< Group number for FLEXSPINOR status codes.*/ + kStatusGroup_CODEC = 148, /*!< Group number for codec status codes. */ + kStatusGroup_ASRC = 149, /*!< Group number for codec status ASRC. */ + kStatusGroup_OTFAD = 150, /*!< Group number for codec status codes. */ + kStatusGroup_SDIOSLV = 151, /*!< Group number for SDIOSLV status codes. */ + kStatusGroup_MECC = 152, /*!< Group number for MECC status codes. */ + kStatusGroup_ENET_QOS = 153, /*!< Group number for ENET_QOS status codes. */ + kStatusGroup_LOG = 154, /*!< Group number for LOG status codes. */ + kStatusGroup_I3CBUS = 155, /*!< Group number for I3CBUS status codes. */ + kStatusGroup_QSCI = 156, /*!< Group number for QSCI status codes. */ + kStatusGroup_SNT = 157, /*!< Group number for SNT status codes. */ + kStatusGroup_QUEUEDSPI = 158, /*!< Group number for QSPI status codes. */ + kStatusGroup_POWER_MANAGER = 159, /*!< Group number for POWER_MANAGER status codes. */ + kStatusGroup_IPED = 160, /*!< Group number for IPED status codes. */ + kStatusGroup_CSS_PKC = 161, /*!< Group number for CSS PKC status codes. */ + kStatusGroup_HOSTIF = 162, /*!< Group number for HOSTIF status codes. */ + kStatusGroup_CLIF = 163, /*!< Group number for CLIF status codes. */ + kStatusGroup_BMA = 164, /*!< Group number for BMA status codes. */ }; -/*! @brief Generic status return codes. */ -enum _generic_status +/*! \public + * @brief Generic status return codes. + */ +enum { - kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), - kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), - kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), - kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), - kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), - kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), - kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6), + kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< Generic status for Success. */ + kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< Generic status for Fail. */ + kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< Generic status for read only failure. */ + kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< Generic status for out of range access. */ + kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Generic status for invalid argument check. */ + kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5), /*!< Generic status for timeout. */ + kStatus_NoTransferInProgress = + MAKE_STATUS(kStatusGroup_Generic, 6), /*!< Generic status for no transfer in progress. */ + kStatus_Busy = MAKE_STATUS(kStatusGroup_Generic, 7), /*!< Generic status for module is busy. */ + kStatus_NoData = + MAKE_STATUS(kStatusGroup_Generic, 8), /*!< Generic status for no data is found for the operation. */ }; /*! @brief Type used for all status and error return values. */ typedef int32_t status_t; -/* - * Macro guard for whether to use default weak IRQ implementation in drivers +/*! + * @name Min/max macros + * @{ */ -#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ -#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1 -#endif - -/*! @name Min/max macros */ -/* @{ */ #if !defined(MIN) #define MIN(a, b) (((a) < (b)) ? (a) : (b)) #endif @@ -204,389 +247,57 @@ typedef int32_t status_t; #endif /* @} */ -/*! @name Timer utilities */ -/* @{ */ -/*! Macro to convert a microsecond period to raw count value */ -#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)((uint64_t)us * clockFreqInHz / 1000000U) -/*! Macro to convert a raw count value to microsecond */ -#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz) - -/*! Macro to convert a millisecond period to raw count value */ -#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U) -/*! Macro to convert a raw count value to millisecond */ -#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz) -/* @} */ - -/*! @name Alignment variable definition macros */ -/* @{ */ -#if (defined(__ICCARM__)) -/** - * Workaround to disable MISRA C message suppress warnings for IAR compiler. - * http://supp.iar.com/Support/?note=24725 - */ -_Pragma("diag_suppress=Pm120") -#define SDK_PRAGMA(x) _Pragma(#x) - _Pragma("diag_error=Pm120") -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var -#endif -#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var -#endif -#elif defined(__GNUC__) -/*! Macro to define a variable with alignbytes alignment */ -#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -/*! Macro to define a variable with L1 d-cache line size alignment */ -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) -#endif -/*! Macro to define a variable with L2 cache line size alignment */ -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) -#endif -#else -#error Toolchain not supported -#define SDK_ALIGN(var, alignbytes) var -#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) -#define SDK_L1DCACHE_ALIGN(var) var -#endif -#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) -#define SDK_L2CACHE_ALIGN(var) var -#endif -#endif - -/*! Macro to change a value to a given size aligned value */ -#define SDK_SIZEALIGN(var, alignbytes) \ - ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1))) -/* @} */ - -/*! @name Non-cacheable region definition macros */ -/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or - * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables, - * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables - * will be initialized to zero in system startup. +/*! @name Suppress fallthrough warning macro */ +/* For switch case code block, if case section ends without "break;" statement, there wil be + fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc. + To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each + case section which misses "break;"statement. */ /* @{ */ -#if (defined(__ICCARM__)) -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) -#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" -#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) +#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough)) #else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var -#endif -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var -#endif -#elif(defined(__GNUC__)) -/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" - * in your projects to make sure the non-cacheable section variables will be initialized in system startup. - */ -#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) -#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ - __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ - __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) -#else -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes))) -#endif -#else -#error Toolchain not supported. -#define AT_NONCACHEABLE_SECTION(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var -#define AT_NONCACHEABLE_SECTION_INIT(var) var -#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var +#define SUPPRESS_FALL_THROUGH_WARNING() #endif /* @} */ -/*! @name Time sensitive region */ -/* @{ */ -#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" -#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func -#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -#else -#if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func -#define AT_QUICKACCESS_SECTION_DATA(func) func -#else -#error Toolchain not supported. -#endif -#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */ -/* @} */ - -/*! @name Ram Function */ -#if (defined(__ICCARM__)) -#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" -#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#elif(defined(__GNUC__)) -#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func -#else -#error Toolchain not supported. -#endif /* defined(__ICCARM__) */ -/* @} */ - -/* - * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t - * defined in previous of this file. - */ -#include "fsl_clock.h" - -/* - * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral - */ -#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ - (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) -#include "fsl_reset.h" -#endif - /******************************************************************************* * API ******************************************************************************/ #if defined(__cplusplus) - extern "C" -{ +extern "C" { #endif - /*! - * @brief Enable specific interrupt. - * - * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt enabled successfully - * @retval kStatus_Fail Failed to enable the interrupt - */ - static inline status_t EnableIRQ(IRQn_Type interrupt) - { - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } +#if !((defined(__DSC__) && defined(__CW__))) +/*! + * @brief Allocate memory with given alignment and aligned size. + * + * This is provided to support the dynamically allocated memory + * used in cache-able region. + * @param size The length required to malloc. + * @param alignbytes The alignment size. + * @retval The allocated memory. + */ +void *SDK_Malloc(size_t size, size_t alignbytes); -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } +/*! + * @brief Free memory. + * + * @param ptr The memory to be release. + */ +void SDK_Free(void *ptr); #endif -#if defined(__GIC_PRIO_BITS) - GIC_EnableIRQ(interrupt); -#else - NVIC_EnableIRQ(interrupt); -#endif - return kStatus_Success; - } - - /*! - * @brief Disable specific interrupt. - * - * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt - * levels. For example, there are NVIC and intmux. Here the interrupts connected - * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. - * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed - * to NVIC first then routed to core. - * - * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts - * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. - * - * @param interrupt The IRQ number. - * @retval kStatus_Success Interrupt disabled successfully - * @retval kStatus_Fail Failed to disable the interrupt - */ - static inline status_t DisableIRQ(IRQn_Type interrupt) - { - if (NotAvail_IRQn == interrupt) - { - return kStatus_Fail; - } - -#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) - { - return kStatus_Fail; - } -#endif - -#if defined(__GIC_PRIO_BITS) - GIC_DisableIRQ(interrupt); -#else - NVIC_DisableIRQ(interrupt); -#endif - return kStatus_Success; - } - - /*! - * @brief Disable the global IRQ - * - * Disable the global interrupt and return the current primask register. User is required to provided the primask - * register for the EnableGlobalIRQ(). - * - * @return Current primask value. - */ - static inline uint32_t DisableGlobalIRQ(void) - { -#if defined (__XCC__) - return 0; -#else -#if defined(CPSR_I_Msk) - uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; - - __disable_irq(); - - return cpsr; -#else - uint32_t regPrimask = __get_PRIMASK(); - - __disable_irq(); - - return regPrimask; -#endif -#endif - } - - /*! - * @brief Enable the global IRQ - * - * Set the primask register with the provided primask value but not just enable the primask. The idea is for the - * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to - * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. - * - * @param primask value of primask register to be restored. The primask value is supposed to be provided by the - * DisableGlobalIRQ(). - */ - static inline void EnableGlobalIRQ(uint32_t primask) - { -#if defined (__XCC__) -#else -#if defined(CPSR_I_Msk) - __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); -#else - __set_PRIMASK(primask); -#endif -#endif - } - -#if defined(ENABLE_RAM_VECTOR_TABLE) - /*! - * @brief install IRQ handler - * - * @param irq IRQ number - * @param irqHandler IRQ handler address - * @return The old IRQ handler address - */ - uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); -#endif /* ENABLE_RAM_VECTOR_TABLE. */ - -#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) - /*! - * @brief Enable specific interrupt for wake-up from deep-sleep mode. - * - * Enable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ - void EnableDeepSleepIRQ(IRQn_Type interrupt); - - /*! - * @brief Disable specific interrupt for wake-up from deep-sleep mode. - * - * Disable the interrupt for wake-up from deep sleep mode. - * Some interrupts are typically used in sleep mode only and will not occur during - * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable - * those clocks (significantly increasing power consumption in the reduced power mode), - * making these wake-ups possible. - * - * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). - * - * @param interrupt The IRQ number. - */ - void DisableDeepSleepIRQ(IRQn_Type interrupt); -#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ - - /*! - * @brief Allocate memory with given alignment and aligned size. - * - * This is provided to support the dynamically allocated memory - * used in cache-able region. - * @param size The length required to malloc. - * @param alignbytes The alignment size. - * @retval The allocated memory. - */ - void *SDK_Malloc(size_t size, size_t alignbytes); - - /*! - * @brief Free memory. - * - * @param ptr The memory to be release. - */ - void SDK_Free(void *ptr); +/*! + * @brief Delay at least for some time. + * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, + * if precise delay count was needed, please implement a new delay function with hardware timer. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); #if defined(__cplusplus) } @@ -594,4 +305,12 @@ _Pragma("diag_suppress=Pm120") /*! @} */ +#if (defined(__DSC__) && defined(__CW__)) +#include "fsl_common_dsc.h" +#elif defined(__XCC__) +#include "fsl_common_dsp.h" +#else +#include "fsl_common_arm.h" +#endif + #endif /* _FSL_COMMON_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.c new file mode 100644 index 0000000000..e77a265ce4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.c @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.common_arm" +#endif + +#ifndef __GIC_PRIO_BITS +#if defined(ENABLE_RAM_VECTOR_TABLE) +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) +{ +#ifdef __VECTOR_TABLE +#undef __VECTOR_TABLE +#endif + +/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$VECTOR_ROM$$Base[]; + extern uint32_t Image$$VECTOR_RAM$$Base[]; + extern uint32_t Image$$RW_m_data$$Base[]; + +#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base +#define __VECTOR_RAM Image$$VECTOR_RAM$$Base +#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) +#elif defined(__ICCARM__) + extern uint32_t __RAM_VECTOR_TABLE_SIZE[]; + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; +#elif defined(__GNUC__) + extern uint32_t __VECTOR_TABLE[]; + extern uint32_t __VECTOR_RAM[]; + extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[]; + uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES); +#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */ + uint32_t n; + uint32_t ret; + uint32_t irqMaskValue; + + irqMaskValue = DisableGlobalIRQ(); + if (SCB->VTOR != (uint32_t)__VECTOR_RAM) + { + /* Copy the vector table from ROM to RAM */ + for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++) + { + __VECTOR_RAM[n] = __VECTOR_TABLE[n]; + } + /* Point the VTOR to the position of vector table */ + SCB->VTOR = (uint32_t)__VECTOR_RAM; + } + + ret = __VECTOR_RAM[(int32_t)irq + 16]; + /* make sure the __VECTOR_RAM is noncachable */ + __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; + + EnableGlobalIRQ(irqMaskValue); + + return ret; +} +#endif /* ENABLE_RAM_VECTOR_TABLE. */ +#endif /* __GIC_PRIO_BITS. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + +/* + * When the SYSCON STARTER registers are discontinuous, these functions are + * implemented in fsl_power.c. + */ +#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) + +void EnableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERSET[index] = 1UL << intNumber; + (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ +} + +void DisableDeepSleepIRQ(IRQn_Type interrupt) +{ + uint32_t intNumber = (uint32_t)interrupt; + + (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + uint32_t index = 0; + + while (intNumber >= 32u) + { + index++; + intNumber -= 32u; + } + + SYSCON->STARTERCLR[index] = 1UL << intNumber; +} +#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) +/* Use WDT. */ +static void enableCpuCycleCounter(void) +{ + /* Make sure the DWT trace fucntion is enabled. */ + if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) + { + CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk; + } + + /* CYCCNT not supported on this device. */ + assert(DWT_CTRL_NOCYCCNT_Msk != (DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk)); + + /* Read CYCCNT directly if CYCCENT has already been enabled, otherwise enable CYCCENT first. */ + if (DWT_CTRL_CYCCNTENA_Msk != (DWT_CTRL_CYCCNTENA_Msk & DWT->CTRL)) + { + DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk; + } +} + +static uint32_t getCpuCycleCount(void) +{ + return DWT->CYCCNT; +} +#else /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ +/* Use software loop. */ +#if defined(__CC_ARM) /* This macro is arm v5 specific */ +/* clang-format off */ +__ASM static void DelayLoop(uint32_t count) +{ +loop + SUBS R0, R0, #1 + CMP R0, #0 + BNE loop + BX LR +} +/* clang-format on */ +#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__) +/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler, + * use SUB and CMP here for compatibility */ +static void DelayLoop(uint32_t count) +{ + __ASM volatile(" MOV R0, %0" : : "r"(count)); + __ASM volatile( + "loop: \n" +#if defined(__GNUC__) && !defined(__ARMCC_VERSION) + " SUB R0, R0, #1 \n" +#else + " SUBS R0, R0, #1 \n" +#endif + " CMP R0, #0 \n" + + " BNE loop \n" + : + : + : "r0"); +} +#endif /* defined(__CC_ARM) */ +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + +/*! + * @brief Delay at least for some time. + * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports + * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. + * + * @param delayTime_us Delay time in unit of microsecond. + * @param coreClock_Hz Core clock frequency with Hz. + */ +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) +{ + uint64_t count; + + if (delayTime_us > 0U) + { + count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); + + assert(count <= UINT32_MAX); + +#if defined(SDK_DELAY_USE_DWT) && defined(DWT) /* Use DWT for better accuracy */ + + enableCpuCycleCounter(); + /* Calculate the count ticks. */ + count += getCpuCycleCount(); + + if (count > UINT32_MAX) + { + count -= UINT32_MAX; + /* Wait for cyccnt overflow. */ + while (count < getCpuCycleCount()) + { + } + } + + /* Wait for cyccnt reach count value. */ + while (count > getCpuCycleCount()) + { + } +#else + /* Divide value may be different in various environment to ensure delay is precise. + * Every loop count includes three instructions, due to Cortex-M7 sometimes executes + * two instructions in one period, through test here set divide 1.5. Other M cores use + * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does + * not matter because other instructions outside while loop is enough to fill the time. + */ +#if (__CORTEX_M == 7) + count = count / 3U * 2U; +#else + count = count / 4U; +#endif + DelayLoop((uint32_t)count); +#endif /* defined(SDK_DELAY_USE_DWT) && defined(DWT) */ + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.h new file mode 100644 index 0000000000..2678ff625c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_common_arm.h @@ -0,0 +1,671 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_COMMON_ARM_H_ +#define _FSL_COMMON_ARM_H_ + +/* + * For CMSIS pack RTE. + * CMSIS pack RTE generates "RTC_Components.h" which contains the statements + * of the related element for all selected software components. + */ +#ifdef _RTE_ +#include "RTE_Components.h" +#endif + +/*! + * @addtogroup ksdk_common + * @{ + */ + +/*! @name Atomic modification + * + * These macros are used for atomic access, such as read-modify-write + * to the peripheral registers. + * + * - SDK_ATOMIC_LOCAL_ADD + * - SDK_ATOMIC_LOCAL_SET + * - SDK_ATOMIC_LOCAL_CLEAR + * - SDK_ATOMIC_LOCAL_TOGGLE + * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET + * + * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr + * means the address of the peripheral register or variable you want to modify + * atomically, the parameter @c clearBits is the bits to clear, the parameter + * @c setBits it the bits to set. + * For example, to set a 32-bit register bit1:bit0 to 0b10, use like this: + * + * @code + volatile uint32_t * reg = (volatile uint32_t *)REG_ADDR; + + SDK_ATOMIC_LOCAL_CLEAR_AND_SET(reg, 0x03, 0x02); + @endcode + * + * In this example, the register bit1:bit0 are cleared and bit1 is set, as a result, + * register bit1:bit0 = 0b10. + * + * @note For the platforms don't support exclusive load and store, these macros + * disable the global interrupt to pretect the modification. + * + * @note These macros only guarantee the local processor atomic operations. For + * the multi-processor devices, use hardware semaphore such as SEMA42 to + * guarantee exclusive access if necessary. + * + * @{ + */ + +/* clang-format off */ +#if ((defined(__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined(__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined(__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined(__ARM_ARCH_8M_BASE__) && (__ARM_ARCH_8M_BASE__ == 1))) +/* clang-format on */ + +/* If the LDREX and STREX are supported, use them. */ +#define _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXB(addr); \ + (ops); \ + } while (0UL != __STREXB((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXH(addr); \ + (ops); \ + } while (0UL != __STREXH((val), (addr))) + +#define _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, val, ops) \ + do \ + { \ + (val) = __LDREXW(addr); \ + (ops); \ + } while (0UL != __STREXW((val), (addr))) + +static inline void _SDK_AtomicLocalAdd1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalAdd4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val += val); +} + +static inline void _SDK_AtomicLocalSub1Byte(volatile uint8_t *addr, uint8_t val) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub2Byte(volatile uint16_t *addr, uint16_t val) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSub4Byte(volatile uint32_t *addr, uint32_t val) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val -= val); +} + +static inline void _SDK_AtomicLocalSet1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalSet4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val |= bits); +} + +static inline void _SDK_AtomicLocalClear1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalClear4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val &= ~bits); +} + +static inline void _SDK_AtomicLocalToggle1Byte(volatile uint8_t *addr, uint8_t bits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle2Byte(volatile uint16_t *addr, uint16_t bits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalToggle4Byte(volatile uint32_t *addr, uint32_t bits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val ^= bits); +} + +static inline void _SDK_AtomicLocalClearAndSet1Byte(volatile uint8_t *addr, uint8_t clearBits, uint8_t setBits) +{ + uint8_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_1BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet2Byte(volatile uint16_t *addr, uint16_t clearBits, uint16_t setBits) +{ + uint16_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_2BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uint32_t clearBits, uint32_t setBits) +{ + uint32_t s_val; + + _SDK_ATOMIC_LOCAL_OPS_4BYTE(addr, s_val, s_val = (s_val & ~clearBits) | setBits); +} + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalAdd1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(val)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalAdd2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(val)) : \ + _SDK_AtomicLocalAdd4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(val)))) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? _SDK_AtomicLocalSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClear2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalClear4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(bits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalToggle2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(bits)) : \ + _SDK_AtomicLocalToggle4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(bits)))) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + ((1UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet1Byte((volatile uint8_t *)(volatile void *)(addr), (uint8_t)(clearBits), (uint8_t)(setBits)) : \ + ((2UL == sizeof(*(addr))) ? \ + _SDK_AtomicLocalClearAndSet2Byte((volatile uint16_t *)(volatile void *)(addr), (uint16_t)(clearBits), (uint16_t)(setBits)) : \ + _SDK_AtomicLocalClearAndSet4Byte((volatile uint32_t *)(volatile void *)(addr), (uint32_t)(clearBits), (uint32_t)(setBits)))) +#else + +#define SDK_ATOMIC_LOCAL_ADD(addr, val) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) += (val); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_SET(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) |= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) &= ~(bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) ^= (bits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \ + do \ + { \ + uint32_t s_atomicOldInt; \ + s_atomicOldInt = DisableGlobalIRQ(); \ + *(addr) = (*(addr) & ~(clearBits)) | (setBits); \ + EnableGlobalIRQ(s_atomicOldInt); \ + } while (0) + +#endif +/* @} */ + +/*! @name Timer utilities */ +/* @{ */ +/*! Macro to convert a microsecond period to raw count value */ +#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U) +/*! Macro to convert a raw count value to microsecond */ +#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000000U / (clockFreqInHz)) + +/*! Macro to convert a millisecond period to raw count value */ +#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U) +/*! Macro to convert a raw count value to millisecond */ +#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz)) +/* @} */ + +/*! @name ISR exit barrier + * @{ + * + * ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping + * exception return operation might vector to incorrect interrupt. + * For Cortex-M7, if core speed much faster than peripheral register write speed, + * the peripheral interrupt flags may be still set after exiting ISR, this results to + * the same error similar with errata 83869. + */ +#if (defined __CORTEX_M) && ((__CORTEX_M == 4U) || (__CORTEX_M == 7U)) +#define SDK_ISR_EXIT_BARRIER __DSB() +#else +#define SDK_ISR_EXIT_BARRIER +#endif + +/* @} */ + +/*! @name Alignment variable definition macros */ +/* @{ */ +#if (defined(__ICCARM__)) +/* + * Workaround to disable MISRA C message suppress warnings for IAR compiler. + * http:/ /supp.iar.com/Support/?note=24725 + */ +_Pragma("diag_suppress=Pm120") +#define SDK_PRAGMA(x) _Pragma(#x) + _Pragma("diag_error=Pm120") +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var +#elif defined(__GNUC__) +/*! Macro to define a variable with alignbytes alignment */ +#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported +#endif + +/*! Macro to define a variable with L1 d-cache line size alignment */ +#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#define SDK_L1DCACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) +#endif +/*! Macro to define a variable with L2 cache line size alignment */ +#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#define SDK_L2CACHE_ALIGN(var) SDK_ALIGN(var, FSL_FEATURE_L2CACHE_LINESIZE_BYTE) +#endif + +/*! Macro to change a value to a given size aligned value */ +#define SDK_SIZEALIGN(var, alignbytes) \ + ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U))) +/* @} */ + +/*! @name Non-cacheable region definition macros */ +/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or + * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable + * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, + * these zero-inited variables will be initialized to zero in system startup. + */ +/* @{ */ + +#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \ + defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE)) + +#if (defined(__ICCARM__)) +#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable" +#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init" +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init" + +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var +#if (defined(__CC_ARM)) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var +#else +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var +#endif + +#elif (defined(__GNUC__)) +/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA" + * in your projects to make sure the non-cacheable section variables will be initialized in system startup. + */ +#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \ + __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes))) +#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \ + __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif + +#else + +#define AT_NONCACHEABLE_SECTION(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_ALIGN(var, alignbytes) +#define AT_NONCACHEABLE_SECTION_INIT(var) var +#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_ALIGN(var, alignbytes) + +#endif + +/* @} */ + +/*! + * @name Time sensitive region + * @{ + */ +#if (defined(__ICCARM__)) +#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA(var) var @"DataQuickAccess" +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + SDK_PRAGMA(data_alignment = alignbytes) var @"DataQuickAccess" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var +#elif (defined(__GNUC__)) +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_DATA(var) __attribute__((section("DataQuickAccess"))) var +#define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \ + __attribute__((section("DataQuickAccess"))) var __attribute__((aligned(alignbytes))) +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ + +/*! @name Ram Function */ +#if (defined(__ICCARM__)) +#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction" +#elif (defined(__CC_ARM) || defined(__ARMCC_VERSION)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#elif (defined(__GNUC__)) +#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func +#else +#error Toolchain not supported. +#endif /* defined(__ICCARM__) */ +/* @} */ + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + void DefaultISR(void); +#endif + +/* + * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t + * defined in previous of this file. + */ +#include "fsl_clock.h" + +/* + * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral + */ +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \ + (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0))) +#include "fsl_reset.h" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief Enable specific interrupt. + * + * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt enabled successfully + * @retval kStatus_Fail Failed to enable the interrupt + */ +static inline status_t EnableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_EnableIRQ(interrupt); +#else + NVIC_EnableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable specific interrupt. + * + * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt + * levels. For example, there are NVIC and intmux. Here the interrupts connected + * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly. + * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed + * to NVIC first then routed to core. + * + * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts + * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS. + * + * @param interrupt The IRQ number. + * @retval kStatus_Success Interrupt disabled successfully + * @retval kStatus_Fail Failed to disable the interrupt + */ +static inline status_t DisableIRQ(IRQn_Type interrupt) +{ + status_t status = kStatus_Success; + + if (NotAvail_IRQn == interrupt) + { + status = kStatus_Fail; + } + +#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + { + status = kStatus_Fail; + } +#endif + + else + { +#if defined(__GIC_PRIO_BITS) + GIC_DisableIRQ(interrupt); +#else + NVIC_DisableIRQ(interrupt); +#endif + } + + return status; +} + +/*! + * @brief Disable the global IRQ + * + * Disable the global interrupt and return the current primask register. User is required to provided the primask + * register for the EnableGlobalIRQ(). + * + * @return Current primask value. + */ +static inline uint32_t DisableGlobalIRQ(void) +{ +#if defined(CPSR_I_Msk) + uint32_t cpsr = __get_CPSR() & CPSR_I_Msk; + + __disable_irq(); + + return cpsr; +#else + uint32_t regPrimask = __get_PRIMASK(); + + __disable_irq(); + + return regPrimask; +#endif +} + +/*! + * @brief Enable the global IRQ + * + * Set the primask register with the provided primask value but not just enable the primask. The idea is for the + * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to + * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair. + * + * @param primask value of primask register to be restored. The primask value is supposed to be provided by the + * DisableGlobalIRQ(). + */ +static inline void EnableGlobalIRQ(uint32_t primask) +{ +#if defined(CPSR_I_Msk) + __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask); +#else + __set_PRIMASK(primask); +#endif +} + +#if defined(ENABLE_RAM_VECTOR_TABLE) +/*! + * @brief install IRQ handler + * + * @param irq IRQ number + * @param irqHandler IRQ handler address + * @return The old IRQ handler address + */ +uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler); +#endif /* ENABLE_RAM_VECTOR_TABLE. */ + +#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) +/*! + * @brief Enable specific interrupt for wake-up from deep-sleep mode. + * + * Enable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void EnableDeepSleepIRQ(IRQn_Type interrupt); + +/*! + * @brief Disable specific interrupt for wake-up from deep-sleep mode. + * + * Disable the interrupt for wake-up from deep sleep mode. + * Some interrupts are typically used in sleep mode only and will not occur during + * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable + * those clocks (significantly increasing power consumption in the reduced power mode), + * making these wake-ups possible. + * + * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly). + * + * @param interrupt The IRQ number. + */ +void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/*! @} */ + +#endif /* _FSL_COMMON_ARM_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.c index 4e88cf5c6d..c73f84997a 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2017, 2019-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -57,7 +57,7 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config) #endif /* configure CRC module and write the seed */ - base->MODE = 0 | CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | + base->MODE = CRC_MODE_CRC_POLY(config->polynomial) | CRC_MODE_BIT_RVS_WR(config->reverseIn) | CRC_MODE_CMPL_WR(config->complementIn) | CRC_MODE_BIT_RVS_SUM(config->reverseOut) | CRC_MODE_CMPL_SUM(config->complementOut); base->SEED = config->seed; @@ -81,7 +81,7 @@ void CRC_Init(CRC_Type *base, const crc_config_t *config) void CRC_GetDefaultConfig(crc_config_t *config) { /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); static const crc_config_t default_config = {CRC_DRIVER_DEFAULT_POLYNOMIAL, CRC_DRIVER_DEFAULT_REVERSE_IN, CRC_DRIVER_DEFAULT_COMPLEMENT_IN, CRC_DRIVER_DEFAULT_REVERSE_OUT, @@ -102,6 +102,18 @@ void CRC_Reset(CRC_Type *base) CRC_Init(base, &config); } +/*! + * brief Write seed (initial checksum) to CRC peripheral module. + * + * param base CRC peripheral address. + * param seed CRC Seed value. + */ +void CRC_WriteSeed(CRC_Type *base, uint32_t seed) +{ + /* write the seed (initial checksum) */ + base->SEED = seed; +} + /*! * brief Loads actual values configured in CRC peripheral to CRC protocol configuration structure. * @@ -113,8 +125,9 @@ void CRC_Reset(CRC_Type *base) void CRC_GetConfig(CRC_Type *base, crc_config_t *config) { /* extract CRC mode settings */ - uint32_t mode = base->MODE; - config->polynomial = (crc_polynomial_t)((mode & CRC_MODE_CRC_POLY_MASK) >> CRC_MODE_CRC_POLY_SHIFT); + uint32_t mode = base->MODE; + config->polynomial = + (crc_polynomial_t)(uint32_t)(((uint32_t)(mode & CRC_MODE_CRC_POLY_MASK)) >> CRC_MODE_CRC_POLY_SHIFT); config->reverseIn = (bool)(mode & CRC_MODE_BIT_RVS_WR_MASK); config->complementIn = (bool)(mode & CRC_MODE_CMPL_WR_MASK); config->reverseOut = (bool)(mode & CRC_MODE_BIT_RVS_SUM_MASK); @@ -144,7 +157,7 @@ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) const uint32_t *data32; /* 8-bit reads and writes till source address is aligned 4 bytes */ - while ((dataSize) && ((uint32_t)data & 3U)) + while ((0U != dataSize) && (0U != ((uint32_t)data & 3U))) { *((__O uint8_t *)&(base->WR_DATA)) = *data; data++; @@ -152,7 +165,7 @@ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) } /* use 32-bit reads and writes as long as possible */ - data32 = (const uint32_t *)data; + data32 = (const uint32_t *)(uint32_t)data; while (dataSize >= sizeof(uint32_t)) { *((__O uint32_t *)&(base->WR_DATA)) = *data32; @@ -163,7 +176,7 @@ void CRC_WriteData(CRC_Type *base, const uint8_t *data, size_t dataSize) data = (const uint8_t *)data32; /* 8-bit reads and writes till end of data buffer */ - while (dataSize) + while (0U != dataSize) { *((__O uint8_t *)&(base->WR_DATA)) = *data; data++; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.h index 0ef6b700ec..08e08bd57d 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_crc.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2017, 2019-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -24,17 +24,23 @@ /*! @name Driver version */ /*@{*/ -/*! @brief CRC driver version. Version 2.0.1. +/*! @brief CRC driver version. Version 2.1.1. * - * Current version: 2.0.1 + * Current version: 2.1.1 * * Change log: * - Version 2.0.0 * - initial version * - Version 2.0.1 * - add explicit type cast when writing to WR_DATA + * - Version 2.0.2 + * - Fix MISRA issue + * - Version 2.1.0 + * - Add CRC_WriteSeed function + * - Version 2.1.1 + * - Fix MISRA issue */ -#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +#define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*@}*/ #ifndef CRC_DRIVER_CUSTOM_DEFAULTS @@ -106,6 +112,14 @@ static inline void CRC_Deinit(CRC_Type *base) */ void CRC_Reset(CRC_Type *base); +/*! + * @brief Write seed to CRC peripheral module. + * + * @param base CRC peripheral address. + * @param seed CRC Seed value. + */ +void CRC_WriteSeed(CRC_Type *base, uint32_t seed); + /*! * @brief Loads default values to CRC protocol configuration structure. * diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c index 590ab321c6..e53bebdd01 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -25,6 +25,13 @@ */ static uint32_t CTIMER_GetInstance(CTIMER_Type *base); +/*! + * @brief CTIMER generic IRQ handle function. + * + * @param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index); + /******************************************************************************* * Variables ******************************************************************************/ @@ -49,10 +56,11 @@ static const reset_ip_name_t s_ctimerResets[] = CTIMER_RSTS; #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /*! @brief Pointers real ISRs installed by drivers for each instance. */ -static ctimer_callback_t *s_ctimerCallback[FSL_FEATURE_SOC_CTIMER_COUNT] = {0}; +static ctimer_callback_t *s_ctimerCallback[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = {0}; /*! @brief Callback type installed by drivers for each instance. */ -static ctimer_callback_type_t ctimerCallbackType[FSL_FEATURE_SOC_CTIMER_COUNT] = {kCTIMER_SingleCallback}; +static ctimer_callback_type_t ctimerCallbackType[sizeof(s_ctimerBases) / sizeof(s_ctimerBases[0])] = { + kCTIMER_SingleCallback}; /*! @brief Array to map timer instance to IRQ number. */ static const IRQn_Type s_ctimerIRQ[] = CTIMER_IRQS; @@ -89,7 +97,7 @@ static uint32_t CTIMER_GetInstance(CTIMER_Type *base) */ void CTIMER_Init(CTIMER_Type *base, const ctimer_config_t *config) { - assert(config); + assert(config != NULL); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the timer clock*/ @@ -128,7 +136,7 @@ void CTIMER_Deinit(CTIMER_Type *base) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Disable IRQ at NVIC Level */ - DisableIRQ(s_ctimerIRQ[index]); + (void)DisableIRQ(s_ctimerIRQ[index]); } /*! @@ -144,10 +152,10 @@ void CTIMER_Deinit(CTIMER_Type *base) */ void CTIMER_GetDefaultConfig(ctimer_config_t *config) { - assert(config); + assert(config != NULL); /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); /* Run as a timer */ config->mode = kCTIMER_TimerMode; @@ -162,83 +170,87 @@ void CTIMER_GetDefaultConfig(ctimer_config_t *config) * * Enables PWM mode on the match channel passed in and will then setup the match value * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. + * This function can manually assign the specified channel to set the PWM cycle. * * note When setting PWM output from multiple output pins, all should use the same PWM * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. * * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period * param matchChannel Match pin to be used to output the PWM signal * param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 * param pwmFreq_Hz PWM signal frequency in Hz * param srcClock_Hz Timer counter clock in Hz * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated + * if it is 0 then no interrupt will be generated. * * return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM cycle */ status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint8_t dutyCyclePercent, uint32_t pwmFreq_Hz, uint32_t srcClock_Hz, bool enableInt) { - assert(pwmFreq_Hz > 0); + assert(pwmFreq_Hz > 0U); uint32_t reg; uint32_t period, pulsePeriod = 0; - uint32_t timerClock = srcClock_Hz / (base->PR + 1); + uint32_t timerClock = srcClock_Hz / (base->PR + 1U); uint32_t index = CTIMER_GetInstance(base); - if (matchChannel == kCTIMER_Match_3) + if (matchChannel == pwmPeriodChannel) { return kStatus_Fail; } - /* Enable PWM mode on the channel */ - base->PWMC |= (1U << matchChannel); + /* Enable PWM mode on the match channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); /* Clear the stop, reset and interrupt bits for this channel */ reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + reg &= + ~(((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK)) + << ((uint32_t)matchChannel * 3U)); /* If call back function is valid then enable match interrupt for the channel */ if (enableInt) { - reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); } - /* Reset the counter when match on channel 3 */ - reg |= CTIMER_MCR_MR3R_MASK; + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); base->MCR = reg; /* Calculate PWM period match value */ - period = (timerClock / pwmFreq_Hz) - 1; + period = (timerClock / pwmFreq_Hz) - 1U; /* Calculate pulse width match value */ - if (dutyCyclePercent == 0) + if (dutyCyclePercent == 0U) { - pulsePeriod = period + 1; + pulsePeriod = period + 1U; } else { - pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; } - /* Match on channel 3 will define the PWM period */ - base->MR[kCTIMER_Match_3] = period; + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = period; /* This will define the PWM pulse period */ base->MR[matchChannel] = pulsePeriod; /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); /* If call back function is valid then enable interrupt and update the call back function */ if (enableInt) { - EnableIRQ(s_ctimerIRQ[index]); + (void)EnableIRQ(s_ctimerIRQ[index]); } return kStatus_Success; @@ -249,23 +261,28 @@ status_t CTIMER_SetupPwm(CTIMER_Type *base, * * Enables PWM mode on the match channel passed in and will then setup the match value * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. + * This function can manually assign the specified channel to set the PWM cycle. * * note When setting PWM output from multiple output pins, all should use the same PWM * period * * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period * param matchChannel Match pin to be used to output the PWM signal * param pwmPeriod PWM period match value * param pulsePeriod Pulse width match value * param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated + * if it is 0 then no interrupt will be generated. * * return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period + * kStatus_Fail If matchChannel is equal to pwmPeriodChannel; this channel is reserved to set the PWM period */ -status_t CTIMER_SetupPwmPeriod( - CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt) +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt) { /* Some CTimers only have 16bits , so the value is limited*/ #if defined(FSL_FEATURE_SOC_CTIMER16B) && FSL_FEATURE_SOC_CTIMER16B @@ -275,40 +292,42 @@ status_t CTIMER_SetupPwmPeriod( uint32_t reg; uint32_t index = CTIMER_GetInstance(base); - if (matchChannel == kCTIMER_Match_3) + if (matchChannel == pwmPeriodChannel) { return kStatus_Fail; } - /* Enable PWM mode on the channel */ - base->PWMC |= (1U << matchChannel); + /* Enable PWM mode on PWM pulse channel */ + base->PWMC |= (1UL << (uint32_t)matchChannel); - /* Clear the stop, reset and interrupt bits for this channel */ + /* Clear the stop, reset and interrupt bits for PWM pulse channel */ reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); - /* If call back function is valid then enable match interrupt for the channel */ + /* If call back function is valid then enable match interrupt for PWM pulse channel */ if (enableInt) { - reg |= (CTIMER_MCR_MR0I_MASK << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + reg |= (((uint32_t)CTIMER_MCR_MR0I_MASK) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); } - /* Reset the counter when match on channel 3 */ - reg |= CTIMER_MCR_MR3R_MASK; + /* Reset the counter when match on PWM period channel (pwmPeriodChannel) */ + reg |= ((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK) << ((uint32_t)pwmPeriodChannel * 3U)); base->MCR = reg; - /* Match on channel 3 will define the PWM period */ - base->MR[kCTIMER_Match_3] = pwmPeriod; + /* Specified channel pwmPeriodChannel will define the PWM period */ + base->MR[pwmPeriodChannel] = pwmPeriod; /* This will define the PWM pulse period */ base->MR[matchChannel] = pulsePeriod; /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); /* If call back function is valid then enable interrupt and update the call back function */ if (enableInt) { - EnableIRQ(s_ctimerIRQ[index]); + (void)EnableIRQ(s_ctimerIRQ[index]); } return kStatus_Success; @@ -317,30 +336,32 @@ status_t CTIMER_SetupPwmPeriod( /*! * brief Updates the duty cycle of an active PWM signal. * - * note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. + * note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. * * param base Ctimer peripheral base address + * param pwmPeriodChannel Specify the channel to control the PWM period * param matchChannel Match pin to be used to output the PWM signal * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent) +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent) { uint32_t pulsePeriod = 0, period; - /* Match channel 3 defines the PWM period */ - period = base->MR[kCTIMER_Match_3]; - - /* Calculate pulse width match value */ - pulsePeriod = (period * dutyCyclePercent) / 100; + /* Specified channel pwmPeriodChannel defines the PWM period */ + period = base->MR[pwmPeriodChannel]; /* For 0% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent == 0) + if (dutyCyclePercent == 0U) { - pulsePeriod = period + 1; + pulsePeriod = period + 1U; } else { - pulsePeriod = (period * (100 - dutyCyclePercent)) / 100; + pulsePeriod = (period * (100U - (uint32_t)dutyCyclePercent)) / 100U; } /* Update dutycycle */ @@ -367,33 +388,53 @@ void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const cti /* Set the counter operation when a match on this channel occurs */ reg = base->MCR; - reg &= ~((CTIMER_MCR_MR0R_MASK | CTIMER_MCR_MR0S_MASK | CTIMER_MCR_MR0I_MASK) << (matchChannel * 3)); - reg |= (uint32_t)((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + (matchChannel * 3))); - reg |= (uint32_t)((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + (matchChannel * 3))); - reg |= (uint32_t)((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + (matchChannel * 3))); + reg &= + ~((uint32_t)((uint32_t)CTIMER_MCR_MR0R_MASK | (uint32_t)CTIMER_MCR_MR0S_MASK | (uint32_t)CTIMER_MCR_MR0I_MASK) + << ((uint32_t)matchChannel * 3U)); + reg |= ((uint32_t)(config->enableCounterReset) << (CTIMER_MCR_MR0R_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableCounterStop) << (CTIMER_MCR_MR0S_SHIFT + ((uint32_t)matchChannel * 3U))); + reg |= ((uint32_t)(config->enableInterrupt) << (CTIMER_MCR_MR0I_SHIFT + ((uint32_t)matchChannel * 3U))); base->MCR = reg; reg = base->EMR; /* Set the match output operation when a match on this channel occurs */ - reg &= ~(CTIMER_EMR_EMC0_MASK << (matchChannel * 2)); - reg |= (uint32_t)config->outControl << (CTIMER_EMR_EMC0_SHIFT + (matchChannel * 2)); + reg &= ~(((uint32_t)CTIMER_EMR_EMC0_MASK) << ((uint32_t)matchChannel * 2U)); + reg |= ((uint32_t)config->outControl) << (CTIMER_EMR_EMC0_SHIFT + ((uint32_t)matchChannel * 2U)); /* Set the initial state of the EM bit/output */ - reg &= ~(CTIMER_EMR_EM0_MASK << matchChannel); - reg |= (uint32_t)config->outPinInitState << matchChannel; + reg &= ~(((uint32_t)CTIMER_EMR_EM0_MASK) << (uint32_t)matchChannel); + reg |= ((uint32_t)config->outPinInitState) << (uint32_t)matchChannel; base->EMR = reg; /* Set the match value */ base->MR[matchChannel] = config->matchValue; /* Clear status flags */ - CTIMER_ClearStatusFlags(base, CTIMER_IR_MR0INT_MASK << matchChannel); + CTIMER_ClearStatusFlags(base, ((uint32_t)CTIMER_IR_MR0INT_MASK) << (uint32_t)matchChannel); /* If interrupt is enabled then enable interrupt and update the call back function */ if (config->enableInterrupt) { - EnableIRQ(s_ctimerIRQ[index]); + (void)EnableIRQ(s_ctimerIRQ[index]); } } +/*! + * brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * param base Ctimer peripheral base address + * param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel) +{ + return (base->EMR & matchChannel); +} + #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) /*! * brief Setup the capture. @@ -413,15 +454,17 @@ void CTIMER_SetupCapture(CTIMER_Type *base, uint32_t index = CTIMER_GetInstance(base); /* Set the capture edge */ - reg &= ~((CTIMER_CCR_CAP0RE_MASK | CTIMER_CCR_CAP0FE_MASK | CTIMER_CCR_CAP0I_MASK) << (capture * 3)); - reg |= (uint32_t)edge << (CTIMER_CCR_CAP0RE_SHIFT + (capture * 3)); + reg &= ~((uint32_t)((uint32_t)CTIMER_CCR_CAP0RE_MASK | (uint32_t)CTIMER_CCR_CAP0FE_MASK | + (uint32_t)CTIMER_CCR_CAP0I_MASK) + << ((uint32_t)capture * 3U)); + reg |= ((uint32_t)edge) << (CTIMER_CCR_CAP0RE_SHIFT + ((uint32_t)capture * 3U)); /* Clear status flags */ - CTIMER_ClearStatusFlags(base, (kCTIMER_Capture0Flag << capture)); + CTIMER_ClearStatusFlags(base, (((uint32_t)kCTIMER_Capture0Flag) << (uint32_t)capture)); /* If call back function is valid then enable capture interrupt for the channel and update the call back function */ if (enableInt) { - reg |= CTIMER_CCR_CAP0I_MASK << (capture * 3); - EnableIRQ(s_ctimerIRQ[index]); + reg |= ((uint32_t)CTIMER_CCR_CAP0I_MASK) << ((uint32_t)capture * 3U); + (void)EnableIRQ(s_ctimerIRQ[index]); } base->CCR = reg; } @@ -441,7 +484,12 @@ void CTIMER_RegisterCallBack(CTIMER_Type *base, ctimer_callback_t *cb_func, ctim ctimerCallbackType[index] = cb_type; } -void CTIMER_GenericIRQHandler(uint32_t index) +/*! + * brief CTIMER generic IRQ handle function. + * + * param index FlexCAN peripheral instance index. + */ +static void CTIMER_GenericIRQHandler(uint32_t index) { uint32_t int_stat, i, mask; /* Get Interrupt status flags */ @@ -450,7 +498,7 @@ void CTIMER_GenericIRQHandler(uint32_t index) CTIMER_ClearStatusFlags(s_ctimerBases[index], int_stat); if (ctimerCallbackType[index] == kCTIMER_SingleCallback) { - if (s_ctimerCallback[index][0]) + if (s_ctimerCallback[index][0] != NULL) { s_ctimerCallback[index][0](int_stat); } @@ -463,82 +511,67 @@ void CTIMER_GenericIRQHandler(uint32_t index) #if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++) #else +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++) +#else + for (i = 0; i <= CTIMER_IR_CR1INT_SHIFT; i++) +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ #endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ #endif { - mask = 0x01 << i; + mask = 0x01UL << i; /* For each status flag bit that was set call the callback function if it is valid */ - if ((int_stat & mask) && (s_ctimerCallback[index][i])) + if (((int_stat & mask) != 0U) && (s_ctimerCallback[index][i] != NULL)) { s_ctimerCallback[index][i](int_stat); } } } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } /* IRQ handler functions overloading weak symbols in the startup */ #if defined(CTIMER0) +void CTIMER0_DriverIRQHandler(void); void CTIMER0_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(0); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(CTIMER1) +void CTIMER1_DriverIRQHandler(void); void CTIMER1_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(1); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(CTIMER2) +void CTIMER2_DriverIRQHandler(void); void CTIMER2_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(2); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(CTIMER3) +void CTIMER3_DriverIRQHandler(void); void CTIMER3_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(3); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(CTIMER4) +void CTIMER4_DriverIRQHandler(void); void CTIMER4_DriverIRQHandler(void) { CTIMER_GenericIRQHandler(4); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h index 8ae0d886a7..ca39c95d30 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ctimer.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,7 +23,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ +#define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2)) /*!< Version 2.2.2 */ /*@}*/ /*! @brief List of Timer capture channels */ @@ -31,10 +31,12 @@ typedef enum _ctimer_capture_channel { kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */ kCTIMER_Capture_1, /*!< Timer capture channel 1 */ - kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + kCTIMER_Capture_2, /*!< Timer capture channel 2 */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 kCTIMER_Capture_3 /*!< Timer capture channel 3 */ -#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ +#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ } ctimer_capture_channel_t; /*! @brief List of capture edge options */ @@ -54,6 +56,15 @@ typedef enum _ctimer_match kCTIMER_Match_3 /*!< Timer match register 3 */ } ctimer_match_t; +/*! @brief List of external match */ +typedef enum _ctimer_external_match +{ + kCTIMER_External_Match_0 = (1U << 0), /*!< External match 0 */ + kCTIMER_External_Match_1 = (1U << 1), /*!< External match 1 */ + kCTIMER_External_Match_2 = (1U << 2), /*!< External match 2 */ + kCTIMER_External_Match_3 = (1U << 3) /*!< External match 3 */ +} ctimer_external_match_t; + /*! @brief List of output control options */ typedef enum _ctimer_match_output_control { @@ -82,7 +93,9 @@ typedef enum _ctimer_interrupt_enable #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */ kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */ #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ @@ -99,7 +112,9 @@ typedef enum _ctimer_status_flags #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */ kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */ +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) && FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT) kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */ +#endif /* FSL_FEATURE_CTIMER_HAS_NO_IR_CR2INT */ #if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */ #endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */ @@ -211,46 +226,47 @@ void CTIMER_GetDefaultConfig(ctimer_config_t *config); * * Enables PWM mode on the match channel passed in and will then setup the match value * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. + * This function can manually assign the specified channel to set the PWM cycle. * * @note When setting PWM output from multiple output pins, all should use the same PWM * period * * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period * @param matchChannel Match pin to be used to output the PWM signal * @param pwmPeriod PWM period match value * @param pulsePeriod Pulse width match value * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * @return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM period + * if it is 0 then no interrupt will be generated. */ -status_t CTIMER_SetupPwmPeriod( - CTIMER_Type *base, ctimer_match_t matchChannel, uint32_t pwmPeriod, uint32_t pulsePeriod, bool enableInt); +status_t CTIMER_SetupPwmPeriod(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint32_t pwmPeriod, + uint32_t pulsePeriod, + bool enableInt); /*! * @brief Configures the PWM signal parameters. * * Enables PWM mode on the match channel passed in and will then setup the match value * and other match parameters to generate a PWM signal. - * This function will assign match channel 3 to set the PWM cycle. + * This function can manually assign the specified channel to set the PWM cycle. * * @note When setting PWM output from multiple output pins, all should use the same PWM * frequency. Please use CTIMER_SetupPwmPeriod to set up the PWM with high resolution. * * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period * @param matchChannel Match pin to be used to output the PWM signal * @param dutyCyclePercent PWM pulse width; the value should be between 0 to 100 * @param pwmFreq_Hz PWM signal frequency in Hz * @param srcClock_Hz Timer counter clock in Hz * @param enableInt Enable interrupt when the timer value reaches the match value of the PWM pulse, - * if it is 0 then no interrupt is generated - * - * @return kStatus_Success on success - * kStatus_Fail If matchChannel passed in is 3; this channel is reserved to set the PWM cycle + * if it is 0 then no interrupt will be generated. */ status_t CTIMER_SetupPwm(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, ctimer_match_t matchChannel, uint8_t dutyCyclePercent, uint32_t pwmFreq_Hz, @@ -273,13 +289,18 @@ static inline void CTIMER_UpdatePwmPulsePeriod(CTIMER_Type *base, ctimer_match_t /*! * @brief Updates the duty cycle of an active PWM signal. * - * @note Please use CTIMER_UpdatePwmPulsePeriod to update the PWM with high resolution. + * @note Please use CTIMER_SetupPwmPeriod to update the PWM with high resolution. + * This function can manually assign the specified channel to set the PWM cycle. * * @param base Ctimer peripheral base address + * @param pwmPeriodChannel Specify the channel to control the PWM period * @param matchChannel Match pin to be used to output the PWM signal * @param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 */ -void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, uint8_t dutyCyclePercent); +void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, + const ctimer_match_t pwmPeriodChannel, + ctimer_match_t matchChannel, + uint8_t dutyCyclePercent); /*! @}*/ @@ -294,6 +315,21 @@ void CTIMER_UpdatePwmDutycycle(CTIMER_Type *base, ctimer_match_t matchChannel, u */ void CTIMER_SetupMatch(CTIMER_Type *base, ctimer_match_t matchChannel, const ctimer_match_config_t *config); +/*! + * @brief Get the status of output match. + * + * This function gets the status of output MAT, whether or not this output is connected to a pin. + * This status is driven to the MAT pins if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. + * + * @param base Ctimer peripheral base address + * @param matchChannel External match channel, user can obtain the status of multiple match channels + * at the same time by using the logic of "|" + * enumeration ::ctimer_external_match_t + * @return The mask of external match channel status flags. Users need to use the + * _ctimer_external_match type to decode the return variables. + */ +uint32_t CTIMER_GetOutputMatchStatus(CTIMER_Type *base, uint32_t matchChannel); + /*! * @brief Setup the capture. * @@ -347,7 +383,10 @@ static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) /* Enable capture interrupts */ #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK + base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 | CTIMER_CCR_CAP3I_MASK #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ @@ -369,7 +408,10 @@ static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) /* Disable capture interrupts */ #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK + base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 | CTIMER_CCR_CAP3I_MASK #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ @@ -395,7 +437,10 @@ static inline uint32_t CTIMER_GetEnabledInterrupts(CTIMER_Type *base) /* Get all the capture interrupts enabled */ #if !(defined(FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE) && (FSL_FEATURE_CTIMER_HAS_NO_INPUT_CAPTURE)) - enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK + enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK +#if !(defined(FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) && FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2) + | CTIMER_CCR_CAP2I_MASK +#endif /* FSL_FEATURE_CTIMER_HAS_NO_CCR_CAP2 */ #if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3 | CTIMER_CCR_CAP3I_MASK #endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.c index e4b401336f..6b7bc594ad 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.c @@ -1,12 +1,15 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_dma.h" +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) +#include "fsl_memory.h" +#endif /******************************************************************************* * Definitions @@ -55,10 +58,34 @@ static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; /*! @brief Pointers to transfer handle for each DMA channel. */ static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; + /*! @brief DMA driver internal descriptor table */ -DMA_ALLOCATE_HEAD_DESCRIPTORS(s_dma_descriptor_table0, FSL_FEATURE_DMA_MAX_CHANNELS); +#ifdef FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE); +#else +#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) +AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#else +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ +#endif /* FSL_FEATURE_DMA0_DESCRIPTOR_ALIGN_SIZE */ + #if defined(DMA1) -DMA_ALLOCATE_HEAD_DESCRIPTORS(s_dma_descriptor_table1, FSL_FEATURE_DMA_MAX_CHANNELS); +#ifdef FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE); +#else +#if (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) +AT_NONCACHEABLE_SECTION_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#else +SDK_ALIGN(static dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS], + FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE); +#endif /* (defined(CPU_MIMXRT685SEVKA_dsp) || defined(CPU_MIMXRT685SFVKB_dsp)) */ +#endif /* FSL_FEATURE_DMA1_DESCRIPTOR_ALIGN_SIZE */ static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1}; #else static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; @@ -70,7 +97,7 @@ static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0}; static uint32_t DMA_GetInstance(DMA_Type *base) { - int32_t instance; + uint32_t instance; /* Find the instance index from base address mappings. */ for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) { @@ -94,7 +121,7 @@ static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base) /* Compute start channel */ for (i = 0; i < instance; i++) { - startChannel += FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); + startChannel += (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(s_dmaBases[i]); } return startChannel; @@ -121,7 +148,11 @@ void DMA_Init(DMA_Type *base) RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]); #endif /* set descriptor table */ +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + base->SRAMBASE = MEMORY_ConvertMemoryMapAddress((uint32_t)s_dma_descriptor_table[instance], kMEMORY_Local2DMA); +#else base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance]; +#endif /* enable dma peripheral */ base->CTRL |= DMA_CTRL_ENABLE_MASK; } @@ -152,14 +183,15 @@ void DMA_Deinit(DMA_Type *base) */ void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger) { - assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert((channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)) && (NULL != trigger)); - uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | - DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); - tmp = base->CHANNEL[channel].CFG & (~tmp); - tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); - base->CHANNEL[channel].CFG = tmp; + uint32_t tmpReg = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | + DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK); + tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); + tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + base->CHANNEL[channel].CFG = tmpReg; } /*! @@ -171,7 +203,8 @@ void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_t */ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes * impossible to distinguish between: @@ -182,15 +215,15 @@ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel) /* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */ if ((!DMA_ChannelIsActive(base, channel)) && - (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> - DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) + (0x3FFUL == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> + DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))) { - return 0; + return 0UL; } return ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + - 1; + 1UL; } /* Verify and convert dma_xfercfg_t to XFERCFG register */ @@ -198,9 +231,10 @@ static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) { assert(xfercfg != NULL); /* check source increment */ - assert((xfercfg->srcInc <= kDMA_AddressInterleave4xWidth) && (xfercfg->dstInc <= kDMA_AddressInterleave4xWidth)); + assert((xfercfg->srcInc <= (uint8_t)kDMA_AddressInterleave4xWidth) && + (xfercfg->dstInc <= (uint8_t)kDMA_AddressInterleave4xWidth)); /* check data width */ - assert(xfercfg->byteWidth <= kDMA_Transfer32BitWidth); + assert(xfercfg->byteWidth <= (uint8_t)kDMA_Transfer32BitWidth); /* check transfer count */ assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); @@ -219,15 +253,15 @@ static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) /* set INTB */ xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB); /* set data width */ - xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1); + xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4U ? 2U : xfercfg->byteWidth - 1UL); /* set source increment value */ - xfer |= DMA_CHANNEL_XFERCFG_SRCINC((xfercfg->srcInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1) : - xfercfg->srcInc); + xfer |= DMA_CHANNEL_XFERCFG_SRCINC( + (xfercfg->srcInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1UL) : xfercfg->srcInc); /* set destination increment value */ - xfer |= DMA_CHANNEL_XFERCFG_DSTINC((xfercfg->dstInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1) : - xfercfg->dstInc); + xfer |= DMA_CHANNEL_XFERCFG_DSTINC( + (xfercfg->dstInc == (uint8_t)kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1UL) : xfercfg->dstInc); /* set transfer count */ - xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1); + xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1UL); /* store xferCFG */ *xfercfg_addr = xfer; @@ -245,7 +279,13 @@ static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) void DMA_SetupDescriptor( dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) { - assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U); + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); + dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); + nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); +#endif uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; @@ -264,20 +304,36 @@ void DMA_SetupDescriptor( width += 1U; } - if (srcInc == 3U) + /* + * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. + * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. + * Transfers of 8 bit width can be at any address + */ + if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && + ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) { - srcInc = kDMA_AddressInterleave4xWidth; - } + if (srcInc == 3U) + { + srcInc = kDMA_AddressInterleave4xWidth; + } - if (dstInc == 3U) + if (dstInc == 3U) + { + dstInc = kDMA_AddressInterleave4xWidth; + } + + desc->xfercfg = xfercfg; + desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + desc->linkToNextDesc = nextDesc; + } + else { - dstInc = kDMA_AddressInterleave4xWidth; + /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ + desc->xfercfg = 0U; + desc->srcEndAddr = NULL; + desc->dstEndAddr = NULL; } - - desc->xfercfg = xfercfg; - desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width); - desc->linkToNextDesc = nextDesc; } /*! @@ -299,7 +355,13 @@ void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, dma_burst_wrap_t wrapType, uint32_t burstSize) { - assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U); + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + +#if (defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) + srcStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)srcStartAddr, kMEMORY_Local2DMA); + dstStartAddr = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)dstStartAddr, kMEMORY_Local2DMA); + nextDesc = (void *)MEMORY_ConvertMemoryMapAddress((uint32_t)(uint32_t *)nextDesc, kMEMORY_Local2DMA); +#endif uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0; @@ -318,41 +380,65 @@ void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, width += 1U; } - if (srcInc == 3U) + /* + * Transfers of 16 bit width require an address alignment to a multiple of 2 bytes. + * Transfers of 32 bit width require an address alignment to a multiple of 4 bytes. + * Transfers of 8 bit width can be at any address + */ + if (((NULL != srcStartAddr) && (0UL == ((uint32_t)(uint32_t *)srcStartAddr) % width)) && + ((NULL != dstStartAddr) && (0UL == ((uint32_t)(uint32_t *)dstStartAddr) % width))) { - srcInc = kDMA_AddressInterleave4xWidth; - } + if (srcInc == 3U) + { + srcInc = kDMA_AddressInterleave4xWidth; + } - if (dstInc == 3U) - { - dstInc = kDMA_AddressInterleave4xWidth; - } + if (dstInc == 3U) + { + dstInc = kDMA_AddressInterleave4xWidth; + } - desc->xfercfg = xfercfg; + desc->xfercfg = xfercfg; - if (wrapType == kDMA_NoWrap) - { - desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width); - } - /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */ - if (wrapType == kDMA_SrcWrap) - { - desc->srcEndAddr = (void *)((uint32_t)srcStartAddr + ((1U << burstSize) - 1U) * width * srcInc); - desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width); - } - if (wrapType == kDMA_DstWrap) - { - desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width); - desc->dstEndAddr = (void *)((uint32_t)dstStartAddr + ((1U << burstSize) - 1U) * width * dstInc); - } - if (wrapType == kDMA_SrcAndDstWrap) - { - desc->srcEndAddr = (void *)((uint32_t)srcStartAddr + ((1U << burstSize) - 1U) * width * srcInc); - desc->dstEndAddr = (void *)((uint32_t)dstStartAddr + ((1U << burstSize) - 1U) * width * dstInc); - } + if (wrapType == kDMA_NoWrap) + { + desc->srcEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + } + /* for the wrap transfer, the destination address should be determined by the burstSize/width/interleave size */ + if (wrapType == kDMA_SrcWrap) + { + desc->srcEndAddr = + (uint32_t *)((uint32_t)(uint32_t *)srcStartAddr + ((1UL << burstSize) - 1UL) * width * srcInc); + desc->dstEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)dstStartAddr, dstInc, transferCount * width, width); + } + if (wrapType == kDMA_DstWrap) + { + desc->srcEndAddr = + DMA_DESCRIPTOR_END_ADDRESS((uint32_t *)srcStartAddr, srcInc, transferCount * width, width); + desc->dstEndAddr = + (uint32_t *)((uint32_t)(uint32_t *)dstStartAddr + ((1UL << burstSize) - 1UL) * width * dstInc); + } + if (wrapType == kDMA_SrcAndDstWrap) + { + desc->srcEndAddr = + (uint32_t *)(((uint32_t)(uint32_t *)srcStartAddr) + ((1UL << burstSize) - 1UL) * width * srcInc); + desc->dstEndAddr = + (uint32_t *)(((uint32_t)(uint32_t *)dstStartAddr) + ((1UL << burstSize) - 1UL) * width * dstInc); + } - desc->linkToNextDesc = nextDesc; + desc->linkToNextDesc = nextDesc; + } + else + { + /* if address alignment not satisfy the requirement, reset the descriptor to make sure DMA generate error */ + desc->xfercfg = 0U; + desc->srcEndAddr = NULL; + desc->dstEndAddr = NULL; + } } /*! @@ -367,9 +453,9 @@ void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, */ void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) { - assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U); - assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth)); - assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth)); + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); + assert((NULL != srcAddr) && (0UL == ((uint32_t)(uint32_t *)srcAddr) % xfercfg->byteWidth)); + assert((NULL != dstAddr) && (0UL == ((uint32_t)(uint32_t *)dstAddr) % xfercfg->byteWidth)); uint32_t xfercfg_reg = 0; @@ -391,10 +477,11 @@ void DMA_AbortTransfer(dma_handle_t *handle) assert(NULL != handle); DMA_DisableChannel(handle->base, handle->channel); - while (DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & (1U << DMA_CHANNEL_INDEX(handle->channel))) + while ((DMA_COMMON_CONST_REG_GET(handle->base, handle->channel, BUSY) & + (1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel))) != 0UL) { } - DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1U << DMA_CHANNEL_INDEX(handle->channel); + DMA_COMMON_REG_GET(handle->base, handle->channel, ABORT) |= 1UL << DMA_CHANNEL_INDEX(handle->base, handle->channel); DMA_EnableChannel(handle->base, handle->channel); } @@ -411,20 +498,21 @@ void DMA_AbortTransfer(dma_handle_t *handle) */ void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel) { - assert((NULL != handle) && (channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert((NULL != handle) && (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); - int32_t dmaInstance; + uint32_t dmaInstance; uint32_t startChannel = 0; /* base address is invalid DMA instance */ dmaInstance = DMA_GetInstance(base); startChannel = DMA_GetVirtualStartChannel(base); - memset(handle, 0, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); handle->base = base; - handle->channel = channel; + handle->channel = (uint8_t)channel; s_DMAHandle[startChannel + channel] = handle; /* Enable NVIC interrupt */ - EnableIRQ(s_dmaIRQNumber[dmaInstance]); + (void)EnableIRQ(s_dmaIRQNumber[dmaInstance]); /* Enable channel interrupt */ DMA_EnableChannelInterrupts(handle->base, channel); } @@ -474,47 +562,49 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config, { uint32_t xfer_count; assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); - assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4)); - assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U); + assert((byteWidth == 1UL) || (byteWidth == 2UL) || (byteWidth == 4UL)); + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); /* check max */ xfer_count = transferBytes / byteWidth; - assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0 == transferBytes % byteWidth)); + assert((xfer_count <= DMA_MAX_TRANSFER_COUNT) && (0UL == transferBytes % byteWidth)); - memset(config, 0, sizeof(*config)); - switch (type) + (void)memset(config, 0, sizeof(*config)); + + if (type == kDMA_MemoryToMemory) { - case kDMA_MemoryToMemory: - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 1; - config->isPeriph = false; - break; - case kDMA_PeripheralToMemory: - /* Peripheral register - source doesn't increment */ - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 1; - config->isPeriph = true; - break; - case kDMA_MemoryToPeripheral: - /* Peripheral register - destination doesn't increment */ - config->xfercfg.srcInc = 1; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - case kDMA_StaticToStatic: - config->xfercfg.srcInc = 0; - config->xfercfg.dstInc = 0; - config->isPeriph = true; - break; - default: - return; + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 1; + config->isPeriph = false; + } + + else if (type == kDMA_PeripheralToMemory) + { + /* Peripheral register - source doesn't increment */ + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 1; + config->isPeriph = true; + } + else if (type == kDMA_MemoryToPeripheral) + { + /* Peripheral register - destination doesn't increment */ + config->xfercfg.srcInc = 1; + config->xfercfg.dstInc = 0; + config->isPeriph = true; + } + /* kDMA_StaticToStatic */ + else + { + config->xfercfg.srcInc = 0; + config->xfercfg.dstInc = 0; + config->isPeriph = true; } config->dstAddr = (uint8_t *)dstAddr; config->srcAddr = (uint8_t *)srcAddr; config->nextDesc = (uint8_t *)nextDesc; - config->xfercfg.transferCount = xfer_count; - config->xfercfg.byteWidth = byteWidth; + config->xfercfg.transferCount = (uint16_t)xfer_count; + config->xfercfg.byteWidth = (uint8_t)byteWidth; config->xfercfg.intA = true; config->xfercfg.reload = nextDesc != NULL; config->xfercfg.valid = true; @@ -531,27 +621,27 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config, */ void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph) { - assert(channel <= FSL_FEATURE_DMA_MAX_CHANNELS); + assert(channel < (uint32_t)FSL_FEATURE_DMA_MAX_CHANNELS); - uint32_t tmp = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; + uint32_t tmpReg = DMA_CHANNEL_CFG_PERIPHREQEN_MASK; if (trigger != NULL) { - tmp |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | - DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | - DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; + tmpReg |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK | + DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | + DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK; } - tmp = base->CHANNEL[channel].CFG & (~tmp); + tmpReg = base->CHANNEL[channel].CFG & (~tmpReg); if (trigger != NULL) { - tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); + tmpReg |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap); } - tmp |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); + tmpReg |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph); - base->CHANNEL[channel].CFG = tmp; + base->CHANNEL[channel].CFG = tmpReg; } /*! @@ -576,27 +666,27 @@ void DMA_PrepareChannelTransfer(dma_channel_config_t *config, void *nextDesc) { assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert(((uint32_t)nextDesc & (FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1)) == 0U); + assert((((uint32_t)(uint32_t *)nextDesc) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0UL); /* check max */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); - switch (type) + if (type == kDMA_MemoryToMemory) { - case kDMA_MemoryToMemory: - config->isPeriph = false; - break; - case kDMA_PeripheralToMemory: - config->isPeriph = true; - break; - case kDMA_MemoryToPeripheral: - config->isPeriph = true; - break; - case kDMA_StaticToStatic: - config->isPeriph = true; - break; - default: - return; + config->isPeriph = false; + } + else if (type == kDMA_PeripheralToMemory) + { + config->isPeriph = true; + } + else if (type == kDMA_MemoryToPeripheral) + { + config->isPeriph = true; + } + /* kDMA_StaticToStatic */ + else + { + config->isPeriph = true; } config->dstStartAddr = (uint8_t *)dstStartAddr; @@ -606,6 +696,43 @@ void DMA_PrepareChannelTransfer(dma_channel_config_t *config, config->xferCfg = xferCfg; } +/*! + * brief load channel transfer decriptor. + * + * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA + * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: + * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly + * and then call this api to load the configured descriptor to driver descriptor table. code DMA_Init(DMA0); + * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); + * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); + * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); + * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); + * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) + * {} + * endcode + * + * param base DMA base address. + * param channel DMA channel. + * param descriptor configured DMA descriptor. + */ +void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor) +{ + assert(NULL != descriptor); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1); + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + + uint32_t instance = DMA_GetInstance(base); + dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][channel]); + + channelDescriptor->xfercfg = descriptor->xfercfg; + channelDescriptor->srcEndAddr = descriptor->srcEndAddr; + channelDescriptor->dstEndAddr = descriptor->dstEndAddr; + channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc; + + /* Set channel XFERCFG register according first channel descriptor. */ + base->CHANNEL[channel].XFERCFG = descriptor->xfercfg; +} + /*! * brief Install DMA descriptor memory. * @@ -621,10 +748,14 @@ void DMA_PrepareChannelTransfer(dma_channel_config_t *config, void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) { assert(addr != NULL); - assert(((uint32_t)addr & (FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1U)) == 0U); +#if defined FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn + assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZEn(base) - 1UL)) == 0U); +#else + assert((((uint32_t)(uint32_t *)addr) & ((uint32_t)FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1UL)) == 0U); +#endif /* reconfigure the DMA descriptor base address */ - base->SRAMBASE = (uint32_t)addr; + base->SRAMBASE = (uint32_t)(uint32_t *)addr; } /*! @@ -646,7 +777,7 @@ void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) required, then application should prepare * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. * code - //define link descriptor table in application with macro + define link descriptor table in application with macro DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), @@ -669,18 +800,19 @@ void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr) * param nextDesc address of next descriptor. */ void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) + dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc) { assert((NULL != srcStartAddr) && (NULL != dstStartAddr)); - assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); + assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); uint32_t instance = DMA_GetInstance(handle->base); dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - DMA_SetupDescriptor(descriptor, xfercfg, srcStartAddr, dstStartAddr, nextDesc); + DMA_SetupDescriptor(descriptor, xferCfg, srcStartAddr, dstStartAddr, nextDesc); /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = xfercfg; + handle->base->CHANNEL[handle->channel].XFERCFG = xferCfg; } /*! @@ -693,7 +825,7 @@ void DMA_SubmitChannelTransferParameter( * 1. for the ping pong case, application should responsible for the descriptor, for example, application should * prepare two descriptor table with macro. * code - //define link descriptor table in application with macro + define link descriptor table in application with macro DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), @@ -713,16 +845,7 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip { assert((NULL != handle) && (NULL != descriptor)); - uint32_t instance = DMA_GetInstance(handle->base); - dma_descriptor_t *channelDescriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); - - channelDescriptor->xfercfg = descriptor->xfercfg; - channelDescriptor->srcEndAddr = descriptor->srcEndAddr; - channelDescriptor->dstEndAddr = descriptor->dstEndAddr; - channelDescriptor->linkToNextDesc = descriptor->linkToNextDesc; - - /* Set channel XFERCFG register according first channel descriptor. */ - handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg; + DMA_LoadChannelDescriptor(handle->base, handle->channel, descriptor); } /*! @@ -745,7 +868,7 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip required, then application should prepare * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. * code - //define link descriptor table in application with macro + define link descriptor table in application with macro DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), @@ -764,7 +887,7 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip prepare * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. * code - //define link descriptor table in application with macro + define link descriptor table in application with macro DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), @@ -785,7 +908,8 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config) { assert((NULL != handle) && (NULL != config)); - assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); + assert(handle->channel < (uint8_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); uint32_t instance = DMA_GetInstance(handle->base); dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); @@ -801,9 +925,9 @@ status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *c DMA_SetupChannelDescriptor( descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc, config->trigger == NULL ? kDMA_NoWrap : config->trigger->wrap, - (config->trigger == NULL ? - kDMA_BurstSize1 : - (config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)); + (config->trigger == NULL ? (uint32_t)kDMA_BurstSize1 : + ((uint32_t)config->trigger->burst & (DMA_CHANNEL_CFG_BURSTPOWER_MASK)) >> + DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)); /* Set channel XFERCFG register according first channel descriptor. */ handle->base->CHANNEL[handle->channel].XFERCFG = config->xferCfg; @@ -828,7 +952,8 @@ status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *c status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) { assert((NULL != handle) && (NULL != config)); - assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); + assert(handle->channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); uint32_t instance = DMA_GetInstance(handle->base); dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]); @@ -867,9 +992,10 @@ status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) void DMA_StartTransfer(dma_handle_t *handle) { assert(NULL != handle); + assert(FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base) != -1); uint32_t channel = handle->channel; - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); + assert(channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base)); /* enable channel */ DMA_EnableChannel(handle->base, channel); @@ -884,12 +1010,13 @@ void DMA_StartTransfer(dma_handle_t *handle) void DMA_IRQHandle(DMA_Type *base) { dma_handle_t *handle; - int32_t channel_index; + uint8_t channel_index; uint32_t startChannel = DMA_GetVirtualStartChannel(base); uint32_t i = 0; + bool intEnabled = false, intA = false, intB = false; /* Find channels that have completed transfer */ - for (i = 0; i < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) + for (i = 0; i < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base); i++) { handle = s_DMAHandle[i + startChannel]; /* Handle is not present */ @@ -897,33 +1024,37 @@ void DMA_IRQHandle(DMA_Type *base) { continue; } - channel_index = DMA_CHANNEL_INDEX(handle->channel); + channel_index = DMA_CHANNEL_INDEX(base, handle->channel); /* Channel uses INTA flag */ - if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1U << channel_index)) + intEnabled = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTENSET) & (1UL << channel_index)) != 0UL); + intA = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTA) & (1UL << channel_index)) != 0UL); + if (intEnabled && intA) { /* Clear INTA flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1U << channel_index)); - if (handle->callback) + DMA_COMMON_REG_SET(handle->base, handle->channel, INTA, (1UL << channel_index)); + if (handle->callback != NULL) { (handle->callback)(handle, handle->userData, true, kDMA_IntA); } } + + intB = ((DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1UL << channel_index)) != 0UL); /* Channel uses INTB flag */ - if (DMA_COMMON_REG_GET(handle->base, handle->channel, INTB) & (1U << channel_index)) + if (intEnabled && intB) { /* Clear INTB flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1U << channel_index)); - if (handle->callback) + DMA_COMMON_REG_SET(handle->base, handle->channel, INTB, (1UL << channel_index)); + if (handle->callback != NULL) { (handle->callback)(handle, handle->userData, true, kDMA_IntB); } } /* Error flag */ - if (DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1U << channel_index)) + if ((DMA_COMMON_REG_GET(handle->base, handle->channel, ERRINT) & (1UL << channel_index)) != 0UL) { /* Clear error flag */ - DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1U << channel_index)); - if (handle->callback) + DMA_COMMON_REG_SET(handle->base, handle->channel, ERRINT, (1UL << channel_index)); + if (handle->callback != NULL) { (handle->callback)(handle, handle->userData, false, kDMA_IntError); } @@ -931,24 +1062,18 @@ void DMA_IRQHandle(DMA_Type *base) } } +void DMA0_DriverIRQHandler(void); void DMA0_DriverIRQHandler(void) { DMA_IRQHandle(DMA0); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #if defined(DMA1) +void DMA1_DriverIRQHandler(void); void DMA1_DriverIRQHandler(void) { DMA_IRQHandle(DMA1); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.h index db1da29fa3..0e857752e5 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_dma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -24,16 +24,16 @@ /*! @name Driver version */ /*@{*/ /*! @brief DMA driver version */ -#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*!< Version 2.3.0. */ +#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version 2.4.4. */ /*@}*/ /*! @brief DMA max transfer size */ -#define DMA_MAX_TRANSFER_COUNT 0x400 +#define DMA_MAX_TRANSFER_COUNT 0x400U /*! @brief DMA channel numbers */ #if defined FSL_FEATURE_DMA_NUMBER_OF_CHANNELS #define FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(x) FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS -#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) +#define FSL_FEATURE_DMA_MAX_CHANNELS FSL_FEATURE_DMA_NUMBER_OF_CHANNELS +#define FSL_FEATURE_DMA_ALL_CHANNELS (FSL_FEATURE_DMA_NUMBER_OF_CHANNELS * FSL_FEATURE_SOC_DMA_COUNT) #endif /*! @brief DMA head link descriptor table align size */ #define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U) @@ -41,25 +41,44 @@ * To simplify user interface, this macro will help allocate descriptor memory, * user just need to provide the name and the number for the allocate descriptor. * - * @param name, allocate decriptor name. - * @param number, number of descriptor to be allocated. + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. */ #define DMA_ALLOCATE_HEAD_DESCRIPTORS(name, number) \ SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA head descriptor table allocate macro at noncacheable section + * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_HEAD_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ + AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE) /*! @brief DMA link descriptor table allocate macro * To simplify user interface, this macro will help allocate descriptor memory, * user just need to provide the name and the number for the allocate descriptor. * - * @param name, allocate decriptor name. - * @param number, number of descriptor to be allocated. + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. */ #define DMA_ALLOCATE_LINK_DESCRIPTORS(name, number) \ SDK_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) - -/* Channel group consists of 32 channels. channel_group = (channel / 32) */ +/*! @brief DMA link descriptor table allocate macro at noncacheable section + * To simplify user interface, this macro will help allocate descriptor memory at noncacheable section, + * user just need to provide the name and the number for the allocate descriptor. + * + * @param name Allocate decriptor name. + * @param number Number of descriptor to be allocated. + */ +#define DMA_ALLOCATE_LINK_DESCRIPTORS_AT_NONCACHEABLE(name, number) \ + AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE) +/*! @brief DMA transfer buffer address need to align with the transfer width */ +#define DMA_ALLOCATE_DATA_TRANSFER_BUFFER(name, width) SDK_ALIGN(name, width) +/* Channel group consists of 32 channels. channel_group = 0 */ #define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) -/* Channel index in channel group. channel_index = (channel % 32) */ -#define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1F) +/* Channel index in channel group. channel_index = (channel % (channel number per instance)) */ +#define DMA_CHANNEL_INDEX(base, channel) (((uint8_t)(channel)) & 0x1FU) /*! @brief DMA linked descriptor address algin size */ #define DMA_COMMON_REG_GET(base, channel, reg) \ (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) @@ -69,40 +88,41 @@ (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) /*! @brief DMA descriptor end address calculate - * @param start, start address - * @param inc, address interleave size - * @param bytes, transfer bytes - * @param width, transfer width + * @param start start address + * @param inc address interleave size + * @param bytes transfer bytes + * @param width transfer width */ -#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) ((void *)((uint32_t)(start) + inc * bytes - inc * width)) +#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) \ + ((uint32_t *)((uint32_t)(start) + (inc) * (bytes) - (inc) * (width))) /*! @brief DMA channel transfer configurations macro - * @param reload, true is reload link descriptor after current exhaust, false is not - * @param clrTrig, true is clear trigger status, wait software trigger, false is not - * @param intA, enable interruptA - * @param intB, enable interruptB - * @param width,transfer width - * @param srcInc, source address interleave size - * @param dstInc, destination address interleave size - * @param bytes, transfer bytes + * @param reload true is reload link descriptor after current exhaust, false is not + * @param clrTrig true is clear trigger status, wait software trigger, false is not + * @param intA enable interruptA + * @param intB enable interruptB + * @param width transfer width + * @param srcInc source address interleave size + * @param dstInc destination address interleave size + * @param bytes transfer bytes */ #define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \ DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \ DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \ - DMA_CHANNEL_XFERCFG_WIDTH(width == 4 ? 2 : (width - 1)) | \ - DMA_CHANNEL_XFERCFG_SRCINC(srcInc == 4 ? (srcInc - 1) : srcInc) | \ - DMA_CHANNEL_XFERCFG_DSTINC(dstInc == 4 ? (dstInc - 1) : dstInc) | \ - DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1) + DMA_CHANNEL_XFERCFG_WIDTH(width == 4UL ? 2UL : (width - 1UL)) | \ + DMA_CHANNEL_XFERCFG_SRCINC(srcInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (srcInc - 1UL) : srcInc) | \ + DMA_CHANNEL_XFERCFG_DSTINC(dstInc == (uint32_t)kDMA_AddressInterleave4xWidth ? (dstInc - 1UL) : dstInc) | \ + DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1UL) -/*! @brief DMA transfer status */ -enum _dma_transfer_status +/*! @brief _dma_transfer_status DMA transfer status */ +enum { kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the transfer request. */ }; -/*! @brief dma address interleave size */ -enum _dma_addr_interleave_size +/*! @brief _dma_addr_interleave_size dma address interleave size */ +enum { kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */ kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */ @@ -110,8 +130,8 @@ enum _dma_addr_interleave_size kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */ }; -/*! @brief dma transfer width */ -enum _dma_transfer_width +/*! @brief _dma_transfer_width dma transfer width */ +enum { kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */ kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */ @@ -177,8 +197,8 @@ typedef enum _dma_trigger_type DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */ } dma_trigger_type_t; -/*! @brief DMA burst size*/ -enum _dma_burst_size +/*! @brief _dma_burst_size DMA burst size*/ +enum { kDMA_BurstSize1 = 0U, /*!< burst size 1 transfer */ kDMA_BurstSize2 = 1U, /*!< burst size 2 transfer */ @@ -329,6 +349,7 @@ void DMA_Deinit(DMA_Type *base); void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); /* @} */ + /*! * @name DMA Channel Operation * @{ @@ -343,8 +364,25 @@ void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr); */ static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1U << DMA_CHANNEL_INDEX(channel))) ? true : false; + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + + return (DMA_COMMON_CONST_REG_GET(base, channel, ACTIVE) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; +} + +/*! + * @brief Return whether DMA channel is busy + * + * @param base DMA peripheral base address. + * @param channel DMA channel number. + * @return True for busy state, false otherwise. + */ +static inline bool DMA_ChannelIsBusy(DMA_Type *base, uint32_t channel) +{ + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + + return (DMA_COMMON_CONST_REG_GET(base, channel, BUSY) & (1UL << DMA_CHANNEL_INDEX(base, channel))) != 0UL; } /*! @@ -355,8 +393,9 @@ static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel) */ static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1U << DMA_CHANNEL_INDEX(channel); + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, INTENSET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); } /*! @@ -367,8 +406,9 @@ static inline void DMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel) */ static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1U << DMA_CHANNEL_INDEX(channel); + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, INTENCLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); } /*! @@ -379,8 +419,9 @@ static inline void DMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel */ static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1U << DMA_CHANNEL_INDEX(channel); + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, ENABLESET) |= 1UL << DMA_CHANNEL_INDEX(base, channel); } /*! @@ -391,8 +432,9 @@ static inline void DMA_EnableChannel(DMA_Type *base, uint32_t channel) */ static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1U << DMA_CHANNEL_INDEX(channel); + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + DMA_COMMON_REG_GET(base, channel, ENABLECLR) |= 1UL << DMA_CHANNEL_INDEX(base, channel); } /*! @@ -403,7 +445,8 @@ static inline void DMA_DisableChannel(DMA_Type *base, uint32_t channel) */ static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); base->CHANNEL[channel].CFG |= DMA_CHANNEL_CFG_PERIPHREQEN_MASK; } @@ -416,7 +459,8 @@ static inline void DMA_EnableChannelPeriphRq(DMA_Type *base, uint32_t channel) */ static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); base->CHANNEL[channel].CFG &= ~DMA_CHANNEL_CFG_PERIPHREQEN_MASK; } @@ -460,7 +504,8 @@ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel); */ static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); base->CHANNEL[channel].CFG = (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority); } @@ -474,13 +519,14 @@ static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_ */ static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel) { - assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base)); - return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> - DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); + assert((FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base) != -1) && + (channel < (uint32_t)FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(base))); + return (dma_priority_t)(uint8_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> + DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); } /*! - * @brief Set channel configuration valid.. + * @brief Set channel configuration valid. * * @param base DMA peripheral base address. * @param channel DMA channel number. @@ -560,6 +606,29 @@ void DMA_SetupChannelDescriptor(dma_descriptor_t *desc, dma_burst_wrap_t wrapType, uint32_t burstSize); +/*! + * @brief load channel transfer decriptor. + * + * This function can be used to load desscriptor to driver internal channel descriptor that is used to start DMA + * transfer, the head descriptor table is defined in DMA driver, it is useful for the case: + * 1. for the polling transfer, application can allocate a local descriptor memory table to prepare a descriptor firstly + * and then call this api to load the configured descriptor to driver descriptor table. + * @code + * DMA_Init(DMA0); + * DMA_EnableChannel(DMA0, DEMO_DMA_CHANNEL); + * DMA_SetupDescriptor(desc, xferCfg, s_srcBuffer, &s_destBuffer[0], NULL); + * DMA_LoadChannelDescriptor(DMA0, DEMO_DMA_CHANNEL, (dma_descriptor_t *)desc); + * DMA_DoChannelSoftwareTrigger(DMA0, DEMO_DMA_CHANNEL); + * while(DMA_ChannelIsBusy(DMA0, DEMO_DMA_CHANNEL)) + * {} + * @endcode + * + * @param base DMA base address. + * @param channel DMA channel. + * @param descriptor configured DMA descriptor. + */ +void DMA_LoadChannelDescriptor(DMA_Type *base, uint32_t channel, dma_descriptor_t *descriptor); + /* @} */ /*! @@ -681,7 +750,7 @@ status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) required, then application should prepare * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. * @code - //define link descriptor table in application with macro + define link descriptor table in application with macro DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[3]); DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), @@ -704,7 +773,7 @@ status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) * @param nextDesc address of next descriptor. */ void DMA_SubmitChannelTransferParameter( - dma_handle_t *handle, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); + dma_handle_t *handle, uint32_t xferCfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc); /*! * @brief Submit channel descriptor. @@ -716,7 +785,7 @@ void DMA_SubmitChannelTransferParameter( * 1. for the ping pong case, application should responsible for the descriptor, for example, application should * prepare two descriptor table with macro. * @code - //define link descriptor table in application with macro + define link descriptor table in application with macro DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc[2]); DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), @@ -754,7 +823,7 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip required, then application should prepare * three descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. * @code - //define link descriptor table in application with macro + define link descriptor table in application with macro DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), srcStartAddr, dstStartAddr, nextDesc1); @@ -772,7 +841,7 @@ void DMA_SubmitChannelDescriptor(dma_handle_t *handle, dma_descriptor_t *descrip prepare * two descriptor table with macro , the head descriptor in driver can be used for the first transfer descriptor. * @code - //define link descriptor table in application with macro + define link descriptor table in application with macro DMA_ALLOCATE_LINK_DESCRIPTOR(nextDesc); DMA_SetupDescriptor(nextDesc0, DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes), diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c index b392bc388a..7a21a1ce0e 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -18,6 +18,15 @@ #define FSL_COMPONENT_ID "platform.drivers.flexcomm" #endif +/*! + * @brief Used for conversion between `void*` and `uint32_t`. + */ +typedef union pvoid_to_u32 +{ + void *pvoid; + uint32_t u32; +} pvoid_to_u32_t; + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -31,18 +40,18 @@ static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T * Variables ******************************************************************************/ +/*! @brief Array to map FLEXCOMM instance number to base address. */ +static const uint32_t s_flexcommBaseAddrs[] = FLEXCOMM_BASE_ADDRS; + /*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */ -static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; +static flexcomm_irq_handler_t s_flexcommIrqHandler[ARRAY_SIZE(s_flexcommBaseAddrs)]; /*! @brief Pointers to handles for each instance to provide context to interrupt routines */ -static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT]; +static void *s_flexcommHandle[ARRAY_SIZE(s_flexcommBaseAddrs)]; /*! @brief Array to map FLEXCOMM instance number to IRQ number. */ IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS; -/*! @brief Array to map FLEXCOMM instance number to base address. */ -static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS; - #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /*! @brief IDs of clock for each FLEXCOMM module */ static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS; @@ -66,11 +75,11 @@ static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T } else if (periph <= FLEXCOMM_PERIPH_I2S_TX) { - return (base->PSELID & (uint32_t)(1 << ((uint32_t)periph + 3))) > (uint32_t)0 ? true : false; + return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false; } else if (periph == FLEXCOMM_PERIPH_I2S_RX) { - return (base->PSELID & (1 << 7)) > (uint32_t)0 ? true : false; + return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false; } else { @@ -82,18 +91,20 @@ static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T /*! brief Returns instance number for FLEXCOMM module with given base address. */ uint32_t FLEXCOMM_GetInstance(void *base) { - int i; + uint32_t i; + pvoid_to_u32_t BaseAddr; + BaseAddr.pvoid = base; - for (i = 0; i < FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) + for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++) { - if ((uint32_t)base == s_flexcommBaseAddrs[i]) + if (BaseAddr.u32 == s_flexcommBaseAddrs[i]) { - return i; + break; } } - assert(false); - return 0; + assert(i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT); + return i; } /* Changes FLEXCOMM mode */ @@ -106,13 +117,14 @@ static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph } /* Flexcomm is locked to different peripheral type than expected */ - if ((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) && ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != periph)) + if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) && + ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph)) { return kStatus_Fail; } /* Check if we are asked to lock */ - if (lock) + if (lock != 0) { base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK; } @@ -127,12 +139,7 @@ static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph /*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */ status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) { - int idx = FLEXCOMM_GetInstance(base); - - if (idx < 0) - { - return kStatus_InvalidArgument; - } + uint32_t idx = FLEXCOMM_GetInstance(base); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the peripheral clock */ @@ -150,7 +157,7 @@ status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph) /*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle) +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle) { uint32_t instance; @@ -159,242 +166,247 @@ void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *ha /* Clear handler first to avoid execution of the handler with wrong handle */ s_flexcommIrqHandler[instance] = NULL; - s_flexcommHandle[instance] = handle; + s_flexcommHandle[instance] = flexcommHandle; s_flexcommIrqHandler[instance] = handler; -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } /* IRQ handler functions overloading weak symbols in the startup */ #if defined(FLEXCOMM0) +void FLEXCOMM0_DriverIRQHandler(void); void FLEXCOMM0_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[0]); - s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM0); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM1) +void FLEXCOMM1_DriverIRQHandler(void); void FLEXCOMM1_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[1]); - s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM1); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM2) +void FLEXCOMM2_DriverIRQHandler(void); void FLEXCOMM2_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[2]); - s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM2); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM3) +void FLEXCOMM3_DriverIRQHandler(void); void FLEXCOMM3_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[3]); - s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM3); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM4) +void FLEXCOMM4_DriverIRQHandler(void); void FLEXCOMM4_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[4]); - s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM4); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM5) +void FLEXCOMM5_DriverIRQHandler(void); void FLEXCOMM5_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[5]); - s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM5); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM6) +void FLEXCOMM6_DriverIRQHandler(void); void FLEXCOMM6_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[6]); - s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM6); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM7) +void FLEXCOMM7_DriverIRQHandler(void); void FLEXCOMM7_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[7]); - s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM7); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM8) +void FLEXCOMM8_DriverIRQHandler(void); void FLEXCOMM8_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[8]); - s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM8); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM9) +void FLEXCOMM9_DriverIRQHandler(void); void FLEXCOMM9_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[9]); - s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM9); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM10) +void FLEXCOMM10_DriverIRQHandler(void); void FLEXCOMM10_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[10]); - s_flexcommIrqHandler[10]((void *)s_flexcommBaseAddrs[10], s_flexcommHandle[10]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM10); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM11) +void FLEXCOMM11_DriverIRQHandler(void); void FLEXCOMM11_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[11]); - s_flexcommIrqHandler[11]((void *)s_flexcommBaseAddrs[11], s_flexcommHandle[11]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM11); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM12) +void FLEXCOMM12_DriverIRQHandler(void); void FLEXCOMM12_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[12]); - s_flexcommIrqHandler[12]((void *)s_flexcommBaseAddrs[12], s_flexcommHandle[12]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM12); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM13) +void FLEXCOMM13_DriverIRQHandler(void); void FLEXCOMM13_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[13]); - s_flexcommIrqHandler[13]((void *)s_flexcommBaseAddrs[13], s_flexcommHandle[13]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM13); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM14) +void FLEXCOMM14_DriverIRQHandler(void); void FLEXCOMM14_DriverIRQHandler(void) { uint32_t instance; /* Look up instance number */ instance = FLEXCOMM_GetInstance(FLEXCOMM14); - assert(s_flexcommIrqHandler[instance]); - s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM15) +void FLEXCOMM15_DriverIRQHandler(void); void FLEXCOMM15_DriverIRQHandler(void) { uint32_t instance; /* Look up instance number */ - instance = FLEXCOMM_GetInstance(FLEXCOMM14); - assert(s_flexcommIrqHandler[instance]); - s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + instance = FLEXCOMM_GetInstance(FLEXCOMM15); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif #if defined(FLEXCOMM16) +void FLEXCOMM16_DriverIRQHandler(void); void FLEXCOMM16_DriverIRQHandler(void) { - assert(s_flexcommIrqHandler[16]); - s_flexcommIrqHandler[16]((void *)s_flexcommBaseAddrs[16], s_flexcommHandle[16]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + uint32_t instance; + + /* Look up instance number */ + instance = FLEXCOMM_GetInstance(FLEXCOMM16); + assert(s_flexcommIrqHandler[instance] != NULL); + s_flexcommIrqHandler[instance]((uint32_t *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]); + SDK_ISR_EXIT_BARRIER; } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h index 91c90c289c..f96086fdec 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_flexcomm.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -17,8 +17,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FlexCOMM driver version 2.0.1. */ -#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @brief FlexCOMM driver version 2.0.2. */ +#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ /*! @brief FLEXCOMM peripheral modes. */ @@ -53,7 +53,7 @@ status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph); /*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM * mode */ -void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle); +void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *flexcommHandle); #if defined(__cplusplus) } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_fro_calib.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_fro_calib.h new file mode 100644 index 0000000000..9662444a52 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_fro_calib.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2017, NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_FRO_CALIB_H_ +#define _FSL_FRO_CALIB_H_ + +#include "fsl_common.h" +#include "fsl_device_registers.h" +#include + +/*! + * @addtogroup power + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief FRO_CALIB driver version 1.0.0. */ +#define FSL_FRO_CALIB_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) +/*@}*/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.fro_calib" +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* Returns the version of the FRO Calibration library */ +unsigned int fro_calib_Get_Lib_Ver(void); + +/* ctimer instance */ +/* ctimer clock frquency in KHz */ +void Chip_TIMER_Instance_Freq(CTIMER_Type *base, unsigned int ctimerFreq); + +/* USB_SOF_Event */ +/* Application software should be written to make sure the USB_SOF_EVENT() is */ +/* being called with lower interrupt latency for calibration to work properly */ +void USB_SOF_Event(void); + +#ifdef __cplusplus +} +#endif + +/** + * @} + */ + +#endif /* _FSL_FRO_CALIB_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.c index dec822dec9..9dc2e5eff0 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2017, 2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -124,11 +124,15 @@ void GINT_SetCtrl(GINT_Type *base, gint_comb_t comb, gint_trig_t trig, gint_cb_t void GINT_GetCtrl(GINT_Type *base, gint_comb_t *comb, gint_trig_t *trig, gint_cb_t *callback) { uint32_t instance; + uint32_t combValue; + uint32_t trigValue; instance = GINT_GetInstance(base); - *comb = (gint_comb_t)((base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT); - *trig = (gint_trig_t)((base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT); + combValue = (base->CTRL & GINT_CTRL_COMB_MASK) >> GINT_CTRL_COMB_SHIFT; + *comb = (gint_comb_t)combValue; + trigValue = (base->CTRL & GINT_CTRL_TRIG_MASK) >> GINT_CTRL_TRIG_SHIFT; + *trig = (gint_trig_t)trigValue; *callback = s_gintCallback[instance]; } @@ -193,7 +197,7 @@ void GINT_EnableCallback(GINT_Type *base) Clear status and pending interrupt before enabling the irq in NVIC. */ GINT_ClrStatus(base); NVIC_ClearPendingIRQ(s_gintIRQ[instance]); - EnableIRQ(s_gintIRQ[instance]); + (void)EnableIRQ(s_gintIRQ[instance]); } /*! @@ -211,7 +215,7 @@ void GINT_DisableCallback(GINT_Type *base) uint32_t instance; instance = GINT_GetInstance(base); - DisableIRQ(s_gintIRQ[instance]); + (void)DisableIRQ(s_gintIRQ[instance]); GINT_ClrStatus(base); NVIC_ClearPendingIRQ(s_gintIRQ[instance]); } @@ -248,6 +252,7 @@ void GINT_Deinit(GINT_Type *base) /* IRQ handler functions overloading weak symbols in the startup */ #if defined(GINT0) +void GINT0_DriverIRQHandler(void); void GINT0_DriverIRQHandler(void) { /* Clear interrupt before callback */ @@ -257,15 +262,12 @@ void GINT0_DriverIRQHandler(void) { s_gintCallback[0](); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(GINT1) +void GINT1_DriverIRQHandler(void); void GINT1_DriverIRQHandler(void) { /* Clear interrupt before callback */ @@ -275,15 +277,12 @@ void GINT1_DriverIRQHandler(void) { s_gintCallback[1](); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(GINT2) +void GINT2_DriverIRQHandler(void); void GINT2_DriverIRQHandler(void) { /* Clear interrupt before callback */ @@ -293,15 +292,12 @@ void GINT2_DriverIRQHandler(void) { s_gintCallback[2](); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(GINT3) +void GINT3_DriverIRQHandler(void); void GINT3_DriverIRQHandler(void) { /* Clear interrupt before callback */ @@ -311,15 +307,12 @@ void GINT3_DriverIRQHandler(void) { s_gintCallback[3](); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(GINT4) +void GINT4_DriverIRQHandler(void); void GINT4_DriverIRQHandler(void) { /* Clear interrupt before callback */ @@ -329,15 +322,12 @@ void GINT4_DriverIRQHandler(void) { s_gintCallback[4](); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(GINT5) +void GINT5_DriverIRQHandler(void); void GINT5_DriverIRQHandler(void) { /* Clear interrupt before callback */ @@ -347,15 +337,12 @@ void GINT5_DriverIRQHandler(void) { s_gintCallback[5](); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(GINT6) +void GINT6_DriverIRQHandler(void); void GINT6_DriverIRQHandler(void) { /* Clear interrupt before callback */ @@ -365,15 +352,12 @@ void GINT6_DriverIRQHandler(void) { s_gintCallback[6](); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(GINT7) +void GINT7_DriverIRQHandler(void); void GINT7_DriverIRQHandler(void) { /* Clear interrupt before callback */ @@ -383,10 +367,6 @@ void GINT7_DriverIRQHandler(void) { s_gintCallback[7](); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.h index 10203874fb..adc301a9e0 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gint.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2017, 2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -24,7 +24,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ +#define FSL_GINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3. */ /*@}*/ /*! @brief GINT combine inputs type */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.c index 926880f2c3..be100d5e9e 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -28,10 +28,27 @@ static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; /******************************************************************************* * Prototypes ************ ******************************************************************/ +/*! + * @brief Enable GPIO port clock. + * + * @param base GPIO peripheral base pointer. + * @param port GPIO port number. + */ +static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port); /******************************************************************************* * Code ******************************************************************************/ +static void GPIO_EnablePortClock(GPIO_Type *base, uint32_t port) +{ +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + assert(port < ARRAY_SIZE(s_gpioClockName)); + + /* Upgate the GPIO clock */ + CLOCK_EnableClock(s_gpioClockName[port]); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +} + /*! * brief Initializes the GPIO peripheral. * @@ -42,12 +59,8 @@ static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N; */ void GPIO_PortInit(GPIO_Type *base, uint32_t port) { -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - assert(port < ARRAY_SIZE(s_gpioClockName)); + GPIO_EnablePortClock(base, port); - /* Upgate the GPIO clock */ - CLOCK_EnableClock(s_gpioClockName[port]); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET) /* Reset the GPIO module */ RESET_PeripheralReset(s_gpioResets[port]); @@ -62,13 +75,13 @@ void GPIO_PortInit(GPIO_Type *base, uint32_t port) * * This is an example to define an input pin or output pin configuration: * code - * // Define a digital input pin configuration, + * Define a digital input pin configuration, * gpio_pin_config_t config = * { * kGPIO_DigitalInput, * 0, * } - * //Define a digital output pin configuration, + * Define a digital output pin configuration, * gpio_pin_config_t config = * { * kGPIO_DigitalOutput, @@ -83,12 +96,14 @@ void GPIO_PortInit(GPIO_Type *base, uint32_t port) */ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config) { + GPIO_EnablePortClock(base, port); + if (config->pinDirection == kGPIO_DigitalInput) { #if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRCLR[port] = 1U << pin; + base->DIRCLR[port] = 1UL << pin; #else - base->DIR[port] &= ~(1U << pin); + base->DIR[port] &= ~(1UL << pin); #endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ } else @@ -96,24 +111,24 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c /* Set default output value */ if (config->outputLogic == 0U) { - base->CLR[port] = (1U << pin); + base->CLR[port] = (1UL << pin); } else { - base->SET[port] = (1U << pin); + base->SET[port] = (1UL << pin); } /* Set pin direction */ #if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) - base->DIRSET[port] = 1U << pin; + base->DIRSET[port] = 1UL << pin; #else - base->DIR[port] |= 1U << pin; + base->DIR[port] |= 1UL << pin; #endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/ } } #if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT /*! - * @brief Configures the gpio pin interrupt. + * @brief Set the configuration of pin interrupt. * * @param base GPIO base pointer. * @param port GPIO port number @@ -122,9 +137,9 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c */ void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config) { - base->INTEDG[port] = base->INTEDG[port] | (config->mode << pin); + base->INTEDG[port] = (base->INTEDG[port] & ~(1UL << pin)) | ((uint32_t)config->mode << pin); - base->INTPOL[port] = base->INTPOL[port] | (config->polarity << pin); + base->INTPOL[port] = (base->INTPOL[port] & ~(1UL << pin)) | ((uint32_t)config->polarity << pin); } /*! @@ -137,11 +152,11 @@ void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gp */ void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) { - if (kGPIO_InterruptA == index) + if ((uint32_t)kGPIO_InterruptA == index) { base->INTENA[port] = base->INTENA[port] | mask; } - else if (kGPIO_InterruptB == index) + else if ((uint32_t)kGPIO_InterruptB == index) { base->INTENB[port] = base->INTENB[port] | mask; } @@ -161,11 +176,11 @@ void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, u */ void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) { - if (kGPIO_InterruptA == index) + if ((uint32_t)kGPIO_InterruptA == index) { base->INTENA[port] = base->INTENA[port] & ~mask; } - else if (kGPIO_InterruptB == index) + else if ((uint32_t)kGPIO_InterruptB == index) { base->INTENB[port] = base->INTENB[port] & ~mask; } @@ -186,11 +201,11 @@ void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, */ void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) { - if (kGPIO_InterruptA == index) + if ((uint32_t)kGPIO_InterruptA == index) { base->INTSTATA[port] = mask; } - else if (kGPIO_InterruptB == index) + else if ((uint32_t)kGPIO_InterruptB == index) { base->INTSTATB[port] = mask; } @@ -212,11 +227,11 @@ uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t in { uint32_t status = 0U; - if (kGPIO_InterruptA == index) + if ((uint32_t)kGPIO_InterruptA == index) { status = base->INTSTATA[port]; } - else if (kGPIO_InterruptB == index) + else if ((uint32_t)kGPIO_InterruptB == index) { status = base->INTSTATB[port]; } @@ -225,7 +240,6 @@ uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t in /*Should not enter here*/ } return status; - } /*! @@ -238,13 +252,13 @@ uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t in */ void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) { - if (kGPIO_InterruptA == index) + if ((uint32_t)kGPIO_InterruptA == index) { - base->INTENA[port] = base->INTENA[port] | (1U << pin); + base->INTENA[port] = base->INTENA[port] | (1UL << pin); } - else if (kGPIO_InterruptB == index) + else if ((uint32_t)kGPIO_InterruptB == index) { - base->INTENB[port] = base->INTENB[port] | (1U << pin); + base->INTENB[port] = base->INTENB[port] | (1UL << pin); } else { @@ -262,13 +276,13 @@ void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint3 */ void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) { - if (kGPIO_InterruptA == index) + if ((uint32_t)kGPIO_InterruptA == index) { - base->INTENA[port] = base->INTENA[port] & ~(1U << pin); + base->INTENA[port] = base->INTENA[port] & ~(1UL << pin); } - else if (kGPIO_InterruptB == index) + else if ((uint32_t)kGPIO_InterruptB == index) { - base->INTENB[port] = base->INTENB[port] & ~(1U << pin); + base->INTENB[port] = base->INTENB[port] & ~(1UL << pin); } else { @@ -287,13 +301,13 @@ void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint */ void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index) { - if (kGPIO_InterruptA == index) + if ((uint32_t)kGPIO_InterruptA == index) { - base->INTSTATA[port] = 1U << pin; + base->INTSTATA[port] = 1UL << pin; } - else if (kGPIO_InterruptB == index) + else if ((uint32_t)kGPIO_InterruptB == index) { - base->INTSTATB[port] = 1U << pin; + base->INTSTATB[port] = 1UL << pin; } else { diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.h index 71c7091ec8..50a33f8920 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_gpio.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -24,14 +24,14 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPC GPIO driver version 2.1.3. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) +/*! @brief LPC GPIO driver version. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 7)) /*@}*/ /*! @brief LPC GPIO direction definition */ typedef enum _gpio_pin_direction { - kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ + kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/ kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/ } gpio_pin_direction_t; @@ -50,16 +50,16 @@ typedef struct _gpio_pin_config #if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT) #define GPIO_PIN_INT_LEVEL 0x00U -#define GPIO_PIN_INT_EDGE 0x01U +#define GPIO_PIN_INT_EDGE 0x01U #define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U -#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U +#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U /*! @brief GPIO Pin Interrupt enable mode */ typedef enum _gpio_pin_enable_mode { kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */ - kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ + kGPIO_PinIntEnableEdge = GPIO_PIN_INT_EDGE /*!< Generate Pin Interrupt on edge mode */ } gpio_pin_enable_mode_t; /*! @brief GPIO Pin Interrupt enable polarity */ @@ -81,8 +81,8 @@ typedef enum _gpio_interrupt_index /*! @brief Configures the interrupt generation condition. */ typedef struct _gpio_interrupt_config { - uint8_t mode; /* The trigger mode of GPIO interrupts */ - uint8_t polarity; /* The polarity of GPIO interrupts */ + uint8_t mode; /* The trigger mode of GPIO interrupts */ + uint8_t polarity; /* The polarity of GPIO interrupts */ } gpio_interrupt_config_t; #endif @@ -90,8 +90,7 @@ typedef struct _gpio_interrupt_config * API ******************************************************************************/ #if defined(__cplusplus) -extern "C" -{ +extern "C" { #endif /*! @name GPIO Configuration */ @@ -115,13 +114,13 @@ void GPIO_PortInit(GPIO_Type *base, uint32_t port); * * This is an example to define an input pin or output pin configuration: * @code - * // Define a digital input pin configuration, + * Define a digital input pin configuration, * gpio_pin_config_t config = * { * kGPIO_DigitalInput, * 0, * } - * //Define a digital output pin configuration, + * Define a digital output pin configuration, * gpio_pin_config_t config = * { * kGPIO_DigitalOutput, @@ -269,7 +268,7 @@ static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port) #if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT /*! - * @brief Configures the gpio pin interrupt. + * @brief Set the configuration of pin interrupt. * * @param base GPIO base pointer. * @param port GPIO port number diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c index b90a6a9061..73a2037ae2 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.c @@ -1,5 +1,5 @@ /* - * Copyright 2017-2019 NXP + * Copyright 2017-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -17,9 +17,9 @@ *******************************************************************************/ /*!< SHA-1 and SHA-256 block size */ -#define SHA_BLOCK_SIZE 64 +#define SHA_BLOCK_SIZE 64U /*!< max number of blocks that can be proccessed in one run (master mode) */ -#define SHA_MASTER_MAX_BLOCKS 2048 +#define SHA_MASTER_MAX_BLOCKS 2048U /*!< Use standard C library memcpy */ #define hashcrypt_memcpy memcpy @@ -51,8 +51,16 @@ typedef struct _hashcrypt_sha_ctx_internal hashcrypt_callback_t hashCallback; /*!< pointer to HASH callback function */ void *userData; /*!< user data to be passed as an argument to callback function, once callback is invoked from isr */ +#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) + uint32_t runningHash[8]; /*!< running hash. up to SHA-256, that is 32 bytes. */ +#endif } hashcrypt_sha_ctx_internal_t; +#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) +#define SHA1_LEN 5u +#define SHA256_LEN 8u +#endif + /*!< SHA-1 and SHA-256 digest length in bytes */ enum _hashcrypt_sha_digest_len { @@ -160,7 +168,7 @@ static inline uint32_t hashcrypt_get_word_from_unaligned(const uint8_t *srcAddr) } return retVal; #else - return *((const uint32_t *)srcAddr); + return *((const uint32_t *)(uintptr_t)srcAddr); #endif } @@ -175,15 +183,15 @@ static status_t hashcrypt_get_key_from_unaligned_src(uint8_t *dest, const uint8_ uint32_t i; /* destination is SDK driver internal workspace and it must be aligned */ - assert(0x0 == ((uint32_t)dest & 0x1u)); - if ((uint32_t)dest & 0x1u) + assert(0x0u == ((uint32_t)dest & 0x1u)); + if (0U != ((uint32_t)dest & 0x1u)) { return retVal; } for (i = 0; i < ((uint32_t)size / 4u); i++) { - ((uint32_t *)dest)[i] = hashcrypt_get_word_from_unaligned(&src[i * sizeof(uint32_t)]); + ((uint32_t *)(uintptr_t)dest)[i] = hashcrypt_get_word_from_unaligned(&src[i * sizeof(uint32_t)]); } return kStatus_Success; @@ -202,6 +210,8 @@ static status_t hashcrypt_get_key_from_unaligned_src(uint8_t *dest, const uint8_ */ __STATIC_FORCEINLINE void hashcrypt_sha_ldm_stm_16_words(HASHCRYPT_Type *base, const uint32_t *src) { + /* Data Synchronization Barrier */ + __DSB(); /* typedef struct _one_block { @@ -213,33 +223,92 @@ __STATIC_FORCEINLINE void hashcrypt_sha_ldm_stm_16_words(HASHCRYPT_Type *base, c *ldst = lsrc[0]; *ldst = lsrc[1]; */ + + /* Data Synchronization Barrier prevent compiler from reordering memory write when -O2 or higher is used. */ + /* The address is passed to the crypto engine for hashing below, therefore out */ + /* of order memory write due to compiler optimization must be prevented. */ + __DSB(); + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(src); base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(1); + + __DSB(); } /*! * @brief Loads data to Hashcrypt engine INDATA register. * - * This function writes desired number of bytes starting from the src address (must be word aligned) + * This function writes desired number of bytes starting from the src address * to the dst address. Dst address does not increment (destination is peripheral module register INDATA). * Src address increments to load consecutive words. * - * @param dst peripheral register address (word aligned) - * @param src address of the input block (word aligned) - * @param size number of bytes to write (word aligned) + * @param src address of the input block + * @param size number of bytes to write * */ -__STATIC_INLINE void hashcrypt_load_data(HASHCRYPT_Type *base, const uint32_t *src, size_t size) +__STATIC_INLINE void hashcrypt_load_data(HASHCRYPT_Type *base, uint32_t *src, size_t size) { + /* 16 bytes aligned input block */ + uint32_t __attribute__((aligned(4))) inAlign[HASHCRYPT_AES_BLOCK_SIZE / sizeof(uint32_t)]; + uint32_t *in; + uint8_t i; + + in = src; + /* Check if address of src data is aligned */ + if ((0U != ((uint32_t)in & 3U))) + { + for (i = 0; i < ((uint32_t)size / 4U); i++) + { + inAlign[i] = hashcrypt_get_word_from_unaligned((uint8_t *)&src[i]); + } + in = &inAlign[0]; + } + if (size >= sizeof(uint32_t)) { - base->INDATA = src[0]; + base->INDATA = in[0]; size -= sizeof(uint32_t); } - for (int i = 0; i < size / 4; i++) + for (uint32_t j = 0; j < size / 4U; j++) { - base->ALIAS[i] = src[i + 1]; + base->ALIAS[j] = in[j + 1U]; + } +} + +/*! + * @brief Checks availability of HW AES key. + * + * This function checks if the AES key is present at dedicated hardware bus + * and can be used at actual security level. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @return kStatus_Success if available, kStatus_Fail otherwise. + * + */ +static status_t hashcrypt_check_need_key(HASHCRYPT_Type *base, hashcrypt_handle_t *handle) +{ + if (handle->keyType == kHASHCRYPT_SecretKey) + { + volatile uint32_t wait = 50u; + /* wait until STATUS register is non-zero */ + while ((wait > 0U) && (base->STATUS == 0U)) + { + wait--; + } + /* if NEEDKEY bit is not set, HW key is available */ + if (0U == (base->STATUS & HASHCRYPT_STATUS_NEEDKEY_MASK)) + { + return kStatus_Success; + } + /* NEEDKEY is set, HW key is not available */ + return kStatus_Fail; + } + else + { + /* in case user key is used, return success */ + return kStatus_Success; } } @@ -256,20 +325,20 @@ static void hashcrypt_get_data(HASHCRYPT_Type *base, uint32_t *output, size_t ou { uint32_t digest[8]; - while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) { } for (int i = 0; i < 8; i++) { - digest[i] = swap_bytes(base->OUTDATA0[i]); + digest[i] = swap_bytes(base->DIGEST0[i]); } if (outputSize > sizeof(digest)) { outputSize = sizeof(digest); } - hashcrypt_memcpy(output, digest, outputSize); + (void)hashcrypt_memcpy(output, digest, outputSize); } /*! @@ -287,6 +356,19 @@ static void hashcrypt_engine_init(HASHCRYPT_Type *base, hashcrypt_algo_t algo) base->CTRL = HASHCRYPT_CTRL_MODE(algo) | HASHCRYPT_CTRL_NEW_HASH(1); } +/*! + * @brief Deinitialization of the Hashcrypt engine. + * + * This function sets MODE field in Hashcrypt Control register to zero - disabled. + * This reduces power consumption of HASHCRYPT. + * + * @param base Hashcrypt peripheral base address. + */ +static inline void hashcrypt_engine_deinit(HASHCRYPT_Type *base) +{ + base->CTRL &= ~(HASHCRYPT_CTRL_MODE_MASK); +} + /*! * @brief Loads user key to INDATA register. * @@ -311,9 +393,10 @@ static void hashcrypt_aes_load_userKey(HASHCRYPT_Type *base, hashcrypt_handle_t keySize = 32; break; default: + /* All the cases have been listed above, the default clause should not be reached. */ break; } - if (keySize == 0) + if (keySize == 0U) { return; } @@ -330,66 +413,89 @@ static void hashcrypt_aes_load_userKey(HASHCRYPT_Type *base, hashcrypt_handle_t * @param output output data * @param size size of data block to process in bytes (must be 16bytes multiple). */ -static status_t hashcrypt_aes_one_block(HASHCRYPT_Type *base, const uint8_t *input, uint8_t *output, size_t size) +static status_t hashcrypt_aes_one_block_aligned(HASHCRYPT_Type *base, + const uint8_t *input, + uint8_t *output, + size_t size) +{ + status_t status = kStatus_Fail; + uint32_t idx = 0; + + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(size / 16U); + while (size >= HASHCRYPT_AES_BLOCK_SIZE) + { + /* Get result */ + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) + { + } + + for (int i = 0; i < 4; i++) + { + ((uint32_t *)(uintptr_t)output + idx)[i] = swap_bytes(base->DIGEST0[i]); + } + + idx += HASHCRYPT_AES_BLOCK_SIZE / 4U; + size -= HASHCRYPT_AES_BLOCK_SIZE; + } + + if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) + { + status = kStatus_Success; + } + + return status; +} + +/*! + * @brief Performs AES encryption/decryption of one data block. + * + * This function encrypts/decrypts one block of data with specified size. + * + * @param base Hashcrypt peripheral base address. + * @param input input data + * @param output output data + * @param size size of data block to process in bytes (must be 16bytes multiple). + */ +static status_t hashcrypt_aes_one_block_unaligned(HASHCRYPT_Type *base, + const uint8_t *input, + uint8_t *output, + size_t size) { status_t status = kStatus_Fail; - int idx = 0; /* we use AHB master mode as much as possible */ /* however, it can work only with aligned input data */ /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ /* then we read data back to it and do memcpy to the output buffer */ - if (((uint32_t)input & 0x3u) || ((uint32_t)output & 0x3u)) + uint32_t temp[256 / sizeof(uint32_t)]; + int cnt = 0; + while (size != 0U) { - uint32_t temp[256 / sizeof(uint32_t)]; - int cnt = 0; - while (size) + size_t actSz = size >= 256u ? 256u : size; + size_t actSzOrig = actSz; + (void)memcpy(temp, (const uint32_t *)(uintptr_t)(input + 256 * cnt), actSz); + size -= actSz; + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(temp); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(actSz / 16U); + uint32_t outidx = 0; + while (actSz != 0U) { - size_t actSz = size >= 256u ? 256u : size; - size_t actSzOrig = actSz; - memcpy(temp, input + 256 * cnt, actSz); - size -= actSz; - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(temp); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(actSz / 16); - int outidx = 0; - while (actSz) - { - while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) - { - } - for (int i = 0; i < 4; i++) - { - (temp + outidx)[i] = swap_bytes(base->OUTDATA0[i]); - } - outidx += HASHCRYPT_AES_BLOCK_SIZE / 4; - actSz -= HASHCRYPT_AES_BLOCK_SIZE; - } - memcpy(output + 256 * cnt, temp, actSzOrig); - cnt++; - } - } - else - { - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(input); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(size / 16); - while (size >= HASHCRYPT_AES_BLOCK_SIZE) - { - /* Get result */ - while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) { } - for (int i = 0; i < 4; i++) { - ((uint32_t *)output + idx)[i] = swap_bytes(base->OUTDATA0[i]); + (temp + outidx)[i] = swap_bytes(base->DIGEST0[i]); } - - idx += HASHCRYPT_AES_BLOCK_SIZE / 4; - size -= HASHCRYPT_AES_BLOCK_SIZE; + outidx += HASHCRYPT_AES_BLOCK_SIZE / 4U; + actSz -= HASHCRYPT_AES_BLOCK_SIZE; } + (void)memcpy(output + 256 * cnt, (const uint8_t *)(uintptr_t)temp, actSzOrig); + cnt++; } - if (0 == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) + if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) { status = kStatus_Success; } @@ -397,6 +503,71 @@ static status_t hashcrypt_aes_one_block(HASHCRYPT_Type *base, const uint8_t *inp return status; } +/*! + * @brief Performs AES encryption/decryption of one data block. + * + * This function encrypts/decrypts one block of data with specified size. + * + * @param base Hashcrypt peripheral base address. + * @param input input data + * @param output output data + * @param size size of data block to process in bytes (must be 16bytes multiple). + */ +static status_t hashcrypt_aes_one_block(HASHCRYPT_Type *base, const uint8_t *input, uint8_t *output, size_t size) +{ + status_t status = kStatus_Fail; + + /*MEMCTRL bitfield for COUNT is 11 bits, and this limits the number of blocks to process in one Master run to 2047 + (2^11 -1) blocks . Each block is 16bytes long, so biggest data size which can we do in one Master run is (2047 + blocks *16 bytes) = 32752 So, when size is overflowing HASHCRYPT_MEMCTRL_COUNT field of MEMCTRL register, we split + our data into more smaller chunks */ + + if (size > 32752U) + + { + size_t numBlock = size / 32752U; /* number of blocks, each block is processed in one run*/ + size_t remainingSize = size - (numBlock * 32752U); /* size of last block */ + + if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) /* If data is unaligned*/ + { + for (uint32_t i = 0; i < numBlock; i++) + { + status = hashcrypt_aes_one_block_unaligned(base, input, output, 32752U); + input += 32752U; + output += 32752U; + } + status = hashcrypt_aes_one_block_unaligned(base, input, output, remainingSize); + } + else /* If data is aligned*/ + { + for (uint32_t i = 0; i < numBlock; i++) + { + status = hashcrypt_aes_one_block_aligned(base, input, output, 32752U); + input += 32752U; + output += 32752U; + } + status = hashcrypt_aes_one_block_aligned(base, input, output, remainingSize); + } + } + + else /* size is less than COUNT field of MEMCTRL register so we can process all data at once */ + { + /* we use AHB master mode as much as possible */ + /* however, it can work only with aligned input data */ + /* so, if unaligned, we do memcpy to temp buffer on stack, which is aligned, and use AHB mode to read data in */ + /* then we read data back to it and do memcpy to the output buffer */ + if ((0U != ((uint32_t)input & 0x3u)) || (0U != ((uint32_t)output & 0x3u))) + { + status = hashcrypt_aes_one_block_unaligned(base, input, output, size); + } + else + { + status = hashcrypt_aes_one_block_aligned(base, input, output, size); + } + } + return status; +} + /*! * @brief Check validity of algoritm. * @@ -412,11 +583,6 @@ static status_t hashcrypt_sha_check_input_alg(HASHCRYPT_Type *base, hashcrypt_al return kStatus_Success; } - if ((algo == kHASHCRYPT_Sha512) && (base->CONFIG & HASHCRYPT_CONFIG_SHA512_MASK)) - { - return kStatus_Success; - } - return kStatus_InvalidArgument; } @@ -478,9 +644,9 @@ static void hashcrypt_sha_one_block(HASHCRYPT_Type *base, const uint8_t *blk) const uint32_t *actBlk; /* make sure the 512-bit block is word aligned */ - if ((uintptr_t)blk & 0x3u) + if (0U != ((uintptr_t)blk & 0x3u)) { - hashcrypt_memcpy(temp, blk, SHA_BLOCK_SIZE); + (void)hashcrypt_memcpy(temp, (const uint32_t *)(uintptr_t)blk, SHA_BLOCK_SIZE); actBlk = (const uint32_t *)(uintptr_t)temp; } else @@ -489,7 +655,7 @@ static void hashcrypt_sha_one_block(HASHCRYPT_Type *base, const uint8_t *blk) } /* poll waiting. */ - while (0 == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) + while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) { } /* feed INDATA (and ALIASes). use STM instruction. */ @@ -515,10 +681,10 @@ static status_t hashcrypt_sha_process_message_data(HASHCRYPT_Type *base, size_t messageSize) { /* first fill the internal buffer to full block */ - if (ctxInternal->blksz) + if (ctxInternal->blksz != 0U) { size_t toCopy = SHA_BLOCK_SIZE - ctxInternal->blksz; - hashcrypt_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); + (void)hashcrypt_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy); message += toCopy; messageSize -= toCopy; @@ -529,7 +695,7 @@ static status_t hashcrypt_sha_process_message_data(HASHCRYPT_Type *base, /* process all full blocks in message[] */ if (messageSize >= SHA_BLOCK_SIZE) { - if ((uintptr_t)message & 0x3u) + if (0U != ((uintptr_t)message & 0x3u)) { while (messageSize >= SHA_BLOCK_SIZE) { @@ -541,23 +707,25 @@ static status_t hashcrypt_sha_process_message_data(HASHCRYPT_Type *base, else { /* poll waiting. */ - while (0 == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) + while (0U == (base->STATUS & HASHCRYPT_STATUS_WAITING_MASK)) { } uint32_t blkNum = (messageSize >> 6); /* div by 64 bytes */ uint32_t blkBytes = blkNum * 64u; /* number of bytes in 64 bytes blocks */ - base->MEMADDR = HASHCRYPT_MEMADDR_BASE(message); - base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(blkNum); + __DSB(); + __ISB(); + base->MEMADDR = HASHCRYPT_MEMADDR_BASE(message); + base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(blkNum); message += blkBytes; messageSize -= blkBytes; - while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) { } } } /* copy last incomplete message bytes into internal block */ - hashcrypt_memcpy(&ctxInternal->blk.b[0], message, messageSize); + (void)hashcrypt_memcpy(&ctxInternal->blk.b[0], message, messageSize); ctxInternal->blksz = messageSize; return kStatus_Success; } @@ -575,15 +743,15 @@ static status_t hashcrypt_sha_finalize(HASHCRYPT_Type *base, hashcrypt_sha_ctx_i { hashcrypt_sha_block_t lastBlock; - memset(&lastBlock, 0, sizeof(hashcrypt_sha_block_t)); + (void)memset(&lastBlock, 0, sizeof(hashcrypt_sha_block_t)); /* this is last call, so need to flush buffered message bytes along with padding */ if (ctxInternal->blksz <= 55u) { /* last data is 440 bits or less. */ - hashcrypt_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz); - lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U; - lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize); + (void)hashcrypt_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz); + lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U; + lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); hashcrypt_sha_one_block(base, &lastBlock.b[0]); } else @@ -602,16 +770,58 @@ static status_t hashcrypt_sha_finalize(HASHCRYPT_Type *base, hashcrypt_sha_ctx_i } hashcrypt_sha_one_block(base, &ctxInternal->blk.b[0]); - lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize); + lastBlock.w[SHA_BLOCK_SIZE / 4U - 1U] = swap_bytes(8u * ctxInternal->fullMessageSize); hashcrypt_sha_one_block(base, &lastBlock.b[0]); } /* poll wait for final digest */ - while (0 == (base->STATUS & HASHCRYPT_STATUS_DIGEST_AKA_OUTDATA_MASK)) + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) { } return kStatus_Success; } +static void hashcrypt_save_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) +{ +#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) + size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; + + /* Wait until digest is ready */ + while (0U == (base->STATUS & HASHCRYPT_STATUS_DIGEST_MASK)) + { + } + + /* Store partial digest to context */ + for (uint32_t i = 0; i < len; i++) + { + ctxInternal->runningHash[i] = base->DIGEST0[i]; + } +#endif +} + +static void hashcrypt_restore_running_hash(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal) +{ +#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) + size_t len = (ctxInternal->algo == kHASHCRYPT_Sha1) ? SHA1_LEN : SHA256_LEN; + + /* When switching from different mode, need to set NEW bit to work properly */ + if ((base->CTRL & HASHCRYPT_CTRL_MODE_MASK) != HASHCRYPT_CTRL_MODE(ctxInternal->algo)) + { + base->CTRL = HASHCRYPT_CTRL_NEW_HASH(1); + base->CTRL = HASHCRYPT_CTRL_MODE(ctxInternal->algo) | HASHCRYPT_CTRL_NEW_HASH(1); + } + /* Set RELOAD bit to allow registers to be used */ + base->CTRL |= HASHCRYPT_CTRL_RELOAD_MASK; + + /* Reload partial hash digest */ + for (uint32_t i = 0; i < len; i++) + { + base->RELOAD[i] = ctxInternal->runningHash[i]; + } + /* Clear RELOAD register before continuing */ + base->CTRL &= ~HASHCRYPT_CTRL_RELOAD_MASK; +#endif +} + status_t HASHCRYPT_SHA(HASHCRYPT_Type *base, hashcrypt_algo_t algo, const uint8_t *input, @@ -654,7 +864,7 @@ status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, has } /* set algorithm in context struct for later use */ - ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; ctxInternal->algo = algo; ctxInternal->blksz = 0u; #ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT @@ -675,12 +885,12 @@ status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, c hashcrypt_sha_ctx_internal_t *ctxInternal; size_t blockSize; - if (inputSize == 0) + if (inputSize == 0U) { return kStatus_Success; } - ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; #ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT status = hashcrypt_sha_check_context(base, ctxInternal); if (kStatus_Success != status) @@ -694,7 +904,7 @@ status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, c /* if we are still less than 64 bytes, keep only in context */ if ((ctxInternal->blksz + inputSize) <= blockSize) { - hashcrypt_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); + (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, input, inputSize); ctxInternal->blksz += inputSize; return kStatus_Success; } @@ -707,10 +917,15 @@ status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, c hashcrypt_engine_init(base, ctxInternal->algo); ctxInternal->state = kHASHCRYPT_HashUpdate; } + else + { + hashcrypt_restore_running_hash(base, ctxInternal); + } } /* process message data */ status = hashcrypt_sha_process_message_data(base, ctxInternal, input, inputSize); + hashcrypt_save_running_hash(base, ctxInternal); return status; } @@ -729,7 +944,7 @@ status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, u return kStatus_InvalidArgument; } - ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; #ifdef HASHCRYPT_SHA_DO_CHECK_CONTEXT status = hashcrypt_sha_check_context(base, ctxInternal); if (kStatus_Success != status) @@ -742,6 +957,10 @@ status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, u { hashcrypt_engine_init(base, ctxInternal->algo); } + else + { + hashcrypt_restore_running_hash(base, ctxInternal); + } size_t outSize = 0u; @@ -749,12 +968,13 @@ status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, u switch (ctxInternal->algo) { case kHASHCRYPT_Sha1: - outSize = kHASHCRYPT_OutLenSha1; + outSize = (size_t)kHASHCRYPT_OutLenSha1; break; case kHASHCRYPT_Sha256: - outSize = kHASHCRYPT_OutLenSha256; + outSize = (size_t)kHASHCRYPT_OutLenSha256; break; default: + /* All the cases have been listed above, the default clause should not be reached. */ break; } algOutSize = outSize; @@ -762,7 +982,7 @@ status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, u /* flush message last incomplete block, if there is any, and add padding bits */ status = hashcrypt_sha_finalize(base, ctxInternal); - if (outputSize) + if (outputSize != NULL) { if (algOutSize < *outputSize) { @@ -774,7 +994,7 @@ status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, u } } - hashcrypt_get_data(base, (uint32_t *)output, algOutSize); + hashcrypt_get_data(base, (uint32_t *)(uintptr_t)output, algOutSize); #ifdef HASHCRYPT_SHA_DO_WIPE_CONTEXT ctxW = (uint32_t *)ctx; @@ -794,11 +1014,11 @@ void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base, hashcrypt_sha_ctx_internal_t *ctxInternal; s_ctx = ctx; - ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; ctxInternal->hashCallback = callback; ctxInternal->userData = userData; - EnableIRQ(HASHCRYPT_IRQn); + (void)EnableIRQ(HASHCRYPT_IRQn); } status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, @@ -810,17 +1030,17 @@ status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, uint32_t numBlocks; status_t status; - if (inputSize == 0) + if (inputSize == 0U) { return kStatus_Success; } - if ((uintptr_t)input & 0x3U) + if (0U != ((uintptr_t)input & 0x3U)) { return kStatus_Fail; } - ctxInternal = (hashcrypt_sha_ctx_internal_t *)ctx; + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)ctx; status = hashcrypt_sha_check_context(base, ctxInternal); if (kStatus_Success != status) { @@ -832,15 +1052,15 @@ status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, ctxInternal->blksz = inputSize % SHA_BLOCK_SIZE; /* copy last incomplete block to context */ - if ((ctxInternal->blksz > 0) && (ctxInternal->blksz <= SHA_BLOCK_SIZE)) + if ((ctxInternal->blksz > 0U) && (ctxInternal->blksz <= SHA_BLOCK_SIZE)) { - hashcrypt_memcpy((&ctxInternal->blk.b[0]), input + SHA_BLOCK_SIZE * ctxInternal->remainingBlcks, - ctxInternal->blksz); + (void)hashcrypt_memcpy((&ctxInternal->blk.b[0]), input + SHA_BLOCK_SIZE * ctxInternal->remainingBlcks, + ctxInternal->blksz); } if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1; + numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; } else { @@ -850,7 +1070,7 @@ status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base, ctxInternal->remainingBlcks -= numBlocks; /* compute hash using AHB Master mode for full blocks */ - if (numBlocks > 0) + if (numBlocks > 0U) { ctxInternal->state = kHASHCRYPT_HashUpdate; hashcrypt_engine_init(base, ctxInternal->algo); @@ -916,12 +1136,12 @@ status_t HASHCRYPT_AES_EncryptEcb( { status_t status = kStatus_Fail; - if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) + if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) { return kStatus_InvalidArgument; } - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | @@ -929,6 +1149,13 @@ status_t HASHCRYPT_AES_EncryptEcb( hashcrypt_engine_init(base, kHASHCRYPT_Aes); + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + /* load key if kHASHCRYPT_UserKey is selected */ if (handle->keyType == kHASHCRYPT_UserKey) { @@ -937,6 +1164,8 @@ status_t HASHCRYPT_AES_EncryptEcb( /* load message and get result */ status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); return status; } @@ -946,12 +1175,12 @@ status_t HASHCRYPT_AES_DecryptEcb( { status_t status = kStatus_Fail; - if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) + if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) { return kStatus_InvalidArgument; } - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesEcb) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | @@ -959,6 +1188,13 @@ status_t HASHCRYPT_AES_DecryptEcb( hashcrypt_engine_init(base, kHASHCRYPT_Aes); + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + /* load key if kHASHCRYPT_UserKey is selected */ if (handle->keyType == kHASHCRYPT_UserKey) { @@ -968,6 +1204,8 @@ status_t HASHCRYPT_AES_DecryptEcb( /* load message and get result */ status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); return status; } @@ -980,12 +1218,12 @@ status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, { status_t status = kStatus_Fail; - if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) + if (0U != ((size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) { return kStatus_InvalidArgument; } - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | @@ -993,6 +1231,13 @@ status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, hashcrypt_engine_init(base, kHASHCRYPT_Aes); + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + /* load key if kHASHCRYPT_UserKey is selected */ if (handle->keyType == kHASHCRYPT_UserKey) { @@ -1000,11 +1245,13 @@ status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base, } /* load 16b iv */ - hashcrypt_load_data(base, (uint32_t *)iv, 16); + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); /* load message and get result */ status = hashcrypt_aes_one_block(base, plaintext, ciphertext, size); + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); return status; } @@ -1017,12 +1264,12 @@ status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, { status_t status = kStatus_Fail; - if ((size % 16u) || (handle->keySize == kHASHCRYPT_InvalidKey)) + if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) { return kStatus_InvalidArgument; } - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_DECRYPT) | HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | @@ -1030,6 +1277,13 @@ status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, hashcrypt_engine_init(base, kHASHCRYPT_Aes); + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + /* load key if kHASHCRYPT_UserKey is selected */ if (handle->keyType == kHASHCRYPT_UserKey) { @@ -1037,11 +1291,13 @@ status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base, } /* load iv */ - hashcrypt_load_data(base, (uint32_t *)iv, 16); + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, 16); /* load message and get result */ status = hashcrypt_aes_one_block(base, ciphertext, plaintext, size); + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); return status; } @@ -1064,7 +1320,7 @@ status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, return kStatus_InvalidArgument; } - uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0 : 1u; + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCtr) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | @@ -1072,6 +1328,13 @@ status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, hashcrypt_engine_init(base, kHASHCRYPT_Aes); + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + /* load key if kHASHCRYPT_UserKey is selected */ if (handle->keyType == kHASHCRYPT_UserKey) { @@ -1079,15 +1342,20 @@ status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, } /* load nonce */ - hashcrypt_load_data(base, (uint32_t *)counter, 16); + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)counter, 16); lastSize = size % HASHCRYPT_AES_BLOCK_SIZE; size -= lastSize; /* encrypt full 16byte blocks */ - hashcrypt_aes_one_block(base, input, output, size); + status = hashcrypt_aes_one_block(base, input, output, size); + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } - while (size) + while (size != 0U) { ctrIncrement(counter); size -= 16u; @@ -1095,9 +1363,9 @@ status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, output += 16; } - if (lastSize) + if (lastSize != 0U) { - if (counterlast) + if (counterlast != NULL) { lastEncryptedCounter = counterlast; } @@ -1110,6 +1378,7 @@ status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, status = hashcrypt_aes_one_block(base, lastBlock, lastEncryptedCounter, HASHCRYPT_AES_BLOCK_SIZE); if (status != kStatus_Success) { + hashcrypt_engine_deinit(base); return status; } /* remain output = input XOR counterlast */ @@ -1124,36 +1393,289 @@ status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, { lastSize = HASHCRYPT_AES_BLOCK_SIZE; /* no remaining bytes in couterlast so clearing it */ - if (counterlast) + if (counterlast != NULL) { - memset(counterlast, 0, HASHCRYPT_AES_BLOCK_SIZE); + (void)memset(counterlast, 0, HASHCRYPT_AES_BLOCK_SIZE); } } - if (szLeft) + if (szLeft != NULL) { *szLeft = HASHCRYPT_AES_BLOCK_SIZE - lastSize; } + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); return kStatus_Success; } -void HASHCRYPT_IRQHandler(void) +status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *input, + uint8_t *output, + size_t size, + const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) +{ + status_t status = kStatus_Fail; + uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + + if (handle->keySize == kHASHCRYPT_InvalidKey) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; + + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load iv */ + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); + + /*Use AES CBC mode and feed input with zeroes as input*/ + /*Output block is then XORed with input*/ + + while (size >= 16u) + { + status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + /* XOR input with output block to get output*/ + for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) + { + output[i] = input[i] ^ blockOutput[i]; + } + size -= 16u; + output += 16; + input += 16; + } + + /* OFB can have non-block multiple size.*/ + if (size != 0U) + { + status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + + /* XOR input with output block to get output*/ + for (uint32_t i = 0; i < size; i++) + { + output[i] = input[i] ^ blockOutput[i]; + } + } + + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); + return status; +} + +status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) +{ + status_t status = kStatus_Fail; + uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + + /* For CFB mode size must be 16-byte multiple */ + if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; + + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load iv */ + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); + + /*Use AES CBC mode and feed input with zeroes for first block */ + /*Output block is then XORed with plaintext to get ciphertext*/ + + status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + /* XOR plaintext with output block to get ciphertext*/ + for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) + { + ciphertext[i] = plaintext[i] ^ blockOutput[i]; + } + size -= 16u; + + /*Remaining blocks use previous plaintext as input for aes block function */ + while (size >= 16u) + { + status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + ciphertext += 16; + plaintext += 16; + + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + /* XOR plaintext with output block to get ciphertext*/ + for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) + { + ciphertext[i] = plaintext[i] ^ blockOutput[i]; + } + size -= 16u; + } + + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); + return status; +} + +status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]) +{ + status_t status = kStatus_Fail; + uint8_t zeroes[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + uint8_t blockOutput[HASHCRYPT_AES_BLOCK_SIZE] = {0}; + + /* For CFB mode size must be 16-byte multiple */ + if ((0U != (size % 16u)) || (handle->keySize == kHASHCRYPT_InvalidKey)) + { + return kStatus_InvalidArgument; + } + + uint32_t keyType = (handle->keyType == kHASHCRYPT_UserKey) ? 0U : 1u; + + base->CRYPTCFG = HASHCRYPT_CRYPTCFG_AESMODE(kHASHCRYPT_AesCbc) | HASHCRYPT_CRYPTCFG_AESDECRYPT(AES_ENCRYPT) | + HASHCRYPT_CRYPTCFG_AESSECRET(keyType) | HASHCRYPT_CRYPTCFG_AESKEYSZ(handle->keySize) | + HASHCRYPT_CRYPTCFG_MSW1ST_OUT(1) | HASHCRYPT_CRYPTCFG_SWAPKEY(1) | HASHCRYPT_CRYPTCFG_SWAPDAT(1) | + HASHCRYPT_CRYPTCFG_MSW1ST(1); + + hashcrypt_engine_init(base, kHASHCRYPT_Aes); + + /* in case of HW AES key, check if it is available */ + if (hashcrypt_check_need_key(base, handle) != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return kStatus_Fail; + } + + /* load key if kHASHCRYPT_UserKey is selected */ + if (handle->keyType == kHASHCRYPT_UserKey) + { + hashcrypt_aes_load_userKey(base, handle); + } + + /* load iv */ + hashcrypt_load_data(base, (uint32_t *)(uintptr_t)iv, HASHCRYPT_AES_BLOCK_SIZE); + + /*Use AES CBC mode and feed input with zeroes for first block */ + /*Output block is then XORed with ciphertext to get plaintext*/ + + status = hashcrypt_aes_one_block(base, zeroes, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + /* XOR ciphertext with output block to get plaintext*/ + for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) + { + plaintext[i] = ciphertext[i] ^ blockOutput[i]; + } + size -= 16u; + + /*Remaining blocks use previous plaintext as input for aes block function */ + while (size >= 16u) + { + status = hashcrypt_aes_one_block(base, plaintext, blockOutput, HASHCRYPT_AES_BLOCK_SIZE); + ciphertext += 16; + plaintext += 16; + + if (status != kStatus_Success) + { + hashcrypt_engine_deinit(base); + return status; + } + /* XOR plaintext with ciphertext block to get plaintext*/ + for (uint32_t i = 0; i < HASHCRYPT_AES_BLOCK_SIZE; i++) + { + plaintext[i] = ciphertext[i] ^ blockOutput[i]; + } + size -= 16u; + } + + /* After processing all data, hashcrypt engine is set to disabled to lower power consumption */ + hashcrypt_engine_deinit(base); + return status; +} + +void HASHCRYPT_DriverIRQHandler(void); +void HASHCRYPT_DriverIRQHandler(void) { hashcrypt_sha_ctx_internal_t *ctxInternal; HASHCRYPT_Type *base = HASHCRYPT; uint32_t numBlocks; status_t status; - ctxInternal = (hashcrypt_sha_ctx_internal_t *)s_ctx; + ctxInternal = (hashcrypt_sha_ctx_internal_t *)(uint32_t)s_ctx; - if (0 == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) + if (0U == (base->STATUS & HASHCRYPT_STATUS_ERROR_MASK)) { - if (ctxInternal->remainingBlcks > 0) + if (ctxInternal->remainingBlcks > 0U) { if (ctxInternal->remainingBlcks >= SHA_MASTER_MAX_BLOCKS) { - numBlocks = SHA_MASTER_MAX_BLOCKS - 1; + numBlocks = SHA_MASTER_MAX_BLOCKS - 1U; } else { @@ -1167,7 +1689,8 @@ void HASHCRYPT_IRQHandler(void) /* no full blocks left, disable interrupts and AHB master mode */ base->INTENCLR = HASHCRYPT_INTENCLR_DIGEST_MASK | HASHCRYPT_INTENCLR_ERROR_MASK; base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(0); - status = kStatus_Success; + hashcrypt_save_running_hash(base, ctxInternal); + status = kStatus_Success; } else { @@ -1183,10 +1706,10 @@ void HASHCRYPT_IRQHandler(void) void HASHCRYPT_Init(HASHCRYPT_Type *base) { - RESET_PeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_EnableClock(kCLOCK_HashCrypt); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ + RESET_PeripheralReset(kHASHCRYPT_RST_SHIFT_RSTn); } void HASHCRYPT_Deinit(HASHCRYPT_Type *base) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h index 5c188563d6..1aa78d5959 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_hashcrypt.h @@ -1,5 +1,5 @@ /* - * Copyright 2017-2019 NXP + * Copyright 2017-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -26,9 +26,9 @@ enum _hashcrypt_status */ /*! @name Driver version */ /*@{*/ -/*! @brief HASHCRYPT driver version. Version 2.0.2. +/*! @brief HASHCRYPT driver version. Version 2.2.5. * - * Current version: 2.0.2 + * Current version: 2.2.5 * * Change log: * - Version 2.0.0 @@ -37,18 +37,55 @@ enum _hashcrypt_status * - Support loading AES key from unaligned address * - Version 2.0.2 * - Support loading AES key from unaligned address for different compiler and core variants + * - Version 2.0.3 + * - Remove SHA512 and AES ICB algorithm definitions + * - Version 2.0.4 + * - Add SHA context switch support + * - Version 2.1.0 + * - Update the register name and macro to align with new header. + * - Version 2.1.1 + * - Fix MISRA C-2012. + * - Version 2.1.2 + * - Support loading AES input data from unaligned address. + * - Version 2.1.3 + * - Fix MISRA C-2012. + * - Version 2.1.4 + * - Fix context switch cannot work when switching from AES. + * - Version 2.1.5 + * - Add data synchronization barriere inside hashcrypt_sha_ldm_stm_16_words() + * to prevent possible optimization issue. + * - Version 2.2.0 + * - Add AES-OFB and AES-CFB mixed IP/SW modes. + * - Version 2.2.1 + * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() + * prevent compiler from reordering memory write when -O2 or higher is used. + * - Version 2.2.2 + * - Add data synchronization barrier inside hashcrypt_sha_ldm_stm_16_words() + * to fix optimization issue + * - Version 2.2.3 + * - Added check for size in hashcrypt_aes_one_block to prevent overflowing COUNT field in MEMCTRL register, if its + * bigger than COUNT field do a multiple runs. + * - Version 2.2.4 + * - In all HASHCRYPT_AES_xx functions have been added setting CTRL_MODE bitfield to 0 after processing data, which + * decreases power consumption. + * - Version 2.2.5 + * - Add data synchronization barrier and instruction synchronization barrier inside + * hashcrypt_sha_process_message_data() to fix optimization issue */ -#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 2, 5)) /*@}*/ +/*! @brief Algorithm definitions correspond with the values for Mode field in Control register !*/ +#define HASHCRYPT_MODE_SHA1 0x1 +#define HASHCRYPT_MODE_SHA256 0x2 +#define HASHCRYPT_MODE_AES 0x4 + /*! @brief Algorithm used for Hashcrypt operation */ typedef enum _hashcrypt_algo_t { - kHASHCRYPT_Sha1 = 1, /*!< SHA_1 */ - kHASHCRYPT_Sha256 = 2, /*!< SHA_256 */ - kHASHCRYPT_Sha512 = 3, /*!< SHA_512 */ - kHASHCRYPT_Aes = 4, /*!< AES */ - kHASHCRYPT_AesIcb = 5, /*!< AES_ICB */ + kHASHCRYPT_Sha1 = HASHCRYPT_MODE_SHA1, /*!< SHA_1 */ + kHASHCRYPT_Sha256 = HASHCRYPT_MODE_SHA256, /*!< SHA_256 */ + kHASHCRYPT_Aes = HASHCRYPT_MODE_AES, /*!< AES */ } hashcrypt_algo_t; /*! @} */ @@ -63,9 +100,9 @@ typedef enum _hashcrypt_algo_t */ /*! AES block size in bytes */ -#define HASHCRYPT_AES_BLOCK_SIZE 16 -#define AES_ENCRYPT 0 -#define AES_DECRYPT 1 +#define HASHCRYPT_AES_BLOCK_SIZE 16U +#define AES_ENCRYPT 0 +#define AES_DECRYPT 1 /*! @brief AES mode */ typedef enum _hashcrypt_aes_mode_t @@ -116,7 +153,11 @@ typedef struct _hashcrypt_handle hashcrypt_handle_t; */ /*! @brief HASHCRYPT HASH Context size. */ +#if defined(FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE) && (FSL_FEATURE_HASHCRYPT_HAS_RELOAD_FEATURE > 0) +#define HASHCRYPT_HASH_CTX_SIZE 30 +#else #define HASHCRYPT_HASH_CTX_SIZE 22 +#endif /*! @brief Storage type used to save hash context. */ typedef struct _hashcrypt_hash_ctx_t @@ -287,6 +328,68 @@ status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base, uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE], size_t *szLeft); +/*! + * @brief Encrypts or decrypts AES using OFB block mode. + * + * Encrypts or decrypts AES using OFB block mode. + * AES OFB mode uses only forward AES cipher and same algorithm for encryption and decryption. + * The only difference between encryption and decryption is that, for encryption, the input argument + * is plain text and the output argument is cipher text. For decryption, the input argument is cipher text + * and the output argument is plain text. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param input Input data for OFB block mode + * @param[out] output Output data for OFB block mode + * @param size Size of input and output data in bytes + * @param iv Input initial vector to combine with the first input block. + * @return Status from encrypt operation + */ + +status_t HASHCRYPT_AES_CryptOfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *input, + uint8_t *output, + size_t size, + const uint8_t iv[HASHCRYPT_AES_BLOCK_SIZE]); + +/*! + * @brief Encrypts AES using CFB block mode. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param plaintext Input plain text to encrypt + * @param[out] ciphertext Output cipher text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from encrypt operation + */ + +status_t HASHCRYPT_AES_EncryptCfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *plaintext, + uint8_t *ciphertext, + size_t size, + const uint8_t iv[16]); + +/*! + * @brief Decrypts AES using CFB block mode. + * + * @param base HASHCRYPT peripheral base address + * @param handle Handle used for this request. + * @param ciphertext Input cipher text to decrypt + * @param[out] plaintext Output plaintext text + * @param size Size of input and output data in bytes. Must be multiple of 16 bytes. + * @param iv Input initial vector to combine with the first input block. + * @return Status from encrypt operation + */ + +status_t HASHCRYPT_AES_DecryptCfb(HASHCRYPT_Type *base, + hashcrypt_handle_t *handle, + const uint8_t *ciphertext, + uint8_t *plaintext, + size_t size, + const uint8_t iv[16]); /*! *@} */ /* end of hashcrypt_driver_aes */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.c index 26b14083f7..9ecde80c90 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -20,23 +20,115 @@ #define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c" #endif -/*! @brief Common sets of flags used by the driver. */ +/*! @brief Common sets of flags used by the driver's transactional layer internally. */ enum _i2c_flag_constants { - kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK, - kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, + kI2C_MasterIrqFlags = I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | + I2C_INTSTAT_EVENTTIMEOUT_MASK | I2C_INTSTAT_SCLTIMEOUT_MASK, + kI2C_SlaveIrqFlags = I2C_INTSTAT_SLVPENDING_MASK | I2C_INTSTAT_SLVDESEL_MASK, }; +/*! + * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_i2c_master_irq_handler_t` and + * `flexcomm_i2c_slave_irq_handler_t`. + */ +typedef union i2c_to_flexcomm +{ + flexcomm_i2c_master_irq_handler_t i2c_master_handler; + flexcomm_i2c_slave_irq_handler_t i2c_slave_handler; + flexcomm_irq_handler_t flexcomm_handler; +} i2c_to_flexcomm_t; + /******************************************************************************* * Prototypes ******************************************************************************/ +/*! + * @brief Waits for Master Pending status bit to set and check for bus error status. + * + * @param base The I2C peripheral base address. + * @return Bus status. + */ +static status_t I2C_PendingStatusWait(I2C_Type *base); +/*! + * @brief Prepares the transfer state machine and fills in the command buffer. + * @param base The I2C peripheral base address. + * @param handle Master nonblocking driver handle. + * @param xfer The I2C transfer configuration structure. + */ static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer); + +/*! + * @brief Resets the slave hardware state machine. + * According to documentation, after disabling slave to rest the slave hardware state machine, the register + * configuration remains unchanged. + * @param base The I2C peripheral base address. + */ static void I2C_SlaveInternalStateMachineReset(I2C_Type *base); + +/*! + * @brief Compute CLKDIV + * + * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. + * This setting is used by hardware during slave clock stretching. + * + * @param base The I2C peripheral base address. + * @return status of the operation + */ static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal); + +/*! + * @brief Poll wait for the SLVPENDING flag. + * + * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. + * + * @param base The I2C peripheral base address. + * @return status register at time the SLVPENDING bit is read as set + */ static uint32_t I2C_SlavePollPending(I2C_Type *base); + +/*! + * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). + * + * Sets the event type to transfer structure and invokes the event callback, if it has been + * enabled by eventMask. + * + * @param base The I2C peripheral base address. + * @param handle The I2C slave handle for non-blocking APIs. + * @param event The I2C slave event to invoke. + */ static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event); + +/*! + * @brief Handle slave address match event. + * + * Called by Slave interrupt routine to ACK or NACK the matched address. + * It also determines master direction (read or write). + * + * @param base The I2C peripheral base address. + * @return true if the matched address is ACK'ed + * @return false if the matched address is NACK'ed + */ static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle); + +/*! + * @brief Starts accepting slave transfers. + * + * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing + * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the + * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked + * from the interrupt context. + * + * @param base The I2C peripheral base address. + * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. + * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. + * @param txSize Size of txData buffer in bytes. + * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL + * if slave TX only. + * @param rxSize Size of rxData buffer in bytes. + * @retval #kStatus_Success Slave transfers were successfully started. + * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. + */ static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, i2c_slave_handle_t *handle, const void *txData, @@ -45,6 +137,30 @@ static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, size_t rxSize, uint32_t eventMask); +/*! + * @brief Execute master transfer software state machine until FIFOs are exhausted. + * + * For master transmit, the states would be kStartState->kTransmitSubaddrState->kTransmitDataState->kStopState + * For master receive, the states would be kStartState->kTransmitSubaddrState->kStartState->kReceiveDataState-> + * kWaitForCompletionState + * + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_I2C_ArbitrationLost + * @retval #kStatus_I2C_Nak + */ +static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone); + +/*! + * @brief Checks the slave response to master's start signal. + * + * @param base I2C peripheral base address. + * @retval kStatus_Success Successfully complete the data transmission. + * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. + * @retval kStataus_I2C_Nak Transfer error, receive NAK during addressing. + */ +static status_t I2C_MasterCheckStartResponse(I2C_Type *base); /******************************************************************************* * Variables ******************************************************************************/ @@ -59,15 +175,6 @@ static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; * Code ******************************************************************************/ -/*! - * @brief Returns an instance number given a base address. - * - * If an invalid base address is passed, debug builds will assert. Release builds will just return - * instance number 0. - * - * @param base The I2C peripheral base address. - * @return I2C instance number starting from 0. - */ /*! * brief Returns an instance number given a base address. * @@ -79,16 +186,16 @@ static const IRQn_Type s_i2cIRQ[] = I2C_IRQS; */ uint32_t I2C_GetInstance(I2C_Type *base) { - int i; - for (i = 0; i < FSL_FEATURE_SOC_I2C_COUNT; i++) + uint32_t i; + for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT; i++) { if ((uint32_t)base == s_i2cBaseAddrs[i]) { - return i; + break; } } - assert(false); - return 0; + assert(i < (uint32_t)FSL_FEATURE_SOC_I2C_COUNT); + return i; } /*! @@ -109,11 +216,12 @@ uint32_t I2C_GetInstance(I2C_Type *base) void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) { /* Initializes the configure structure to zero. */ - memset(masterConfig, 0, sizeof(*masterConfig)); + (void)memset(masterConfig, 0, sizeof(*masterConfig)); masterConfig->enableMaster = true; masterConfig->baudRate_Bps = 100000U; masterConfig->enableTimeout = false; + masterConfig->timeout_Ms = 35; } /*! @@ -131,9 +239,10 @@ void I2C_MasterGetDefaultConfig(i2c_master_config_t *masterConfig) */ void I2C_MasterInit(I2C_Type *base, const i2c_master_config_t *masterConfig, uint32_t srcClock_Hz) { - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); I2C_MasterEnable(base, masterConfig->enableMaster); I2C_MasterSetBaudRate(base, masterConfig->baudRate_Bps, srcClock_Hz); + I2C_MasterSetTimeoutValue(base, masterConfig->timeout_Ms, srcClock_Hz); } /*! @@ -149,6 +258,44 @@ void I2C_MasterDeinit(I2C_Type *base) I2C_MasterEnable(base, false); } +/*! + * brief Gets the I2C status flags. + * + * A bit mask with the state of all I2C status flags is returned. For each flag, the corresponding bit + * in the return value is set if the flag is asserted. + * + * param base The I2C peripheral base address. + * return State of the status flags: + * - 1: related status flag is set. + * - 0: related status flag is not set. + * see ref _i2c_status_flags, ref _i2c_master_status_flags and ref _i2c_slave_status_flags. + */ +uint32_t I2C_GetStatusFlags(I2C_Type *base) +{ + uint32_t statusMask = base->STAT; + if ((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_MasterIdleFlag; + } + if (((statusMask & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == 3UL) + { + statusMask = (statusMask & ~(uint32_t)I2C_STAT_MSTSTATE_MASK) | (uint32_t)kI2C_MasterAddrNackFlag; + } + if ((statusMask & (uint32_t)I2C_STAT_SLVSTATE_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_SlaveAddressedFlag; + } + if ((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) == 0UL) + { + statusMask |= (uint32_t)kI2C_SlaveAddress0MatchFlag; + } + if (((statusMask & (uint32_t)I2C_STAT_SLVIDX_MASK) >> I2C_STAT_SLVIDX_SHIFT) == 3UL) + { + statusMask = (statusMask & ~(uint32_t)I2C_STAT_SLVIDX_MASK) | (uint32_t)kI2C_SlaveAddress3MatchFlag; + } + return statusMask; +} + /*! * brief Sets the I2C bus frequency for master transactions. * @@ -162,9 +309,10 @@ void I2C_MasterDeinit(I2C_Type *base) void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz) { uint32_t scl, divider; + uint32_t mindivider; uint32_t err, best_err; - uint32_t best_scl = 0; - uint32_t best_div = 0; + uint32_t best_scl = 0U; + uint32_t best_div = 0U; #if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) /* @@ -172,81 +320,156 @@ void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcCl * I2C peripheral clock frequency has to be fixed at 8MHz * source clock is 32MHz or 48MHz so divider is a round integer value */ - best_div = srcClock_Hz / 8000000; - best_scl = 8000000 / (2 * baudRate_Bps); + best_div = srcClock_Hz / 8000000U; + best_scl = 8000000U / baudRate_Bps; - if (((8000000 / (2 * best_scl)) - baudRate_Bps) > (baudRate_Bps - (8000000 / (2 * (best_scl + 1))))) + if ((8000000U / best_scl - baudRate_Bps) > (baudRate_Bps - (8000000U / (best_scl + 1U)))) { - best_scl = best_scl + 1; + best_scl = best_scl + 1U; } /* - * If master SCL frequency does not fit in workaround range, fallback to - * usual baudrate computation method + * Fallback to usual baudrate computation method, when: + * 1.Master SCL frequency does not fit in workaround range, + * 2.User's setting of baudRate_Bps is 400kHz while the clock frequency after divval is larger than 2MHz */ - if ((best_scl > 9) || ((best_scl < 2))) + if ((best_scl > 18U) || ((best_scl < 4U)) || ((baudRate_Bps == 400000U) && (srcClock_Hz / best_div > 2000000U))) { #endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - best_err = 0; - - for (scl = 9; scl >= 2; scl--) + /* Calculate the minimal divider value to make sure the clock frequency after divval is not larger than 2MHz */ + /* This is required in RM in order to generate 400kHz baudrate */ + mindivider = ((srcClock_Hz * 10U) / 2000000U + 5U) / 10U; + /* If the scl value with current mindivider is smaller than 4, which is the minimal value register can achieve, + update mindivider */ + if ((srcClock_Hz / mindivider / baudRate_Bps) < 4U) { - /* calculated ideal divider value for given scl */ - divider = srcClock_Hz / (baudRate_Bps * scl * 2u); + mindivider = srcClock_Hz / 4U / baudRate_Bps; + } + /* Calculate the ideal div and scl value*/ + best_err = 0U; + for (divider = mindivider; divider <= 0x10000U; divider++) + { + /* Calculte ideal scl value, round up the value */ + scl = ((srcClock_Hz * 10U) / (divider * baudRate_Bps) + 5U) / 10U; /* adjust it if it is out of range */ - divider = (divider > 0x10000u) ? 0x10000 : divider; + scl = (scl > 18U) ? 18U : scl; /* calculate error */ - err = srcClock_Hz - (baudRate_Bps * scl * 2u * divider); - if ((err < best_err) || (best_err == 0)) + err = srcClock_Hz - (baudRate_Bps * scl * divider); + if ((err < best_err) || (best_err == 0U)) { best_div = divider; best_scl = scl; best_err = err; } - if ((err == 0) || (divider >= 0x10000u)) + if ((err == 0U) || (scl <= 4U)) { /* either exact value was found - or divider is at its max (it would even greater in the next iteration for sure) */ + or scl is at its min (it would be even smaller in the next iteration for sure) */ break; } } #if defined(FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) && (FSL_FEATURE_I2C_PREPCLKFRG_8MHZ) } #endif /*FSL_FEATURE_I2C_PREPCLKFRG_8MHZ*/ - base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1); - base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl - 2u) | I2C_MSTTIME_MSTSCLHIGH(best_scl - 2u); + base->CLKDIV = I2C_CLKDIV_DIVVAL(best_div - 1U); + if (best_scl % 2U == 0U) + { + base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 2U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); + } + else + { + base->MSTTIME = I2C_MSTTIME_MSTSCLLOW(best_scl / 2U - 1U) | I2C_MSTTIME_MSTSCLHIGH(best_scl / 2U - 2U); + } } -static uint32_t I2C_PendingStatusWait(I2C_Type *base) +/*! + * brief Sets the I2C bus timeout value. + * + * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or + * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. + * + * param base The I2C peripheral base address. + * param timeout_Ms Timeout value in millisecond. + * param srcClock_Hz I2C functional clock frequency in Hertz. + */ +void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz) { + assert((timeout_Ms != 0U) && (srcClock_Hz != 0U)); + + /* The low 4 bits of the timout reister TIMEOUT is hard-wired to be 1, so the the time out value is always 16 times + the I2C functional clock, we only need to calculate the high bits. */ + uint32_t timeoutValue = ((uint32_t)timeout_Ms * srcClock_Hz / 16UL / 100UL + 5UL) / 10UL; + if (timeoutValue > 0x1000UL) + { + timeoutValue = 0x1000UL; + } + timeoutValue = ((timeoutValue - 1UL) << 4UL) | 0xFUL; + base->TIMEOUT = timeoutValue; +} + +static status_t I2C_PendingStatusWait(I2C_Type *base) +{ + status_t result = kStatus_Success; uint32_t status; -#if I2C_RETRY_TIMES +#if I2C_RETRY_TIMES != 0U uint32_t waitTimes = I2C_RETRY_TIMES; #endif do { status = I2C_GetStatusFlags(base); -#if I2C_RETRY_TIMES - } while (((status & I2C_STAT_MSTPENDING_MASK) == 0) && (--waitTimes)); + if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) + { + result = kStatus_I2C_EventTimeout; + } + if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) + { + result = kStatus_I2C_SclLowTimeout; + } +#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY + if (result != kStatus_Success) + { + I2C_MasterEnable(base, false); + I2C_MasterEnable(base, true); + break; + } +#endif +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while (((status & (uint32_t)kI2C_MasterPendingFlag) == 0U) && (waitTimes != 0U)); - if (waitTimes == 0) + if (waitTimes == 0U) { +#if defined(FSL_FEATURE_I2C_TIMEOUT_RECOVERY) && FSL_FEATURE_I2C_TIMEOUT_RECOVERY + I2C_MasterEnable(base, false); + I2C_MasterEnable(base, true); +#endif return kStatus_I2C_Timeout; } #else - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); + } while ((status & (uint32_t)kI2C_MasterPendingFlag) == 0U); #endif - /* Clear controller state. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + if ((status & (uint32_t)kI2C_MasterArbitrationLostFlag) != 0U) + { + result = kStatus_I2C_ArbitrationLost; + } - return status; + if ((status & (uint32_t)kI2C_MasterStartStopErrorFlag) != 0U) + { + result = kStatus_I2C_StartStopError; + } + + /* Clear controller state. */ + I2C_ClearStatusFlags( + base, (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_EventTimeoutFlag | (uint32_t)kI2C_SclTimeoutFlag); + + return result; } /*! @@ -265,13 +488,13 @@ status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direct { status_t result; result = I2C_PendingStatusWait(base); - if (result == kStatus_I2C_Timeout) + if (result != kStatus_Success) { - return kStatus_I2C_Timeout; + return result; } /* Write Address and RW bit to data register */ - base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u); + base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1U); /* Start the transfer */ base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; @@ -286,11 +509,10 @@ status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direct */ status_t I2C_MasterStop(I2C_Type *base) { - status_t result; - result = I2C_PendingStatusWait(base); - if (result == kStatus_I2C_Timeout) + status_t result = I2C_PendingStatusWait(base); + if (result != kStatus_Success) { - return kStatus_I2C_Timeout; + return result; } base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; @@ -316,37 +538,24 @@ status_t I2C_MasterStop(I2C_Type *base) */ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSize, uint32_t flags) { - uint32_t status; uint32_t master_state; status_t err; - const uint8_t *buf = (const uint8_t *)(uintptr_t)txBuff; + const uint8_t *buf = (const uint8_t *)txBuff; - assert(txBuff); + assert(txBuff != NULL); err = kStatus_Success; - while (txSize) + while (txSize != 0U) { - status = I2C_PendingStatusWait(base); + err = I2C_PendingStatusWait(base); -#if I2C_RETRY_TIMES - if (status == kStatus_I2C_Timeout) + if (err != kStatus_Success) { - return kStatus_I2C_Timeout; - } -#endif - - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - return kStatus_I2C_ArbitrationLost; + return err; } - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - return kStatus_I2C_StartStopError; - } - - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; switch (master_state) { case I2C_STAT_MSTCODE_TXREADY: @@ -358,8 +567,9 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi case I2C_STAT_MSTCODE_NACKADR: case I2C_STAT_MSTCODE_NACKDAT: - /* slave nacked the last byte */ err = kStatus_I2C_Nak; + /* Issue nack signal when nacked by slave. */ + (void)I2C_MasterStop(base); break; default: @@ -374,39 +584,33 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi } } - status = I2C_PendingStatusWait(base); + err = I2C_PendingStatusWait(base); -#if I2C_RETRY_TIMES - if (status == kStatus_I2C_Timeout) + if (err != kStatus_Success) { - return kStatus_I2C_Timeout; + return err; + } + +#if !I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK + /* Check nack signal. If master is nacked by slave of the last byte, return kStatus_I2C_Nak. */ + if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == (uint32_t)I2C_STAT_MSTCODE_NACKDAT) + { + (void)I2C_MasterStop(base); + return kStatus_I2C_Nak; } #endif - if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0) + if (0U == (flags & (uint32_t)kI2C_TransferNoStopFlag)) { - if (!(flags & kI2C_TransferNoStopFlag)) + /* Initiate stop */ + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + err = I2C_PendingStatusWait(base); + if (err != kStatus_Success) { - /* Initiate stop */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - status = I2C_PendingStatusWait(base); - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } + return err; } } - if (status & I2C_STAT_MSTARBLOSS_MASK) - { - return kStatus_I2C_ArbitrationLost; - } - - if (status & I2C_STAT_MSTSTSTPERR_MASK) - { - return kStatus_I2C_StartStopError; - } - return kStatus_Success; } @@ -425,55 +629,40 @@ status_t I2C_MasterWriteBlocking(I2C_Type *base, const void *txBuff, size_t txSi */ status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags) { - uint32_t status = 0; uint32_t master_state; status_t err; uint8_t *buf = (uint8_t *)(rxBuff); - assert(rxBuff); + assert(rxBuff != NULL); err = kStatus_Success; - while (rxSize) + while (rxSize != 0U) { - status = I2C_PendingStatusWait(base); + err = I2C_PendingStatusWait(base); -#if I2C_RETRY_TIMES - if (status == kStatus_I2C_Timeout) + if (err != kStatus_Success) { - return kStatus_I2C_Timeout; - } -#endif - - if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) - { - break; + return err; } - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; switch (master_state) { case I2C_STAT_MSTCODE_RXREADY: /* ready to send next byte */ - *(buf++) = base->MSTDAT; - if (--rxSize) + *(buf++) = (uint8_t)base->MSTDAT; + if (--rxSize != 0U) { base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; } else { - if ((flags & kI2C_TransferNoStopFlag) == 0) + if ((flags & (uint32_t)kI2C_TransferNoStopFlag) == 0U) { /* initiate NAK and stop */ base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - status = I2C_PendingStatusWait(base); - -#if I2C_RETRY_TIMES - if (status == kStatus_I2C_Timeout) - { - return kStatus_I2C_Timeout; - } -#endif + err = I2C_PendingStatusWait(base); } } break; @@ -496,16 +685,24 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uin } } - if (status & I2C_STAT_MSTARBLOSS_MASK) + return kStatus_Success; +} + +static status_t I2C_MasterCheckStartResponse(I2C_Type *base) +{ + /* Wait for start signal to be transmitted. */ + status_t result = I2C_PendingStatusWait(base); + + if (result != kStatus_Success) { - return kStatus_I2C_ArbitrationLost; + return result; } - if (status & I2C_STAT_MSTSTSTPERR_MASK) + if (((base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT) == I2C_STAT_MSTCODE_NACKADR) { - return kStatus_I2C_StartStopError; + (void)I2C_MasterStop(base); + return kStatus_I2C_Addr_Nak; } - return kStatus_Success; } @@ -522,59 +719,80 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uin * retval kStatus_I2C_Timeout Transfer error, wait signal timeout. * retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. * retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + * retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. */ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) { status_t result = kStatus_Success; uint32_t subaddress; uint8_t subaddrBuf[4]; + i2c_direction_t direction; int i; - assert(xfer); + assert(xfer != NULL); - /* If repeated start is requested, send repeated start. */ - if (!(xfer->flags & kI2C_TransferNoStartFlag)) + /* If start signal is requested, send start signal. */ + if (0U == (xfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) { - if (xfer->subaddressSize) + direction = (xfer->subaddressSize != 0U) ? kI2C_Write : xfer->direction; + result = I2C_MasterStart(base, xfer->slaveAddress, direction); + if (result == kStatus_Success) { - result = I2C_MasterStart(base, xfer->slaveAddress, kI2C_Write); - if (result == kStatus_Success) + result = I2C_MasterCheckStartResponse(base); + if (result != kStatus_Success) + { + return result; + } + if ((xfer->subaddressSize) != 0U) { /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) + for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) { - subaddrBuf[i] = subaddress & 0xff; + subaddrBuf[i] = (uint8_t)subaddress & 0xffU; subaddress >>= 8; } /* Send subaddress. */ - result = I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, kI2C_TransferNoStopFlag); - if ((result == kStatus_Success) && (xfer->direction == kI2C_Read)) + result = + I2C_MasterWriteBlocking(base, subaddrBuf, xfer->subaddressSize, (uint32_t)kI2C_TransferNoStopFlag); + if (result != kStatus_Success) + { + if (result == kStatus_I2C_Nak) + { + (void)I2C_MasterStop(base); + return kStatus_I2C_Addr_Nak; + } + } + else if (xfer->direction == kI2C_Read) { result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); + if (result == kStatus_Success) + { + result = I2C_MasterCheckStartResponse(base); + if (result != kStatus_Success) + { + return result; + } + } + } + else + { + /* Empty else block to avoid MISRA 14.1 violation. */ } } } - else if (xfer->flags & kI2C_TransferRepeatedStartFlag) - { - result = I2C_MasterRepeatedStart(base, xfer->slaveAddress, xfer->direction); - } - else - { - result = I2C_MasterStart(base, xfer->slaveAddress, xfer->direction); - } } if (result == kStatus_Success) { - if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0)) + if ((xfer->direction == kI2C_Write) && (xfer->dataSize > 0U)) { /* Transmit data. */ result = I2C_MasterWriteBlocking(base, xfer->data, xfer->dataSize, xfer->flags); } else { - if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0)) + if ((xfer->direction == kI2C_Read) && (xfer->dataSize > 0U)) { /* Receive Data. */ result = I2C_MasterReadBlocking(base, xfer->data, xfer->dataSize, xfer->flags); @@ -584,7 +802,7 @@ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer) if (result == kStatus_I2C_Nak) { - I2C_MasterStop(base); + (void)I2C_MasterStop(base); } return result; @@ -607,12 +825,14 @@ void I2C_MasterTransferCreateHandle(I2C_Type *base, i2c_master_transfer_callback_t callback, void *userData) { - uint32_t instance; + assert(handle != NULL); - assert(handle); + uint32_t instance; + i2c_to_flexcomm_t handler; + handler.i2c_master_handler = I2C_MasterTransferHandleIRQ; /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); /* Look up instance number */ instance = I2C_GetInstance(base); @@ -621,11 +841,11 @@ void I2C_MasterTransferCreateHandle(I2C_Type *base, handle->completionCallback = callback; handle->userData = userData; - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); - EnableIRQ(s_i2cIRQ[instance]); + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); + (void)EnableIRQ(s_i2cIRQ[instance]); } /*! @@ -642,27 +862,27 @@ status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *hand { status_t result; - assert(handle); - assert(xfer); + assert(handle != NULL); + assert(xfer != NULL); assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); /* Return busy if another transaction is in progress. */ - if (handle->state != kIdleState) + if (handle->state != (uint8_t)kIdleState) { return kStatus_I2C_Busy; } /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); /* Prepare transfer state machine. */ result = I2C_InitTransferStateMachine(base, handle, xfer); /* Clear error flags. */ - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); + I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, kI2C_MasterIrqFlags); + I2C_EnableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); return result; } @@ -677,15 +897,15 @@ status_t I2C_MasterTransferNonBlocking(I2C_Type *base, i2c_master_handle_t *hand */ status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, size_t *count) { - assert(handle); + assert(handle != NULL); - if (!count) + if (NULL == count) { return kStatus_InvalidArgument; } /* Catch when there is not an active transfer. */ - if (handle->state == kIdleState) + if (handle->state == (uint8_t)kIdleState) { *count = 0; return kStatus_NoTransferInProgress; @@ -709,52 +929,48 @@ status_t I2C_MasterTransferGetCount(I2C_Type *base, i2c_master_handle_t *handle, */ status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle) { - uint32_t status; + status_t result = kStatus_Success; uint32_t master_state; - if (handle->state != kIdleState) + if (handle->state != (uint8_t)kIdleState) { /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); /* Wait until module is ready */ - status = I2C_PendingStatusWait(base); + result = I2C_PendingStatusWait(base); -#if I2C_RETRY_TIMES - if (status == kStatus_I2C_Timeout) + if (result != kStatus_Success) { - /* Reset handle to idle state. */ - handle->state = kIdleState; - return kStatus_I2C_Timeout; + handle->state = (uint8_t)kIdleState; + return result; } -#endif /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - if (master_state != I2C_STAT_MSTCODE_IDLE) + if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) { /* Send a stop command to finalize the transfer. */ base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; /* Wait until the STOP is completed */ - status = I2C_PendingStatusWait(base); - if (status == kStatus_I2C_Timeout) + result = I2C_PendingStatusWait(base); + + if (result != kStatus_Success) { - return kStatus_I2C_Timeout; + handle->state = (uint8_t)kIdleState; + return result; } } /* Reset handle. */ - handle->state = kIdleState; + handle->state = (uint8_t)kIdleState; + handle->checkAddrNack = false; } return kStatus_Success; } -/*! - * @brief Prepares the transfer state machine and fills in the command buffer. - * @param handle Master nonblocking driver handle. - */ static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, i2c_master_transfer_t *xfer) { struct _i2c_master_transfer *transfer; @@ -766,21 +982,22 @@ static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t handle->remainingBytes = transfer->dataSize; handle->buf = (uint8_t *)transfer->data; handle->remainingSubaddr = 0; + handle->checkAddrNack = false; - if (transfer->flags & kI2C_TransferNoStartFlag) + if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) { /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0) + if (transfer->dataSize == 0U) { - handle->state = kStopState; + handle->state = (uint8_t)kStopState; } else if (handle->transfer.direction == kI2C_Write) { - handle->state = kTransmitDataState; + handle->state = (uint8_t)kTransmitDataState; } else if (handle->transfer.direction == kI2C_Read) { - handle->state = kReceiveDataState; + handle->state = (uint8_t)kReceiveDataBeginState; } else { @@ -789,7 +1006,7 @@ static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t } else { - if (transfer->subaddressSize != 0) + if (transfer->subaddressSize != 0U) { int i; uint32_t subaddress; @@ -801,27 +1018,20 @@ static status_t I2C_InitTransferStateMachine(I2C_Type *base, i2c_master_handle_t /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) + for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) { - handle->subaddrBuf[i] = subaddress & 0xff; + handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; subaddress >>= 8; } handle->remainingSubaddr = transfer->subaddressSize; } - handle->state = kStartState; + handle->state = (uint8_t)kStartState; + handle->checkAddrNack = true; } return kStatus_Success; } -/*! - * @brief Execute states until FIFOs are exhausted. - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t *handle, bool *isDone) { uint32_t status; @@ -830,146 +1040,191 @@ static status_t I2C_RunTransferStateMachine(I2C_Type *base, i2c_master_handle_t status_t err; transfer = &(handle->transfer); - bool ignoreNak = ((handle->state == kStopState) && (handle->remainingBytes == 0U)) || - ((handle->state == kWaitForCompletionState) && (handle->remainingBytes == 0U)); + bool ignoreNak = ((handle->state == (uint8_t)kWaitForCompletionState) && (handle->remainingBytes == 0U)) +#if I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK + /* If master is nacked by slave after the last byte during transmit, ignore the nack. */ + || ((handle->state == (uint8_t)kStopState) && (handle->remainingBytes == 0U)) +#endif + ; *isDone = false; status = I2C_GetStatusFlags(base); - if (status & I2C_STAT_MSTARBLOSS_MASK) + if ((status & I2C_STAT_MSTARBLOSS_MASK) != 0U) { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); + I2C_ClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); return kStatus_I2C_ArbitrationLost; } - if (status & I2C_STAT_MSTSTSTPERR_MASK) + if ((status & I2C_STAT_MSTSTSTPERR_MASK) != 0U) { - I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); + I2C_ClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); return kStatus_I2C_StartStopError; } - if ((status & I2C_STAT_MSTPENDING_MASK) == 0) + /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT + register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens + before, the timeout status can be used to avoid the transfer hangs indefinitely. */ + if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); + return kStatus_I2C_EventTimeout; + } + + /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time + specified by TIMEOUT register. */ + if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); + return kStatus_I2C_SclLowTimeout; + } + + if ((status & I2C_STAT_MSTPENDING_MASK) == 0U) { return kStatus_I2C_Busy; } - /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - - if (((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) && + /* Get the hardware state of the I2C module */ + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + if (((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || + (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) && (ignoreNak != true)) { /* Slave NACKed last byte, issue stop and return error */ base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - return kStatus_I2C_Nak; + handle->state = (uint8_t)kWaitForCompletionState; + /* If master is nacked during slave probe or during sending subaddress, return kStatus_I2C_ADDR_Nak. */ + if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack)) + { + return kStatus_I2C_Addr_Nak; + } + else /* Otherwise just return kStatus_I2C_Nak */ + { + return kStatus_I2C_Nak; + } } err = kStatus_Success; switch (handle->state) { - case kStartState: - if (handle->remainingSubaddr) + case (uint8_t)kStartState: + if (handle->remainingSubaddr != 0U) { /* Subaddress takes precedence over the data transfer, direction is always "write" in this case */ - base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = kTransmitSubaddrState; + base->MSTDAT = (uint32_t)transfer->slaveAddress << 1U; + handle->state = (uint8_t)kTransmitSubaddrState; } else if (transfer->direction == kI2C_Write) { base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = handle->remainingBytes ? kTransmitDataState : kStopState; + handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kTransmitDataState : (uint8_t)kStopState; } else { base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - handle->state = handle->remainingBytes ? kReceiveDataState : kStopState; + handle->state = (handle->remainingBytes != 0U) ? (uint8_t)kReceiveDataState : (uint8_t)kStopState; } /* Send start condition */ base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; break; - case kTransmitSubaddrState: - if (master_state != I2C_STAT_MSTCODE_TXREADY) + case (uint8_t)kTransmitSubaddrState: + if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) { return kStatus_I2C_UnexpectedState; } - /* Most significant subaddress byte comes first */ base->MSTDAT = handle->subaddrBuf[handle->transfer.subaddressSize - handle->remainingSubaddr]; base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--(handle->remainingSubaddr)) + if (--(handle->remainingSubaddr) != 0U) { /* There are still subaddress bytes to be transmitted */ break; } - if (handle->remainingBytes) + if (handle->remainingBytes != 0U) { /* There is data to be transferred, if there is write to read turnaround it is necessary to perform * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; + handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; } else { /* No more data, schedule stop condition */ - handle->state = kStopState; + handle->state = (uint8_t)kStopState; } break; - case kTransmitDataState: - if (master_state != I2C_STAT_MSTCODE_TXREADY) + case (uint8_t)kTransmitDataState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) { return kStatus_I2C_UnexpectedState; } base->MSTDAT = *(handle->buf)++; base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; - if (--handle->remainingBytes == 0) + if (--handle->remainingBytes == 0U) { /* No more data, schedule stop condition */ - handle->state = kStopState; + handle->state = (uint8_t)kStopState; } handle->transferCount++; break; - case kReceiveDataState: - if (master_state != I2C_STAT_MSTCODE_RXREADY) + case (uint8_t)kReceiveDataBeginState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) { return kStatus_I2C_UnexpectedState; } - *(handle->buf)++ = base->MSTDAT; - if (--handle->remainingBytes) + (void)base->MSTDAT; + base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; + handle->state = (uint8_t)kReceiveDataState; + break; + + case (uint8_t)kReceiveDataState: + handle->checkAddrNack = false; + if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) + { + return kStatus_I2C_UnexpectedState; + } + *(handle->buf)++ = (uint8_t)base->MSTDAT; + if (--handle->remainingBytes != 0U) { base->MSTCTL = I2C_MSTCTL_MSTCONTINUE_MASK; } else { /* No more data expected, issue NACK and STOP right away */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; + if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + } + handle->state = (uint8_t)kWaitForCompletionState; } handle->transferCount++; break; - case kStopState: - if (transfer->flags & kI2C_TransferNoStopFlag) + case (uint8_t)kStopState: + handle->checkAddrNack = false; + if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) { /* Stop condition is omitted, we are done */ *isDone = true; - handle->state = kIdleState; + handle->state = (uint8_t)kIdleState; break; } /* Send stop condition */ base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; + handle->state = (uint8_t)kWaitForCompletionState; break; - case kWaitForCompletionState: + case (uint8_t)kWaitForCompletionState: *isDone = true; - handle->state = kIdleState; + handle->state = (uint8_t)kIdleState; break; - case kIdleState: + case (uint8_t)kIdleState: default: /* State machine shall not be invoked again once it enters the idle state */ err = kStatus_I2C_UnexpectedState; @@ -992,86 +1247,70 @@ void I2C_MasterTransferHandleIRQ(I2C_Type *base, i2c_master_handle_t *handle) status_t result; /* Don't do anything if we don't have a valid handle. */ - if (!handle) + if (NULL == handle) { return; } result = I2C_RunTransferStateMachine(base, handle, &isDone); - if (isDone || (result != kStatus_Success)) + if ((result != kStatus_Success) || isDone) { /* Restore handle to idle state. */ - handle->state = kIdleState; + handle->state = (uint8_t)kIdleState; /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, kI2C_MasterIrqFlags); + I2C_DisableInterrupts(base, (uint32_t)kI2C_MasterIrqFlags); /* Invoke callback. */ - if (handle->completionCallback) + if (handle->completionCallback != NULL) { handle->completionCallback(base, handle, result, handle->userData); } } } -/*! - * @brief Sets the hardware slave state machine to reset - * - * Per documentation, the only the state machine is reset, the configuration settings remain. - * - * @param base The I2C peripheral base address. - */ static void I2C_SlaveInternalStateMachineReset(I2C_Type *base) { I2C_SlaveEnable(base, false); /* clear SLVEN Slave enable bit */ } -/*! - * @brief Compute CLKDIV - * - * This function computes CLKDIV value according to the given bus speed and Flexcomm source clock frequency. - * This setting is used by hardware during slave clock stretching. - * - * @param base The I2C peripheral base address. - * @return status of the operation - */ static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busSpeed, uint32_t *divVal) { uint32_t dataSetupTime_ns; - switch (busSpeed) + switch ((uint8_t)(busSpeed)) { - case kI2C_SlaveStandardMode: - dataSetupTime_ns = 250u; + case (uint8_t)kI2C_SlaveStandardMode: + dataSetupTime_ns = 250U; break; - case kI2C_SlaveFastMode: - dataSetupTime_ns = 100u; + case (uint8_t)kI2C_SlaveFastMode: + dataSetupTime_ns = 100U; break; - case kI2C_SlaveFastModePlus: - dataSetupTime_ns = 50u; + case (uint8_t)kI2C_SlaveFastModePlus: + dataSetupTime_ns = 50U; break; - case kI2C_SlaveHsMode: - dataSetupTime_ns = 10u; + case (uint8_t)kI2C_SlaveHsMode: + dataSetupTime_ns = 10U; break; default: - dataSetupTime_ns = 0; + dataSetupTime_ns = 0U; break; } - if (0 == dataSetupTime_ns) + if (0U == dataSetupTime_ns) { return kStatus_InvalidArgument; } /* divVal = (sourceClock_Hz / 1000000) * (dataSetupTime_ns / 1000) */ - *divVal = srcClock_Hz / 1000u; + *divVal = srcClock_Hz / 1000U; *divVal = (*divVal) * dataSetupTime_ns; - *divVal = (*divVal) / 1000000u; + *divVal = (*divVal) / 1000000U; if ((*divVal) > I2C_CLKDIV_DIVVAL_MASK) { @@ -1081,60 +1320,46 @@ static status_t I2C_SlaveDivVal(uint32_t srcClock_Hz, i2c_slave_bus_speed_t busS return kStatus_Success; } -/*! - * @brief Poll wait for the SLVPENDING flag. - * - * Wait for the pending status to be set (SLVPENDING = 1) by polling the STAT register. - * - * @param base The I2C peripheral base address. - * @return status register at time the SLVPENDING bit is read as set - */ static uint32_t I2C_SlavePollPending(I2C_Type *base) { uint32_t stat; -#if I2C_RETRY_TIMES +#if I2C_RETRY_TIMES != 0U uint32_t waitTimes = I2C_RETRY_TIMES; #endif do { stat = base->STAT; -#if I2C_RETRY_TIMES - } while ((0u == (stat & I2C_STAT_SLVPENDING_MASK)) && (--waitTimes)); +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == (stat & I2C_STAT_SLVPENDING_MASK)) && (waitTimes != 0U)); - if (waitTimes == 0u) + if (waitTimes == 0U) { - return kStatus_I2C_Timeout; + return (uint32_t)kStatus_I2C_Timeout; } #else - } while (0u == (stat & I2C_STAT_SLVPENDING_MASK)); + } while (0U == (stat & I2C_STAT_SLVPENDING_MASK)); #endif return stat; } -/*! - * @brief Invoke event from I2C_SlaveTransferHandleIRQ(). - * - * Sets the event type to transfer structure and invokes the event callback, if it has been - * enabled by eventMask. - * - * @param base The I2C peripheral base address. - * @param handle The I2C slave handle for non-blocking APIs. - * @param event The I2C slave event to invoke. - */ static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c_slave_transfer_event_t event) { + uint32_t eventMask = handle->transfer.eventMask; handle->transfer.event = event; - if ((handle->callback) && (handle->transfer.eventMask & event)) + if (((handle->callback) != NULL) && ((eventMask & (uint32_t)event) != 0U)) { handle->callback(base, &handle->transfer, handle->userData); + size_t txSize = handle->transfer.txSize; + size_t rxSize = handle->transfer.rxSize; /* if after event callback we have data buffer (callback func has added new data), keep transfer busy */ if (false == handle->isBusy) { - if (((handle->transfer.txData) && (handle->transfer.txSize)) || - ((handle->transfer.rxData) && (handle->transfer.rxSize))) + if (((handle->transfer.txData != NULL) && (txSize != 0U)) || + ((handle->transfer.rxData != NULL) && (rxSize != 0U))) { handle->isBusy = true; } @@ -1148,19 +1373,11 @@ static void I2C_SlaveInvokeEvent(I2C_Type *base, i2c_slave_handle_t *handle, i2c } } -/*! - * @brief Handle slave address match event. - * - * Called by Slave interrupt routine to ACK or NACK the matched address. - * It also determines master direction (read or write). - * - * @param base The I2C peripheral base address. - * @return true if the matched address is ACK'ed - * @return false if the matched address is NACK'ed - */ static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) { uint8_t addressByte0; + size_t txSize; + size_t rxSize; addressByte0 = (uint8_t)base->SLVDAT; @@ -1168,16 +1385,18 @@ static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) handle->transfer.receivedAddress = addressByte0; /* R/nW */ - if (addressByte0 & 1u) + if ((addressByte0 & 1U) != 0U) { + txSize = handle->transfer.txSize; /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) + if ((handle->transfer.txData == NULL) || (txSize == 0U)) { I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); } + txSize = handle->transfer.txSize; /* NACK if we have no data in this transfer. */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) + if ((handle->transfer.txData == NULL) || (txSize == 0U)) { base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; return false; @@ -1188,14 +1407,16 @@ static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) } else { + rxSize = handle->transfer.rxSize; /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) { I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); } + rxSize = handle->transfer.rxSize; /* NACK if we have no data in this transfer */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) { base->SLVCTL = I2C_SLVCTL_SLVNACK_MASK; return false; @@ -1211,25 +1432,6 @@ static bool I2C_SlaveAddressIRQ(I2C_Type *base, i2c_slave_handle_t *handle) return true; } -/*! - * @brief Starts accepting slave transfers. - * - * Call this API after calling I2C_SlaveInit() and I2C_SlaveTransferCreateHandle() to start processing - * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the - * callback that was passed into the call to I2C_SlaveTransferCreateHandle(). The callback is always invoked - * from the interrupt context. - * - * @param base The I2C peripheral base address. - * @param handle Pointer to #i2c_slave_handle_t structure which stores the transfer state. - * @param txData Data to be transmitted to master in response to master read from slave requests. NULL if slave RX only. - * @param txSize Size of txData buffer in bytes. - * @param rxData Data where received data from master will be stored in response to master write to slave requests. NULL - * if slave TX only. - * @param rxSize Size of rxData buffer in bytes. - * - * @retval #kStatus_Success Slave transfers were successfully started. - * @retval #kStatus_I2C_Busy Slave transfers have already been started on this handle. - */ static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, i2c_slave_handle_t *handle, const void *txData, @@ -1238,14 +1440,13 @@ static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, size_t rxSize, uint32_t eventMask) { + assert(handle != NULL); + status_t status; - - assert(handle); - status = kStatus_Success; /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); /* Return busy if another transaction is in progress. */ if (handle->isBusy) @@ -1254,13 +1455,13 @@ static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, } /* Save transfer into handle. */ - handle->transfer.txData = (const uint8_t *)(uintptr_t)txData; + handle->transfer.txData = (const uint8_t *)txData; handle->transfer.txSize = txSize; handle->transfer.rxData = (uint8_t *)rxData; handle->transfer.rxSize = rxSize; handle->transfer.transferredCount = 0; - handle->transfer.eventMask = eventMask | kI2C_SlaveTransmitEvent | kI2C_SlaveReceiveEvent; - handle->isBusy = true; + handle->transfer.eventMask = eventMask | (uint32_t)kI2C_SlaveTransmitEvent | (uint32_t)kI2C_SlaveReceiveEvent; + handle->isBusy = true; /* Set the SLVEN bit to 1 in the CFG register. */ I2C_SlaveEnable(base, true); @@ -1269,7 +1470,7 @@ static status_t I2C_SlaveTransferNonBlockingInternal(I2C_Type *base, base->STAT |= 0u; /* Enable I2C internal IRQ sources. */ - I2C_EnableInterrupts(base, kI2C_SlaveIrqFlags); + I2C_EnableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); return status; } @@ -1376,7 +1577,7 @@ void I2C_SlaveSetAddress(I2C_Type *base, */ void I2C_SlaveGetDefaultConfig(i2c_slave_config_t *slaveConfig) { - assert(slaveConfig); + assert(slaveConfig != NULL); i2c_slave_config_t mySlaveConfig = {0}; @@ -1414,7 +1615,7 @@ status_t I2C_SlaveInit(I2C_Type *base, const i2c_slave_config_t *slaveConfig, ui return status; } - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2C); /* I2C Clock Divider register */ base->CLKDIV = divVal; @@ -1474,14 +1675,14 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) + if (stat == (uint32_t)kStatus_I2C_Timeout) { return kStatus_I2C_Timeout; } /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); /* in I2C_SlaveSend() it shall be either slaveAddress or slaveTransmit */ if (!(slaveAddress || slaveTransmit)) @@ -1497,16 +1698,16 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) + if (stat == (uint32_t)kStatus_I2C_Timeout) { return kStatus_I2C_Timeout; } } /* send bytes up to txSize */ - while (txSize) + while (txSize != 0U) { - slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); + slaveTransmit = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_TX); if (!slaveTransmit) { @@ -1524,11 +1725,11 @@ status_t I2C_SlaveWriteBlocking(I2C_Type *base, const uint8_t *txBuff, size_t tx buf++; txSize--; - if (txSize) + if (txSize != 0U) { /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) + if (stat == (uint32_t)kStatus_I2C_Timeout) { return kStatus_I2C_Timeout; } @@ -1561,14 +1762,14 @@ status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) + if (stat == (uint32_t)kStatus_I2C_Timeout) { return kStatus_I2C_Timeout; } /* Get slave machine state */ - slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); + slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); /* in I2C_SlaveReceive() it shall be either slaveAddress or slaveReceive */ if (!(slaveAddress || slaveReceive)) @@ -1584,16 +1785,16 @@ status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) + if (stat == (uint32_t)kStatus_I2C_Timeout) { return kStatus_I2C_Timeout; } } /* receive bytes up to rxSize */ - while (rxSize) + while (rxSize != 0U) { - slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); + slaveReceive = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_RX); if (!slaveReceive) { @@ -1611,11 +1812,11 @@ status_t I2C_SlaveReadBlocking(I2C_Type *base, uint8_t *rxBuff, size_t rxSize) buf++; rxSize--; - if (rxSize) + if (rxSize != 0U) { /* wait for SLVPENDING */ stat = I2C_SlavePollPending(base); - if (stat == kStatus_I2C_Timeout) + if (stat == (uint32_t)kStatus_I2C_Timeout) { return kStatus_I2C_Timeout; } @@ -1642,12 +1843,14 @@ void I2C_SlaveTransferCreateHandle(I2C_Type *base, i2c_slave_transfer_callback_t callback, void *userData) { - uint32_t instance; + assert(handle != NULL); - assert(handle); + uint32_t instance; + i2c_to_flexcomm_t handler; + handler.i2c_slave_handler = I2C_SlaveTransferHandleIRQ; /* Clear out the handle. */ - memset(handle, 0, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); /* Look up instance number */ instance = I2C_GetInstance(base); @@ -1662,11 +1865,11 @@ void I2C_SlaveTransferCreateHandle(I2C_Type *base, /* store pointer to handle into transfer struct */ handle->transfer.handle = handle; - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_SlaveTransferHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); - EnableIRQ(s_i2cIRQ[instance]); + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); + (void)EnableIRQ(s_i2cIRQ[instance]); } /*! @@ -1712,9 +1915,9 @@ status_t I2C_SlaveTransferNonBlocking(I2C_Type *base, i2c_slave_handle_t *handle */ status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, size_t *count) { - assert(handle); + assert(handle != NULL); - if (!count) + if (NULL == count) { return kStatus_InvalidArgument; } @@ -1743,14 +1946,14 @@ status_t I2C_SlaveTransferGetCount(I2C_Type *base, i2c_slave_handle_t *handle, s void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) { /* Disable I2C IRQ sources while we configure stuff. */ - I2C_DisableInterrupts(base, kI2C_SlaveIrqFlags); + I2C_DisableInterrupts(base, (uint32_t)kI2C_SlaveIrqFlags); /* Set the SLVEN bit to 0 in the CFG register. */ I2C_SlaveEnable(base, false); handle->isBusy = false; - handle->transfer.txSize = 0; - handle->transfer.rxSize = 0; + handle->transfer.txSize = 0U; + handle->transfer.rxSize = 0U; } /*! @@ -1763,22 +1966,26 @@ void I2C_SlaveTransferAbort(I2C_Type *base, i2c_slave_handle_t *handle) void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) { uint32_t i2cStatus = base->STAT; + uint8_t tmpdata; + size_t txSize; + size_t rxSize; - if (i2cStatus & I2C_STAT_SLVDESEL_MASK) + if ((i2cStatus & I2C_STAT_SLVDESEL_MASK) != 0U) { I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveDeselectedEvent); I2C_SlaveClearStatusFlags(base, I2C_STAT_SLVDESEL_MASK); } /* SLVPENDING flag is cleared by writing I2C_SLVCTL_SLVCONTINUE_MASK to SLVCTL register */ - if (i2cStatus & I2C_STAT_SLVPENDING_MASK) + if ((i2cStatus & I2C_STAT_SLVPENDING_MASK) != 0U) { - bool slaveAddress = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR); + bool slaveAddress = + (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == (uint32_t)I2C_STAT_SLVST_ADDR); if (slaveAddress) { - I2C_SlaveAddressIRQ(base, handle); I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveAddressMatchEvent); + (void)I2C_SlaveAddressIRQ(base, handle); } else { @@ -1786,30 +1993,35 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) { case kI2C_SlaveFsmReceive: { - bool slaveReceive = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_RX); + bool slaveReceive = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == + (uint32_t)I2C_STAT_SLVST_RX); if (slaveReceive) { + rxSize = handle->transfer.rxSize; /* if we have no receive buffer in this transfer, call callback to get new */ - if ((handle->transfer.rxData == NULL) || (handle->transfer.rxSize == 0)) + if ((handle->transfer.rxData == NULL) || (rxSize == 0U)) { I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveReceiveEvent); } + rxSize = handle->transfer.rxSize; /* receive a byte */ - if ((handle->transfer.rxData) && (handle->transfer.rxSize)) + if ((handle->transfer.rxData != NULL) && (rxSize != 0U)) { /* continue transaction */ base->SLVCTL = I2C_SLVCTL_SLVCONTINUE_MASK; - *(handle->transfer.rxData) = (uint8_t)base->SLVDAT; + tmpdata = (uint8_t)base->SLVDAT; + *(handle->transfer.rxData) = tmpdata; (handle->transfer.rxSize)--; (handle->transfer.rxData)++; (handle->transfer.transferredCount)++; } + rxSize = handle->transfer.rxSize; + txSize = handle->transfer.txSize; /* is this last transaction for this transfer? allow next transaction */ - if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) + if ((0U == rxSize) && (0U == txSize)) { handle->isBusy = false; I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); @@ -1824,19 +2036,21 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) case kI2C_SlaveFsmTransmit: { - bool slaveTransmit = - (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_TX); + bool slaveTransmit = (((i2cStatus & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == + (uint32_t)I2C_STAT_SLVST_TX); if (slaveTransmit) { + txSize = handle->transfer.txSize; /* if we have no data in this transfer, call callback to get new */ - if ((handle->transfer.txData == NULL) || (handle->transfer.txSize == 0)) + if ((handle->transfer.txData == NULL) || (txSize == 0U)) { I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveTransmitEvent); } + txSize = handle->transfer.txSize; /* transmit a byte */ - if ((handle->transfer.txData) && (handle->transfer.txSize)) + if ((handle->transfer.txData != NULL) && (txSize != 0U)) { base->SLVDAT = *(handle->transfer.txData); /* continue transaction */ @@ -1846,8 +2060,10 @@ void I2C_SlaveTransferHandleIRQ(I2C_Type *base, i2c_slave_handle_t *handle) (handle->transfer.transferredCount)++; } + rxSize = handle->transfer.rxSize; + txSize = handle->transfer.txSize; /* is this last transaction for this transfer? allow next transaction */ - if ((0 == handle->transfer.rxSize) && (0 == handle->transfer.txSize)) + if ((0U == rxSize) && (0U == txSize)) { handle->isBusy = false; I2C_SlaveInvokeEvent(base, handle, kI2C_SlaveCompletionEvent); diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.h index 50bc3588ce..b521a1ad75 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -27,8 +27,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief I2C driver version 2.0.5. */ -#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*! @brief I2C driver version. */ +#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*@}*/ /*! @brief Retry times for waiting flag. */ @@ -36,20 +36,26 @@ #define I2C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ #endif +/*! @brief Whether to ignore the nack signal of the last byte during master transmit. */ +#ifndef I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK +#define I2C_MASTER_TRANSMIT_IGNORE_LAST_NACK \ + 1U /* Define to one means master ignores the last byte's nack and considers the transfer successful. */ +#endif + /* definitions for MSTCODE bits in I2C Status register STAT */ -#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */ -#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */ -#define I2C_STAT_MSTCODE_TXREADY (2) /*!< Master Transmit Ready State Code */ -#define I2C_STAT_MSTCODE_NACKADR (3) /*!< Master NACK by slave on address State Code */ -#define I2C_STAT_MSTCODE_NACKDAT (4) /*!< Master NACK by slave on data State Code */ +#define I2C_STAT_MSTCODE_IDLE (0U) /*!< Master Idle State Code */ +#define I2C_STAT_MSTCODE_RXREADY (1U) /*!< Master Receive Ready State Code */ +#define I2C_STAT_MSTCODE_TXREADY (2U) /*!< Master Transmit Ready State Code */ +#define I2C_STAT_MSTCODE_NACKADR (3U) /*!< Master NACK by slave on address State Code */ +#define I2C_STAT_MSTCODE_NACKDAT (4U) /*!< Master NACK by slave on data State Code */ /* definitions for SLVSTATE bits in I2C Status register STAT */ #define I2C_STAT_SLVST_ADDR (0) -#define I2C_STAT_SLVST_RX (1) -#define I2C_STAT_SLVST_TX (2) +#define I2C_STAT_SLVST_RX (1) +#define I2C_STAT_SLVST_TX (2) /*! @brief I2C status return codes. */ -enum _i2c_status +enum { kStatus_I2C_Busy = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 0), /*!< The master is already performing a transfer. */ kStatus_I2C_Idle = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 1), /*!< The slave driver is idle. */ @@ -62,33 +68,112 @@ enum _i2c_status kStatus_I2C_NoTransferInProgress = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */ kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */ - kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), - kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), - kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 10), /*!< Timeout poling status flags. */ - kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ + kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8), /*!< Start and stop error. */ + kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9), /*!< Unexpected state. */ + kStatus_I2C_Timeout = + MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, + 10), /*!< Timeout when waiting for I2C master/slave pending status to set to continue transfer. */ + kStatus_I2C_Addr_Nak = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 11), /*!< NAK received for Address */ + kStatus_I2C_EventTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 12), /*!< Timeout waiting for bus event. */ + kStatus_I2C_SclLowTimeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 13), /*!< Timeout SCL signal remains low. */ }; /*! @} */ +/*! + * @addtogroup i2c_driver + * @{ + */ + +/*! + * @brief I2C status flags. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i2c_status_flags +{ + kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 0 */ + kI2C_MasterArbitrationLostFlag = + I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus. bit 4*/ + kI2C_MasterStartStopErrorFlag = + I2C_STAT_MSTSTSTPERR_MASK, /*!< There was an error during start or stop phase of the transaction. bit 6 */ + kI2C_MasterIdleFlag = 1UL << 5U, /*!< The I2C master idle status. bit 5 */ + kI2C_MasterRxReadyFlag = 1UL << I2C_STAT_MSTSTATE_SHIFT, /*!< The I2C master rx ready status. bit 1 */ + kI2C_MasterTxReadyFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 1U), /*!< The I2C master tx ready status. bit 2 */ + kI2C_MasterAddrNackFlag = 1UL << 7U, /*!< The I2C master address nack status. bit 7 */ + kI2C_MasterDataNackFlag = 1UL << (I2C_STAT_MSTSTATE_SHIFT + 2U), /*!< The I2C master data nack status. bit 3 */ + kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. bit 8 */ + kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 + = yes, 1 = no). bit 11 */ + kI2C_SlaveSelected = + I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. bit 14 */ + kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK, /*!< Indicates that slave was previously deselected (deselect event + took place, w1c). bit 15 */ + kI2C_SlaveAddressedFlag = 1UL << 22U, /*!< One of the I2C slave's 4 addresses is matched. bit 22 */ + kI2C_SlaveReceiveFlag = 1UL << I2C_STAT_SLVSTATE_SHIFT, /*!< Slave receive data available. bit 9 */ + kI2C_SlaveTransmitFlag = 1UL << (I2C_STAT_SLVSTATE_SHIFT + 1U), /*!< Slave data can be transmitted. bit 10 */ + kI2C_SlaveAddress0MatchFlag = 1UL << 20U, /*!< Slave address0 match. bit 20 */ + kI2C_SlaveAddress1MatchFlag = 1UL << I2C_STAT_SLVIDX_SHIFT, /*!< Slave address1 match. bit 12 */ + kI2C_SlaveAddress2MatchFlag = 1UL << (I2C_STAT_SLVIDX_SHIFT + 1U), /*!< Slave address2 match. bit 13 */ + kI2C_SlaveAddress3MatchFlag = 1UL << 21U, /*!< Slave address3 match. bit 21 */ + kI2C_MonitorReadyFlag = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. bit 16 */ + kI2C_MonitorOverflowFlag = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. bit 17 */ + kI2C_MonitorActiveFlag = I2C_STAT_MONACTIVE_MASK, /*!< The monitor is active. bit 18 */ + kI2C_MonitorIdleFlag = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. bit 19 */ + kI2C_EventTimeoutFlag = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. bit 24 */ + kI2C_SclTimeoutFlag = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. bit 25 */ + + /* All master flags that can be cleared by software */ + kI2C_MasterAllClearFlags = kI2C_MasterArbitrationLostFlag | kI2C_MasterStartStopErrorFlag, + /* All slave flags that can be cleared by software */ + kI2C_SlaveAllClearFlags = kI2C_SaveDeselected, + /* All common flags that can be cleared by software */ + kI2C_CommonAllClearFlags = + kI2C_MonitorOverflowFlag | kI2C_MonitorIdleFlag | kI2C_EventTimeoutFlag | kI2C_SclTimeoutFlag, +}; + +/*! + * @brief I2C interrupt enable. + * + * @note These enums are meant to be OR'd together to form a bit mask. + */ +enum _i2c_interrupt_enable +{ + kI2C_MasterPendingInterruptEnable = + I2C_STAT_MSTPENDING_MASK, /*!< The I2C master communication pending interrupt. */ + kI2C_MasterArbitrationLostInterruptEnable = + I2C_STAT_MSTARBLOSS_MASK, /*!< The I2C master arbitration lost interrupt. */ + kI2C_MasterStartStopErrorInterruptEnable = + I2C_STAT_MSTSTSTPERR_MASK, /*!< The I2C master start/stop timing error interrupt. */ + kI2C_SlavePendingInterruptEnable = I2C_STAT_SLVPENDING_MASK, /*!< The I2C slave communication pending interrupt. */ + kI2C_SlaveNotStretchingInterruptEnable = + I2C_STAT_SLVNOTSTR_MASK, /*!< The I2C slave not streching interrupt, deep-sleep mode can be entered only when + this interrupt occurs. */ + kI2C_SlaveDeselectedInterruptEnable = I2C_STAT_SLVDESEL_MASK, /*!< The I2C slave deselection interrupt. */ + kI2C_MonitorReadyInterruptEnable = I2C_STAT_MONRDY_MASK, /*!< The I2C monitor ready interrupt. */ + kI2C_MonitorOverflowInterruptEnable = I2C_STAT_MONOV_MASK, /*!< The monitor data overrun interrupt. */ + kI2C_MonitorIdleInterruptEnable = I2C_STAT_MONIDLE_MASK, /*!< The monitor idle interrupt. */ + kI2C_EventTimeoutInterruptEnable = I2C_STAT_EVENTTIMEOUT_MASK, /*!< The bus event timeout interrupt. */ + kI2C_SclTimeoutInterruptEnable = I2C_STAT_SCLTIMEOUT_MASK, /*!< The SCL timeout interrupt. */ + + /* All master interrupt sources */ + kI2C_MasterAllInterruptEnable = kI2C_MasterPendingInterruptEnable | kI2C_MasterArbitrationLostInterruptEnable | + kI2C_MasterStartStopErrorInterruptEnable, + /* All slave interrupt sources */ + kI2C_SlaveAllInterruptEnable = + kI2C_SlavePendingInterruptEnable | kI2C_SlaveNotStretchingInterruptEnable | kI2C_SlaveDeselectedInterruptEnable, + /* All common interrupt sources */ + kI2C_CommonAllInterruptEnable = kI2C_MonitorReadyInterruptEnable | kI2C_MonitorOverflowInterruptEnable | + kI2C_MonitorIdleInterruptEnable | kI2C_EventTimeoutInterruptEnable | + kI2C_SclTimeoutInterruptEnable, +}; +/*! @} */ + /*! * @addtogroup i2c_master_driver * @{ */ -/*! - * @brief I2C master peripheral flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_master_flags -{ - kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_MasterArbitrationLostFlag = - I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */ - kI2C_MasterStartStopErrorFlag = - I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */ -}; - /*! @brief Direction of master and slave transfers. */ typedef enum _i2c_direction { @@ -110,6 +195,7 @@ typedef struct _i2c_master_config bool enableMaster; /*!< Whether to enable master mode. */ uint32_t baudRate_Bps; /*!< Desired baud rate in bits per second. */ bool enableTimeout; /*!< Enable internal timeout function. */ + uint8_t timeout_Ms; /*!< Event timeout and SCL low timeout value. */ } i2c_master_config_t; /* Forward declaration of the transfer descriptor and handle typedefs. */ @@ -154,6 +240,7 @@ enum _i2c_transfer_states kIdleState = 0, kTransmitSubaddrState, kTransmitDataState, + kReceiveDataBeginState, kReceiveDataState, kReceiveLastDataState, kStartState, @@ -170,7 +257,7 @@ struct _i2c_master_transfer { uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i2c_master_transfer_flags for available options. Set to 0 or #kI2C_TransferDefaultFlag for normal transfers. */ - uint16_t slaveAddress; /*!< The 7-bit slave address. */ + uint8_t slaveAddress; /*!< The 7-bit slave address. */ i2c_direction_t direction; /*!< Either #kI2C_Read or #kI2C_Write. */ uint32_t subaddress; /*!< Sub address. Transferred MSB first. */ size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */ @@ -190,7 +277,8 @@ struct _i2c_master_handle uint8_t *buf; /*!< Buffer pointer for current state. */ uint32_t remainingSubaddr; uint8_t subaddrBuf[4]; - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ + i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ i2c_master_transfer_callback_t completionCallback; /*!< Callback function pointer. */ void *userData; /*!< Application data passed to callback. */ }; @@ -201,22 +289,6 @@ struct _i2c_master_handle * @addtogroup i2c_slave_driver * @{ */ - -/*! - * @brief I2C slave peripheral flags. - * - * @note These enums are meant to be OR'd together to form a bit mask. - */ -enum _i2c_slave_flags -{ - kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */ - kI2C_SlaveNotStretching = - I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */ - kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */ - kI2C_SaveDeselected = - I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */ -}; - /*! @brief I2C slave address register. */ typedef enum _i2c_slave_address_register { @@ -359,6 +431,11 @@ struct _i2c_slave_handle void *userData; /*!< Callback parameter passed to callback. */ }; +/*! @brief Typedef for master interrupt handler. */ +typedef void (*flexcomm_i2c_master_irq_handler_t)(I2C_Type *base, i2c_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*flexcomm_i2c_slave_irq_handler_t)(I2C_Type *base, i2c_slave_handle_t *handle); /*! @} */ /******************************************************************************* @@ -451,11 +528,11 @@ static inline void I2C_MasterEnable(I2C_Type *base, bool enable) { if (enable) { - base->CFG = (base->CFG & I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; + base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) | I2C_CFG_MSTEN_MASK; } else { - base->CFG = (base->CFG & I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; + base->CFG = (base->CFG & (uint32_t)I2C_CFG_MASK) & ~I2C_CFG_MSTEN_MASK; } } @@ -463,7 +540,6 @@ static inline void I2C_MasterEnable(I2C_Type *base, bool enable) /*! @name Status */ /*@{*/ - /*! * @brief Gets the I2C status flags. * @@ -474,16 +550,33 @@ static inline void I2C_MasterEnable(I2C_Type *base, bool enable) * @return State of the status flags: * - 1: related status flag is set. * - 0: related status flag is not set. - * @see _i2c_master_flags + * @see @ref _i2c_status_flags. */ -static inline uint32_t I2C_GetStatusFlags(I2C_Type *base) +uint32_t I2C_GetStatusFlags(I2C_Type *base); + +/*! + * @brief Clears the I2C status flag state. + * + * Refer to kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags to see + * the clearable flags. Attempts to clear other flags has no effect. + * + * @param base The I2C peripheral base address. + * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of the members in + * kI2C_CommonAllClearStatusFlags, kI2C_MasterAllClearStatusFlags and kI2C_SlaveAllClearStatusFlags. You may pass + * the result of a previous call to I2C_GetStatusFlags(). + * @see #_i2c_status_flags, _i2c_master_status_flags and _i2c_slave_status_flags. + */ +static inline void I2C_ClearStatusFlags(I2C_Type *base, uint32_t statusMask) { - return base->STAT; + /* Only deal with the clearable flags */ + statusMask &= + ((uint32_t)kI2C_CommonAllClearFlags | (uint32_t)kI2C_MasterAllClearFlags | (uint32_t)kI2C_SlaveAllClearFlags); + base->STAT = statusMask; } /*! * @brief Clears the I2C master status flag state. - * + * @deprecated Do not use this function. It has been superceded by @ref I2C_ClearStatusFlags * The following status register flags can be cleared: * - #kI2C_MasterArbitrationLostFlag * - #kI2C_MasterStartStopErrorFlag @@ -492,9 +585,9 @@ static inline uint32_t I2C_GetStatusFlags(I2C_Type *base) * * @param base The I2C peripheral base address. * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_master_flags enumerators OR'd together. You may pass the result of a previous call to + * #_i2c_status_flags enumerators OR'd together. You may pass the result of a previous call to * I2C_GetStatusFlags(). - * @see _i2c_master_flags. + * @see _i2c_status_flags. */ static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMask) { @@ -508,10 +601,10 @@ static inline void I2C_MasterClearStatusFlags(I2C_Type *base, uint32_t statusMas /*@{*/ /*! - * @brief Enables the I2C master interrupt requests. + * @brief Enables the I2C interrupt requests. * * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to enable. See #_i2c_master_flags for the set + * @param interruptMask Bit mask of interrupts to enable. See #_i2c_interrupt_enable for the set * of constants that should be OR'd together to form the bit mask. */ static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) @@ -520,10 +613,10 @@ static inline void I2C_EnableInterrupts(I2C_Type *base, uint32_t interruptMask) } /*! - * @brief Disables the I2C master interrupt requests. + * @brief Disables the I2C interrupt requests. * * @param base The I2C peripheral base address. - * @param interruptMask Bit mask of interrupts to disable. See #_i2c_master_flags for the set + * @param interruptMask Bit mask of interrupts to disable. See #_i2c_interrupt_enable for the set * of constants that should be OR'd together to form the bit mask. */ static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) @@ -532,10 +625,10 @@ static inline void I2C_DisableInterrupts(I2C_Type *base, uint32_t interruptMask) } /*! - * @brief Returns the set of currently enabled I2C master interrupt requests. + * @brief Returns the set of currently enabled I2C interrupt requests. * * @param base The I2C peripheral base address. - * @return A bitmask composed of #_i2c_master_flags enumerators OR'd together to indicate the + * @return A bitmask composed of #_i2c_interrupt_enable enumerators OR'd together to indicate the * set of enabled interrupts. */ static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) @@ -560,6 +653,18 @@ static inline uint32_t I2C_GetEnabledInterrupts(I2C_Type *base) */ void I2C_MasterSetBaudRate(I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz); +/*! + * @brief Sets the I2C bus timeout value. + * + * If the SCL signal remains low or bus does not have event longer than the timeout value, kI2C_SclTimeoutFlag or + * kI2C_EventTimeoutFlag is set. This can indicete the bus is held by slave or any fault occurs to the I2C module. + * + * @param base The I2C peripheral base address. + * @param timeout_Ms Timeout value in millisecond. + * @param srcClock_Hz I2C functional clock frequency in Hertz. + */ +void I2C_MasterSetTimeoutValue(I2C_Type *base, uint8_t timeout_Ms, uint32_t srcClock_Hz); + /*! * @brief Returns whether the bus is idle. * @@ -658,6 +763,7 @@ status_t I2C_MasterReadBlocking(I2C_Type *base, void *rxBuff, size_t rxSize, uin * @retval kStatus_I2C_Timeout Transfer error, wait signal timeout. * @retval kStatus_I2C_ArbitrationLost Transfer error, arbitration lost. * @retval kStataus_I2C_Nak Transfer error, receive NAK during transfer. + * @retval kStataus_I2C_Addr_Nak Transfer error, receive NAK during addressing. */ status_t I2C_MasterTransferBlocking(I2C_Type *base, i2c_master_transfer_t *xfer); @@ -835,7 +941,7 @@ static inline void I2C_SlaveEnable(I2C_Type *base, bool enable) * * @param base The I2C peripheral base address. * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of - * #_i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to + * _i2c_slave_flags enumerators OR'd together. You may pass the result of a previous call to * I2C_SlaveGetStatusFlags(). * @see _i2c_slave_flags. */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c index 98cb88f283..45d47e5907 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -25,6 +25,15 @@ typedef struct _i2c_master_dma_private_handle i2c_master_dma_handle_t *handle; } i2c_master_dma_private_handle_t; +/*! + * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_i2c_dma_master_irq_handler_t` + */ +typedef union i2c_dma_to_flexcomm +{ + flexcomm_i2c_dma_master_irq_handler_t i2c_dma_master_handler; + flexcomm_irq_handler_t flexcomm_handler; +} i2c_dma_to_flexcomm_t; + /******************************************************************************* * Prototypes ******************************************************************************/ @@ -35,7 +44,7 @@ typedef struct _i2c_master_dma_private_handle * @param handle DMA handler for I2C master DMA driver * @param userData user param passed to the callback function */ -static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData); +static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode); /*! * @brief Set up master transfer, send slave address and sub address(if any), wait until the @@ -49,24 +58,30 @@ static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, i2c_master_transfer_t *xfer); +static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle); + +/*! + * @brief Execute states until the transfer is done. + * @param handle Master nonblocking driver handle. + * @param[out] isDone Set to true if the transfer has completed. + * @retval #kStatus_Success + * @retval #kStatus_I2C_ArbitrationLost + * @retval #kStatus_I2C_Nak + */ +static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone); /******************************************************************************* * Variables ******************************************************************************/ -/*transfer = *xfer; transfer = &(handle->transfer); - handle->transferCount = 0; - handle->remainingBytesDMA = 0; + handle->transferCount = 0U; + handle->remainingBytesDMA = 0U; handle->buf = (uint8_t *)transfer->data; - handle->remainingSubaddr = 0; + handle->remainingSubaddr = 0U; - if (transfer->flags & kI2C_TransferNoStartFlag) + if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) { - /* Start condition shall be ommited, switch directly to next phase */ - if (transfer->dataSize == 0) + handle->checkAddrNack = false; + /* Start condition shall not be ommited, switch directly to next phase */ + if (transfer->dataSize == 0U) { - handle->state = kStopState; + handle->state = (uint8_t)kStopState; } else if (handle->transfer.direction == kI2C_Write) { - handle->state = xfer->dataSize = kTransmitDataState; + handle->state = (uint8_t)kTransmitDataState; } else if (handle->transfer.direction == kI2C_Read) { - handle->state = (xfer->dataSize == 1) ? kReceiveLastDataState : kReceiveDataState; + handle->state = (xfer->dataSize == 1U) ? (uint8_t)kReceiveLastDataState : (uint8_t)kReceiveDataState; } else { @@ -103,7 +119,7 @@ static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base, } else { - if (transfer->subaddressSize != 0) + if (transfer->subaddressSize != 0U) { int i; uint32_t subaddress; @@ -115,15 +131,16 @@ static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base, /* Prepare subaddress transmit buffer, most significant byte is stored at the lowest address */ subaddress = xfer->subaddress; - for (i = xfer->subaddressSize - 1; i >= 0; i--) + for (i = (int)xfer->subaddressSize - 1; i >= 0; i--) { - handle->subaddrBuf[i] = subaddress & 0xff; + handle->subaddrBuf[i] = (uint8_t)subaddress & 0xffU; subaddress >>= 8; } handle->remainingSubaddr = transfer->subaddressSize; } - handle->state = kStartState; + handle->state = (uint8_t)kStartState; + handle->checkAddrNack = true; } return kStatus_Success; @@ -131,14 +148,18 @@ static status_t I2C_InitTransferStateMachineDMA(I2C_Type *base, static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) { - int transfer_size; + uint32_t transfer_size; dma_transfer_config_t xferConfig; + uint32_t address; + address = (uint32_t)&base->MSTDAT; /* Update transfer count */ - handle->transferCount = handle->buf - (uint8_t *)handle->transfer.data; + int32_t count = handle->buf - (uint8_t *)handle->transfer.data; + assert(count >= 0); + handle->transferCount = (uint32_t)count; /* Check if there is anything to be transferred at all */ - if (handle->remainingBytesDMA == 0) + if (handle->remainingBytesDMA == 0U) { /* No data to be transferrred, disable DMA */ base->MSTCTL = 0; @@ -147,20 +168,20 @@ static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) /* Calculate transfer size */ transfer_size = handle->remainingBytesDMA; - if (transfer_size > I2C_MAX_DMA_TRANSFER_COUNT) + if (transfer_size > (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT) { - transfer_size = I2C_MAX_DMA_TRANSFER_COUNT; + transfer_size = (uint32_t)I2C_MAX_DMA_TRANSFER_COUNT; } switch (handle->transfer.direction) { case kI2C_Write: - DMA_PrepareTransfer(&xferConfig, handle->buf, (void *)&base->MSTDAT, sizeof(uint8_t), transfer_size, + DMA_PrepareTransfer(&xferConfig, handle->buf, (uint32_t *)address, sizeof(uint8_t), transfer_size, kDMA_MemoryToPeripheral, NULL); break; case kI2C_Read: - DMA_PrepareTransfer(&xferConfig, (void *)&base->MSTDAT, handle->buf, sizeof(uint8_t), transfer_size, + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, handle->buf, sizeof(uint8_t), transfer_size, kDMA_PeripheralToMemory, NULL); break; @@ -170,21 +191,14 @@ static void I2C_RunDMATransfer(I2C_Type *base, i2c_master_dma_handle_t *handle) break; } - DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); + (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); DMA_StartTransfer(handle->dmaHandle); handle->remainingBytesDMA -= transfer_size; handle->buf += transfer_size; + handle->checkAddrNack = false; } -/*! - * @brief Execute states until the transfer is done. - * @param handle Master nonblocking driver handle. - * @param[out] isDone Set to true if the transfer has completed. - * @retval #kStatus_Success - * @retval #kStatus_I2C_ArbitrationLost - * @retval #kStatus_I2C_Nak - */ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, bool *isDone) { uint32_t status; @@ -192,7 +206,9 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha struct _i2c_master_transfer *transfer; dma_transfer_config_t xferConfig; status_t err; - uint32_t start_flag = 0; + uint32_t start_flag = 0U; + uint32_t address; + address = (uint32_t)&base->MSTDAT; transfer = &(handle->transfer); @@ -200,7 +216,7 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha status = I2C_GetStatusFlags(base); - if (status & I2C_STAT_MSTARBLOSS_MASK) + if ((status & (uint32_t)I2C_STAT_MSTARBLOSS_MASK) != 0U) { I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK); DMA_AbortTransfer(handle->dmaHandle); @@ -208,7 +224,7 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha return kStatus_I2C_ArbitrationLost; } - if (status & I2C_STAT_MSTSTSTPERR_MASK) + if ((status & (uint32_t)I2C_STAT_MSTSTSTPERR_MASK) != 0U) { I2C_MasterClearStatusFlags(base, I2C_STAT_MSTSTSTPERR_MASK); DMA_AbortTransfer(handle->dmaHandle); @@ -216,62 +232,90 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha return kStatus_I2C_StartStopError; } - if ((status & I2C_STAT_MSTPENDING_MASK) == 0) + /* Event timeout happens when the time since last bus event has been longer than the time specified by TIMEOUT + register. eg: Start signal fails to generate, no error status is set and transfer hangs if glitch on bus happens + before, the timeout status can be used to avoid the transfer hangs indefinitely. */ + if ((status & (uint32_t)kI2C_EventTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_EventTimeoutFlag); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_EventTimeout; + } + + /* SCL timeout happens when the slave is holding the SCL line low and the time has been longer than the time + specified by TIMEOUT register. */ + if ((status & (uint32_t)kI2C_SclTimeoutFlag) != 0U) + { + I2C_ClearStatusFlags(base, (uint32_t)kI2C_SclTimeoutFlag); + DMA_AbortTransfer(handle->dmaHandle); + base->MSTCTL = 0; + return kStatus_I2C_SclLowTimeout; + } + + if ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U) { return kStatus_I2C_Busy; } /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + master_state = (base->STAT & (uint32_t)I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - if ((master_state == I2C_STAT_MSTCODE_NACKADR) || (master_state == I2C_STAT_MSTCODE_NACKDAT)) + if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (master_state == (uint32_t)I2C_STAT_MSTCODE_NACKDAT)) { /* Slave NACKed last byte, issue stop and return error */ DMA_AbortTransfer(handle->dmaHandle); base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; - return kStatus_I2C_Nak; + handle->state = (uint8_t)kWaitForCompletionState; + if ((master_state == (uint32_t)I2C_STAT_MSTCODE_NACKADR) || (handle->checkAddrNack == true)) + { + return kStatus_I2C_Addr_Nak; + } + else + { + return kStatus_I2C_Nak; + } } err = kStatus_Success; - if (handle->state == kStartState) + if (handle->state == (uint8_t)kStartState) { /* set start flag for later use */ start_flag = I2C_MSTCTL_MSTSTART_MASK; - if (handle->remainingSubaddr) + if (handle->remainingSubaddr != 0U) { base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - handle->state = kTransmitSubaddrState; + handle->state = (uint8_t)kTransmitSubaddrState; } else if (transfer->direction == kI2C_Write) { base->MSTDAT = (uint32_t)transfer->slaveAddress << 1; - if (transfer->dataSize == 0) + if (transfer->dataSize == 0U) { /* No data to be transferred, initiate start and schedule stop */ base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = kStopState; + handle->state = (uint8_t)kStopState; return err; } - handle->state = kTransmitDataState; + handle->state = (uint8_t)kTransmitDataState; } - else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0)) + else if ((transfer->direction == kI2C_Read) && (transfer->dataSize > 0U)) { base->MSTDAT = ((uint32_t)transfer->slaveAddress << 1) | 1u; - if (transfer->dataSize == 1) + if (transfer->dataSize == 1U) { /* The very last byte is always received by means of SW */ base->MSTCTL = I2C_MSTCTL_MSTSTART_MASK; - handle->state = kReceiveLastDataState; + handle->state = (uint8_t)kReceiveLastDataState; return err; } - handle->state = kReceiveDataState; + handle->state = (uint8_t)kReceiveDataState; } else { - handle->state = kIdleState; + handle->state = (uint8_t)kIdleState; err = kStatus_I2C_UnexpectedState; return err; } @@ -279,8 +323,8 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha switch (handle->state) { - case kTransmitSubaddrState: - if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) + case (uint8_t)kTransmitSubaddrState: + if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) { return kStatus_I2C_UnexpectedState; } @@ -288,26 +332,26 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; /* Prepare and submit DMA transfer. */ - DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t), + DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (uint32_t *)address, sizeof(uint8_t), handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL); - DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); + (void)DMA_SubmitTransfer(handle->dmaHandle, &xferConfig); DMA_StartTransfer(handle->dmaHandle); handle->remainingSubaddr = 0; - if (transfer->dataSize) + if (transfer->dataSize != 0U) { /* There is data to be transferred, if there is write to read turnaround it is necessary to perform * repeated start */ - handle->state = (transfer->direction == kI2C_Read) ? kStartState : kTransmitDataState; + handle->state = (transfer->direction == kI2C_Read) ? (uint8_t)kStartState : (uint8_t)kTransmitDataState; } else { /* No more data, schedule stop condition */ - handle->state = kStopState; + handle->state = (uint8_t)kStopState; } break; - case kTransmitDataState: - if ((master_state != I2C_STAT_MSTCODE_TXREADY) && (!start_flag)) + case (uint8_t)kTransmitDataState: + if ((master_state != (uint32_t)I2C_STAT_MSTCODE_TXREADY) && (0U == start_flag)) { return kStatus_I2C_UnexpectedState; } @@ -318,58 +362,71 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha I2C_RunDMATransfer(base, handle); /* Schedule stop condition */ - handle->state = kStopState; + handle->state = (uint8_t)kStopState; + handle->checkAddrNack = false; break; - case kReceiveDataState: - if ((master_state != I2C_STAT_MSTCODE_RXREADY) && (!start_flag)) + case (uint8_t)kReceiveDataState: + if ((master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) && (0U == start_flag)) { - return kStatus_I2C_UnexpectedState; + if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStartFlag)) + { + return kStatus_I2C_UnexpectedState; + } } base->MSTCTL = start_flag | I2C_MSTCTL_MSTDMA_MASK; - handle->remainingBytesDMA = handle->transfer.dataSize - 1; + handle->remainingBytesDMA = handle->transfer.dataSize - 1U; + if ((transfer->flags & (uint32_t)kI2C_TransferNoStartFlag) != 0U) + { + /* Read the master data register to avoid the data be read again */ + (void)base->MSTDAT; + } I2C_RunDMATransfer(base, handle); /* Schedule reception of last data byte */ - handle->state = kReceiveLastDataState; + handle->state = (uint8_t)kReceiveLastDataState; + handle->checkAddrNack = false; break; - case kReceiveLastDataState: - if (master_state != I2C_STAT_MSTCODE_RXREADY) + case (uint8_t)kReceiveLastDataState: + if (master_state != (uint32_t)I2C_STAT_MSTCODE_RXREADY) { return kStatus_I2C_UnexpectedState; } - ((uint8_t *)transfer->data)[transfer->dataSize - 1] = base->MSTDAT; + ((uint8_t *)transfer->data)[transfer->dataSize - 1U] = (uint8_t)base->MSTDAT; handle->transferCount++; /* No more data expected, issue NACK and STOP right away */ - base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; + if (0U == (transfer->flags & (uint32_t)kI2C_TransferNoStopFlag)) + { + base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; + } + handle->state = (uint8_t)kWaitForCompletionState; break; - case kStopState: - if (transfer->flags & kI2C_TransferNoStopFlag) + case (uint8_t)kStopState: + if ((transfer->flags & (uint32_t)kI2C_TransferNoStopFlag) != 0U) { /* Stop condition is omitted, we are done */ *isDone = true; - handle->state = kIdleState; + handle->state = (uint8_t)kIdleState; break; } /* Send stop condition */ base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; - handle->state = kWaitForCompletionState; + handle->state = (uint8_t)kWaitForCompletionState; break; - case kWaitForCompletionState: + case (uint8_t)kWaitForCompletionState: *isDone = true; - handle->state = kIdleState; + handle->state = (uint8_t)kIdleState; break; - case kStartState: - case kIdleState: + case (uint8_t)kStartState: + case (uint8_t)kIdleState: default: /* State machine shall not be invoked again once it enters the idle state */ err = kStatus_I2C_UnexpectedState; @@ -379,39 +436,42 @@ static status_t I2C_RunTransferStateMachineDMA(I2C_Type *base, i2c_master_dma_ha return err; } -void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) +static void I2C_MasterTransferDMAHandleIRQ(I2C_Type *base, i2c_master_dma_handle_t *handle) { bool isDone; status_t result; /* Don't do anything if we don't have a valid handle. */ - if (!handle) + if (NULL == handle) { return; } result = I2C_RunTransferStateMachineDMA(base, handle, &isDone); - if (isDone || (result != kStatus_Success)) + if ((result != kStatus_Success) || isDone) { + /* Restore handle to idle state. */ + handle->state = (uint8_t)kIdleState; + /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); + I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | + I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); /* Invoke callback. */ - if (handle->completionCallback) + if (handle->completionCallback != NULL) { handle->completionCallback(base, handle, result, handle->userData); } } } -static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData) +static void I2C_MasterTransferCallbackDMA(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) { i2c_master_dma_private_handle_t *dmaPrivateHandle; /* Don't do anything if we don't have a valid handle. */ - if (!handle) + if (NULL == handle) { return; } @@ -435,13 +495,15 @@ void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, void *userData, dma_handle_t *dmaHandle) { - uint32_t instance; + assert(handle != NULL); + assert(dmaHandle != NULL); - assert(handle); - assert(dmaHandle); + uint32_t instance; + i2c_dma_to_flexcomm_t handler; + handler.i2c_dma_master_handler = I2C_MasterTransferDMAHandleIRQ; /* Zero handle. */ - memset(handle, 0, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); /* Look up instance number */ instance = I2C_GetInstance(base); @@ -450,12 +512,12 @@ void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, handle->completionCallback = callback; handle->userData = userData; - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2C_MasterTransferDMAHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); - EnableIRQ(s_i2cIRQ[instance]); + I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | + I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); + (void)EnableIRQ(s_i2cIRQ[instance]); /* Set the handle for DMA. */ handle->dmaHandle = dmaHandle; @@ -463,7 +525,7 @@ void I2C_MasterTransferCreateHandleDMA(I2C_Type *base, s_dmaPrivateHandle[instance].base = base; s_dmaPrivateHandle[instance].handle = handle; - DMA_SetCallback(dmaHandle, (dma_callback)I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); + DMA_SetCallback(dmaHandle, I2C_MasterTransferCallbackDMA, &s_dmaPrivateHandle[instance]); } /*! @@ -482,12 +544,12 @@ status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, { status_t result; - assert(handle); - assert(xfer); + assert(handle != NULL); + assert(xfer != NULL); assert(xfer->subaddressSize <= sizeof(xfer->subaddress)); /* Return busy if another transaction is in progress. */ - if (handle->state != kIdleState) + if (handle->state != (uint8_t)kIdleState) { return kStatus_I2C_Busy; } @@ -499,8 +561,10 @@ status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); /* Enable I2C internal IRQ sources */ - I2C_EnableInterrupts(base, - I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_MSTPENDING_MASK); + /* Enable arbitration lost interrupt, start/stop error interrupt and master pending interrupt. + The master pending flag is not set during dma transfer. */ + I2C_EnableInterrupts(base, I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK | + I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); return result; } @@ -514,15 +578,15 @@ status_t I2C_MasterTransferDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, */ status_t I2C_MasterTransferGetCountDMA(I2C_Type *base, i2c_master_dma_handle_t *handle, size_t *count) { - assert(handle); + assert(handle != NULL); - if (!count) + if (NULL == count) { return kStatus_InvalidArgument; } /* Catch when there is not an active transfer. */ - if (handle->state == kIdleState) + if (handle->state == (uint8_t)kIdleState) { *count = 0; return kStatus_NoTransferInProgress; @@ -544,7 +608,7 @@ void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) uint32_t status; uint32_t master_state; - if (handle->state != kIdleState) + if (handle->state != (uint8_t)kIdleState) { DMA_AbortTransfer(handle->dmaHandle); @@ -552,22 +616,22 @@ void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) base->MSTCTL = 0; /* Disable internal IRQ enables. */ - I2C_DisableInterrupts(base, - I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | I2C_INTSTAT_MSTSTSTPERR_MASK); + I2C_DisableInterrupts(base, I2C_INTSTAT_MSTPENDING_MASK | I2C_INTSTAT_MSTARBLOSS_MASK | + I2C_INTSTAT_MSTSTSTPERR_MASK | I2C_INTSTAT_EVENTTIMEOUT_MASK); /* Wait until module is ready */ do { status = I2C_GetStatusFlags(base); - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); + } while ((status & (uint8_t)I2C_STAT_MSTPENDING_MASK) == 0U); /* Clear controller state. */ I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); /* Get the state of the I2C module */ - master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; + master_state = (base->STAT & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT; - if (master_state != I2C_STAT_MSTCODE_IDLE) + if (master_state != (uint32_t)I2C_STAT_MSTCODE_IDLE) { /* Send a stop command to finalize the transfer. */ base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK; @@ -576,13 +640,13 @@ void I2C_MasterTransferAbortDMA(I2C_Type *base, i2c_master_dma_handle_t *handle) do { status = I2C_GetStatusFlags(base); - } while ((status & I2C_STAT_MSTPENDING_MASK) == 0); + } while ((status & (uint32_t)I2C_STAT_MSTPENDING_MASK) == 0U); /* Clear controller state. */ I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK); } /* Reset the state to idle. */ - handle->state = kIdleState; + handle->state = (uint8_t)kIdleState; } } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h index 1e0d5eb713..07899f9c7c 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_dma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief I2C DMA driver version 2.0.3. */ -#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*! @brief I2C DMA driver version. */ +#define FSL_I2C_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /*@}*/ /*! @brief Maximum lenght of single DMA transfer (determined by capability of the DMA engine) */ @@ -38,6 +38,9 @@ typedef void (*i2c_master_dma_transfer_callback_t)(I2C_Type *base, status_t status, void *userData); +/*! @brief Typedef for master dma handler. */ +typedef void (*flexcomm_i2c_dma_master_irq_handler_t)(I2C_Type *base, i2c_master_dma_handle_t *handle); + /*! @brief I2C master dma transfer structure. */ struct _i2c_master_dma_handle { @@ -47,8 +50,9 @@ struct _i2c_master_dma_handle uint8_t *buf; /*!< Buffer pointer for current state. */ uint32_t remainingSubaddr; uint8_t subaddrBuf[4]; - dma_handle_t *dmaHandle; /*!< The DMA handler used. */ - i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ + bool checkAddrNack; /*!< Whether to check the nack signal is detected during addressing. */ + dma_handle_t *dmaHandle; /*!< The DMA handler used. */ + i2c_master_transfer_t transfer; /*!< Copy of the current transfer info. */ i2c_master_dma_transfer_callback_t completionCallback; /*!< Callback function called after dma transfer finished. */ void *userData; /*!< Callback parameter passed to callback function. */ }; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.c new file mode 100644 index 0000000000..9b700df46a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.c @@ -0,0 +1,125 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_i2c_freertos.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_i2c_freertos" +#endif + +static void I2C_RTOS_Callback(I2C_Type *base, i2c_master_handle_t *drv_handle, status_t status, void *userData) +{ + i2c_rtos_handle_t *handle = (i2c_rtos_handle_t *)userData; + BaseType_t reschedule; + handle->async_status = status; + (void)xSemaphoreGiveFromISR(handle->semaphore, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/*! + * brief Initializes I2C. + * + * This function initializes the I2C module and the related RTOS context. + * + * param handle The RTOS I2C handle, the pointer to an allocated space for RTOS context. + * param base The pointer base address of the I2C instance to initialize. + * param masterConfig Configuration structure to set-up I2C in master mode. + * param srcClock_Hz Frequency of input clock of the I2C module. + * return status of the operation. + */ +status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle, + I2C_Type *base, + const i2c_master_config_t *masterConfig, + uint32_t srcClock_Hz) +{ + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + if (base == NULL) + { + return kStatus_InvalidArgument; + } + + (void)memset(handle, 0, sizeof(i2c_rtos_handle_t)); + + handle->mutex = xSemaphoreCreateMutex(); + if (handle->mutex == NULL) + { + return kStatus_Fail; + } + + handle->semaphore = xSemaphoreCreateBinary(); + if (handle->semaphore == NULL) + { + vSemaphoreDelete(handle->mutex); + return kStatus_Fail; + } + + handle->base = base; + + I2C_MasterInit(handle->base, masterConfig, srcClock_Hz); + I2C_MasterTransferCreateHandle(base, &handle->drv_handle, I2C_RTOS_Callback, (void *)handle); + + return kStatus_Success; +} + +/*! + * brief Deinitializes the I2C. + * + * This function deinitializes the I2C module and the related RTOS context. + * + * param handle The RTOS I2C handle. + */ +status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle) +{ + I2C_MasterDeinit(handle->base); + + vSemaphoreDelete(handle->semaphore); + vSemaphoreDelete(handle->mutex); + + return kStatus_Success; +} + +/*! + * brief Performs I2C transfer. + * + * This function performs an I2C transfer according to data given in the transfer structure. + * + * param handle The RTOS I2C handle. + * param transfer Structure specifying the transfer parameters. + * return status of the operation. + */ +status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer) +{ + status_t status; + + /* Lock resource mutex */ + if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) + { + return kStatus_I2C_Busy; + } + + status = I2C_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->mutex); + return status; + } + + /* Wait for transfer to finish */ + (void)xSemaphoreTake(handle->semaphore, portMAX_DELAY); + + /* Unlock resource mutex */ + (void)xSemaphoreGive(handle->mutex); + + /* Return status captured by callback function */ + return handle->async_status; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.h new file mode 100644 index 0000000000..1e929496d5 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2c_freertos.h @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __FSL_I2C_FREERTOS_H__ +#define __FSL_I2C_FREERTOS_H__ + +#include "FreeRTOS.h" +#include "portable.h" +#include "semphr.h" + +#include "fsl_i2c.h" + +/*! + * @addtogroup i2c_freertos_driver I2C FreeRTOS Driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief I2C FreeRTOS driver version 2.0.8. */ +#define FSL_I2C_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 0, 8)) +/*@}*/ + +/*! @brief I2C FreeRTOS handle */ +typedef struct _i2c_rtos_handle +{ + I2C_Type *base; /*!< I2C base address */ + i2c_master_handle_t drv_handle; /*!< A handle of the underlying driver, treated as opaque by the RTOS layer */ + status_t async_status; /*!< Transactional state of the underlying driver */ + SemaphoreHandle_t mutex; /*!< A mutex to lock the handle during a transfer */ + SemaphoreHandle_t semaphore; /*!< A semaphore to notify and unblock task when the transfer ends */ +#if (configSUPPORT_STATIC_ALLOCATION == 1) + StaticSemaphore_t mutexBuffer; /*!< Statically allocated memory for mutex */ + StaticSemaphore_t semaphoreBuffer; /*!< Statically allocated memory for semaphore */ +#endif +} i2c_rtos_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name I2C RTOS Operation + * @{ + */ + +/*! + * @brief Initializes I2C. + * + * This function initializes the I2C module and the related RTOS context. + * + * @param handle The RTOS I2C handle, the pointer to an allocated space for RTOS context. + * @param base The pointer base address of the I2C instance to initialize. + * @param masterConfig Configuration structure to set-up I2C in master mode. + * @param srcClock_Hz Frequency of input clock of the I2C module. + * @return status of the operation. + */ +status_t I2C_RTOS_Init(i2c_rtos_handle_t *handle, + I2C_Type *base, + const i2c_master_config_t *masterConfig, + uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the I2C. + * + * This function deinitializes the I2C module and the related RTOS context. + * + * @param handle The RTOS I2C handle. + */ +status_t I2C_RTOS_Deinit(i2c_rtos_handle_t *handle); + +/*! + * @brief Performs I2C transfer. + * + * This function performs an I2C transfer according to data given in the transfer structure. + * + * @param handle The RTOS I2C handle. + * @param transfer Structure specifying the transfer parameters. + * @return status of the operation. + */ +status_t I2C_RTOS_Transfer(i2c_rtos_handle_t *handle, i2c_master_transfer_t *transfer); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* __FSL_I2C_FREERTOS_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.c index d3c6206b4c..c13f2f4bcd 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -20,15 +20,18 @@ #endif /* TODO - absent in device header files, should be there */ -#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) +#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U) #define I2S_FIFOCFG_TXI2SE0_SHIFT (2U) -#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) -#define I2S_FIFOCFG_PACK48_MASK (0x8U) -#define I2S_FIFOCFG_PACK48_SHIFT (3U) -#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) - -/*! @brief I2S states. */ -enum _i2s_state +#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK) +#define I2S_FIFOCFG_PACK48_MASK (0x8U) +#define I2S_FIFOCFG_PACK48_SHIFT (3U) +#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK) +/*! @brief i2s empty tx fifo timeout value */ +#define I2S_FIFO_DEPTH (8U) +#define I2S_TX_ONE_SAMPLE_MAX_TIMEOUT (125U) /* 8K/8bit one sample need 125us*/ +#define I2S_TX_FIFO_EMPTY_TIMEOUT(count) (count) * I2S_TX_ONE_SAMPLE_MAX_TIMEOUT +/*! @brief _i2s_state I2S states. */ +enum { kI2S_StateIdle = 0x0, /*!< Not performing transfer */ kI2S_StateTx, /*!< Performing transmit */ @@ -51,7 +54,7 @@ static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfe ******************************************************************************/ /*! @brief Array to map i2c instance number to base address. */ -static const uint32_t s_i2sBaseAddrs[FSL_FEATURE_SOC_I2S_COUNT] = I2S_BASE_ADDRS; +static const uint32_t s_i2sBaseAddrs[] = I2S_BASE_ADDRS; /*! @brief IRQ name array */ static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; @@ -68,10 +71,10 @@ static const IRQn_Type s_i2sIRQ[] = I2S_IRQS; * @param base The I2S peripheral base address. * @return I2S instance number starting from 0. */ -uint32_t I2S_GetInstance(I2S_Type *base) +static uint32_t I2S_GetInstance(I2S_Type *base) { - int i; - for (i = 0; i < FSL_FEATURE_SOC_I2S_COUNT; i++) + uint32_t i; + for (i = 0; i < (uint32_t)ARRAY_SIZE(s_i2sBaseAddrs); i++) { if ((uint32_t)base == s_i2sBaseAddrs[i]) { @@ -82,12 +85,44 @@ uint32_t I2S_GetInstance(I2S_Type *base) return 0; } +/*! + * brief Transmitter bit clock rate configurations. + * + * param base SAI base pointer. + * param sourceClockHz, bit clock source frequency. + * param sampleRate audio data sample rate. + * param bitWidth, audio data bitWidth. + * param channelNumbers, audio channel numbers. + */ +void I2S_SetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers) +{ + uint32_t bitClockDivider = sourceClockHz / sampleRate / bitWidth / channelNumbers; + + assert(bitClockDivider >= 1U); + base->DIV = I2S_DIV_DIV(bitClockDivider - 1U); +} + +/*! + * brief Initializes the FLEXCOMM peripheral for I2S transmit functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S transmission using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_TxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the I2S driver. + * + * param base I2S base pointer. + * param config pointer to I2S configuration structure. + */ void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) { uint32_t cfg = 0U; uint32_t trig = 0U; - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_TX); I2S_Config(base, config); /* Configure FIFO */ @@ -103,12 +138,26 @@ void I2S_TxInit(I2S_Type *base, const i2s_config_t *config) base->FIFOTRIG = trig; } +/*! + * brief Initializes the FLEXCOMM peripheral for I2S receive functionality. + * + * Ungates the FLEXCOMM clock and configures the module + * for I2S receive using a configuration structure. + * The configuration structure can be custom filled or set with default values by + * I2S_RxGetDefaultConfig(). + * + * note This API should be called at the beginning of the application to use + * the I2S driver. + * + * param base I2S base pointer. + * param config pointer to I2S configuration structure. + */ void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) { uint32_t cfg = 0U; uint32_t trig = 0U; - FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); + (void)FLEXCOMM_Init(base, FLEXCOMM_PERIPH_I2S_RX); I2S_Config(base, config); /* Configure FIFO */ @@ -123,6 +172,68 @@ void I2S_RxInit(I2S_Type *base, const i2s_config_t *config) base->FIFOTRIG = trig; } +/*! + * brief Flush the valid data in TX fifo. + * + * param base I2S base pointer. + * return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. + */ +status_t I2S_EmptyTxFifo(I2S_Type *base) +{ + uint32_t timeout = I2S_TX_FIFO_EMPTY_TIMEOUT(I2S_FIFO_DEPTH); + + while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) + { + timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; + SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + + /* The last piece of valid data can be still being transmitted from I2S at this moment */ + timeout = I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; + /* Write additional data to FIFO */ + base->FIFOWR = 0U; + while (((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) && (timeout != 0U)) + { + timeout -= I2S_TX_ONE_SAMPLE_MAX_TIMEOUT; + SDK_DelayAtLeastUs(I2S_TX_ONE_SAMPLE_MAX_TIMEOUT, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + } + + return ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) ? kStatus_Fail : kStatus_Success; +} + +/*! + * brief Sets the I2S Tx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_TxInit(). + * The initialized structure can remain unchanged in I2S_TxInit(), or it can be modified + * before calling I2S_TxInit(). + * Example: + code + i2s_config_t config; + I2S_TxGetDefaultConfig(&config); + endcode + * + * Default values: + * code + * config->masterSlave = kI2S_MasterSlaveNormalMaster; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = true; + * config->pack48 = false; + * endcode + * + * param config pointer to I2S configuration structure. + */ void I2S_TxGetDefaultConfig(i2s_config_t *config) { config->masterSlave = kI2S_MasterSlaveNormalMaster; @@ -144,6 +255,39 @@ void I2S_TxGetDefaultConfig(i2s_config_t *config) config->pack48 = false; } +/*! + * brief Sets the I2S Rx configuration structure to default values. + * + * This API initializes the configuration structure for use in I2S_RxInit(). + * The initialized structure can remain unchanged in I2S_RxInit(), or it can be modified + * before calling I2S_RxInit(). + * Example: + code + i2s_config_t config; + I2S_RxGetDefaultConfig(&config); + endcode + * + * Default values: + * code + * config->masterSlave = kI2S_MasterSlaveNormalSlave; + * config->mode = kI2S_ModeI2sClassic; + * config->rightLow = false; + * config->leftJust = false; + * config->pdmData = false; + * config->sckPol = false; + * config->wsPol = false; + * config->divider = 1; + * config->oneChannel = false; + * config->dataLength = 16; + * config->frameLength = 32; + * config->position = 0; + * config->watermark = 4; + * config->txEmptyZero = false; + * config->pack48 = false; + * endcode + * + * param config pointer to I2S configuration structure. + */ void I2S_RxGetDefaultConfig(i2s_config_t *config) { config->masterSlave = kI2S_MasterSlaveNormalSlave; @@ -167,7 +311,7 @@ void I2S_RxGetDefaultConfig(i2s_config_t *config) static void I2S_Config(I2S_Type *base, const i2s_config_t *config) { - assert(config); + assert(config != NULL); uint32_t cfg1 = 0U; uint32_t cfg2 = 0U; @@ -185,7 +329,7 @@ static void I2S_Config(I2S_Type *base, const i2s_config_t *config) cfg1 |= I2S_CFG1_LEFTJUST(config->leftJust); #if (defined(FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) && FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION) - if (FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn((FLEXCOMM_Type *)base) > 0) + if (FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn((FLEXCOMM_Type *)(uint32_t)base) > 0) { /* set source to PDM dmic */ cfg1 |= I2S_CFG1_PDMDATA(config->pdmData); @@ -202,10 +346,10 @@ static void I2S_Config(I2S_Type *base, const i2s_config_t *config) cfg1 |= I2S_CFG1_ONECHANNEL(config->oneChannel); /* set data length */ - cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1U); + cfg1 |= I2S_CFG1_DATALEN(config->dataLength - 1UL); /* set frame length */ - cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1U); + cfg2 |= I2S_CFG2_FRAMELEN(config->frameLength - 1UL); /* set data position of this channel pair within the frame */ cfg2 |= I2S_CFG2_POSITION(config->position); @@ -215,9 +359,17 @@ static void I2S_Config(I2S_Type *base, const i2s_config_t *config) base->CFG2 = cfg2; /* set the clock divider */ - base->DIV = I2S_DIV_DIV(config->divider - 1U); + base->DIV = I2S_DIV_DIV(config->divider - 1UL); } +/*! + * brief De-initializes the I2S peripheral. + * + * This API gates the FLEXCOMM clock. The I2S module can't operate unless I2S_TxInit + * or I2S_RxInit is called to enable the clock. + * + * param base I2S base pointer. + */ void I2S_Deinit(I2S_Type *base) { /* TODO gate FLEXCOMM clock via FLEXCOMM driver */ @@ -227,12 +379,12 @@ static void I2S_TxEnable(I2S_Type *base, bool enable) { if (enable) { - I2S_EnableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); I2S_Enable(base); + I2S_EnableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); } else { - I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); + I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); I2S_Disable(base); base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; } @@ -242,12 +394,12 @@ static void I2S_RxEnable(I2S_Type *base, bool enable) { if (enable) { - I2S_EnableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); I2S_Enable(base); + I2S_EnableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); } else { - I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); + I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); I2S_Disable(base); base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; } @@ -255,8 +407,9 @@ static void I2S_RxEnable(I2S_Type *base, bool enable) static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfer) { - assert(transfer->data); - if (!transfer->data) + assert(transfer->data != NULL); + + if (transfer->data == NULL) { return kStatus_InvalidArgument; } @@ -352,9 +505,20 @@ static status_t I2S_ValidateBuffer(i2s_handle_t *handle, i2s_transfer_t *transfe } #if (defined(FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) && FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL) +/*! + * brief Enables I2S secondary channel. + * + * param base I2S base pointer. + * param channel seondary channel channel number, reference _i2s_secondary_channel. + * param oneChannel true is treated as single channel, functionality left channel for this pair. + * param position define the location within the frame of the data, should not bigger than 0x1FFU. + */ void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChannel, uint32_t position) { - assert(channel <= kI2S_SecondaryChannel3); + assert(channel <= (uint32_t)kI2S_SecondaryChannel3); +#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn + assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); +#endif uint32_t pcfg1 = base->SECCHANNEL[channel].PCFG1; uint32_t pcfg2 = base->SECCHANNEL[channel].PCFG2; @@ -369,14 +533,23 @@ void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChanne base->SECCHANNEL[channel].PCFG2 = pcfg2; } #endif + +/*! + * brief Initializes handle for transfer of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) { + assert(handle != NULL); + uint32_t instance; - assert(handle); - /* Clear out the handle */ - memset(handle, 0U, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); /* Look up instance number */ instance = I2S_GetInstance(base); @@ -386,43 +559,53 @@ void I2S_TxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transf handle->userData = userData; /* Remember some items set previously by configuration */ - handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); - handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); + handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_TXLVL_MASK) >> I2S_FIFOTRIG_TXLVL_SHIFT); + handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0U ? true : false; + handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; + handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0u ? true : false; handle->useFifo48H = false; /* Register IRQ handling */ FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_TxHandleIRQ, handle); /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); - EnableIRQ(s_i2sIRQ[instance]); + I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); + (void)EnableIRQ(s_i2sIRQ[instance]); } +/*! + * brief Begins or queue sending of the given data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with unsent buffers. + */ status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) { - assert(handle); - if (!handle) + assert(handle != NULL); + + status_t result; + + if (handle == NULL) { return kStatus_InvalidArgument; } - status_t result; - result = I2S_ValidateBuffer(handle, &transfer); if (result != kStatus_Success) { return result; } - if (handle->i2sQueue[handle->queueUser].dataSize) + if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) { /* Previously prepared buffers not processed yet */ return kStatus_I2S_Busy; } - handle->state = kI2S_StateTx; handle->i2sQueue[handle->queueUser].data = transfer.data; handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; @@ -433,30 +616,44 @@ status_t I2S_TxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_tra return kStatus_Success; } +/*! + * brief Aborts sending of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ void I2S_TxTransferAbort(I2S_Type *base, i2s_handle_t *handle) { - assert(handle); + assert(handle != NULL); /* Disable I2S operation and interrupts */ I2S_TxEnable(base, false); /* Reset state */ - handle->state = kI2S_StateIdle; + handle->state = (uint32_t)kI2S_StateIdle; /* Clear transfer queue */ - memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); + (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); handle->queueDriver = 0U; handle->queueUser = 0U; } +/*! + * brief Initializes handle for reception of audio data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param callback function to be called back when transfer is done or fails. + * param userData pointer to data passed to callback. + */ void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_callback_t callback, void *userData) { + assert(handle != NULL); + uint32_t instance; - assert(handle); - /* Clear out the handle */ - memset(handle, 0U, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); /* Look up instance number */ instance = I2S_GetInstance(base); @@ -466,43 +663,54 @@ void I2S_RxTransferCreateHandle(I2S_Type *base, i2s_handle_t *handle, i2s_transf handle->userData = userData; /* Remember some items set previously by configuration */ - handle->watermark = ((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); - handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT); - handle->dataLength = ((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; - handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT); + handle->watermark = (uint8_t)((base->FIFOTRIG & I2S_FIFOTRIG_RXLVL_MASK) >> I2S_FIFOTRIG_RXLVL_SHIFT); + handle->oneChannel = ((base->CFG1 & I2S_CFG1_ONECHANNEL_MASK) >> I2S_CFG1_ONECHANNEL_SHIFT) != 0UL ? true : false; + handle->dataLength = (uint8_t)((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U; + handle->pack48 = ((base->FIFOCFG & I2S_FIFOCFG_PACK48_MASK) >> I2S_FIFOCFG_PACK48_SHIFT) != 0UL ? true : false; handle->useFifo48H = false; /* Register IRQ handling */ FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)I2S_RxHandleIRQ, handle); /* Clear internal IRQ enables and enable NVIC IRQ. */ - I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); - EnableIRQ(s_i2sIRQ[instance]); + I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); + + (void)EnableIRQ(s_i2sIRQ[instance]); } +/*! + * brief Begins or queue reception of data into given buffer. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param transfer data buffer. + * + * retval kStatus_Success + * retval kStatus_I2S_Busy if all queue slots are occupied with buffers which are not full. + */ status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_transfer_t transfer) { - assert(handle); - if (!handle) + assert(handle != NULL); + + status_t result; + + if (NULL == handle) { return kStatus_InvalidArgument; } - status_t result; - result = I2S_ValidateBuffer(handle, &transfer); if (result != kStatus_Success) { return result; } - if (handle->i2sQueue[handle->queueUser].dataSize) + if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) { /* Previously prepared buffers not processed yet */ return kStatus_I2S_Busy; } - handle->state = kI2S_StateRx; handle->i2sQueue[handle->queueUser].data = transfer.data; handle->i2sQueue[handle->queueUser].dataSize = transfer.dataSize; handle->queueUser = (handle->queueUser + 1U) % I2S_NUM_BUFFERS; @@ -513,37 +721,54 @@ status_t I2S_RxTransferNonBlocking(I2S_Type *base, i2s_handle_t *handle, i2s_tra return kStatus_Success; } +/*! + * brief Aborts receiving of data. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ void I2S_RxTransferAbort(I2S_Type *base, i2s_handle_t *handle) { - assert(handle); + assert(handle != NULL); /* Disable I2S operation and interrupts */ I2S_RxEnable(base, false); /* Reset state */ - handle->state = kI2S_StateIdle; + handle->state = (uint32_t)kI2S_StateIdle; /* Clear transfer queue */ - memset((void *)&handle->i2sQueue, 0U, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); + (void)memset((void *)&handle->i2sQueue, 0, sizeof(i2s_transfer_t) * I2S_NUM_BUFFERS); handle->queueDriver = 0U; handle->queueUser = 0U; } +/*! + * brief Returns number of bytes transferred so far. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param[out] count number of bytes transferred so far by the non-blocking transaction. + * + * retval kStatus_Success + * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) { - assert(handle); - if (!handle) + assert(handle != NULL); + assert(count != NULL); + + if (NULL == handle) { return kStatus_InvalidArgument; } - assert(count); - if (!count) + if (NULL == count) { return kStatus_InvalidArgument; } - if (handle->state == kI2S_StateIdle) + if (handle->state == (uint32_t)kI2S_StateIdle) { return kStatus_NoTransferInProgress; } @@ -553,21 +778,32 @@ status_t I2S_TransferGetCount(I2S_Type *base, i2s_handle_t *handle, size_t *coun return kStatus_Success; } +/*! + * brief Returns number of buffer underruns or overruns. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + * param[out] count number of transmit errors encountered so far by the non-blocking transaction. + * + * retval kStatus_Success + * retval kStatus_NoTransferInProgress there is no non-blocking transaction currently in progress. + */ status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t *count) { - assert(handle); - if (!handle) + assert(handle != NULL); + assert(count != NULL); + + if (NULL == handle) { return kStatus_InvalidArgument; } - assert(count); - if (!count) + if (NULL == count) { return kStatus_InvalidArgument; } - if (handle->state == kI2S_StateIdle) + if (handle->state == (uint32_t)kI2S_StateIdle) { return kStatus_NoTransferInProgress; } @@ -577,12 +813,21 @@ status_t I2S_TransferGetErrorCount(I2S_Type *base, i2s_handle_t *handle, size_t return kStatus_Success; } +/*! + * brief Invoked from interrupt handler when transmit FIFO level decreases. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) { uint32_t intstat = base->FIFOINTSTAT; uint32_t data; + uint8_t queueDriverIndex = handle->queueDriver; + uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; + uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - if (intstat & I2S_FIFOINTSTAT_TXERR_MASK) + if ((intstat & I2S_FIFOINTSTAT_TXERR_MASK) != 0UL) { handle->errorCount++; @@ -590,38 +835,63 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) base->FIFOSTAT = I2S_FIFOSTAT_TXERR(1U); } - if (intstat & I2S_FIFOINTSTAT_TXLVL_MASK) + if ((intstat & I2S_FIFOINTSTAT_TXLVL_MASK) != 0UL) { - if (handle->state == kI2S_StateTx) + if ((handle->state != (uint32_t)kI2S_StateTx) && (dataSize != 0U) && (dataAddr != 0U)) + { + handle->state = (uint32_t)kI2S_StateTx; + } + + if (handle->state == (uint32_t)kI2S_StateTx) { /* Send data */ - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) && - (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) + while (((base->FIFOSTAT & I2S_FIFOSTAT_TXNOTFULL_MASK) != 0UL) && (dataSize > 0U)) { /* Write output data */ if (handle->dataLength == 4U) { - data = *(handle->i2sQueue[handle->queueDriver].data); + data = *((uint8_t *)dataAddr); base->FIFOWR = ((data & 0xF0U) << 12U) | (data & 0xFU); - handle->i2sQueue[handle->queueDriver].data++; + dataAddr++; handle->transferCount++; - handle->i2sQueue[handle->queueDriver].dataSize--; + dataSize--; } else if (handle->dataLength <= 8U) { - data = *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data); - base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + data = *((volatile uint16_t *)dataAddr); + if (handle->oneChannel) + { + base->FIFOWR = (data & 0xFFU); + dataAddr += sizeof(uint8_t); + handle->transferCount += sizeof(uint8_t); + dataSize -= sizeof(uint8_t); + } + else + { + base->FIFOWR = ((data & 0xFF00U) << 8U) | (data & 0xFFU); + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } } else if (handle->dataLength <= 16U) { - base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + data = *((volatile uint32_t *)(dataAddr)); + if (handle->oneChannel) + { + base->FIFOWR = data & 0xFFFFU; + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + else + { + base->FIFOWR = data; + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } } else if (handle->dataLength <= 24U) { @@ -629,27 +899,27 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) { if (handle->useFifo48H) { - base->FIFOWR48H = *((volatile uint16_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); + base->FIFOWR48H = *((volatile uint16_t *)(dataAddr)); + dataAddr += sizeof(uint16_t); handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + dataSize -= sizeof(uint16_t); handle->useFifo48H = false; } else { - base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + base->FIFOWR = *((volatile uint32_t *)(dataAddr)); + dataAddr += sizeof(uint32_t); handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + dataSize -= sizeof(uint32_t); handle->useFifo48H = true; } } else { - data = (uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++)); - data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 8U; - data |= ((uint32_t)(*(handle->i2sQueue[handle->queueDriver].data++))) << 16U; - if (handle->useFifo48H) + data = (uint32_t)(*(uint8_t *)(dataAddr++)); + data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 8U; + data |= ((uint32_t)(*(uint8_t *)(dataAddr++))) << 16U; + if ((handle->useFifo48H) && (handle->oneChannel == false)) { base->FIFOWR48H = data; handle->useFifo48H = false; @@ -660,24 +930,25 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) handle->useFifo48H = true; } handle->transferCount += 3U; - handle->i2sQueue[handle->queueDriver].dataSize -= 3U; + dataSize -= 3U; } } else /* if (handle->dataLength <= 32U) */ { - base->FIFOWR = *((volatile uint32_t *)(handle->i2sQueue[handle->queueDriver].data)); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + base->FIFOWR = *((volatile uint32_t *)(dataAddr)); + dataAddr += sizeof(uint32_t); handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + dataSize -= sizeof(uint32_t); } - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + if (dataSize == 0U) { + handle->i2sQueue[queueDriverIndex].dataSize = 0U; /* Actual data buffer sent out, switch to a next one */ - handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; + handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; /* Notify user */ - if (handle->completionCallback) + if (handle->completionCallback != NULL) { handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); } @@ -690,9 +961,14 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) break; } } + else + { + handle->i2sQueue[queueDriverIndex].dataSize = dataSize; + handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; + } } } - else if (handle->state == kI2S_StateTxWaitToWriteDummyData) + else if (handle->state == (uint32_t)kI2S_StateTxWaitToWriteDummyData) { /* Write dummy data */ if ((handle->dataLength > 16U) && (handle->dataLength < 25U)) @@ -715,23 +991,23 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) /* Next time invoke this handler when FIFO becomes empty (TX level 0) */ base->FIFOTRIG &= ~I2S_FIFOTRIG_TXLVL_MASK; - handle->state = kI2S_StateTxWaitForEmptyFifo; + handle->state = (uint32_t)kI2S_StateTxWaitForEmptyFifo; } - else if (handle->state == kI2S_StateTxWaitForEmptyFifo) + else if (handle->state == (uint32_t)kI2S_StateTxWaitForEmptyFifo) { /* FIFO, including additional dummy data, has been emptied now, * all relevant data should have been output from peripheral */ /* Stop transfer */ I2S_Disable(base); - I2S_DisableInterrupts(base, kI2S_TxErrorFlag | kI2S_TxLevelFlag); + I2S_DisableInterrupts(base, (uint32_t)kI2S_TxErrorFlag | (uint32_t)kI2S_TxLevelFlag); base->FIFOCFG |= I2S_FIFOCFG_EMPTYTX_MASK; /* Reset state */ - handle->state = kI2S_StateIdle; + handle->state = (uint32_t)kI2S_StateIdle; /* Notify user */ - if (handle->completionCallback) + if (handle->completionCallback != NULL) { handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); } @@ -746,12 +1022,21 @@ void I2S_TxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) } } +/*! + * brief Invoked from interrupt handler when receive FIFO level decreases. + * + * param base I2S base pointer. + * param handle pointer to handle structure. + */ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) { uint32_t intstat = base->FIFOINTSTAT; uint32_t data; + uint8_t queueDriverIndex = handle->queueDriver; + uint32_t dataAddr = (uint32_t)handle->i2sQueue[queueDriverIndex].data; + uint32_t dataSize = handle->i2sQueue[queueDriverIndex].dataSize; - if (intstat & I2S_FIFOINTSTAT_RXERR_MASK) + if ((intstat & I2S_FIFOINTSTAT_RXERR_MASK) != 0UL) { handle->errorCount++; @@ -759,35 +1044,56 @@ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) base->FIFOSTAT = I2S_FIFOSTAT_RXERR(1U); } - if (intstat & I2S_FIFOINTSTAT_RXLVL_MASK) + if ((intstat & I2S_FIFOINTSTAT_RXLVL_MASK) != 0UL) { - while ((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) && (handle->i2sQueue[handle->queueDriver].dataSize > 0U)) + while (((base->FIFOSTAT & I2S_FIFOSTAT_RXNOTEMPTY_MASK) != 0UL) && (dataSize > 0U)) { /* Read input data */ if (handle->dataLength == 4U) { - data = base->FIFORD; - *(handle->i2sQueue[handle->queueDriver].data) = ((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU); - handle->i2sQueue[handle->queueDriver].data++; + data = base->FIFORD; + *((uint8_t *)dataAddr) = (uint8_t)(((data & 0x000F0000U) >> 12U) | (data & 0x0000000FU)); + dataAddr++; handle->transferCount++; - handle->i2sQueue[handle->queueDriver].dataSize--; + dataSize--; } else if (handle->dataLength <= 8U) { data = base->FIFORD; - *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = - ((data >> 8U) & 0xFF00U) | (data & 0xFFU); - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); - handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + + if (handle->oneChannel) + { + *((volatile uint8_t *)dataAddr) = (uint8_t)(data & 0xFFU); + dataAddr += sizeof(uint8_t); + handle->transferCount += sizeof(uint8_t); + dataSize -= sizeof(uint8_t); + } + else + { + *((volatile uint16_t *)dataAddr) = (uint16_t)(((data >> 8U) & 0xFF00U) | (data & 0xFFU)); + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } } else if (handle->dataLength <= 16U) { - data = base->FIFORD; - *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); - handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + data = base->FIFORD; + + if (handle->oneChannel) + { + *((volatile uint16_t *)dataAddr) = (uint16_t)(data & 0xFFFFU); + dataAddr += sizeof(uint16_t); + handle->transferCount += sizeof(uint16_t); + dataSize -= sizeof(uint16_t); + } + else + { + *((volatile uint32_t *)dataAddr) = data; + dataAddr += sizeof(uint32_t); + handle->transferCount += sizeof(uint32_t); + dataSize -= sizeof(uint32_t); + } } else if (handle->dataLength <= 24U) { @@ -798,20 +1104,20 @@ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) data = base->FIFORD48H; handle->useFifo48H = false; - *((volatile uint16_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint16_t); + *((volatile uint16_t *)dataAddr) = (uint16_t)data; + dataAddr += sizeof(uint16_t); handle->transferCount += sizeof(uint16_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint16_t); + dataSize -= sizeof(uint16_t); } else { data = base->FIFORD; handle->useFifo48H = true; - *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + *((volatile uint32_t *)dataAddr) = data; + dataAddr += sizeof(uint32_t); handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + dataSize -= sizeof(uint32_t); } } else @@ -827,29 +1133,30 @@ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) handle->useFifo48H = true; } - *(handle->i2sQueue[handle->queueDriver].data++) = data & 0xFFU; - *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 8U) & 0xFFU; - *(handle->i2sQueue[handle->queueDriver].data++) = (data >> 16U) & 0xFFU; + *(uint8_t *)(dataAddr++) = (uint8_t)(data & 0xFFU); + *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 8U) & 0xFFU); + *(uint8_t *)(dataAddr++) = (uint8_t)((data >> 16U) & 0xFFU); handle->transferCount += 3U; - handle->i2sQueue[handle->queueDriver].dataSize -= 3U; + dataSize -= 3U; } } else /* if (handle->dataLength <= 32U) */ { - data = base->FIFORD; - *((volatile uint32_t *)handle->i2sQueue[handle->queueDriver].data) = data; - handle->i2sQueue[handle->queueDriver].data += sizeof(uint32_t); + data = base->FIFORD; + *((volatile uint32_t *)dataAddr) = data; + dataAddr += sizeof(uint32_t); handle->transferCount += sizeof(uint32_t); - handle->i2sQueue[handle->queueDriver].dataSize -= sizeof(uint32_t); + dataSize -= sizeof(uint32_t); } - if (handle->i2sQueue[handle->queueDriver].dataSize == 0U) + if (dataSize == 0U) { + handle->i2sQueue[queueDriverIndex].dataSize = 0U; /* Actual data buffer filled with input data, switch to a next one */ - handle->queueDriver = (handle->queueDriver + 1U) % I2S_NUM_BUFFERS; + handle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; /* Notify user */ - if (handle->completionCallback) + if (handle->completionCallback != NULL) { handle->completionCallback(base, handle, kStatus_I2S_BufferComplete, handle->userData); } @@ -860,14 +1167,14 @@ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) /* Disable I2S operation and interrupts */ I2S_Disable(base); - I2S_DisableInterrupts(base, kI2S_RxErrorFlag | kI2S_RxLevelFlag); + I2S_DisableInterrupts(base, (uint32_t)kI2S_RxErrorFlag | (uint32_t)kI2S_RxLevelFlag); base->FIFOCFG |= I2S_FIFOCFG_EMPTYRX_MASK; /* Reset state */ - handle->state = kI2S_StateIdle; + handle->state = (uint32_t)kI2S_StateIdle; /* Notify user */ - if (handle->completionCallback) + if (handle->completionCallback != NULL) { handle->completionCallback(base, handle, kStatus_I2S_Done, handle->userData); } @@ -878,6 +1185,11 @@ void I2S_RxHandleIRQ(I2S_Type *base, i2s_handle_t *handle) return; } } + else + { + handle->i2sQueue[queueDriverIndex].dataSize = dataSize; + handle->i2sQueue[queueDriverIndex].data = (uint8_t *)dataAddr; + } } /* Clear RX level interrupt flag */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.h index 4af608c282..e0787d6b14 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -26,19 +26,19 @@ /*! @name Driver version */ /*@{*/ -/*! @brief I2S driver version 2.1.0. */ -#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @brief I2S driver version 2.3.1. */ +#define FSL_I2S_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*@}*/ #ifndef I2S_NUM_BUFFERS /*! @brief Number of buffers . */ -#define I2S_NUM_BUFFERS (4) +#define I2S_NUM_BUFFERS (4U) #endif -/*! @brief I2S status codes. */ -enum _i2s_status +/*! @brief _i2s_status I2S status codes. */ +enum { kStatus_I2S_BufferComplete = MAKE_STATUS(kStatusGroup_I2S, 0), /*!< Transfer from/into a single buffer has completed */ @@ -78,8 +78,8 @@ typedef enum _i2s_mode kI2S_ModeDspWsLong = 0x3 /*!< DSP mode, WS having one data slot long pulse */ } i2s_mode_t; -/*! @brief I2S secondary channel. */ -enum _i2s_secondary_channel +/*! @brief _i2s_secondary_channel I2S secondary channel. */ +enum { kI2S_SecondaryChannel1 = 0U, /*!< secondary channel 1 */ kI2S_SecondaryChannel2 = 1U, /*!< secondary channel 2 */ @@ -112,8 +112,8 @@ typedef struct _i2s_config /*! @brief Buffer to transfer from or receive audio data into. */ typedef struct _i2s_transfer { - volatile uint8_t *data; /*!< Pointer to data buffer. */ - volatile size_t dataSize; /*!< Buffer size in bytes. */ + uint8_t *data; /*!< Pointer to data buffer. */ + size_t dataSize; /*!< Buffer size in bytes. */ } i2s_transfer_t; /*! @brief Transactional state of the intialized transfer or receive I2S operation. */ @@ -136,20 +136,21 @@ typedef void (*i2s_transfer_callback_t)(I2S_Type *base, /*! @brief Members not to be accessed / modified outside of the driver. */ struct _i2s_handle { - uint32_t state; /*!< State of transfer */ + volatile uint32_t state; /*!< State of transfer */ i2s_transfer_callback_t completionCallback; /*!< Callback function pointer */ void *userData; /*!< Application data passed to callback */ bool oneChannel; /*!< true mono, false stereo */ uint8_t dataLength; /*!< Data length (4 - 32) */ - bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit - values) */ - bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ + bool pack48; /*!< Packing format for 48-bit data (false - 24 bit values, true - alternating 32-bit and 16-bit + values) */ + uint8_t watermark; /*!< FIFO trigger level */ + bool useFifo48H; /*!< When dataLength 17-24: true use FIFOWR48H, false use FIFOWR */ + volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ volatile uint32_t errorCount; /*!< Number of buffer underruns/overruns */ volatile uint32_t transferCount; /*!< Number of bytes transferred */ - volatile uint8_t watermark; /*!< FIFO trigger level */ }; /******************************************************************************* @@ -277,6 +278,18 @@ void I2S_RxGetDefaultConfig(i2s_config_t *config); */ void I2S_Deinit(I2S_Type *base); +/*! + * @brief Transmitter/Receiver bit clock rate configurations. + * + * @param base SAI base pointer. + * @param sourceClockHz bit clock source frequency. + * @param sampleRate audio data sample rate. + * @param bitWidth audio data bitWidth. + * @param channelNumbers audio channel numbers. + */ +void I2S_SetBitClockRate( + I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers); + /*! @} */ /*! @@ -404,6 +417,10 @@ void I2S_EnableSecondaryChannel(I2S_Type *base, uint32_t channel, bool oneChanne */ static inline void I2S_DisableSecondaryChannel(I2S_Type *base, uint32_t channel) { +#if defined FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn + assert(FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_SUPPORT_SECONDARY_CHANNELn((FLEXCOMM_Type *)(uint32_t)base) == 1); +#endif + base->SECCHANNEL[channel].PCFG1 &= ~I2S_CFG1_MAINENABLE_MASK; } #endif @@ -461,6 +478,14 @@ static inline uint32_t I2S_GetEnabledInterrupts(I2S_Type *base) return base->FIFOINTENSET; } +/*! + * @brief Flush the valid data in TX fifo. + * + * @param base I2S base pointer. + * @return kStatus_Fail empty TX fifo failed, kStatus_Success empty tx fifo success. + */ +status_t I2S_EmptyTxFifo(I2S_Type *base); + /*! * @brief Invoked from interrupt handler when transmit FIFO level decreases. * diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c index f3bf1773c8..84f25b30e9 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,7 +21,7 @@ #endif #define DMA_MAX_TRANSFER_BYTES (DMA_MAX_TRANSFER_COUNT * sizeof(uint32_t)) -#define DMA_DESCRIPTORS (2U) +#define DMA_DESCRIPTORS (2U) /*i2sQueue[handle->queueUser].dataSize) + if (handle->i2sQueue[handle->queueUser].dataSize != 0UL) { /* Previously prepared buffers not processed yet, reject request */ return kStatus_I2S_Busy; @@ -164,7 +171,7 @@ static inline void I2S_DisableDMAInterrupts(i2s_dma_handle_t *handle) static inline void I2S_EnableDMAInterrupts(i2s_dma_handle_t *handle) { - if (handle->state != kI2S_DmaStateIdle) + if (handle->state != (uint32_t)kI2S_DmaStateIdle) { DMA_EnableChannelInterrupts(handle->dmaHandle->base, handle->dmaHandle->channel); } @@ -185,19 +192,19 @@ void I2S_TxTransferCreateHandleDMA(I2S_Type *base, i2s_dma_transfer_callback_t callback, void *userData) { - assert(handle); - assert(dmaHandle); + assert(handle != NULL); + assert(dmaHandle != NULL); uint32_t instance = I2S_GetInstance(base); i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); - memset(handle, 0U, sizeof(*handle)); - handle->state = kI2S_DmaStateIdle; + (void)memset(handle, 0, sizeof(*handle)); + handle->state = (uint32_t)kI2S_DmaStateIdle; handle->dmaHandle = dmaHandle; handle->completionCallback = callback; handle->userData = userData; - handle->bytesPerFrame = (((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U; + handle->bytesPerFrame = (uint8_t)((((base->CFG1 & I2S_CFG1_DATALEN_MASK) >> I2S_CFG1_DATALEN_SHIFT) + 1U) / 8U); /* if one channel is disabled, bytesPerFrame should be 4U, user should pay attention that when data length is * shorter than 16, the data format: left data put in 0-15 bit and right data should put in 16-31 */ @@ -211,7 +218,7 @@ void I2S_TxTransferCreateHandleDMA(I2S_Type *base, handle->bytesPerFrame = 4U; } - memset(privateHandle, 0U, sizeof(*privateHandle)); + (void)memset(privateHandle, 0, sizeof(*privateHandle)); privateHandle->base = base; privateHandle->handle = handle; @@ -243,9 +250,9 @@ status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_tra } /* Initialize DMA transfer */ - if (handle->state == kI2S_DmaStateIdle) + if (handle->state == (uint32_t)kI2S_DmaStateIdle) { - handle->state = kI2S_DmaStateTx; + handle->state = (uint32_t)kI2S_DmaStateTx; status = I2S_StartTransferDMA(base, handle); if (status != kStatus_Success) { @@ -268,8 +275,8 @@ status_t I2S_TxTransferSendDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_tra */ void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) { - assert(handle); - assert(handle->dmaHandle); + assert(handle != NULL); + assert(handle->dmaHandle != NULL); uint32_t instance = I2S_GetInstance(base); i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); @@ -279,41 +286,30 @@ void I2S_TransferAbortDMA(I2S_Type *base, i2s_dma_handle_t *handle) /* Abort operation */ DMA_AbortTransfer(handle->dmaHandle); - if (handle->state == kI2S_DmaStateTx) + if (handle->state == (uint32_t)kI2S_DmaStateTx) { - /* Wait until all transmitted data get out of FIFO */ - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) - { - } - /* The last piece of valid data can be still being transmitted from I2S at this moment */ - - /* Write additional data to FIFO */ - base->FIFOWR = 0U; - while ((base->FIFOSTAT & I2S_FIFOSTAT_TXEMPTY_MASK) == 0U) - { - } - /* At this moment the additional data are out of FIFO, starting being transmitted. - * This means the preceding valid data has been just transmitted and we can stop I2S. */ + /* Disable TX */ I2S_TxEnableDMA(base, false); } else { + /* Disable RX */ I2S_RxEnableDMA(base, false); } I2S_Disable(base); /* Reset state */ - handle->state = kI2S_DmaStateIdle; + handle->state = (uint32_t)kI2S_DmaStateIdle; /* Clear transfer queue */ - memset((void *)&(handle->i2sQueue), 0U, sizeof(handle->i2sQueue)); + (void)memset((void *)&(handle->i2sQueue), 0, sizeof(handle->i2sQueue)); handle->queueDriver = 0U; handle->queueUser = 0U; /* Clear internal state */ - memset((void *)&(privateHandle->descriptorQueue), 0U, sizeof(privateHandle->descriptorQueue)); - memset((void *)&(privateHandle->enqueuedBytes), 0U, sizeof(privateHandle->enqueuedBytes)); + (void)memset((void *)&(privateHandle->descriptorQueue), 0, sizeof(privateHandle->descriptorQueue)); + (void)memset((void *)&(privateHandle->enqueuedBytes), 0, sizeof(privateHandle->enqueuedBytes)); privateHandle->enqueuedBytesStart = 0U; privateHandle->enqueuedBytesEnd = 0U; privateHandle->dmaDescriptorsUsed = 0U; @@ -366,9 +362,9 @@ status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_ } /* Initialize DMA transfer */ - if (handle->state == kI2S_DmaStateIdle) + if (handle->state == (uint32_t)kI2S_DmaStateIdle) { - handle->state = kI2S_DmaStateRx; + handle->state = (uint32_t)kI2S_DmaStateRx; status = I2S_StartTransferDMA(base, handle); if (status != kStatus_Success) { @@ -411,17 +407,17 @@ static void I2S_RxEnableDMA(I2S_Type *base, bool enable) static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) { - assert(transfer); + assert(transfer != NULL); uint16_t transferBytes; - if (transfer->dataSize >= (2 * DMA_MAX_TRANSFER_BYTES)) + if (transfer->dataSize >= (2UL * DMA_MAX_TRANSFER_BYTES)) { transferBytes = DMA_MAX_TRANSFER_BYTES; } else if (transfer->dataSize > DMA_MAX_TRANSFER_BYTES) { - transferBytes = transfer->dataSize / 2U; + transferBytes = (uint16_t)(transfer->dataSize / 2U); if ((transferBytes % 4U) != 0U) { transferBytes -= (transferBytes % 4U); @@ -429,40 +425,254 @@ static uint16_t I2S_GetTransferBytes(volatile i2s_transfer_t *transfer) } else { - transferBytes = transfer->dataSize; + transferBytes = (uint16_t)transfer->dataSize; } return transferBytes; } +/*! + * brief Install DMA descriptor memory for loop transfer only. + * + * This function used to register DMA descriptor memory for the i2s loop dma transfer. + * + * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after + * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. + * + * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. + * + * param handle Pointer to i2s DMA transfer handle. + * param dmaDescriptorAddr DMA descriptor start address. + * param dmaDescriptorNum DMA descriptor number. + */ +void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, + void *dmaDescriptorAddr, + size_t dmaDescriptorNum) +{ + assert(handle != NULL); + assert((((uint32_t)(uint32_t *)dmaDescriptorAddr) & ((uint32_t)FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE - 1UL)) == + 0UL); + + handle->i2sLoopDMADescriptor = (dma_descriptor_t *)dmaDescriptorAddr; + handle->i2sLoopDMADescriptorNum = dmaDescriptorNum; +} + +static status_t I2S_TransferLoopDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + i2s_transfer_t *xfer, + uint32_t loopTransferCount) +{ + assert(handle != NULL); + assert(handle->dmaHandle != NULL); + assert(xfer != NULL); + + uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; + i2s_transfer_t *currentTransfer = xfer; + bool intA = true; + + if (handle->i2sLoopDMADescriptor == NULL) + { + return kStatus_InvalidArgument; + } + + if (handle->state == (uint32_t)kI2S_DmaStateBusyLoopTransfer) + { + return kStatus_I2S_Busy; + } + + for (uint32_t i = 0U; i < loopTransferCount; i++) + { + currentTransfer = &xfer[i]; + + if ((currentTransfer->data == NULL) || (currentTransfer->dataSize == 0U) || + (i >= handle->i2sLoopDMADescriptorNum) || + (currentTransfer->dataSize / handle->bytesPerFrame > DMA_MAX_TRANSFER_COUNT)) + { + return kStatus_InvalidArgument; + } + + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + srcAddr = (uint32_t *)(uint32_t)currentTransfer->data; + destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); + srcInc = 1U; + destInc = 0UL; + } + else + { + srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); + destAddr = (uint32_t *)(uint32_t)currentTransfer->data; + srcInc = 0U; + destInc = 1UL; + } + + intA = intA == true ? false : true; + + if (i == (loopTransferCount - 1U)) + { + /* set up linked descriptor */ + DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], + DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, + currentTransfer->dataSize), + srcAddr, destAddr, &handle->i2sLoopDMADescriptor[0U]); + } + else + { + /* set up linked descriptor */ + DMA_SetupDescriptor(&handle->i2sLoopDMADescriptor[i], + DMA_CHANNEL_XFER(1UL, 0UL, intA, !intA, handle->bytesPerFrame, srcInc, destInc, + currentTransfer->dataSize), + srcAddr, destAddr, &handle->i2sLoopDMADescriptor[i + 1U]); + } + } + + /* transferSize make sense to non link transfer only */ + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + srcAddr = (uint32_t *)(uint32_t)xfer->data; + destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); + srcInc = 1U; + destInc = 0UL; + } + else + { + srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); + destAddr = (uint32_t *)(uint32_t)xfer->data; + srcInc = 0U; + destInc = 1UL; + } + + DMA_SubmitChannelTransferParameter( + handle->dmaHandle, + DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)xfer->dataSize), srcAddr, + destAddr, (void *)&handle->i2sLoopDMADescriptor[1U]); + + /* Submit and start initial DMA transfer */ + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + I2S_TxEnableDMA(base, true); + } + else + { + I2S_RxEnableDMA(base, true); + } + DMA_EnableChannelPeriphRq(handle->dmaHandle->base, handle->dmaHandle->channel); + /* start transfer */ + DMA_StartTransfer(handle->dmaHandle); + I2S_Enable(base); + + handle->state = (uint32_t)kI2S_DmaStateBusyLoopTransfer; + + return kStatus_Success; +} + +/*! + * brief Send loop transfer data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * This function support loop transfer, such as A->B->...->A, the loop transfer chain + * will be converted into a chain of descriptor and submit to dma. + * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, + * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. + * + * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support + * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop + * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. + * + * param base I2S peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param xfer I2S DMA transfer structure. See #i2s_transfer_t. + * param i2s_channel I2S start channel number + * retval kStatus_Success + */ +status_t I2S_TransferSendLoopDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + i2s_transfer_t *xfer, + uint32_t loopTransferCount) +{ + assert(handle != NULL); + assert(handle->i2sLoopDMADescriptor != NULL); + + handle->state = (uint32_t)kI2S_DmaStateTx; + + return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); +} + +/*! + * brief Receive loop transfer data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * This function support loop transfer, such as A->B->...->A, the loop transfer chain + * will be converted into a chain of descriptor and submit to dma. + * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, + * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. + * + * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support + * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop + * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. + * + * param base I2S peripheral base address. + * param handle Pointer to usart_dma_handle_t structure. + * param xfer I2S DMA transfer structure. See #i2s_transfer_t. + * param i2s_channel I2S start channel number + * retval kStatus_Success + */ +status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + i2s_transfer_t *xfer, + uint32_t loopTransferCount) +{ + assert(handle != NULL); + assert(handle->i2sLoopDMADescriptor != NULL); + + handle->state = (uint32_t)kI2S_DmaStateRx; + + return I2S_TransferLoopDMA(base, handle, xfer, loopTransferCount); +} + static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) { uint32_t instance = I2S_GetInstance(base); i2s_dma_private_handle_t *privateHandle = &(s_DmaPrivateHandle[instance]); volatile i2s_transfer_t *transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); uint16_t transferBytes = I2S_GetTransferBytes(transfer); - int i = 0U; + uint32_t i = 0U; uint32_t xferConfig = 0U; + uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + srcAddr = (uint32_t *)(uint32_t)transfer->data; + destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); + srcInc = 1U; + destInc = 0UL; + } + else + { + srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); + destAddr = (uint32_t *)(uint32_t)transfer->data; + srcInc = 0U; + destInc = 1UL; + } /* Initial descriptor is stored in another place in memory, but treat it as another descriptor for simplicity */ privateHandle->dmaDescriptorsUsed = 1U; privateHandle->intA = false; /* submit transfer parameter directly */ - xferConfig = DMA_CHANNEL_XFER(true, false, privateHandle->intA, !privateHandle->intA, handle->bytesPerFrame, - (handle->state == kI2S_DmaStateTx) ? 1U : 0U, - (handle->state == kI2S_DmaStateTx) ? 0U : 1U, transferBytes); - DMA_SubmitChannelTransferParameter( - handle->dmaHandle, xferConfig, - (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)transfer->data : (uint32_t)(&(base->FIFORD))), - (void *)((handle->state == kI2S_DmaStateTx) ? (uint32_t)(&(base->FIFOWR)) : (uint32_t)transfer->data), - (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); + xferConfig = DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 1UL, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); + + DMA_SubmitChannelTransferParameter(handle->dmaHandle, xferConfig, srcAddr, destAddr, + (void *)&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + 0U])); privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; transfer->dataSize -= transferBytes; - transfer->data += transferBytes; + transfer->data = (uint8_t *)((uint32_t)transfer->data + transferBytes); if (transfer->dataSize == 0U) { @@ -478,17 +688,16 @@ static status_t I2S_StartTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) */ for (i = 0; i < DMA_DESCRIPTORS; i++) { - DMA_SetupDescriptor(&(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]), - DMA_CHANNEL_XFER(true, false, false, false, sizeof(uint32_t), 0U, 0U, 8U), - ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)&s_DummyBufferTx : - (void *)(uint32_t)(&(base->FIFORD))), - ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)(&(base->FIFOWR)) : - (void *)(uint32_t)&s_DummyBufferRx), - &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1) % DMA_DESCRIPTORS)])); + /* DMA_CHANNEL_XFER(1UL, 0UL, 0UL, 0UL, sizeof(uint32_t), 0U, 0U, 8U) = 0x10203UL */ + DMA_SetupDescriptor( + &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + i]), 0x10203UL, + ((handle->state == (uint32_t)kI2S_DmaStateTx) ? &s_DummyBufferTx : (uint32_t *)(uint32_t)(&(base->FIFORD))), + ((handle->state == (uint32_t)kI2S_DmaStateTx) ? (uint32_t *)(uint32_t)(&(base->FIFOWR)) : &s_DummyBufferRx), + &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + ((i + 1U) % DMA_DESCRIPTORS)])); } /* Submit and start initial DMA transfer */ - if (handle->state == kI2S_DmaStateTx) + if (handle->state == (uint32_t)kI2S_DmaStateTx) { I2S_TxEnableDMA(base, true); } @@ -514,6 +723,8 @@ static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) dma_descriptor_t *descriptor; dma_descriptor_t *nextDescriptor; uint32_t xferConfig = 0U; + bool intA = false; + uint32_t *srcAddr = NULL, *destAddr = NULL, srcInc = 4UL, destInc = 4UL; instance = I2S_GetInstance(base); privateHandle = &(s_DmaPrivateHandle[instance]); @@ -521,13 +732,28 @@ static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) while (privateHandle->dmaDescriptorsUsed < DMA_DESCRIPTORS) { transfer = &(privateHandle->descriptorQueue[privateHandle->queueDescriptor]); - + intA = privateHandle->intA; if (transfer->dataSize == 0U) { /* Nothing to be added */ return; } + if (handle->state == (uint32_t)kI2S_DmaStateTx) + { + srcAddr = (uint32_t *)(uint32_t)transfer->data; + destAddr = (uint32_t *)(uint32_t)(&(base->FIFOWR)); + srcInc = 1U; + destInc = 0UL; + } + else + { + srcAddr = (uint32_t *)(uint32_t)(&(base->FIFORD)); + destAddr = (uint32_t *)(uint32_t)transfer->data; + srcInc = 0U; + destInc = 1UL; + } + /* Determine currently configured descriptor and the other which it will link to */ descriptor = &(s_DmaDescriptors[(instance * DMA_DESCRIPTORS) + privateHandle->descriptor]); privateHandle->descriptor = (privateHandle->descriptor + 1U) % DMA_DESCRIPTORS; @@ -537,16 +763,10 @@ static void I2S_AddTransferDMA(I2S_Type *base, i2s_dma_handle_t *handle) privateHandle->enqueuedBytes[privateHandle->enqueuedBytesEnd] = transferBytes; privateHandle->enqueuedBytesEnd = (privateHandle->enqueuedBytesEnd + 1U) % DMA_DESCRIPTORS; - xferConfig = DMA_CHANNEL_XFER(true, false, !privateHandle->intA, privateHandle->intA, handle->bytesPerFrame, - (handle->state == kI2S_DmaStateTx) ? 1U : 0U, - (handle->state == kI2S_DmaStateTx) ? 0U : 1U, transferBytes); + xferConfig = + DMA_CHANNEL_XFER(1UL, 0UL, !intA, intA, handle->bytesPerFrame, srcInc, destInc, (uint32_t)transferBytes); - DMA_SetupDescriptor(descriptor, xferConfig, - ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t)transfer->data : - (void *)(uint32_t) & (base->FIFORD)), - ((handle->state == kI2S_DmaStateTx) ? (void *)(uint32_t) & (base->FIFOWR) : - (void *)(uint32_t)transfer->data), - nextDescriptor); + DMA_SetupDescriptor(descriptor, xferConfig, srcAddr, destAddr, nextDescriptor); /* Advance internal state */ privateHandle->dmaDescriptorsUsed++; @@ -575,8 +795,11 @@ void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, ui i2s_dma_private_handle_t *privateHandle = (i2s_dma_private_handle_t *)userData; i2s_dma_handle_t *i2sHandle = privateHandle->handle; I2S_Type *base = privateHandle->base; + uint8_t queueDriverIndex = i2sHandle->queueDriver; + uint32_t enqueueBytes = privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; + uint32_t queueDataAddr = (uint32_t)i2sHandle->i2sQueue[queueDriverIndex].data; - if ((!transferDone) || (i2sHandle->state == kI2S_DmaStateIdle)) + if ((!transferDone) || (i2sHandle->state == (uint32_t)kI2S_DmaStateIdle)) { return; } @@ -585,35 +808,41 @@ void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, ui { /* Finished descriptor, decrease amount of data to be processed */ - i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize -= - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; - i2sHandle->i2sQueue[i2sHandle->queueDriver].data += - privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart]; + i2sHandle->i2sQueue[queueDriverIndex].dataSize -= enqueueBytes; + i2sHandle->i2sQueue[queueDriverIndex].data = (uint8_t *)(queueDataAddr + enqueueBytes); privateHandle->enqueuedBytes[privateHandle->enqueuedBytesStart] = 0U; privateHandle->enqueuedBytesStart = (privateHandle->enqueuedBytesStart + 1U) % DMA_DESCRIPTORS; privateHandle->dmaDescriptorsUsed--; } - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) + if (i2sHandle->i2sQueue[queueDriverIndex].dataSize == 0U) { /* Entire user buffer sent or received - advance to next one */ - i2sHandle->i2sQueue[i2sHandle->queueDriver].data = NULL; - i2sHandle->queueDriver = (i2sHandle->queueDriver + 1U) % I2S_NUM_BUFFERS; + i2sHandle->i2sQueue[queueDriverIndex].data = NULL; + i2sHandle->queueDriver = (queueDriverIndex + 1U) % I2S_NUM_BUFFERS; /* Notify user about buffer completion */ - if (i2sHandle->completionCallback) + if (i2sHandle->completionCallback != NULL) { (i2sHandle->completionCallback)(base, i2sHandle, kStatus_I2S_BufferComplete, i2sHandle->userData); } } - /* check next buffer queue is avaliable or not */ - if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) + + if (i2sHandle->state != (uint32_t)kI2S_DmaStateBusyLoopTransfer) { - /* All user buffers processed */ - I2S_TransferAbortDMA(base, i2sHandle); - } - else - { - /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ - I2S_AddTransferDMA(base, i2sHandle); + /* check next buffer queue is avaliable or not */ + if (i2sHandle->i2sQueue[i2sHandle->queueDriver].dataSize == 0U) + { + if (i2sHandle->state == (uint32_t)kI2S_DmaStateTx) + { + (void)I2S_EmptyTxFifo(base); + } + /* All user buffers processed */ + I2S_TransferAbortDMA(base, i2sHandle); + } + else + { + /* Enqueue another user buffer to DMA if it could not be done when in I2S_Rx/TxTransferSendDMA */ + I2S_AddTransferDMA(base, i2sHandle); + } } } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h index b2b0e5e2f7..ec63472653 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_i2s_dma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -26,8 +26,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief I2S DMA driver version 2.1.0. */ -#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @brief I2S DMA driver version 2.3.1. */ +#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*@}*/ /*! @brief Members not to be accessed / modified outside of the driver. */ @@ -56,6 +56,9 @@ struct _i2s_dma_handle volatile i2s_transfer_t i2sQueue[I2S_NUM_BUFFERS]; /*!< Transfer queue storing transfer buffers */ volatile uint8_t queueUser; /*!< Queue index where user's next transfer will be stored */ volatile uint8_t queueDriver; /*!< Queue index of buffer actually used by the driver */ + + dma_descriptor_t *i2sLoopDMADescriptor; /*!< descriptor pool pointer */ + size_t i2sLoopDMADescriptorNum; /*!< number of descriptor in descriptors pool */ }; /******************************************************************************* @@ -151,6 +154,76 @@ status_t I2S_RxTransferReceiveDMA(I2S_Type *base, i2s_dma_handle_t *handle, i2s_ */ void I2S_DMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t tcds); +/*! + * @brief Install DMA descriptor memory for loop transfer only. + * + * This function used to register DMA descriptor memory for the i2s loop dma transfer. + * + * It must be callbed before I2S_TransferSendLoopDMA/I2S_TransferReceiveLoopDMA and after + * I2S_RxTransferCreateHandleDMA/I2S_TxTransferCreateHandleDMA. + * + * User should be take care about the address of DMA descriptor pool which required align with 16BYTE at least. + * + * @param handle Pointer to i2s DMA transfer handle. + * @param dmaDescriptorAddr DMA descriptor start address. + * @param dmaDescriptorNum DMA descriptor number. + */ +void I2S_TransferInstallLoopDMADescriptorMemory(i2s_dma_handle_t *handle, + void *dmaDescriptorAddr, + size_t dmaDescriptorNum); + +/*! + * @brief Send link transfer data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * This function support loop transfer, such as A->B->...->A, the loop transfer chain + * will be converted into a chain of descriptor and submit to dma. + * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, + * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. + * + * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support + * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop + * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. + * + * @param base I2S peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. + * @param loopTransferCount loop count + * @retval kStatus_Success + */ +status_t I2S_TransferSendLoopDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + i2s_transfer_t *xfer, + uint32_t loopTransferCount); + +/*! + * @brief Receive link transfer data using DMA. + * + * This function receives data using DMA. This is a non-blocking function, which returns + * right away. When all data is received, the receive callback function is called. + * + * This function support loop transfer, such as A->B->...->A, the loop transfer chain + * will be converted into a chain of descriptor and submit to dma. + * Application must be aware of that the more counts of the loop transfer, then more DMA descriptor memory required, + * user can use function I2S_InstallDMADescriptorMemory to register the dma descriptor memory. + * + * As the DMA support maximum 1024 transfer count, so application must be aware of that this transfer function support + * maximum 1024 samples in each transfer, otherwise assert error or error status will be returned. Once the loop + * transfer start, application can use function I2S_TransferAbortDMA to stop the loop transfer. + * + * @param base I2S peripheral base address. + * @param handle Pointer to usart_dma_handle_t structure. + * @param xfer I2S DMA transfer structure. See #i2s_transfer_t. + * @param loopTransferCount loop count + * @retval kStatus_Success + */ +status_t I2S_TransferReceiveLoopDMA(I2S_Type *base, + i2s_dma_handle_t *handle, + i2s_transfer_t *xfer, + uint32_t loopTransferCount); + /*! @} */ /*! @} */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.c index 7114b07c70..712b0faef7 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -8,30 +8,58 @@ #include "fsl_iap.h" #include "fsl_iap_ffr.h" +#include "fsl_iap_kbp.h" +#include "fsl_iap_skboot_authenticate.h" #include "fsl_device_registers.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.iap1" #endif +#if (defined(LPC5512_SERIES) || defined(LPC5514_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC55S16_SERIES) || defined(LPC5524_SERIES) || defined(LPC5502_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5506_SERIES) || defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x1301fe00U) + +#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || defined(LPC5526_SERIES) || \ + defined(LPC55S26_SERIES) || defined(LPC5528_SERIES) || defined(LPC55S28_SERIES) || \ + defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) + +#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)0x130010f0U) + +#else +#error "No valid CPU defined!" + +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static status_t get_cfpa_higher_version(flash_config_t *config); + /*! - * @addtogroup flash_driver_api + * @name flash and ffr Structure * @{ */ -#define ROM_API_TREE ((uint32_t *)0x130010f0) -#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)ROM_API_TREE) +typedef union functionCommandOption +{ + uint32_t commandAddr; + status_t (*eraseCommand)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*programCommand)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*verifyProgramCommand)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flashReadCommand)(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); +} function_command_option_t; -static uint32_t S_VersionMajor = 0; - -typedef status_t (*EraseCommend_t)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); -typedef status_t (*ProgramCommend_t)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); -typedef status_t (*VerifyProgramCommend_t)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); /* *!@brief Structure of version property. * @@ -58,7 +86,7 @@ typedef union StandardVersion } standard_version_t; /*! @brief Interface for the flash driver.*/ -typedef struct FlashDriverInterface +typedef struct version1FlashDriverInterface { standard_version_t version; /*!< flash driver API version number.*/ @@ -74,20 +102,10 @@ typedef struct FlashDriverInterface uint32_t *failedAddress, uint32_t *failedData); status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); - status_t (*flash_erase_with_checker)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); - status_t (*flash_program_with_checker)(flash_config_t *config, - uint32_t start, - uint8_t *src, - uint32_t lengthInBytes); - status_t (*flash_verify_program_with_checker)(flash_config_t *config, - uint32_t start, - uint32_t lengthInBytes, - const uint8_t *expectedData, - uint32_t *failedAddress, - uint32_t *failedData); + uint32_t reserved[3]; /*! Reserved for future use */ /*!< Flash FFR driver*/ status_t (*ffr_init)(flash_config_t *config); - status_t (*ffr_deinit)(flash_config_t *config); + status_t (*ffr_lock_all)(flash_config_t *config); status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); @@ -96,8 +114,69 @@ typedef struct FlashDriverInterface status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +} version1_flash_driver_interface_t; + +/*! @brief Interface for the flash driver.*/ +typedef struct version0FlashDriverInterface +{ + standard_version_t version; /*!< flash driver API version number.*/ + + /*!< Flash driver.*/ + status_t (*flash_init)(flash_config_t *config); + status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); + status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); + status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes); + status_t (*flash_verify_program)(flash_config_t *config, + uint32_t start, + uint32_t lengthInBytes, + const uint8_t *expectedData, + uint32_t *failedAddress, + uint32_t *failedData); + status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value); + + /*!< Flash FFR driver*/ + status_t (*ffr_init)(flash_config_t *config); + status_t (*ffr_lock_all)(flash_config_t *config); + status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part); + status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid); + status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore); + status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode); + status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); + status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); + status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); +} version0_flash_driver_interface_t; + +typedef union flashDriverInterface +{ + const version1_flash_driver_interface_t *version1FlashDriver; + const version0_flash_driver_interface_t *version0FlashDriver; } flash_driver_interface_t; +/*! @}*/ + +/*! + * @name Bootloader API and image authentication Structure + * @{ + */ + +/*! @brief Interface for Bootloader API functions. */ +typedef struct _kb_interface +{ + /*!< Initialize the API. */ + status_t (*kb_init_function)(kb_session_ref_t **session, const kb_options_t *options); + status_t (*kb_deinit_function)(kb_session_ref_t *session); + status_t (*kb_execute_function)(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); +} kb_interface_t; + +//! @brief Interface for image authentication API +typedef struct _skboot_authenticate_interface +{ + skboot_status_t (*skboot_authenticate_function)(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); + void (*skboot_hashcrypt_irq_handler)(void); +} skboot_authenticate_interface_t; +/*! @}*/ + /*! * @brief Root of the bootloader API tree. * @@ -108,74 +187,151 @@ typedef struct FlashDriverInterface */ typedef struct BootloaderTree { - void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ - standard_version_t bootloader_version; /*!< Bootloader version number. */ - const char *copyright; /*!< Copyright string. */ - const uint32_t *reserved; /*!< Do NOT use. */ - const flash_driver_interface_t *flashDriver; /*!< Flash driver API. */ + void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */ + standard_version_t bootloader_version; /*!< Bootloader version number. */ + const char *copyright; /*!< Copyright string. */ + const uint32_t reserved0; /*!< Do NOT use. */ + flash_driver_interface_t flashDriver; + const kb_interface_t *kbApi; /*!< Bootloader API. */ + const uint32_t reserved1[4]; /*!< Do NOT use. */ + const skboot_authenticate_interface_t *skbootAuthenticate; /*!< Image authentication API. */ } bootloader_tree_t; +/******************************************************************************* + * Prototype + ******************************************************************************/ +static uint32_t get_rom_api_version(void); + /******************************************************************************* * Variables ******************************************************************************/ -/*! @brief Global pointer to the flash driver API table in ROM. */ -flash_driver_interface_t *FLASH_API_TREE; /*! Get pointer to flash driver API table in ROM. */ -#define FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver +#define VERSION1_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version1FlashDriver +#define VERSION0_FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver.version0FlashDriver +#define LPC55S69_REV0_FLASH_READ_ADDR (0x130043a3U) +#define LPC55S69_REV1_FLASH_READ_ADDR (0x13007539U) +#define LPC55S16_REV0_FLASH_READ_ADDR (0x1300ade5U) + /******************************************************************************* * Code ******************************************************************************/ -/*! See fsl_flash.h for documentation of this function. */ +static uint32_t get_rom_api_version(void) +{ + if (BOOTLOADER_API_TREE_POINTER->bootloader_version.major == 3u) + { + return 1u; + } + else + { + return 0u; + } +} + +/*! + * @brief Initializes the global flash properties structure members. + * + * This function checks and initializes the Flash module for the other Flash APIs. + */ status_t FLASH_Init(flash_config_t *config) { - assert(FLASH_API_TREE); - config->modeConfig.sysFreqInMHz = kSysToFlashFreq_defaultInMHz; - S_VersionMajor = BOOTLOADER_API_TREE_POINTER->bootloader_version.major; - return FLASH_API_TREE->flash_init(config); + status_t status; + /* Initialize the clock to 96MHz */ + config->modeConfig.sysFreqInMHz = (uint32_t)kSysToFlashFreq_defaultInMHz; + if (get_rom_api_version() == 1u) + { + status = VERSION1_FLASH_API_TREE->flash_init(config); + } + else + { + status = VERSION0_FLASH_API_TREE->flash_init(config); + } + + if (config->PFlashTotalSize == 0xA0000U) + { + config->PFlashTotalSize -= 17U * config->PFlashPageSize; + } + + return status; } -/*! See fsl_flash.h for documentation of this function. */ +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. + */ status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) { - if (S_VersionMajor == 2) + if (get_rom_api_version() == 0u) { - EraseCommend_t EraseCommand = - (EraseCommend_t)(0x1300413b); /*!< get the flash erase api location adress int rom */ - return EraseCommand(config, start, lengthInBytes, key); + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300413bU; /*!< get the flash erase api location adress in rom */ + return runCmdFuncOption.eraseCommand(config, start, lengthInBytes, key); } else { - assert(FLASH_API_TREE); - return FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); + return VERSION1_FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key); } } -/*! See fsl_flash.h for documentation of this function. */ +/*! See fsl_iap.h for documentation of this function. */ status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) { - if (S_VersionMajor == 2) + if (get_rom_api_version() == 0u) { - ProgramCommend_t ProgramCommend = - (ProgramCommend_t)(0x1300419d); /*!< get the flash program api location adress in rom*/ - return ProgramCommend(config, start, src, lengthInBytes); + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300419dU; /*!< get the flash program api location adress in rom*/ + return runCmdFuncOption.programCommand(config, start, src, lengthInBytes); } else { - assert(FLASH_API_TREE); - return FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_program(config, start, src, lengthInBytes); } } -/*! See fsl_flash.h for documentation of this function. */ -status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); + if (get_rom_api_version() == 0u) + { + /*!< get the flash read api location adress in rom*/ + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = LPC55S69_REV0_FLASH_READ_ADDR; + return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); + } + else + { + /*!< get the flash read api location adress in rom*/ + function_command_option_t runCmdFuncOption; + if ((SYSCON->DIEID & SYSCON_DIEID_REV_ID_MASK) != 0u) + { + runCmdFuncOption.commandAddr = LPC55S69_REV1_FLASH_READ_ADDR; + } + else + { + runCmdFuncOption.commandAddr = LPC55S16_REV0_FLASH_READ_ADDR; + } + return runCmdFuncOption.flashReadCommand(config, start, dest, lengthInBytes); + } } -/*! See fsl_flash.h for documentation of this function. */ +/*! See fsl_iap.h for documentation of this function. */ +status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes) +{ + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes); +} + +/*! + * @brief Verifies programming of the desired flash area at a specified margin level. + * + * This function verifies the data programed in the flash memory using the + * Flash Program Check Command and compares it to the expected data for a given + * flash area as determined by the start address and length. + */ status_t FLASH_VerifyProgram(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, @@ -183,103 +339,328 @@ status_t FLASH_VerifyProgram(flash_config_t *config, uint32_t *failedAddress, uint32_t *failedData) { - if (S_VersionMajor == 2) + if (get_rom_api_version() == 0u) { - VerifyProgramCommend_t VerifyProgramCommend = - (VerifyProgramCommend_t)(0x1300427d); /*!< get the flash verify program api location adress in - rom*/ - return VerifyProgramCommend(config, start, lengthInBytes, expectedData, failedAddress, failedData); + function_command_option_t runCmdFuncOption; + runCmdFuncOption.commandAddr = 0x1300427dU; /*!< get the flash verify program api location adress in rom*/ + return runCmdFuncOption.verifyProgramCommand(config, start, lengthInBytes, expectedData, failedAddress, + failedData); } else { - assert(FLASH_API_TREE); - return FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, - failedData); + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, + failedData); } } -/*! See fsl_flash.h for documentation of this function.*/ +/*! + * @brief Returns the desired flash property. + */ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->flash_get_property(config, whichProperty, value); + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->flash_get_property(config, whichProperty, value); } /******************************************************************************** * fsl iap ffr CODE *******************************************************************************/ -/*! See fsl_iap_ffr.h for documentation of this function. */ +static status_t get_cfpa_higher_version(flash_config_t *config) +{ + uint32_t pageData[FLASH_FFR_MAX_PAGE_SIZE / sizeof(uint32_t)]; + uint32_t versionPing = 0U; + uint32_t versionPong = 0U; + + /* Get the CFPA ping page data and the corresponding version */ + config->ffrConfig.cfpaPageOffset = 1U; + status_t status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); + if (status != (int32_t)kStatus_FLASH_Success) + { + return status; + } + versionPing = pageData[1]; + + /* Get the CFPA pong page data and the corresponding version */ + config->ffrConfig.cfpaPageOffset = 2U; + status = FFR_GetCustomerInfieldData(config, (uint8_t *)pageData, 0U, FLASH_FFR_MAX_PAGE_SIZE); + if (status != (int32_t)kStatus_FLASH_Success) + { + return status; + } + versionPong = pageData[1]; + + /* Compare the CFPA ping version and pong version and set it correctly in flash_config structure */ + if (versionPing > versionPong) + { + config->ffrConfig.cfpaPageVersion = versionPing; + config->ffrConfig.cfpaPageOffset = 1U; + } + else + { + config->ffrConfig.cfpaPageVersion = versionPong; + config->ffrConfig.cfpaPageOffset = 2U; + } + return (int32_t)kStatus_FLASH_Success; +} + +/*! + * Initializes the global FFR properties structure members. + */ status_t FFR_Init(flash_config_t *config) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_init(config); + status_t status; + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + status = VERSION0_FLASH_API_TREE->ffr_init(config); + if (status != (status_t)kStatus_FLASH_Success) + { + return status; + } + return get_cfpa_higher_version(config); + } + else + { + assert(VERSION1_FLASH_API_TREE); + status = VERSION1_FLASH_API_TREE->ffr_init(config); + if (status != (status_t)kStatus_FLASH_Success) + { + return status; + } + return get_cfpa_higher_version(config); + } } -/*! See fsl_iap_ffr.h for documentation of this function. */ -status_t FFR_Deinit(flash_config_t *config) +/*! + * Enable firewall for all flash banks. + */ +status_t FFR_Lock_All(flash_config_t *config) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_deinit(config); + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_lock_all(config); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_lock_all(config); + } } -/*! See fsl_iap_ffr.h for documentation of this function. */ +/*! + * APIs to access CMPA pages; + * This routine will erase "customer factory page" and program the page with passed data. + */ status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part); + } } -/*! See fsl_iap_ffr.h for documentation of this function. */ +/*! + * See fsl_iap_ffr.h for documentation of this function. + */ status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_get_uuid(config, uuid); + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_uuid(config, uuid); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_uuid(config, uuid); + } } -/*! See fsl_iap_ffr.h for documentation of this function. */ +/*! + * APIs to access CMPA pages + * Read data stored in 'Customer Factory CFG Page'. + */ status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len); + } } -/*! See fsl_iap_ffr.h for documentation of this function. */ +/*! + * This routine writes the 3 pages allocated for Key store data, + * Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. + */ status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_write(config, pKeyStore); + } } /*! See fsl_iap_ffr.h for documentation of this function. */ status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode); + } } /*! See fsl_iap_ffr.h for documentation of this function. */ status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex); + } } -/*! See fsl_iap_ffr.h for documentation of this function. */ +/*! + * APIs to access CFPA pages + * This routine will erase CFPA and program the CFPA page with passed data. + */ status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_infield_page_write(config, page_data, valid_len); + } } -/*! See fsl_iap_ffr.h for documentation of this function. */ +/*! + * APIs to access CFPA pages + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + */ status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len) { - assert(FLASH_API_TREE); - return FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); + if (get_rom_api_version() == 0u) + { + assert(VERSION0_FLASH_API_TREE); + return VERSION0_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); + } + else + { + assert(VERSION1_FLASH_API_TREE); + return VERSION1_FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len); + } } -/*! @}*/ +/******************************************************************************** + * Bootloader API + *******************************************************************************/ +/*! + * @brief Initialize ROM API for a given operation. + * + * Inits the ROM API based on the options provided by the application in the second + * argument. Every call to rom_init() should be paired with a call to rom_deinit(). + */ +status_t kb_init(kb_session_ref_t **session, const kb_options_t *options) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_init_function(session, options); +} +/*! + * @brief Cleans up the ROM API context. + * + * After this call, the @a context parameter can be reused for another operation + * by calling rom_init() again. + */ +status_t kb_deinit(kb_session_ref_t *session) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_deinit_function(session); +} + +/*! + * Perform the operation configured during init. + * + * This application must call this API repeatedly, passing in sequential chunks of + * data from the boot image (SB file) that is to be processed. The ROM will perform + * the selected operation on this data and return. The application may call this + * function with as much or as little data as it wishes, which can be used to select + * the granularity of time given to the application in between executing the operation. + * + * @param context Current ROM context pointer. + * @param data Buffer of boot image data provided to the ROM by the application. + * @param dataLength Length in bytes of the data in the buffer provided to the ROM. + * + * @retval #kStatus_Success The operation has completed successfully. + * @retval #kStatus_Fail An error occurred while executing the operation. + * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to + * continue processing the boot image. + */ +status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->kbApi->kb_execute_function(session, data, dataLength); +} + +/******************************************************************************** + * Image authentication API + *******************************************************************************/ + +/*! + * @brief Authenticate entry function with ARENA allocator init + * + * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface + */ +skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified) +{ + assert(BOOTLOADER_API_TREE_POINTER); + return BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_authenticate_function(imageStartAddr, + isSignVerified); +} + +/*! + * @brief Interface for image authentication API + */ +void HASH_IRQHandler(void) +{ + assert(BOOTLOADER_API_TREE_POINTER); + BOOTLOADER_API_TREE_POINTER->skbootAuthenticate->skboot_hashcrypt_irq_handler(); +} /******************************************************************************** * EOF *******************************************************************************/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.h index c57f667078..f7b318b66b 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -30,15 +30,15 @@ #endif /*! @brief Flash driver version for SDK*/ -#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +#define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4. */ /*! @brief Flash driver version for ROM*/ enum _flash_driver_version_constants { kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/ kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/ - kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/ - kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/ + kFLASH_DriverVersionMinor = 1, /*!< Minor flash driver version.*/ + kFLASH_DriverVersionBugfix = 3 /*!< Bugfix for flash driver version.*/ }; /*@}*/ @@ -61,13 +61,13 @@ enum _flash_driver_version_constants */ /*! @brief Flash driver status group. */ #if defined(kStatusGroup_FlashDriver) -#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupGeneric kStatusGroup_Generic #define kStatusGroupFlashDriver kStatusGroup_FlashDriver #elif defined(kStatusGroup_FLASHIAP) -#define kStatusGroupGeneric kStatusGroup_Generic +#define kStatusGroupGeneric kStatusGroup_Generic #define kStatusGroupFlashDriver kStatusGroup_FLASH #else -#define kStatusGroupGeneric 0 +#define kStatusGroupGeneric 0 #define kStatusGroupFlashDriver 1 #endif @@ -350,12 +350,14 @@ status_t FLASH_Init(flash_config_t *config); * * @param config The pointer to the storage for the driver runtime state. * @param start The start address of the desired flash memory to be erased. - * The start address does not need to be sector-aligned. + * The start address need to be 512bytes-aligned. * @param lengthInBytes The length, given in bytes (not words or long-words) - * to be erased. Must be word-aligned. + * to be erased. Must be 512bytes-aligned. * @param key The value used to validate all flash erase APIs. * - * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_Success API was executed successfully; + * the appropriate number of flash sectors based on the desired + * start address and length were erased successfully. * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. * @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. * @retval #kStatus_FLASH_AddressError The address is out of range. @@ -381,13 +383,14 @@ status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBy * * @param config A pointer to the storage for the driver runtime state. * @param start The start address of the desired flash memory to be programmed. Must be - * word-aligned. + * 512bytes-aligned. * @param src A pointer to the source buffer of data that is to be programmed * into the flash. * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be programmed. Must be word-aligned. + * to be programmed. Must be 512bytes-aligned. * - * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_Success API was executed successfully; the desired data were programed successfully + * into flash based on desired start address and length. * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. * @retval #kStatus_FLASH_AddressError Address is out of range. @@ -401,6 +404,31 @@ status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uin /*@}*/ +/*! + * @brief Reads flash at locations passed in through parameters. + * + * This function read the flash memory from a given flash area as determined + * by the start address and the length. + * + * @param config A pointer to the storage for the driver runtime state. + * @param start The start address of the desired flash memory to be read. + * @param dest A pointer to the dest buffer of data that is to be read + * from the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be read. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @retval #kStatus_FLASH_AddressError Address is out of range. + * @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + */ +status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes); + /*! * @name Verification * @{ @@ -415,12 +443,11 @@ status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uin * * @param config A pointer to the storage for the driver runtime state. * @param start The start address of the desired flash memory to be verified. - * The start address does not need to be sector-aligned but must be word-aligned. + * The start address need to be 512bytes-aligned. * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. Must be word-aligned. - * @param margin Read margin choice. + * to be verified. Must be 512bytes-aligned. * - * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_Success API was executed successfully; the specified FLASH region has been erased. * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. * @retval #kStatus_FLASH_AddressError Address is out of range. @@ -440,18 +467,19 @@ status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t leng * flash area as determined by the start address and length. * * @param config A pointer to the storage for the driver runtime state. - * @param start The start address of the desired flash memory to be verified. Must be word-aligned. + * @param start The start address of the desired flash memory to be verified. need be 512bytes-aligned. * @param lengthInBytes The length, given in bytes (not words or long-words), - * to be verified. Must be word-aligned. + * to be verified. need be 512bytes-aligned. * @param expectedData A pointer to the expected data that is to be * verified against. - * @param margin Read margin choice. * @param failedAddress A pointer to the returned failing address. * @param failedData A pointer to the returned failing data. Some derivatives do * not include failed data as part of the FCCOBx registers. In this * case, zeros are returned upon failure. * - * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_Success API was executed successfully; + * the desired data have been successfully programed into specified FLASH region. + * * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. * @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline. * @retval #kStatus_FLASH_AddressError Address is out of range. @@ -483,7 +511,7 @@ status_t FLASH_VerifyProgram(flash_config_t *config, * enum flash_property_tag_t * @param value A pointer to the value returned for the desired flash property. * - * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_Success API was executed successfully; the flash property was stored to value. * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. * @retval #kStatus_FLASH_UnknownProperty An unknown property tag. */ @@ -495,4 +523,6 @@ status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichPro } #endif +/*@}*/ + #endif /* __FLASH_FLASH_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h index 1f366868d1..9481e07af1 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_ffr.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -26,7 +26,7 @@ * @{ */ /*! @brief Flash IFR driver version for SDK*/ -#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ /*@}*/ /*! @brief Alignment(down) utility. */ @@ -39,10 +39,11 @@ #define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a)))))) #endif -#define FLASH_FFR_MAX_PAGE_SIZE (512u) +#define FLASH_FFR_MAX_PAGE_SIZE (512u) #define FLASH_FFR_HASH_DIGEST_SIZE (32u) -#define FLASH_FFR_IV_CODE_SIZE (52u) +#define FLASH_FFR_IV_CODE_SIZE (52u) +/*! @brief flash ffr page offset. */ enum _flash_ffr_page_offset { kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/ @@ -61,6 +62,7 @@ enum _flash_ffr_page_offset kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/ }; +/*! @brief flash ffr page number. */ enum _flash_ffr_page_num { kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/ @@ -112,14 +114,14 @@ typedef struct _cfpa_cfg_info uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */ } cfpa_cfg_info_t; -#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) +#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U) #define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U) #define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U) #define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U) -#define FFR_USBID_VENDORID_MASK (0xFFFFU) -#define FFR_USBID_VENDORID_SHIFT (0U) -#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) +#define FFR_USBID_VENDORID_MASK (0xFFFFU) +#define FFR_USBID_VENDORID_SHIFT (0U) +#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U) #define FFR_USBID_PRODUCTID_SHIFT (16U) typedef struct _cmpa_cfg_info @@ -150,16 +152,16 @@ typedef struct _cmpa_key_store_header uint8_t reserved[4]; } cmpa_key_store_header_t; -#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) -#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) -#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) +#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U) +#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U) +#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U) #define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U) #define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U) #define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U) -#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) -#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) -#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) +#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU) +#define FFR_PERIPHERALCFG_PERI_SHIFT (0U) +#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U) #define FFR_PERIPHERALCFG_COREEN_SHIFT (31U) typedef struct _nmpa_cfg_info @@ -226,36 +228,161 @@ typedef enum _ffr_bank_type extern "C" { #endif -/*! Generic APIs for FFR */ -status_t FFR_Init(flash_config_t *config); -status_t FFR_Deinit(flash_config_t *config); +/*! + * @name FFR APIs + * @{ + */ -/*! APIs to access CFPA pages */ -status_t FFR_CustomerPagesInit(flash_config_t *config); +/*! + * @brief Initializes the global FFR properties structure members. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success API was executed successfully. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FFR_Init(flash_config_t *config); + +/*! + * @brief Enable firewall for all flash banks. + * + * CFPA, CMPA, and NMPA flash areas region will be locked, After this function executed; + * Unless the board is reset again. + * + * @param config A pointer to the storage for the driver runtime state. + * + * @retval #kStatus_FLASH_Success An invalid argument is provided. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + */ +status_t FFR_Lock_All(flash_config_t *config); + +/*! + * @brief APIs to access CFPA pages + * + * This routine will erase CFPA and program the CFPA page with passed data. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the CFPA. + * @param valid_len The length, given in bytes, to be programmed. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CFPA. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_FfrBankIsLocked The CFPA was locked. + * @retval #kStatus_FLASH_OutOfDateCfpaPage It is not newest CFPA page. + */ status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len); -/*! Read data stored in 'Customer In-field Page'. */ + +/*! + * @brief APIs to access CFPA pages + * + * Generic read function, used by customer to read data stored in 'Customer In-field Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read from 'Customer In-field Page'. + * @param offset An offset from the 'Customer In-field Page' start address. + * @param len The length, given in bytes, to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer In-field Page'. + * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -/*! APIs to access CMPA pages */ -bool FFR_IsCmpaCfgPageUpdateInProgress(flash_config_t *config); -status_t FFR_RecoverCmpaCfgPage(flash_config_t *config); -status_t FFR_ProcessCmpaCfgPageUpdate(flash_config_t *config, cmpa_prog_process_t option); +/*! + * @brief APIs to access CMPA pages + * + * This routine will erase "customer factory page" and program the page with passed data. + * If 'seal_part' parameter is TRUE then the routine will compute SHA256 hash of + * the page contents and then programs the pages. + * 1.During development customer code uses this API with 'seal_part' set to FALSE. + * 2.During manufacturing this parameter should be set to TRUE to seal the part + * from further modifications + * 3.This routine checks if the page is sealed or not. A page is said to be sealed if + * the SHA256 value in the page has non-zero value. On boot ROM locks the firewall for + * the region if hash is programmed anyways. So, write/erase commands will fail eventually. + * + * @param config A pointer to the storage for the driver runtime state. + * @param page_data A pointer to the source buffer of data that is to be programmed + * into the "customer factory page". + * @param seal_part Set fasle for During development customer code. + * + * @retval #kStatus_FLASH_Success The desire page-data were programed successfully into CMPA. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part); -/*! Read data stored in 'Customer Factory CFG Page'. */ + +/*! + * @brief APIs to access CMPA page + * + * Read data stored in 'Customer Factory CFG Page'. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pData A pointer to the dest buffer of data that is to be read + * from the Customer Factory CFG Page. + * @param offset Address offset relative to the CMPA area. + * @param len The length, given in bytes to be read. + * + * @retval #kStatus_FLASH_Success Get data from 'Customer Factory CFG Page'. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); + +/*! + * @brief APIs to access CMPA page + * + * 1.SW should use this API routine to get the UUID of the chip. + * 2.Calling routine should pass a pointer to buffer which can hold 128-bit value. + */ +status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); + +/*! + * @brief This routine writes the 3 pages allocated for Key store data, + * + * 1.Used during manufacturing. Should write pages when 'customer factory page' is not in sealed state. + * 2.Optional routines to set individual data members (activation code, key codes etc) to construct + * the key store structure in RAM before committing it to IFR/FFR. + * + * @param config A pointer to the storage for the driver runtime state. + * @param pKeyStore A Pointer to the 3 pages allocated for Key store data. + * that will be written to 'customer factory page'. + * + * @retval #kStatus_FLASH_Success The key were programed successfully into FFR. + * @retval #kStatus_FLASH_InvalidArgument Parameter is not aligned with the specified baseline. + * @retval kStatus_FTFx_AddressError Address is out of range. + * @retval #kStatus_FLASH_CommandFailure access error. + */ status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore); + +/*! + * @brief Get/Read Key store code routines + * + * 1. Calling code should pass buffer pointer which can hold activation code 1192 bytes. + * 2. Check if flash aperture is small or regular and read the data appropriately. + */ status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode); + +/*! + * @brief Get/Read Key store code routines + * + * 1. Calling code should pass buffer pointer which can hold key code 52 bytes. + * 2. Check if flash aperture is small or regular and read the data appropriately. + * 3. keyIndex specifies which key code is read. + */ status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex); -/*! APIs to access NMPA pages */ -status_t FFR_NxpAreaCheckIntegrity(flash_config_t *config); -status_t FFR_GetRompatchData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -/*! Read data stored in 'NXP Manufacuring Programmed CFG Page'. */ -status_t FFR_GetManufactureData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len); -status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid); +/*@}*/ #ifdef __cplusplus } #endif +/*@}*/ + #endif /*! __FSL_FLASH_FFR_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_kbp.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_kbp.h new file mode 100644 index 0000000000..453a89a8fd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_kbp.h @@ -0,0 +1,245 @@ +/* + * Copyright (c) 2020-2021, Freescale Semiconductor, Inc. + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_IAP_KBP_H_ +#define _FSL_IAP_KBP_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup kb_driver + * @{ + */ +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief ROM API status group number */ +#define kStatusGroup_RomApi (108U) + +/*! @brief ROM API status codes. */ +enum +{ + kStatus_RomApiExecuteCompleted = kStatus_Success, /*!< ROM successfully process the whole sb file/boot image.*/ + kStatus_RomApiNeedMoreData = + MAKE_STATUS(kStatusGroup_RomApi, 1), /*!< ROM needs more data to continue processing the boot image.*/ + kStatus_RomApiBufferSizeNotEnough = + MAKE_STATUS(kStatusGroup_RomApi, + 2), /*!< The user buffer is not enough for use by Kboot during execution of the operation.*/ + kStatus_RomApiInvalidBuffer = + MAKE_STATUS(kStatusGroup_RomApi, 3), /*!< The user buffer is not ok for sbloader or authentication.*/ +}; + +/*! + * @brief Details of the operation to be performed by the ROM. + * + * The #kRomAuthenticateImage operation requires the entire signed image to be + * available to the application. + */ +typedef enum _kb_operation +{ + kRomAuthenticateImage = 1, /*!< Authenticate a signed image.*/ + kRomLoadImage = 2, /*!< Load SB file.*/ + kRomOperationCount = 3, +} kb_operation_t; + +/*! + * @brief Security constraint flags, Security profile flags. + */ +enum _kb_security_profile +{ + kKbootMinRSA4096 = (1 << 16), +}; + +/*! + * @brief Memory region definition. + */ +typedef struct _kb_region +{ + uint32_t address; + uint32_t length; +} kb_region_t; + +/*! + * @brief User-provided options passed into kb_init(). + * + * The buffer field is a pointer to memory provided by the caller for use by + * Kboot during execution of the operation. Minimum size is the size of each + * certificate in the chain plus 432 bytes additional per certificate. + * + * The profile field is a mask that specifies which features are required in + * the SB file or image being processed. This includes the minimum AES and RSA + * key sizes. See the _kb_security_profile enum for profile mask constants. + * The image being loaded or authenticated must match the profile or an error will + * be returned. + * + * minBuildNumber is an optional field that can be used to prevent version + * rollback. The API will check the build number of the image, and if it is less + * than minBuildNumber will fail with an error. + * + * maxImageLength is used to verify the offsetToCertificateBlockHeaderInBytes + * value at the beginning of a signed image. It should be set to the length of + * the SB file. If verifying an image in flash, it can be set to the internal + * flash size or a large number like 0x10000000. + * + * userRHK can optionally be used by the user to override the RHK in IFR. If + * userRHK is not NULL, it points to a 32-byte array containing the SHA-256 of + * the root certificate's RSA public key. + * + * The regions field points to an array of memory regions that the SB file being + * loaded is allowed to access. If regions is NULL, then all memory is + * accessible by the SB file. This feature is required to prevent a malicious + * image from erasing good code or RAM contents while it is being loaded, only + * for us to find that the image is inauthentic when we hit the end of the + * section. + * + * overrideSBBootSectionID lets the caller override the default section of the + * SB file that is processed during a kKbootLoadSB operation. By default, + * the section specified in the firstBootableSectionID field of the SB header + * is loaded. If overrideSBBootSectionID is non-zero, then the section with + * the given ID will be loaded instead. + * + * The userSBKEK field lets a user provide their own AES-256 key for unwrapping + * keys in an SB file during the kKbootLoadSB operation. userSBKEK should point + * to a 32-byte AES-256 key. If userSBKEK is NULL then the IFR SBKEK will be used. + * After kb_init() returns, the caller should zero out the data pointed to by + * userSBKEK, as the API will have installed the key in the CAU3. + */ + +typedef struct _kb_load_sb +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t overrideSBBootSectionID; + uint32_t *userSBKEK; + uint32_t regionCount; + const kb_region_t *regions; +} kb_load_sb_t; + +typedef struct _kb_authenticate +{ + uint32_t profile; + uint32_t minBuildNumber; + uint32_t maxImageLength; + uint32_t *userRHK; +} kb_authenticate_t; + +typedef struct _kb_options +{ + uint32_t version; /*!< Should be set to kKbootApiVersion.*/ + uint8_t *buffer; /*!< Caller-provided buffer used by Kboot.*/ + uint32_t bufferLength; + kb_operation_t op; + union + { + kb_authenticate_t authenticate; /*! Settings for kKbootAuthenticate operation.*/ + kb_load_sb_t loadSB; /*! Settings for kKbootLoadSB operation.*/ + }; +} kb_options_t; + +/*! + * @brief Interface to memory operations for one region of memory. + */ +typedef struct _memory_region_interface +{ + status_t (*init)(void); + status_t (*read)(uint32_t address, uint32_t length, uint8_t *buffer); + status_t (*write)(uint32_t address, uint32_t length, const uint8_t *buffer); + status_t (*fill)(uint32_t address, uint32_t length, uint32_t pattern); + status_t (*flush)(void); + status_t (*erase)(uint32_t address, uint32_t length); + status_t (*config)(uint32_t *buffer); + status_t (*erase_all)(void); +} memory_region_interface_t; + +/*! + * @brief Structure of a memory map entry. + */ +typedef struct _memory_map_entry +{ + uint32_t startAddress; + uint32_t endAddress; + uint32_t memoryProperty; + uint32_t memoryId; + const memory_region_interface_t *memoryInterface; +} memory_map_entry_t; + +typedef struct _kb_opaque_session_ref +{ + kb_options_t context; + bool cau3Initialized; + memory_map_entry_t *memoryMap; +} kb_session_ref_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Initialize ROM API for a given operation. + * + * Inits the ROM API based on the options provided by the application in the second + * argument. Every call to rom_init() should be paired with a call to rom_deinit(). + * + * @retval #kStatus_Success API was executed successfully. + * @retval #kStatus_InvalidArgument An invalid argument is provided. + * @retval #kStatus_RomApiBufferSizeNotEnough The user buffer is not enough for use by Kboot during execution of the + * operation. + * @retval #kStatus_RomApiInvalidBuffer The user buffer is not ok for sbloader or authentication. + * @retval #kStatus_SKBOOT_Fail Return the failed status of secure boot. + * @retval #kStatus_SKBOOT_KeyStoreMarkerInvalid The key code for the particular PRINCE region is not present in the + * keystore + * @retval #kStatus_SKBOOT_Success Return the successful status of secure boot. + */ +status_t kb_init(kb_session_ref_t **session, const kb_options_t *options); + +/*! + * @brief Cleans up the ROM API context. + * + * After this call, the context parameter can be reused for another operation + * by calling rom_init() again. + * + * @retval #kStatus_Success API was executed successfully + */ +status_t kb_deinit(kb_session_ref_t *session); + +/*! + * Perform the operation configured during init. + * + * This application must call this API repeatedly, passing in sequential chunks of + * data from the boot image (SB file) that is to be processed. The ROM will perform + * the selected operation on this data and return. The application may call this + * function with as much or as little data as it wishes, which can be used to select + * the granularity of time given to the application in between executing the operation. + * + * @param session Current ROM context pointer. + * @param data Buffer of boot image data provided to the ROM by the application. + * @param dataLength Length in bytes of the data in the buffer provided to the ROM. + * + * @retval #kStatus_Success ROM successfully process the part of sb file/boot image. + * @retval #kStatus_RomApiExecuteCompleted ROM successfully process the whole sb file/boot image. + * @retval #kStatus_Fail An error occurred while executing the operation. + * @retval #kStatus_RomApiNeedMoreData No error occurred, but the ROM needs more data to + * continue processing the boot image. + * @retval #kStatus_RomApiBufferSizeNotEnough user buffer is not enough for + * use by Kboot during execution of the operation. + */ +status_t kb_execute(kb_session_ref_t *session, const uint8_t *data, uint32_t dataLength); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_IAP_KBP_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_skboot_authenticate.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_skboot_authenticate.h new file mode 100644 index 0000000000..67a513bc3c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iap_skboot_authenticate.h @@ -0,0 +1,77 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_IAP_SKBOOT_AUTHENTICATE_H_ +#define _FSL_IAP_SKBOOT_AUTHENTICATE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup skboot_authenticate + * @{ + */ + +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! @brief SKBOOT return status*/ +typedef enum _skboot_status +{ + kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< SKBOOT return success status.*/ + kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< SKBOOT return fail status.*/ + kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< SKBOOT return invalid argument status.*/ + kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< SKBOOT return Keystore invalid Marker status.*/ + kStatus_SKBOOT_HashcryptFinishedWithStatusSuccess = + 0xc15a5ac3, /*!< SKBOOT return Hashcrypt finished with the success status.*/ + kStatus_SKBOOT_HashcryptFinishedWithStatusFail = + 0xc15a5acb, /*!< SKBOOT return Hashcrypt finished with the fail status.*/ +} skboot_status_t; + +/*! @brief Secure bool flag*/ +typedef enum _secure_bool +{ + kSECURE_TRUE = 0xc33cc33cU, /*!< Secure true flag.*/ + kSECURE_FALSE = 0x5aa55aa5U, /*!< Secure false flag.*/ + kSECURE_CALLPROTECT_SECURITY_FLAGS = 0xc33c5aa5U, /*!< Secure call protect the security flag.*/ + kSECURE_CALLPROTECT_IS_APP_READY = 0x5aa5c33cU, /*!< Secure call protect the app is ready flag.*/ + kSECURE_TRACKER_VERIFIED = 0x55aacc33U, /*!< Secure tracker verified flag.*/ +} secure_bool_t; + +/******************************************************************************* + * Externs + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Authenticate entry function with ARENA allocator init + * + * This is called by ROM boot or by ROM API g_skbootAuthenticateInterface + */ +skboot_status_t skboot_authenticate(const uint8_t *imageStartAddr, secure_bool_t *isSignVerified); + +/*! + * @brief Interface for image authentication API + */ +void HASH_IRQHandler(void); + +#if defined(__cplusplus) +} +#endif + +/*! + *@} + */ + +#endif /* _FSL_IAP_SKBOOT_AUTHENTICATE_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c index b2f10a7c65..5ef935985f 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -61,9 +61,9 @@ void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connect /* extract pmux to be used */ pmux_id = ((uint32_t)(connection)) >> PMUX_SHIFT; /* extract function number */ - output_id = ((uint32_t)(connection)) & 0xffffU; + output_id = ((uint32_t)(connection)) & ((1UL << PMUX_SHIFT) - 1U); /* programm signal */ - *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4)) = output_id; + *(volatile uint32_t *)(((uint32_t)base) + pmux_id + (index * 4U)) = output_id; } #if defined(FSL_FEATURE_INPUTMUX_HAS_SIGNAL_ENA) @@ -81,20 +81,34 @@ void INPUTMUX_AttachSignal(INPUTMUX_Type *base, uint32_t index, inputmux_connect void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable) { uint32_t ena_id; + uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U; uint32_t bit_offset; +#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX + uint32_t chmux_offset; + uint32_t chmux_value; + + /* Only enable need to update channel mux */ + if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U)) + { + chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL); + chmux_value = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL); + *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value; + } + ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U; +#endif /* extract enable register to be used */ - ena_id = ((uint32_t)(signal)) >> ENA_SHIFT; + ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask; /* extract enable bit offset */ - bit_offset = ((uint32_t)(signal)) & 0xfU; + bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U); /* set signal */ if (enable) { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1U << bit_offset); + *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset); } else { - *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1U << bit_offset); + *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset); } } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h index edf4ffa3cd..ddb9e26c55 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -27,8 +27,8 @@ /*! @name Driver version */ /*@{*/ /*! @brief Group interrupt driver version for SDK */ -#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ - /*@}*/ +#define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ /******************************************************************************* * API diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux_connections.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux_connections.h index 189ad093eb..6031941dca 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux_connections.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_inputmux_connections.h @@ -28,143 +28,149 @@ */ /*! @brief Periphinmux IDs */ -#define SCT0_INMUX0 0x00U -#define TIMER0CAPTSEL0 0x20U -#define TIMER1CAPTSEL0 0x40U -#define TIMER2CAPTSEL0 0x60U -#define PINTSEL0 0xC0U -#define DMA0_ITRIG_INMUX0 0xE0U -#define DMA0_OTRIG_INMUX0 0x160U -#define FREQMEAS_REF_REG 0x180U +#define SCT0_INMUX0 0x00U +#define TIMER0CAPTSEL0 0x20U +#define TIMER1CAPTSEL0 0x40U +#define TIMER2CAPTSEL0 0x60U +#define PINTSEL_PMUX_ID 0xC0U +#define PINTSEL0 0xC0U +#define DMA0_ITRIG_INMUX0 0xE0U +#define DMA0_OTRIG_INMUX0 0x160U +#define FREQMEAS_REF_REG 0x180U #define FREQMEAS_TARGET_REG 0x184U -#define TIMER3CAPTSEL0 0x1A0U -#define TIMER4CAPTSEL0 0x1C0U -#define PINTSECSEL0 0x1E0U -#define DMA1_ITRIG_INMUX0 0x200U -#define DMA1_OTRIG_INMUX0 0x240U -#define PMUX_SHIFT 20U +#define TIMER3CAPTSEL0 0x1A0U +#define TIMER4CAPTSEL0 0x1C0U +#define PINTSECSEL0 0x1E0U +#define DMA1_ITRIG_INMUX0 0x200U +#define DMA1_OTRIG_INMUX0 0x240U +#define DMA0_REQ_ENA_ID 0x740U +#define DMA1_REQ_ENA_ID 0x760U +#define DMA0_ITRIG_ENA_ID 0x780U +#define DMA1_ITRIG_ENA_ID 0x7A0U +#define ENA_SHIFT 8U +#define PMUX_SHIFT 20U /*! @brief INPUTMUX connections type */ typedef enum _inputmux_connection_t { /*!< SCT0 INMUX. */ - kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT), kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT), kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), - kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT), + kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT), /*!< TIMER0 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT), /*!< TIMER1 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT), /*!< TIMER2 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT), /*!< Pin interrupt select. */ - kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT), @@ -187,16 +193,16 @@ typedef enum _inputmux_connection_t kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT), kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT), kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT), kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT), @@ -221,33 +227,33 @@ typedef enum _inputmux_connection_t kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT), /*!< DMA0 Input trigger. */ - kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT), /*!< DMA0 output trigger. */ - kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), @@ -264,94 +270,94 @@ typedef enum _inputmux_connection_t kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT), /*!< Selection for frequency measurement reference clock. */ kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasRef= 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeasRef = 4u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT), - /*!< Selection for frequency measurement target clock. */ + /*!< Selection for frequency measurement target clock. */ kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_32KhzOscToFreqmeasTarget= 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), - kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_32KhzOscToFreqmeasTarget = 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), + kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT), /*!< TIMER3 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT), /*!< Timer4 CAPTSEL. */ - kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT), kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), - kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT), + kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT), /*Pin interrupt secure select */ - kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), - kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT), + kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT), @@ -376,34 +382,115 @@ typedef enum _inputmux_connection_t kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT), /*!< DMA1 Input trigger. */ - kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Ctimer4M1ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Ctimer4M0ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT), /*!< DMA1 output trigger. */ - kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm2RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), - kINPUTMUX_Dma1Flexcomm2TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm3RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), + kINPUTMUX_Dma1Flexcomm3TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT), } inputmux_connection_t; +/*! @brief INPUTMUX signal enable/disable type */ +typedef enum _inputmux_signal_t +{ + /*!< DMA0 REQ signal. */ + kINPUTMUX_HashCryptToDmac0Ch0RequestEna = 0U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm8RxToDmac0Ch2RequestEna = 2U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm8TxToDmac0Ch3RequestEna = 3U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm0RxToDmac0Ch4RequestEna = 4U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm0TxToDmac0Ch5RequestEna = 5U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm1RxToDmac0Ch6RequestEna = 6U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm1TxToDmac0Ch7RequestEna = 7U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm3RxToDmac0Ch8RequestEna = 8U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm3TxToDmac0Ch9RequestEna = 9U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm2RxToDmac0Ch10RequestEna = 10U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm2TxToDmac0Ch11RequestEna = 11U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm4RxToDmac0Ch12RequestEna = 12U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm4TxToDmac0Ch13RequestEna = 13U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm5RxToDmac0Ch14RequestEna = 14U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm5TxToDmac0Ch15RequestEna = 15U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm6RxToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm6TxToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm7RxToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm7TxToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Adc0FIFO0ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Adc0FIFO1ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_ENA_ID << ENA_SHIFT), + + /*!< DMA1 REQ signal. */ + kINPUTMUX_HashCryptToDmac1Ch0RequestEna = 0U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm8RxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm8TxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm0RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm0TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm1RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm1TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm3RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + kINPUTMUX_Flexcomm3TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_ENA_ID << ENA_SHIFT), + + /*!< DMA0 input trigger source enable. */ + kINPUTMUX_Dmac0InputTriggerPint0Ena = 0U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerPint1Ena = 1U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerPint2Ena = 2U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerPint3Ena = 3U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 4U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 5U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 6U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 7U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 8U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 9U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 10U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 11U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 12U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 13U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerCompOutEna = 14U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerDma0Out0Ena = 15U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerDma0Out1Ena = 16U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerDma0Out2Ena = 17U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerDma0Out3Ena = 18U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerSctDmac0Ena = 19U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerSctDmac1Ena = 20U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac0InputTriggerHashOutEna = 21U + (DMA0_ITRIG_ENA_ID << ENA_SHIFT), + + /*!< DMA1 input trigger source enable. */ + kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 6U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerCtimer4M0Ena = 7U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerDma1Out0Ena = 8U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerDma1Out1Ena = 9U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerDma1Out2Ena = 10U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerDma1Out3Ena = 11U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerSctDmac0Ena = 12U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerSctDmac1Ena = 13U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), + kINPUTMUX_Dmac1InputTriggerHashOutEna = 14U + (DMA1_ITRIG_ENA_ID << ENA_SHIFT), +} inputmux_signal_t; + +/*@}*/ + /*@}*/ #endif /* _FSL_INPUTMUX_CONNECTIONS_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iocon.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iocon.h index 25cd4e9b2b..e705e91f66 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iocon.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_iocon.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -29,8 +29,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief IOCON driver version 2.1.1. */ -#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*! @brief IOCON driver version. */ +#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*@}*/ /** @@ -38,53 +38,57 @@ */ typedef struct _iocon_group { - uint32_t port : 8; /* Pin port */ - uint32_t pin : 8; /* Pin number */ - uint32_t ionumber : 8; /* IO number */ - uint32_t modefunc : 16; /* Function and mode */ + uint8_t port; /* Pin port */ + uint8_t pin; /* Pin number */ + uint8_t ionumber; /* IO number */ + uint16_t modefunc; /* Function and mode */ } iocon_group_t; /** * @brief IOCON function and mode selection definitions * @note See the User Manual for specific modes and functions supported by the various pins. */ +#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ +#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ +#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ +#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ +#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ +#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ +#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ +#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ #if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ -#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ -#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ +#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ +#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ #define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ #define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ #define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ #define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ #define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ #define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ +#endif /* FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH */ + #if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ +#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ #define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ +#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ #define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ #endif #if defined(IOCON_PIO_I2CSLEW_SHIFT) #define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_MODE (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ #endif #if defined(IOCON_PIO_EGP_SHIFT) #define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_MODE (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ +#define IOCON_I2C_SLEW IOCON_I2C_MODE /*!< Deprecated name for #IOCON_I2C_MODE */ #endif #if defined(IOCON_PIO_SLEW_SHIFT) #define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ -#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ +#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */ #endif #if defined(IOCON_PIO_INVERT_SHIFT) @@ -99,11 +103,11 @@ typedef struct _iocon_group #if defined(IOCON_PIO_FILTEROFF_SHIFT) #define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ +#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ #endif #if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ +#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ #define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ #endif @@ -113,7 +117,7 @@ typedef struct _iocon_group #if defined(IOCON_PIO_I2CFILTER_SHIFT) #define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ +#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */ #endif #if defined(IOCON_PIO_ASW_SHIFT) @@ -127,20 +131,20 @@ typedef struct _iocon_group #if defined(IOCON_PIO_ECS_SHIFT) #define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */ -#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ +#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */ #endif #if defined(IOCON_PIO_S_MODE_SHIFT) #define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ #define IOCON_S_MODE_1CLK \ (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ + */ #define IOCON_S_MODE_2CLK \ (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ + */ #define IOCON_S_MODE_3CLK \ (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ + */ #define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ #endif @@ -150,83 +154,6 @@ typedef struct _iocon_group << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ #endif -#else -#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ -#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ -#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ -#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ -#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ -#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ -#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ -#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ - -#if defined(IOCON_PIO_MODE_SHIFT) -#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */ -#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */ -#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */ -#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */ -#endif - -#if defined(IOCON_PIO_I2CSLEW_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_EGP_SHIFT) -#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */ -#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */ -#endif - -#if defined(IOCON_PIO_INVERT_SHIFT) -#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */ -#endif - -#if defined(IOCON_PIO_DIGIMODE_SHIFT) -#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */ -#define IOCON_DIGITAL_EN \ - (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */ -#endif - -#if defined(IOCON_PIO_FILTEROFF_SHIFT) -#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */ -#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */ -#endif - -#if defined(IOCON_PIO_I2CDRIVE_SHIFT) -#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */ -#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */ -#endif - -#if defined(IOCON_PIO_OD_SHIFT) -#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */ -#endif - -#if defined(IOCON_PIO_I2CFILTER_SHIFT) -#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */ -#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */ -#endif - -#if defined(IOCON_PIO_S_MODE_SHIFT) -#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */ -#define IOCON_S_MODE_1CLK \ - (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_2CLK \ - (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE_3CLK \ - (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \ - */ -#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */ -#endif - -#if defined(IOCON_PIO_CLK_DIV_SHIFT) -#define IOCON_CLKDIV(div) \ - ((div) \ - << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ -#endif - -#endif #if defined(__cplusplus) extern "C" { #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c index 8bfe105651..7835e6fc45 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -69,7 +69,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the clock for LPADC instance. */ - CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); + (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Reset the module. */ @@ -119,7 +119,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */ | ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */ | ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */ - | ADC_CFG_TPRICTRL(config->triggerPrioirtyPolicy); /* Trigger priority policy. */ + | ADC_CFG_TPRICTRL(config->triggerPriorityPolicy); /* Trigger priority policy. */ base->CFG = tmp32; /* ADCx_PAUSE. */ @@ -157,7 +157,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) * config->powerUpDelay = 0x80; * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; * config->enableConvPause = false; * config->convPauseDelay = 0U; * config->FIFO0Watermark = 0U; @@ -169,7 +169,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config) void LPADC_GetDefaultConfig(lpadc_config_t *config) { /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); #if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN config->enableInternalClock = false; @@ -186,7 +186,7 @@ void LPADC_GetDefaultConfig(lpadc_config_t *config) config->powerUpDelay = 0x80; config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; config->powerLevelMode = kLPADC_PowerLevelAlt1; - config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately; + config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; config->enableConvPause = false; config->convPauseDelay = 0U; #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) @@ -209,7 +209,7 @@ void LPADC_Deinit(ADC_Type *base) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Gate the clock. */ - CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); + (void)CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } @@ -294,7 +294,10 @@ void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_ | ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */ | ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */ #if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) - | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) + | ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) +#if !(defined(FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) && FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B) + | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect) +#endif /* FSL_FEATURE_LPADC_HAS_NO_TCTRL_FIFO_SEL_B */ #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ ; if (config->enableHardwareTrigger) @@ -324,12 +327,12 @@ void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config) assert(config != NULL); /* Check if the input pointer is available. */ /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); config->targetCommandId = 0U; config->delayPower = 0U; config->priority = 0U; -#if defined(FSL_FEATURE_LPADC_FIFO_COUNT) && FSL_FEATURE_LPADC_FIFO_COUNT +#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) config->channelAFIFOSelect = 0U; config->channelBFIFOSelect = 0U; #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ @@ -378,7 +381,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_ } #endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - tmp32 |= ADC_CMDL_MODE(config->conversionResoultuionMode); + tmp32 |= ADC_CMDL_MODE(config->conversionResolutionMode); #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ base->CMD[commandId].CMDL = tmp32; @@ -433,7 +436,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_ * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; * config->hardwareCompareValueHigh = 0U; * config->hardwareCompareValueLow = 0U; - * config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; * config->enableWaitTrigger = false; * endcode * param config Pointer to configuration structure. @@ -443,7 +446,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) assert(config != NULL); /* Check if the input pointer is available. */ /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE config->sampleScaleMode = kLPADC_SampleFullScale; @@ -459,7 +462,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) config->hardwareCompareValueHigh = 0U; /* No used. */ config->hardwareCompareValueLow = 0U; /* No used. */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard; + config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; #endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ #if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG config->enableWaitTrigger = false; @@ -477,7 +480,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config) * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. * * param base LPADC peripheral base address. - * bool enable switcher to the calibration function. + * param enable switcher to the calibration function. */ void LPADC_EnableCalibration(ADC_Type *base, bool enable) { @@ -539,7 +542,7 @@ void LPADC_DoAutoCalibration(ADC_Type *base) { } /* The valid bits of data are bits 14:3 in the RESFIFO register. */ - LPADC_SetOffsetValue(base, (mLpadcResultConfigStruct.convValue) >> 3U); + LPADC_SetOffsetValue(base, (uint32_t)(mLpadcResultConfigStruct.convValue) >> 3UL); /* Disable the calibration function. */ LPADC_EnableCalibration(base, false); diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h index 4a862f7bb4..d3e5a9ec30 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_lpadc.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,8 +23,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPADC driver version 2.1.1. */ -#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) +/*! @brief LPADC driver version 2.5.1. */ +#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 5, 1)) /*@}*/ /*! @@ -70,6 +70,42 @@ enum _lpadc_interrupt_enable requests when FOF1 flag is asserted. */ kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt requests when RDY1 flag is asserted. */ +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) + kLPADC_TriggerExceptionInterruptEnable = ADC_IE_TEXC_IE_MASK, /*!< Configures ADC to generate trigger exception + interrupt. */ + kLPADC_Trigger0CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 0UL), /*!< Configures ADC to generate interrupt + when trigger 0 completion. */ + kLPADC_Trigger1CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 1UL), /*!< Configures ADC to generate interrupt + when trigger 1 completion. */ + kLPADC_Trigger2CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 2UL), /*!< Configures ADC to generate interrupt + when trigger 2 completion. */ + kLPADC_Trigger3CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 3UL), /*!< Configures ADC to generate interrupt + when trigger 3 completion. */ + kLPADC_Trigger4CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 4UL), /*!< Configures ADC to generate interrupt + when trigger 4 completion. */ + kLPADC_Trigger5CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 5UL), /*!< Configures ADC to generate interrupt + when trigger 5 completion. */ + kLPADC_Trigger6CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 6UL), /*!< Configures ADC to generate interrupt + when trigger 6 completion. */ + kLPADC_Trigger7CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 7UL), /*!< Configures ADC to generate interrupt + when trigger 7 completion. */ + kLPADC_Trigger8CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 8UL), /*!< Configures ADC to generate interrupt + when trigger 8 completion. */ + kLPADC_Trigger9CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 9UL), /*!< Configures ADC to generate interrupt + when trigger 9 completion. */ + kLPADC_Trigger10CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 10UL), /*!< Configures ADC to generate interrupt + when trigger 10 completion. */ + kLPADC_Trigger11CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 11UL), /*!< Configures ADC to generate interrupt + when trigger 11 completion. */ + kLPADC_Trigger12CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 12UL), /*!< Configures ADC to generate interrupt + when trigger 12 completion. */ + kLPADC_Trigger13CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 13UL), /*!< Configures ADC to generate interrupt + when trigger 13 completion. */ + kLPADC_Trigger14CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 14UL), /*!< Configures ADC to generate interrupt + when trigger 14 completion. */ + kLPADC_Trigger15CompletionInterruptEnable = ADC_IE_TCOMP_IE(1UL << 15UL), /*!< Configures ADC to generate interrupt + when trigger 15 completion. */ +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ }; #else /*! @@ -95,6 +131,64 @@ enum _lpadc_interrupt_enable }; #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */ +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +/*! + * @brief The enumerator of lpadc trigger status flags, including interrupted flags and completed flags. + */ +enum _lpadc_trigger_status_flags +{ + kLPADC_Trigger0InterruptedFlag = 1UL << 0UL, /*!< Trigger 0 is interrupted by a high priority exception. */ + kLPADC_Trigger1InterruptedFlag = 1UL << 1UL, /*!< Trigger 1 is interrupted by a high priority exception. */ + kLPADC_Trigger2InterruptedFlag = 1UL << 2UL, /*!< Trigger 2 is interrupted by a high priority exception. */ + kLPADC_Trigger3InterruptedFlag = 1UL << 3UL, /*!< Trigger 3 is interrupted by a high priority exception. */ + kLPADC_Trigger4InterruptedFlag = 1UL << 4UL, /*!< Trigger 4 is interrupted by a high priority exception. */ + kLPADC_Trigger5InterruptedFlag = 1UL << 5UL, /*!< Trigger 5 is interrupted by a high priority exception. */ + kLPADC_Trigger6InterruptedFlag = 1UL << 6UL, /*!< Trigger 6 is interrupted by a high priority exception. */ + kLPADC_Trigger7InterruptedFlag = 1UL << 7UL, /*!< Trigger 7 is interrupted by a high priority exception. */ + kLPADC_Trigger8InterruptedFlag = 1UL << 8UL, /*!< Trigger 8 is interrupted by a high priority exception. */ + kLPADC_Trigger9InterruptedFlag = 1UL << 9UL, /*!< Trigger 9 is interrupted by a high priority exception. */ + kLPADC_Trigger10InterruptedFlag = 1UL << 10UL, /*!< Trigger 10 is interrupted by a high priority exception. */ + kLPADC_Trigger11InterruptedFlag = 1UL << 11UL, /*!< Trigger 11 is interrupted by a high priority exception. */ + kLPADC_Trigger12InterruptedFlag = 1UL << 12UL, /*!< Trigger 12 is interrupted by a high priority exception. */ + kLPADC_Trigger13InterruptedFlag = 1UL << 13UL, /*!< Trigger 13 is interrupted by a high priority exception. */ + kLPADC_Trigger14InterruptedFlag = 1UL << 14UL, /*!< Trigger 14 is interrupted by a high priority exception. */ + kLPADC_Trigger15InterruptedFlag = 1UL << 15UL, /*!< Trigger 15 is interrupted by a high priority exception. */ + + kLPADC_Trigger0CompletedFlag = 1UL << 16UL, /*!< Trigger 0 is completed and + trigger 0 has enabled completion interrupts. */ + kLPADC_Trigger1CompletedFlag = 1UL << 17UL, /*!< Trigger 1 is completed and + trigger 1 has enabled completion interrupts. */ + kLPADC_Trigger2CompletedFlag = 1UL << 18UL, /*!< Trigger 2 is completed and + trigger 2 has enabled completion interrupts. */ + kLPADC_Trigger3CompletedFlag = 1UL << 19UL, /*!< Trigger 3 is completed and + trigger 3 has enabled completion interrupts. */ + kLPADC_Trigger4CompletedFlag = 1UL << 20UL, /*!< Trigger 4 is completed and + trigger 4 has enabled completion interrupts. */ + kLPADC_Trigger5CompletedFlag = 1UL << 21UL, /*!< Trigger 5 is completed and + trigger 5 has enabled completion interrupts. */ + kLPADC_Trigger6CompletedFlag = 1UL << 22UL, /*!< Trigger 6 is completed and + trigger 6 has enabled completion interrupts. */ + kLPADC_Trigger7CompletedFlag = 1UL << 23UL, /*!< Trigger 7 is completed and + trigger 7 has enabled completion interrupts. */ + kLPADC_Trigger8CompletedFlag = 1UL << 24UL, /*!< Trigger 8 is completed and + trigger 8 has enabled completion interrupts. */ + kLPADC_Trigger9CompletedFlag = 1UL << 25UL, /*!< Trigger 9 is completed and + trigger 9 has enabled completion interrupts. */ + kLPADC_Trigger10CompletedFlag = 1UL << 26UL, /*!< Trigger 10 is completed and + trigger 10 has enabled completion interrupts. */ + kLPADC_Trigger11CompletedFlag = 1UL << 27UL, /*!< Trigger 11 is completed and + trigger 11 has enabled completion interrupts. */ + kLPADC_Trigger12CompletedFlag = 1UL << 28UL, /*!< Trigger 12 is completed and + trigger 12 has enabled completion interrupts. */ + kLPADC_Trigger13CompletedFlag = 1UL << 29UL, /*!< Trigger 13 is completed and + trigger 13 has enabled completion interrupts. */ + kLPADC_Trigger14CompletedFlag = 1UL << 30UL, /*!< Trigger 14 is completed and + trigger 14 has enabled completion interrupts. */ + kLPADC_Trigger15CompletedFlag = 1UL << 31UL, /*!< Trigger 15 is completed and + trigger 15 has enabled completion interrupts. */ +}; +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ + /*! * @brief Define enumeration of sample scale mode. * @@ -119,8 +213,8 @@ typedef enum _lpadc_sample_channel_mode kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */ kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF - kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minue side. */ - kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minue side. */ + kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minus side. */ + kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minus side. */ #elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */ kLPADC_SampleChannelDualSingleEndBothSide = @@ -179,11 +273,12 @@ typedef enum _lpadc_hardware_compare_mode kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */ } lpadc_hardware_compare_mode_t; +#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE /*! * @brief Define enumeration of conversion resolution mode. * * Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to - * #_lpadc_sample_channel_mode + * #lpadc_sample_channel_mode_t */ typedef enum _lpadc_conversion_resolution_mode { @@ -192,6 +287,7 @@ typedef enum _lpadc_conversion_resolution_mode kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit conversion with 2’s complement output. */ } lpadc_conversion_resolution_mode_t; +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS /*! @@ -260,7 +356,7 @@ typedef enum _lpadc_trigger_priority_policy } lpadc_trigger_priority_policy_t; /*! - * @beief LPADC global configuration. + * @brief LPADC global configuration. * * This structure would used to keep the settings for initialization. */ @@ -291,8 +387,8 @@ typedef struct lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for conversions.*/ lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */ - lpadc_trigger_priority_policy_t triggerPrioirtyPolicy; /*!< Control how higher priority triggers are handled, see to - #lpadc_trigger_priority_policy_mode_t. */ + lpadc_trigger_priority_policy_t triggerPriorityPolicy; /*!< Control how higher priority triggers are handled, see to + lpadc_trigger_priority_policy_t. */ bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during command execution sequencing between LOOP iterations, between commands in a sequence, and between conversions when command is executing in "Compare Until True" configuration. */ @@ -341,8 +437,8 @@ typedef struct uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */ uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */ #if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE - lpadc_conversion_resolution_mode_t conversionResoultuionMode; /*!< Conversion resolution mode. */ -#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ + lpadc_conversion_resolution_mode_t conversionResolutionMode; /*!< Conversion resolution mode. */ +#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */ #if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be automatically executed; when enabled, the active trigger must be asserted again before @@ -413,7 +509,7 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config); * config->powerUpDelay = 0x80; * config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1; * config->powerLevelMode = kLPADC_PowerLevelAlt1; - * config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately; + * config->triggerPriorityPolicy = kLPADC_TriggerPriorityPreemptImmediately; * config->enableConvPause = false; * config->convPauseDelay = 0U; * config->FIFOWatermark = 0U; @@ -523,6 +619,32 @@ static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) base->STAT = mask; } +#if (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) +/*! + * @brief Get trigger status flags to indicate which trigger sequences have been completed or interrupted by a high + * priority trigger exception. + * + * @param base LPADC peripheral base address. + * @return The OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline uint32_t LPADC_GetTriggerStatusFlags(ADC_Type *base) +{ + return base->TSTAT; +} + +/*! + * @brief Clear trigger status flags. + * + * @param base LPADC peripheral base address. + * @param mask The mask of trigger status flags to be cleared, should be the + * OR'ed value of @ref _lpadc_trigger_status_flags. + */ +static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask) +{ + base->TSTAT = mask; +} +#endif /* FSL_FEATURE_LPADC_HAS_TSTAT */ + /* @} */ /*! @@ -534,7 +656,7 @@ static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask) * @brief Enable interrupts. * * @param base LPADC peripheral base address. - * @mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. + * @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable. */ static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask) { @@ -728,7 +850,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_ * config->hardwareCompareMode = kLPADC_HardwareCompareDisabled; * config->hardwareCompareValueHigh = 0U; * config->hardwareCompareValueLow = 0U; - * config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard; + * config->conversionResolutionMode = kLPADC_ConversionResolutionStandard; * config->enableWaitTrigger = false; * @endcode * @param config Pointer to configuration structure. @@ -746,7 +868,7 @@ void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config); * OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction. * * @param base LPADC peripheral base address. - * @bool enable switcher to the calibration function. + * @param enable switcher to the calibration function. */ void LPADC_EnableCalibration(ADC_Type *base, bool enable); #if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM @@ -800,7 +922,7 @@ static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_ * @brief Enable the offset calibration function. * * @param base LPADC peripheral base address. - * @bool enable switcher to the calibration function. + * @param enable switcher to the calibration function. */ static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable) { @@ -830,6 +952,7 @@ void LPADC_DoOffsetCalibration(ADC_Type *base); void LPADC_DoAutoCalibration(ADC_Type *base); #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */ #endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */ + /* @} */ #if defined(__cplusplus) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h index a73554252d..a55e5ec294 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mailbox.h @@ -1,7 +1,6 @@ /* - * Copyright 2014, NXP * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -30,8 +29,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief MAILBOX driver version 2.1.0. */ -#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @brief MAILBOX driver version 2.2.0. */ +#define FSL_MAILBOX_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*@}*/ /*! @@ -43,13 +42,25 @@ typedef enum _mailbox_cpu_id kMAILBOX_CM33_Core1 = 0, kMAILBOX_CM33_Core0 } mailbox_cpu_id_t; -#else +#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) typedef enum _mailbox_cpu_id { kMAILBOX_CM0Plus = 0, kMAILBOX_CM4 } mailbox_cpu_id_t; #endif + +#if (defined(CPU_NXH2004J640UK48)) +typedef enum _mailbox_id +{ + kMAILBOX_CM0Plus_Core0 = 0, + kMAILBOX_CM0Plus_Core1, + kMAILBOX_CM0Plus_Sw_Irq0, + kMAILBOX_CM0Plus_Sw_Irq1, + kMAILBOX_CM0Plus_Sw_Irq2, + kMAILBOX_CM0Plus_Sw_Irq3 +} mailbox_id_t; +#endif /******************************************************************************* * API ******************************************************************************/ @@ -97,6 +108,8 @@ static inline void MAILBOX_Deinit(MAILBOX_Type *base) /* @} */ +#if ((defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) || \ + (defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) /*! * @brief Set data value in the mailbox based on the CPU ID. * @@ -111,7 +124,7 @@ static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu_id, { #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#else +#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); #endif base->MBOXIRQ[cpu_id].IRQ = mboxData; @@ -130,7 +143,7 @@ static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_cpu_id_t cpu { #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#else +#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); #endif return base->MBOXIRQ[cpu_id].IRQ; @@ -151,7 +164,7 @@ static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_cpu_id_t cpu { #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#else +#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); #endif base->MBOXIRQ[cpu_id].IRQSET = mboxSetBits; @@ -172,12 +185,76 @@ static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_cpu_id_t c { #if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES)) assert((cpu_id == kMAILBOX_CM33_Core0) || (cpu_id == kMAILBOX_CM33_Core1)); -#else +#elif ((defined(LPC54114_cm4_SERIES) || defined(LPC54114_cm0plus_SERIES))) assert((cpu_id == kMAILBOX_CM0Plus) || (cpu_id == kMAILBOX_CM4)); #endif base->MBOXIRQ[cpu_id].IRQCLR = mboxClrBits; } +#elif (defined(CPU_NXH2004J640UK48)) + +/*! + * @brief Set data value in the mailbox based on the Mailbox ID. + * + * @param base MAILBOX peripheral base address. + * @param id Mailbox Index for NXH2004 devices + * @param mboxData Data to send in the mailbox. + * + */ +static inline void MAILBOX_SetValue(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxData) +{ + assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); + base->MBOXIRQ[id].IRQ = mboxData; +} + +/*! + * @brief Get data in the mailbox based on the Mailbox ID. + * + * @param base MAILBOX peripheral base address. + * @param id, Mailbox index for NXH2004 devies. + * + * @return Current mailbox data. + */ +static inline uint32_t MAILBOX_GetValue(MAILBOX_Type *base, mailbox_id_t id) +{ + assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); + return base->MBOXIRQ[id].IRQ; +} + +/*! + * @brief Set data bits in the mailbox based on the Mailbox Index. + * + * @param base MAILBOX peripheral base address. + * @param id Mailbox Index for NXH2004 devices + * @param mboxSetBits Data bits to set in the mailbox. + * + * @note Sets data bits to send via the MAILBOX. A value of 0 will + * do nothing. Only sets bits selected with a 1 in it's bit position. + */ +static inline void MAILBOX_SetValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxSetBits) +{ + assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); + base->MBOXIRQ[id].IRQSET = mboxSetBits; +} + +/*! + * @brief Clear data bits in the mailbox based on the Mailbox ID. + * + * @param base MAILBOX peripheral base address. + * @param id, Index to Mailbox for NXH2004 devices. + * @param mboxClrBits Data bits to clear in the mailbox. + * + * @note Clear data bits to send via the MAILBOX. A value of 0 will do + * nothing. Only clears bits selected with a 1 in it's bit position. + */ +static inline void MAILBOX_ClearValueBits(MAILBOX_Type *base, mailbox_id_t id, uint32_t mboxClrBits) +{ + assert((id >= kMAILBOX_CM0Plus_Core0) && (id <= kMAILBOX_CM0Plus_Sw_Irq3)); + base->MBOXIRQ[id].IRQCLR = mboxClrBits; +} + +#endif /*CPU_NXH2004J640UK48*/ + /*! * @brief Get MUTEX state and lock mutex * diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.c index 8306b33e76..69697a21b5 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2017, 2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -37,10 +37,10 @@ static const clock_ip_name_t s_mrtClocks[] = MRT_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) -#if defined(FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET) && FSL_FEATURE_MRT_WRITE_ZERO_ASSERT_RESET +#if defined(MRT_RSTS_N) /*! @brief Pointers to MRT resets for each instance, writing a zero asserts the reset */ static const reset_ip_name_t s_mrtResets[] = MRT_RSTS_N; -#else +#elif defined(MRT_RSTS) /*! @brief Pointers to MRT resets for each instance, writing a one asserts the reset */ static const reset_ip_name_t s_mrtResets[] = MRT_RSTS; #endif @@ -79,7 +79,7 @@ static uint32_t MRT_GetInstance(MRT_Type *base) */ void MRT_Init(MRT_Type *base, const mrt_config_t *config) { - assert(config); + assert(config != NULL); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Ungate the MRT clock */ @@ -87,8 +87,10 @@ void MRT_Init(MRT_Type *base, const mrt_config_t *config) #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(MRT_RSTS_N) || defined(MRT_RSTS) /* Reset the module. */ RESET_PeripheralReset(s_mrtResets[MRT_GetInstance(base)]); +#endif #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) @@ -136,10 +138,10 @@ void MRT_Deinit(MRT_Type *base) */ void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, bool immediateLoad) { - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); uint32_t newValue = count; - if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == kMRT_OneShotMode) || (immediateLoad)) + if (((base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_MODE_MASK) == (uint8_t)kMRT_OneShotMode) || (immediateLoad)) { /* For one-shot interrupt mode, load the new value immediately even if user forgot to enable */ newValue |= MRT_CHANNEL_INTVAL_LOAD_MASK; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.h index 2e90d01d5f..7829d984e2 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_mrt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2017, 2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,7 +23,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ +#define FSL_MRT_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*!< Version 2.0.3 */ /*@}*/ /*! @brief List of MRT channels */ @@ -112,7 +112,7 @@ void MRT_Deinit(MRT_Type *base); */ static inline void MRT_GetDefaultConfig(mrt_config_t *config) { - assert(config); + assert(config != NULL); #if !(defined(FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) && FSL_FEATURE_MRT_HAS_NO_MODCFG_MULTITASK) /* Use hardware status operating mode */ config->enableMultiTask = false; @@ -128,14 +128,14 @@ static inline void MRT_GetDefaultConfig(mrt_config_t *config) */ static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, const mrt_timer_mode_t mode) { - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); uint32_t reg = base->CHANNEL[channel].CTRL; /* Clear old value */ reg &= ~MRT_CHANNEL_CTRL_MODE_MASK; /* Add the new mode */ - reg |= mode; + reg |= (uint32_t)mode; base->CHANNEL[channel].CTRL = reg; } @@ -157,7 +157,7 @@ static inline void MRT_SetupChannelMode(MRT_Type *base, mrt_chnl_t channel, cons */ static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) { - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); base->CHANNEL[channel].CTRL |= mask; } @@ -171,7 +171,7 @@ static inline void MRT_EnableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint */ static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) { - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); base->CHANNEL[channel].CTRL &= ~mask; } @@ -186,7 +186,7 @@ static inline void MRT_DisableInterrupts(MRT_Type *base, mrt_chnl_t channel, uin */ static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t channel) { - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); return (base->CHANNEL[channel].CTRL & MRT_CHANNEL_CTRL_INTEN_MASK); } @@ -208,7 +208,7 @@ static inline uint32_t MRT_GetEnabledInterrupts(MRT_Type *base, mrt_chnl_t chann */ static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) { - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); return (base->CHANNEL[channel].STAT & (MRT_CHANNEL_STAT_INTFLAG_MASK | MRT_CHANNEL_STAT_RUN_MASK)); } @@ -222,7 +222,7 @@ static inline uint32_t MRT_GetStatusFlags(MRT_Type *base, mrt_chnl_t channel) */ static inline void MRT_ClearStatusFlags(MRT_Type *base, mrt_chnl_t channel, uint32_t mask) { - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); base->CHANNEL[channel].STAT = (mask & MRT_CHANNEL_STAT_INTFLAG_MASK); } @@ -264,7 +264,7 @@ void MRT_UpdateTimerPeriod(MRT_Type *base, mrt_chnl_t channel, uint32_t count, b */ static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t channel) { - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); return base->CHANNEL[channel].TIMER; } @@ -285,12 +285,12 @@ static inline uint32_t MRT_GetCurrentTimerCount(MRT_Type *base, mrt_chnl_t chann * * @param base Multi-Rate timer peripheral base address * @param channel Timer channel number. - * @param count Timer period in units of ticks + * @param count Timer period in units of ticks. Count can contain the LOAD bit, which control the force load feature. */ static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t count) { - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); - assert(count < MRT_CHANNEL_INTVAL_IVALUE_MASK); + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint32_t)(count & ~MRT_CHANNEL_INTVAL_LOAD_MASK) <= (uint32_t)MRT_CHANNEL_INTVAL_IVALUE_MASK); /* Write the timer interval value */ base->CHANNEL[channel].INTVAL = count; } @@ -305,7 +305,7 @@ static inline void MRT_StartTimer(MRT_Type *base, mrt_chnl_t channel, uint32_t c */ static inline void MRT_StopTimer(MRT_Type *base, mrt_chnl_t channel) { - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); /* Stop the timer immediately */ base->CHANNEL[channel].INTVAL = MRT_CHANNEL_INTVAL_LOAD_MASK; } @@ -343,7 +343,7 @@ static inline uint32_t MRT_GetIdleChannel(MRT_Type *base) */ static inline void MRT_ReleaseChannel(MRT_Type *base, mrt_chnl_t channel) { - assert(channel < FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); + assert((uint8_t)channel < (uint8_t)FSL_FEATURE_MRT_NUMBER_OF_CHANNELS); uint32_t reg = base->CHANNEL[channel].STAT; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c index 27c86c005b..c3acfb0e48 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.c @@ -1,5 +1,5 @@ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -31,6 +31,16 @@ typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb); */ static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base); +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) +/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. + * + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ + /******************************************************************************* * Variables ******************************************************************************/ @@ -46,7 +56,11 @@ static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS; #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* OSTIMER ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static ostimer_isr_t s_ostimerIsr = (ostimer_isr_t)DefaultISR; +#else static ostimer_isr_t s_ostimerIsr; +#endif /******************************************************************************* * Code @@ -71,23 +85,75 @@ static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base) return instance; } -/* @brief Translate the value from gray-code to decimal. */ -static uint64_t OSTIMER_GrayToDecimal(uint64_t gray) +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) +/* @brief Translate the value from gray-code to decimal by the Code Gray in SYSCTL. + * + * @param gray The gray value input. + * + * @return the decimal value. + */ +static uint64_t OSTIMER_GrayToDecimalbyCodeGray(uint64_t gray) { + uint64_t decOut; + + SYSCTL->CODE_GRAY_LSB = (uint32_t)(gray & 0xFFFFFFFFU); + SYSCTL->CODE_GRAY_MSB = (uint32_t)((gray >> 32U) & 0x3FFU); // limit to 42bits as OSevent timer + __NOP(); + decOut = ((uint64_t)(SYSCTL->CODE_BIN_MSB) & 0x3FFU) << 32U; + decOut |= (uint64_t)(SYSCTL->CODE_BIN_LSB); + + return decOut; +} +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ + +/* @brief Translate the value from gray-code to decimal. */ +/* + * @param gray The gray value input. + * + * @return the decimal value. + */ +uint64_t OSTIMER_GrayToDecimal(uint64_t gray) +{ +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + return OSTIMER_GrayToDecimalbyCodeGray(gray); +#else uint64_t temp = gray; - while (temp) + while (temp != 0U) { temp >>= 1U; gray ^= temp; } return gray; +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ } -/* @brief Translate the value from decimal to gray-code. */ -static uint64_t OSTIMER_DecimalToGray(uint64_t dec) +/* @brief Enable the OSTIMER interrupt. + * + * After calling this function, the OSTIMER driver will enable/disable the IRQ and module interrupt enablement. + * + * @param base OSTIMER peripheral base address. + * @param enable enable/disable the IRQ and module interrupt enablement. + * - true: Disable the IRQ and module interrupt enablement. + * - false: Disable the IRQ and module interrupt enablement. + * @return none + */ +static void OSTIMER_EnableInterrupt(OSTIMER_Type *base, bool enable) { - return (dec ^ (dec >> 1U)); + assert(NULL != base); + + if (enable) + { + /* Enable the IRQ and module interrupt enablement. */ + (void)EnableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); + base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; + } + else + { + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + (void)DisableIRQ(s_ostimerIRQ[OSTIMER_GetInstance(base)]); + base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; /* Clear interrupt flag by writing 1. */ + } } /*! @@ -96,18 +162,20 @@ static uint64_t OSTIMER_DecimalToGray(uint64_t dec) */ void OSTIMER_Init(OSTIMER_Type *base) { - assert(base); + assert(NULL != base); uint32_t instance = OSTIMER_GetInstance(base); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) #if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) /* Enable the OSTIMER 32k clock in PMC module. */ - PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK; - PMC->OSTIMERr &= ~PMC_OSTIMER_OSC32KPD_MASK; + CLOCK_EnableOstimer32kClock(); #endif /* Enable clock for OSTIMER. */ CLOCK_EnableClock(s_ostimerClock[instance]); +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + CLOCK_EnableClock(kCLOCK_Sysctl); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } @@ -123,6 +191,9 @@ void OSTIMER_Deinit(OSTIMER_Type *base) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable clock for OSTIMER. */ CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]); +#if (defined(FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) && FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY) + CLOCK_DisableClock(kCLOCK_Sysctl); +#endif /* FSL_FEATURE_SYSCTRL_HAS_CODE_GRAY. */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } @@ -147,6 +218,7 @@ uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base) * Currently, only match interrupt flag can be cleared. * * @param base OSTIMER peripheral base address. + * @param mask Clear bit mask. * @return none */ void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) @@ -165,26 +237,62 @@ void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask) * @param count OSTIMER timer match value.(Value is gray-code format) * * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @return none + * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match raw value fail. */ -void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) { - uint64_t tmp = count; - uint32_t instance = OSTIMER_GetInstance(base); +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + uint64_t decValueTimer; +#endif + status_t status; + uint64_t tmp = count; + uint32_t instance = OSTIMER_GetInstance(base); + + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, false); + s_ostimerIsr = OSTIMER_HandleIRQ; s_ostimerHandle[instance] = cb; /* Set the match value. */ - base->MATCHN_L = tmp; - base->MATCHN_H = tmp >> 32U; + base->MATCH_L = (uint32_t)tmp; + base->MATCH_H = (uint32_t)(tmp >> 32U); - /* Enable IRQ for generating call back function. */ - base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; -#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) - PMC->OSTIMERr |= PMC_OSTIMER_DPDWAKEUPENABLE_MASK; -#endif +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + /* Workaround-2019-12-30: + * Since OSTimer's counter register is Gray-encoded, it would cost more time to write register. When EVTimer Match + * Write Ready bit is low, which means the previous match value has been updated successfully by that time, it is + * safe to reload (write) the Match Registers. Even if there is the RM comment that "In typical applications, it + * should not be necessary to test this bit", but we found the interruption would not be reported when the delta + * timer user added is smaller(IE: RT595 11us in 1MHz typical application) in release version." To prevent such + * issue from happening, we'd better wait for the match value to update successfully before enabling IRQ. + */ + while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) + { + } - EnableIRQ(s_ostimerIRQ[instance]); + /* After the WR_RDY bit became low, we need to check whether current time goes ahead of the match value we set. + * (1) If current timer value has gone ahead of the match value, the interrupt will not be reported before 64-bit + * timer value over flow. We need to check whether the interrupt flag has been set or not: if yes, we will enable + * interrupt and return success; if not, we will return fail directly. + * (2) If current timer value has not gone ahead of match value, we will enable interrupt and return success. + */ + decValueTimer = OSTIMER_GetCurrentTimerValue(base); + if ((decValueTimer >= OSTIMER_GrayToDecimal(tmp)) && + (0U == (base->OSEVENT_CTRL & (uint32_t)kOSTIMER_MatchInterruptFlag))) + { + status = kStatus_Fail; + } + else +#endif /* #ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK */ + { + /* Enable the module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, true); + status = kStatus_Success; + } + + return status; } /*! @@ -197,13 +305,14 @@ void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callba * @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in * API. ) * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @return none + * @retval kStatus_Success - Set match value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match value fail. */ -void OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) +status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb) { uint64_t tmp = OSTIMER_DecimalToGray(count); - OSTIMER_SetMatchRawValue(base, tmp, cb); + return OSTIMER_SetMatchRawValue(base, tmp, cb); } /*! @@ -244,23 +353,29 @@ uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base) void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb) { - /* Clear the match interrupt flag. */ - OSTIMER_ClearStatusFlags(base, kOSTIMER_MatchInterruptFlag); + /* Clear interrupt flag, disable the IRQ and module interrupt enablement. */ + OSTIMER_EnableInterrupt(base, false); - if (cb) + if (cb != NULL) { cb(); } } +#if defined(OSTIMER0) +void OS_EVENT_DriverIRQHandler(void); +void OS_EVENT_DriverIRQHandler(void) +{ + s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]); + SDK_ISR_EXIT_BARRIER; +} +#endif + #if defined(OSTIMER) +void OS_EVENT_DriverIRQHandler(void); void OS_EVENT_DriverIRQHandler(void) { s_ostimerIsr(OSTIMER, s_ostimerHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h index b7191c1c2c..c74a793136 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_ostimer.h @@ -1,5 +1,5 @@ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief OSTIMER driver version 2.0.1. */ -#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @brief OSTIMER driver version. */ +#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*@}*/ /*! @@ -67,19 +67,22 @@ void OSTIMER_Init(OSTIMER_Type *base); void OSTIMER_Deinit(OSTIMER_Type *base); /*! - * @brief OSTIMER software reset. + * @brief Translate the value from gray-code to decimal. * - * This function will use software to trigger an OSTIMER reset. - * Please note that, the OS timer reset bit was in PMC->OSTIMERr register. - * - * @param base OSTIMER peripheral base address. + * @param gray The gray value input. + * @return The decimal value. */ -static inline void OSTIMER_SoftwareReset(OSTIMER_Type *base) +uint64_t OSTIMER_GrayToDecimal(uint64_t gray); + +/*! + * @brief Translate the value from decimal to gray-code. + * + * @param dec The decimal value. + * @return The gray code of the input value. + */ +static inline uint64_t OSTIMER_DecimalToGray(uint64_t dec) { -#if !(defined(FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) && FSL_FEATURE_PMC_HAS_NO_OSTIMER_REG) - PMC->OSTIMERr |= PMC_OSTIMER_SOFTRESET_MASK; - PMC->OSTIMERr &= ~PMC_OSTIMER_SOFTRESET_MASK; -#endif + return (dec ^ (dec >> 1U)); } /*! @@ -100,6 +103,7 @@ uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base); * Currently, only match interrupt flag can be cleared. * * @param base OSTIMER peripheral base address. + * @param mask Clear bit mask. * @return none */ void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); @@ -115,9 +119,10 @@ void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask); * @param count OSTIMER timer match value.(Value is gray-code format) * * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @return none + * @retval kStatus_Success - Set match raw value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match raw value fail. */ -void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); +status_t OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); /*! * @brief Set the match value for OSTIMER. @@ -130,9 +135,60 @@ void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callba * internally.) * * @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)). - * @return none + * @retval kStatus_Success - Set match value and enable interrupt Successfully. + * @retval kStatus_Fail - Set match value fail. */ -void OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); +status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb); + +/*! + * @brief Set value to OSTIMER MATCH register directly. + * + * This function writes the input value to OSTIMER MATCH register directly, + * it does not touch any other registers. Note that, the data format is + * gray-code. The function @ref OSTIMER_DecimalToGray could convert decimal + * value to gray code. + * + * @param base OSTIMER peripheral base address. + * @param count OSTIMER timer match value (Value is gray-code format). + */ +static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value) +{ +#ifdef OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK + /* Wait for MATCH register ready for write. */ + while (0U != (base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_MATCH_WR_RDY_MASK)) + { + } +#endif + + base->MATCH_L = (uint32_t)value; + base->MATCH_H = (uint32_t)(value >> 32U); +} + +/*! + * @brief Enable the OSTIMER counter match interrupt. + * + * Enable the timer counter match interrupt. The interrupt happens when OSTIMER + * counter matches the value in MATCH registers. + * + * @param base OSTIMER peripheral base address. + */ +static inline void OSTIMER_EnableMatchInterrupt(OSTIMER_Type *base) +{ + base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; +} + +/*! + * @brief Disable the OSTIMER counter match interrupt. + * + * Disable the timer counter match interrupt. The interrupt happens when OSTIMER + * counter matches the value in MATCH registers. + * + * @param base OSTIMER peripheral base address. + */ +static inline void OSTIMER_DisableMatchInterrupt(OSTIMER_Type *base) +{ + base->OSEVENT_CTRL &= ~OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK; +} /*! * @brief Get current timer raw count value from OSTIMER. @@ -177,8 +233,8 @@ static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base) { uint64_t tmp = 0U; - tmp = base->CAPTUREN_L; - tmp |= (uint64_t)(base->CAPTUREN_H) << 32U; + tmp = base->CAPTURE_L; + tmp |= (uint64_t)(base->CAPTURE_H) << 32U; return tmp; } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.c index e651702a9f..c5557dd030 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -17,21 +17,20 @@ * Variables ******************************************************************************/ -#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) /*! @brief Irq number array */ static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; -/*! @brief Callback function array for PINT(s). */ -static pint_cb_t - s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS + FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; +/*! @brief Callback function array for SECPINT(s). */ +static pint_cb_t s_secpintCallback[FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS]; #else /*! @brief Irq number array */ static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ /*! @brief Callback function array for PINT(s). */ static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; -#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ /******************************************************************************* * Code @@ -49,89 +48,102 @@ static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; void PINT_Init(PINT_Type *base) { uint32_t i; - uint32_t pmcfg; - uint8_t pintcount; - assert(base); - pmcfg = 0; + uint32_t pmcfg = 0; + uint8_t pintcount = 0; + assert(base != NULL); -#if defined(SECPINT) - pintcount = SEC_PINT_PIN_INT_COUNT; -#else - pintcount = PINT_PIN_INT_COUNT; -#endif /* SECPINT */ - - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + if (base == PINT) { - s_pintCallback[i] = NULL; + pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; + /* clear PINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; + /* clear SECPINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_secpintCallback[i] = NULL; + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ } /* Disable all bit slices for pint*/ for (i = 0; i < pintcount; i++) { - pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); + pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); } #if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) + #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the clock. */ CLOCK_EnableClock(kCLOCK_GpioInt); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) /* Reset the module. */ RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) + + if (base == PINT) + { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio0); + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio0); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if defined(SECPINT) + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_Sec); + /* Enable the clock. */ + CLOCK_EnableClock(kCLOCK_Gpio_Sec); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#endif /* SECPINT */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + #else - /* if need config SECURE PINT device,then enable secure pint interrupt clock */ + if (base == PINT) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the clock. */ CLOCK_EnableClock(kCLOCK_Pint); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) /* Reset the module. */ RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ } -#if defined(SECPINT) - else if (base == SECPINT) + else { + /* if need config SECURE PINT device,then enable secure pint interrupt clock */ +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the clock. */ - CLOCK_EnableClock(kCLOCK_Gpio_sec_Int); + CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) /* Reset the module. */ RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ } -#endif /* SECPINT */ #endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ /* Disable all pattern match bit slices */ @@ -152,18 +164,30 @@ void PINT_Init(PINT_Type *base) */ void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enable_t enable, pint_cb_t callback) { - assert(base); + assert(base != NULL); /* Clear Rise and Fall flags first */ PINT_PinInterruptClrRiseFlag(base, intr); PINT_PinInterruptClrFallFlag(base, intr); + /* Security PINT uses additional callback array */ + if (base == PINT) + { + s_pintCallback[intr] = callback; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + s_secpintCallback[intr] = callback; +#endif + } + /* select level or edge sensitive */ - base->ISEL = - (base->ISEL & ~(1UL << (uint32_t)intr)) | ((enable & PINT_PIN_INT_LEVEL) ? (1UL << (uint32_t)intr) : 0U); + base->ISEL = (base->ISEL & ~(1UL << (uint32_t)intr)) | + ((((uint32_t)enable & PINT_PIN_INT_LEVEL) != 0U) ? (1UL << (uint32_t)intr) : 0U); /* enable rising or level interrupt */ - if (enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) + if (((unsigned)enable & (PINT_PIN_INT_LEVEL | PINT_PIN_INT_RISE)) != 0U) { base->SIENR = 1UL << (uint32_t)intr; } @@ -173,7 +197,7 @@ void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enab } /* Enable falling or select high level */ - if (enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) + if (((unsigned)enable & PINT_PIN_INT_FALL_OR_HIGH_LEVEL) != 0U) { base->SIENF = 1UL << (uint32_t)intr; } @@ -181,8 +205,6 @@ void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enab { base->CIENF = 1UL << (uint32_t)intr; } - - s_pintCallback[intr] = callback; } /*! @@ -202,7 +224,7 @@ void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_ uint32_t mask; bool level; - assert(base); + assert(base != NULL); *enable = kPINT_PinIntEnableNone; level = false; @@ -251,7 +273,17 @@ void PINT_PinInterruptGetConfig(PINT_Type *base, pint_pin_int_t pintr, pint_pin_ } } - *callback = s_pintCallback[pintr]; + /* Security PINT uses additional callback array */ + if (base == PINT) + { + *callback = s_pintCallback[pintr]; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + *callback = s_secpintCallback[pintr]; +#endif + } } /*! @@ -273,17 +305,17 @@ void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_ uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - assert(base); + assert(base != NULL); src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); /* Input source selection for selected bit slice */ - base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | (cfg->bs_src << src_shift); + base->PMSRC = (base->PMSRC & ~(tmp_src_shift << src_shift)) | ((uint32_t)(cfg->bs_src) << src_shift); /* Bit slice configuration */ pmcfg = base->PMCFG; - pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | (cfg->bs_cfg << cfg_shift); + pmcfg = (pmcfg & ~(tmp_cfg_shift << cfg_shift)) | ((uint32_t)(cfg->bs_cfg) << cfg_shift); /* If end point is true, enable the bits */ if ((uint32_t)bslice != 7UL) @@ -301,7 +333,22 @@ void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_ base->PMCFG = pmcfg; /* Save callback pointer */ - s_pintCallback[bslice] = cfg->callback; + if (base == PINT) + { + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + s_pintCallback[bslice] = cfg->callback; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + s_secpintCallback[bslice] = cfg->callback; + } +#endif + } } /*! @@ -322,13 +369,13 @@ void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pi uint32_t tmp_src_shift = PININT_BITSLICE_SRC_MASK; uint32_t tmp_cfg_shift = PININT_BITSLICE_CFG_MASK; - assert(base); + assert(base != NULL); src_shift = PININT_BITSLICE_SRC_START + ((uint32_t)bslice * 3UL); cfg_shift = PININT_BITSLICE_CFG_START + ((uint32_t)bslice * 3UL); - cfg->bs_src = (pint_pmatch_input_src_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); - cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); + cfg->bs_src = (pint_pmatch_input_src_t)(uint32_t)((base->PMSRC & (tmp_src_shift << src_shift)) >> src_shift); + cfg->bs_cfg = (pint_pmatch_bslice_cfg_t)(uint32_t)((base->PMCFG & (tmp_cfg_shift << cfg_shift)) >> cfg_shift); if ((uint32_t)bslice == 7U) { @@ -336,9 +383,25 @@ void PINT_PatternMatchGetConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pi } else { - cfg->end_point = ((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice); + cfg->end_point = (((base->PMCFG & (1UL << (uint32_t)bslice)) >> (uint32_t)bslice) != 0U) ? true : false; + } + + if (base == PINT) + { + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + cfg->callback = s_pintCallback[bslice]; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + if ((uint32_t)bslice < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + { + cfg->callback = s_secpintCallback[bslice]; + } +#endif } - cfg->callback = s_pintCallback[bslice]; } /*! @@ -403,10 +466,22 @@ void PINT_PinInterruptClrStatusAll(PINT_Type *base) { uint32_t pinIntMode = 0; uint32_t pinIntStatus = 0; + uint32_t pinIntCount = 0; uint32_t mask = 0; uint32_t i; - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + if (base == PINT) + { + pinIntCount = (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + pinIntCount = (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + + for (i = 0; i < pinIntCount; i++) { pinIntMode = base->ISEL & (1UL << i); pinIntStatus = base->IST & (1UL << i); @@ -435,13 +510,27 @@ void PINT_EnableCallback(PINT_Type *base) { uint32_t i; - assert(base); + assert(base != NULL); - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + if (base == PINT) { - NVIC_ClearPendingIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - (void)EnableIRQ(s_pintIRQ[i]); + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + (void)EnableIRQ(s_pintIRQ[i]); + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + (void)EnableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ } } @@ -457,10 +546,20 @@ void PINT_EnableCallback(PINT_Type *base) */ void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) { - assert(base); + assert(base != NULL); + + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + /* Get the right security pint irq index in array */ + if (base == SECPINT) + { + pintIdx = + (pint_pin_int_t)(uint32_t)((uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); (void)EnableIRQ(s_pintIRQ[pintIdx]); } @@ -478,13 +577,27 @@ void PINT_DisableCallback(PINT_Type *base) { uint32_t i; - assert(base); + assert(base != NULL); - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + if (base == PINT) { - (void)DisableIRQ(s_pintIRQ[i]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); - NVIC_ClearPendingIRQ(s_pintIRQ[i]); + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + (void)DisableIRQ(s_pintIRQ[i]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i]); + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + (void)DisableIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)i); + NVIC_ClearPendingIRQ(s_pintIRQ[i + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ } } @@ -500,11 +613,22 @@ void PINT_DisableCallback(PINT_Type *base) */ void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx) { - assert(base); + assert(base != NULL); - (void)DisableIRQ(s_pintIRQ[pintIdx]); - PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); - NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); + if (base == PINT) + { + (void)DisableIRQ(s_pintIRQ[pintIdx]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + (void)DisableIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); + PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); + NVIC_ClearPendingIRQ(s_pintIRQ[(uint32_t)pintIdx + (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]); +#endif + } } /*! @@ -520,79 +644,99 @@ void PINT_Deinit(PINT_Type *base) { uint32_t i; - assert(base); + assert(base != NULL); /* Cleanup */ PINT_DisableCallback(base); - for (i = 0; i < FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + if (base == PINT) { - s_pintCallback[i] = NULL; + /* clear PINT callback array*/ + for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_pintCallback[i] = NULL; + } + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) + /* clear SECPINT callback array */ + for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++) + { + s_secpintCallback[i] = NULL; + } +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ } #if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) + +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_GpioInt); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) /* Reset the module. */ RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn); #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_GpioInt); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - #elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio0); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - -#if defined(SECPINT) -#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) - /* Reset the module. */ - RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); -#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Enable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_Sec); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -#endif /* SECPINT */ -#else if (base == PINT) { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio0); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + } + else + { +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_Sec); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ + } + +#else + + if (base == PINT) + { +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Pint); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) /* Reset the module. */ RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Pint); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } -#if defined(SECPINT) - else if (base == SECPINT) + else { + /* if need config SECURE PINT device,then enable secure pint interrupt clock */ +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) +#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) + /* Enable the clock. */ + CLOCK_DisableClock(kCLOCK_Gpio_Sec_Int); +#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) /* Reset the module. */ RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn); #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ - -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* Disable the clock. */ - CLOCK_DisableClock(kCLOCK_Gpio_sec_Int); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ } -#endif /* SECPINT */ #endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ } -#if defined(SECPINT) +#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) /* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void); void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) { uint32_t pmstatus = 0; @@ -600,24 +744,21 @@ void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void) /* Reset pattern match detection */ pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); /* Call user function */ - if (s_pintCallback[kPINT_SecPinInt0] != NULL) + if (s_secpintCallback[kPINT_SecPinInt0] != NULL) { - s_pintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); + s_secpintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus); } if ((SECPINT->ISEL & 0x1U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) /* IRQ handler functions overloading weak symbols in the startup */ +void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void); void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) { uint32_t pmstatus; @@ -625,25 +766,22 @@ void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void) /* Reset pattern match detection */ pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT); /* Call user function */ - if (s_pintCallback[kPINT_SecPinInt1] != NULL) + if (s_secpintCallback[kPINT_SecPinInt1] != NULL) { - s_pintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); + s_secpintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus); } if ((SECPINT->ISEL & 0x1U) == 0x0U) { /* Edge sensitive: clear Pin interrupt after callback */ PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ -#endif /* SECPINT */ +#endif /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ /* IRQ handler functions overloading weak symbols in the startup */ +void PIN_INT0_DriverIRQHandler(void); void PIN_INT0_DriverIRQHandler(void) { uint32_t pmstatus; @@ -660,14 +798,11 @@ void PIN_INT0_DriverIRQHandler(void) /* Edge sensitive: clear Pin interrupt after callback */ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +void PIN_INT1_DriverIRQHandler(void); void PIN_INT1_DriverIRQHandler(void) { uint32_t pmstatus; @@ -684,15 +819,12 @@ void PIN_INT1_DriverIRQHandler(void) /* Edge sensitive: clear Pin interrupt after callback */ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) +void PIN_INT2_DriverIRQHandler(void); void PIN_INT2_DriverIRQHandler(void) { uint32_t pmstatus; @@ -709,15 +841,12 @@ void PIN_INT2_DriverIRQHandler(void) /* Edge sensitive: clear Pin interrupt after callback */ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) +void PIN_INT3_DriverIRQHandler(void); void PIN_INT3_DriverIRQHandler(void) { uint32_t pmstatus; @@ -734,15 +863,12 @@ void PIN_INT3_DriverIRQHandler(void) /* Edge sensitive: clear Pin interrupt after callback */ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) +void PIN_INT4_DriverIRQHandler(void); void PIN_INT4_DriverIRQHandler(void) { uint32_t pmstatus; @@ -759,18 +885,16 @@ void PIN_INT4_DriverIRQHandler(void) /* Edge sensitive: clear Pin interrupt after callback */ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) #if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT5_DAC1_IRQHandler(void); void PIN_INT5_DAC1_IRQHandler(void) #else +void PIN_INT5_DriverIRQHandler(void); void PIN_INT5_DriverIRQHandler(void) #endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ { @@ -788,18 +912,16 @@ void PIN_INT5_DriverIRQHandler(void) /* Edge sensitive: clear Pin interrupt after callback */ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) #if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT6_USART3_IRQHandler(void); void PIN_INT6_USART3_IRQHandler(void) #else +void PIN_INT6_DriverIRQHandler(void); void PIN_INT6_DriverIRQHandler(void) #endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ { @@ -817,18 +939,16 @@ void PIN_INT6_DriverIRQHandler(void) /* Edge sensitive: clear Pin interrupt after callback */ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) #if defined(FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER) && FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER +void PIN_INT7_USART4_IRQHandler(void); void PIN_INT7_USART4_IRQHandler(void) #else +void PIN_INT7_DriverIRQHandler(void); void PIN_INT7_DriverIRQHandler(void) #endif /* FSL_FEATURE_NVIC_HAS_SHARED_INTERTTUPT_NUMBER */ { @@ -846,10 +966,6 @@ void PIN_INT7_DriverIRQHandler(void) /* Edge sensitive: clear Pin interrupt after callback */ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7); } -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.h index 074bf23fec..eb7ed612b9 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_pint.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -24,7 +24,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*!< Version 2.1.3 */ +#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) /*!< Version 2.1.9 */ /*@}*/ /* Number of interrupt line supported by PINT */ @@ -38,31 +38,31 @@ /* PININT Bit slice source register bits */ #define PININT_BITSLICE_SRC_START 8U -#define PININT_BITSLICE_SRC_MASK 7U +#define PININT_BITSLICE_SRC_MASK 7U /* PININT Bit slice configuration register bits */ #define PININT_BITSLICE_CFG_START 8U -#define PININT_BITSLICE_CFG_MASK 7U +#define PININT_BITSLICE_CFG_MASK 7U #define PININT_BITSLICE_ENDP_MASK 7U -#define PINT_PIN_INT_LEVEL 0x10U -#define PINT_PIN_INT_EDGE 0x00U +#define PINT_PIN_INT_LEVEL 0x10U +#define PINT_PIN_INT_EDGE 0x00U #define PINT_PIN_INT_FALL_OR_HIGH_LEVEL 0x02U -#define PINT_PIN_INT_RISE 0x01U -#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) -#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) -#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) -#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_INT_RISE 0x01U +#define PINT_PIN_RISE_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE) +#define PINT_PIN_FALL_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_BOTH_EDGE (PINT_PIN_INT_EDGE | PINT_PIN_INT_RISE | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) +#define PINT_PIN_LOW_LEVEL (PINT_PIN_INT_LEVEL) +#define PINT_PIN_HIGH_LEVEL (PINT_PIN_INT_LEVEL | PINT_PIN_INT_FALL_OR_HIGH_LEVEL) /*! @brief PINT Pin Interrupt enable type */ typedef enum _pint_pin_enable { - kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ - kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ - kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ + kPINT_PinIntEnableNone = 0U, /*!< Do not generate Pin Interrupt */ + kPINT_PinIntEnableRiseEdge = PINT_PIN_RISE_EDGE, /*!< Generate Pin Interrupt on rising edge */ + kPINT_PinIntEnableFallEdge = PINT_PIN_FALL_EDGE, /*!< Generate Pin Interrupt on falling edge */ kPINT_PinIntEnableBothEdges = PINT_PIN_BOTH_EDGE, /*!< Generate Pin Interrupt on both edges */ - kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ + kPINT_PinIntEnableLowLevel = PINT_PIN_LOW_LEVEL, /*!< Generate Pin Interrupt on low level */ kPINT_PinIntEnableHighLevel = PINT_PIN_HIGH_LEVEL /*!< Generate Pin Interrupt on high level */ } pint_pin_enable_t; @@ -70,92 +70,94 @@ typedef enum _pint_pin_enable typedef enum _pint_int { kPINT_PinInt0 = 0U, /*!< Pin Interrupt 0 */ -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) kPINT_PinInt1 = 1U, /*!< Pin Interrupt 1 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) kPINT_PinInt2 = 2U, /*!< Pin Interrupt 2 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) kPINT_PinInt3 = 3U, /*!< Pin Interrupt 3 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) kPINT_PinInt4 = 4U, /*!< Pin Interrupt 4 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) kPINT_PinInt5 = 5U, /*!< Pin Interrupt 5 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) kPINT_PinInt6 = 6U, /*!< Pin Interrupt 6 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ #endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kPINT_SecPinInt0 = 8U, /*!< Secure Pin Interrupt 0 */ +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kPINT_SecPinInt0 = 0U, /*!< Secure Pin Interrupt 0 */ #endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kPINT_SecPinInt1 = 9U, /*!< Secure Pin Interrupt 1 */ +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_SecPinInt1 = 1U, /*!< Secure Pin Interrupt 1 */ #endif } pint_pin_int_t; /*! @brief PINT Pattern Match bit slice input source type */ typedef enum _pint_pmatch_input_src { - kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ - kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ - kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ - kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ - kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ - kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ - kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ - kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ + kPINT_PatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_PatternMatchInp1Src = 1U, /*!< Input source 1 */ + kPINT_PatternMatchInp2Src = 2U, /*!< Input source 2 */ + kPINT_PatternMatchInp3Src = 3U, /*!< Input source 3 */ + kPINT_PatternMatchInp4Src = 4U, /*!< Input source 4 */ + kPINT_PatternMatchInp5Src = 5U, /*!< Input source 5 */ + kPINT_PatternMatchInp6Src = 6U, /*!< Input source 6 */ + kPINT_PatternMatchInp7Src = 7U, /*!< Input source 7 */ + kPINT_SecPatternMatchInp0Src = 0U, /*!< Input source 0 */ + kPINT_SecPatternMatchInp1Src = 1U, /*!< Input source 1 */ } pint_pmatch_input_src_t; /*! @brief PINT Pattern Match bit slice type */ typedef enum _pint_pmatch_bslice { kPINT_PatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) kPINT_PatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 2U) kPINT_PatternMatchBSlice2 = 2U, /*!< Bit slice 2 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 3U) kPINT_PatternMatchBSlice3 = 3U, /*!< Bit slice 3 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 4U) kPINT_PatternMatchBSlice4 = 4U, /*!< Bit slice 4 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 5U) kPINT_PatternMatchBSlice5 = 5U, /*!< Bit slice 5 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 6U) kPINT_PatternMatchBSlice6 = 6U, /*!< Bit slice 6 */ #endif -#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) +#if defined(FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ #endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) - kSECPINT_PatternMatchBSlice0 = 8U, /*!< Bit slice 0 */ +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U) + kPINT_SecPatternMatchBSlice0 = 0U, /*!< Bit slice 0 */ #endif -#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) - kSECPINT_PatternMatchBSlice1 = 9U, /*!< Bit slice 1 */ +#if defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U) + kPINT_SecPatternMatchBSlice1 = 1U, /*!< Bit slice 1 */ #endif } pint_pmatch_bslice_t; /*! @brief PINT Pattern Match configuration type */ typedef enum _pint_pmatch_bslice_cfg { - kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ - kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ - kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ + kPINT_PatternMatchAlways = 0U, /*!< Always Contributes to product term match */ + kPINT_PatternMatchStickyRise = 1U, /*!< Sticky Rising edge */ + kPINT_PatternMatchStickyFall = 2U, /*!< Sticky Falling edge */ kPINT_PatternMatchStickyBothEdges = 3U, /*!< Sticky Rising or Falling edge */ - kPINT_PatternMatchHigh = 4U, /*!< High level */ - kPINT_PatternMatchLow = 5U, /*!< Low level */ - kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ - kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ + kPINT_PatternMatchHigh = 4U, /*!< High level */ + kPINT_PatternMatchLow = 5U, /*!< Low level */ + kPINT_PatternMatchNever = 6U, /*!< Never contributes to product term match */ + kPINT_PatternMatchBothEdges = 7U, /*!< Either rising or falling edge */ } pint_pmatch_bslice_cfg_t; /*! @brief PINT Callback function. */ @@ -552,7 +554,7 @@ void PINT_Deinit(PINT_Type *base); * This function enables callback by pin index instead of enabling all pins. * * @param base Base address of the peripheral. - * @param pinIdx pin index. + * @param pintIdx pin index. * * @retval None. */ @@ -564,7 +566,7 @@ void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx); * This function disables callback by pin index instead of disabling all pins. * * @param base Base address of the peripheral. - * @param pinIdx pin index. + * @param pintIdx pin index. * * @retval None. */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.c index 082ed0571b..b50f472675 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -95,3 +95,69 @@ void PLU_Deinit(PLU_Type *base) CLOCK_DisableClock((s_pluClocks[PLU_GetInstance(base)])); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ } + +#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG +/*! + * @brief Gets an available pre-defined settings for wakeup/interrupt control. + * + * This function initializes the initial configuration structure with an available settings. The default values are: + * @code + * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; + * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; + * @endcode + * @param config Pointer to configuration structure. + */ +void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config) +{ + /* Initializes the configure structure to zero. */ + (void)memset(config, 0, sizeof(*config)); + + config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; + config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; +} + +/*! + * @brief Enable PLU outputs wakeup/interrupt request. + * + * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt + * request. + * + * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN + * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint + * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the + * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may + * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is + * generated. + * + * @param base PLU peripheral base address. + * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). + * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) + */ +void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config) +{ + uint32_t tmp32 = 0U; + + tmp32 = PLU_WAKEINT_CTRL_FILTER_MODE(config->filterMode) | PLU_WAKEINT_CTRL_FILTER_CLKSEL(config->clockSource) | + PLU_WAKEINT_CTRL_MASK(interruptMask); + + base->WAKEINT_CTRL = tmp32; +} + +/*! + * @brief Clear the latched interrupt + * + * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() + * + * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. + * + * @param base PLU peripheral base address. + */ +void PLU_ClearLatchedInterrupt(PLU_Type *base) +{ + base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_INTR_CLEAR_MASK; + /* It will take a delay of up to 1.5 PLU_CLKIN clock cycles before this write-to-clear takes effect. */ + while (PLU_WAKEINT_CTRL_INTR_CLEAR_MASK == (base->WAKEINT_CTRL & PLU_WAKEINT_CTRL_INTR_CLEAR_MASK)) + { + } +} +#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.h index e7da779c8c..0c94d49091 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_plu.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -20,7 +20,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */ +#define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1 */ /*@}*/ /*! @brief Index of LUT */ @@ -153,6 +153,46 @@ typedef enum _plu_output_source kPLU_OUT_SRC_FLIPFLOP_3 = 29U /*!< Select Flip-Flops state(3) to be connected to PLU output */ } plu_output_source_t; +#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG + +/*! @brief The enumerator of PLU Interrupt. */ +enum _plu_interrupt_mask +{ + kPLU_OUTPUT_0_INTERRUPT_MASK = 1 << 0, /*!< Select PLU output 0 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_1_INTERRUPT_MASK = 1 << 1, /*!< Select PLU output 1 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_2_INTERRUPT_MASK = 1 << 2, /*!< Select PLU output 2 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_3_INTERRUPT_MASK = 1 << 3, /*!< Select PLU output 3 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_4_INTERRUPT_MASK = 1 << 4, /*!< Select PLU output 4 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_5_INTERRUPT_MASK = 1 << 5, /*!< Select PLU output 5 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_6_INTERRUPT_MASK = 1 << 6, /*!< Select PLU output 6 contribute to interrupt/wake-up generation */ + kPLU_OUTPUT_7_INTERRUPT_MASK = 1 << 7 /*!< Select PLU output 7 contribute to interrupt/wake-up generation */ +}; + +/*! @brief Control input of the PLU, add filtering for glitch. */ +typedef enum _plu_wakeint_filter_mode +{ + kPLU_WAKEINT_FILTER_MODE_BYPASS = 0U, /*!< Select Bypass mode */ + kPLU_WAKEINT_FILTER_MODE_1_CLK_PERIOD = 1U, /*!< Filter 1 clock period */ + kPLU_WAKEINT_FILTER_MODE_2_CLK_PERIOD = 2U, /*!< Filter 2 clock period */ + kPLU_WAKEINT_FILTER_MODE_3_CLK_PERIOD = 3U /*!< Filter 3 clock period */ +} plu_wakeint_filter_mode_t; + +/*! @brief Clock source for filter mode. */ +typedef enum _plu_wakeint_filter_clock_source +{ + kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC = 0U, /*!< Select the 1MHz low-power oscillator as the filter clock */ + kPLU_WAKEINT_FILTER_CLK_SRC_12MHZ_FRO = 1U, /*!< Select the 12MHz FRO as the filer clock */ + kPLU_WAKEINT_FILTER_CLK_SRC_ALT = 2U /*!< Select a third clock source */ +} plu_wakeint_filter_clock_source_t; + +/*! @brief Wake configuration. */ +typedef struct _plu_wakeint_config +{ + plu_wakeint_filter_mode_t filterMode; /*!< Filter Mode. */ + plu_wakeint_filter_clock_source_t clockSource; /*!< The clock source for filter mode. */ +} plu_wakeint_config_t; +#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ + /******************************************************************************* * API ******************************************************************************/ @@ -167,7 +207,7 @@ extern "C" { */ /*! - * @brief Ungates the PLU clock and reset the module. + * @brief Enable the PLU clock and reset the module. * * @note This API should be called at the beginning of the application using the PLU driver. * @@ -205,7 +245,7 @@ static inline void PLU_SetLutInputSource(PLU_Type *base, plu_lut_in_index_t lutInIndex, plu_lut_input_source_t inputSrc) { - PLU->LUT[lutIndex].INP[lutInIndex] = inputSrc; + PLU->LUT[lutIndex].INP_MUX[lutInIndex] = (uint32_t)inputSrc; } /*! @@ -219,7 +259,7 @@ static inline void PLU_SetLutInputSource(PLU_Type *base, */ static inline void PLU_SetOutputSource(PLU_Type *base, plu_output_index_t outputIndex, plu_output_source_t outputSrc) { - base->OUTPUT_MUX[outputIndex] = outputSrc; + base->OUTPUT_MUX[outputIndex] = (uint32_t)outputSrc; } /*! @@ -257,6 +297,74 @@ static inline uint32_t PLU_ReadOutputState(PLU_Type *base) /*! @}*/ +#if defined(FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG) && FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG +/*! + * @name Wake-up/Interrupt Control + * @{ + */ + +/*! + * @brief Gets an available pre-defined settings for wakeup/interrupt control. + * + * This function initializes the initial configuration structure with an available settings. The default values are: + * @code + * config->filterMode = kPLU_WAKEINT_FILTER_MODE_BYPASS; + * config->clockSource = kPLU_WAKEINT_FILTER_CLK_SRC_1MHZ_LPOSC; + * @endcode + * @param config Pointer to configuration structure. + */ +void PLU_GetDefaultWakeIntConfig(plu_wakeint_config_t *config); + +/*! + * @brief Enable PLU outputs wakeup/interrupt request. + * + * This function enables Any of the eight selected PLU outputs to contribute to an asynchronous wake-up or an interrupt + * request. + * + * Note: If a PLU_CLKIN is provided, the raw wake-up/interrupt request will be set on the rising-edge of the PLU_CLKIN + * whenever the raw request signal is high. This registered signal will be glitch-free and just use the default wakeint + * config by PLU_GetDefaultWakeIntConfig(). If not, have to specify the filter mode and clock source to eliminate the + * glitches caused by long and widely disparate delays through the network of LUTs making up the PLU. This way may + * increase power consumption in low-power operating modes and inject delay before the wake-up/interrupt request is + * generated. + * + * @param base PLU peripheral base address. + * @param interruptMask PLU interrupt mask (see @ref _plu_interrupt_mask enumeration). + * @param config Pointer to configuration structure (see @ref plu_wakeint_config_t typedef enumeration) + */ +void PLU_EnableWakeIntRequest(PLU_Type *base, uint32_t interruptMask, const plu_wakeint_config_t *config); + +/*! + * @brief Latch an interrupt + * + * This function latches the interrupt and then it can be cleared with PLU_ClearLatchedInterrupt(). + * + * Note: This mode is not compatible with use of the glitch filter. If this bit is set, the FILTER MODE should be set + * to kPLU_WAKEINT_FILTER_MODE_BYPASS (Bypass Mode) and PLU_CLKIN should be provided. If this bit is set, the + * wake-up/interrupt request will be set on the rising-edge of PLU_CLKIN whenever the raw wake-up/interrupt signal is + * high. The request must be cleared by software. + * + * @param base PLU peripheral base address. + */ +static inline void PLU_LatchInterrupt(PLU_Type *base) +{ + base->WAKEINT_CTRL |= PLU_WAKEINT_CTRL_LATCH_ENABLE_MASK; +} + +/*! + * @brief Clear the latched interrupt + * + * This function clears the wake-up/interrupt request flag latched by PLU_LatchInterrupt() + * + * Note: It is not necessary for the PLU bus clock to be enabled in order to write-to or read-back this bit. + * + * @param base PLU peripheral base address. + */ +void PLU_ClearLatchedInterrupt(PLU_Type *base); + +/*! @}*/ +#endif /* FSL_FEATURE_PLU_HAS_WAKEINT_CTRL_REG */ + #if defined(__cplusplus) } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.c index a0b8331753..f520454383 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.c @@ -13,7 +13,1819 @@ #endif /******************************************************************************* - * Code + * Variables ******************************************************************************/ -/* Empty file since implementation is in header file and power library */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +/** @brief Low Power main structure */ +typedef enum +{ + VD_AON = 0x0, /*!< Digital Always On power domain */ + VD_MEM = 0x1, /*!< Memories (SRAM) power domain */ + VD_DCDC = 0x2, /*!< Core logic power domain */ + VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */ +} LPC_POWER_DOMAIN_T; + +/** + * @brief LDO_FLASH_NV & LDO_USB voltage settings + */ +typedef enum _v_flashnv +{ + V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */ + V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */ + V_LDOFLASHNV_1P750 = 2, /*!< 1 V */ + V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */ + V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */ + V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */ + V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */ + V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */ +} v_flashnv_t; + +/** @brief Low Power main structure */ +typedef struct +{ /* */ + __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ + __IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules + in the different Low power modes, including ROM */ + __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances + in the different Low power modes */ + __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */ + __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */ + __IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */ + __IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */ + __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes + in case an interrupt is pending when the processor request deepsleep */ + __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */ + __IO uint32_t TIMERCFG; /*!< Wake up timers configuration */ + __IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/ + __IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some + interrupt handlers)*/ +} LPC_LOWPOWER_T; + +/* */ +#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBAUL /*!< */ + +/** + * @brief SRAM Low Power Modes + */ +#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL) +#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */ +#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */ +#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */ +#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */ +#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */ + +/** + * @brief Wake up timers configuration in Low Power Modes + */ +#define LOWPOWER_TIMERCFG_CTRL_INDEX 0 +#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX) +#define LOWPOWER_TIMERCFG_TIMER_INDEX 1 +#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX) +#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4 +#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX) + +#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */ +#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */ + +/** + * @brief Primary Wake up timers configuration in Low Power Modes + */ +#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */ +#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */ +#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */ + +#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */ +#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */ + +//! @brief Interface for lowpower functions +typedef struct LowpowerDriverInterface +{ + void (*power_cycle_cpu_and_flash)(void); + void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg); +} lowpower_driver_interface_t; + +/**< DCDC Power Profiles */ +typedef enum +{ + DCDC_POWER_PROFILE_LOW, /**< LOW (for CPU frequencies below DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) */ + DCDC_POWER_PROFILE_MEDIUM, /**< MEDIUM (for CPU frequencies between DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ and + DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) */ + DCDC_POWER_PROFILE_HIGH, /**< HIGH (for CPU frequencies between DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ and + DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ) */ +} lowpower_dcdc_power_profile_enum; + +/**< Manufacturing Process Corners */ +typedef enum +{ + PROCESS_CORNER_SSS, /**< Slow Corner Process */ + PROCESS_CORNER_NNN, /**< Nominal Corner Process */ + PROCESS_CORNER_FFF, /**< Fast Corner Process */ + PROCESS_CORNER_OTHERS, /**< SFN, SNF, NFS, Poly Res ... Corner Process */ +} lowpower_process_corner_enum; + +/** + * @brief DCDC voltage settings + */ +typedef enum _v_dcdc +{ + V_DCDC_0P950 = 0, /*!< 0.95 V */ + V_DCDC_0P975 = 1, /*!< 0.975 V */ + V_DCDC_1P000 = 2, /*!< 1 V */ + V_DCDC_1P025 = 3, /*!< 1.025 V */ + V_DCDC_1P050 = 4, /*!< 1.050 V */ + V_DCDC_1P075 = 5, /*!< 1.075 V */ + V_DCDC_1P100 = 6, /*!< 1.1 V */ + V_DCDC_1P125 = 7, /*!< 1.125 V */ + V_DCDC_1P150 = 8, /*!< 1.150 V */ + V_DCDC_1P175 = 9, /*!< 1.175 V */ + V_DCDC_1P200 = 10 /*!< 1.2 V */ +} v_dcdc_t; + +/** + * @brief Deep Sleep LDO voltage settings + */ +typedef enum _v_deepsleep +{ + V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */ + V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */ + V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */ + V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */ + V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */ + V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */ + V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */ + V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */ +} v_deepsleep_t; + +/** + * @brief Always On and Memories LDO voltage settings + */ +typedef enum _v_ao +{ + V_AO_0P700 = 1, /*!< 0.7 V */ + V_AO_0P725 = 2, /*!< 0.725 V */ + V_AO_0P750 = 3, /*!< 0.75 V */ + V_AO_0P775 = 4, /*!< 0.775 V */ + V_AO_0P800 = 5, /*!< 0.8 V */ + V_AO_0P825 = 6, /*!< 0.825 V */ + V_AO_0P850 = 7, /*!< 0.85 V */ + V_AO_0P875 = 8, /*!< 0.875 V */ + V_AO_0P900 = 9, /*!< 0.9 V */ + V_AO_0P960 = 10, /*!< 0.96 V */ + V_AO_0P970 = 11, /*!< 0.97 V */ + V_AO_0P980 = 12, /*!< 0.98 V */ + V_AO_0P990 = 13, /*!< 0.99 V */ + V_AO_1P000 = 14, /*!< 1 V */ + V_AO_1P010 = 15, /*!< 1.01 V */ + V_AO_1P020 = 16, /*!< 1.02 V */ + V_AO_1P030 = 17, /*!< 1.03 V */ + V_AO_1P040 = 18, /*!< 1.04 V */ + V_AO_1P050 = 19, /*!< 1.05 V */ + V_AO_1P060 = 20, /*!< 1.06 V */ + V_AO_1P070 = 21, /*!< 1.07 V */ + V_AO_1P080 = 22, /*!< 1.08 V */ + V_AO_1P090 = 23, /*!< 1.09 V */ + V_AO_1P100 = 24, /*!< 1.1 V */ + V_AO_1P110 = 25, /*!< 1.11 V */ + V_AO_1P120 = 26, /*!< 1.12 V */ + V_AO_1P130 = 27, /*!< 1.13 V */ + V_AO_1P140 = 28, /*!< 1.14 V */ + V_AO_1P150 = 29, /*!< 1.15 V */ + V_AO_1P160 = 30, /*!< 1.16 V */ + V_AO_1P220 = 31 /*!< 1.22 V */ +} v_ao_t; + +/* Low Power modes */ +#define LOWPOWER_CFG_LPMODE_INDEX 0 +#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX) +#define LOWPOWER_CFG_SELCLOCK_INDEX 2 +#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX) +#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3 +#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX) +#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4 +#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX) +#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5 +#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX) + +#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */ +#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */ +#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */ +#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */ +#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */ + +#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */ +#define LOWPOWER_CFG_SELCLOCK_12MHZ \ + 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/ + +#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */ +#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP \ + 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */ + +#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING \ + 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high \ + as possible -- 1.1V typical -- during low power mode) */ +#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING \ + 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low \ + as possible -- down to 0.7V -- during low power mode) */ + +#define LOWPOWER_CFG_LDODEEPSLEEPREF_FLASHBUFFER 0 /*!< LDO DEEP SLEEP uses Flash Buffer as reference */ +#define LOWPOWER_CFG_LDODEEPSLEEPREF_BANDGAG0P8V 1 /*!< LDO DEEP SLEEP uses Band Gap 0.8V as reference */ + +/* CPU Retention Control*/ +#define LOWPOWER_CPURETCTRL_ENA_INDEX 0 +#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX) +#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1 +#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFFUL << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) +#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14 +#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX) + +/* Voltgae setting*/ +#define DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ \ + (100000000U) /* Maximum System Frequency allowed with DCDC Power Profile LOW */ +#define DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ \ + (130000000U) /* Maximum System Frequency allowed with DCDC Power Profile MEDIUM */ +#define DCDC_POWER_PROFILE_HIGH_MAX_FREQ_HZ \ + (150000000U) /* Maximum System Frequency allowed with DCDC Power Profile HIGH */ +#define PROCESS_NNN_AVG_HZ (19300000U) /* Average Ring OScillator value for Nominal (NNN) Manufacturing Process */ +#define PROCESS_NNN_STD_HZ \ + (400000U) /* Standard Deviation Ring OScillator value for Nominal (NNN) Manufacturing Process */ +#define PROCESS_NNN_LIMITS \ + (6U) /* Nominal (NNN) Manufacturing Process Ring Oscillator values limit (with respect to the Average value) */ +#define PROCESS_NNN_MIN_HZ \ + (PROCESS_NNN_AVG_HZ - \ + (PROCESS_NNN_LIMITS * \ + PROCESS_NNN_STD_HZ)) /* Minimum Ring OScillator value for Nominal (NNN) Manufacturing Process */ +#define PROCESS_NNN_MAX_HZ \ + (PROCESS_NNN_AVG_HZ + \ + (PROCESS_NNN_LIMITS * \ + PROCESS_NNN_STD_HZ)) /* Maximum Ring OScillator value for Nominal (NNN) Manufacturing Process */ +#define VOLTAGE_SSS_LOW_MV (1075U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=LOW */ +#define VOLTAGE_SSS_MED_MV (1150U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=MEDIUM */ +#define VOLTAGE_SSS_HIG_MV (1200U) /* Voltage Settings for : Process=SSS, DCDC Power Profile=HIGH */ +#define VOLTAGE_NNN_LOW_MV (1000U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=LOW */ +#define VOLTAGE_NNN_MED_MV (1100U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=MEDIUM */ +#define VOLTAGE_NNN_HIG_MV (1150U) /* Voltage Settings for : Process=NNN, DCDC Power Profile=HIGH */ +#define VOLTAGE_FFF_LOW_MV (1000U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=LOW */ +#define VOLTAGE_FFF_MED_MV (1025U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=MEDIUM */ +#define VOLTAGE_FFF_HIG_MV (1050U) /* Voltage Settings for : Process=FFF, DCDC Power Profile=HIGH */ + +/** + * @brief LDO Voltage control in Low Power Modes + */ +#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 +#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) +#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5 +#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) +#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10 +#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) +#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19 +#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) +#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24 +#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) +#define LOWPOWER_VOLTAGE_DCDC_INDEX 29 +#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX) + +/*! @brief set and clear bit MACRO's. */ +#define U32_SET_BITS(P, B) ((*(uint32_t *)P) |= (B)) +#define U32_CLR_BITS(P, B) ((*(uint32_t *)P) &= ~(B)) +/* Return values from Config (N-2) page of flash */ +#define GET_16MXO_TRIM() (*(uint32_t *)0x9FCC8) +#define GET_32KXO_TRIM() (*(uint32_t *)0x9FCCC) + +#define CPU_RETENTION_RAMX_STORAGE_START_ADDR (0x04006000) + +#define XO_SLAVE_EN (1) +/******************************************************************************* + * Codes + ******************************************************************************/ + +/******************************************************************************* + * LOCAL FUNCTIONS PROTOTYPES + ******************************************************************************/ +static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage); +static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage); +static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl); +static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity); + +static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile); +static lowpower_process_corner_enum lowpower_get_part_process_corner(void); +static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile); + +/** + * @brief Configures and enters in low power mode + * @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters + * @return Nothing + * + * !!! IMPORTANT NOTES : + * 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the + * API. + * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk + * of Dead Lock). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + * reset) + */ +static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg); + +/** + * @brief + * @param + * @return + */ +static void lf_set_dcdc_power_profile_low(void) +{ +#define DCDC_POWER_PROFILE_LOW_0_ADDRS (0x9FCE0U) +#define DCDC_POWER_PROFILE_LOW_1_ADDRS (0x9FCE4U) + + uint32_t dcdcTrimValue0 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_0_ADDRS))); + uint32_t dcdcTrimValue1 = (*((volatile unsigned int *)(DCDC_POWER_PROFILE_LOW_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + PMC->DCDC0 = dcdcTrimValue0 >> 1; + PMC->DCDC1 = dcdcTrimValue1; + } +} + +/** + * @brief Configures and enters in low power mode + * @param : p_lowpower_cfg + * @return Nothing + */ +static void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg) +{ + lowpower_driver_interface_t *s_lowpowerDriver; + /* Judging the core and call the corresponding API base address*/ + if (0UL == Chip_GetVersion()) + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL); + } + else + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL); + } + /* PMC clk set to 12 MHZ */ + p_lowpower_cfg->CFG |= (uint32_t)LOWPOWER_CFG_SELCLOCK_12MHZ << LOWPOWER_CFG_SELCLOCK_INDEX; + + /* Enable Analog References fast wake-up in case of wake-up from a low power mode (DEEP SLEEP, POWER DOWN and DEEP + * POWER DOWN) and Hardware Pin reset */ + PMC->REFFASTWKUP = (PMC->REFFASTWKUP & (~PMC_REFFASTWKUP_LPWKUP_MASK) & (~PMC_REFFASTWKUP_HWWKUP_MASK)) | + PMC_REFFASTWKUP_LPWKUP(1) | PMC_REFFASTWKUP_HWWKUP(1); + + /* SRAM uses Voltage Scaling in all Low Power modes */ + PMC->SRAMCTRL = (PMC->SRAMCTRL & (~PMC_SRAMCTRL_SMB_MASK)) | PMC_SRAMCTRL_SMB(3); + + /* CPU Retention configuration : preserve the value of FUNCRETENTIONCTRL.RET_LENTH which is a Hardware defined + * parameter. */ + p_lowpower_cfg->CPURETCTRL = (SYSCON->FUNCRETENTIONCTRL & SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK) | + (p_lowpower_cfg->CPURETCTRL & (~SYSCON_FUNCRETENTIONCTRL_RET_LENTH_MASK)); + + /* Switch System Clock to FRO12Mhz (the configuration before calling this function will not be restored back) */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* Switch main clock to FRO12MHz */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /* Main clock divided by 1 */ + SYSCON->FMCCR = (SYSCON->FMCCR & 0xFFFF0000UL) | 0x201AUL; /* Adjust FMC waiting time cycles */ + lf_set_dcdc_power_profile_low(); /* Align DCDC Power profile with the 12 MHz clock (DCDC Power Profile LOW) */ + + (*(s_lowpowerDriver->set_lowpower_mode))(p_lowpower_cfg); + + /* Restore the configuration of the MISCCTRL Register : LOWPWR_FLASH_BUF = 0, LDOMEMBLEEDDSLP = 0, LDOMEMHIGHZMODE = + * 0 */ + PMC->MISCCTRL &= (~PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK) & (~PMC_MISCCTRL_DISABLE_BLEED_MASK) & + (~PMC_MISCCTRL_LDOMEMHIGHZMODE_MASK); +} + +/** + * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event + * @param None + * @return Nothing + */ +void POWER_CycleCpuAndFlash(void) +{ + /* Judging the core and call the corresponding API base address*/ + lowpower_driver_interface_t *s_lowpowerDriver; + if (0UL == Chip_GetVersion()) + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x130010d4UL); + } + else + { + s_lowpowerDriver = (lowpower_driver_interface_t *)(0x13001204UL); + } + (*(s_lowpowerDriver->power_cycle_cpu_and_flash))(); +}; + +/** + * brief PMC Deep Sleep function call + * return nothing + */ +void POWER_EnterDeepSleep(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t hardware_wake_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint32_t dcdc_voltage; + uint32_t pmc_reset_ctrl; + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPSLEEP + << LOWPOWER_CFG_LPMODE_INDEX; /* DEEPSLEEP mode */ + + lf_get_deepsleep_core_supply_cfg(exclude_from_pd, &dcdc_voltage); + + if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && + ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) + { + /* USB High Speed is required as wake-up source in Deep Sleep mode: make sure LDO FLASH NV stays powered during + * deep-sleep */ + exclude_from_pd = exclude_from_pd | (uint32_t)kPDRUNCFG_PD_LDOFLASHNV; + } + + /* DCDC will be always used during Deep Sleep (instead of LDO Deep Sleep); Make sure LDO MEM & Analog references + * will stay powered, Shut down ROM */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd & ~(uint32_t)kPDRUNCFG_PD_DCDC & ~(uint32_t)kPDRUNCFG_PD_LDOMEM & + ~(uint32_t)kPDRUNCFG_PD_BIAS) | + (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP | (uint32_t)kPDRUNCFG_PD_ROM; + + /* Voltage control in DeepSleep Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, dcdc_voltage); + + /* SRAM retention control during POWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* CPU Wake up & Interrupt sources control */ + lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts; + lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts; + + /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */ + if (0UL != (hardware_wake_ctrl & (LOWPOWER_HWWAKE_PERIPHERALS | LOWPOWER_HWWAKE_SDMA0 | LOWPOWER_HWWAKE_SDMA1))) + { + lv_low_power_mode_cfg.HWWAKE = (hardware_wake_ctrl & ~LOWPOWER_HWWAKE_FORCED) | LOWPOWER_HWWAKE_ENABLE_FRO192M; + } + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power + * API */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + pmc_reset_ctrl = PMC->RESETCTRL; + if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODCORERESETENABLE_MASK)) + { + /* BoD CORE reset is activated, so make sure BoD Core won't be shutdown */ + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODCORE; + } + if (0UL != (pmc_reset_ctrl & PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) + { + /* BoD VBAT reset is activated, so make sure BoD VBAT won't be shutdown */ + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_BODVBAT; + } + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the + * low power API */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; +} + +/** + * brief PMC power Down function call + * return nothing + */ +void POWER_EnterPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t cpu_retention_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint64_t wakeup_src_int; + uint32_t pmc_reset_ctrl; + + uint32_t analog_ctrl_regs[12]; /* To store Analog Controller Regristers */ + + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_POWERDOWN + << LOWPOWER_CFG_LPMODE_INDEX; /* POWER DOWN mode */ + + /* Only FRO32K, XTAL32K, COMP, BIAS and LDO_MEM can be stay powered during POWERDOWN (valid from application point + * of view; Hardware allows BODVBAT, LDODEEPSLEEP and FRO1M to stay powered, that's why they are excluded below) */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BODVBAT | (uint32_t)kPDRUNCFG_PD_FRO1M | + (uint32_t)kPDRUNCFG_PD_LDODEEPSLEEP; + + /* SRAM retention control during POWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ + if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) + { + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; + } + + /* Voltage control in Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_POWERDOWN, 0); + + /* CPU0 retention Ctrl. + * For the time being, we do not allow customer to relocate the CPU retention area in SRAMX, meaning that the + * retention area range is [0x0400_6000 - 0x0400_6600] (beginning of RAMX2) If required by customer, + * cpu_retention_ctrl[13:1] will be used for that to modify the default retention area + */ + lv_low_power_mode_cfg.CPURETCTRL = + (cpu_retention_ctrl & LOWPOWER_CPURETCTRL_ENA_MASK) | + ((((uint32_t)CPU_RETENTION_RAMX_STORAGE_START_ADDR >> 2UL) << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) & + LOWPOWER_CPURETCTRL_MEMBASE_MASK); + if (0UL != (cpu_retention_ctrl & 0x1UL)) + { + /* CPU retention is required: store Analog Controller Registers */ + analog_ctrl_regs[0] = ANACTRL->FRO192M_CTRL; + analog_ctrl_regs[1] = ANACTRL->ANALOG_CTRL_CFG; + analog_ctrl_regs[2] = ANACTRL->ADC_CTRL; + analog_ctrl_regs[3] = ANACTRL->XO32M_CTRL; + analog_ctrl_regs[4] = ANACTRL->BOD_DCDC_INT_CTRL; + analog_ctrl_regs[5] = ANACTRL->RINGO0_CTRL; + analog_ctrl_regs[6] = ANACTRL->RINGO1_CTRL; + analog_ctrl_regs[7] = ANACTRL->RINGO2_CTRL; + analog_ctrl_regs[8] = ANACTRL->LDO_XO32M; + analog_ctrl_regs[9] = ANACTRL->AUX_BIAS; + analog_ctrl_regs[10] = ANACTRL->USBHS_PHY_CTRL; + analog_ctrl_regs[11] = ANACTRL->USBHS_PHY_TRIM; + } + + /* CPU Wake up & Interrupt sources control : only WAKEUP_GPIO_GLOBALINT0, WAKEUP_GPIO_GLOBALINT1, WAKEUP_FLEXCOMM3, + * WAKEUP_ACMP_CAPT, WAKEUP_RTC_LITE_ALARM_WAKEUP, WAKEUP_OS_EVENT_TIMER, WAKEUP_ALLWAKEUPIOS */ + wakeup_src_int = (uint64_t)(WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP_CAPT | + WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | WAKEUP_ALLWAKEUPIOS); + lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts & wakeup_src_int; + lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts & wakeup_src_int; + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power + * API */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + pmc_reset_ctrl = PMC->RESETCTRL; + /* Disable BoD VBAT and BoD Core resets */ + PMC->RESETCTRL = + pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK)); + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /*** We'll reach this point in case of POWERDOWN with CPU retention or if the POWERDOWN has not been taken (for + instance because an interrupt is pending). In case of CPU retention, assumption is that the SRAM containing the + stack used to call this function shall be preserved during low power ***/ + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore PMC RESETCTRL register */ + PMC->RESETCTRL = pmc_reset_ctrl; + + /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the + * low power API */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; + + if (0UL != (cpu_retention_ctrl & 0x1UL)) + { + /* Restore Analog Controller Registers */ + ANACTRL->FRO192M_CTRL = analog_ctrl_regs[0] | ANACTRL_FRO192M_CTRL_WRTRIM_MASK; + ANACTRL->ANALOG_CTRL_CFG = analog_ctrl_regs[1]; + ANACTRL->ADC_CTRL = analog_ctrl_regs[2]; + ANACTRL->XO32M_CTRL = analog_ctrl_regs[3]; + ANACTRL->BOD_DCDC_INT_CTRL = analog_ctrl_regs[4]; + ANACTRL->RINGO0_CTRL = analog_ctrl_regs[5]; + ANACTRL->RINGO1_CTRL = analog_ctrl_regs[6]; + ANACTRL->RINGO2_CTRL = analog_ctrl_regs[7]; + ANACTRL->LDO_XO32M = analog_ctrl_regs[8]; + ANACTRL->AUX_BIAS = analog_ctrl_regs[9]; + ANACTRL->USBHS_PHY_CTRL = analog_ctrl_regs[10]; + ANACTRL->USBHS_PHY_TRIM = analog_ctrl_regs[11]; + } +} + +/** + * brief PMC Deep Sleep Power Down function call + * return nothing + */ +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t wakeup_io_ctrl) +{ + LPC_LOWPOWER_T lv_low_power_mode_cfg; /* Low Power Mode configuration structure */ + uint32_t cpu0_nmi_enable; + uint32_t cpu0_int_enable_0; + uint32_t cpu0_int_enable_1; + uint32_t pmc_reset_ctrl; + + /* Clear Low Power Mode configuration variable */ + (void)memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T)); + + /* Configure Low Power Mode configuration variable */ + lv_low_power_mode_cfg.CFG |= (uint32_t)LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN + << LOWPOWER_CFG_LPMODE_INDEX; /* DEEP POWER DOWN mode */ + + /* Only FRO32K, XTAL32K and LDO_MEM can be stay powered during DEEPPOWERDOWN (valid from application point of view; + * Hardware allows BODVBAT, BIAS FRO1M and COMP to stay powered, that's why they are excluded below) */ + lv_low_power_mode_cfg.PDCTRL0 = (~exclude_from_pd) | (uint32_t)kPDRUNCFG_PD_BIAS | (uint32_t)kPDRUNCFG_PD_BODVBAT | + (uint32_t)kPDRUNCFG_PD_FRO1M | (uint32_t)kPDRUNCFG_PD_COMP; + + /* SRAM retention control during DEEPPOWERDOWN */ + sram_retention_ctrl = + sram_retention_ctrl & + (~(LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 | LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 | LOWPOWER_SRAMRETCTRL_RETEN_RAM00)); + + /* SRAM retention control during DEEPPOWERDOWN */ + lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl; + + /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ + if ((sram_retention_ctrl & 0x7FFFUL) != 0UL) + { + lv_low_power_mode_cfg.PDCTRL0 &= ~(uint32_t)kPDRUNCFG_PD_LDOMEM; + } + + /* Voltage control in Low Power Modes */ + /* The Memories Voltage settings below are for voltage scaling */ + lv_low_power_mode_cfg.VOLTAGE = lf_set_ldo_ao_ldo_mem_voltage(LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN, 0); + + lv_low_power_mode_cfg.WAKEUPINT = + wakeup_interrupts & (WAKEUP_RTC_LITE_ALARM_WAKEUP | + WAKEUP_OS_EVENT_TIMER); /* CPU Wake up sources control : only WAKEUP_RTC_LITE_ALARM_WAKEUP, + WAKEUP_OS_EVENT_TIMER */ + lv_low_power_mode_cfg.WAKEUPSRC = + wakeup_interrupts & + (WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | + WAKEUP_ALLWAKEUPIOS); /*!< Hardware Wake up sources control: : only WAKEUP_RTC_LITE_ALARM_WAKEUP, + WAKEUP_OS_EVENT_TIMER and WAKEUP_ALLWAKEUPIOS */ + + /* Wake up I/O sources */ + lv_low_power_mode_cfg.WAKEUPIOSRC = lf_wakeup_io_ctrl(wakeup_io_ctrl); + + cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; /* Save the configuration of the NMI Register */ + SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK; /* Disable NMI of CPU0 */ + + /* Save the configuration of the CPU interrupt enable Registers */ + cpu0_int_enable_0 = NVIC->ISER[0]; + cpu0_int_enable_1 = NVIC->ISER[1]; + + /* Save the configuration of the PMC RESETCTRL register */ + pmc_reset_ctrl = PMC->RESETCTRL; + /* Disable BoD VBAT and BoD Core resets */ + PMC->RESETCTRL = + pmc_reset_ctrl & (~(PMC_RESETCTRL_BODVBATRESETENABLE_MASK | PMC_RESETCTRL_BODCORERESETENABLE_MASK)); + + /* Disable LDO MEM bleed current */ + // PMC->MISCCTRL |= PMC_MISCCTRL_DISABLE_BLEED_MASK; + + /* Enter low power mode */ + POWER_EnterLowPower(&lv_low_power_mode_cfg); + + /* Restore the configuration of the NMI Register */ + SYSCON->NMISRC |= cpu0_nmi_enable; + + /* Restore PMC RESETCTRL register */ + PMC->RESETCTRL = pmc_reset_ctrl; + + /* Restore the configuration of the CPU interrupt enable Registers */ + NVIC->ISER[0] = cpu0_int_enable_0; + NVIC->ISER[1] = cpu0_int_enable_1; +} + +/** + * brief PMC Sleep function call + * return nothing + */ +void POWER_EnterSleep(void) +{ + uint32_t pmsk; + pmsk = __get_PRIMASK(); + __disable_irq(); + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + __WFI(); + __set_PRIMASK(pmsk); +} + +/** + * @brief Get Digital Core logic supply source to be used during Deep Sleep. + * @param [in] exclude_from_pd: COmpoenents NOT to be powered down during Deep Sleep + * @param [out] core_supply: 0 = LDO DEEPSLEEP will be used / 1 = DCDC will be used + * @param [out] dcdc_voltage: as defined by V_DCDC_* in fsl_power.h + + * @return Nothing + */ +static void lf_get_deepsleep_core_supply_cfg(uint32_t exclude_from_pd, uint32_t *dcdc_voltage) +{ + *dcdc_voltage = (uint32_t)V_DCDC_0P950; /* Default value */ + + if (((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_USB1_PHY) != 0UL) && + ((exclude_from_pd & (uint32_t)kPDRUNCFG_PD_LDOUSBHS) != 0UL)) + { + /* USB High Speed is required as wake-up source in Deep Sleep mode */ + PMC->MISCCTRL |= PMC_MISCCTRL_LOWPWR_FLASH_BUF_MASK; /* Force flash buffer in low power mode */ + *dcdc_voltage = + (uint32_t)V_DCDC_1P000; /* Set DCDC voltage to be 1.000 V (USB HS IP cannot work below 0.990 V) */ + } +} + +/** + * @brief + * @param + * @return + */ +static uint32_t lf_set_ldo_ao_ldo_mem_voltage(uint32_t p_lp_mode, uint32_t p_dcdc_voltage) +{ +#define FLASH_NMPA_LDO_AO_ADDRS (0x9FCF4U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK (0x100U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK (0x3E00U) +#define FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT (9U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK (0x10000U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK (0x3E0000U) +#define FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT (17U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK (0x1000000U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK (0x3E000000U) +#define FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT (25U) + + uint32_t ldo_ao_trim, voltage; + uint32_t lv_v_ldo_pmu, lv_v_ldo_pmu_boost; + + ldo_ao_trim = (*((volatile unsigned int *)(FLASH_NMPA_LDO_AO_ADDRS))); + + switch (p_lp_mode) + { + case LOWPOWER_CFG_LPMODE_DEEPSLEEP: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DSLP_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DSLP_TRIM_SHIFT; + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P900; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P850; + } + } + break; + + case LOWPOWER_CFG_LPMODE_POWERDOWN: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_PDWN_TRIM_MASK) >> FLASH_NMPA_LDO_AO_PDWN_TRIM_SHIFT; + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P800; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; + } + } + break; + + case LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN: + { + if ((ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_VALID_MASK) != 0UL) + { + /* Apply settings coming from Flash */ + lv_v_ldo_pmu = (ldo_ao_trim & FLASH_NMPA_LDO_AO_DPDW_TRIM_MASK) >> FLASH_NMPA_LDO_AO_DPDW_TRIM_SHIFT; + lv_v_ldo_pmu_boost = lv_v_ldo_pmu - 2UL; /* - 50 mV */ + } + else + { + /* Apply default settings */ + lv_v_ldo_pmu = (uint32_t)V_AO_0P800; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_0P750; + } + } + break; + + default: + /* Should never reach this point */ + lv_v_ldo_pmu = (uint32_t)V_AO_1P100; + lv_v_ldo_pmu_boost = (uint32_t)V_AO_1P050; + break; + } + + /* The Memories Voltage settings below are for voltage scaling */ + voltage = + (lv_v_ldo_pmu << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) | /* */ + (lv_v_ldo_pmu_boost << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | /* */ + ((uint32_t)V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) | /* Set to 0.75V (voltage Scaling) */ + ((uint32_t)V_AO_0P700 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) | /* Set to 0.7V (voltage Scaling) */ + ((uint32_t)V_DEEPSLEEP_0P900 + << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) | /* Set to 0.90 V (Not used because LDO_DEEP_SLEEP is disabled)*/ + (p_dcdc_voltage << LOWPOWER_VOLTAGE_DCDC_INDEX) /* */ + ; + + return (voltage); +} + +/** + * @brief + * @param + * @return + */ +static uint32_t lf_wakeup_io_ctrl(uint32_t p_wakeup_io_ctrl) +{ + uint32_t wake_up_type; + uint32_t misc_ctrl_reg; + uint8_t use_external_pullupdown = 0; + + /* Configure Pull up & Pull down based on the required wake-up edge */ + CLOCK_EnableClock(kCLOCK_Iocon); + + misc_ctrl_reg = 0UL; + + /* Wake-up I/O 0 */ + wake_up_type = (p_wakeup_io_ctrl & 0x3UL) >> LOWPOWER_WAKEUPIOSRC_PIO0_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][1] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[8]:WAKEUPIOCTRL[8]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK; + } + + /* Wake-up I/O 1 */ + wake_up_type = (p_wakeup_io_ctrl & 0xCUL) >> LOWPOWER_WAKEUPIOSRC_PIO1_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[0][28] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[9]:WAKEUPIOCTRL[9]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK; + } + + /* Wake-up I/O 2 */ + wake_up_type = (p_wakeup_io_ctrl & 0x30UL) >> LOWPOWER_WAKEUPIOSRC_PIO2_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][18] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[10]:WAKEUPIOCTRL[10]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK; + } + + /* Wake-up I/O 3 */ + wake_up_type = (p_wakeup_io_ctrl & 0xC0UL) >> LOWPOWER_WAKEUPIOSRC_PIO3_INDEX; + use_external_pullupdown = (uint8_t)((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK) >> + LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX); + + if (use_external_pullupdown == 0UL) + { + if ((wake_up_type == 1UL) || (wake_up_type == 3UL)) + { + /* Rising edge and both rising and falling edges */ + IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(1); /* Pull down */ + misc_ctrl_reg |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + else + { + if (wake_up_type == 2UL) + { + /* Falling edge only */ + IOCON->PIO[1][30] = IOCON_PIO_DIGIMODE(1) | IOCON_PIO_MODE(2); /* Pull up */ + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + p_wakeup_io_ctrl |= LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is disabled : set it as required by the user */ + if ((p_wakeup_io_ctrl & LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK) != 0UL) + { + /* Wake-up I/O is configured as Plain Input */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + else + { + /* Wake-up I/O is configured as pull-up or pull-down */ + misc_ctrl_reg |= (~p_wakeup_io_ctrl) & LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + } + } + } + else + { + /* MISCCTRL[11]:WAKEUPIOCTRL[11]:00 -no pullup,pulldown, 10 - pulldown, 01 - pullup, 11 - reserved */ + p_wakeup_io_ctrl &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + misc_ctrl_reg &= ~LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK; + } + + PMC->MISCCTRL = (PMC->MISCCTRL & 0xFFFFF0FFUL) | misc_ctrl_reg; + PMC->WAKEUPIOCTRL = p_wakeup_io_ctrl & 0xFFFUL; + + /* + * Defined according to : + * - LOWPOWER_WAKEUPIOSRC_ in fsl_power.h + * - LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_<...> in fsl_power.h + */ + return (p_wakeup_io_ctrl & 0xFFFUL); +} + +/** + * @brief + * @param + * @return + */ +static uint8_t CLOCK_u8OscCapConvert(uint8_t u8OscCap, uint8_t u8CapBankDiscontinuity) +{ + /* Compensate for discontinuity in the capacitor banks */ + if (u8OscCap < 64U) + { + if (u8OscCap >= u8CapBankDiscontinuity) + { + u8OscCap -= u8CapBankDiscontinuity; + } + else + { + u8OscCap = 0U; + } + } + else + { + if (u8OscCap <= (127U - u8CapBankDiscontinuity)) + { + u8OscCap += u8CapBankDiscontinuity; + } + else + { + u8OscCap = 127U; + } + } + return u8OscCap; +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_system_voltage(uint32_t system_voltage_mv) +{ + /* + * Set system voltage + */ + uint32_t lv_ldo_ao = (uint32_t)V_AO_1P100; /* */ + uint32_t lv_ldo_ao_boost = (uint32_t)V_AO_1P150; /* */ + uint32_t lv_dcdc = (uint32_t)V_DCDC_1P100; /* */ + + if (system_voltage_mv <= 950UL) + { + lv_dcdc = (uint32_t)V_DCDC_0P950; + lv_ldo_ao = (uint32_t)V_AO_0P960; + lv_ldo_ao_boost = (uint32_t)V_AO_1P010; + } + else if (system_voltage_mv <= 975UL) + { + lv_dcdc = (uint32_t)V_DCDC_0P975; + lv_ldo_ao = (uint32_t)V_AO_0P980; + lv_ldo_ao_boost = (uint32_t)V_AO_1P030; + } + else if (system_voltage_mv <= 1000UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P000; + lv_ldo_ao = (uint32_t)V_AO_1P000; + lv_ldo_ao_boost = (uint32_t)V_AO_1P050; + } + else if (system_voltage_mv <= 1025UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P025; + lv_ldo_ao = (uint32_t)V_AO_1P030; + lv_ldo_ao_boost = (uint32_t)V_AO_1P080; + } + else if (system_voltage_mv <= 1050UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P050; + lv_ldo_ao = (uint32_t)V_AO_1P060; + lv_ldo_ao_boost = (uint32_t)V_AO_1P110; + } + else if (system_voltage_mv <= 1075UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P075; + lv_ldo_ao = (uint32_t)V_AO_1P080; + lv_ldo_ao_boost = (uint32_t)V_AO_1P130; + } + else if (system_voltage_mv <= 1100UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P100; + lv_ldo_ao = (uint32_t)V_AO_1P100; + lv_ldo_ao_boost = (uint32_t)V_AO_1P150; + } + else if (system_voltage_mv <= 1125UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P125; + lv_ldo_ao = (uint32_t)V_AO_1P130; + lv_ldo_ao_boost = (uint32_t)V_AO_1P160; + } + else if (system_voltage_mv <= 1150UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P150; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + else if (system_voltage_mv <= 1175UL) + { + lv_dcdc = (uint32_t)V_DCDC_1P175; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + else + { + lv_dcdc = (uint32_t)V_DCDC_1P200; + lv_ldo_ao = (uint32_t)V_AO_1P160; + lv_ldo_ao_boost = (uint32_t)V_AO_1P220; + } + + /* Set up LDO Always-On voltages */ + PMC->LDOPMU = (PMC->LDOPMU & (~PMC_LDOPMU_VADJ_MASK) & (~PMC_LDOPMU_VADJ_BOOST_MASK)) | PMC_LDOPMU_VADJ(lv_ldo_ao) | + PMC_LDOPMU_VADJ_BOOST(lv_ldo_ao_boost); + + /* Set up DCDC voltage */ + PMC->DCDC0 = (PMC->DCDC0 & (~PMC_DCDC0_VOUT_MASK)) | PMC_DCDC0_VOUT(lv_dcdc); +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_dcdc_power_profile(lowpower_dcdc_power_profile_enum dcdc_power_profile) +{ +#define FLASH_NMPA_BASE (0x9FC00u) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS (FLASH_NMPA_BASE + 0xE0U) // (0x9FCE0U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS (FLASH_NMPA_BASE + 0xE4U) // (0x9FCE4U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS (FLASH_NMPA_BASE + 0xE8U) // (0x9FCE8U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS (FLASH_NMPA_BASE + 0xECU) // (0x9FCECU) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS (FLASH_NMPA_BASE + 0xD8U) // (0x9FCD8U) +#define FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS (FLASH_NMPA_BASE + 0xDCU) // (0x9FCDCU) + + const uint32_t PMC_DCDC0_DEFAULT = 0x010C4E68; + const uint32_t PMC_DCDC1_DEFAULT = 0x01803A98; + + uint32_t dcdcTrimValue0; + uint32_t dcdcTrimValue1; + + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_LOW: + /* Low */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_LOW_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "LOW" + "\n"); +#endif + } + break; + + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_MEDIUM_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "MEDIUM" + "\n"); +#endif + } + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + dcdcTrimValue0 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_0_ADDRS))); + dcdcTrimValue1 = (*((volatile unsigned int *)(FLASH_NMPA_DCDC_POWER_PROFILE_HIGH_1_ADDRS))); + + if (0UL != (dcdcTrimValue0 & 0x1UL)) + { + dcdcTrimValue0 = dcdcTrimValue0 >> 1; + + PMC->DCDC0 = dcdcTrimValue0; + PMC->DCDC1 = dcdcTrimValue1; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "HIGH" + "\n"); +#endif + } + break; + + default: + /* Low */ + PMC->DCDC0 = PMC_DCDC0_DEFAULT; + PMC->DCDC1 = PMC_DCDC1_DEFAULT; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : DCDC Power Profile set to " + "LOW" + "\n"); +#endif + break; + } +} + +/** + * @brief + * @param + * @return + */ +static lowpower_process_corner_enum lowpower_get_part_process_corner(void) +{ +#define FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS (FLASH_NMPA_BASE + 0x130U) +#define FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS (FLASH_NMPA_BASE + 0x140U) + + lowpower_process_corner_enum part_process_corner; + uint32_t pvt_ringo_hz; + uint32_t pvt_ringo_0 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_0_RINGO_ADDRS))); + uint32_t pvt_ringo_1 = (*((volatile unsigned int *)(FLASH_NMPA_PVT_MONITOR_1_RINGO_ADDRS))); + + /* + * Check that the PVT Monitors Trimmings in flash are valid. + */ + if (0UL != (pvt_ringo_0 & 0x1UL)) + { + /* PVT Trimmings in Flash are valid */ + pvt_ringo_0 = pvt_ringo_0 >> 1; + } + else + { + /* PVT Trimmings in Flash are NOT valid (average value assumed) */ + pvt_ringo_0 = PROCESS_NNN_AVG_HZ; + } + + if (0UL != (pvt_ringo_1 & 0x1UL)) + { + /* PVT Trimmings in Flash are valid */ + pvt_ringo_1 = pvt_ringo_1 >> 1; + } + else + { + /* PVT Trimmings in Flash are NOT valid (average value assumed) */ + pvt_ringo_1 = PROCESS_NNN_AVG_HZ; + } + + if (pvt_ringo_1 <= pvt_ringo_0) + { + pvt_ringo_hz = pvt_ringo_1; + } + else + { + pvt_ringo_hz = pvt_ringo_0; + } + + /* + * Determine the process corner based on the value of the Ring Oscillator frequency + */ + if (pvt_ringo_hz <= PROCESS_NNN_MIN_HZ) + { + /* SSS Process Corner */ + part_process_corner = PROCESS_CORNER_SSS; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "SSS" + "\n"); +#endif + } + else + { + if (pvt_ringo_hz <= PROCESS_NNN_MAX_HZ) + { + /* NNN Process Corner */ + part_process_corner = PROCESS_CORNER_NNN; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "NNN" + "\n"); +#endif + } + else + { + /* FFF Process Corner */ + part_process_corner = PROCESS_CORNER_FFF; +#if (defined(NIOBE_DEBUG_LEVEL) && (NIOBE_DEBUG_LEVEL >= 1)) + PRINTF( + "\nINFO : Process Corner : " + "FFF" + "\n"); +#endif + } + } + + return (part_process_corner); +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +static void lowpower_set_voltage_for_process(lowpower_dcdc_power_profile_enum dcdc_power_profile) +{ + /* Get Sample Process Corner */ + lowpower_process_corner_enum part_process_corner = lowpower_get_part_process_corner(); + + switch (part_process_corner) + { + case PROCESS_CORNER_SSS: + /* Slow Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_SSS_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_SSS_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_SSS_LOW_MV); + break; + } // switch(dcdc_power_profile) + } + break; + + case PROCESS_CORNER_FFF: + /* Fast Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_FFF_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_FFF_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_FFF_LOW_MV); + break; + } // switch(dcdc_power_profile) + } + break; + + default: + /* Nominal (NNN) and all others Process Corners : assume Nominal Corner */ + { + switch (dcdc_power_profile) + { + case DCDC_POWER_PROFILE_MEDIUM: + /* Medium */ + lowpower_set_system_voltage(VOLTAGE_NNN_MED_MV); + break; + + case DCDC_POWER_PROFILE_HIGH: + /* High */ + lowpower_set_system_voltage(VOLTAGE_NNN_HIG_MV); + break; + + default: + /* DCDC_POWER_PROFILE_LOW */ + lowpower_set_system_voltage(VOLTAGE_NNN_LOW_MV); + break; + } // switch(dcdc_power_profile) + break; + } + } // switch(part_process_corner) +} + +/** + * @brief Described in fsl_common.h + * @param + * @return + */ +void POWER_SetVoltageForFreq(uint32_t system_freq_hz) +{ + if (system_freq_hz <= DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ) + { + /* [0 Hz - DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz] */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_LOW); /* DCDC VOUT = 1.05 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_LOW); + } + else + { + if (system_freq_hz <= DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ) + { + /* ]DCDC_POWER_PROFILE_LOW_MAX_FREQ_HZ Hz - DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz] */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_MEDIUM); /* DCDC VOUT = 1.15 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_MEDIUM); + } + else + { + /* > DCDC_POWER_PROFILE_MEDIUM_MAX_FREQ_HZ Hz */ + lowpower_set_dcdc_power_profile(DCDC_POWER_PROFILE_HIGH); /* DCDC VOUT = 1.2 V by default */ + lowpower_set_voltage_for_process(DCDC_POWER_PROFILE_HIGH); + } + } +} + +void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, + int32_t pi32_16MfXtalPPcbParCappF_x100, + int32_t pi32_16MfXtalNPcbParCappF_x100) +{ + uint32_t u32XOTrimValue; + uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF, u8XOSlave; + int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; + int32_t iXOCapInpF_x100, iXOCapOutpF_x100; + uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; + uint32_t u32RegVal; + int32_t i32Tmp; + + /* Enable and set LDO, if not already done */ + POWER_SetXtal16mhzLdo(); + /* Get Cal values from Flash */ + u32XOTrimValue = GET_16MXO_TRIM(); + /* Check validity and apply */ + if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) + { + /* These fields are 7 bits, unsigned */ + u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); + u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); + u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); + u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); + /* This field is 1 bit */ + u8XOSlave = (uint8_t)((u32XOTrimValue >> 30UL) & 0x1UL); + /* Linear fit coefficients calculation */ + iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; + ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; + iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; + ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; + } + else + { + iaXin_x4 = 20; // gain in LSB/pF + ibXin = -9; // offset in LSB + iaXout_x4 = 20; // gain in LSB/pF + ibXout = -13; // offset in LSB + u8XOSlave = 0; + } + /* In & out load cap calculation with derating */ + iXOCapInpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalNPcbParCappF_x100 + + 39 * ((int32_t)XO_SLAVE_EN - (int32_t)u8XOSlave) - 15; + iXOCapOutpF_x100 = 2 * pi32_16MfXtalIecLoadpF_x100 - pi32_16MfXtalPPcbParCappF_x100 - 21; + /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ + i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; + u8XOCapInCtrl = (uint8_t)i32Tmp; + i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; + u8XOCapOutCtrl = (uint8_t)i32Tmp; + /* Read register and clear fields to be written */ + u32RegVal = ANACTRL->XO32M_CTRL; + u32RegVal &= ~(ANACTRL_XO32M_CTRL_OSC_CAP_IN_MASK | ANACTRL_XO32M_CTRL_OSC_CAP_OUT_MASK); + /* Configuration of 32 MHz XO output buffers */ +#if (XO_SLAVE_EN == 0) + u32RegVal &= ~(ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK); +#else + u32RegVal |= ANACTRL_XO32M_CTRL_SLAVE_MASK | ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK; +#endif + /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_IN_SHIFT; + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 13) << ANACTRL_XO32M_CTRL_OSC_CAP_OUT_SHIFT; + /* Write back to register */ + ANACTRL->XO32M_CTRL = u32RegVal; +} + +void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, + int32_t pi32_32kfXtalPPcbParCappF_x100, + int32_t pi32_32kfXtalNPcbParCappF_x100) +{ + uint32_t u32XOTrimValue; + uint8_t u8IECXinCapCal6pF, u8IECXinCapCal8pF, u8IECXoutCapCal6pF, u8IECXoutCapCal8pF; + int32_t iaXin_x4, ibXin, iaXout_x4, ibXout; + int32_t iXOCapInpF_x100, iXOCapOutpF_x100; + uint8_t u8XOCapInCtrl, u8XOCapOutCtrl; + uint32_t u32RegVal; + int32_t i32Tmp; + /* Get Cal values from Flash */ + u32XOTrimValue = GET_32KXO_TRIM(); + /* check validity and apply */ + if ((0UL != (u32XOTrimValue & 1UL)) && (0UL != ((u32XOTrimValue >> 15UL) & 1UL))) + { + /* These fields are 7 bits, unsigned */ + u8IECXinCapCal6pF = (uint8_t)((u32XOTrimValue >> 1UL) & 0x7fUL); + u8IECXinCapCal8pF = (uint8_t)((u32XOTrimValue >> 8UL) & 0x7fUL); + u8IECXoutCapCal6pF = (uint8_t)((u32XOTrimValue >> 16UL) & 0x7fUL); + u8IECXoutCapCal8pF = (uint8_t)((u32XOTrimValue >> 23UL) & 0x7fUL); + /* Linear fit coefficients calculation */ + iaXin_x4 = (int)u8IECXinCapCal8pF - (int)u8IECXinCapCal6pF; + ibXin = (int)u8IECXinCapCal6pF - iaXin_x4 * 3; + iaXout_x4 = (int)u8IECXoutCapCal8pF - (int)u8IECXoutCapCal6pF; + ibXout = (int)u8IECXoutCapCal6pF - iaXout_x4 * 3; + } + else + { + iaXin_x4 = 16; // gain in LSB/pF + ibXin = 12; // offset in LSB + iaXout_x4 = 16; // gain in LSB/pF + ibXout = 11; // offset in LSB + } + + /* In & out load cap calculation with derating */ + iXOCapInpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalNPcbParCappF_x100 - 130; + iXOCapOutpF_x100 = 2 * pi32_32kfXtalIecLoadpF_x100 - pi32_32kfXtalPPcbParCappF_x100 - 41; + + /* In & out XO_OSC_CAP_Code_CTRL calculation, with rounding */ + i32Tmp = ((iXOCapInpF_x100 * iaXin_x4 + ibXin * 400) + 200) / 400; + u8XOCapInCtrl = (uint8_t)i32Tmp; + i32Tmp = ((iXOCapOutpF_x100 * iaXout_x4 + ibXout * 400) + 200) / 400; + u8XOCapOutCtrl = (uint8_t)i32Tmp; + + /* Read register and clear fields to be written */ + u32RegVal = PMC->XTAL32K; + u32RegVal &= ~(PMC_XTAL32K_CAPBANKIN_MASK | PMC_XTAL32K_CAPBANKOUT_MASK); + + /* XO_OSC_CAP_Code_CTRL to XO_OSC_CAP_Code conversion */ + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapInCtrl, 23) << PMC_XTAL32K_CAPBANKIN_SHIFT; + u32RegVal |= (uint32_t)CLOCK_u8OscCapConvert(u8XOCapOutCtrl, 23) << PMC_XTAL32K_CAPBANKOUT_SHIFT; + + /* Write back to register */ + PMC->XTAL32K = u32RegVal; +} + +void POWER_SetXtal16mhzLdo(void) +{ + uint32_t temp; + const uint32_t u32Mask = + (ANACTRL_LDO_XO32M_VOUT_MASK | ANACTRL_LDO_XO32M_IBIAS_MASK | ANACTRL_LDO_XO32M_STABMODE_MASK); + + const uint32_t u32Value = + (ANACTRL_LDO_XO32M_VOUT(0x5) | ANACTRL_LDO_XO32M_IBIAS(0x2) | ANACTRL_LDO_XO32M_STABMODE(0x1)); + + /* Enable & set-up XTAL 32 MHz clock LDO */ + temp = ANACTRL->LDO_XO32M; + + if ((temp & u32Mask) != u32Value) + { + temp &= ~u32Mask; + + /* + * Enable the XTAL32M LDO + * Adjust the output voltage level, 0x5 for 1.1V + * Adjust the biasing current, 0x2 value + * Stability configuration, 0x1 default mode + */ + temp |= u32Value; + + ANACTRL->LDO_XO32M = temp; + + /* Delay for LDO to be up */ + // CLOCK_uDelay(20); + } + + /* Enable LDO XO32M */ + PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK; +} + +/** + * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. + * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. + * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. + * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. + + * @return Nothing + * + * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! + * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! + * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! + * - 1. p_wakeupio_cause is NOT ACCURATE + * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when + * several wake-up sources are enabled during DEEP-POWER-DOWN + * (like enabling wake-up on RTC and Falling edge wake-up pins) + * + */ +void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, + power_device_boot_mode_t *p_boot_mode, + uint32_t *p_wakeupio_cause) +{ + uint32_t reset_cause_reg; + uint32_t boot_mode_reg; + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + reset_cause_reg = (PMC->AOREG1) & 0x3FF0UL; +#else /* LPC55S69/28 */ + reset_cause_reg = (PMC->AOREG1) & 0x1FF0UL; +#endif + + /* + * Prioritize interrupts source with respect to their critical level + */ +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + if (0UL != (reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK)) + { /* Code Watchdog Reset */ + *p_reset_cause = kRESET_CAUSE_CDOGRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else +#endif + { + if (0UL != (reset_cause_reg & PMC_AOREG1_WDTRESET_MASK)) + { /* Watchdog Timer Reset */ + *p_reset_cause = kRESET_CAUSE_WDTRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK)) + { /* ARM System Reset */ + *p_reset_cause = kRESET_CAUSE_ARMSYSTEMRESET; + *p_boot_mode = kBOOT_MODE_POWER_UP; + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + } + else + { + boot_mode_reg = (PMC->STATUS & PMC_STATUS_BOOTMODE_MASK) >> PMC_STATUS_BOOTMODE_SHIFT; + + if (boot_mode_reg == 0UL) /* POWER-UP: Power On Reset, Pin reset, Brown Out Detectors, Software Reset */ + { + *p_boot_mode = kBOOT_MODE_POWER_UP; /* All non wake-up from a Low Power mode */ + *p_wakeupio_cause = 0; /* Device has not been waked-up by any wake-up pins */ + + /* + * Prioritise Reset causes, starting from the strongest (Power On Reset) + */ + if (0UL != (reset_cause_reg & PMC_AOREG1_POR_MASK)) + { /* Power On Reset */ + *p_reset_cause = kRESET_CAUSE_POR; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_BODRESET_MASK)) + { /* Brown-out Detector reset (either BODVBAT or BODCORE) */ + *p_reset_cause = kRESET_CAUSE_BODRESET; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_PADRESET_MASK)) + { /* Hardware Pin Reset */ + *p_reset_cause = kRESET_CAUSE_PADRESET; + } + else + { + if (0UL != (reset_cause_reg & PMC_AOREG1_SWRRESET_MASK)) + { /* Software triggered Reset */ + *p_reset_cause = kRESET_CAUSE_SWRRESET; + } + else + { /* Unknown Reset Cause */ + *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; + } + } + } + } + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + /* Transfer the control of the 4 wake-up pins to IOCON (instead of the Power Management Controller + */ + PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); +#endif + } + else /* DEEP-SLEEP, POWER-DOWN and DEEP-POWER-DOWN */ + { + /* + * 1- First, save wakeup_io_cause register ... + */ + *p_wakeupio_cause = PMC->WAKEIOCAUSE; + + if (boot_mode_reg == 3UL) /* DEEP-POWER-DOWN */ + { + *p_boot_mode = kBOOT_MODE_LP_DEEP_POWER_DOWN; + + switch (((reset_cause_reg >> PMC_AOREG1_DPDRESET_WAKEUPIO_SHIFT) & 0x7UL)) + { + case 1: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO; + break; + case 2: + *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC; + break; + case 3: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC; + break; + case 4: + *p_reset_cause = kRESET_CAUSE_DPDRESET_OSTIMER; + break; + case 5: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER; + break; + case 6: + *p_reset_cause = kRESET_CAUSE_DPDRESET_RTC_OSTIMER; + break; + case 7: + *p_reset_cause = kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER; + break; + default: + /* Unknown Reset Cause */ + *p_reset_cause = kRESET_CAUSE_NOT_DETERMINISTIC; + break; + } + +#if (defined(LPC55S06_SERIES) || defined(LPC55S04_SERIES) || defined(LPC5506_SERIES) || defined(LPC5504_SERIES) || \ + defined(LPC5502_SERIES) || defined(LPC55S16_SERIES) || defined(LPC55S14_SERIES) || defined(LPC5516_SERIES) || \ + defined(LPC5514_SERIES) || defined(LPC5512_SERIES)) + /* + * 2- Next, transfer the control of the 4 wake-up pins + * to IOCON (instead of the Power Management Controller) + */ + PMC->WAKEUPIOCTRL = PMC->WAKEUPIOCTRL & (~PMC_WAKEUPIOCTRL_WAKEUPIO_ENABLE_CTRL_MASK); +#endif + } + else /* DEEP-SLEEP and POWER-DOWN */ + { + *p_reset_cause = kRESET_CAUSE_NOT_RELEVANT; + + /* + * The control of the 4 wake-up pins is already in IOCON, + * so there is nothing special to do. + */ + + if (boot_mode_reg == 1UL) /* DEEP-SLEEP */ + { + *p_boot_mode = kBOOT_MODE_LP_DEEP_SLEEP; + } + else /* POWER-DOWN */ + { + *p_boot_mode = kBOOT_MODE_LP_POWER_DOWN; + + } /* if ( boot_mode_reg == 1 ) DEEP-SLEEP */ + + } /* if ( boot_mode == 3 ) DEEP-POWER-DOWN */ + + } /* if ( boot_mode == 0 ) POWER-UP */ + + } /* if ( reset_cause_reg & PMC_AOREG1_CDOGRESET_MASK ) */ + + } /* if ( reset_cause_reg & PMC_AOREG1_WDTRESET_MASK ) */ + + } /* if ( reset_cause_reg & PMC_AOREG1_SYSTEMRESET_MASK ) */ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.h index e945037f10..6a9de7a9f5 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_power.h @@ -25,112 +25,45 @@ #define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0)) /*@}*/ - -/** @brief Low Power main structure */ -typedef enum +/* Power mode configuration API parameter */ +typedef enum _power_mode_config { - VD_AON = 0x0, /*!< Digital Always On power domain */ - VD_MEM = 0x1, /*!< Memories (SRAM) power domain */ - VD_DCDC = 0x2, /*!< Core logic power domain */ - VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */ -} LPC_POWER_DOMAIN_T; - -/** @brief Low Power main structure */ -typedef struct -{ /* */ - __IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */ - __IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules - in the different Low power modes, including ROM */ - __IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances - in the different Low power modes */ - __IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */ - __IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */ - __IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */ - __IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */ - __IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes - in case an interrupt is pending when the processor request deepsleep */ - __IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */ - __IO uint32_t TIMERCFG; /*!< Wake up timers configuration */ - __IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/ - __IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some - interrupt handlers)*/ -} LPC_LOWPOWER_T; - -/* */ -#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBA /*!< */ - -/* Low Power modes */ -#define LOWPOWER_CFG_LPMODE_INDEX 0 -#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX) -#define LOWPOWER_CFG_SELCLOCK_INDEX 2 -#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX) -#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3 -#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX) -#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4 -#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX) -#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5 -#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX) - -#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */ -#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */ -#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */ -#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */ - -#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */ -#define LOWPOWER_CFG_SELCLOCK_12MHZ 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/ - -#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */ -#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */ - -#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high as possible -- 1.1V typical -- during low power mode) */ -#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low as possible -- down to 0.7V -- during low power mode) */ - -#define LOWPOWER_CFG_LDODEEPSLEEPREF_FLASHBUFFER 0 /*!< LDO DEEP SLEEP uses Flash Buffer as reference */ -#define LOWPOWER_CFG_LDODEEPSLEEPREF_BANDGAG0P8V 1 /*!< LDO DEEP SLEEP uses Band Gap 0.8V as reference */ - -/* CPU Retention Control*/ -#define LOWPOWER_CPURETCTRL_ENA_INDEX 0 -#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX) -#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1 -#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFF << LOWPOWER_CPURETCTRL_MEMBASE_INDEX) -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14 -#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX) - -#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ -#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ + kPmu_Sleep = 0U, + kPmu_Deep_Sleep = 1U, + kPmu_PowerDown = 2U, + kPmu_Deep_PowerDown = 3U, +} power_mode_cfg_t; /** * @brief Analog components power modes control during low power modes */ typedef enum pd_bits { - kPDRUNCFG_PD_DCDC = (1UL << 0), - kPDRUNCFG_PD_BIAS = (1UL << 1), - kPDRUNCFG_PD_BODCORE = (1UL << 2), - kPDRUNCFG_PD_BODVBAT = (1UL << 3), - kPDRUNCFG_PD_FRO1M = (1UL << 4), - kPDRUNCFG_PD_FRO192M = (1UL << 5), - kPDRUNCFG_PD_FRO32K = (1UL << 6), - kPDRUNCFG_PD_XTAL32K = (1UL << 7), - kPDRUNCFG_PD_XTAL32M = (1UL << 8), - kPDRUNCFG_PD_PLL0 = (1UL << 9), - kPDRUNCFG_PD_PLL1 = (1UL << 10), - kPDRUNCFG_PD_USB0_PHY = (1UL << 11), - kPDRUNCFG_PD_USB1_PHY = (1UL << 12), - kPDRUNCFG_PD_COMP = (1UL << 13), - kPDRUNCFG_PD_TEMPSENS = (1UL << 14), - kPDRUNCFG_PD_GPADC = (1UL << 15), - kPDRUNCFG_PD_LDOMEM = (1UL << 16), + kPDRUNCFG_PD_DCDC = (1UL << 0), + kPDRUNCFG_PD_BIAS = (1UL << 1), + kPDRUNCFG_PD_BODCORE = (1UL << 2), + kPDRUNCFG_PD_BODVBAT = (1UL << 3), + kPDRUNCFG_PD_FRO1M = (1UL << 4), + kPDRUNCFG_PD_FRO192M = (1UL << 5), + kPDRUNCFG_PD_FRO32K = (1UL << 6), + kPDRUNCFG_PD_XTAL32K = (1UL << 7), + kPDRUNCFG_PD_XTAL32M = (1UL << 8), + kPDRUNCFG_PD_PLL0 = (1UL << 9), + kPDRUNCFG_PD_PLL1 = (1UL << 10), + kPDRUNCFG_PD_USB0_PHY = (1UL << 11), + kPDRUNCFG_PD_USB1_PHY = (1UL << 12), + kPDRUNCFG_PD_COMP = (1UL << 13), + kPDRUNCFG_PD_TEMPSENS = (1UL << 14), + kPDRUNCFG_PD_GPADC = (1UL << 15), + kPDRUNCFG_PD_LDOMEM = (1UL << 16), kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17), - kPDRUNCFG_PD_LDOUSBHS = (1UL << 18), - kPDRUNCFG_PD_LDOGPADC = (1UL << 19), - kPDRUNCFG_PD_LDOXO32M = (1UL << 20), - kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), - kPDRUNCFG_PD_RNG = (1UL << 22), - kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), - kPDRUNCFG_PD_ROM = (1UL << 24), - + kPDRUNCFG_PD_LDOUSBHS = (1UL << 18), + kPDRUNCFG_PD_LDOGPADC = (1UL << 19), + kPDRUNCFG_PD_LDOXO32M = (1UL << 20), + kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21), + kPDRUNCFG_PD_RNG = (1UL << 22), + kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23), + kPDRUNCFG_PD_ROM = (1UL << 24), /* This enum member has no practical meaning,it is used to avoid MISRA issue, user should not trying to use it. @@ -138,38 +71,7 @@ typedef enum pd_bits kPDRUNCFG_ForceUnsigned = 0x80000000U, } pd_bit_t; -/** - * @brief SRAM instances retention control during low power modes - */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */ -#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */ - -/** - * @brief SRAM Low Power Modes - */ - -#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL) -#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */ -#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */ -#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */ -#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */ -#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */ - -/*@brief BOD VBAT level */ +/*! @brief BOD VBAT level */ typedef enum _power_bod_vbat_level { kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */ @@ -200,7 +102,16 @@ typedef enum _power_bod_vbat_level kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */ } power_bod_vbat_level_t; -/*@brief BOD core level */ +/*! @brief BOD Hysteresis control */ +typedef enum _power_bod_hyst +{ + kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ + kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ + kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ + kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ +} power_bod_hyst_t; + +/*! @brief BOD core level */ typedef enum _power_bod_core_level { kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */ @@ -213,269 +124,245 @@ typedef enum _power_bod_core_level kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */ } power_bod_core_level_t; -/*@brief BOD Hysteresis control */ -typedef enum _power_bod_hyst +/** + * @brief Device Reset Causes + */ +typedef enum _power_device_reset_cause { - kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */ - kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */ - kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */ - kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */ -} power_bod_hyst_t; + kRESET_CAUSE_POR = 0UL, /*!< Power On Reset */ + kRESET_CAUSE_PADRESET = 1UL, /*!< Hardware Pin Reset */ + kRESET_CAUSE_BODRESET = 2UL, /*!< Brown-out Detector reset (either BODVBAT or BODCORE) */ + kRESET_CAUSE_ARMSYSTEMRESET = 3UL, /*!< ARM System Reset */ + kRESET_CAUSE_WDTRESET = 4UL, /*!< Watchdog Timer Reset */ + kRESET_CAUSE_SWRRESET = 5UL, /*!< Software Reset */ + kRESET_CAUSE_CDOGRESET = 6UL, /*!< Code Watchdog Reset */ + /* Reset causes in DEEP-POWER-DOWN low power mode */ + kRESET_CAUSE_DPDRESET_WAKEUPIO = 7UL, /*!< Any of the 4 wake-up pins */ + kRESET_CAUSE_DPDRESET_RTC = 8UL, /*!< Real Time Counter (RTC) */ + kRESET_CAUSE_DPDRESET_OSTIMER = 9UL, /*!< OS Event Timer (OSTIMER) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC = 10UL, /*!< Any of the 4 wake-up pins and RTC (it is not possible to distinguish + which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_OSTIMER = 11UL, /*!< Any of the 4 wake-up pins and OSTIMER (it is not possible to + distinguish which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_RTC_OSTIMER = 12UL, /*!< Real Time Counter or OS Event Timer (it is not possible to + distinguish which of these 2 events occured first) */ + kRESET_CAUSE_DPDRESET_WAKEUPIO_RTC_OSTIMER = 13UL, /*!< Any of the 4 wake-up pins (it is not possible to distinguish + which of these 3 events occured first) */ + /* Miscallenous */ + kRESET_CAUSE_NOT_RELEVANT = + 14UL, /*!< No reset cause (for example, this code is used when waking up from DEEP-SLEEP low power mode) */ + kRESET_CAUSE_NOT_DETERMINISTIC = 15UL, /*!< Unknown Reset Cause. Should be treated like "Hardware Pin Reset" from an + application point of view. */ +} power_device_reset_cause_t; /** - * @brief LDO Voltage control in Low Power Modes + * @brief Device Boot Modes */ -#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0 -#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5 -#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10 -#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19 -#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24 -#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) -#define LOWPOWER_VOLTAGE_DCDC_INDEX 29 -#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX) +typedef enum _power_device_boot_mode +{ + kBOOT_MODE_POWER_UP = + 0UL, /*!< All non Low Power Mode wake up (Power On Reset, Pin Reset, BoD Reset, ARM System Reset ... ) */ + kBOOT_MODE_LP_DEEP_SLEEP = 1UL, /*!< Wake up from DEEP-SLEEP Low Power mode */ + kBOOT_MODE_LP_POWER_DOWN = 2UL, /*!< Wake up from POWER-DOWN Low Power mode */ + kBOOT_MODE_LP_DEEP_POWER_DOWN = 4UL, /*!< Wake up from DEEP-POWER-DOWN Low Power mode */ +} power_device_boot_mode_t; /** - * @brief Always On and Memories LDO voltage settings + * @brief SRAM instances retention control during low power modes */ - -typedef enum _v_ao -{ - // V_AO_1P220 1.22 = 0, /*!< 1.22 V */ - V_AO_0P700 = 1, /*!< 0.7 V */ - V_AO_0P725 = 2, /*!< 0.725 V */ - V_AO_0P750 = 3, /*!< 0.75 V */ - V_AO_0P775 = 4, /*!< 0.775 V */ - V_AO_0P800 = 5, /*!< 0.8 V */ - V_AO_0P825 = 6, /*!< 0.825 V */ - V_AO_0P850 = 7, /*!< 0.85 V */ - V_AO_0P875 = 8, /*!< 0.875 V */ - V_AO_0P900 = 9, /*!< 0.9 V */ - V_AO_0P960 = 10, /*!< 0.96 V */ - V_AO_0P970 = 11, /*!< 0.97 V */ - V_AO_0P980 = 12, /*!< 0.98 V */ - V_AO_0P990 = 13, /*!< 0.99 V */ - V_AO_1P000 = 14, /*!< 1 V */ - V_AO_1P010 = 15, /*!< 1.01 V */ - V_AO_1P020 = 16, /*!< 1.02 V */ - V_AO_1P030 = 17, /*!< 1.03 V */ - V_AO_1P040 = 18, /*!< 1.04 V */ - V_AO_1P050 = 19, /*!< 1.05 V */ - V_AO_1P060 = 20, /*!< 1.06 V */ - V_AO_1P070 = 21, /*!< 1.07 V */ - V_AO_1P080 = 22, /*!< 1.08 V */ - V_AO_1P090 = 23, /*!< 1.09 V */ - V_AO_1P100 = 24, /*!< 1.1 V */ - V_AO_1P110 = 25, /*!< 1.11 V */ - V_AO_1P120 = 26, /*!< 1.12 V */ - V_AO_1P130 = 27, /*!< 1.13 V */ - V_AO_1P140 = 28, /*!< 1.14 V */ - V_AO_1P150 = 29, /*!< 1.15 V */ - V_AO_1P160 = 30, /*!< 1.16 V */ - V_AO_1P220 = 31 /*!< 1.22 V */ -} v_ao_t; - -/** - * @brief Deep Sleep LDO voltage settings - */ -typedef enum _v_deepsleep -{ - V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */ - V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */ - V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */ - V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */ - V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */ - V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */ - V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */ - V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */ -} v_deepsleep_t; - -/** - * @brief DCDC voltage settings - */ -typedef enum _v_dcdc -{ - V_DCDC_0P950 = 0, /*!< 0.95 V */ - V_DCDC_0P975 = 1, /*!< 0.975 V */ - V_DCDC_1P000 = 2, /*!< 1 V */ - V_DCDC_1P025 = 3, /*!< 1.025 V */ - V_DCDC_1P050 = 4, /*!< 1.050 V */ - V_DCDC_1P075 = 5, /*!< 1.075 V */ - V_DCDC_1P100 = 6, /*!< 1.1 V */ - V_DCDC_1P125 = 7, /*!< 1.125 V */ - V_DCDC_1P150 = 8, /*!< 1.150 V */ - V_DCDC_1P175 = 9, /*!< 1.175 V */ - V_DCDC_1P200 = 10 /*!< 1.2 V */ -} v_dcdc_t; -/** - * @brief LDO_FLASH_NV & LDO_USB voltage settings - */ -typedef enum _v_flashnv -{ - V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */ - V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */ - V_LDOFLASHNV_1P750 = 2, /*!< 1 V */ - V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */ - V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */ - V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */ - V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */ - V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */ -} v_flashnv_t; +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 \ + (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 \ + (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 \ + (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 \ + (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 \ + (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 \ + (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 \ + (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 \ + (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 \ + (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 \ + (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 \ + (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 \ + (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 \ + (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 \ + (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS \ + (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */ +#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF \ + (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */ /** * @brief Low Power Modes Wake up sources */ - -#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ -#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ -#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ -#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ -// reserved (1ULL << 23) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/ +#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */ +#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */ +#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */ +#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ // reserved (1ULL << 25) // reserved (1ULL << 26) -#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ -#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */ -#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ -#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ +#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */ +#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */ +#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */ // reserved (1ULL << 39) // reserved (1ULL << 40) // reserved (1ULL << 41) -#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */ +#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */ // reserved (1ULL << 43) // reserved (1ULL << 44) // reserved (1ULL << 45) // reserved (1ULL << 46) -#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ -#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_SEC_VIO (1ULL << 53) -#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ -#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ -#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */ -#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */ -#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ -#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */ +#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_SEC_VIO (1ULL << 53) +#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */ +#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */ +#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */ +#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */ +#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */ +#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */ // reserved WAKEUP_PVTVF0_AMBER (1ULL << 60) // reserved WAKEUP_PVTVF0_RED (1ULL << 61) // reserved WAKEUP_PVTVF1_AMBER (1ULL << 62) -#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ - +#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */ /** * @brief Sleep Postpone */ -#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ -#define LOWPOWER_HWWAKE_PERIPHERALS (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted */ -#define LOWPOWER_HWWAKE_SDMA0 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_SDMA1 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ -#define LOWPOWER_HWWAKE_ENABLE_FRO192M (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ +#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */ +#define LOWPOWER_HWWAKE_PERIPHERALS \ + (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause \ + peripheral clocking to wake up temporarily while the related status is asserted */ +#define LOWPOWER_HWWAKE_SDMA0 \ + (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_SDMA1 \ + (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA \ + completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */ +#define LOWPOWER_HWWAKE_ENABLE_FRO192M \ + (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of \ + LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */ +#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */ +#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */ /** * @brief Wake up I/O sources */ -#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ -#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ -#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ -#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ +#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */ +#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */ +#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */ +#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */ -#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ -#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ -#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ -#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ +#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */ +#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */ +#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */ +#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */ -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX 8 /*!< Wake-up I/O 0 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX 9 /*!< Wake-up I/O 1 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX 10 /*!< Wake-up I/O 2 pull-up/down configuration index */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX 11 /*!< Wake-up I/O 3 pull-up/down configuration index */ -#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_PULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_PULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_PULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down mask */ +#define LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_PULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down mask */ -#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ -#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ +#define LOWPOWER_WAKEUPIO_PULLDOWN 0 /*!< Select pull-down */ +#define LOWPOWER_WAKEUPIO_PULLUP 1 /*!< Select pull-up */ -/** - * @brief Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_CTRL_INDEX 0 -#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX) -#define LOWPOWER_TIMERCFG_TIMER_INDEX 1 -#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX) -#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4 -#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX) +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX \ + 12 /*!< Wake-up I/O 0 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX \ + 13 /*!< Wake-up I/O 1 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX \ + 14 /*!< Wake-up I/O 2 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX \ + 15 /*!< Wake-up I/O 3 pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 pull-up/down disable/enable mask */ +#define LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_DISABLEPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 pull-up/down disable/enable mask */ -#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */ -#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */ - -/** - * @brief Primary Wake up timers configuration in Low Power Modes - */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */ -#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */ - -#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */ -#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */ - -//! @brief Interface for lowpower functions -typedef struct LowpowerDriverInterface -{ - void (*power_cycle_cpu_and_flash)(void); - void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg); -} lowpower_driver_interface_t; - -/* Power mode configuration API parameter */ -typedef enum _power_mode_config -{ - kPmu_Sleep = 0U, - kPmu_Deep_Sleep = 1U, - kPmu_PowerDown = 2U, - kPmu_Deep_PowerDown = 3U, -} power_mode_cfg_t; - -/******************************************************************************* - * API - ******************************************************************************/ +#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX \ + (16) /*!< Wake-up I/O 0 use external pull-up/down disable/enable control index*/ +#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX \ + (17) /*!< Wake-up I/O 1 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX \ + (18) /*!< Wake-up I/O 2 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX \ + (19) /*!< Wake-up I/O 3 use external pull-up/down disable/enable control index */ +#define LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO0_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 0 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO1_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 1 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO2_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 2 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ +#define LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_MASK \ + (1UL << LOWPOWER_WAKEUPIO_PIO3_USEEXTERNALPULLUPDOWN_INDEX) /*!< Wake-up I/O 3 use external pull-up/down \ + disable/enable mask, 0: disable, 1: enable */ #ifdef __cplusplus extern "C" { #endif +/******************************************************************************* + * API + ******************************************************************************/ /*! * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral @@ -486,7 +373,7 @@ extern "C" { static inline void POWER_EnablePD(pd_bit_t en) { /* PDRUNCFGSET */ - PMC->PDRUNCFGSET0 = en; + PMC->PDRUNCFGSET0 = (uint32_t)en; } /*! @@ -498,7 +385,7 @@ static inline void POWER_EnablePD(pd_bit_t en) static inline void POWER_DisablePD(pd_bit_t en) { /* PDRUNCFGCLR */ - PMC->PDRUNCFGCLR0 = en; + PMC->PDRUNCFGCLR0 = (uint32_t)en; } /*! @@ -511,11 +398,12 @@ static inline void POWER_DisablePD(pd_bit_t en) static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset) { PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) | - PMC_BODVBAT_HYST(hyst); + PMC_BODVBAT_HYST(hyst); PMC->RESETCTRL = (PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset); } +#if defined(PMC_BODCORE_TRIGLVL_MASK) /*! * @brief set BOD core level. * @@ -526,15 +414,15 @@ static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset) { PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) | - PMC_BODCORE_HYST(hyst); + PMC_BODCORE_HYST(hyst); PMC->RESETCTRL = (PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset); } +#endif /*! * @brief API to enable deep sleep bit in the ARM Core. * - * @param none * @return none */ static inline void POWER_EnableDeepSleep(void) @@ -545,7 +433,6 @@ static inline void POWER_EnableDeepSleep(void) /*! * @brief API to disable deep sleep bit in the ARM Core. * - * @param none * @return none */ static inline void POWER_DisableDeepSleep(void) @@ -553,58 +440,12 @@ static inline void POWER_DisableDeepSleep(void) SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; } -/*! - * @brief API to power down flash controller. - * - * @param none - * @return none - */ -static inline void POWER_PowerDownFlash(void) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ - CLOCK_DisableClock(kCLOCK_Flash); - - /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ - CLOCK_DisableClock(kCLOCK_Fmc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/*! - * @brief API to power up flash controller. - * - * @param none - * @return none - */ -static inline void POWER_PowerUpFlash(void) -{ -#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) - /* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */ - CLOCK_EnableClock(kCLOCK_Fmc); -#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ -} - -/** - * @brief Configures and enters in low power mode - * @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters - * @return Nothing - * - * !!! IMPORTANT NOTES : - * 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the - * API. - * 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk - * of Dead Lock). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip - * reset) - */ -void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg); - /** * @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event * This MUST BE EXECUTED outside the Flash: * either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is * preferable to have all functions defined in this file implemented in ROM. - * @param None + * * @return Nothing */ void POWER_CycleCpuAndFlash(void); @@ -620,12 +461,17 @@ void POWER_CycleCpuAndFlash(void); * * !!! IMPORTANT NOTES : 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) - reset) + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in + case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) reset) */ -void POWER_EnterDeepSleep(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts,uint32_t hardware_wake_ctrl); +void POWER_EnterDeepSleep(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t hardware_wake_ctrl); /** * @brief Configures and enters in POWERDOWN low power mode @@ -639,13 +485,21 @@ void POWER_EnterDeepSleep(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl * * !!! IMPORTANT NOTES : 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance containing the stack used to call this function WILL BE preserved during low power (via parameter "sram_retention_ctrl") - * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) - reset) + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in + case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance + containing the stack used to call this function WILL BE preserved during low power (via parameter + "sram_retention_ctrl") + * 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) reset) */ -void POWER_EnterPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t cpu_retention_ctrl); + +void POWER_EnterPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t cpu_retention_ctrl); /** * @brief Configures and enters in DEEPPOWERDOWN low power mode @@ -658,11 +512,17 @@ void POWER_EnterPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl * * !!! IMPORTANT NOTES : 0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API. - * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). - * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset) + * 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if + DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be + restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending). + * 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip + reset) */ -void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t wakeup_io_ctrl); +void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, + uint32_t sram_retention_ctrl, + uint64_t wakeup_interrupts, + uint32_t wakeup_io_ctrl); /** * @brief Configures and enters in SLEEP low power mode @@ -680,31 +540,29 @@ void POWER_EnterSleep(void); */ void POWER_SetVoltageForFreq(uint32_t system_freq_hz); -/*! - * @brief Power Library API to return the library version. - * - * @param none - * @return version number of the power library - */ -uint32_t POWER_GetLibVersion(void); - /** * @brief Sets board-specific trim values for 16MHz XTAL - * @param pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_16MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_16MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 + * @param pi32_16MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + * becomes 120 * @return none * @note Following default Values can be used: * pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600 * pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20 * pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 */ -extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, int32_t pi32_16MfXtalPPcbParCappF_x100, int32_t pi32_16MfXtalNPcbParCappF_x100); +extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, + int32_t pi32_16MfXtalPPcbParCappF_x100, + int32_t pi32_16MfXtalNPcbParCappF_x100); /** * @brief Sets board-specific trim values for 32kHz XTAL * @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 - * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120 + * @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + becomes 120 + * @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF + becomes 120 * @return none * @note Following default Values can be used: @@ -712,22 +570,38 @@ extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, int * pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40 * pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40 */ -extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, int32_t pi32_32kfXtalPPcbParCappF_x100, int32_t pi32_32kfXtalNPcbParCappF_x100); +extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, + int32_t pi32_32kfXtalPPcbParCappF_x100, + int32_t pi32_32kfXtalNPcbParCappF_x100); /** * @brief Enables and sets LDO for 16MHz XTAL - * @param none + * * @return none */ extern void POWER_SetXtal16mhzLdo(void); + /** - * @brief Set up 16-MHz XTAL Trimmings - * @param amp Amplitude - * @param gm Transconductance - * @return none + * @brief Return some key information related to the device reset causes / wake-up sources, for all power modes. + * @param p_reset_cause : the device reset cause, according to the definition of power_device_reset_cause_t type. + * @param p_boot_mode : the device boot mode, according to the definition of power_device_boot_mode_t type. + * @param p_wakeupio_cause: the wake-up pin sources, according to the definition of register PMC->WAKEIOCAUSE[3:0]. + + * @return Nothing + * + * !!! IMPORTANT ERRATA - IMPORTANT ERRATA - IMPORTANT ERRATA !!! + * !!! valid ONLY for LPC55S69 (not for LPC55S16 and LPC55S06) !!! + * !!! when FALLING EDGE DETECTION is enabled on wake-up pins: !!! + * - 1. p_wakeupio_cause is NOT ACCURATE + * - 2. Spurious kRESET_CAUSE_DPDRESET_WAKEUPIO* event is reported when + * several wake-up sources are enabled during DEEP-POWER-DOWN + * (like enabling wake-up on RTC and Falling edge wake-up pins) + * */ -extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm); +void POWER_GetWakeUpCause(power_device_reset_cause_t *p_reset_cause, + power_device_boot_mode_t *p_boot_mode, + uint32_t *p_wakeupio_cause); #ifdef __cplusplus - } +} #endif /** diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h index 573b6f3713..f17b891678 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad.h @@ -1,5 +1,5 @@ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -30,33 +30,33 @@ /*! @name Driver version */ /*@{*/ -#define FSL_POWERQUAD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ +#define FSL_POWERQUAD_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*!< Version. */ /*@}*/ #define PQ_FLOAT32 0U #define PQ_FIXEDPT 1U -#define CP_PQ 0U -#define CP_MTX 1U -#define CP_FFT 2U -#define CP_FIR 3U +#define CP_PQ 0U +#define CP_MTX 1U +#define CP_FFT 2U +#define CP_FIR 3U #define CP_CORDIC 5U -#define PQ_TRANS 0U -#define PQ_TRIG 1U +#define PQ_TRANS 0U +#define PQ_TRIG 1U #define PQ_BIQUAD 2U -#define PQ_TRANS_FIXED 4U -#define PQ_TRIG_FIXED 5U +#define PQ_TRANS_FIXED 4U +#define PQ_TRIG_FIXED 5U #define PQ_BIQUAD_FIXED 6U -#define PQ_INV 0U -#define PQ_LN 1U -#define PQ_SQRT 2U +#define PQ_INV 0U +#define PQ_LN 1U +#define PQ_SQRT 2U #define PQ_INVSQRT 3U -#define PQ_ETOX 4U -#define PQ_ETONX 5U -#define PQ_DIV 6U +#define PQ_ETOX 4U +#define PQ_ETONX 5U +#define PQ_DIV 6U #define PQ_SIN 0U #define PQ_COS 1U @@ -64,21 +64,21 @@ #define PQ_BIQ0_CALC 1U #define PQ_BIQ1_CALC 1U -#define PQ_COMP0_ONLY (0U << 1) -#define PQ_COMP1_ONLY (1U << 1) +#define PQ_COMP0_ONLY (0U << 1U) +#define PQ_COMP1_ONLY (1U << 1U) -#define CORDIC_ITER(x) (x << 2) -#define CORDIC_MIU(x) (x << 1) -#define CORDIC_T(x) (x << 0) -#define CORDIC_ARCTAN CORDIC_T(1) | CORDIC_MIU(0) -#define CORDIC_ARCTANH CORDIC_T(1) | CORDIC_MIU(1) +#define CORDIC_ITER(x) ((uint32_t)(x) << 2U) +#define CORDIC_MIU(x) ((uint32_t)(x) << 1U) +#define CORDIC_T(x) ((uint32_t)(x) << 0U) +#define CORDIC_ARCTAN CORDIC_T(1U) | CORDIC_MIU(0U) +#define CORDIC_ARCTANH CORDIC_T(1U) | CORDIC_MIU(1U) #define INST_BUSY 0x80000000U -#define PQ_ERRSTAT_OVERFLOW 0U -#define PQ_ERRSTAT_NAN 1U +#define PQ_ERRSTAT_OVERFLOW 0U +#define PQ_ERRSTAT_NAN 1U #define PQ_ERRSTAT_FIXEDOVERFLOW 2U -#define PQ_ERRSTAT_UNDERFLOW 3U +#define PQ_ERRSTAT_UNDERFLOW 3U #define PQ_TRANS_CFFT 0U #define PQ_TRANS_IFFT 1U @@ -88,71 +88,71 @@ #define PQ_TRANS_RDCT 6U #define PQ_MTX_SCALE 1U -#define PQ_MTX_MULT 2U -#define PQ_MTX_ADD 3U -#define PQ_MTX_INV 4U -#define PQ_MTX_PROD 5U -#define PQ_MTX_SUB 7U -#define PQ_VEC_DOTP 9U -#define PQ_MTX_TRAN 10U +#define PQ_MTX_MULT 2U +#define PQ_MTX_ADD 3U +#define PQ_MTX_INV 4U +#define PQ_MTX_PROD 5U +#define PQ_MTX_SUB 7U +#define PQ_VEC_DOTP 9U +#define PQ_MTX_TRAN 10U /* FIR engine operation type */ -#define PQ_FIR_FIR 0U +#define PQ_FIR_FIR 0U #define PQ_FIR_CONVOLUTION 1U #define PQ_FIR_CORRELATION 2U #define PQ_FIR_INCREMENTAL 4U -#define _pq_ln0(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_inv0(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_sqrt0(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_invsqrt0(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_etox0(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_etonx0(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) -#define _pq_sin0(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRIG) -#define _pq_cos0(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRIG) -#define _pq_biquad0(x) __arm_mcr(CP_PQ, PQ_BIQ0_CALC, x, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_BIQUAD) +#define _pq_ln0(x) __arm_mcr(CP_PQ, PQ_LN, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_inv0(x) __arm_mcr(CP_PQ, PQ_INV, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_sqrt0(x) __arm_mcr(CP_PQ, PQ_SQRT, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_invsqrt0(x) __arm_mcr(CP_PQ, PQ_INVSQRT, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_etox0(x) __arm_mcr(CP_PQ, PQ_ETOX, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_etonx0(x) __arm_mcr(CP_PQ, PQ_ETONX, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRANS) +#define _pq_sin0(x) __arm_mcr(CP_PQ, PQ_SIN, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRIG) +#define _pq_cos0(x) __arm_mcr(CP_PQ, PQ_COS, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_TRIG) +#define _pq_biquad0(x) __arm_mcr(CP_PQ, PQ_BIQ0_CALC, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP0_ONLY, 0, PQ_BIQUAD) -#define _pq_ln_fx0(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_inv_fx0(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sqrt_fx0(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_invsqrt_fx0(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etox_fx0(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etonx_fx0(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sin_fx0(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_cos_fx0(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_biquad0_fx(x) __arm_mcr(CP_PQ, PQ_BIQ0_CALC, x, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_BIQUAD_FIXED) +#define _pq_ln_fx0(x) __arm_mcr(CP_PQ, PQ_LN, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_inv_fx0(x) __arm_mcr(CP_PQ, PQ_INV, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_sqrt_fx0(x) __arm_mcr(CP_PQ, PQ_SQRT, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_invsqrt_fx0(x) __arm_mcr(CP_PQ, PQ_INVSQRT, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_etox_fx0(x) __arm_mcr(CP_PQ, PQ_ETOX, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_etonx_fx0(x) __arm_mcr(CP_PQ, PQ_ETONX, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_sin_fx0(x) __arm_mcr(CP_PQ, PQ_SIN, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRIG_FIXED) +#define _pq_cos_fx0(x) __arm_mcr(CP_PQ, PQ_COS, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_TRIG_FIXED) +#define _pq_biquad0_fx(x) __arm_mcr(CP_PQ, PQ_BIQ0_CALC, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP0_ONLY, 0, PQ_BIQUAD_FIXED) -#define _pq_div0(x) __arm_mcrr(CP_PQ, PQ_FLOAT32 | PQ_COMP0_ONLY, x, PQ_DIV) -#define _pq_div1(x) __arm_mcrr(CP_PQ, PQ_FLOAT32 | PQ_COMP1_ONLY, x, PQ_DIV) +#define _pq_div0(x) __arm_mcrr(CP_PQ, PQ_FLOAT32 | PQ_COMP0_ONLY, (uint64_t)(x), PQ_DIV) +#define _pq_div1(x) __arm_mcrr(CP_PQ, PQ_FLOAT32 | PQ_COMP1_ONLY, (uint64_t)(x), PQ_DIV) -#define _pq_ln1(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_inv1(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_sqrt1(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_invsqrt1(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_etox1(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_etonx1(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) -#define _pq_sin1(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRIG) -#define _pq_cos1(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRIG) -#define _pq_biquad1(x) __arm_mcr(CP_PQ, PQ_BIQ1_CALC, x, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_BIQUAD) +#define _pq_ln1(x) __arm_mcr(CP_PQ, PQ_LN, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_inv1(x) __arm_mcr(CP_PQ, PQ_INV, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_sqrt1(x) __arm_mcr(CP_PQ, PQ_SQRT, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_invsqrt1(x) __arm_mcr(CP_PQ, PQ_INVSQRT, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_etox1(x) __arm_mcr(CP_PQ, PQ_ETOX, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_etonx1(x) __arm_mcr(CP_PQ, PQ_ETONX, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRANS) +#define _pq_sin1(x) __arm_mcr(CP_PQ, PQ_SIN, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRIG) +#define _pq_cos1(x) __arm_mcr(CP_PQ, PQ_COS, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_TRIG) +#define _pq_biquad1(x) __arm_mcr(CP_PQ, PQ_BIQ1_CALC, (uint32_t)(x), PQ_FLOAT32 | PQ_COMP1_ONLY, 0, PQ_BIQUAD) -#define _pq_ln_fx1(x) __arm_mcr(CP_PQ, PQ_LN, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_inv_fx1(x) __arm_mcr(CP_PQ, PQ_INV, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sqrt_fx1(x) __arm_mcr(CP_PQ, PQ_SQRT, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_invsqrt_fx1(x) __arm_mcr(CP_PQ, PQ_INVSQRT, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etox_fx1(x) __arm_mcr(CP_PQ, PQ_ETOX, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_etonx_fx1(x) __arm_mcr(CP_PQ, PQ_ETONX, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) -#define _pq_sin_fx1(x) __arm_mcr(CP_PQ, PQ_SIN, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_cos_fx1(x) __arm_mcr(CP_PQ, PQ_COS, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRIG_FIXED) -#define _pq_biquad1_fx(x) __arm_mcr(CP_PQ, PQ_BIQ1_CALC, x, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_BIQUAD_FIXED) +#define _pq_ln_fx1(x) __arm_mcr(CP_PQ, PQ_LN, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_inv_fx1(x) __arm_mcr(CP_PQ, PQ_INV, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_sqrt_fx1(x) __arm_mcr(CP_PQ, PQ_SQRT, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_invsqrt_fx1(x) __arm_mcr(CP_PQ, PQ_INVSQRT, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_etox_fx1(x) __arm_mcr(CP_PQ, PQ_ETOX, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_etonx_fx1(x) __arm_mcr(CP_PQ, PQ_ETONX, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRANS_FIXED) +#define _pq_sin_fx1(x) __arm_mcr(CP_PQ, PQ_SIN, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRIG_FIXED) +#define _pq_cos_fx1(x) __arm_mcr(CP_PQ, PQ_COS, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_TRIG_FIXED) +#define _pq_biquad1_fx(x) __arm_mcr(CP_PQ, PQ_BIQ1_CALC, (uint32_t)(x), PQ_FIXEDPT | PQ_COMP1_ONLY, 0, PQ_BIQUAD_FIXED) -#define _pq_readMult0() __arm_mrc(CP_PQ, 0, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, 0) -#define _pq_readAdd0() __arm_mrc(CP_PQ, 1, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, 0) -#define _pq_readMult1() __arm_mrc(CP_PQ, 0, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, 0) -#define _pq_readAdd1() __arm_mrc(CP_PQ, 1, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, 0) +#define _pq_readMult0() __arm_mrc(CP_PQ, 0, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, 0) +#define _pq_readAdd0() __arm_mrc(CP_PQ, 1, PQ_FLOAT32 | PQ_COMP0_ONLY, 0, 0) +#define _pq_readMult1() __arm_mrc(CP_PQ, 0, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, 0) +#define _pq_readAdd1() __arm_mrc(CP_PQ, 1, PQ_FLOAT32 | PQ_COMP1_ONLY, 0, 0) #define _pq_readMult0_fx() __arm_mrc(CP_PQ, 0, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, 0) -#define _pq_readAdd0_fx() __arm_mrc(CP_PQ, 1, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, 0) +#define _pq_readAdd0_fx() __arm_mrc(CP_PQ, 1, PQ_FIXEDPT | PQ_COMP0_ONLY, 0, 0) #define _pq_readMult1_fx() __arm_mrc(CP_PQ, 0, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, 0) -#define _pq_readAdd1_fx() __arm_mrc(CP_PQ, 1, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, 0) +#define _pq_readAdd1_fx() __arm_mrc(CP_PQ, 1, PQ_FIXEDPT | PQ_COMP1_ONLY, 0, 0) /*! Parameter used for vector ln(x) */ #define PQ_LN_INF PQ_LN, 1, PQ_TRANS @@ -171,6 +171,14 @@ /*! Parameter used for vector cos(x) */ #define PQ_COS_INF PQ_COS, 1, PQ_TRIG +/* + * Workaround used in vector functions: + * + * 1. In floating sin/cos case, there must be at least 5 core clock cycles + * between MCR and following MRRC + * 2. In fixed sin/cos case, there must be one NOP between two MCR + */ + /* * Register assignment for the vector calculation assembly. * r0: pSrc, r1: pDest, r2-r7: Data @@ -201,6 +209,8 @@ __asm volatile("STRD r4,r5,[r1],#8"); /* store fourth two results */ \ } \ __asm volatile("LDMIA r0!,{r4-r5}"); /* load next 2 datas */ \ + __asm volatile("NOP"); \ + __asm volatile("NOP"); \ if (DOUBLE_READ_ADDERS) \ { \ __asm volatile("MRRC p0,#0,r2,r3,c1"); \ @@ -212,6 +222,8 @@ PQ_RUN_OPCODE_R5_R4(BATCH_OPCODE, BATCH_MACHINE); \ __asm volatile("STRD r2,r3,[r1],#8"); /* store first two results */ \ __asm volatile("LDMIA r0!,{r6-r7}"); /* load next 2 datas */ \ + __asm volatile("NOP"); \ + __asm volatile("NOP"); \ if (DOUBLE_READ_ADDERS) \ { \ __asm volatile("MRRC p0,#0,r4,r5,c1"); \ @@ -223,6 +235,8 @@ PQ_RUN_OPCODE_R7_R6(BATCH_OPCODE, BATCH_MACHINE); \ __asm volatile("STRD r4,r5,[r1],#8"); /* store second two results */ \ __asm volatile("LDRD r4,r5,[r0],#8"); /* load last 2 of the 8 */ \ + __asm volatile("NOP"); \ + __asm volatile("NOP"); \ if (DOUBLE_READ_ADDERS) \ { \ __asm volatile("MRRC p0,#0,r6,r7,c1"); \ @@ -240,7 +254,11 @@ else \ { \ __asm volatile("NOP"); \ + __asm volatile("NOP"); \ + __asm volatile("NOP"); \ } \ + __asm volatile("NOP"); \ + __asm volatile("NOP"); \ if (DOUBLE_READ_ADDERS) \ { \ __asm volatile("MRRC p0,#0,r4,r5,c1"); \ @@ -257,18 +275,21 @@ #define PQ_RUN_OPCODE_R2_R3(BATCH_OPCODE, BATCH_MACHINE) \ __asm volatile( \ " MCR p0,%[opcode],r2,c1,c0,%[machine] \n" \ + " NOP \n" \ " MCR p0,%[opcode],r3,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ [machine] "i"(BATCH_MACHINE)) #define PQ_RUN_OPCODE_R4_R5(BATCH_OPCODE, BATCH_MACHINE) \ __asm volatile( \ " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ + " NOP \n" \ " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ [machine] "i"(BATCH_MACHINE)) #define PQ_RUN_OPCODE_R6_R7(BATCH_OPCODE, BATCH_MACHINE) \ __asm volatile( \ " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ + " NOP \n" \ " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" ::[opcode] "i"(BATCH_OPCODE), \ [machine] "i"(BATCH_MACHINE)) @@ -338,8 +359,8 @@ * * Start the vector calculation, the input data could be float, int32_t or Q31. * - * @param PSRC Pointer to the source data. - * @param PDST Pointer to the destination data. + * @param pSrc Pointer to the source data. + * @param pDst Pointer to the destination data. */ #define PQ_Initiate_Vector_Func(pSrc, pDst) \ __asm volatile( \ @@ -525,7 +546,7 @@ __asm volatile( \ "1: \n" \ " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ - " ISB \n" \ + " NOP \n" \ " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" \ " CMP r3, #0 \n" \ " ITE NE \n" \ @@ -535,20 +556,20 @@ " MRC p0,%[dra],r4,c1,c0,#0 \n" \ " MRC p0,%[dra],r5,c3,c0,#0 \n" \ " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " ISB \n" \ + " NOP \n" \ " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ " STRD r4,r5,[r1],#8 \n" /* store first two results */ \ " MRC p0,%[dra],r6,c1,c0,#0 \n" \ " MRC p0,%[dra],r7,c3,c0,#0 \n" \ " MCR p0,%[opcode],r8,c1,c0,%[machine] \n" \ - " ISB \n" \ + " NOP \n" \ " MCR p0,%[opcode],r9,c3,c0,%[machine] \n" \ " STRD r6,r7,[r1],#8 \n" /* store second two results */ \ " LDRD r6,r7,[r0],#8 \n" /* load last 2 of the 8 */ \ " MRC p0,%[dra],r8,c1,c0,#0 \n" \ " MRC p0,%[dra],r9,c3,c0,#0 \n" \ " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " ISB \n" \ + " NOP \n" \ " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ " STRD r8,r9,[r1],#8 \n" /* store third two results */ \ " SUBS r2, r2, #8 \n" /* length -= 8; if (length != 0) */ \ @@ -657,7 +678,7 @@ __asm volatile( \ "1: \n" \ " MCR p0,%[opcode],r4,c1,c0,%[machine] \n" \ - " ISB \n" \ + " NOP \n" \ " MCR p0,%[opcode],r5,c3,c0,%[machine] \n" \ " CMP r3, #0 \n" \ " ITTTE NE \n" \ @@ -671,7 +692,7 @@ " MRC p0,%[dra],r4,c1,c0,#0 \n" \ " MRC p0,%[dra],r5,c3,c0,#0 \n" \ " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " ISB \n" \ + " NOP \n" \ " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ " LSR r4,r4,#16 \n" /* store first two results */ \ " BFI r5,r4,#0,#16 \n" /* store first two results */ \ @@ -682,7 +703,7 @@ " MRC p0,%[dra],r6,c1,c0,#0 \n" \ " MRC p0,%[dra],r7,c3,c0,#0 \n" \ " MCR p0,%[opcode],r8,c1,c0,%[machine] \n" \ - " ISB \n" \ + " NOP \n" \ " MCR p0,%[opcode],r9,c3,c0,%[machine] \n" \ " LSR r6,r6,#16 \n" /* store second two results */ \ " BFI r7,r6,#0,#16 \n" /* store second two results */ \ @@ -693,7 +714,7 @@ " MRC p0,%[dra],r8,c1,c0,#0 \n" \ " MRC p0,%[dra],r9,c3,c0,#0 \n" \ " MCR p0,%[opcode],r6,c1,c0,%[machine] \n" \ - " ISB \n" \ + " NOP \n" \ " MCR p0,%[opcode],r7,c3,c0,%[machine] \n" \ " LSR r8,r8,#16 \n" /* store third two results */ \ " BFI r9,r8,#0,#16 \n" /* store third two results */ \ @@ -1641,7 +1662,7 @@ typedef enum typedef union _pq_float { float floatX; /*!< Float type.*/ - uint32_t integerX; /*!< Iterger type.*/ + uint32_t integerX; /*!< Unsigned interger type.*/ } pq_float_t; /******************************************************************************* @@ -1665,7 +1686,7 @@ extern "C" { * Bits[15:8] scaler (for scaled 'q31' formats) * Bits[5:4] external format. 00b=q15, 01b=q31, 10b=float * Bits[1:0] internal format. 00b=q15, 01b=q31, 10b=float - * POWERQUAD->INAFORMAT = (config->inputAPrescale << 8) | (config->inputAFormat << 4) | config->machineFormat + * POWERQUAD->INAFORMAT = (config->inputAPrescale << 8U) | (config->inputAFormat << 4U) | config->machineFormat * * For all Powerquad operations internal format must be float (with the only exception being * the FFT related functions, ie FFT/IFFT/DCT/IDCT which must be set to q31). @@ -1702,7 +1723,7 @@ void PQ_SetConfig(POWERQUAD_Type *base, const pq_config_t *config); */ static inline void PQ_SetCoprocessorScaler(POWERQUAD_Type *base, const pq_prescale_t *prescale) { - assert(prescale); + assert(NULL != prescale); base->CPPRE = POWERQUAD_CPPRE_CPPRE_IN(prescale->inputPrescale) | POWERQUAD_CPPRE_CPPRE_OUT(prescale->outputPrescale) | @@ -1754,8 +1775,12 @@ static inline void PQ_WaitDone(POWERQUAD_Type *base) */ static inline void PQ_LnF32(float *pSrc, float *pDst) { - _pq_ln0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readAdd0(); + pq_float_t val; + + val.floatX = *pSrc; + _pq_ln0(val.integerX); + val.integerX = _pq_readAdd0(); + *pDst = val.floatX; } /*! @@ -1766,8 +1791,12 @@ static inline void PQ_LnF32(float *pSrc, float *pDst) */ static inline void PQ_InvF32(float *pSrc, float *pDst) { - _pq_inv0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readMult0(); + pq_float_t val; + + val.floatX = *pSrc; + _pq_inv0(val.integerX); + val.integerX = _pq_readMult0(); + *pDst = val.floatX; } /*! @@ -1778,8 +1807,12 @@ static inline void PQ_InvF32(float *pSrc, float *pDst) */ static inline void PQ_SqrtF32(float *pSrc, float *pDst) { - _pq_sqrt0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readMult0(); + pq_float_t val; + + val.floatX = *pSrc; + _pq_sqrt0(val.integerX); + val.integerX = _pq_readMult0(); + *pDst = val.floatX; } /*! @@ -1790,8 +1823,12 @@ static inline void PQ_SqrtF32(float *pSrc, float *pDst) */ static inline void PQ_InvSqrtF32(float *pSrc, float *pDst) { - _pq_invsqrt0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readMult0(); + pq_float_t val; + + val.floatX = *pSrc; + _pq_invsqrt0(val.integerX); + val.integerX = _pq_readMult0(); + *pDst = val.floatX; } /*! @@ -1802,8 +1839,12 @@ static inline void PQ_InvSqrtF32(float *pSrc, float *pDst) */ static inline void PQ_EtoxF32(float *pSrc, float *pDst) { - _pq_etox0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readMult0(); + pq_float_t val; + + val.floatX = *pSrc; + _pq_etox0(val.integerX); + val.integerX = _pq_readMult0(); + *pDst = val.floatX; } /*! @@ -1814,8 +1855,12 @@ static inline void PQ_EtoxF32(float *pSrc, float *pDst) */ static inline void PQ_EtonxF32(float *pSrc, float *pDst) { - _pq_etonx0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readMult0(); + pq_float_t val; + + val.floatX = *pSrc; + _pq_etonx0(val.integerX); + val.integerX = _pq_readMult0(); + *pDst = val.floatX; } /*! @@ -1827,8 +1872,12 @@ static inline void PQ_EtonxF32(float *pSrc, float *pDst) */ static inline void PQ_SinF32(float *pSrc, float *pDst) { - _pq_sin0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readAdd0(); + pq_float_t val; + + val.floatX = *pSrc; + _pq_sin0(val.integerX); + val.integerX = _pq_readAdd0(); + *pDst = val.floatX; } /*! @@ -1840,8 +1889,12 @@ static inline void PQ_SinF32(float *pSrc, float *pDst) */ static inline void PQ_CosF32(float *pSrc, float *pDst) { - _pq_cos0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readAdd0(); + pq_float_t val; + + val.floatX = *pSrc; + _pq_cos0(val.integerX); + val.integerX = _pq_readAdd0(); + *pDst = val.floatX; } /*! @@ -1852,8 +1905,12 @@ static inline void PQ_CosF32(float *pSrc, float *pDst) */ static inline void PQ_BiquadF32(float *pSrc, float *pDst) { - _pq_biquad0(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readAdd0(); + pq_float_t val; + + val.floatX = *pSrc; + _pq_biquad0(val.integerX); + val.integerX = _pq_readAdd0(); + *pDst = val.floatX; } /*! @@ -1867,12 +1924,16 @@ static inline void PQ_BiquadF32(float *pSrc, float *pDst) */ static inline void PQ_DivF32(float *x1, float *x2, float *pDst) { - uint32_t X1 = *(uint32_t *)x1; - uint32_t X2 = *(uint32_t *)x2; - uint64_t input = (uint64_t)(X2) | ((uint64_t)(X1) << 32U); + pq_float_t X1; + pq_float_t X2; + + X1.floatX = *x1; + X2.floatX = *x2; + uint64_t input = (uint64_t)(X2.integerX) | ((uint64_t)(X1.integerX) << 32U); _pq_div0(input); - *(int32_t *)pDst = _pq_readMult0(); + X1.integerX = _pq_readMult0(); + *pDst = X1.floatX; } /*! @@ -1883,8 +1944,12 @@ static inline void PQ_DivF32(float *x1, float *x2, float *pDst) */ static inline void PQ_Biquad1F32(float *pSrc, float *pDst) { - _pq_biquad1(*(int32_t *)pSrc); - *(int32_t *)pDst = _pq_readAdd1(); + pq_float_t val; + + val.floatX = *pSrc; + _pq_biquad1(val.integerX); + val.integerX = _pq_readAdd1(); + *pDst = val.floatX; } /*! @@ -1896,7 +1961,7 @@ static inline void PQ_Biquad1F32(float *pSrc, float *pDst) static inline int32_t PQ_LnFixed(int32_t val) { _pq_ln_fx0(val); - return _pq_readAdd0_fx(); + return (int32_t)_pq_readAdd0_fx(); } /*! @@ -1908,7 +1973,7 @@ static inline int32_t PQ_LnFixed(int32_t val) static inline int32_t PQ_InvFixed(int32_t val) { _pq_inv_fx0(val); - return _pq_readMult0_fx(); + return (int32_t)_pq_readMult0_fx(); } /*! @@ -1932,7 +1997,7 @@ static inline uint32_t PQ_SqrtFixed(uint32_t val) static inline int32_t PQ_InvSqrtFixed(int32_t val) { _pq_invsqrt_fx0(val); - return _pq_readMult0_fx(); + return (int32_t)_pq_readMult0_fx(); } /*! @@ -1944,7 +2009,7 @@ static inline int32_t PQ_InvSqrtFixed(int32_t val) static inline int32_t PQ_EtoxFixed(int32_t val) { _pq_etox_fx0(val); - return _pq_readMult0_fx(); + return (int32_t)_pq_readMult0_fx(); } /*! @@ -1956,7 +2021,7 @@ static inline int32_t PQ_EtoxFixed(int32_t val) static inline int32_t PQ_EtonxFixed(int32_t val) { _pq_etonx_fx0(val); - return _pq_readMult0_fx(); + return (int32_t)_pq_readMult0_fx(); } /*! @@ -1983,11 +2048,11 @@ static inline int32_t PQ_SinQ31(int32_t val) #if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA _pq_sin0(valFloat.integerX); - ret = _pq_readAdd0(); - ret = _pq_readAdd0_fx(); + (void)_pq_readAdd0(); + ret = (int32_t)_pq_readAdd0_fx(); #else _pq_sin_fx0(val); - ret = _pq_readAdd0_fx(); + ret = (int32_t)_pq_readAdd0_fx(); #endif POWERQUAD->CPPRE = cppre; @@ -2003,14 +2068,14 @@ static inline int32_t PQ_SinQ31(int32_t val) */ static inline int16_t PQ_SinQ15(int16_t val) { - int32_t ret; + uint32_t ret; uint32_t cppre; #if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA pq_float_t magic; pq_float_t valFloat; - magic.integerX = 0x30c90fdb; - valFloat.floatX = magic.floatX * (float)(val << 16); + magic.integerX = 0x30c90fdbU; + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)val << 16U); #endif cppre = POWERQUAD->CPPRE; @@ -2020,12 +2085,11 @@ static inline int16_t PQ_SinQ15(int16_t val) #if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA _pq_sin0(valFloat.integerX); - ret = _pq_readAdd0(); - ret = _pq_readAdd0_fx(); - ret >>= 16; + (void)_pq_readAdd0(); + ret = (_pq_readAdd0_fx() >> 16U); #else - _pq_sin_fx0((uint32_t)val << 16); - ret = (_pq_readAdd0_fx()) >> 16; + _pq_sin_fx0((uint32_t)val << 16U); + ret = (_pq_readAdd0_fx() >> 16U); #endif POWERQUAD->CPPRE = cppre; @@ -2057,11 +2121,11 @@ static inline int32_t PQ_CosQ31(int32_t val) #if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA _pq_cos0(valFloat.integerX); - ret = _pq_readAdd0(); - ret = _pq_readAdd0_fx(); + (void)_pq_readAdd0(); + ret = (int32_t)_pq_readAdd0_fx(); #else _pq_cos_fx0(val); - ret = _pq_readAdd0_fx(); + ret = (int32_t)_pq_readAdd0_fx(); #endif POWERQUAD->CPPRE = cppre; @@ -2077,14 +2141,14 @@ static inline int32_t PQ_CosQ31(int32_t val) */ static inline int16_t PQ_CosQ15(int16_t val) { - int32_t ret; + uint32_t ret; uint32_t cppre; #if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA pq_float_t magic; pq_float_t valFloat; - magic.integerX = 0x30c90fdb; - valFloat.floatX = magic.floatX * (float)(val << 16); + magic.integerX = 0x30c90fdbU; + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)val << 16U); #endif cppre = POWERQUAD->CPPRE; @@ -2093,12 +2157,11 @@ static inline int16_t PQ_CosQ15(int16_t val) #if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA _pq_cos0(valFloat.integerX); - ret = _pq_readAdd0(); - ret = _pq_readAdd0_fx(); - ret >>= 16; + (void)_pq_readAdd0(); + ret = _pq_readAdd0_fx() >> 16U; #else - _pq_cos_fx0((uint32_t)val << 16); - ret = (_pq_readAdd0_fx()) >> 16; + _pq_cos_fx0((uint32_t)val << 16U); + ret = _pq_readAdd0_fx() >> 16U; #endif POWERQUAD->CPPRE = cppre; @@ -2115,7 +2178,7 @@ static inline int16_t PQ_CosQ15(int16_t val) static inline int32_t PQ_BiquadFixed(int32_t val) { _pq_biquad0_fx(val); - return _pq_readAdd0_fx(); + return (int32_t)_pq_readAdd0_fx(); } /*! @@ -2348,7 +2411,7 @@ void PQ_VectorBiqaudDf2F32(float *pSrc, float *pDst, int32_t length); * * @param *pSrc points to the block of input data * @param *pDst points to the block of output data - * @param blocksSize the block size of input data + * @param length the block size of input data */ void PQ_VectorBiqaudDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length); @@ -2357,7 +2420,7 @@ void PQ_VectorBiqaudDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length); * * @param *pSrc points to the block of input data * @param *pDst points to the block of output data - * @param blocksSize the block size of input data + * @param length the block size of input data */ void PQ_VectorBiqaudDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length); @@ -2366,7 +2429,7 @@ void PQ_VectorBiqaudDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length); * * @param *pSrc points to the block of input data * @param *pDst points to the block of output data - * @param blocksSize the block size of input data + * @param length the block size of input data */ void PQ_VectorBiqaudCascadeDf2F32(float *pSrc, float *pDst, int32_t length); @@ -2375,7 +2438,7 @@ void PQ_VectorBiqaudCascadeDf2F32(float *pSrc, float *pDst, int32_t length); * * @param *pSrc points to the block of input data * @param *pDst points to the block of output data - * @param blocksSize the block size of input data + * @param length the block size of input data */ void PQ_VectorBiqaudCascadeDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length); @@ -2384,7 +2447,7 @@ void PQ_VectorBiqaudCascadeDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t leng * * @param *pSrc points to the block of input data * @param *pDst points to the block of output data - * @param blocksSize the block size of input data + * @param length the block size of input data */ void PQ_VectorBiqaudCascadeDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length); @@ -2427,7 +2490,7 @@ int32_t PQ_ArctanhFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_it static inline int32_t PQ_Biquad1Fixed(int32_t val) { _pq_biquad1_fx(val); - return _pq_readAdd1_fx(); + return (int32_t)_pq_readAdd1_fx(); } /*! @@ -2564,8 +2627,13 @@ void PQ_BiquadCascadeDf2Fixed16(const pq_biquad_cascade_df2_instance *S, * @param pResult array for the output data * @param opType operation type, could be PQ_FIR_FIR, PQ_FIR_CONVOLUTION, PQ_FIR_CORRELATION. */ -void PQ_FIR( - POWERQUAD_Type *base, void *pAData, int32_t ALength, void *pBData, int32_t BLength, void *pResult, uint32_t opType); +void PQ_FIR(POWERQUAD_Type *base, + const void *pAData, + int32_t ALength, + const void *pBData, + int32_t BLength, + void *pResult, + uint32_t opType); /*! * @brief Processing function for the incremental FIR. @@ -2575,7 +2643,7 @@ void PQ_FIR( * @param base POWERQUAD peripheral base address * @param ALength number of input samples * @param BLength number of taps - * @param xoffset offset for number of input samples + * @param xOffset offset for number of input samples */ void PQ_FIRIncrement(POWERQUAD_Type *base, int32_t ALength, int32_t BLength, int32_t xOffset); @@ -2693,7 +2761,7 @@ void PQ_MatrixTranspose(POWERQUAD_Type *base, uint32_t length, void *pData, void * @param pData input matrix * @param pResult array for the output data. */ -void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, void *pData, void *pResult); +void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, const void *pData, void *pResult); /* @} */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_basic.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_basic.c index a389b7bd06..3a1de44b62 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_basic.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_basic.c @@ -1,5 +1,5 @@ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -30,31 +30,35 @@ void PQ_GetDefaultConfig(pq_config_t *config) config->tmpFormat = kPQ_Float; config->tmpPrescale = 0; config->machineFormat = kPQ_Float; - config->tmpBase = (uint32_t *)0xE0000000; + config->tmpBase = (uint32_t *)0xE0000000U; } void PQ_SetConfig(POWERQUAD_Type *base, const pq_config_t *config) { - assert(config); + assert(NULL != config); - base->TMPBASE = (uint32_t)config->tmpBase; - base->INAFORMAT = - ((uint32_t)config->inputAPrescale << 8U) | ((uint32_t)config->inputAFormat << 4U) | config->machineFormat; - base->INBFORMAT = - ((uint32_t)config->inputBPrescale << 8U) | ((uint32_t)config->inputBFormat << 4U) | config->machineFormat; + base->TMPBASE = (uint32_t)config->tmpBase; + base->INAFORMAT = ((uint32_t)config->inputAPrescale << 8U) | ((uint32_t)config->inputAFormat << 4U) | + (uint32_t)config->machineFormat; + base->INBFORMAT = ((uint32_t)config->inputBPrescale << 8U) | ((uint32_t)config->inputBFormat << 4U) | + (uint32_t)config->machineFormat; base->TMPFORMAT = - ((uint32_t)config->tmpPrescale << 8U) | ((uint32_t)config->tmpFormat << 4U) | config->machineFormat; - base->OUTFORMAT = - ((uint32_t)config->outputPrescale << 8U) | ((uint32_t)config->outputFormat << 4U) | config->machineFormat; + ((uint32_t)config->tmpPrescale << 8U) | ((uint32_t)config->tmpFormat << 4U) | (uint32_t)config->machineFormat; + base->OUTFORMAT = ((uint32_t)config->outputPrescale << 8U) | ((uint32_t)config->outputFormat << 4U) | + (uint32_t)config->machineFormat; } void PQ_Init(POWERQUAD_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(POWERQUAD_CLOCKS) CLOCK_EnableClock(kCLOCK_PowerQuad); #endif +#endif #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) +#if defined(POWERQUAD_RSTS) RESET_PeripheralReset(kPOWERQUAD_RST_SHIFT_RSTn); +#endif #endif /* Enable event used for WFE. */ @@ -66,8 +70,10 @@ void PQ_Init(POWERQUAD_Type *base) void PQ_Deinit(POWERQUAD_Type *base) { #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) +#if defined(POWERQUAD_CLOCKS) CLOCK_DisableClock(kCLOCK_PowerQuad); #endif +#endif } void PQ_SetFormat(POWERQUAD_Type *base, pq_computationengine_t engine, pq_format_t format) @@ -113,7 +119,7 @@ void PQ_SetFormat(POWERQUAD_Type *base, pq_computationengine_t engine, pq_format config.tmpPrescale = 0; } - if (CP_FFT == engine) + if (CP_FFT == (uint8_t)engine) { config.machineFormat = kPQ_32Bit; } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_cmsis.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_cmsis.c index 6353347e0f..fd34d1ade6 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_cmsis.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_cmsis.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -18,90 +18,96 @@ #define FSL_COMPONENT_ID "platform.drivers.powerquad_cmsis" #endif -#define PQ_SET_FIX32_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000 +#define PQ_SET_FIX32_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000U -#define PQ_SET_FIX16_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000 +#define PQ_SET_FIX16_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000U -#define PQ_SET_Q31_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(-31) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000 +#define PQ_SET_Q31_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(-31) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000U -#define PQ_SET_Q15_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(-15) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000 +#define PQ_SET_Q15_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(-15) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000U -#define PQ_SET_F32_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000 +#define PQ_SET_F32_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000U -#define PQ_SET_FFT_Q31_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_32Bit; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_32Bit; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_32Bit; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_32Bit; \ - POWERQUAD->TMPBASE = 0xE0000000 +#define PQ_SET_FFT_Q31_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_32Bit; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_32Bit; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_32Bit; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_32Bit; \ + POWERQUAD->TMPBASE = 0xE0000000U -#define PQ_SET_FFT_Q15_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_32Bit; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_32Bit; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_32Bit; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_32Bit; \ - POWERQUAD->TMPBASE = 0xE0000000 +#define PQ_SET_FFT_Q15_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_32Bit; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_32Bit; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_32Bit; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_32Bit; \ + POWERQUAD->TMPBASE = 0xE0000000U -#define PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000 +#define PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000U -#define PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000 +#define PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_32Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000U -#define PQ_SET_MAT_FIX16_WORKAROUND_SCALE_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000 +#define PQ_SET_MAT_FIX16_WORKAROUND_SCALE_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000U -#define PQ_SET_MAT_FIX16_WORKAROUND_MULT_CONFIG \ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; \ - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; \ - POWERQUAD->TMPBASE = 0xE0000000 +#define PQ_SET_MAT_FIX16_WORKAROUND_MULT_CONFIG \ + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; \ + POWERQUAD->TMPBASE = 0xE0000000U /******************************************************************************* * Code ******************************************************************************/ -static void _arm_fir_increment(void *pSrc, uint16_t srcLen, void *pTap, uint16_t tapLen, void *pDst, uint32_t offset) +static void _arm_fir_increment(const void *pSrc, + uint32_t srcLen, + const void *pTap, + uint16_t tapLen, + void *pDst, + uint32_t offset, + uint32_t elemSize) { - POWERQUAD->INABASE = (uint32_t)pSrc; - POWERQUAD->INBBASE = (uint32_t)pTap; - POWERQUAD->LENGTH = ((uint32_t)tapLen << 16U) + srcLen; - POWERQUAD->OUTBASE = (uint32_t)pDst; + POWERQUAD->INABASE = ((uint32_t)(const uint32_t *)pSrc) - (offset * elemSize); + POWERQUAD->INBBASE = (uint32_t)(const uint32_t *)pTap; + POWERQUAD->LENGTH = (((uint32_t)tapLen & 0xFFFFUL) << 16U) + (srcLen & 0xFFFFUL); + POWERQUAD->OUTBASE = ((uint32_t)(uint32_t *)pDst) - (offset * elemSize); POWERQUAD->MISC = offset; - POWERQUAD->CONTROL = (CP_FIR << 4) | PQ_FIR_INCREMENTAL; + POWERQUAD->CONTROL = (CP_FIR << 4U) | PQ_FIR_INCREMENTAL; } float32_t arm_cos_f32(float32_t x) @@ -155,52 +161,58 @@ q15_t arm_sin_q15(q15_t x) arm_status arm_sqrt_q31(q31_t in, q31_t *pOut) { uint32_t cppre; + arm_status status; /* If the input is a positive number then compute the signBits. */ if (in > 0) { cppre = POWERQUAD->CPPRE; POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_IN(-31) | POWERQUAD_CPPRE_CPPRE_OUT(31); - *pOut = PQ_SqrtFixed(in); + *pOut = (q31_t)PQ_SqrtFixed((uint32_t)in); POWERQUAD->CPPRE = cppre; - return (ARM_MATH_SUCCESS); + status = (ARM_MATH_SUCCESS); } /* If the number is a negative number then store zero as its square root value */ else { *pOut = 0; - return (ARM_MATH_ARGUMENT_ERROR); + status = (ARM_MATH_ARGUMENT_ERROR); } + + return status; } arm_status arm_sqrt_q15(q15_t in, q15_t *pOut) { uint32_t cppre; + arm_status status; /* If the input is a positive number then compute the signBits. */ if (in > 0) { cppre = POWERQUAD->CPPRE; POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_IN(-15) | POWERQUAD_CPPRE_CPPRE_OUT(15); - *pOut = PQ_SqrtFixed(in); + *pOut = (q15_t)PQ_SqrtFixed((uint32_t)in); POWERQUAD->CPPRE = cppre; - return (ARM_MATH_SUCCESS); + status = (ARM_MATH_SUCCESS); } /* If the number is a negative number then store zero as its square root value */ else { *pOut = 0; - return (ARM_MATH_ARGUMENT_ERROR); + status = (ARM_MATH_ARGUMENT_ERROR); } + + return status; } void arm_cfft_q31(const arm_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag) { - assert(bitReverseFlag == 1); + assert(bitReverseFlag == 1U); q31_t *pIn = p1; q31_t *pOut = p1; @@ -222,7 +234,7 @@ void arm_cfft_q31(const arm_cfft_instance_q31 *S, q31_t *p1, uint8_t ifftFlag, u void arm_cfft_q15(const arm_cfft_instance_q15 *S, q15_t *p1, uint8_t ifftFlag, uint8_t bitReverseFlag) { - assert(bitReverseFlag == 1); + assert(bitReverseFlag == 1U); q15_t *pIn = p1; q15_t *pOut = p1; @@ -245,8 +257,8 @@ void arm_cfft_q15(const arm_cfft_instance_q15 *S, q15_t *p1, uint8_t ifftFlag, u arm_status arm_rfft_init_q31(arm_rfft_instance_q31 *S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag) { /* Only supprt such mode. */ - assert(ifftFlagR == 0); - assert(bitReverseFlag == 1); + assert(ifftFlagR == 0U); + assert(bitReverseFlag == 1U); /* Initialise the default arm status */ arm_status status = ARM_MATH_SUCCESS; @@ -278,8 +290,8 @@ void arm_rfft_q31(const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst) arm_status arm_rfft_init_q15(arm_rfft_instance_q15 *S, uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag) { /* Only supprt such mode. */ - assert(ifftFlagR == 0); - assert(bitReverseFlag == 1); + assert(ifftFlagR == 0U); + assert(bitReverseFlag == 1U); /* Initialise the default arm status */ arm_status status = ARM_MATH_SUCCESS; @@ -315,6 +327,8 @@ arm_status arm_dct4_init_q31(arm_dct4_instance_q31 *S, uint16_t Nby2, q31_t normalize) { + arm_status status = ARM_MATH_SUCCESS; + /* Initialize the DCT4 length */ S->N = N; @@ -355,24 +369,28 @@ arm_status arm_dct4_init_q31(arm_dct4_instance_q31 *S, break; default: - return ARM_MATH_ARGUMENT_ERROR; + status = ARM_MATH_ARGUMENT_ERROR; + break; } - /* Initialize the RFFT/RIFFT Function */ - arm_rfft_init_q31(S->pRfft, S->N, 0, 1); + if (ARM_MATH_SUCCESS == status) + { + /* Initialize the RFFT/RIFFT Function */ + status = arm_rfft_init_q31(S->pRfft, S->N, 0, 1); + } - return ARM_MATH_SUCCESS; + return status; } void arm_dct4_q31(const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer) { /* Calculate DCT-II for N-point input */ - uint16_t i; /* Loop counter */ - q31_t *weights; /* Pointer to the Weights table */ - q31_t *pOut; /* Temporary pointers for output buffer */ - q31_t *pS1, *pbuff; /* Temporary pointers for input buffer and pState buffer */ - q31_t in; /* Temporary variable */ - q31_t *cosFact; + uint16_t i; /* Loop counter */ + const q31_t *weights; /* Pointer to the Weights table */ + q31_t *pOut; /* Temporary pointers for output buffer */ + q31_t *pS1, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q31_t in; /* Temporary variable */ + const q31_t *cosFact; uint32_t length; uint8_t matRow; uint8_t matCol; @@ -391,31 +409,31 @@ void arm_dct4_q31(const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineB * Use matrix production function for preprocessing. Matrix production * supports 16x16 at the most, so the matrix row is set to 16. */ - matRow = 16; - lenPerMatLoop = S->N >= 256 ? 256 : S->N; - matCol = lenPerMatLoop / 16; - matLoop = ((S->N - 1) >> 8) + 1; + matRow = 16U; + lenPerMatLoop = S->N >= 256U ? 256U : S->N; + matCol = (uint8_t)(lenPerMatLoop / 16U); + matLoop = (uint8_t)(((S->N - 1U) >> 8U) + 1U); cosFact = S->pCosFactor; pbuff = pInlineBuffer; length = POWERQUAD_MAKE_MATRIX_LEN(matRow, matCol, matCol); - while (matLoop--) + while ((matLoop--) != 0U) { PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; /* cos factor is Q31, convert to float */ - PQ_MatrixScale(POWERQUAD, length, 2.0f / 2147483648.0f, cosFact, (void *)0xE0000000); - cosFact += lenPerMatLoop; + PQ_MatrixScale(POWERQUAD, length, 2.0f / 2147483648.0f, cosFact, (void *)(uint32_t *)0xE0000000U); + cosFact = &cosFact[lenPerMatLoop]; PQ_WaitDone(POWERQUAD); /* Product. */ PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG; - PQ_MatrixProduct(POWERQUAD, length, pbuff, (void *)0xE0000000, pbuff); + PQ_MatrixProduct(POWERQUAD, length, pbuff, (void *)(uint32_t *)0xE0000000U, pbuff); - pbuff += lenPerMatLoop; + pbuff = &pbuff[lenPerMatLoop]; PQ_WaitDone(POWERQUAD); } @@ -429,9 +447,9 @@ void arm_dct4_q31(const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineB * Use matrix production function for twiddle multiplication. * Matrix production supports 16x16 at the most. The total elements are 2*N; */ - lenPerMatLoop = S->N >= 128 ? 128 : S->N; - matCol = lenPerMatLoop / 8; - matLoop = ((S->N - 1) >> 7) + 1; + lenPerMatLoop = S->N >= 128U ? 128U : S->N; + matCol = (uint8_t)(lenPerMatLoop / 8U); + matLoop = (uint8_t)(((S->N - 1U) >> 7U) + 1U); weights = S->pTwiddle; pOut = pState; @@ -439,33 +457,33 @@ void arm_dct4_q31(const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineB PQ_WaitDone(POWERQUAD); - while (matLoop--) + while ((matLoop--) != 0U) { PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; /* Downscale by 1024 * 1024 * 16, because the twiddle are multiplied by 1024 * 1024 * 16. */ - PQ_MatrixScale(POWERQUAD, length, 1.0f / 16777216.0f, weights, (void *)0xE0000000); - weights += lenPerMatLoop * 2; + PQ_MatrixScale(POWERQUAD, length, 1.0f / 16777216.0f, weights, (void *)(uint32_t *)0xE0000000U); + weights = &weights[lenPerMatLoop * 2U]; PQ_WaitDone(POWERQUAD); /* Product. */ PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG; - PQ_MatrixProduct(POWERQUAD, length, pOut, (void *)0xE0000000, pOut); + PQ_MatrixProduct(POWERQUAD, length, pOut, (void *)(uint32_t *)0xE0000000U, pOut); PQ_WaitDone(POWERQUAD); - for (i = 0; i < lenPerMatLoop / 4; i++) + for (i = 0; i < lenPerMatLoop / 4U; i++) { - *pOut -= *(pOut + 1); - pOut += 2; - *pOut -= *(pOut + 1); - pOut += 2; - *pOut -= *(pOut + 1); - pOut += 2; - *pOut -= *(pOut + 1); - pOut += 2; + pOut[0] -= pOut[1]; + pOut = &pOut[2]; + pOut[0] -= pOut[1]; + pOut = &pOut[2]; + pOut[0] -= pOut[1]; + pOut = &pOut[2]; + pOut[0] -= pOut[1]; + pOut = &pOut[2]; } } @@ -482,41 +500,41 @@ void arm_dct4_q31(const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineB pS1 = pState; /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2. Considering the DCT II normalize, here divided by sqrt(2).*/ - in = (q31_t)((float)*pS1 / 1.41421356237f); + in = (q31_t)(float)((float)*pS1 / 1.41421356237f); *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; - i = S->N / 4 - 1; + i = S->N / 4U - 1U; while (i > 0U) { in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; i--; } @@ -529,6 +547,8 @@ arm_status arm_dct4_init_q15(arm_dct4_instance_q15 *S, uint16_t Nby2, q15_t normalize) { + arm_status status = ARM_MATH_SUCCESS; + /* Initialize the DCT4 length */ S->N = N; @@ -539,55 +559,59 @@ arm_status arm_dct4_init_q15(arm_dct4_instance_q15 *S, { /* Initialize the table modifier values */ case 512U: - S->pTwiddle = (q15_t *)dct512_twiddle; - S->pCosFactor = (q15_t *)dct512_cosFactor; + S->pTwiddle = (void *)dct512_twiddle; + S->pCosFactor = (void *)dct512_cosFactor; break; case 256U: - S->pTwiddle = (q15_t *)dct256_twiddle; - S->pCosFactor = (q15_t *)dct256_cosFactor; + S->pTwiddle = (void *)dct256_twiddle; + S->pCosFactor = (void *)dct256_cosFactor; break; case 128U: - S->pTwiddle = (q15_t *)dct128_twiddle; - S->pCosFactor = (q15_t *)dct128_cosFactor; + S->pTwiddle = (void *)dct128_twiddle; + S->pCosFactor = (void *)dct128_cosFactor; break; case 64U: - S->pTwiddle = (q15_t *)dct64_twiddle; - S->pCosFactor = (q15_t *)dct64_cosFactor; + S->pTwiddle = (void *)dct64_twiddle; + S->pCosFactor = (void *)dct64_cosFactor; break; case 32U: - S->pTwiddle = (q15_t *)dct32_twiddle; - S->pCosFactor = (q15_t *)dct32_cosFactor; + S->pTwiddle = (void *)dct32_twiddle; + S->pCosFactor = (void *)dct32_cosFactor; break; case 16U: - S->pTwiddle = (q15_t *)dct16_twiddle; - S->pCosFactor = (q15_t *)dct16_cosFactor; + S->pTwiddle = (void *)dct16_twiddle; + S->pCosFactor = (void *)dct16_cosFactor; break; default: - return ARM_MATH_ARGUMENT_ERROR; + status = ARM_MATH_ARGUMENT_ERROR; + break; } - /* Initialize the RFFT/RIFFT Function */ - arm_rfft_init_q15(S->pRfft, S->N, 0, 1); + if (ARM_MATH_SUCCESS == status) + { + /* Initialize the RFFT/RIFFT Function */ + status = arm_rfft_init_q15(S->pRfft, S->N, 0, 1); + } /* return the status of DCT4 Init function */ - return ARM_MATH_SUCCESS; + return status; } void arm_dct4_q15(const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer) { /* Calculate DCT-II for N-point input */ - uint16_t i; /* Loop counter */ - q15_t *weights; /* Pointer to the Weights table */ - q15_t *pOut; /* Temporary pointers for output buffer */ - q15_t *pS1, *pbuff; /* Temporary pointers for input buffer and pState buffer */ - q15_t in; /* Temporary variable */ - q15_t *cosFact; + uint16_t i; /* Loop counter */ + const q15_t *weights; /* Pointer to the Weights table */ + q15_t *pOut; /* Temporary pointers for output buffer */ + q15_t *pS1, *pbuff; /* Temporary pointers for input buffer and pState buffer */ + q15_t in; /* Temporary variable */ + const q15_t *cosFact; uint32_t length; uint8_t matRow; uint8_t matCol; @@ -606,37 +630,37 @@ void arm_dct4_q15(const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineB * Use matrix production function for preprocessing. Matrix production * supports 16x16 at the most, so the matrix row is set to 16. */ - matRow = 16; - lenPerMatLoop = S->N >= 256 ? 256 : S->N; - matCol = lenPerMatLoop / 16; - matLoop = ((S->N - 1) >> 8) + 1; + matRow = 16U; + lenPerMatLoop = S->N >= 256U ? 256U : S->N; + matCol = (uint8_t)(lenPerMatLoop / 16U); + matLoop = (uint8_t)(((S->N - 1U) >> 8U) + 1U); cosFact = S->pCosFactor; pbuff = pInlineBuffer; length = POWERQUAD_MAKE_MATRIX_LEN(matRow, matCol, 0); - while (matLoop--) + while ((matLoop--) != 0U) { PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; /* cos factor is Q31, convert to float */ - PQ_MatrixScale(POWERQUAD, length, 2.0f / 2147483648.0f, cosFact, (void *)0xE0000000); - cosFact += 2 * lenPerMatLoop; + PQ_MatrixScale(POWERQUAD, length, 2.0f / 2147483648.0f, cosFact, (void *)(uint32_t *)0xE0000000U); + cosFact = &cosFact[2U * lenPerMatLoop]; PQ_WaitDone(POWERQUAD); /* Product. */ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; - POWERQUAD->TMPBASE = 0xE0000000; + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; + POWERQUAD->TMPBASE = 0xE0000000U; - PQ_MatrixProduct(POWERQUAD, length, pbuff, (void *)0xE0000000, pbuff); + PQ_MatrixProduct(POWERQUAD, length, pbuff, (void *)(uint32_t *)0xE0000000U, pbuff); PQ_WaitDone(POWERQUAD); - pbuff += lenPerMatLoop; + pbuff = &pbuff[lenPerMatLoop]; } PQ_SET_FFT_Q15_CONFIG; @@ -648,9 +672,9 @@ void arm_dct4_q15(const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineB * Use matrix production function for twiddle multiplication. * Matrix production supports 16x16 at the most. The total elements are 2*N; */ - lenPerMatLoop = S->N >= 128 ? 128 : S->N; - matCol = lenPerMatLoop / 8; - matLoop = ((S->N - 1) >> 7) + 1; + lenPerMatLoop = S->N >= 128U ? 128U : S->N; + matCol = (uint8_t)(lenPerMatLoop / 8U); + matLoop = (uint8_t)(((S->N - 1U) >> 7U) + 1U); weights = S->pTwiddle; pOut = pState; @@ -658,37 +682,37 @@ void arm_dct4_q15(const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineB PQ_WaitDone(POWERQUAD); - while (matLoop--) + while ((matLoop--) != 0U) { PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; /* Downscale by 1024 * 1024 * 16, because the twiddle are multiplied by 1024 * 1024 * 16. */ - PQ_MatrixScale(POWERQUAD, length, 1.0f / 16777216.0f, weights, (void *)0xE0000000); - weights += lenPerMatLoop * 2; + PQ_MatrixScale(POWERQUAD, length, 1.0f / 16777216.0f, weights, (void *)(uint32_t *)0xE0000000U); + weights = &weights[lenPerMatLoop * 2U]; PQ_WaitDone(POWERQUAD); /* Product. */ - POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; - POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | kPQ_Float; - POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; - POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | kPQ_Float; - POWERQUAD->TMPBASE = 0xE0000000; + POWERQUAD->OUTFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; + POWERQUAD->INAFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_16Bit << 4U) | (uint32_t)kPQ_Float; + POWERQUAD->INBFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; + POWERQUAD->TMPFORMAT = ((uint32_t)(0) << 8U) | ((uint32_t)kPQ_Float << 4U) | (uint32_t)kPQ_Float; + POWERQUAD->TMPBASE = 0xE0000000U; - PQ_MatrixProduct(POWERQUAD, length, pOut, (void *)0xE0000000, pOut); + PQ_MatrixProduct(POWERQUAD, length, pOut, (void *)(uint32_t *)0xE0000000U, pOut); PQ_WaitDone(POWERQUAD); - for (i = 0; i < lenPerMatLoop / 4; i++) + for (i = 0; i < lenPerMatLoop / 4U; i++) { - *pOut -= *(pOut + 1); - pOut += 2; - *pOut -= *(pOut + 1); - pOut += 2; - *pOut -= *(pOut + 1); - pOut += 2; - *pOut -= *(pOut + 1); - pOut += 2; + pOut[0] -= pOut[1]; + pOut = &pOut[2]; + pOut[0] -= pOut[1]; + pOut = &pOut[2]; + pOut[0] -= pOut[1]; + pOut = &pOut[2]; + pOut[0] -= pOut[1]; + pOut = &pOut[2]; } } @@ -705,48 +729,48 @@ void arm_dct4_q15(const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineB pS1 = pState; /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2. Considering the DCT II normalize, here divided by sqrt(2).*/ - in = (q15_t)((float)*pS1 / 1.41421356237f); + in = (q15_t)(float)((float)*pS1 / 1.41421356237f); *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; - i = S->N / 4 - 1; + i = S->N / 4U - 1U; while (i > 0U) { in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; in = *pS1 - in; *pbuff++ = in; - pS1 += 2; + pS1 = &pS1[2]; i--; } } void arm_fir_init_f32( - arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, uint32_t blockSize) + arm_fir_instance_f32 *S, uint16_t numTaps, const float32_t *pCoeffs, float32_t *pState, uint32_t blockSize) { uint32_t i; @@ -758,21 +782,22 @@ void arm_fir_init_f32( * Because the length of pState is (numTaps + blockSize -1), to ensure enough space, * the blockSize should be larger than 1. */ - assert(blockSize > 1); + assert(blockSize > 1U); S->numTaps = numTaps; S->pCoeffs = pCoeffs; S->pState = pState; - for (i = 0; i < numTaps; i++) + for (i = 0U; i < numTaps; i++) { pState[numTaps - i] = pCoeffs[i]; } - *(uint32_t *)pState = 0; + *(uint32_t *)(void *)pState = 0U; } -void arm_fir_init_q31(arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, uint32_t blockSize) +void arm_fir_init_q31( + arm_fir_instance_q31 *S, uint16_t numTaps, const q31_t *pCoeffs, q31_t *pState, uint32_t blockSize) { uint32_t i; @@ -784,13 +809,13 @@ void arm_fir_init_q31(arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, * Because the length of pState is (numTaps + blockSize -1), to ensure enough space, * the blockSize should be larger than 1. */ - assert(blockSize > 1); + assert(blockSize > 1U); S->numTaps = numTaps; S->pCoeffs = pCoeffs; S->pState = pState; - for (i = 0; i < numTaps; i++) + for (i = 0U; i < numTaps; i++) { pState[numTaps - i] = pCoeffs[i]; } @@ -799,9 +824,9 @@ void arm_fir_init_q31(arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, } arm_status arm_fir_init_q15( - arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, uint32_t blockSize) + arm_fir_instance_q15 *S, uint16_t numTaps, const q15_t *pCoeffs, q15_t *pState, uint32_t blockSize) { - uint32_t i; + uint16_t i; /* * CMSIS DSP API filter coefficients stored in time reversed order, but PQ @@ -811,167 +836,178 @@ arm_status arm_fir_init_q15( * Because the length of pState is (numTaps + blockSize -1), to ensure enough space, * the blockSize should be larger than 2. */ - assert(blockSize > 2); + assert(blockSize > 2U); S->numTaps = numTaps; S->pCoeffs = pCoeffs; S->pState = pState; - for (i = 0; i < numTaps; i++) + for (i = 0U; i < numTaps; i++) { - pState[numTaps + 1 - i] = pCoeffs[i]; + pState[numTaps + 1U - i] = pCoeffs[i]; } - *(uint32_t *)pState = 0; + *(uint32_t *)(void *)pState = 0U; return ARM_MATH_SUCCESS; } -void arm_fir_f32(const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, uint32_t blockSize) +/** + * brief Processing function for the floating-point FIR filter. + * param[in] S points to an instance of the floating-point FIR structure. + * param[in] pSrc points to the block of input data. + * param[out] pDst points to the block of output data. + * param[in] blockSize number of samples to process. + * + * Note: Powerquad has a hardware limitation, when using it for FIR increment calculation, the address of pSrc needs to + * be a continuous address. + */ +void arm_fir_f32(const arm_fir_instance_f32 *S, const float32_t *pSrc, float32_t *pDst, uint32_t blockSize) { - assert(S); - assert(pSrc); - assert(pDst); + assert(NULL != S); + assert(NULL != pSrc); + assert(NULL != pDst); uint32_t curOffset; PQ_SET_F32_CONFIG; - curOffset = *(uint32_t *)(S->pState); + curOffset = *(uint32_t *)(void *)(S->pState); - if (curOffset == 0) + if (curOffset == 0U) { - PQ_FIR(POWERQUAD, pSrc, blockSize, &(S->pState[1]), S->numTaps, pDst, PQ_FIR_FIR); + PQ_FIR(POWERQUAD, pSrc, (int32_t)blockSize, &(S->pState[1]), (int32_t)S->numTaps, pDst, PQ_FIR_FIR); } else { - _arm_fir_increment(pSrc - curOffset, blockSize, &S->pState[1], S->numTaps, pDst - curOffset, curOffset); + _arm_fir_increment(pSrc, blockSize, &S->pState[1], S->numTaps, pDst, curOffset, sizeof(*pSrc)); } - *(uint32_t *)(S->pState) = curOffset + blockSize; + *(uint32_t *)(void *)(S->pState) = curOffset + blockSize; PQ_WaitDone(POWERQUAD); } -void arm_fir_q31(const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize) +void arm_fir_q31(const arm_fir_instance_q31 *S, const q31_t *pSrc, q31_t *pDst, uint32_t blockSize) { - assert(S); - assert(pSrc); - assert(pDst); + assert(NULL != S); + assert(NULL != pSrc); + assert(NULL != pDst); uint32_t curOffset; PQ_SET_Q31_CONFIG; - curOffset = *(uint32_t *)(S->pState); + curOffset = *(uint32_t *)(void *)(S->pState); - if (curOffset == 0) + if (curOffset == 0U) { - PQ_FIR(POWERQUAD, pSrc, blockSize, &(S->pState[1]), S->numTaps, pDst, PQ_FIR_FIR); + PQ_FIR(POWERQUAD, pSrc, (int32_t)blockSize, &(S->pState[1]), (int32_t)S->numTaps, pDst, PQ_FIR_FIR); } else { - _arm_fir_increment(pSrc - curOffset, blockSize, &S->pState[1], S->numTaps, pDst - curOffset, curOffset); + _arm_fir_increment(pSrc, blockSize, &S->pState[1], S->numTaps, pDst, curOffset, sizeof(*pSrc)); } - *(uint32_t *)(S->pState) = curOffset + blockSize; + *(uint32_t *)(void *)(S->pState) = curOffset + blockSize; PQ_WaitDone(POWERQUAD); } -void arm_fir_q15(const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize) +void arm_fir_q15(const arm_fir_instance_q15 *S, const q15_t *pSrc, q15_t *pDst, uint32_t blockSize) { - assert(S); - assert(pSrc); - assert(pDst); + assert(NULL != S); + assert(NULL != pSrc); + assert(NULL != pDst); uint32_t curOffset; PQ_SET_Q15_CONFIG; - curOffset = *(uint32_t *)(S->pState); + curOffset = *(uint32_t *)(void *)(S->pState); - if (curOffset == 0) + if (curOffset == 0U) { - PQ_FIR(POWERQUAD, pSrc, blockSize, &(S->pState[2]), S->numTaps, pDst, PQ_FIR_FIR); + PQ_FIR(POWERQUAD, pSrc, (int32_t)blockSize, &(S->pState[2]), (int32_t)S->numTaps, pDst, PQ_FIR_FIR); } else { - _arm_fir_increment(pSrc - curOffset, blockSize, &S->pState[2], S->numTaps, pDst - curOffset, curOffset); + _arm_fir_increment(pSrc, blockSize, &S->pState[2], S->numTaps, pDst, curOffset, sizeof(*pSrc)); } - *(uint32_t *)(S->pState) = curOffset + blockSize; + *(uint32_t *)(void *)(S->pState) = curOffset + blockSize; PQ_WaitDone(POWERQUAD); } -void arm_conv_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst) +void arm_conv_f32(const float32_t *pSrcA, uint32_t srcALen, const float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); PQ_SET_F32_CONFIG; - PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CONVOLUTION); + PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CONVOLUTION); PQ_WaitDone(POWERQUAD); } -void arm_conv_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst) +void arm_conv_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); PQ_SET_Q31_CONFIG; - PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CONVOLUTION); + PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CONVOLUTION); PQ_WaitDone(POWERQUAD); } -void arm_conv_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst) +void arm_conv_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); PQ_SET_Q15_CONFIG; - PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CONVOLUTION); + PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CONVOLUTION); PQ_WaitDone(POWERQUAD); } -void arm_correlate_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst) +void arm_correlate_f32( + const float32_t *pSrcA, uint32_t srcALen, const float32_t *pSrcB, uint32_t srcBLen, float32_t *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); PQ_SET_F32_CONFIG; - PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CORRELATION); + PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CORRELATION); PQ_WaitDone(POWERQUAD); } -void arm_correlate_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst) +void arm_correlate_q31(const q31_t *pSrcA, uint32_t srcALen, const q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); PQ_SET_Q31_CONFIG; - PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CORRELATION); + PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CORRELATION); PQ_WaitDone(POWERQUAD); } -void arm_correlate_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst) +void arm_correlate_q15(const q15_t *pSrcA, uint32_t srcALen, const q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); PQ_SET_Q15_CONFIG; - PQ_FIR(POWERQUAD, pSrcA, srcALen, pSrcB, srcBLen, pDst, PQ_FIR_CORRELATION); + PQ_FIR(POWERQUAD, pSrcA, (int32_t)srcALen, pSrcB, (int32_t)srcBLen, pDst, PQ_FIR_CORRELATION); PQ_WaitDone(POWERQUAD); } @@ -1015,12 +1051,12 @@ arm_status arm_mat_add_f32(const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1035,7 +1071,7 @@ arm_status arm_mat_add_f32(const arm_matrix_instance_f32 *pSrcA, { PQ_SET_F32_CONFIG; - length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); PQ_MatrixAddition(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); @@ -1053,12 +1089,12 @@ arm_status arm_mat_add_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1073,7 +1109,7 @@ arm_status arm_mat_add_q31(const arm_matrix_instance_q31 *pSrcA, { PQ_SET_FIX32_CONFIG; - length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); PQ_MatrixAddition(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); @@ -1091,12 +1127,12 @@ arm_status arm_mat_add_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1111,7 +1147,7 @@ arm_status arm_mat_add_q15(const arm_matrix_instance_q15 *pSrcA, { PQ_SET_FIX16_CONFIG; - length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); PQ_MatrixAddition(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); @@ -1129,12 +1165,12 @@ arm_status arm_mat_sub_f32(const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1149,7 +1185,7 @@ arm_status arm_mat_sub_f32(const arm_matrix_instance_f32 *pSrcA, { PQ_SET_F32_CONFIG; - length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); PQ_MatrixSubtraction(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); @@ -1167,12 +1203,12 @@ arm_status arm_mat_sub_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1187,7 +1223,7 @@ arm_status arm_mat_sub_q31(const arm_matrix_instance_q31 *pSrcA, { PQ_SET_FIX32_CONFIG; - length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); PQ_MatrixSubtraction(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); @@ -1205,12 +1241,12 @@ arm_status arm_mat_sub_q15(const arm_matrix_instance_q15 *pSrcA, const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1225,7 +1261,7 @@ arm_status arm_mat_sub_q15(const arm_matrix_instance_q15 *pSrcA, { PQ_SET_FIX16_CONFIG; - length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); PQ_MatrixSubtraction(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); @@ -1243,12 +1279,12 @@ arm_status arm_mat_mult_f32(const arm_matrix_instance_f32 *pSrcA, const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1263,7 +1299,7 @@ arm_status arm_mat_mult_f32(const arm_matrix_instance_f32 *pSrcA, { PQ_SET_F32_CONFIG; - length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); PQ_MatrixMultiplication(POWERQUAD, length, pSrcA->pData, pSrcB->pData, pDst->pData); @@ -1281,12 +1317,12 @@ arm_status arm_mat_mult_q31(const arm_matrix_instance_q31 *pSrcA, const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; /* * The output prescale does not supprt negative value due to hardware issue, @@ -1307,20 +1343,20 @@ arm_status arm_mat_mult_q31(const arm_matrix_instance_q31 *pSrcA, else #endif { - length = (pSrcB->numCols << 8) | (pSrcB->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrcB->numRows, pSrcB->numCols, 0U); PQ_SET_MAT_FIX32_WORKAROUND_SCALE_CONFIG; /* Downscale. */ - PQ_MatrixScale(POWERQUAD, length, 1.0f / 2147483648.0f, pSrcB->pData, (void *)0xE0000000); + PQ_MatrixScale(POWERQUAD, length, 1.0f / 2147483648.0f, pSrcB->pData, (void *)(uint32_t *)0xE0000000U); - length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); PQ_WaitDone(POWERQUAD); PQ_SET_MAT_FIX32_WORKAROUND_MULT_CONFIG; - PQ_MatrixMultiplication(POWERQUAD, length, pSrcA->pData, (void *)0xE0000000, pDst->pData); + PQ_MatrixMultiplication(POWERQUAD, length, pSrcA->pData, (void *)(uint32_t *)0xE0000000U, pDst->pData); /* Wait for the completion */ PQ_WaitDone(POWERQUAD); @@ -1337,12 +1373,12 @@ arm_status arm_mat_mult_q15(const arm_matrix_instance_q15 *pSrcA, arm_matrix_instance_q15 *pDst, q15_t *pState) { - assert(pSrcA); - assert(pSrcB); - assert(pDst); + assert(NULL != pSrcA); + assert(NULL != pSrcB); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1355,20 +1391,20 @@ arm_status arm_mat_mult_q15(const arm_matrix_instance_q15 *pSrcA, else #endif { - length = (pSrcB->numCols << 8) | (pSrcB->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrcB->numRows, pSrcB->numCols, 0U); PQ_SET_MAT_FIX16_WORKAROUND_SCALE_CONFIG; /* Downscale. */ - PQ_MatrixScale(POWERQUAD, length, 1.0f / 32768.0f, pSrcB->pData, (void *)0xE0000000); + PQ_MatrixScale(POWERQUAD, length, 1.0f / 32768.0f, pSrcB->pData, (void *)(uint32_t *)0xE0000000U); - length = (pSrcB->numCols << 16) | (pSrcA->numCols << 8) | (pSrcA->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrcA->numRows, pSrcA->numCols, pSrcB->numCols); PQ_WaitDone(POWERQUAD); PQ_SET_MAT_FIX16_WORKAROUND_MULT_CONFIG; - PQ_MatrixMultiplication(POWERQUAD, length, pSrcA->pData, (void *)0xE0000000, pDst->pData); + PQ_MatrixMultiplication(POWERQUAD, length, pSrcA->pData, (void *)(uint32_t *)0xE0000000U, pDst->pData); /* Wait for the completion */ PQ_WaitDone(POWERQUAD); @@ -1380,18 +1416,18 @@ arm_status arm_mat_mult_q15(const arm_matrix_instance_q15 *pSrcA, return status; } -arm_status arm_mat_inverse_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst) +arm_status arm_mat_inverse_f32(const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *dst) { - assert(pSrc); - assert(pDst); + assert(NULL != src); + assert(NULL != dst); arm_status status; - q31_t length; + uint32_t length; float tmp[1024]; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ - if ((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols) || (pSrc->numRows != pDst->numRows)) + if ((src->numRows != src->numCols) || (dst->numRows != dst->numCols) || (src->numRows != dst->numRows)) { /* Set status as ARM_MATH_SIZE_MISMATCH */ status = ARM_MATH_SIZE_MISMATCH; @@ -1401,9 +1437,9 @@ arm_status arm_mat_inverse_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_i { PQ_SET_F32_CONFIG; - length = (pSrc->numRows << 16) | (pSrc->numRows << 8) | (pSrc->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(src->numRows, src->numCols, src->numRows); - PQ_MatrixInversion(POWERQUAD, length, pSrc->pData, tmp, pDst->pData); + PQ_MatrixInversion(POWERQUAD, length, src->pData, tmp, dst->pData); /* Wait for the completion */ PQ_WaitDone(POWERQUAD); @@ -1417,11 +1453,11 @@ arm_status arm_mat_inverse_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_i arm_status arm_mat_trans_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst) { - assert(pSrc); - assert(pDst); + assert(NULL != pSrc); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1433,7 +1469,7 @@ arm_status arm_mat_trans_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_ins else #endif { - length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); PQ_SetFormat(POWERQUAD, kPQ_CP_MTX, kPQ_Float); @@ -1450,11 +1486,11 @@ arm_status arm_mat_trans_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_ins arm_status arm_mat_trans_q31(const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst) { - assert(pSrc); - assert(pDst); + assert(NULL != pSrc); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1468,7 +1504,7 @@ arm_status arm_mat_trans_q31(const arm_matrix_instance_q31 *pSrc, arm_matrix_ins { PQ_SET_FIX32_CONFIG; - length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); PQ_MatrixTranspose(POWERQUAD, length, pSrc->pData, pDst->pData); @@ -1484,11 +1520,11 @@ arm_status arm_mat_trans_q31(const arm_matrix_instance_q31 *pSrc, arm_matrix_ins arm_status arm_mat_trans_q15(const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst) { - assert(pSrc); - assert(pDst); + assert(NULL != pSrc); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1502,7 +1538,7 @@ arm_status arm_mat_trans_q15(const arm_matrix_instance_q15 *pSrc, arm_matrix_ins { PQ_SET_FIX16_CONFIG; - length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); PQ_MatrixTranspose(POWERQUAD, length, pSrc->pData, pDst->pData); @@ -1518,11 +1554,11 @@ arm_status arm_mat_trans_q15(const arm_matrix_instance_q15 *pSrc, arm_matrix_ins arm_status arm_mat_scale_f32(const arm_matrix_instance_f32 *pSrc, float32_t scale, arm_matrix_instance_f32 *pDst) { - assert(pSrc); - assert(pDst); + assert(NULL != pSrc); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; #ifdef ARM_MATH_MATRIX_CHECK /* Check for matrix mismatch condition */ @@ -1536,7 +1572,7 @@ arm_status arm_mat_scale_f32(const arm_matrix_instance_f32 *pSrc, float32_t scal { PQ_SET_F32_CONFIG; - length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); PQ_MatrixScale(POWERQUAD, length, scale, pSrc->pData, pDst->pData); @@ -1551,28 +1587,28 @@ arm_status arm_mat_scale_f32(const arm_matrix_instance_f32 *pSrc, float32_t scal } arm_status arm_mat_scale_q31(const arm_matrix_instance_q31 *pSrc, - q31_t scale, + q31_t scaleFract, int32_t shift, arm_matrix_instance_q31 *pDst) { - assert(pSrc); - assert(pDst); + assert(NULL != pSrc); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; float scaleFloat; pq_config_t config = { - kPQ_32Bit, /* inputAFormat */ - 0, /* inputAPrescale */ - kPQ_32Bit, /* inputBFormat */ - 0, /* inputBPrescale */ - kPQ_32Bit, /* outputFormat */ - (int8_t)shift, /* outputPrescale */ - kPQ_Float, /* tmpFormat */ - 0, /* tmpPrescale */ - kPQ_Float, /* machineFormat */ - (uint32_t *)0xe0000000, /* tmpBase */ + kPQ_32Bit, /* inputAFormat */ + 0, /* inputAPrescale */ + kPQ_32Bit, /* inputBFormat */ + 0, /* inputBPrescale */ + kPQ_32Bit, /* outputFormat */ + (int8_t)shift, /* outputPrescale */ + kPQ_Float, /* tmpFormat */ + 0, /* tmpPrescale */ + kPQ_Float, /* machineFormat */ + (uint32_t *)0xe0000000U, /* tmpBase */ }; #ifdef ARM_MATH_MATRIX_CHECK @@ -1585,9 +1621,9 @@ arm_status arm_mat_scale_q31(const arm_matrix_instance_q31 *pSrc, else #endif { - length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); - scaleFloat = PQ_Q31_2_FLOAT(scale); + scaleFloat = PQ_Q31_2_FLOAT(scaleFract); PQ_SetConfig(POWERQUAD, &config); @@ -1604,28 +1640,28 @@ arm_status arm_mat_scale_q31(const arm_matrix_instance_q31 *pSrc, } arm_status arm_mat_scale_q15(const arm_matrix_instance_q15 *pSrc, - q15_t scale, + q15_t scaleFract, int32_t shift, arm_matrix_instance_q15 *pDst) { - assert(pSrc); - assert(pDst); + assert(NULL != pSrc); + assert(NULL != pDst); arm_status status; - q31_t length; + uint32_t length; float scaleFloat; pq_config_t config = { - kPQ_16Bit, /* inputAFormat */ - 0, /* inputAPrescale */ - kPQ_16Bit, /* inputBFormat */ - 0, /* inputBPrescale */ - kPQ_16Bit, /* outputFormat */ - (int8_t)shift, /* outputPrescale */ - kPQ_Float, /* tmpFormat */ - 0, /* tmpPrescale */ - kPQ_Float, /* machineFormat */ - (uint32_t *)0xe0000000, /* tmpBase */ + kPQ_16Bit, /* inputAFormat */ + 0, /* inputAPrescale */ + kPQ_16Bit, /* inputBFormat */ + 0, /* inputBPrescale */ + kPQ_16Bit, /* outputFormat */ + (int8_t)shift, /* outputPrescale */ + kPQ_Float, /* tmpFormat */ + 0, /* tmpPrescale */ + kPQ_Float, /* machineFormat */ + (uint32_t *)0xe0000000U, /* tmpBase */ }; #ifdef ARM_MATH_MATRIX_CHECK @@ -1638,9 +1674,9 @@ arm_status arm_mat_scale_q15(const arm_matrix_instance_q15 *pSrc, else #endif { - length = (pSrc->numCols << 8) | (pSrc->numRows << 0); + length = POWERQUAD_MAKE_MATRIX_LEN(pSrc->numRows, pSrc->numCols, 0U); - scaleFloat = PQ_Q15_2_FLOAT(scale); + scaleFloat = PQ_Q15_2_FLOAT(scaleFract); PQ_SetConfig(POWERQUAD, &config); diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.c index 9cee85b24e..a0b613263e 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.c @@ -1,11 +1,12 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include +#include "fsl_powerquad_data.h" /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.h index 3c43bf138a..e0bbb5b675 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_data.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -26,12 +26,12 @@ extern int32_t idct64_twiddle[128]; extern int32_t idct128_twiddle[256]; extern int32_t idct256_twiddle[512]; extern int32_t idct512_twiddle[1024]; -extern int32_t dct16_cosFactor[32]; -extern int32_t dct32_cosFactor[64]; -extern int32_t dct64_cosFactor[128]; -extern int32_t dct128_cosFactor[256]; -extern int32_t dct256_cosFactor[512]; -extern int32_t dct512_cosFactor[1024]; +extern int32_t dct16_cosFactor[16]; +extern int32_t dct32_cosFactor[32]; +extern int32_t dct64_cosFactor[64]; +extern int32_t dct128_cosFactor[128]; +extern int32_t dct256_cosFactor[256]; +extern int32_t dct512_cosFactor[512]; /******************************************************************************* * API diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_filter.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_filter.c index fe5688d0f4..e783fb33be 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_filter.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_filter.c @@ -1,5 +1,5 @@ /* - * Copyright 2018-2019 NXP + * Copyright 2018-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,18 +22,21 @@ void PQ_VectorBiqaudDf2F32(float *pSrc, float *pDst, int32_t length) { int32_t remainderBy8 = length % 8; + pq_float_t val; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - _pq_biquad0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readAdd0(); + val.floatX = *pSrc++; + _pq_biquad0(val.integerX); + val.integerX = _pq_readAdd0(); + *pDst++ = val.floatX; } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8BiquadDf2F32(); @@ -45,17 +48,17 @@ void PQ_VectorBiqaudDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_biquad0_fx(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8BiquadDf2Fixed32(); @@ -67,17 +70,17 @@ void PQ_VectorBiqaudDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_biquad0_fx(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); + *pDst++ = (int16_t)_pq_readAdd0_fx(); } } - if (length) + if (length > 0) { PQ_StartVectorFixed16(pSrc, pDst, length); PQ_Vector8BiquadDf2Fixed16(); @@ -88,8 +91,9 @@ void PQ_VectorBiqaudDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length) void PQ_VectorBiqaudCascadeDf2F32(float *pSrc, float *pDst, int32_t length) { int32_t remainderBy8 = length % 8; + pq_float_t val; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; @@ -97,16 +101,23 @@ void PQ_VectorBiqaudCascadeDf2F32(float *pSrc, float *pDst, int32_t length) for (int i = 1; i < remainderBy8; i++) { - _pq_biquad0(*(int32_t *)&pSrc[i - 1]); - _pq_biquad1(*(int32_t *)&pSrc[i]); - *(int32_t *)&pDst[i - 1] = _pq_readAdd0(); - *(int32_t *)&pDst[i] = _pq_readAdd1(); + val.floatX = pSrc[i - 1]; + _pq_biquad0(val.integerX); + + val.floatX = pSrc[i]; + _pq_biquad1(val.integerX); + + val.integerX = _pq_readAdd0(); + pDst[i - 1] = val.floatX; + + val.integerX = _pq_readAdd1(); + pDst[i] = val.floatX; } PQ_BiquadF32(&pSrc[remainderBy8 - 1], &pDst[remainderBy8 - 1]); } - if (length) + if (length > 0) { PQ_StartVector(&pSrc[remainderBy8], &pDst[remainderBy8], length); PQ_Vector8BiqaudDf2CascadeF32(); @@ -118,26 +129,26 @@ void PQ_VectorBiqaudCascadeDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t leng { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; _pq_biquad1_fx(pSrc[0]); - pDst[0] = _pq_readAdd1_fx(); + pDst[0] = (int32_t)_pq_readAdd1_fx(); for (int i = 1; i < remainderBy8; i++) { _pq_biquad0_fx(pSrc[i - 1]); _pq_biquad1_fx(pSrc[i]); - pDst[i - 1] = _pq_readAdd0_fx(); - pDst[i] = _pq_readAdd1_fx(); + pDst[i - 1] = (int32_t)_pq_readAdd0_fx(); + pDst[i] = (int32_t)_pq_readAdd1_fx(); } _pq_biquad0_fx(pSrc[remainderBy8 - 1]); - pDst[remainderBy8 - 1] = _pq_readAdd0_fx(); + pDst[remainderBy8 - 1] = (int32_t)_pq_readAdd0_fx(); } - if (length) + if (length > 0) { PQ_StartVector(&pSrc[remainderBy8], &pDst[remainderBy8], length); PQ_Vector8BiqaudDf2CascadeFixed32(); @@ -149,26 +160,26 @@ void PQ_VectorBiqaudCascadeDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t leng { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; _pq_biquad1_fx(pSrc[0]); - pDst[0] = _pq_readAdd1_fx(); + pDst[0] = (int16_t)_pq_readAdd1_fx(); for (int i = 1; i < remainderBy8; i++) { _pq_biquad0_fx(pSrc[i - 1]); _pq_biquad1_fx(pSrc[i]); - pDst[i - 1] = _pq_readAdd0_fx(); - pDst[i] = _pq_readAdd1_fx(); + pDst[i - 1] = (int16_t)_pq_readAdd0_fx(); + pDst[i] = (int16_t)_pq_readAdd1_fx(); } _pq_biquad0_fx(pSrc[remainderBy8 - 1]); - pDst[remainderBy8 - 1] = _pq_readAdd0_fx(); + pDst[remainderBy8 - 1] = (int16_t)_pq_readAdd0_fx(); } - if (length) + if (length > 0) { PQ_StartVectorFixed16(&pSrc[remainderBy8], &pDst[remainderBy8], length); PQ_Vector8BiqaudDf2CascadeFixed16(); @@ -258,25 +269,30 @@ void PQ_BiquadRestoreInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_ } } -void PQ_FIR( - POWERQUAD_Type *base, void *pAData, int32_t ALength, void *pBData, int32_t BLength, void *pResult, uint32_t opType) +void PQ_FIR(POWERQUAD_Type *base, + const void *pAData, + int32_t ALength, + const void *pBData, + int32_t BLength, + void *pResult, + uint32_t opType) { - assert(pAData); - assert(pBData); - assert(pResult); + assert(NULL != pAData); + assert(NULL != pBData); + assert(NULL != pResult); - base->INABASE = (uint32_t)pAData; - base->INBBASE = (uint32_t)pBData; + base->INABASE = (uint32_t)(const uint32_t *)pAData; + base->INBBASE = (uint32_t)(const uint32_t *)pBData; base->LENGTH = ((uint32_t)BLength << 16U) + (uint32_t)ALength; - base->OUTBASE = (uint32_t)pResult; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; base->CONTROL = (CP_FIR << 4U) | opType; } void PQ_FIRIncrement(POWERQUAD_Type *base, int32_t ALength, int32_t BLength, int32_t xOffset) { - base->MISC = xOffset; - base->LENGTH = ((uint32_t)BLength << 16) + (uint32_t)ALength; - base->CONTROL = (CP_FIR << 4) | PQ_FIR_INCREMENTAL; + base->MISC = (uint32_t)xOffset; + base->LENGTH = ((uint32_t)BLength << 16U) + (uint32_t)ALength; + base->CONTROL = (CP_FIR << 4U) | PQ_FIR_INCREMENTAL; } void PQ_BiquadCascadeDf2Init(pq_biquad_cascade_df2_instance *S, uint8_t numStages, pq_biquad_state_t *pState) @@ -292,14 +308,14 @@ void PQ_BiquadCascadeDf2F32(const pq_biquad_cascade_df2_instance *S, float *pSrc if (pDst != pSrc) { - memcpy(pDst, pSrc, 4 * blockSize); + (void)memcpy(pDst, pSrc, 4U * blockSize); } - if (stage % 2 != 0) + if (stage % 2U != 0U) { PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - PQ_VectorBiqaudDf2F32(pSrc, pDst, blockSize); + PQ_VectorBiqaudDf2F32(pSrc, pDst, (int32_t)blockSize); PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); @@ -313,7 +329,7 @@ void PQ_BiquadCascadeDf2F32(const pq_biquad_cascade_df2_instance *S, float *pSrc states++; PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - PQ_VectorBiqaudCascadeDf2F32(pDst, pDst, blockSize); + PQ_VectorBiqaudCascadeDf2F32(pDst, pDst, (int32_t)blockSize); states--; PQ_BiquadBackUpInternalState(POWERQUAD, 1, states); @@ -336,14 +352,14 @@ void PQ_BiquadCascadeDf2Fixed32(const pq_biquad_cascade_df2_instance *S, if (pDst != pSrc) { - memcpy(pDst, pSrc, 4 * blockSize); + (void)memcpy(pDst, pSrc, 4U * blockSize); } - if (stage % 2 != 0) + if (stage % 2U != 0U) { PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - PQ_VectorBiqaudDf2Fixed32(pSrc, pDst, blockSize); + PQ_VectorBiqaudDf2Fixed32(pSrc, pDst, (int32_t)blockSize); PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); @@ -357,7 +373,7 @@ void PQ_BiquadCascadeDf2Fixed32(const pq_biquad_cascade_df2_instance *S, states++; PQ_BiquadRestoreInternalState(POWERQUAD, 1, states); - PQ_VectorBiqaudCascadeDf2Fixed32(pDst, pDst, blockSize); + PQ_VectorBiqaudCascadeDf2Fixed32(pDst, pDst, (int32_t)blockSize); states--; PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); @@ -379,14 +395,14 @@ void PQ_BiquadCascadeDf2Fixed16(const pq_biquad_cascade_df2_instance *S, if (pDst != pSrc) { - memcpy(pDst, pSrc, 2 * blockSize); + (void)memcpy(pDst, pSrc, 2U * blockSize); } - if (stage % 2 != 0) + if (stage % 2U != 0U) { PQ_BiquadRestoreInternalState(POWERQUAD, 0, states); - PQ_VectorBiqaudDf2Fixed16(pSrc, pDst, blockSize); + PQ_VectorBiqaudDf2Fixed16(pSrc, pDst, (int32_t)blockSize); PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); @@ -400,7 +416,7 @@ void PQ_BiquadCascadeDf2Fixed16(const pq_biquad_cascade_df2_instance *S, states++; PQ_BiquadRestoreInternalState(POWERQUAD, 1, states); - PQ_VectorBiqaudCascadeDf2Fixed16(pDst, pDst, blockSize); + PQ_VectorBiqaudCascadeDf2Fixed16(pDst, pDst, (int32_t)blockSize); states--; PQ_BiquadBackUpInternalState(POWERQUAD, 0, states); diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_math.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_math.c index 78c4a836a3..19d39f2e63 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_math.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_math.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,18 +22,21 @@ void PQ_VectorLnF32(float *pSrc, float *pDst, int32_t length) { int32_t remainderBy8 = length % 8; + pq_float_t val; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - _pq_ln0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readAdd0(); + val.floatX = *pSrc++; + _pq_ln0(val.integerX); + val.integerX = _pq_readAdd0(); + *pDst++ = val.floatX; } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8F32(PQ_LN, 1, PQ_TRANS); @@ -44,18 +47,21 @@ void PQ_VectorLnF32(float *pSrc, float *pDst, int32_t length) void PQ_VectorInvF32(float *pSrc, float *pDst, int32_t length) { int32_t remainderBy8 = length % 8; + pq_float_t val; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - _pq_inv0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readMult0(); + val.floatX = *pSrc++; + _pq_inv0(val.integerX); + val.integerX = _pq_readMult0(); + *pDst++ = val.floatX; } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8F32(PQ_INV, 0, PQ_TRANS); @@ -66,18 +72,21 @@ void PQ_VectorInvF32(float *pSrc, float *pDst, int32_t length) void PQ_VectorSqrtF32(float *pSrc, float *pDst, int32_t length) { int32_t remainderBy8 = length % 8; + pq_float_t val; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - _pq_sqrt0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readMult0(); + val.floatX = *pSrc++; + _pq_sqrt0(val.integerX); + val.integerX = _pq_readMult0(); + *pDst++ = val.floatX; } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8F32(PQ_SQRT, 0, PQ_TRANS); @@ -88,18 +97,21 @@ void PQ_VectorSqrtF32(float *pSrc, float *pDst, int32_t length) void PQ_VectorInvSqrtF32(float *pSrc, float *pDst, int32_t length) { int32_t remainderBy8 = length % 8; + pq_float_t val; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - _pq_invsqrt0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readMult0(); + val.floatX = *pSrc++; + _pq_invsqrt0(val.integerX); + val.integerX = _pq_readMult0(); + *pDst++ = val.floatX; } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8F32(PQ_INVSQRT, 0, PQ_TRANS); @@ -110,18 +122,21 @@ void PQ_VectorInvSqrtF32(float *pSrc, float *pDst, int32_t length) void PQ_VectorEtoxF32(float *pSrc, float *pDst, int32_t length) { int32_t remainderBy8 = length % 8; + pq_float_t val; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - _pq_etox0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readMult0(); + val.floatX = *pSrc++; + _pq_etox0(val.integerX); + val.integerX = _pq_readMult0(); + *pDst++ = val.floatX; } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8F32(PQ_ETOX, 0, PQ_TRANS); @@ -132,18 +147,21 @@ void PQ_VectorEtoxF32(float *pSrc, float *pDst, int32_t length) void PQ_VectorEtonxF32(float *pSrc, float *pDst, int32_t length) { int32_t remainderBy8 = length % 8; + pq_float_t val; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - _pq_etonx0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readMult0(); + val.floatX = *pSrc++; + _pq_etonx0(val.integerX); + val.integerX = _pq_readMult0(); + *pDst++ = val.floatX; } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8F32(PQ_ETONX, 0, PQ_TRANS); @@ -154,18 +172,21 @@ void PQ_VectorEtonxF32(float *pSrc, float *pDst, int32_t length) void PQ_VectorSinF32(float *pSrc, float *pDst, int32_t length) { int32_t remainderBy8 = length % 8; + pq_float_t val; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - _pq_sin0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readAdd0(); + val.floatX = *pSrc++; + _pq_sin0(val.integerX); + val.integerX = _pq_readAdd0(); + *pDst++ = val.floatX; } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8F32(PQ_SIN, 1, PQ_TRIG); @@ -176,18 +197,21 @@ void PQ_VectorSinF32(float *pSrc, float *pDst, int32_t length) void PQ_VectorCosF32(float *pSrc, float *pDst, int32_t length) { int32_t remainderBy8 = length % 8; + pq_float_t val; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - _pq_cos0(*(int32_t *)pSrc++); - *(int32_t *)pDst++ = _pq_readAdd0(); + val.floatX = *pSrc++; + _pq_cos0(val.integerX); + val.integerX = _pq_readAdd0(); + *pDst++ = val.floatX; } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8F32(PQ_COS, 1, PQ_TRIG); @@ -199,17 +223,17 @@ void PQ_VectorLnFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_ln_fx0(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8Fixed32(PQ_LN, 1, PQ_TRANS_FIXED); @@ -221,17 +245,17 @@ void PQ_VectorInvFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_inv_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); + *pDst++ = (int32_t)_pq_readMult0_fx(); } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8Fixed32(PQ_INV, 0, PQ_TRANS_FIXED); @@ -243,17 +267,17 @@ void PQ_VectorSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_sqrt_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); + *pDst++ = (int32_t)_pq_readMult0_fx(); } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8Fixed32(PQ_SQRT, 0, PQ_TRANS_FIXED); @@ -265,17 +289,17 @@ void PQ_VectorInvSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_invsqrt_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); + *pDst++ = (int32_t)_pq_readMult0_fx(); } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8Fixed32(PQ_INVSQRT, 0, PQ_TRANS_FIXED); @@ -287,17 +311,17 @@ void PQ_VectorEtoxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_etox_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); + *pDst++ = (int32_t)_pq_readMult0_fx(); } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8Fixed32(PQ_ETOX, 0, PQ_TRANS_FIXED); @@ -309,17 +333,17 @@ void PQ_VectorEtonxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_etonx_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); + *pDst++ = (int32_t)_pq_readMult0_fx(); } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8Fixed32(PQ_ETONX, 0, PQ_TRANS_FIXED); @@ -336,22 +360,22 @@ void PQ_VectorSinQ31(int32_t *pSrc, int32_t *pDst, int32_t length) pq_float_t magic; pq_float_t valFloat; - magic.integerX = 0x30c90fdb; + magic.integerX = 0x30c90fdbU; #endif cppre = POWERQUAD->CPPRE; POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); #if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); } } @@ -359,59 +383,59 @@ void PQ_VectorSinQ31(int32_t *pSrc, int32_t *pDst, int32_t length) { valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); length -= 8; } #else - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_sin_fx0(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8Fixed32(PQ_SIN, 1, PQ_TRIG_FIXED); @@ -438,15 +462,15 @@ void PQ_VectorCosQ31(int32_t *pSrc, int32_t *pDst, int32_t length) POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31); #if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); } } @@ -454,59 +478,59 @@ void PQ_VectorCosQ31(int32_t *pSrc, int32_t *pDst, int32_t length) { valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); valFloat.floatX = magic.floatX * (float)(*pSrc++); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()); + (void)_pq_readAdd0(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); length -= 8; } #else - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_cos_fx0(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); + *pDst++ = (int32_t)_pq_readAdd0_fx(); } } - if (length) + if (length > 0) { PQ_StartVector(pSrc, pDst, length); PQ_Vector8Fixed32(PQ_COS, 1, PQ_TRIG_FIXED); @@ -521,17 +545,17 @@ void PQ_VectorLnFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_ln_fx0(*pSrc++); - *pDst++ = _pq_readAdd0_fx(); + *pDst++ = (int16_t)_pq_readAdd0_fx(); } } - if (length) + if (length > 0) { PQ_StartVectorFixed16(pSrc, pDst, length); PQ_Vector8Fixed16(PQ_LN, 1, PQ_TRANS_FIXED); @@ -543,17 +567,17 @@ void PQ_VectorInvFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_inv_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); + *pDst++ = (int16_t)_pq_readMult0_fx(); } } - if (length) + if (length > 0) { PQ_StartVectorFixed16(pSrc, pDst, length); PQ_Vector8Fixed16(PQ_INV, 0, PQ_TRANS_FIXED); @@ -565,17 +589,17 @@ void PQ_VectorSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_sqrt_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); + *pDst++ = (int16_t)_pq_readMult0_fx(); } } - if (length) + if (length > 0) { PQ_StartVectorFixed16(pSrc, pDst, length); PQ_Vector8Fixed16(PQ_SQRT, 0, PQ_TRANS_FIXED); @@ -587,17 +611,17 @@ void PQ_VectorInvSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_invsqrt_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); + *pDst++ = (int16_t)_pq_readMult0_fx(); } } - if (length) + if (length > 0) { PQ_StartVectorFixed16(pSrc, pDst, length); PQ_Vector8Fixed16(PQ_INVSQRT, 0, PQ_TRANS_FIXED); @@ -609,17 +633,17 @@ void PQ_VectorEtoxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_etox_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); + *pDst++ = (int16_t)_pq_readMult0_fx(); } } - if (length) + if (length > 0) { PQ_StartVectorFixed16(pSrc, pDst, length); PQ_Vector8Fixed16(PQ_ETOX, 0, PQ_TRANS_FIXED); @@ -631,17 +655,17 @@ void PQ_VectorEtonxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length) { int32_t remainderBy8 = length % 8; - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { _pq_etonx_fx0(*pSrc++); - *pDst++ = _pq_readMult0_fx(); + *pDst++ = (int16_t)_pq_readMult0_fx(); } } - if (length) + if (length > 0) { PQ_StartVectorFixed16(pSrc, pDst, length); PQ_Vector8Fixed16(PQ_ETONX, 0, PQ_TRANS_FIXED); @@ -665,76 +689,76 @@ void PQ_VectorSinQ15(int16_t *pSrc, int16_t *pDst, int32_t length) int32_t remainderBy8 = length % 8; #if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); - _pq_sin0(*(int32_t *)(&valFloat)); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); + _pq_sin0(valFloat.integerX); + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); } } while (length > 0) { - valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((uint32_t)(*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_sin0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); length -= 8; } #else - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - _pq_sin_fx0((uint32_t)(*pSrc++) << 16); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + _pq_sin_fx0((uint32_t)(*pSrc++) << 16U); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); } } - if (length) + if (length > 0) { PQ_StartVectorQ15(pSrc, pDst, length); PQ_Vector8Q15(PQ_SIN, 1, PQ_TRIG_FIXED); @@ -752,7 +776,7 @@ void PQ_VectorCosQ15(int16_t *pSrc, int16_t *pDst, int32_t length) pq_float_t magic; pq_float_t valFloat; - magic.integerX = 0x30c90fdb; + magic.integerX = 0x30c90fdbU; #endif cppre = POWERQUAD->CPPRE; @@ -761,76 +785,76 @@ void PQ_VectorCosQ15(int16_t *pSrc, int16_t *pDst, int32_t length) int32_t remainderBy8 = length % 8; #if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); } } while (length > 0) { - valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); - valFloat.floatX = magic.floatX * (float)((*pSrc++) << 16); + valFloat.floatX = magic.floatX * (float)(uint32_t)((uint32_t)(*pSrc++) << 16U); _pq_cos0(valFloat.integerX); - _pq_readAdd0(); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + (void)_pq_readAdd0(); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); length -= 8; } #else - if (remainderBy8) + if (remainderBy8 > 0) { length -= remainderBy8; - while (remainderBy8--) + while ((remainderBy8--) > 0) { - _pq_cos_fx0((uint32_t)(*pSrc++) << 16); - *pDst++ = (_pq_readAdd0_fx()) >> 16; + _pq_cos_fx0((uint32_t)(*pSrc++) << 16U); + *pDst++ = (int16_t)(uint32_t)((_pq_readAdd0_fx()) >> 16U); } } - if (length) + if (length > 0) { PQ_StartVectorQ15(pSrc, pDst, length); PQ_Vector8Q15(PQ_COS, 1, PQ_TRIG_FIXED); @@ -843,22 +867,22 @@ void PQ_VectorCosQ15(int16_t *pSrc, int16_t *pDst, int32_t length) int32_t PQ_ArctanFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration) { - base->CORDIC_X = x; - base->CORDIC_Y = y; - base->CORDIC_Z = 0; - base->CONTROL = (CP_CORDIC << 4) | CORDIC_ARCTAN | CORDIC_ITER(iteration); + base->CORDIC_X = (uint32_t)x; + base->CORDIC_Y = (uint32_t)y; + base->CORDIC_Z = 0U; + base->CONTROL = (CP_CORDIC << 4U) | CORDIC_ARCTAN | CORDIC_ITER(iteration); PQ_WaitDone(base); - return base->CORDIC_Z; + return (int32_t)base->CORDIC_Z; } int32_t PQ_ArctanhFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration) { - base->CORDIC_X = x; - base->CORDIC_Y = y; - base->CORDIC_Z = 0; - base->CONTROL = (CP_CORDIC << 4) | CORDIC_ARCTANH | CORDIC_ITER(iteration); + base->CORDIC_X = (uint32_t)x; + base->CORDIC_Y = (uint32_t)y; + base->CORDIC_Z = 0U; + base->CONTROL = (CP_CORDIC << 4U) | CORDIC_ARCTANH | CORDIC_ITER(iteration); PQ_WaitDone(base); - return base->CORDIC_Z; + return (int32_t)base->CORDIC_Z; } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_matrix.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_matrix.c index 6d14e16336..6394cfd13b 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_matrix.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_matrix.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,114 +21,111 @@ ******************************************************************************/ void PQ_MatrixAddition(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) { - assert(pAData); - assert(pBData); - assert(pResult); + assert(NULL != pAData); + assert(NULL != pBData); + assert(NULL != pResult); - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pAData; - base->INBBASE = (int32_t)pBData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pAData; + base->INBBASE = (uint32_t)(uint32_t *)pBData; base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_ADD; + base->CONTROL = (CP_MTX << 4U) | PQ_MTX_ADD; } void PQ_MatrixSubtraction(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) { - assert(pAData); - assert(pBData); - assert(pResult); + assert(NULL != pAData); + assert(NULL != pBData); + assert(NULL != pResult); - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pAData; - base->INBBASE = (int32_t)pBData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pAData; + base->INBBASE = (uint32_t)(uint32_t *)pBData; base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_SUB; + base->CONTROL = (CP_MTX << 4U) | PQ_MTX_SUB; } void PQ_MatrixMultiplication(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) { - assert(pAData); - assert(pBData); - assert(pResult); + assert(NULL != pAData); + assert(NULL != pBData); + assert(NULL != pResult); - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pAData; - base->INBBASE = (int32_t)pBData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pAData; + base->INBBASE = (uint32_t)(uint32_t *)pBData; base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_MULT; + base->CONTROL = (CP_MTX << 4U) | PQ_MTX_MULT; } void PQ_MatrixProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) { - assert(pAData); - assert(pBData); - assert(pResult); + assert(NULL != pAData); + assert(NULL != pBData); + assert(NULL != pResult); - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pAData; - base->INBBASE = (int32_t)pBData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pAData; + base->INBBASE = (uint32_t)(uint32_t *)pBData; base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_PROD; + base->CONTROL = (CP_MTX << 4U) | PQ_MTX_PROD; } void PQ_VectorDotProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult) { - assert(pAData); - assert(pBData); - assert(pResult); + assert(NULL != pAData); + assert(NULL != pBData); + assert(NULL != pResult); - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pAData; - base->INBBASE = (int32_t)pBData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pAData; + base->INBBASE = (uint32_t)(uint32_t *)pBData; base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_VEC_DOTP; + base->CONTROL = (CP_MTX << 4U) | PQ_VEC_DOTP; } void PQ_MatrixInversion(POWERQUAD_Type *base, uint32_t length, void *pData, void *pTmpData, void *pResult) { - assert(pData); - assert(pTmpData); - assert(pResult); + assert(NULL != pData); + assert(NULL != pTmpData); + assert(NULL != pResult); /* Workaround: * * Matrix inv depends on the coproc 1/x function, this puts coproc to right state. */ - _pq_inv0(1.0); + _pq_inv0(1.0f); - base->INABASE = (uint32_t)pData; - base->TMPBASE = (uint32_t)pTmpData; - base->OUTBASE = (uint32_t)pResult; + base->INABASE = (uint32_t)(uint32_t *)pData; + base->TMPBASE = (uint32_t)(uint32_t *)pTmpData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_INV; + base->CONTROL = (CP_MTX << 4U) | PQ_MTX_INV; } void PQ_MatrixTranspose(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) { - assert(pData); - assert(pResult); + assert(NULL != pData); + assert(NULL != pResult); - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pData; base->LENGTH = length; - base->CONTROL = (CP_MTX << 4) | PQ_MTX_TRAN; + base->CONTROL = (CP_MTX << 4U) | PQ_MTX_TRAN; } -void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, void *pData, void *pResult) +void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, const void *pData, void *pResult) { - assert(pData); - assert(pResult); + assert(NULL != pData); + assert(NULL != pResult); + pq_float_t val; - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(const uint32_t *)pData; base->LENGTH = length; -#if defined(__GNUC__) -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wstrict-aliasing" -#endif - base->MISC = *(uint32_t *)&misc; -#if defined(__GNUC__) -#pragma GCC diagnostic pop -#endif - base->CONTROL = (CP_MTX << 4) | PQ_MTX_SCALE; + + val.floatX = misc; + base->MISC = val.integerX; + + base->CONTROL = (CP_MTX << 4U) | PQ_MTX_SCALE; } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_transform.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_transform.c index 43c8285030..9a7d3244f8 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_transform.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_powerquad_transform.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,83 +21,83 @@ ******************************************************************************/ void PQ_TransformCFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) { - assert(pData); - assert(pResult); + assert(NULL != pData); + assert(NULL != pResult); - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pData; base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_CFFT; + base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_CFFT; } void PQ_TransformRFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) { - assert(pData); - assert(pResult); + assert(NULL != pData); + assert(NULL != pResult); /* Set 0's for imaginary inputs as not be reading them in by the machine */ - base->GPREG[1] = 0; - base->GPREG[3] = 0; - base->GPREG[5] = 0; - base->GPREG[7] = 0; - base->GPREG[9] = 0; - base->GPREG[11] = 0; - base->GPREG[13] = 0; - base->GPREG[15] = 0; - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; + base->GPREG[1] = 0U; + base->GPREG[3] = 0U; + base->GPREG[5] = 0U; + base->GPREG[7] = 0U; + base->GPREG[9] = 0U; + base->GPREG[11] = 0U; + base->GPREG[13] = 0U; + base->GPREG[15] = 0U; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pData; base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_RFFT; + base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_RFFT; } void PQ_TransformIFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) { - assert(pData); - assert(pResult); + assert(NULL != pData); + assert(NULL != pResult); - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pData; base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_IFFT; + base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_IFFT; } void PQ_TransformCDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) { - assert(pData); - assert(pResult); + assert(NULL != pData); + assert(NULL != pResult); - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pData; base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_CDCT; + base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_CDCT; } void PQ_TransformRDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) { - assert(pData); - assert(pResult); + assert(NULL != pData); + assert(NULL != pResult); - base->GPREG[1] = 0; - base->GPREG[3] = 0; - base->GPREG[5] = 0; - base->GPREG[7] = 0; - base->GPREG[9] = 0; - base->GPREG[11] = 0; - base->GPREG[13] = 0; - base->GPREG[15] = 0; - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; + base->GPREG[1] = 0U; + base->GPREG[3] = 0U; + base->GPREG[5] = 0U; + base->GPREG[7] = 0U; + base->GPREG[9] = 0U; + base->GPREG[11] = 0U; + base->GPREG[13] = 0U; + base->GPREG[15] = 0U; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pData; base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_RDCT; + base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_RDCT; } void PQ_TransformIDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult) { - assert(pData); - assert(pResult); + assert(NULL != pData); + assert(NULL != pResult); - base->OUTBASE = (int32_t)pResult; - base->INABASE = (int32_t)pData; + base->OUTBASE = (uint32_t)(uint32_t *)pResult; + base->INABASE = (uint32_t)(uint32_t *)pData; base->LENGTH = length; - base->CONTROL = (CP_FFT << 4) | PQ_TRANS_IDCT; + base->CONTROL = (CP_FFT << 4U) | PQ_TRANS_IDCT; } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.c index e312282352..63e4c27852 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018 - 2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,54 +23,189 @@ /******************************************************************************* * Code ******************************************************************************/ +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +static secure_bool_t PRINCE_CheckerAlgorithm(uint32_t address, + uint32_t length, + prince_flags_t flag, + flash_config_t *flash_context) +{ + uint32_t temp_base = 0, temp_sr = 0, region_index = 0, contiguous_start_index = 0, contiguous_end_index = 32; + secure_bool_t is_prince_region_contiguous = kSECURE_TRUE; + uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; + + if (address >= flash_context->ffrConfig.ffrBlockBase) + { + /* If it is not in flash region, return true to allow erase/write operation. */ + return kSECURE_TRUE; + } + + /* Iterate for all PRINCE regions */ + for (region_index = (uint32_t)kPRINCE_Region0; region_index <= (uint32_t)kPRINCE_Region2; region_index++) + { + contiguous_start_index = 0; + contiguous_end_index = 32; + switch (region_index) + { + case (uint32_t)kPRINCE_Region0: + temp_base = PRINCE->BASE_ADDR0; + temp_sr = PRINCE->SR_ENABLE0; + break; + + case (uint32_t)kPRINCE_Region1: + temp_base = PRINCE->BASE_ADDR1; + temp_sr = PRINCE->SR_ENABLE1; + break; + + case (uint32_t)kPRINCE_Region2: + temp_base = PRINCE->BASE_ADDR2; + temp_sr = PRINCE->SR_ENABLE2; + break; + + default: + /* All the cases have been listed above, the default clause should not be reached. */ + break; + } + + if (((address >= temp_base) && + ((address + length) < (temp_base + (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 32U * 1024U)))) && + (temp_sr != 0U)) + { + /* Check if the mask is contiguous */ + secure_bool_t first_set_bit_found = kSECURE_FALSE; + secure_bool_t contiguous_end_found = kSECURE_FALSE; + for (uint32_t i = 0; i < 32U; i++) + { + if (0U != (temp_sr & (1UL << i))) + { + if (kSECURE_FALSE == first_set_bit_found) + { + first_set_bit_found = kSECURE_TRUE; + contiguous_start_index = i; + } + if (kSECURE_TRUE == contiguous_end_found) + { + is_prince_region_contiguous = kSECURE_FALSE; + break; + } + } + else + { + if ((kSECURE_TRUE == first_set_bit_found) && (kSECURE_FALSE == contiguous_end_found)) + { + contiguous_end_found = kSECURE_TRUE; + contiguous_end_index = i; + } + } + } + } + else + { + continue; /* No encryption enabled, continue with the next region checking. */ + } + + /* Check if the provided memory range covers all addresses defined in the SR mask */ + if ((kSECURE_TRUE == is_prince_region_contiguous) && + ((address <= (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) && + (((address + length) >= + (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U))))) + { + /* In case of erase operation, invalidate the old PRINCE IV by regenerating the new one */ + if (kPRINCE_Flag_EraseCheck == flag) + { + /* Re-generate the PRINCE IV in case of erase operation */ + + /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ + if (kStatus_Success == + PRINCE_GenNewIV((prince_region_t)region_index, &prince_iv_code[0], true, flash_context)) + { + /* Store the new IV for the PRINCE region into PRINCE registers. */ + if (kStatus_Success == PRINCE_LoadIV((prince_region_t)region_index, &prince_iv_code[0])) + { + /* Encryption is enabled, all subregions are to be erased/written at once, IV successfully + * regenerated, return true to allow erase operation. */ + return kSECURE_TRUE; + } + } + /* Encryption is enabled, all subregions are to be erased/written at once but IV has not been correctly + * regenerated, return false to disable erase operation. */ + return kSECURE_FALSE; + } + + /* Encryption is enabled and all subregions are to be erased/written at once, return true to allow + * erase/write operation. */ + return kSECURE_TRUE; + } + /* The provided memory range does not cover all addresses defined in the SR mask. */ + else + { + /* Is the provided memory range outside the addresses defined by the SR mask? */ + if ((kSECURE_TRUE == is_prince_region_contiguous) && + ((((address + length) <= + (temp_base + (contiguous_start_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))) || + ((address >= (temp_base + (contiguous_end_index * FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U)))))) + { + /* No encryption enabled for the provided memory range, true could be returned to allow erase/write + operation, but due to the same base address for all three prince regions on Niobe4Mini we should + continue with other regions (SR mask) checking. */ + continue; + } + else + { + /* Encryption is enabled but not all subregions are to be erased/written at once, return false to + * disable erase/write operation. */ + return kSECURE_FALSE; + } + } + } + return kSECURE_TRUE; +} +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) /*! - * brief Generate new IV code. + * @brief Generate new IV code. * * This function generates new IV code and stores it into the persistent memory. * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! * - * param region PRINCE region index. - * param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. - * param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * param flash_context pointer to the flash driver context structure. + * @param region PRINCE region index. + * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. + * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). + * @param flash_context pointer to the flash driver context structure. * - * return kStatus_Success upon success - * return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular * PRINCE region is not present in the keystore (though new IV code has been provided) */ status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context) { - status_t retVal = kStatus_Fail; + status_t status = kStatus_Fail; uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; - - if (((SYSCON->PERIPHENCFG & SYSCON_PERIPHENCFG_PRINCEEN_MASK) ? true : false) == false) - { - return retVal; /* PRINCE peripheral not enabled, return kStatus_Fail. */ - } + uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; /* Make sure PUF is started to allow key and IV code decryption and generation */ if (true != PUF_IsGetKeyAllowed(PUF)) { - return retVal; + return status; } /* Generate new IV code for the PRINCE region */ - retVal = PUF_SetIntrinsicKey(PUF, (puf_key_index_register_t)(kPUF_KeyIndex_02 + (puf_key_index_register_t)region), - 8, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - if ((kStatus_Success == retVal) && (true == store)) + status = + PUF_SetIntrinsicKey(PUF, (puf_key_index_register_t)(uint32_t)((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region), 8, + &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); + if ((kStatus_Success == status) && (true == store)) { /* Store the new IV code for the PRINCE region into the respective FFRs. */ /* Create a new version of "Customer Field Programmable" (CFP) page. */ - if (kStatus_FLASH_Success == + if ((int32_t)kStatus_FLASH_Success == FFR_GetCustomerInfieldData(flash_context, (uint8_t *)tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) { /* Set the IV code in the page */ - memcpy(&tempBuffer[offsetof(cfpa_cfg_info_t, ivCodePrinceRegion) + ((region * sizeof(cfpa_cfg_iv_code_t))) + - 4], - &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); + (void)memcpy(&tempBuffer[offsetof(cfpa_cfg_info_t, ivCodePrinceRegion) + + (((uint32_t)region * sizeof(cfpa_cfg_iv_code_t))) + 4U], + &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); - uint32_t *p32 = (uint32_t *)tempBuffer; + uint32_t *p32 = (uint32_t *)(uint32_t)tempBuffer; uint32_t version = p32[1]; if (version == 0xFFFFFFFFu) { @@ -80,197 +215,243 @@ status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, f p32[1] = version; /* Program the page and enable firewall for "Customer field area" */ - if (kStatus_FLASH_Success == + if ((int32_t)kStatus_FLASH_Success == FFR_InfieldPageWrite(flash_context, (uint8_t *)tempBuffer, FLASH_FFR_MAX_PAGE_SIZE)) { - retVal = kStatus_Success; + status = kStatus_Success; } else { - retVal = kStatus_Fail; + status = kStatus_Fail; } } } - if (retVal == kStatus_Success) + if (status == kStatus_Success) { /* Pass the new IV code */ - memcpy(iv_code, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); + (void)memcpy(iv_code, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE); } - return retVal; -} + return status; +} +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) /*! - * brief Load IV code. + * @brief Load IV code. * * This function enables IV code loading into the PRINCE bus encryption engine. * - * param region PRINCE region index. - * param iv_code IV code pointer used for passing the IV code. + * @param region PRINCE region index. + * @param iv_code IV code pointer used for passing the IV code. * - * return kStatus_Success upon success - * return kStatus_Fail otherwise + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise */ status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code) { - status_t retVal = kStatus_Fail; - uint32_t keyIndex = 0x0Fu & iv_code[1]; + status_t status = kStatus_Fail; + uint32_t keyIndex = (0x0Fu & (uint32_t)iv_code[1]); uint8_t prince_iv[8] = {0}; - if (((SYSCON->PERIPHENCFG & SYSCON_PERIPHENCFG_PRINCEEN_MASK) ? true : false) == false) - { - return retVal; /* PRINCE peripheral not enabled, return kStatus_Fail. */ - } - /* Make sure PUF is started to allow key and IV code decryption and generation */ if (true != PUF_IsGetKeyAllowed(PUF)) { - return retVal; + return kStatus_Fail; } /* Check if region number matches the PUF index value */ - if ((kPUF_KeyIndex_02 + (puf_key_index_register_t)region) == (puf_key_index_register_t)keyIndex) + if (((uint32_t)kPUF_KeyIndex_02 + (uint32_t)region) == (uint32_t)keyIndex) { /* Decrypt the IV */ if (kStatus_Success == PUF_GetKey(PUF, iv_code, FLASH_FFR_IV_CODE_SIZE, &prince_iv[0], 8)) { /* Store the new IV for the PRINCE region into PRINCE registers. */ - PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, prince_iv); - retVal = kStatus_Success; + (void)PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, prince_iv); + status = kStatus_Success; } } - return retVal; -} + return status; +} +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) /*! - * brief Allow encryption/decryption for specified address range. + * @brief Allow encryption/decryption for specified address range. * * This function sets the encryption/decryption for specified address range. + * The SR mask value for the selected Prince region is calculated from provided + * start_address and length parameters. This calculated value is OR'ed with the + * actual SR mask value and stored into the PRINCE SR_ENABLE register and also + * into the persistent memory (FFR) to be used after the device reset. It is + * possible to define several nonadjacent encrypted areas within one Prince + * region when calling this function repeatedly. If the length parameter is set + * to 0, the SR mask value is set to 0 and thus the encryption/decryption for + * the whole selected Prince region is disabled. * Ensure about 800 bytes free space on the stack when calling this routine! * - * param region PRINCE region index. - * param start_address start address of the area to be encrypted/decrypted. - * param length length of the area to be encrypted/decrypted. - * param flash_context pointer to the flash driver context structure. + * @param region PRINCE region index. + * @param start_address start address of the area to be encrypted/decrypted. + * @param length length of the area to be encrypted/decrypted. + * @param flash_context pointer to the flash driver context structure. + * @param regenerate_iv flag to allow IV code regenerating, storing into + * the persistent memory (FFR) and loading into the PRINCE engine * - * return kStatus_Success upon success - * return kStatus_Fail otherwise + * @return kStatus_Success upon success + * @return kStatus_Fail otherwise */ -status_t PRINCE_SetEncryptForAddressRange(prince_region_t region, - uint32_t start_address, - uint32_t length, - flash_config_t *flash_context) +status_t PRINCE_SetEncryptForAddressRange( + prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv) { - status_t retVal = kStatus_Fail; + status_t status = kStatus_Fail; uint32_t srEnableRegister = 0; uint32_t alignedStartAddress; - uint32_t end_address = start_address + length; - uint32_t prince_region_base_address = 0; - uint8_t my_prince_iv_code[52] = {0}; - uint8_t tempBuffer[512] = {0}; - uint32_t prince_base_addr_ffr_word = 0; + uint32_t prince_base_addr_ffr_word = 0; + uint32_t end_address = start_address + length; + uint32_t prince_region_base_address = 0; + uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0}; - /* Check the address range, regions overlaping. */ - if ((start_address > 0xA0000) || ((start_address < 0x40000) && (end_address > 0x40000)) || - ((start_address < 0x80000) && (end_address > 0x80000)) || - ((start_address < 0xA0000) && (end_address > 0xA0000))) + /* Check input parameters. */ + if (NULL == flash_context) { return kStatus_Fail; } - /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ - retVal = PRINCE_GenNewIV((prince_region_t)region, &my_prince_iv_code[0], true, flash_context); - if (kStatus_Success != retVal) + /* Check the address range, region borders crossing. */ +#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ + (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) + if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || + ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) { return kStatus_Fail; } - - /* Store the new IV for the PRINCE region into PRINCE registers. */ - retVal = PRINCE_LoadIV((prince_region_t)region, &my_prince_iv_code[0]); - if (kStatus_Success != retVal) +#endif +#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) + if ((start_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) || + ((start_address < 0x40000U) && (end_address > 0x40000U)) || + ((start_address < 0x80000U) && (end_address > 0x80000U)) || + ((start_address < FSL_PRINCE_DRIVER_MAX_FLASH_ADDR) && (end_address > FSL_PRINCE_DRIVER_MAX_FLASH_ADDR))) { return kStatus_Fail; } +#endif - alignedStartAddress = ALIGN_DOWN(start_address, FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); + if (true == regenerate_iv) + { + uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0}; - uint32_t subregion = alignedStartAddress / (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); - if (subregion < (32)) + /* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */ + status = PRINCE_GenNewIV((prince_region_t)region, &prince_iv_code[0], true, flash_context); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Store the new IV for the PRINCE region into PRINCE registers. */ + status = PRINCE_LoadIV((prince_region_t)region, &prince_iv_code[0]); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + } + + alignedStartAddress = ALIGN_DOWN(start_address, (int32_t)FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); + + uint32_t subregion = alignedStartAddress / (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); + if (subregion < (32U)) { /* PRINCE_Region0 */ prince_region_base_address = 0; } - else if (subregion < (64)) + else if (subregion < (64U)) { /* PRINCE_Region1 */ - subregion = subregion - 32; + subregion = subregion - 32U; prince_region_base_address = 0x40000; } else { /* PRINCE_Region2 */ - subregion = subregion - 64; + subregion = subregion - 64U; prince_region_base_address = 0x80000; } - srEnableRegister = (1 << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); - - while (alignedStartAddress < (start_address + length)) + /* If length > 0 then srEnableRegister mask is set based on the alignedStartAddress and the length. + If the length is 0, srEnableRegister should be kept 0 (no subregion enabled). */ + if (length != 0U) { - subregion++; - srEnableRegister |= (1 << subregion); - alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024); + srEnableRegister = (1UL << subregion); + alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); + + while (alignedStartAddress < (start_address + length)) + { + subregion++; + srEnableRegister |= (1UL << subregion); + alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024U); + } + + uint32_t srEnableRegisterActual = 0; + (void)PRINCE_GetRegionSREnable(PRINCE, (prince_region_t)region, &srEnableRegisterActual); + srEnableRegister |= srEnableRegisterActual; } /* Store BASE_ADDR into PRINCE register before storing the SR to avoid en/decryption triggering from addresses being defined by current BASE_ADDR register content (could be 0 and the decryption of actually executed code can be started causing the hardfault then). */ - retVal = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, prince_region_base_address); - if (kStatus_Success != retVal) + status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, prince_region_base_address); + if (kStatus_Success != status) { - return retVal; + return status; } /* Store SR into PRINCE register */ - retVal = PRINCE_SetRegionSREnable(PRINCE, (prince_region_t)region, srEnableRegister); - if (kStatus_Success != retVal) + status = PRINCE_SetRegionSREnable(PRINCE, (prince_region_t)region, srEnableRegister); + if (kStatus_Success != status) { - return retVal; + return status; } /* Store SR and BASE_ADDR into CMPA FFR */ if (kStatus_Success == FFR_GetCustomerData(flash_context, (uint8_t *)&tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE)) { /* Set the PRINCE_SR_X in the page */ - memcpy(&tempBuffer[offsetof(cmpa_cfg_info_t, princeSr) + (region * sizeof(uint32_t))], &srEnableRegister, - sizeof(uint32_t)); - + (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeSr) + + ((uint32_t)region * sizeof(uint32_t))], + &srEnableRegister, sizeof(uint32_t)); /* Set the ADDRX_PRG in the page */ - memcpy(&prince_base_addr_ffr_word, &tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], sizeof(uint32_t)); - prince_base_addr_ffr_word &= ~((FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << (region * 4)); - prince_base_addr_ffr_word |= - (((prince_region_base_address >> 18) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << (region * 4)); - memcpy(&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], &prince_base_addr_ffr_word, sizeof(uint32_t)); + (void)memcpy(&prince_base_addr_ffr_word, + (const uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], + sizeof(uint32_t)); + prince_base_addr_ffr_word &= + ~(((uint32_t)FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << ((uint32_t)region * 4U)); + prince_base_addr_ffr_word |= (((prince_region_base_address >> PRINCE_BASE_ADDR0_ADDR_PRG_SHIFT) & + FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) + << ((uint32_t)region * 4U)); + (void)memcpy((uint32_t *)(uintptr_t)&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], + &prince_base_addr_ffr_word, sizeof(uint32_t)); - /* Program the CMPA page, set seal_part parameter to false (used during development to avoid sealing the part) + /* Program the CMPA page, set seal_part parameter to false (used during development to avoid sealing the + * part) */ - retVal = FFR_CustFactoryPageWrite(flash_context, (uint8_t *)tempBuffer, false); + status = FFR_CustFactoryPageWrite(flash_context, (uint8_t *)tempBuffer, false); } - return retVal; + return status; } +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ /*! - * brief Gets the PRINCE Sub-Region Enable register. + * @brief Gets the PRINCE Sub-Region Enable register. * * This function gets PRINCE SR_ENABLE register. * - * param base PRINCE peripheral address. - * param region PRINCE region index. - * param sr_enable Sub-Region Enable register pointer. + * @param base PRINCE peripheral address. + * @param region PRINCE region index. + * @param sr_enable Sub-Region Enable register pointer. * - * return kStatus_Success upon success - * return kStatus_InvalidArgument + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument */ status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable) { @@ -299,16 +480,16 @@ status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uin } /*! - * brief Gets the PRINCE region base address register. + * @brief Gets the PRINCE region base address register. * * This function gets PRINCE BASE_ADDR register. * - * param base PRINCE peripheral address. - * param region PRINCE region index. - * param region_base_addr Region base address pointer. + * @param base PRINCE peripheral address. + * @param region PRINCE region index. + * @param region_base_addr Region base address pointer. * - * return kStatus_Success upon success - * return kStatus_InvalidArgument + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument */ status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr) { @@ -344,10 +525,13 @@ status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, * @param base PRINCE peripheral address. * @param region Selection of the PRINCE region to be configured. * @param iv 64-bit AES IV in little-endian byte order. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument */ status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]) { - status_t status = kStatus_Fail; + status_t status = kStatus_Fail; volatile uint32_t *IVMsb_reg = NULL; volatile uint32_t *IVLsb_reg = NULL; @@ -377,7 +561,7 @@ status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uin { *IVLsb_reg = ((uint32_t *)(uintptr_t)iv)[0]; *IVMsb_reg = ((uint32_t *)(uintptr_t)iv)[1]; - status = kStatus_Success; + status = kStatus_Success; } return status; @@ -391,11 +575,29 @@ status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uin * @param base PRINCE peripheral address. * @param region Selection of the PRINCE region to be configured. * @param region_base_addr Base Address for region. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument */ status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr) { status_t status = kStatus_Success; + /* Check input parameters. */ +#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || (defined(FSL_PRINCE_DRIVER_LPC55S1x)) || \ + (defined(FSL_PRINCE_DRIVER_LPC55S2x)) || (defined(FSL_PRINCE_DRIVER_LPC55S3x)) + if (region_base_addr > 0U) + { + return kStatus_InvalidArgument; + } +#endif +#if (defined(FSL_PRINCE_DRIVER_LPC55S6x)) + if (region_base_addr > 0x80000U) + { + return kStatus_InvalidArgument; + } +#endif + switch (region) { case kPRINCE_Region0: @@ -426,6 +628,9 @@ status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, * @param base PRINCE peripheral address. * @param region Selection of the PRINCE region to be configured. * @param sr_enable Sub-Region Enable register value. + * + * @return kStatus_Success upon success + * @return kStatus_InvalidArgument */ status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable) { @@ -452,3 +657,440 @@ status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uin return status; } + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. It deals with the flash erase function + * complenentary to the standard erase API of the IAP1 driver. This implementation + * additionally checks if the whole encrypted PRINCE subregions are erased at once + * to avoid secrets revealing. The checker implementation is limited to one contiguous + * PRINCE-controlled memory area. + * + * @param config The pointer to the flash driver context structure. + * @param start The start address of the desired flash memory to be erased. + * The start address needs to be prince-sburegion-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be prince-sburegion-size-aligned. + * @param key The value used to validate all flash erase APIs. + * + * @return #kStatus_FLASH_Success API was executed successfully. + * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @return #kStatus_FLASH_AddressError The address is out of range. + * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. + */ +status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key) +{ + /* Check input parameters. */ + if (NULL == config) + { + return kStatus_Fail; + } + /* Check that the whole encrypted region is erased at once. */ + if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_EraseCheck, config)) + { + return (int32_t)kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce; + } + return FLASH_Erase(config, start, lengthInBytes, key); +} + +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. It deals with the + * flash program function complenentary to the standard program API of the IAP1 driver. + * This implementation additionally checks if the whole PRINCE subregions are + * programmed at once to avoid secrets revealing. The checker implementation is limited + * to one contiguous PRINCE-controlled memory area. + * + * @param config The pointer to the flash driver context structure. + * @param start The start address of the desired flash memory to be programmed. Must be + * prince-sburegion-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be prince-sburegion-size-aligned. + * + * @return #kStatus_FLASH_Success API was executed successfully. + * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @return #kStatus_FLASH_AddressError Address is out of range. + * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. + */ +status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes) +{ + /* Check input parameters. */ + if (NULL == config) + { + return kStatus_Fail; + } + /* Check that the whole encrypted subregions will be writen at once. */ + if (kSECURE_TRUE != PRINCE_CheckerAlgorithm(start, lengthInBytes, kPRINCE_Flag_WriteCheck, config)) + { + return (int32_t)kStatus_FLASH_SizeError; + } + return FLASH_Program(config, start, src, lengthInBytes); +} +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if defined(FSL_PRINCE_DRIVER_LPC55S3x) +static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen); +static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp); +static status_t PRINCE_CSS_gen_iv_key(void); +static status_t PRINCE_CSS_enable(void); +static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg); + +/*! + * @brief Configures PRINCE setting. + * + * This function does the initial PRINCE configuration via ROM IAP API call. + * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). + * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. + * + * Note: This function is expected to be called once in the device lifetime, + * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. + * + * @param coreCtx The pointer to the ROM API driver context structure. + * @param config The pointer to the PRINCE driver configuration structure. + * + * @retval #kStatus_Success + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_InvalidArgument + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_Fail + * @retval #kStatus_OutOfRange + * @retval #kStatus_SPI_BaudrateNotSupport + */ +status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config) +{ + /* Enable CSS and check keys */ + if (kStatus_Success != PRINCE_CSS_enable()) + { + return kStatus_Fail; + } + + return MEM_Config(coreCtx, (uint32_t *)config, kMemoryInternal); +} + +/*! + * @brief Configures PRINCE setting. + * + * This function is used to re-configure PRINCE IP based on configuration stored in FFR. + * This function also needs to be called after wake up from power-down mode to regenerate IV + * encryption key in CSS key store whose presence is necessary for correct PRINCE operation + * during erase and write operations to encrypted regions of internal flash memory + * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). + * + * @param coreCtx The pointer to the ROM API driver context structure. + * + * @retval #kStatus_Success + * @retval #kStatus_Fail + */ +status_t PRINCE_Reconfigure(api_core_context_t *coreCtx) +{ + status_t status = kStatus_Fail; + uint64_t princeMask; + uint32_t IvReg[4] = {0}; + uint32_t ivEraseCounter[3]; + uint32_t srEnable[3]; + uint32_t uuid[4]; + flash_config_t flash_config; + uint32_t lockWord; + uint8_t lock[3]; + + /* Enable CSS and check keys */ + status = PRINCE_CSS_enable(); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Set PRINCE mask value. */ + status = PRINCE_CSS_generate_random((uint8_t *)&princeMask, sizeof(princeMask)); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + PRINCE_SetMask(PRINCE, princeMask); + + /* Clean up Flash driver structure and Init*/ + memset(&flash_config, 0, sizeof(flash_config_t)); + if (FLASH_Init(&flash_config) != kStatus_Success) + { + return kStatus_Fail; + } + + /* FFR Init */ + if (FFR_Init(&flash_config) != kStatus_Success) + { + return kStatus_Fail; + } + + /* Get UUID from FFR */ + status = FFR_GetUUID(&flash_config, (uint8_t *)uuid); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Check version of CFPA scratch first */ + uint32_t cfpaScratchVer = 0u; + memcpy(&cfpaScratchVer, (void *)(CFPA_SCRATCH_VER), sizeof(uint32_t)); + + /* Get CFPA version using FFR ROM API */ + uint32_t cfpaVer = 0u; + if (kStatus_Success != + FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)&cfpaVer, CFPA_VER_OFFSET, sizeof(uint32_t))) + { + status = kStatus_Fail; + return status; + } + + /* Compare the version of CFPA scratch and version of CFPA returned by ROM API */ + if (cfpaScratchVer > cfpaVer) + { + /* Get PRINCE_IV_CTRs from CFPA scratch */ + memcpy(&ivEraseCounter, (void *)CFPA_SCRATCH_IV, sizeof(uint32_t) * PRINCE_REGION_COUNT); + } + else + { + /* Get PRINCE_IV_CTRs IVs from CFPA ping/pong page */ + status = FFR_GetCustomerInfieldData(&flash_config, (uint8_t *)ivEraseCounter, CFPA_PRINCE_IV_OFFSET, + sizeof(uint32_t) * PRINCE_REGION_COUNT); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + } + + /* Get PRINCE sub-region enable word from FFR */ + status = FFR_GetCustomerData(&flash_config, (uint8_t *)srEnable, CMPA_PRINCE_SR_OFFSET, + sizeof(uint32_t) * PRINCE_REGION_COUNT); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Get PRINCE lock setting from FFR */ + status = FFR_GetCustomerData(&flash_config, (uint8_t *)&lockWord, CMPA_PRINCE_LOCK_OFFSET, sizeof(uint32_t)); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + lock[0] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG0_MASK) >> PRINCE_BASE_ADDR_LOCK_REG0_SHIFT; + lock[1] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG1_MASK) >> PRINCE_BASE_ADDR_LOCK_REG1_SHIFT; + lock[2] = (lockWord & PRINCE_BASE_ADDR_LOCK_REG2_MASK) >> PRINCE_BASE_ADDR_LOCK_REG2_SHIFT; + + /* Iterate for all internal PRINCE regions */ + for (prince_region_t region = kPRINCE_Region0; region <= kPRINCE_Region2; region++) + { + /* Set region base address. Should be always 0x0 on LPC55S36 */ + status = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, 0x0u); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + status = PRINCE_SetRegionSREnable(PRINCE, region, srEnable[region]); + if (kStatus_Success != status) + { + return kStatus_Fail; + } + + /* Prepare ivSeed for current region */ + IvReg[0] = uuid[0]; + IvReg[1] = uuid[1]; + IvReg[2] = uuid[2] ^ region; + IvReg[3] = ivEraseCounter[region]; + + /* Calculate IV as IvReg = AES_ECB_ENC(DUK_derived_key, {ctx_erase_counter, ctx_id}) */ + status = PRINCE_CSS_calculate_iv(IvReg); + if (status != kStatus_Success) + { + return kStatus_Fail; + } + + /* Load IV into PRINCE registers */ + status = PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, (uint8_t *)IvReg); + if (status != kStatus_Success) + { + return kStatus_Fail; + } + + /* Lock region if required */ + if ((lock[region] == 0x1u) || (lock[region] == 0x2u) || (lock[region] == 0x3u)) + { + PRINCE_SetLock(PRINCE, (kPRINCE_Region0Lock << region)); + } + } + + /* Break the main loop in case that error occured during PRINCE configuration */ + if (status != kStatus_Success) + { + return kStatus_Fail; + } + + /* When ENC_ENABLE is set, reading from PRINCE-encrypted regions is disabled. */ + /* For LPC55S36, the ENC_ENABLE is self-cleared after programming memory. */ + PRINCE_EncryptDisable(PRINCE); + return status; +} + +static status_t PRINCE_CSS_generate_random(uint8_t *output, size_t outputByteLen) +{ + status_t status = kStatus_Fail; + + // PRNG needs to be initialized; this can be done by calling mcuxClCss_KeyDelete_Async + // (delete any key slot, can be empty) + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_KeyDelete_Async(18)); + // mcuxClCss_KeyDelete_Async is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_KeyDelete_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) + return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_KeyDelete_Async operation was + // started. + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + // Wait for operation to finish + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); + // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) != token) || (MCUXCLCSS_STATUS_OK != result)) + return kStatus_Fail; // Expect that no error occurred, meaning that the mcuxClCss_WaitForOperation operation was + // started. + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_Prng_GetRandom(output, outputByteLen)); + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Prng_GetRandom) != token) || (MCUXCLCSS_STATUS_OK != result)) + return kStatus_Fail; + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + status = kStatus_Success; + return status; +} + +static status_t PRINCE_CSS_check_key(uint8_t keyIdx, mcuxClCss_KeyProp_t *pKeyProp) +{ + /* Check if CSS required keys are available in CSS keystore */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, + mcuxClCss_GetKeyProperties(keyIdx, pKeyProp)); // Get key propertis from the CSS. + // mcuxClCss_GetKeyProperties is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_GetKeyProperties) != token) || (MCUXCLCSS_STATUS_OK != result)) + return kStatus_Fail; + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + return kStatus_Success; +} + +static status_t PRINCE_CSS_gen_iv_key(void) +{ + /* The NXP_DIE_MEM_IV_ENC_SK is not loaded and needs to be regenerated (power-down wakeup) */ + /* Set KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK */ + SYSCON->CSS_KDF_MASK = SYSCON_CSS_KDF_MASK; + static const uint32_t ddata2[3] = {0x62032504, 0x72f04280, 0x87a2bbae}; + mcuxClCss_KeyProp_t keyProp; + /* Set key properties in structure */ + keyProp.word.value = CSS_CSS_KS2_ks2_uaes_MASK | CSS_CSS_KS2_ks2_fgp_MASK | CSS_CSS_KS2_ks2_kact_MASK; + status_t status = kStatus_Fail; + + /* Generate the key using CKDF */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( + result, token, + mcuxClCss_Ckdf_Sp800108_Async((mcuxClCss_KeyIndex_t)0, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, keyProp, + (uint8_t const *)ddata2)); + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Ckdf_Sp800108_Async) != token) && (MCUXCLCSS_STATUS_OK != result)) + { + return kStatus_Fail; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + /* Wait for CKDF to finish */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN(result, token, mcuxClCss_WaitForOperation(MCUXCLCSS_ERROR_FLAGS_CLEAR)); + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) + { + status = kStatus_Success; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + return status; +} + +static status_t PRINCE_CSS_enable(void) +{ + mcuxClCss_KeyProp_t key_properties; + status_t status = kStatus_Fail; + + /* Enable CSS and related clocks */ + status = CSS_PowerDownWakeupInit(CSS); + if (status != kStatus_Success) + { + return kStatus_Fail; + } + + /* Check if MEM_ENC_SK key is available in CSS keystore */ + status = PRINCE_CSS_check_key(NXP_DIE_MEM_ENC_SK, &key_properties); + if (status != kStatus_Success || key_properties.bits.kactv != 1u) + { + return kStatus_Fail; + } + + /* Check if MEM_IV_ENC_SK key is available in CSS keystore */ + status = PRINCE_CSS_check_key(NXP_DIE_MEM_IV_ENC_SK, &key_properties); + if (status != kStatus_Success || key_properties.bits.kactv != 1u) + { + return PRINCE_CSS_gen_iv_key(); + } + + return kStatus_Success; +} + +static status_t PRINCE_CSS_calculate_iv(uint32_t *IvReg) +{ + mcuxClCss_CipherOption_t cipherOptions = {0}; + status_t status = kStatus_Fail; + + /* Configure CSS for AES ECB-128, using NXP_DIE_MEM_IV_ENC_SK key */ + cipherOptions.bits.cphmde = MCUXCLCSS_CIPHERPARAM_ALGORITHM_AES_ECB; + cipherOptions.bits.dcrpt = MCUXCLCSS_CIPHER_ENCRYPT; + cipherOptions.bits.extkey = MCUXCLCSS_CIPHER_INTERNAL_KEY; + + do + { + /* Calculate IV as IvReg = AES_ECB_ENC(NXP_DIE_MEM_IV_ENC_SK, ivSeed[127:0]) */ + /* ivSeed[127:0] = {UUID[96:0] ^ regionNumber[1:0], ivEraseCounter[31:0]} */ + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( + result, token, + mcuxClCss_Cipher_Async(cipherOptions, (mcuxClCss_KeyIndex_t)NXP_DIE_MEM_IV_ENC_SK, NULL, + MCUXCLCSS_CIPHER_KEY_SIZE_AES_128, (uint8_t *)IvReg, MCUXCLCSS_CIPHER_BLOCK_SIZE_AES, + NULL, (uint8_t *)IvReg)); + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_Cipher_Async) != token) || (MCUXCLCSS_STATUS_OK_WAIT != result)) + break; + MCUX_CSSL_FP_FUNCTION_CALL_END(); + + MCUX_CSSL_FP_FUNCTION_CALL_BEGIN( + result, token, + mcuxClCss_WaitForOperation( + MCUXCLCSS_ERROR_FLAGS_CLEAR)); // Wait for the mcuxClCss_Enable_Async operation to complete. + // mcuxClCss_WaitForOperation is a flow-protected function: Check the protection token and the return value + if ((MCUX_CSSL_FP_FUNCTION_CALLED(mcuxClCss_WaitForOperation) == token) && (MCUXCLCSS_STATUS_OK == result)) + { + status = kStatus_Success; + } + MCUX_CSSL_FP_FUNCTION_CALL_END(); + } while (0); + + return status; +} +#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.h index 04e37a48ac..1d702ae499 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_prince.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018 - 2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -9,8 +9,8 @@ #define _FSL_PRINCE_H_ #include "fsl_common.h" -#include "fsl_iap_ffr.h" -#include "fsl_puf.h" + +#include FFR_INCLUDE /*! * @addtogroup prince @@ -23,23 +23,92 @@ /*! @name Driver version */ /*@{*/ -/*! @brief PRINCE driver version 2.0.0. +/*! @brief PRINCE driver version 2.5.0. * - * Current version: 2.0.0 + * Current version: 2.5.0 * * Change log: * - Version 2.0.0 * - Initial version. + * - Version 2.1.0 + * - Update for the A1 rev. of LPC55Sxx serie. + * - Version 2.2.0 + * - Add runtime checking of the A0 and A1 rev. of LPC55Sxx serie to support + * both silicone revisions. + * - Version 2.3.0 + * - Add support for LPC55S1x and LPC55S2x series + * - Version 2.3.0 + * - Fix MISRA-2012 issues. + * - Version 2.3.1 + * - Add support for LPC55S0x series + * - Version 2.3.2 + * - Fix documentation of enumeration. Extend PRINCE example. + * - Version 2.4.0 + * - Add support for LPC55S3x series + * - Version 2.5.0 + * - Add PRINCE_Config() and PRINCE_Reconfig() features. */ -#define FSL_PRINCE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +#define FSL_PRINCE_DRIVER_VERSION (MAKE_VERSION(2, 5, 0)) /*@}*/ -#define FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB (8) +#if (defined(LPC55S04_SERIES) || defined(LPC55S06_SERIES)) +/* LPC55S0x series*/ +#define FSL_PRINCE_DRIVER_LPC55S0x +#include "fsl_puf.h" + +#elif (defined(LPC55S14_SERIES) || defined(LPC55S16_SERIES)) +/* LPC55S1x series*/ +#define FSL_PRINCE_DRIVER_LPC55S1x +#include "fsl_puf.h" + +#elif (defined(LPC55S26_SERIES) || defined(LPC55S28_SERIES)) +/* LPC55S2x series*/ +#define FSL_PRINCE_DRIVER_LPC55S2x +#include "fsl_puf.h" + +#elif (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \ + defined(LPC55S66_cm33_core0_SERIES) || defined(LPC55S66_cm33_core1_SERIES)) +/* LPC55S6x series*/ +#define FSL_PRINCE_DRIVER_LPC55S6x +#include "fsl_puf.h" + +#elif (defined(LPC55S36_SERIES)) +/* LPC55S3x series*/ +#define FSL_PRINCE_DRIVER_LPC55S3x +#define PRINCE PRINCE0 +#include "fsl_mem_interface.h" +#include "fsl_css.h" // Power Down Wake-up Init +#include // Interface to the entire nxpClCss component +#include // Code flow protection +#else +#error "No valid CPU defined!" +#endif + +#define FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB (8U) +#define FSL_PRINCE_DRIVER_MAX_FLASH_ADDR \ + ((uint32_t)FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES - (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 2U * 1024U)) #if !defined(ALIGN_DOWN) #define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a)))) #endif +/*! @brief Secure status enumeration. */ +typedef enum _skboot_status +{ + kStatus_SKBOOT_Success = 0x5ac3c35au, /*!< PRINCE Success */ + kStatus_SKBOOT_Fail = 0xc35ac35au, /*!< PRINCE Fail */ + kStatus_SKBOOT_InvalidArgument = 0xc35a5ac3u, /*!< PRINCE Invalid argument */ + kStatus_SKBOOT_KeyStoreMarkerInvalid = 0xc3c35a5au, /*!< PRINCE Invalid marker */ +} skboot_status_t; + +/*! @brief Secure boolean enumeration. */ +typedef enum _secure_bool +{ + kSECURE_TRUE = 0xc33cc33cU, /*!< PRINCE true */ + kSECURE_FALSE = 0x5aa55aa5U, /*!< PRINCE false */ +} secure_bool_t; + +/*! @brief Prince region. */ typedef enum _prince_region { kPRINCE_Region0 = 0U, /*!< PRINCE region 0 */ @@ -47,14 +116,66 @@ typedef enum _prince_region kPRINCE_Region2 = 2U, /*!< PRINCE region 2 */ } prince_region_t; +/*! @brief Prince lock. */ typedef enum _prince_lock { - kPRINCE_Region0Lock = 1U, /*!< PRINCE region 0 lock */ - kPRINCE_Region1Lock = 2U, /*!< PRINCE region 1 lock */ - kPRINCE_Region2Lock = 4U, /*!< PRINCE region 2 lock */ - kPRINCE_MaskLock = 256U, /*!< PRINCE mask register lock */ + kPRINCE_Region0Lock = 1U, /*!< PRINCE region 0 lock */ + kPRINCE_Region1Lock = 2U, /*!< PRINCE region 1 lock */ + kPRINCE_Region2Lock = 4U, /*!< PRINCE region 2 lock */ + kPRINCE_MaskLock = 256U, /*!< PRINCE mask register lock */ } prince_lock_t; +/*! @brief Prince flag. */ +typedef enum _prince_flags +{ + kPRINCE_Flag_None = 0U, /*!< PRINCE Flag None */ + kPRINCE_Flag_EraseCheck = 1U, /*!< PRINCE Flag Erase check */ + kPRINCE_Flag_WriteCheck = 2U, /*!< PRINCE Flag Write check */ +} prince_flags_t; + +#if defined(FSL_PRINCE_DRIVER_LPC55S3x) +typedef struct +{ + uint32_t target_prince_region : 2; // 0/1/2 + uint32_t reserved : 22; + uint32_t tag : 8; // Fixed to 0x50 ('P') +} prince_prot_region_option_t; +typedef struct +{ + prince_prot_region_option_t option; + uint32_t start; + uint32_t length; +} prince_prot_region_arg_t; + +/*! @brief Prince fixed tag in prince_prot_region_option_t structure */ +#define PRINCE_TAG 0x50u +#define PRINCE_TAG_SHIFT 24u +/*! @brief Prince region count */ +#define PRINCE_REGION_COUNT 3u +/*! @brief Define for CSS key store indexes */ +#define NXP_DIE_MEM_ENC_SK 2u +#define NXP_DIE_MEM_IV_ENC_SK 4u +/*! @brief KDF mask and key properties for NXP_DIE_MEM_IV_ENC_SK (see SYSCON documentation)*/ +#define SYSCON_CSS_KDF_MASK 0x07000FCF +/*! @brief CFPA version and IV indexes (see Protected Flash Region table) */ +#define CFPA_VER_OFFSET 0x04 +#define CFPA_PRINCE_IV_OFFSET 0x14u +/*! @brief CMPA SR and lock indexes (see Protected Flash Region table) */ +#define CMPA_PRINCE_SR_OFFSET 0x24u +#define CMPA_PRINCE_LOCK_OFFSET 0x20u +/*! @brief CFPA scrach version and IV addresses (see Protected Flash Region table) */ +#define CFPA_SCRATCH_VER 0x3dc04 +#define CFPA_SCRATCH_IV 0x3dc14 +/*! @brief CMPA lock bit-field defines (see Protected Flash Region table) */ +#define PRINCE_BASE_ADDR_LOCK_REG0_SHIFT (16u) +#define PRINCE_BASE_ADDR_LOCK_REG0_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG0_SHIFT) +#define PRINCE_BASE_ADDR_LOCK_REG1_SHIFT (18u) +#define PRINCE_BASE_ADDR_LOCK_REG1_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG1_SHIFT) +#define PRINCE_BASE_ADDR_LOCK_REG2_SHIFT (20u) +#define PRINCE_BASE_ADDR_LOCK_REG2_MASK (0x3u << PRINCE_BASE_ADDR_LOCK_REG2_SHIFT) + +#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + /******************************************************************************* * API ******************************************************************************/ @@ -71,7 +192,7 @@ extern "C" { */ static inline void PRINCE_EncryptEnable(PRINCE_Type *base) { - base->ENC_ENABLE = 1; + base->ENC_ENABLE = 1u; } /*! @@ -83,7 +204,20 @@ static inline void PRINCE_EncryptEnable(PRINCE_Type *base) */ static inline void PRINCE_EncryptDisable(PRINCE_Type *base) { - base->ENC_ENABLE = 0; + base->ENC_ENABLE = 0u; +} + +/*! + * @brief Is Enable data encryption. + * + * This function test if PRINCE on-the-fly data encryption is enabled. + * + * @param base PRINCE peripheral address. + * @return true if enabled, false if not + */ +static inline bool PRINCE_IsEncryptEnable(PRINCE_Type *base) +{ + return (base->ENC_ENABLE == 1u) ? true : false; } /*! @@ -96,8 +230,8 @@ static inline void PRINCE_EncryptDisable(PRINCE_Type *base) */ static inline void PRINCE_SetMask(PRINCE_Type *base, uint64_t mask) { - base->MASK_LSB = mask & 0xffffffffu; - base->MASK_MSB = mask >> 32u; + base->MASK_LSB = (uint32_t)(mask & 0xffffffffu); + base->MASK_MSB = (uint32_t)(mask >> 32u); } /*! @@ -114,29 +248,30 @@ static inline void PRINCE_SetLock(PRINCE_Type *base, uint32_t lock) base->LOCK = lock & 0x1ffu; } +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) /*! * @brief Generate new IV code. * * This function generates new IV code and stores it into the persistent memory. - * This function is implemented as a wrapper of the exported ROM bootloader API. * Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true! * * @param region PRINCE region index. * @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code. * @param store flag to allow storing the newly generated IV code into the persistent memory (FFR). - * param flash_context pointer to the flash driver context structure. + * @param flash_context pointer to the flash driver context structure. * * @return kStatus_Success upon success * @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular * PRINCE region is not present in the keystore (though new IV code has been provided) */ status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context); +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) /*! * @brief Load IV code. * * This function enables IV code loading into the PRINCE bus encryption engine. - * This function is implemented as a wrapper of the exported ROM bootloader API. * * @param region PRINCE region index. * @param iv_code IV code pointer used for passing the IV code. @@ -145,26 +280,36 @@ status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, f * @return kStatus_Fail otherwise */ status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code); +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) /*! * @brief Allow encryption/decryption for specified address range. * * This function sets the encryption/decryption for specified address range. - * This function is implemented as a wrapper of the exported ROM bootloader API. + * The SR mask value for the selected Prince region is calculated from provided + * start_address and length parameters. This calculated value is OR'ed with the + * actual SR mask value and stored into the PRINCE SR_ENABLE register and also + * into the persistent memory (FFR) to be used after the device reset. It is + * possible to define several nonadjacent encrypted areas within one Prince + * region when calling this function repeatedly. If the length parameter is set + * to 0, the SR mask value is set to 0 and thus the encryption/decryption for + * the whole selected Prince region is disabled. * Ensure about 800 bytes free space on the stack when calling this routine! * * @param region PRINCE region index. * @param start_address start address of the area to be encrypted/decrypted. * @param length length of the area to be encrypted/decrypted. - * param flash_context pointer to the flash driver context structure. + * @param flash_context pointer to the flash driver context structure. + * @param regenerate_iv flag to allow IV code regenerating, storing into + * the persistent memory (FFR) and loading into the PRINCE engine * * @return kStatus_Success upon success * @return kStatus_Fail otherwise */ -status_t PRINCE_SetEncryptForAddressRange(prince_region_t region, - uint32_t start_address, - uint32_t length, - flash_config_t *flash_context); +status_t PRINCE_SetEncryptForAddressRange( + prince_region_t region, uint32_t start_address, uint32_t length, flash_config_t *flash_context, bool regenerate_iv); +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ /*! * @brief Gets the PRINCE Sub-Region Enable register. @@ -227,6 +372,145 @@ status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, */ status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable); +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Erases the flash sectors encompassed by parameters passed into function. + * + * This function erases the appropriate number of flash sectors based on the + * desired start address and length. It deals with the flash erase function + * complenentary to the standard erase API of the IAP1 driver. This implementation + * additionally checks if the whole encrypted PRINCE subregions are erased at once + * to avoid secrets revealing. The checker implementation is limited to one contiguous + * PRINCE-controlled memory area. + * + * @param config The pointer to the flash driver context structure. + * @param start The start address of the desired flash memory to be erased. + * The start address needs to be prince-sburegion-aligned. + * @param lengthInBytes The length, given in bytes (not words or long-words) + * to be erased. Must be prince-sburegion-size-aligned. + * @param key The value used to validate all flash erase APIs. + * + * @return #kStatus_FLASH_Success API was executed successfully. + * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @return #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline. + * @return #kStatus_FLASH_AddressError The address is out of range. + * @return #kStatus_FLASH_EraseKeyError The API erase key is invalid. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @return #kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce Encrypted flash subregions are not erased at once. + */ +status_t PRINCE_FlashEraseWithChecker(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key); +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if !defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Programs flash with data at locations passed in through parameters. + * + * This function programs the flash memory with the desired data for a given + * flash area as determined by the start address and the length. It deals with the + * flash program function complenentary to the standard program API of the IAP1 driver. + * This implementation additionally checks if the whole PRINCE subregions are + * programmed at once to avoid secrets revealing. The checker implementation is limited + * to one contiguous PRINCE-controlled memory area. + * + * @param config The pointer to the flash driver context structure. + * @param start The start address of the desired flash memory to be programmed. Must be + * prince-sburegion-aligned. + * @param src A pointer to the source buffer of data that is to be programmed + * into the flash. + * @param lengthInBytes The length, given in bytes (not words or long-words), + * to be programmed. Must be prince-sburegion-size-aligned. + * + * @return #kStatus_FLASH_Success API was executed successfully. + * @return #kStatus_FLASH_InvalidArgument An invalid argument is provided. + * @return #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline. + * @return #kStatus_FLASH_AddressError Address is out of range. + * @return #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandFailure Run-time error during the command execution. + * @return #kStatus_FLASH_CommandNotSupported Flash API is not supported. + * @return #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution. + * @return #kStatus_FLASH_SizeError Encrypted flash subregions are not programmed at once. + */ +status_t PRINCE_FlashProgramWithChecker(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes); +#endif /* !defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Configures PRINCE setting. + * + * This function does the initial PRINCE configuration via ROM IAP API call. + * PRINCE_SR_x configuration for each region configuration is stored into FFR (CMPA). + * PRINCE IV erase counters (MCTR_INT_IV_CTRx) in CFPA are updated accordingly. + * + * Note: This function is expected to be called once in the device lifetime, + * typically during the initial device provisioning, since it is programming the CMPA pages in PFR flash. + * + * @param coreCtx The pointer to the ROM API driver context structure. + * @param config The pointer to the PRINCE driver configuration structure. + * + * @retval #kStatus_Success + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_InvalidArgument + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_Fail + * @retval #kStatus_OutOfRange + * @retval #kStatus_SPI_BaudrateNotSupport + */ +status_t PRINCE_Configure(api_core_context_t *coreCtx, prince_prot_region_arg_t *config); +#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Reconfigures PRINCE setting. + * + * This function is used to re-configure PRINCE IP based on configuration stored in FFR. + * This function also needs to be called after wake up from power-down mode to regenerate IV + * encryption key in CSS key store whose presence is necessary for correct PRINCE operation + * during erase and write operations to encrypted regions of internal flash memory + * (dependency for correct operation of MEM_Erase() and MEM_Write() after wake up from power-down mode). + * + * @param coreCtx The pointer to the ROM API driver context structure. + * + * @retval #kStatus_Success + * @retval #kStatus_CommandUnsupported + * @retval #kStatus_InvalidArgument + * @retval #kStatus_FLASH_ModifyProtectedAreaDisallowed + * @retval #kStatusMemoryRangeInvalid + * @retval #kStatus_Fail + * @retval #kStatus_OutOfRange + * @retval #kStatus_SPI_BaudrateNotSupport + */ +status_t PRINCE_Reconfigure(api_core_context_t *coreCtx); +#endif /* defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + +#if (defined(FSL_PRINCE_DRIVER_LPC55S0x)) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || defined(FSL_PRINCE_DRIVER_LPC55S3x) +/*! + * @brief Gets the PRINCE Error status register. + * + * @param base PRINCE peripheral address. + * + * @return PRINCE Error status register + */ +static inline uint32_t PRINCE_GetErrorStatus(PRINCE_Type *base) +{ + return base->ERR; +} + +/*! + * @brief Clears the PRINCE Error status register. + * + * @param base PRINCE peripheral address. + */ +static inline void PRINCE_ClearErrorStatus(PRINCE_Type *base) +{ + base->ERR = 0U; +} +#endif /* defined(FSL_PRINCE_DRIVER_LPC55S0x) || defined(FSL_PRINCE_DRIVER_LPC55S1x) || \ + defined(FSL_PRINCE_DRIVER_LPC55S3x) */ + #if defined(__cplusplus) } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.c index 805c98d456..d82299ed24 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * All rights reserved. * * @@ -8,44 +8,68 @@ #include "fsl_puf.h" #include "fsl_clock.h" -#include "fsl_reset.h" #include "fsl_common.h" + +#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) +#include "fsl_reset.h" +#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ + /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.puf" #endif +/* RT6xx POWER CONTROL bit masks */ +#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) +#define PUF_PWRCTRL_CKDIS_MASK (0x4U) +#define PUF_PWRCTRL_RAMINIT_MASK (0x8U) +#define PUF_PWRCTRL_RAMPSWLARGEMA_MASK (0x10U) +#define PUF_PWRCTRL_RAMPSWLARGEMP_MASK (0x20U) +#define PUF_PWRCTRL_RAMPSWSMALLMA_MASK (0x40U) +#define PUF_PWRCTRL_RAMPSWSMALLMP_MASK (0x80U) +#endif + +#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) +#define DEFAULT_CKGATING 0x0u +#define PUF_ENABLE_MASK 0xFFFFFFFEu +#define PUF_ENABLE_CTRL 0x1u + +#else static void puf_wait_usec(volatile uint32_t usec, uint32_t coreClockFrequencyMHz) { - while (usec > 0) - { - usec--; + SDK_DelayAtLeastUs(usec, coreClockFrequencyMHz * 1000000U); - /* number of MHz is directly number of core clocks to wait 1 usec. */ - /* the while loop below is actually 4 clocks so divide by 4 for ~1 usec */ - register uint32_t ticksCount = coreClockFrequencyMHz / 4u + 1u; - while (ticksCount--) - { - } - } + /* Instead of calling SDK_DelayAtLeastUs() implement delay loop here */ + // while (usec > 0U) + // { + // usec--; + + // number of MHz is directly number of core clocks to wait 1 usec. + // the while loop below is actually 4 clocks so divide by 4 for ~1 usec + // volatile uint32_t ticksCount = coreClockFrequencyMHz / 4u + 1u; + // while (0U != ticksCount--) + // { + // } + // } } +#endif /* defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) */ static status_t puf_waitForInit(PUF_Type *base) { status_t status = kStatus_Fail; /* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */ - while (0 == base->STAT) + while (0U == base->STAT) { } /* wait if busy */ - while ((base->STAT & PUF_STAT_BUSY_MASK) != 0) + while ((base->STAT & PUF_STAT_BUSY_MASK) != 0U) { } /* return status */ - if (base->STAT & (PUF_STAT_SUCCESS_MASK | PUF_STAT_ERROR_MASK)) + if (0U != (base->STAT & (PUF_STAT_SUCCESS_MASK | PUF_STAT_ERROR_MASK))) { status = kStatus_Success; } @@ -53,103 +77,163 @@ static status_t puf_waitForInit(PUF_Type *base) return status; } -static void puf_powerOn(PUF_Type *base) +static void puf_powerOn(PUF_Type *base, puf_config_t *conf) { #if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) /* RT6xxs */ - base->PWRCTRL = 0x5u; - base->PWRCTRL = 0xDu; - base->PWRCTRL = 0x9u; + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); +#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* LPCXpresso55s16 */ + conf->puf_sram_base->CFG |= PUF_ENABLE_CTRL; + while (0U == (PUF_SRAM_CTRL_STATUS_READY_MASK & conf->puf_sram_base->STATUS)) + { + } #else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* Niobe4 & Aruba FL */ + /* LPCXpresso55s69 & LPCXpresso54S018 */ base->PWRCTRL = PUF_PWRCTRL_RAMON_MASK; - while (0 == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) + while (0U == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) { } #endif /* FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ } - -static status_t puf_powerCycle(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz) +/*! + * brief Powercycle PUF + * + * This function make powercycle of PUF. + * + * param base PUF peripheral base address + * param conf PUF configuration structure + * return Status of the powercycle operation. + */ +status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf) { #if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) /* RT6xxs */ - uint32_t coreClockFrequencyMHz = coreClockFrequencyHz / 1000000u; + uint32_t coreClockFrequencyMHz = conf->coreClockFrequencyHz / 1000000u; - base->PWRCTRL = 0xDu; /* disable RAM CK */ + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ /* enter ASPS mode */ - base->PWRCTRL = 0xCu; /* SLEEP = 1 */ - base->PWRCTRL = 0x8u; /* enable RAM CK */ - base->PWRCTRL = 0xF8u; /* SLEEP=1, PSW*=1 */ + base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ + base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK); /* enable RAM CK */ + base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | + PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ /* Wait enough time to discharge fully */ - puf_wait_usec(dischargeTimeMsec * 1000u, coreClockFrequencyHz / 1000000u); + puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); /* write PWRCTRL=0x38. wait time > 1 us */ - base->PWRCTRL = 0x38u; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=1. */ + base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | + PUF_PWRCTRL_RAMPSWLARGEMP_MASK); /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=1. */ puf_wait_usec(1, coreClockFrequencyMHz); /* write PWRCTRL=0x8. wait time > 1 us */ - base->PWRCTRL = 0x08u; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=0 */ + base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=0 */ puf_wait_usec(1, coreClockFrequencyMHz); - base->PWRCTRL = 0xCu; - base->PWRCTRL = 0xDu; - base->PWRCTRL = 0x9u; + base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* Generate INITN low pulse */ - base->PWRCTRL = 0xDu; - base->PWRCTRL = 0x5u; - base->PWRCTRL = 0x1u; + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK); + base->PWRCTRL = PUF_PWRCTRL_RAM_ON_MASK; +#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* LPCXpresso55s16 */ + conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; #else - /* Niobe4 & Aruba FL */ + /* LPCXpresso55s69 & LPCXpresso54S018 */ base->PWRCTRL = 0x0u; - while (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL) + while (0U != (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)) { } /* Wait enough time to discharge fully */ - puf_wait_usec(dischargeTimeMsec * 1000u, coreClockFrequencyHz / 1000000u); + puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); #endif +#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) /* Reset PUF and reenable power to PUF SRAM */ RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); - puf_powerOn(base); +#endif /* FSL_TEATURE_PUF_HAS_NO_RESET */ + puf_powerOn(base, conf); return kStatus_Success; } +/*! + * brief Sets the default configuration of PUF + * + * This function initialize PUF config structure to default values. + * + * param conf PUF configuration structure + */ +void PUF_GetDefaultConfig(puf_config_t *conf) +{ +#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* LPCXpresso55s16 */ + conf->puf_sram_base = PUF_SRAM_CTRL; + + /* Default configuration after reset */ + conf->CKGATING = DEFAULT_CKGATING; /* PUF SRAM Clock Gating */ +#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ + + conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; + conf->coreClockFrequencyHz = CLOCK_GetFreq(kCLOCK_CoreSysClk); + + return; +} + /*! * brief Initialize PUF * * This function enables power to PUF block and waits until the block initializes. * * param base PUF peripheral base address - * param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge - * param coreClockFrequencyHz core clock frequency in Hz + * param conf PUF configuration structure * return Status of the init operation */ -status_t PUF_Init(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz) +status_t PUF_Init(PUF_Type *base, puf_config_t *conf) { status_t status = kStatus_Fail; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_EnableClock(kCLOCK_Puf); #endif +#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) /* Reset PUF */ RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn); +#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ + +#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* Set configuration for SRAM */ + conf->puf_sram_base->CFG |= PUF_SRAM_CTRL_CFG_CKGATING(conf->CKGATING); + +#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ /* Enable power to PUF SRAM */ - puf_powerOn(base); + puf_powerOn(base, conf); /* Wait for peripheral to become ready */ status = puf_waitForInit(base); - /* In case of error or enroll & start not allowed, do power-cycle */ - if ((status != kStatus_Success) || ((PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK) != - (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) + /* In case of error or enroll or start not allowed, do power-cycle */ + /* First try with shorter discharge time, if then it also fails try with longer time */ + /* conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS; */ + if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) { - puf_powerCycle(base, dischargeTimeMsec, coreClockFrequencyHz); + (void)PUF_PowerCycle(base, conf); + status = puf_waitForInit(base); + } + + /* In case of error or enroll or start not allowed, do power-cycle with worst discharge timing */ + if ((status != kStatus_Success) || (0U == (base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK)))) + { + conf->dischargeTimeMsec = KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS; + (void)PUF_PowerCycle(base, conf); status = puf_waitForInit(base); } @@ -162,26 +246,33 @@ status_t PUF_Init(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClock * This function disables power to PUF SRAM and peripheral clock. * * param base PUF peripheral base address + * param conf PUF configuration structure */ -void PUF_Deinit(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz) +void PUF_Deinit(PUF_Type *base, puf_config_t *conf) { #if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0) /* RT6xxs */ - base->PWRCTRL = 0xDu; /* disable RAM CK */ + base->PWRCTRL = (PUF_PWRCTRL_RAM_ON_MASK | PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* disable RAM CK */ /* enter ASPS mode */ - base->PWRCTRL = 0xCu; /* SLEEP = 1 */ - base->PWRCTRL = 0x8u; /* enable RAM CK */ - base->PWRCTRL = 0xF8u; /* SLEEP=1, PSW*=1 */ -#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ - /* Niobe4 & Aruba FL */ + base->PWRCTRL = (PUF_PWRCTRL_CK_DIS_MASK | PUF_PWRCTRL_RAMINIT_MASK); /* SLEEP = 1 */ + base->PWRCTRL = PUF_PWRCTRL_RAMINIT_MASK; /* enable RAM CK */ + base->PWRCTRL = (PUF_PWRCTRL_RAMINIT_MASK | PUF_PWRCTRL_RAMPSWLARGEMA_MASK | PUF_PWRCTRL_RAMPSWLARGEMP_MASK | + PUF_PWRCTRL_RAMPSWSMALLMA_MASK | PUF_PWRCTRL_RAMPSWSMALLMP_MASK); /* SLEEP=1, PSW*=1 */ + puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); +#elif defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* LPCXpresso55s16 */ + conf->puf_sram_base = PUF_SRAM_CTRL; + conf->puf_sram_base->CFG &= PUF_ENABLE_MASK; +#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */ + /* LPCXpresso55s69 & LPCXpresso54S018 */ base->PWRCTRL = 0x00u; + puf_wait_usec(conf->dischargeTimeMsec * 1000u, conf->coreClockFrequencyHz / 1000000u); #endif - /* Wait enough time to discharge fully */ - puf_wait_usec(dischargeTimeMsec * 1000u, coreClockFrequencyHz / 1000000u); - +#if !(defined(FSL_FEATURE_PUF_HAS_NO_RESET) && (FSL_FEATURE_PUF_HAS_NO_RESET > 0)) RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn); +#endif /* FSL_FEATURE_PUF_HAS_NO_RESET */ #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_DisableClock(kCLOCK_Puf); @@ -213,7 +304,7 @@ status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCo } /* only work with aligned activationCode */ - if (0x3u & (uintptr_t)activationCode) + if (0U != (0x3u & (uintptr_t)activationCode)) { return kStatus_InvalidArgument; } @@ -223,21 +314,21 @@ status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCo /* check if ENROLL is allowed */ if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWENROLL_MASK)) { - return kStatus_Fail; + return kStatus_EnrollNotAllowed; } /* begin */ base->CTRL = PUF_CTRL_ENROLL_MASK; /* check status */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) { } /* read out AC */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) { - if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) + if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) { temp32 = base->CODEOUTPUT; if (activationCodeSize >= sizeof(uint32_t)) @@ -249,7 +340,7 @@ status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCo } } - if ((base->STAT & PUF_STAT_SUCCESS_MASK) && (activationCodeSize == 0)) + if (((base->STAT & PUF_STAT_SUCCESS_MASK) != 0U) && (activationCodeSize == 0U)) { status = kStatus_Success; } @@ -276,13 +367,13 @@ status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activat register uint32_t temp32 = 0; /* check that activation code size is at least 1192 bytes */ - if (activationCodeSize < 1192) + if (activationCodeSize < 1192U) { return kStatus_InvalidArgument; } /* only work with aligned activationCode */ - if (0x3u & (uintptr_t)activationCode) + if (0U != (0x3u & (uintptr_t)activationCode)) { return kStatus_InvalidArgument; } @@ -292,21 +383,21 @@ status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activat /* check if START is allowed */ if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSTART_MASK)) { - return kStatus_Fail; + return kStatus_StartNotAllowed; } /* begin */ base->CTRL = PUF_CTRL_START_MASK; /* check status */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) { } /* while busy send AC */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) { - if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT)) + if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) { if (activationCodeSize >= sizeof(uint32_t)) { @@ -319,7 +410,7 @@ status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activat } /* get status */ - if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) + if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) { status = kStatus_Success; } @@ -358,13 +449,13 @@ status_t PUF_SetIntrinsicKey( } /* only work with aligned keyCode */ - if (0x3u & (uintptr_t)keyCode) + if (0U != (0x3u & (uintptr_t)keyCode)) { return kStatus_InvalidArgument; } /* Check that keySize is in the correct range and that it is multiple of 8 */ - if ((keySize < kPUF_KeySizeMin) || (keySize > kPUF_KeySizeMax) || (keySize & 0x7)) + if ((keySize < (uint32_t)kPUF_KeySizeMin) || (keySize > (uint32_t)kPUF_KeySizeMax) || (0U != (keySize & 0x7U))) { return kStatus_InvalidArgument; } @@ -375,7 +466,7 @@ status_t PUF_SetIntrinsicKey( return kStatus_InvalidArgument; } - if ((uint32_t)keyIndex > kPUF_KeyIndexMax) + if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) { return kStatus_InvalidArgument; } @@ -390,14 +481,14 @@ status_t PUF_SetIntrinsicKey( base->CTRL = PUF_CTRL_GENERATEKEY_MASK; /* wait till command is accepted */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) { } /* while busy read KC */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) { - if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) + if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) { temp32 = base->CODEOUTPUT; if (keyCodeSize >= sizeof(uint32_t)) @@ -410,7 +501,7 @@ status_t PUF_SetIntrinsicKey( } /* get status */ - if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) + if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) { status = kStatus_Success; } @@ -453,13 +544,14 @@ status_t PUF_SetUserKey(PUF_Type *base, } /* only work with aligned keyCode */ - if (0x3u & (uintptr_t)keyCode) + if (0U != (0x3u & (uintptr_t)keyCode)) { return kStatus_InvalidArgument; } /* Check that userKeySize is in the correct range and that it is multiple of 8 */ - if ((userKeySize < kPUF_KeySizeMin) || (userKeySize > kPUF_KeySizeMax) || (userKeySize & 0x7)) + if ((userKeySize < (uint32_t)kPUF_KeySizeMin) || (userKeySize > (uint32_t)kPUF_KeySizeMax) || + (0U != (userKeySize & 0x7U))) { return kStatus_InvalidArgument; } @@ -470,7 +562,7 @@ status_t PUF_SetUserKey(PUF_Type *base, return kStatus_InvalidArgument; } - if ((uint32_t)keyIndex > kPUF_KeyIndexMax) + if ((uint32_t)keyIndex > (uint32_t)kPUF_KeyIndexMax) { return kStatus_InvalidArgument; } @@ -482,29 +574,57 @@ status_t PUF_SetUserKey(PUF_Type *base, base->KEYSIZE = userKeySize >> 3; /* convert to 64-bit blocks */ base->KEYINDEX = (uint32_t)keyIndex; + /* We have to store the user key on index 0 swaped for HW bus */ + if (keyIndex == kPUF_KeyIndex_00) + { + userKeyAligned = userKeyAligned + (userKeySize / sizeof(uint32_t)); + } + /* begin */ base->CTRL = PUF_CTRL_SETKEY_MASK; /* wait till command is accepted */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) { } /* while busy write UK and read KC */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) { - if (0 != (PUF_STAT_KEYINREQ_MASK & base->STAT)) + if (0U != (PUF_STAT_KEYINREQ_MASK & base->STAT)) { if (userKeySize >= sizeof(uint32_t)) { - temp32 = *userKeyAligned; - userKeyAligned++; - userKeySize -= sizeof(uint32_t); +#if defined(LPC54S018_SERIES) + if (keyIndex == kPUF_KeyIndex_00) + { + userKeyAligned--; + temp32 = *userKeyAligned; + userKeySize -= sizeof(uint32_t); + } +#else + if (keyIndex == kPUF_KeyIndex_00) + { + userKeyAligned--; + temp32 = __REV(*userKeyAligned); + userKeySize--; + } +#endif /* defined(LPC54S018_SERIES) */ + else if (keyIndex != kPUF_KeyIndex_00) + { + temp32 = *userKeyAligned; + userKeyAligned++; + userKeySize -= sizeof(uint32_t); + } + else + { + /* Intentional empty */ + } } base->KEYINPUT = temp32; } - if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) + if (0U != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT)) { temp32 = base->CODEOUTPUT; if (keyCodeSize >= sizeof(uint32_t)) @@ -517,7 +637,7 @@ status_t PUF_SetUserKey(PUF_Type *base, } /* get status */ - if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) + if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) { status = kStatus_Success; } @@ -537,14 +657,14 @@ static status_t puf_getHwKey(PUF_Type *base, const uint8_t *keyCode, size_t keyC base->CTRL = PUF_CTRL_GETKEY_MASK; /* wait till command is accepted */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) { } /* while busy send KC, key is reconstructed to HW bus */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) { - if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT)) + if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) { if (keyCodeSize >= sizeof(uint32_t)) { @@ -557,7 +677,7 @@ static status_t puf_getHwKey(PUF_Type *base, const uint8_t *keyCode, size_t keyC } /* get status */ - if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)) + if (0U != (base->STAT & PUF_STAT_SUCCESS_MASK)) { status = kStatus_Success; } @@ -595,7 +715,7 @@ status_t PUF_GetHwKey( } /* only work with aligned keyCode */ - if (0x3u & (uintptr_t)keyCode) + if (0U != (0x3u & (uintptr_t)keyCode)) { return kStatus_Fail; } @@ -606,7 +726,7 @@ status_t PUF_GetHwKey( return kStatus_InvalidArgument; } - keyIndex = 0x0Fu & keyCode[1]; + keyIndex = (uint32_t)(0x0Fu & (uint32_t)keyCode[1]); /* check the Key Code header byte 1. index must be zero for the hw key. */ if (kPUF_KeyIndex_00 != (puf_key_index_register_t)keyIndex) @@ -614,9 +734,9 @@ status_t PUF_GetHwKey( return kStatus_Fail; } -#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 0) +#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) volatile uint32_t *keyMask_reg = NULL; - uint32_t regVal = (2 << (2 * keySlot)); + uint32_t regVal = ((uint32_t)2U << ((uint32_t)2U * (uint32_t)keySlot)); switch (keySlot) { @@ -627,7 +747,7 @@ status_t PUF_GetHwKey( case kPUF_KeySlot1: keyMask_reg = &base->KEYMASK[1]; break; -#if (FSL_FEATURE_PUF_HAS_KEYSLOTS > 2) +#if (PUF_KEYMASK_COUNT > 2) case kPUF_KeySlot2: keyMask_reg = &base->KEYMASK[2]; break; @@ -635,16 +755,16 @@ status_t PUF_GetHwKey( case kPUF_KeySlot3: keyMask_reg = &base->KEYMASK[3]; break; -#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS > 2 */ +#endif /* PUF_KEYMASK_COUNT > 2 */ default: status = kStatus_InvalidArgument; break; } -#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */ +#endif /* PUF_KEYMASK_COUNT */ if (status != kStatus_InvalidArgument) { -#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 0) +#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 0) base->KEYRESET = regVal; base->KEYENABLE = regVal; *keyMask_reg = keyMask; @@ -658,13 +778,25 @@ status_t PUF_GetHwKey( if (status == kStatus_Success) { /* if the corresponding shift count does not match, return fail anyway */ - keyWords = ((((size_t)keyCode[3]) * 2) - 1u) << (keySlot << 2); - if (keyWords != ((0x0Fu << (keySlot << 2)) & base->SHIFT_STATUS)) + keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); + if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->SHIFT_STATUS)) { status = kStatus_Fail; } } -#endif /* FSL_FEATURE_PUF_HAS_SHIFT_STATUS */ +#elif defined(PUF_IDXBLK_SHIFT_IND_KEY0_MASK) && PUF_IDXBLK_SHIFT_IND_KEY0_MASK + size_t keyWords = 0; + + if (status == kStatus_Success) + { + /* if the corresponding shift count does not match, return fail anyway */ + keyWords = ((((size_t)keyCode[3]) * 2U) - 1u) << ((size_t)keySlot << 2U); + if (keyWords != ((0x0FUL << ((uint32_t)keySlot << 2U)) & base->IDXBLK_SHIFT)) + { + status = kStatus_Fail; + } + } +#endif /* FSL_FEATURE_PUF_HAS_SHIFT_STATUS || PUF_IDXBLK_SHIFT_IND_KEY0_MASK */ } return status; @@ -719,13 +851,13 @@ status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, } /* only work with aligned keyCode */ - if (0x3u & (uintptr_t)keyCode) + if (0U != (0x3u & (uintptr_t)keyCode)) { return kStatus_Fail; } /* only work with aligned key */ - if (0x3u & (uintptr_t)key) + if (0U != (0x3u & (uintptr_t)key)) { return kStatus_Fail; } @@ -736,7 +868,7 @@ status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, return kStatus_InvalidArgument; } - keyIndex = 0x0Fu & keyCode[1]; + keyIndex = (0x0Fu & (uint32_t)keyCode[1]); /* check the Key Code header byte 1. index must be non-zero for the register key. */ if (kPUF_KeyIndex_00 == (puf_key_index_register_t)keyIndex) @@ -751,14 +883,14 @@ status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, base->CTRL = PUF_CTRL_GETKEY_MASK; /* wait till command is accepted */ - while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) + while (0U == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK))) { } /* while busy send KC, read key */ - while (0 != (base->STAT & PUF_STAT_BUSY_MASK)) + while (0U != (base->STAT & PUF_STAT_BUSY_MASK)) { - if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT)) + if (0U != (PUF_STAT_CODEINREQ_MASK & base->STAT)) { temp32 = 0; if (keyCodeSize >= sizeof(uint32_t)) @@ -770,7 +902,7 @@ status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, base->CODEINPUT = temp32; } - if (0 != (PUF_STAT_KEYOUTAVAIL_MASK & base->STAT)) + if (0U != (PUF_STAT_KEYOUTAVAIL_MASK & base->STAT)) { keyIndex = base->KEYOUTINDEX; temp32 = base->KEYOUTPUT; @@ -784,7 +916,7 @@ status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, } /* get status */ - if ((keyIndex) && (0 != (base->STAT & PUF_STAT_SUCCESS_MASK))) + if ((keyIndex != 0U) && (0U != (base->STAT & PUF_STAT_SUCCESS_MASK))) { status = kStatus_Success; } @@ -808,7 +940,7 @@ status_t PUF_Zeroize(PUF_Type *base) base->CTRL = PUF_CTRL_ZEROIZE_MASK; /* check that command is accepted */ - if ((0 != (base->STAT & PUF_STAT_ERROR_MASK)) && (0 == base->ALLOW)) + if ((0U != (base->STAT & PUF_STAT_ERROR_MASK)) && (0U == base->ALLOW)) { status = kStatus_Success; } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.h index abc00ffaf6..b8a5c51c85 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_puf.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * All rights reserved. * * @@ -14,6 +14,52 @@ #include "fsl_common.h" +/******************************************************************************* + * Definitions + *******************************************************************************/ + +/*! + * @addtogroup puf_driver + * @{ + */ +/*! @name Driver version */ +/*@{*/ +/*! @brief PUF driver version. Version 2.1.6. + * + * Current version: 2.1.6 + * + * Change log: + * - 2.0.0 + * - Initial version. + * - 2.0.1 + * - Fixed puf_wait_usec function optimization issue. + * - 2.0.2 + * - Add PUF configuration structure and support for PUF SRAM controller. + * Remove magic constants. + * - 2.0.3 + * - Fix MISRA C-2012 issue. + * - 2.1.0 + * - Align driver with PUF SRAM controller registers on LPCXpresso55s16. + * - Update initizalition logic . + * - 2.1.1 + * - Fix ARMGCC build warning . + * - 2.1.2 + * - Update: Add automatic big to little endian swap for user + * (pre-shared) keys destinated to secret hardware bus (PUF key index 0). + * - 2.1.3 + * - Fix MISRA C-2012 issue. + * - 2.1.4 + * - Replace register uint32_t ticksCount with volatile uint32_t ticksCount in puf_wait_usec() to prevent optimization + * out delay loop. + * - 2.1.5 + * - Use common SDK delay in puf_wait_usec() + * - 2.1.6 + * - Changed wait time in PUF_Init(), when initialization fails it will try PUF_Powercycle() with shorter time. If + * this shorter time will also fail, initialization will be tried with worst case time as before. + */ +#define FSL_PUF_DRIVER_VERSION (MAKE_VERSION(2, 1, 6)) +/*@}*/ + typedef enum _puf_key_index_register { kPUF_KeyIndex_00 = 0x00U, @@ -41,20 +87,42 @@ typedef enum _puf_min_max kPUF_KeyIndexMax = kPUF_KeyIndex_15, } puf_min_max_t; +/*! @brief PUF key slot. */ typedef enum _puf_key_slot { kPUF_KeySlot0 = 0U, /*!< PUF key slot 0 */ kPUF_KeySlot1 = 1U, /*!< PUF key slot 1 */ -#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 2) +#if defined(PUF_KEYMASK_COUNT) && (PUF_KEYMASK_COUNT > 2) kPUF_KeySlot2 = 2U, /*!< PUF key slot 2 */ kPUF_KeySlot3 = 3U, /*!< PUF key slot 3 */ #endif } puf_key_slot_t; +typedef struct +{ + uint32_t dischargeTimeMsec; + uint32_t coreClockFrequencyHz; +#if defined(FSL_FEATURE_PUF_HAS_SRAM_CTRL) && (FSL_FEATURE_PUF_HAS_SRAM_CTRL > 0) + /* LPCXpresso55s16 */ + PUF_SRAM_CTRL_Type *puf_sram_base; + uint8_t CKGATING; +#endif /* FSL_FEATURE_PUF_HAS_SRAM_CTRL */ +} puf_config_t; /*! @brief Get Key Code size in bytes from key size in bytes at compile time. */ -#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((160u + ((((x << 3) + 255u) >> 8) << 8)) >> 3) -#define PUF_MIN_KEY_CODE_SIZE PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(8) -#define PUF_ACTIVATION_CODE_SIZE 1192 +#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((160u + (((((x) << 3) + 255u) >> 8) << 8)) >> 3) +#define PUF_MIN_KEY_CODE_SIZE PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(8UL) +#define PUF_ACTIVATION_CODE_SIZE 1192U +#define KEYSTORE_PUF_DISCHARGE_TIME_FIRST_TRY_MS 50 +#define KEYSTORE_PUF_DISCHARGE_TIME_MAX_MS 400 + +/*! PUF status return codes. */ +enum +{ + kStatus_EnrollNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 1), + kStatus_StartNotAllowed = MAKE_STATUS(kStatusGroup_PUF, 2) +}; + +/*! @} */ /******************************************************************************* * API *******************************************************************************/ @@ -63,17 +131,25 @@ typedef enum _puf_key_slot extern "C" { #endif /* __cplusplus */ +/*! + * @brief Sets the default configuration of PUF + * + * This function initialize PUF config structure to default values. + * + * @param conf PUF configuration structure + */ +void PUF_GetDefaultConfig(puf_config_t *conf); + /*! * @brief Initialize PUF * * This function enables power to PUF block and waits until the block initializes. * * @param base PUF peripheral base address - * @param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge - * @param coreClockFrequencyHz core clock frequency in Hz + * @param conf PUF configuration structure * @return Status of the init operation */ -status_t PUF_Init(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz); +status_t PUF_Init(PUF_Type *base, puf_config_t *conf); /*! * @brief Denitialize PUF @@ -81,10 +157,9 @@ status_t PUF_Init(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClock * This function disables power to PUF SRAM and peripheral clock. * * @param base PUF peripheral base address - * @param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge - * @param coreClockFrequencyHz core clock frequency in Hz + * @param conf PUF configuration structure */ -void PUF_Deinit(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz); +void PUF_Deinit(PUF_Type *base, puf_config_t *conf); /*! * @brief Enroll PUF @@ -214,15 +289,44 @@ status_t PUF_Zeroize(PUF_Type *base); */ bool PUF_IsGetKeyAllowed(PUF_Type *base); +#if defined(PUF_CFG_BLOCKKEYOUTPUT_MASK) && PUF_CFG_BLOCKKEYOUTPUT_MASK static inline void PUF_BlockSetKey(PUF_Type *base) { base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */ } +#endif /* PUF_CFG_BLOCKKEYOUTPUT_MASK */ +#if defined(PUF_CFG_PUF_BLOCK_SET_KEY_MASK) && PUF_CFG_PUF_BLOCK_SET_KEY_MASK +static inline void PUF_BlockSetKey(PUF_Type *base) +{ + base->CFG |= PUF_CFG_PUF_BLOCK_SET_KEY_MASK; /* block set key */ +} +#endif /* PUF_CFG_PUF_BLOCK_SET_KEY_MASK */ + +#if defined(PUF_CFG_BLOCKENROLL_SETKEY_MASK) && PUF_CFG_BLOCKENROLL_SETKEY_MASK static inline void PUF_BlockEnroll(PUF_Type *base) { base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */ } +#endif /* PUF_CFG_BLOCKENROLL_SETKEY_MASK */ + +#if defined(PUF_CFG_PUF_BLOCK_ENROLL_MASK) && PUF_CFG_PUF_BLOCK_ENROLL_MASK +static inline void PUF_BlockEnroll(PUF_Type *base) +{ + base->CFG |= PUF_CFG_PUF_BLOCK_ENROLL_MASK; /* block enroll */ +} +#endif /* PUF_CFG_PUF_BLOCK_ENROLL_MASK */ + +/*! + * @brief Powercycle PUF + * + * This function make powercycle. + * + * @param base PUF peripheral base address + * @param conf PUF configuration structure + * @return Status of the powercycle operation. + */ +status_t PUF_PowerCycle(PUF_Type *base, puf_config_t *conf); #if defined(__cplusplus) } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.c index 84857298fa..4326e0dae2 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.c @@ -42,8 +42,8 @@ void RESET_SetPeripheralReset(reset_ip_name_t peripheral) { const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1u << bitPos; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; assert(bitPos < 32u); @@ -67,8 +67,8 @@ void RESET_SetPeripheralReset(reset_ip_name_t peripheral) void RESET_ClearPeripheralReset(reset_ip_name_t peripheral) { const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16; - const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); - const uint32_t bitMask = 1u << bitPos; + const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu); + const uint32_t bitMask = 1UL << bitPos; assert(bitPos < 32u); diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.h index 1e92823ff6..314f6c66a3 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_reset.h @@ -16,7 +16,7 @@ #include "fsl_device_registers.h" /*! - * @addtogroup ksdk_common + * @addtogroup reset * @{ */ @@ -26,8 +26,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief reset driver version 2.0.0. */ -#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*! @brief reset driver version 2.0.3. */ +#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*@}*/ /*! @@ -37,78 +37,78 @@ */ typedef enum _SYSCON_RSTn { - kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ - kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ - kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ - kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ - kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ - kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ - kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ - kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ - kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ - kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ - kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ - kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ - kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ - kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ - kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ - kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ - kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ - kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ - kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ - kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ + kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */ + kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */ + kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */ + kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */ + kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */ + kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */ + kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */ + kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */ + kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */ + kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */ + kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */ + kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */ + kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */ + kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */ + kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */ + kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */ + kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */ + kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */ + kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */ + kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */ kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */ - kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ + kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */ - kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ - kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ - kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ - kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ - kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ - kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ - kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ - kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ - kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ - kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ - kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ - kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ - kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ - kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ - kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ - kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ - kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ - kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ - kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ - kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ + kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */ + kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */ + kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */ + kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */ + kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */ + kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */ + kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */ + kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */ + kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */ + kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */ + kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */ + kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */ + kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */ + kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */ + kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */ + kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */ + kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */ + kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */ + kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */ + kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */ - kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ - kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ - kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ - kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ - kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ - kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ - kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ - kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ - kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ - kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ - kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ - kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ - kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ - kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ - kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ - kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ - kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ - kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ - kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ - kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ - kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ - kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ - kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ - kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ - kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ - kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ - kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ - kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ + kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */ + kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */ + kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */ + kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */ + kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */ + kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */ + kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */ + kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */ + kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */ + kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */ + kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */ + kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */ + kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */ + kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */ + kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */ + kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */ + kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */ + kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */ + kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */ + kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */ + kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */ + kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */ + kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */ + kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */ + kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */ + kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */ + kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */ + kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */ kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */ } SYSCON_RSTn_t; @@ -230,9 +230,25 @@ typedef enum _SYSCON_RSTn kPLULUT_RST_SHIFT_RSTn \ } /* Reset bits for PLU peripheral */ #define OSTIMER_RSTS \ - { \ + { \ kOSTIMER0_RST_SHIFT_RSTn \ } /* Reset bits for OSTIMER peripheral */ +#define POWERQUAD_RSTS \ + { \ + kPOWERQUAD_RST_SHIFT_RSTn \ + } /* Reset bits for Powerquad peripheral */ +#define CASPER_RSTS \ + { \ + kCASPER_RST_SHIFT_RSTn \ + } /* Reset bits for Casper peripheral */ +#define HASHCRYPT_RSTS \ + { \ + kHASHCRYPT_RST_SHIFT_RSTn \ + } /* Reset bits for Hashcrypt peripheral */ +#define PUF_RSTS \ + { \ + kPUF_RST_SHIFT_RSTn \ + } /* Reset bits for PUF peripheral */ typedef SYSCON_RSTn_t reset_ip_name_t; /******************************************************************************* diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.c index 5da5be4104..1b2e9d4d61 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.c @@ -1,5 +1,5 @@ /* - * Copyright 2017 NXP + * Copyright 2017, 2019, 2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,24 +23,140 @@ /******************************************************************************* * Code ******************************************************************************/ +static void rng_accumulateEntropy(RNG_Type *base) +{ + uint32_t minChiSq; + uint32_t maxChiSq; + + /* Steps to accumulate entropy, more info can be found in LPC55SXX UM*/ + + /* Select fourth clock on which to compute CHI SQUARE statistics*/ + base->COUNTER_CFG = (base->COUNTER_CFG & ~RNG_COUNTER_CFG_CLOCK_SEL_MASK) | RNG_COUNTER_CFG_CLOCK_SEL(4U); + + /* Activate CHI computing */ + base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1U); + + /* Read min chi squared value, on power on should be higher than max chi squared value */ + minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); + + /* Read max chi squared value */ + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + + /* Wait until minChiSq decreases and become smaller than maxChiSq*/ + while (minChiSq > (maxChiSq - 1U)) + { + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + minChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MIN_CHI_SQUARED_SHIFT); + } +} + +/*! + * @brief Gets a entry data from the RNG. + * + * This function gets an entropy data from RNG. + */ +static uint32_t rng_readEntropy(RNG_Type *base) +{ + uint32_t data; + uint32_t refreshCnt, maxChiSq, tmpShift4x; + + /* Activate CHI computing */ + base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(1); + + /* Wait for refresh count become 31 to refill fresh entropy since last read of random number*/ + do + { + refreshCnt = ((base->COUNTER_VAL & RNG_COUNTER_VAL_REFRESH_CNT_MASK) >> RNG_COUNTER_VAL_REFRESH_CNT_SHIFT); + } while (refreshCnt < 31U); + + /* reading RANDOM_NUMBER register will reset refCnt to 0 */ + data = base->RANDOM_NUMBER; + + /* Perform CHI computing by checking max chi squared value */ + /* Wait until maxChiSq become smaller or equal than 4, then next random number can be read*/ + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + + while (maxChiSq > 4U) + { + /* Deactivate CHI computing to reset*/ + base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); + + /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ + tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); + if (tmpShift4x < 7U) + { + tmpShift4x++; + base->COUNTER_CFG = + (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); + } + rng_accumulateEntropy(base); + + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + } + + return data; +} void RNG_Init(RNG_Type *base) { + uint32_t maxChiSq, tmpShift4x; + /* Clear ring oscilator disable bit*/ PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_EnableClock(kCLOCK_Rng); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ - /* Clear POWERDOWN bit to enable RNG */ - base->POWERDOWN &= ~RNG_POWERDOWN_POWERDOWN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + + /* Turn on CHI Squared test */ + /* Activate CHI computing and wait until min chi squared become smaller than max chi squared */ + rng_accumulateEntropy(base); + + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + + /* When maxChiSq is bigger than 4 its assumed there is not enough entropy and previous steps are repeated */ + /* When maxChiSq is 4 or less initialization is complete and random number can be read*/ + while (maxChiSq > 4U) + { + /* Deactivate CHI coputing to reset*/ + base->ONLINE_TEST_CFG = RNG_ONLINE_TEST_CFG_ACTIVATE(0); + + /* read Shift4x register, if is less than 7 increment it and then start accumulating entropy again */ + tmpShift4x = ((base->COUNTER_CFG & RNG_COUNTER_CFG_SHIFT4X_MASK) >> RNG_COUNTER_CFG_SHIFT4X_SHIFT); + if (tmpShift4x < 7U) + { + tmpShift4x++; + base->COUNTER_CFG = + (base->COUNTER_CFG & ~RNG_COUNTER_CFG_SHIFT4X_MASK) | RNG_COUNTER_CFG_SHIFT4X(tmpShift4x); + } + rng_accumulateEntropy(base); + + maxChiSq = ((base->ONLINE_TEST_VAL & RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_MASK) >> + RNG_ONLINE_TEST_VAL_MAX_CHI_SQUARED_SHIFT); + } } void RNG_Deinit(RNG_Type *base) { /* Set ring oscilator disable bit*/ PMC->PDRUNCFGSET0 = PMC_PDRUNCFG0_PDEN_RNG_MASK; - /* Set POWERDOWN bit to disable RNG */ - base->POWERDOWN |= RNG_POWERDOWN_POWERDOWN_MASK; + +#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) + /* Reset the module. */ + RESET_PeripheralReset(kRNG_RST_SHIFT_RSTn); +#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ + #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) CLOCK_DisableClock(kCLOCK_Rng); #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ @@ -56,20 +172,20 @@ status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize) uint32_t i; /* Check input parameters.*/ - if (!(base && data && dataSize)) + if (!((base != NULL) && (data != NULL) && (dataSize != 0U))) { result = kStatus_InvalidArgument; } else { /* Check that ring oscilator is enabled */ - if (!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_RNG_MASK)) + if (0U == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_RNG_MASK)) { do { /* Read Entropy.*/ - random32 = base->RANDOM_NUMBER; - pRandom = (uint8_t *)&random32; + random32 = rng_readEntropy(base); + pRandom = (uint8_t *)&random32; if (dataSize < sizeof(random32)) { @@ -86,7 +202,7 @@ status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize) } dataSize -= randomSize; - } while (dataSize > 0); + } while (dataSize > 0U); result = kStatus_Success; } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.h index e5a7e90c48..38279cad7f 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rng.h @@ -1,5 +1,5 @@ /* - * Copyright 2017 NXP + * Copyright 2017, 2019, 2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,15 +21,25 @@ /*! @name Driver version */ /*@{*/ -/*! @brief RNG driver version. Version 2.0.0. +/*! @brief RNG driver version. Version 2.0.3. * - * Current version: 2.0.0 + * Current version: 2.0.3 * * Change log: * - Version 2.0.0 * - Initial version + * + * - Version 2.0.1 + * - Fix MISRA C-2012 issue. + * + * - Version 2.0.2 + * - Add RESET_PeripheralReset function inside RNG_Init and RNG_Deinit functions. + * + * - Version 2.0.3 + * - Modified RNG_Init and RNG_GetRandomData functions, added rng_accumulateEntropy and rng_readEntropy functions. + * - These changes are reflecting recommended usage of RNG according to device UM. */ -#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) /*@}*/ /******************************************************************************* @@ -47,7 +57,6 @@ extern "C" { * When called, the RNG module and ring oscillator is enabled. * * @param base RNG base address - * @param userConfig Pointer to the initialization configuration structure. * @return If successful, returns the kStatus_RNG_Success. Otherwise, it returns an error. */ void RNG_Init(RNG_Type *base); @@ -71,7 +80,7 @@ void RNG_Deinit(RNG_Type *base); * @param dataSize Size of the buffer pointed by the data parameter. * @return random data */ -status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t data_size); +status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize); /*! * @brief Returns random 32-bit number. diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.c index 49915aec41..b39370b683 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -17,18 +17,18 @@ #define FSL_COMPONENT_ID "platform.drivers.lpc_rtc" #endif -#define SECONDS_IN_A_DAY (86400U) -#define SECONDS_IN_A_HOUR (3600U) +#define SECONDS_IN_A_DAY (86400U) +#define SECONDS_IN_A_HOUR (3600U) #define SECONDS_IN_A_MINUTE (60U) -#define DAYS_IN_A_YEAR (365U) -#define YEAR_RANGE_START (1970U) -#define YEAR_RANGE_END (2099U) +#define DAYS_IN_A_YEAR (365U) +#define YEAR_RANGE_START (1970U) +#define YEAR_RANGE_END (2099U) /******************************************************************************* * Prototypes ******************************************************************************/ /*! - * @brief Checks whether the date and time passed in is valid + * @brief Check whether the date and time passed in is valid * * @param datetime Pointer to structure where the date and time details are stored * @@ -37,7 +37,7 @@ static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); /*! - * @brief Converts time data from datetime to seconds + * @brief Convert time data from datetime to seconds * * @param datetime Pointer to datetime structure where the date and time details are stored * @@ -46,7 +46,7 @@ static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime); static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime); /*! - * @brief Converts time data from seconds to a datetime structure + * @brief Convert time data from seconds to a datetime structure * * @param seconds Seconds value that needs to be converted to datetime format * @param datetime Pointer to the datetime structure where the result of the conversion is stored @@ -74,7 +74,7 @@ static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime) } /* Adjust the days in February for a leap year */ - if ((((datetime->year & 3U) == 0) && (datetime->year % 100 != 0)) || (datetime->year % 400 == 0)) + if ((((datetime->year & 3U) == 0U) && (datetime->year % 100U != 0U)) || (datetime->year % 400U == 0U)) { daysPerMonth[2] = 29U; } @@ -98,16 +98,16 @@ static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime) uint32_t seconds; /* Compute number of days from 1970 till given year*/ - seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR; + seconds = ((uint32_t)datetime->year - 1970U) * DAYS_IN_A_YEAR; /* Add leap year days */ - seconds += ((datetime->year / 4) - (1970U / 4)); + seconds += (((uint32_t)datetime->year / 4U) - (1970U / 4U)); /* Add number of days till given month*/ seconds += monthDays[datetime->month]; /* Add days in given month. We subtract the current day as it is * represented in the hours, minutes and seconds field*/ - seconds += (datetime->day - 1); + seconds += ((uint32_t)datetime->day - 1U); /* For leap year if month less than or equal to Febraury, decrement day counter*/ - if ((!(datetime->year & 3U)) && (datetime->month <= 2U)) + if (((datetime->year & 3U) == 0x00U) && (datetime->month <= 2U)) { seconds--; } @@ -122,9 +122,10 @@ static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datet { assert(datetime); - uint32_t x; - uint32_t secondsRemaining, days; + uint8_t i; uint16_t daysInYear; + uint32_t secondsRemaining; + uint32_t days; /* Table of days in a month for a non leap year. First entry in the table is not used, * valid months start from 1 */ @@ -136,16 +137,16 @@ static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datet /* Calcuate the number of days, we add 1 for the current day which is represented in the * hours and seconds field */ - days = secondsRemaining / SECONDS_IN_A_DAY + 1; + days = secondsRemaining / SECONDS_IN_A_DAY + 1U; /* Update seconds left*/ secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY; /* Calculate the datetime hour, minute and second fields */ - datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR; + datetime->hour = (uint8_t)(secondsRemaining / SECONDS_IN_A_HOUR); secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR; - datetime->minute = secondsRemaining / 60U; - datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE; + datetime->minute = (uint8_t)(secondsRemaining / 60U); + datetime->second = (uint8_t)(secondsRemaining % SECONDS_IN_A_MINUTE); /* Calculate year */ daysInYear = DAYS_IN_A_YEAR; @@ -157,40 +158,40 @@ static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datet datetime->year++; /* Adjust the number of days for a leap year */ - if (datetime->year & 3U) + if ((datetime->year & 3U) != 0x00U) { daysInYear = DAYS_IN_A_YEAR; } else { - daysInYear = DAYS_IN_A_YEAR + 1; + daysInYear = DAYS_IN_A_YEAR + 1U; } } /* Adjust the days in February for a leap year */ - if (!(datetime->year & 3U)) + if ((datetime->year & 3U) == 0x00U) { daysPerMonth[2] = 29U; } - for (x = 1U; x <= 12U; x++) + for (i = 1U; i <= 12U; i++) { - if (days <= daysPerMonth[x]) + if (days <= daysPerMonth[i]) { - datetime->month = x; + datetime->month = i; break; } else { - days -= daysPerMonth[x]; + days -= daysPerMonth[i]; } } - datetime->day = days; + datetime->day = (uint8_t)days; } /*! - * brief Ungates the RTC clock and enables the RTC oscillator. + * brief Ungate the RTC clock and enables the RTC oscillator. * * note This API should be called at the beginning of the application using the RTC driver. * @@ -216,7 +217,7 @@ void RTC_Init(RTC_Type *base) } /*! - * brief Sets the RTC date and time according to the given time structure. + * brief Set the RTC date and time according to the given time structure. * * The RTC counter must be stopped prior to calling this function as writes to the RTC * seconds register will fail if the RTC counter is running. @@ -255,12 +256,12 @@ void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) uint32_t seconds = 0; - seconds = base->COUNT; + seconds = RTC_GetSecondsTimerCount(base); RTC_ConvertSecondsToDatetime(seconds, datetime); } /*! - * brief Sets the RTC alarm time + * brief Set the RTC alarm time * * The function checks whether the specified alarm time is greater than the present * time. If not, the function does not set the alarm and returns an error. @@ -274,7 +275,7 @@ void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime) */ status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) { - assert(alarmTime); + assert(alarmTime != NULL); uint32_t alarmSeconds = 0; uint32_t currSeconds = 0; @@ -288,7 +289,7 @@ status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime); /* Get the current time */ - currSeconds = base->COUNT; + currSeconds = RTC_GetSecondsTimerCount(base); /* Return error if the alarm time has passed */ if (alarmSeconds < currSeconds) @@ -303,7 +304,7 @@ status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime) } /*! - * brief Returns the RTC alarm time. + * brief Return the RTC alarm time. * * param base RTC peripheral base address * param datetime Pointer to structure where the alarm date and time details are stored. diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.h index ebffd9c529..a960d8baf7 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_rtc.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,7 +23,7 @@ /*! @name Driver version */ /*@{*/ -#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */ +#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*!< Version 2.1.2 */ /*@}*/ /*! @brief List of RTC interrupts */ @@ -65,7 +65,7 @@ extern "C" { */ /*! - * @brief Ungates the RTC clock and enables the RTC oscillator. + * @brief Un-gate the RTC clock and enable the RTC oscillator. * * @note This API should be called at the beginning of the application using the RTC driver. * @@ -97,7 +97,7 @@ static inline void RTC_Deinit(RTC_Type *base) */ /*! - * @brief Sets the RTC date and time according to the given time structure. + * @brief Set the RTC date and time according to the given time structure. * * The RTC counter must be stopped prior to calling this function as writes to the RTC * seconds register will fail if the RTC counter is running. @@ -111,7 +111,7 @@ static inline void RTC_Deinit(RTC_Type *base) status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); /*! - * @brief Gets the RTC time and stores it in the given time structure. + * @brief Get the RTC time and stores it in the given time structure. * * @param base RTC peripheral base address * @param datetime Pointer to structure where the date and time details are stored. @@ -119,7 +119,7 @@ status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime); void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); /*! - * @brief Sets the RTC alarm time + * @brief Set the RTC alarm time * * The function checks whether the specified alarm time is greater than the present * time. If not, the function does not set the alarm and returns an error. @@ -134,7 +134,7 @@ void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime); status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime); /*! - * @brief Returns the RTC alarm time. + * @brief Return the RTC alarm time. * * @param base RTC peripheral base address * @param datetime Pointer to structure where the alarm date and time details are stored. @@ -144,29 +144,131 @@ void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime); /*! @}*/ /*! - * @brief Enable the RTC high resolution timer and set the wake-up time. - * - * @param base RTC peripheral base address - * @param wakeupValue The value to be loaded into the RTC WAKE register + * @name RTC wake-up timer (1KHZ) Enable + * @{ */ -static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) -{ - /* Enable the 1kHz RTC timer */ - base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; - /* Set the start count value into the wake-up timer */ - base->WAKE = wakeupValue; +/*! + * @brief Enable the RTC wake-up timer (1KHZ). + * + * After calling this function, the RTC driver will use/un-use the RTC wake-up (1KHZ) at the same time. + * + * @param base RTC peripheral base address + * @param enable Use/Un-use the RTC wake-up timer. + * - true: Use RTC wake-up timer at the same time. + * - false: Un-use RTC wake-up timer, RTC only use the normal seconds timer by default. + */ +static inline void RTC_EnableWakeupTimer(RTC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; + } + else + { + base->CTRL &= ~RTC_CTRL_RTC1KHZ_EN_MASK; + } } /*! - * @brief Read actual RTC counter value. + * @brief Get the enabled status of the RTC wake-up timer (1KHZ). + * + + * @param base RTC peripheral base address + * + * @return The enabled status of RTC wake-up timer (1KHZ). + */ +static inline uint32_t RTC_GetEnabledWakeupTimer(RTC_Type *base) +{ + return (base->CTRL & RTC_CTRL_RTC1KHZ_EN_MASK); +} + +/*! @}*/ + +/*! + * @brief Set the RTC seconds timer (1HZ) MATCH value. * * @param base RTC peripheral base address + * @param matchValue The value to be set into the RTC MATCH register + */ +static inline void RTC_SetSecondsTimerMatch(RTC_Type *base, uint32_t matchValue) +{ + /* Set the start match value into the default RTC seconds timer (1HZ). */ + base->MATCH = matchValue; +} + +/*! + * @brief Read actual RTC seconds timer (1HZ) MATCH value. + * + * @param base RTC peripheral base address + * + * @return The actual RTC seconds timer (1HZ) MATCH value. + */ +static inline uint32_t RTC_GetSecondsTimerMatch(RTC_Type *base) +{ + /* Read the RTC default seconds timer (1HZ) MATCH value. */ + return base->MATCH; +} + +/*! + * @brief Set the RTC seconds timer (1HZ) COUNT value. + * + * @param base RTC peripheral base address + * @param countValue The value to be loaded into the RTC COUNT register + */ +static inline void RTC_SetSecondsTimerCount(RTC_Type *base, uint32_t countValue) +{ + /* Set the start count value into the default RTC seconds timer (1HZ). */ + base->COUNT = countValue; +} + +/*! + * @brief Read the actual RTC seconds timer (1HZ) COUNT value. + * + * @param base RTC peripheral base address + * + * @return The actual RTC seconds timer (1HZ) COUNT value. + */ +static inline uint32_t RTC_GetSecondsTimerCount(RTC_Type *base) +{ + uint32_t a, b; + + /* Follow the RF document to read the RTC default seconds timer (1HZ) counter value. */ + do + { + a = base->COUNT; + b = base->COUNT; + } while (a != b); + + return b; +} + +/*! + * @brief Enable the RTC wake-up timer (1KHZ) and set countdown value to the RTC WAKE register. + * + * @param base RTC peripheral base address + * @param wakeupValue The value to be loaded into the WAKE register in RTC wake-up timer (1KHZ). + */ +static inline void RTC_SetWakeupCount(RTC_Type *base, uint16_t wakeupValue) +{ + /* Use the RTC wake-up timer (1KHZ) */ + base->CTRL |= RTC_CTRL_RTC1KHZ_EN_MASK; + + /* Set the start countdown value into the RTC WAKE register */ + base->WAKE = RTC_WAKE_VAL((uint32_t)wakeupValue); +} + +/*! + * @brief Read the actual value from the WAKE register value in RTC wake-up timer (1KHZ). + * + * @param base RTC peripheral base address + * + * @return The actual value of the WAKE register value in RTC wake-up timer (1HZ). */ static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) { - /* Read wake-up counter */ - return RTC_WAKE_VAL(base->WAKE); + /* Read current wake-up countdown value */ + return (uint16_t)((base->WAKE & RTC_WAKE_VAL_MASK) >> RTC_WAKE_VAL_SHIFT); } /*! @@ -174,8 +276,50 @@ static inline uint16_t RTC_GetWakeupCount(RTC_Type *base) * @{ */ +/*! + * @brief Enable the wake-up timer interrupt from deep power down mode. + * + * @param base RTC peripheral base address + * @param enable Enable/Disable wake-up timer interrupt from deep power down mode. + * - true: Enable wake-up timer interrupt from deep power down mode. + * - false: Disable wake-up timer interrupt from deep power down mode. + */ +static inline void RTC_EnableWakeUpTimerInterruptFromDPD(RTC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= RTC_CTRL_WAKEDPD_EN_MASK; + } + else + { + base->CTRL &= ~RTC_CTRL_WAKEDPD_EN_MASK; + } +} + +/*! + * @brief Enable the alarm timer interrupt from deep power down mode. + * + * @param base RTC peripheral base address + * @param enable Enable/Disable alarm timer interrupt from deep power down mode. + * - true: Enable alarm timer interrupt from deep power down mode. + * - false: Disable alarm timer interrupt from deep power down mode. + */ +static inline void RTC_EnableAlarmTimerInterruptFromDPD(RTC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= RTC_CTRL_ALARMDPD_EN_MASK; + } + else + { + base->CTRL &= ~RTC_CTRL_ALARMDPD_EN_MASK; + } +} + /*! * @brief Enables the selected RTC interrupts. + * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD + * and RTC_EnableWakeUpTimerInterruptFromDPD * * @param base RTC peripheral base address * @param mask The interrupts to enable. This is a logical OR of members of the @@ -194,6 +338,8 @@ static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask) /*! * @brief Disables the selected RTC interrupts. + * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableAlarmTimerInterruptFromDPD + * and RTC_EnableWakeUpTimerInterruptFromDPD * * @param base RTC peripheral base address * @param mask The interrupts to enable. This is a logical OR of members of the @@ -210,7 +356,8 @@ static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask) } /*! - * @brief Gets the enabled RTC interrupts. + * @brief Get the enabled RTC interrupts. + * @deprecated Do not use this function. It will be deleted in next release version. * * @param base RTC peripheral base address * @@ -230,7 +377,7 @@ static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base) */ /*! - * @brief Gets the RTC status flags + * @brief Get the RTC status flags * * @param base RTC peripheral base address * @@ -243,7 +390,7 @@ static inline uint32_t RTC_GetStatusFlags(RTC_Type *base) } /*! - * @brief Clears the RTC status flags. + * @brief Clear the RTC status flags. * * @param base RTC peripheral base address * @param mask The status flags to clear. This is a logical OR of members of the @@ -265,12 +412,39 @@ static inline void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask) /*! @}*/ /*! - * @name Timer Start and Stop + * @name Timer Enable * @{ */ +/*! + * @brief Enable the RTC timer counter. + * + * After calling this function, the RTC inner counter increments once a second when only using the RTC seconds timer + * (1hz), while the RTC inner wake-up timer countdown once a millisecond when using RTC wake-up timer (1KHZ) at the + * same time. RTC timer contain two timers, one is the RTC normal seconds timer, the other one is the RTC wake-up timer, + * the RTC enable bit is the master switch for the whole RTC timer, so user can use the RTC seconds (1HZ) timer + * independly, but they can't use the RTC wake-up timer (1KHZ) independently. + * + * @param base RTC peripheral base address + * @param enable Enable/Disable RTC Timer counter. + * - true: Enable RTC Timer counter. + * - false: Disable RTC Timer counter. + */ +static inline void RTC_EnableTimer(RTC_Type *base, bool enable) +{ + if (enable) + { + base->CTRL |= RTC_CTRL_RTC_EN_MASK; + } + else + { + base->CTRL &= ~RTC_CTRL_RTC_EN_MASK; + } +} + /*! * @brief Starts the RTC time counter. + * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer * * After calling this function, the timer counter increments once a second provided SR[TOF] or * SR[TIF] are not set. @@ -284,6 +458,7 @@ static inline void RTC_StartTimer(RTC_Type *base) /*! * @brief Stops the RTC time counter. + * @deprecated Do not use this function. It has been superceded by @ref RTC_EnableTimer * * RTC's seconds register can be written to only when the timer is stopped. * @@ -297,7 +472,7 @@ static inline void RTC_StopTimer(RTC_Type *base) /*! @}*/ /*! - * @brief Performs a software reset on the RTC module. + * @brief Perform a software reset on the RTC module. * * This resets all RTC registers to their reset value. The bit is cleared by software explicitly clearing it. * diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c index ab89d3ff4e..4208097a8b 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -62,8 +62,10 @@ static uint32_t s_currentEvent; /*!< @brief Keep track of SCTimer state number */ static uint32_t s_currentState; -/*!< @brief Keep track of SCTimer match/capture register number */ +/*!< @brief Keep track of SCTimer unify 32-bit or low 16-bit match/capture register number. */ static uint32_t s_currentMatch; +/*!< @brief Keep track of SCTimer high 16-bit match/capture register number. */ +static uint32_t s_currentMatchhigh; /*! @brief Pointer to SCTimer IRQ handler */ static sctimer_isr_t s_sctimerIsr; @@ -102,7 +104,8 @@ static uint32_t SCTIMER_GetInstance(SCT_Type *base) */ status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) { - assert(config); + assert(NULL != config); + uint32_t i; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -120,26 +123,30 @@ status_t SCTIMER_Init(SCT_Type *base, const sctimer_config_t *config) base->CONFIG = SCT_CONFIG_CKSEL(config->clockSelect) | SCT_CONFIG_CLKMODE(config->clockMode) | SCT_CONFIG_UNIFY(config->enableCounterUnify) | SCT_CONFIG_INSYNC(config->inputsync); - /* Write to the control register, clear the counter and keep the counters halted */ - base->CTRL = SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | - SCT_CTRL_CLRCTR_L_MASK | SCT_CTRL_HALT_L_MASK; + /* Write to the control register, keep the counters halted. */ + base->CTRL = + SCT_CTRL_BIDIR_L(config->enableBidirection_l) | SCT_CTRL_PRE_L(config->prescale_l) | SCT_CTRL_HALT_L_MASK; + /* Clear the counter after changing the PRE value. */ + base->CTRL |= SCT_CTRL_CLRCTR_L_MASK; if (!(config->enableCounterUnify)) { - base->CTRL |= SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | - SCT_CTRL_CLRCTR_H_MASK | SCT_CTRL_HALT_H_MASK; + base->CTRL |= + SCT_CTRL_BIDIR_H(config->enableBidirection_h) | SCT_CTRL_PRE_H(config->prescale_h) | SCT_CTRL_HALT_H_MASK; + base->CTRL |= SCT_CTRL_CLRCTR_H_MASK; } /* Initial state of channel output */ base->OUTPUT = config->outInitState; /* Clear the global variables */ - s_currentEvent = 0; - s_currentState = 0; - s_currentMatch = 0; + s_currentEvent = 0U; + s_currentState = 0U; + s_currentMatch = 0U; + s_currentMatchhigh = 0U; /* Clear the callback array */ - for (i = 0; i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) + for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) { s_eventCallback[i] = NULL; } @@ -185,10 +192,10 @@ void SCTIMER_Deinit(SCT_Type *base) */ void SCTIMER_GetDefaultConfig(sctimer_config_t *config) { - assert(config); + assert(NULL != config); /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); /* SCT operates as a unified 32-bit counter */ config->enableCounterUnify = true; @@ -255,163 +262,174 @@ status_t SCTIMER_SetupPwm(SCT_Type *base, uint32_t srcClock_Hz, uint32_t *event) { - assert(pwmParams); - assert(srcClock_Hz); - assert(pwmFreq_Hz); - assert(pwmParams->output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + assert(NULL != pwmParams); + assert(0U != srcClock_Hz); + assert(0U != pwmFreq_Hz); + assert((uint32_t)pwmParams->output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* If we do not have enough events available (this function will create two events), + * the function will return fail. + */ + status_t status = kStatus_Fail; + status_t status2; uint32_t period, pulsePeriod = 0; - uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1); + uint32_t sctClock = srcClock_Hz / (((base->CTRL & SCT_CTRL_PRE_L_MASK) >> SCT_CTRL_PRE_L_SHIFT) + 1U); uint32_t periodEvent = 0, pulseEvent = 0; uint32_t reg; - /* This function will create 2 events, return an error if we do not have enough events available */ - if ((s_currentEvent + 2) > FSL_FEATURE_SCT_NUMBER_OF_EVENTS) + if ((s_currentEvent + 2U) <= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) { - return kStatus_Fail; - } - - if (pwmParams->dutyCyclePercent == 0) - { - return kStatus_Fail; - } - - /* Set unify bit to operate in 32-bit counter mode */ - base->CONFIG |= SCT_CONFIG_UNIFY_MASK; - - /* Use bi-directional mode for center-aligned PWM */ - if (mode == kSCTIMER_CenterAlignedPwm) - { - base->CTRL |= SCT_CTRL_BIDIR_L_MASK; - } - - /* Calculate PWM period match value */ - if (mode == kSCTIMER_EdgeAlignedPwm) - { - period = (sctClock / pwmFreq_Hz) - 1; - } - else - { - period = sctClock / (pwmFreq_Hz * 2); - } - - /* Calculate pulse width match value */ - pulsePeriod = (period * pwmParams->dutyCyclePercent) / 100; - - /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (pwmParams->dutyCyclePercent >= 100) - { - pulsePeriod = period + 2; - } - - /* Schedule an event when we reach the PWM period */ - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_L, &periodEvent); - - /* Schedule an event when we reach the pulse width */ - SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_L, &pulseEvent); - - /* Reset the counter when we reach the PWM period */ - SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_L, periodEvent); - - /* Return the period event to the user */ - *event = periodEvent; - - /* For high-true level */ - if (pwmParams->level == kSCTIMER_HighTrue) - { - /* Set the initial output level to low which is the inactive state */ - base->OUTPUT &= ~(1U << pwmParams->output); + /* Use bi-directional mode for center-aligned PWM */ + if (mode == kSCTIMER_CenterAlignedPwm) + { + base->CTRL |= SCT_CTRL_BIDIR_L_MASK; + } + /* Calculate PWM period match value */ if (mode == kSCTIMER_EdgeAlignedPwm) { - /* Set the output when we reach the PWM period */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, periodEvent); - /* Clear the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); + period = (sctClock / pwmFreq_Hz) - 1U; } else { - /* Clear the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); - reg |= (1U << (2 * pwmParams->output)); - base->OUTPUTDIRCTRL = reg; + period = sctClock / (pwmFreq_Hz * 2U); } - } - /* For low-true level */ - else - { - /* Set the initial output level to high which is the inactive state */ - base->OUTPUT |= (1U << pwmParams->output); - if (mode == kSCTIMER_EdgeAlignedPwm) + /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ + if (pwmParams->dutyCyclePercent >= 100U) { - /* Clear the output when we reach the PWM period */ - SCTIMER_SetupOutputClearAction(base, pwmParams->output, periodEvent); - /* Set the output when we reach the PWM pulse value */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); + pulsePeriod = period + 2U; } else { - /* Set the output when we reach the PWM pulse event */ - SCTIMER_SetupOutputSetAction(base, pwmParams->output, pulseEvent); - /* Reverse output when down counting */ - reg = base->OUTPUTDIRCTRL; - reg &= ~(SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2 * pwmParams->output)); - reg |= (1U << (2 * pwmParams->output)); - base->OUTPUTDIRCTRL = reg; + pulsePeriod = (uint32_t)(((uint64_t)period * pwmParams->dutyCyclePercent) / 100U); + } + + /* Schedule an event when we reach the PWM period */ + status = + SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, period, 0, kSCTIMER_Counter_U, &periodEvent); + + /* Schedule an event when we reach the pulse width */ + status2 = SCTIMER_CreateAndScheduleEvent(base, kSCTIMER_MatchEventOnly, pulsePeriod, 0, kSCTIMER_Counter_U, + &pulseEvent); + + if ((kStatus_Success == status) && (kStatus_Success == status2)) + { + /* Reset the counter when we reach the PWM period */ + SCTIMER_SetupCounterLimitAction(base, kSCTIMER_Counter_U, periodEvent); + + /* Return the period event to the user */ + *event = periodEvent; + + /* For high-true level */ + if ((uint32_t)pwmParams->level == (uint32_t)kSCTIMER_HighTrue) + { + if (mode == kSCTIMER_EdgeAlignedPwm) + { + /* Set the initial output level to low which is the inactive state */ + base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); + /* Set the output when we reach the PWM period */ + SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, periodEvent); + /* Clear the output when we reach the PWM pulse value */ + SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); + } + else + { + /* Set the initial output level to high which is the inactive state */ + base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); + /* Clear the output when we reach the PWM pulse event */ + SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, pulseEvent); + /* Reverse output when down counting */ + reg = base->OUTPUTDIRCTRL; + reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); + reg |= (1UL << (2U * (uint32_t)pwmParams->output)); + base->OUTPUTDIRCTRL = reg; + } + } + /* For low-true level */ + else + { + if (mode == kSCTIMER_EdgeAlignedPwm) + { + /* Set the initial output level to high which is the inactive state */ + base->OUTPUT |= (1UL << (uint32_t)pwmParams->output); + /* Clear the output when we reach the PWM period */ + SCTIMER_SetupOutputClearAction(base, (uint32_t)pwmParams->output, periodEvent); + /* Set the output when we reach the PWM pulse value */ + SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); + } + else + { + /* Set the initial output level to low which is the inactive state */ + base->OUTPUT &= ~(1UL << (uint32_t)pwmParams->output); + /* Set the output when we reach the PWM pulse event */ + SCTIMER_SetupOutputSetAction(base, (uint32_t)pwmParams->output, pulseEvent); + /* Reverse output when down counting */ + reg = base->OUTPUTDIRCTRL; + reg &= ~((uint32_t)SCT_OUTPUTDIRCTRL_SETCLR0_MASK << (2U * (uint32_t)pwmParams->output)); + reg |= (1UL << (2U * (uint32_t)pwmParams->output)); + base->OUTPUTDIRCTRL = reg; + } + } + } + else + { + status = kStatus_Fail; } } - return kStatus_Success; + return status; } /*! * brief Updates the duty cycle of an active PWM signal. * + * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). + * * param base SCTimer peripheral base address * param output The output to configure - * param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 + * param dutyCyclePercent New PWM pulse width; the value should be between 0 to 100 * param event Event number associated with this PWM signal. This was returned to the user by the * function SCTIMER_SetupPwm(). */ void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t dutyCyclePercent, uint32_t event) { - assert(dutyCyclePercent > 0); - assert(output < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + assert(dutyCyclePercent <= 100U); + assert((uint32_t)output < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); uint32_t periodMatchReg, pulseMatchReg; uint32_t pulsePeriod = 0, period; /* Retrieve the match register number for the PWM period */ - periodMatchReg = base->EVENT[event].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; + periodMatchReg = base->EV[event].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; /* Retrieve the match register number for the PWM pulse period */ - pulseMatchReg = base->EVENT[event + 1].CTRL & SCT_EVENT_CTRL_MATCHSEL_MASK; + pulseMatchReg = base->EV[event + 1U].CTRL & SCT_EV_CTRL_MATCHSEL_MASK; - period = base->SCTMATCH[periodMatchReg]; - - /* Calculate pulse width match value */ - pulsePeriod = (period * dutyCyclePercent) / 100; + period = base->MATCH[periodMatchReg]; /* For 100% dutycyle, make pulse period greater than period so the event will never occur */ - if (dutyCyclePercent >= 100) + if (dutyCyclePercent >= 100U) { - pulsePeriod = period + 2; + pulsePeriod = period + 2U; + } + else + { + pulsePeriod = (uint32_t)(((uint64_t)period * dutyCyclePercent) / 100U); } /* Stop the counter before updating match register */ - SCTIMER_StopTimer(base, kSCTIMER_Counter_L); + SCTIMER_StopTimer(base, (uint32_t)kSCTIMER_Counter_U); /* Update dutycycle */ - base->SCTMATCH[pulseMatchReg] = SCT_SCTMATCH_MATCHn_L(pulsePeriod); - base->SCTMATCHREL[pulseMatchReg] = SCT_SCTMATCHREL_RELOADn_L(pulsePeriod); + base->MATCH[pulseMatchReg] = SCT_MATCH_MATCHn_L(pulsePeriod); + base->MATCHREL[pulseMatchReg] = SCT_MATCHREL_RELOADn_L(pulsePeriod); /* Restart the counter */ - SCTIMER_StartTimer(base, kSCTIMER_Counter_L); + SCTIMER_StartTimer(base, (uint32_t)kSCTIMER_Counter_U); } /*! @@ -429,8 +447,8 @@ void SCTIMER_UpdatePwmDutycycle(SCT_Type *base, sctimer_out_t output, uint8_t du * param matchValue The match value that will be programmed to a match register * param whichIO The input or output that will be involved in event triggering. This field * is ignored if the event type is "match only" - * param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as we have only 1 unified counter; hence ignored. + * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. * param event Pointer to a variable where the new event number is stored * * return kStatus_Success on success @@ -444,85 +462,113 @@ status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t *event) { - uint32_t combMode = (((uint32_t)howToMonitor & SCT_EVENT_CTRL_COMBMODE_MASK) >> SCT_EVENT_CTRL_COMBMODE_SHIFT); - uint32_t currentCtrlVal = howToMonitor; + uint32_t combMode = (((uint32_t)howToMonitor & SCT_EV_CTRL_COMBMODE_MASK) >> SCT_EV_CTRL_COMBMODE_SHIFT); + uint32_t currentCtrlVal = (uint32_t)howToMonitor; + status_t status = kStatus_Success; + uint32_t temp = 0; - /* Return an error if we have hit the limit in terms of number of events created */ - if (s_currentEvent >= FSL_FEATURE_SCT_NUMBER_OF_EVENTS) + if (s_currentEvent < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS) { - return kStatus_Fail; - } - - /* IO only mode */ - if (combMode == 0x2U) - { - base->EVENT[s_currentEvent].CTRL = currentCtrlVal | SCT_EVENT_CTRL_IOSEL(whichIO); - } - /* Match mode only */ - else if (combMode == 0x1U) - { - /* Return an error if we have hit the limit in terms of number of number of match registers */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + if (2U == combMode) { - return kStatus_Fail; - } - - currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch); - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); + base->EV[s_currentEvent].CTRL = currentCtrlVal | SCT_EV_CTRL_IOSEL(whichIO); } else { - /* Select the counter, no need for this if operating in 32-bit mode */ - currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); + if ((0U == combMode) || (3U == combMode)) + { + currentCtrlVal |= SCT_EV_CTRL_IOSEL(whichIO); + } + + if ((kSCTIMER_Counter_L == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) + { + if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); + + /* Use Counter_L bits if user wants to setup the Low counter */ + base->MATCH_ACCESS16BIT[s_currentMatch].MATCHL = (uint16_t)matchValue; + base->MATCHREL_ACCESS16BIT[s_currentMatch].MATCHRELL = (uint16_t)matchValue; + base->EV[s_currentEvent].CTRL = currentCtrlVal; + + /* Increment the match register number */ + s_currentMatch++; + } + else + { + /* An error would occur if we have hit the limit in terms of number of match registers */ + status = kStatus_Fail; + } + } + else if ((kSCTIMER_Counter_H == whichCounter) && (0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) + { + if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatchhigh); + + /* Use Counter_H bits if user wants to setup the High counter */ + currentCtrlVal |= SCT_EV_CTRL_HEVENT(1U); + temp = base->MATCH_ACCESS16BIT[s_currentMatchhigh].MATCHL; + base->MATCH[s_currentMatchhigh] = temp | (matchValue << 16U); + temp = base->MATCHREL_ACCESS16BIT[s_currentMatchhigh].MATCHRELL; + base->MATCHREL[s_currentMatchhigh] = temp | (matchValue << 16U); + + base->EV[s_currentEvent].CTRL = currentCtrlVal; + /* Increment the match register number */ + s_currentMatchhigh++; + } + else + { + /* An error would occur if we have hit the limit in terms of number of match registers */ + status = kStatus_Fail; + } + } + else if ((kSCTIMER_Counter_U == whichCounter) && (0U != (base->CONFIG & SCT_CONFIG_UNIFY_MASK))) + { + if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + /* Use Counter_L bits if counter is operating in 32-bit mode */ + currentCtrlVal |= SCT_EV_CTRL_MATCHSEL(s_currentMatch); + + base->MATCH[s_currentMatch] = matchValue; + base->MATCHREL[s_currentMatch] = matchValue; + base->EV[s_currentEvent].CTRL = currentCtrlVal; + + /* Increment the match register number */ + s_currentMatch++; + } + else + { + /* An error would occur if we have hit the limit in terms of number of match registers */ + status = kStatus_Fail; + } + } + else + { + /* The used counter must match the CONFIG[UNIFY] bit selection */ + status = kStatus_Fail; + } + } + + if (kStatus_Success == status) + { + /* Enable the event in the current state */ + base->EV[s_currentEvent].STATE = (1UL << s_currentState); + + /* Return the event number */ + *event = s_currentEvent; + + /* Increment the event number */ + s_currentEvent++; } - base->EVENT[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatch++; } - /* Use both Match & IO */ else { - /* Return an error if we have hit the limit in terms of number of number of match registers */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - return kStatus_Fail; - } - - currentCtrlVal |= SCT_EVENT_CTRL_MATCHSEL(s_currentMatch) | SCT_EVENT_CTRL_IOSEL(whichIO); - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) - { - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_L(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_L(matchValue); - } - else - { - /* Select the counter, no need for this if operating in 32-bit mode */ - currentCtrlVal |= SCT_EVENT_CTRL_HEVENT(whichCounter); - base->SCTMATCH[s_currentMatch] = SCT_SCTMATCH_MATCHn_H(matchValue); - base->SCTMATCHREL[s_currentMatch] = SCT_SCTMATCHREL_RELOADn_H(matchValue); - } - base->EVENT[s_currentEvent].CTRL = currentCtrlVal; - /* Increment the match register number */ - s_currentMatch++; + /* An error would occur if we have hit the limit in terms of number of events created */ + status = kStatus_Fail; } - /* Enable the event in the current state */ - base->EVENT[s_currentEvent].STATE = (1U << s_currentState); - - /* Return the event number */ - *event = s_currentEvent; - - /* Increment the event number */ - s_currentEvent++; - - return kStatus_Success; + return status; } /*! @@ -539,7 +585,7 @@ status_t SCTIMER_CreateAndScheduleEvent(SCT_Type *base, void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) { /* Enable event in the current state */ - base->EVENT[event].STATE |= (1U << s_currentState); + base->EV[event].STATE |= (1UL << s_currentState); } /*! @@ -556,15 +602,19 @@ void SCTIMER_ScheduleEvent(SCT_Type *base, uint32_t event) */ status_t SCTIMER_IncreaseState(SCT_Type *base) { + status_t status = kStatus_Success; + /* Return an error if we have hit the limit in terms of states used */ - if (s_currentState >= FSL_FEATURE_SCT_NUMBER_OF_STATES) + if (s_currentState >= (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES) { - return kStatus_Fail; + status = kStatus_Fail; + } + else + { + s_currentState++; } - s_currentState++; - - return kStatus_Success; + return status; } /*! @@ -592,18 +642,18 @@ uint32_t SCTIMER_GetCurrentState(SCT_Type *base) */ void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t event) { - assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); uint32_t reg; /* Set the same event to set and clear the output */ - base->OUT[whichIO].CLR |= (1U << event); - base->OUT[whichIO].SET |= (1U << event); + base->OUT[whichIO].CLR |= (1UL << event); + base->OUT[whichIO].SET |= (1UL << event); /* Set the conflict resolution to toggle output */ reg = base->RES; - reg &= ~(SCT_RES_O0RES_MASK << (2 * whichIO)); - reg |= (uint32_t)(kSCTIMER_ResolveToggle << (2 * whichIO)); + reg &= ~(((uint32_t)SCT_RES_O0RES_MASK) << (2U * whichIO)); + reg |= ((uint32_t)(kSCTIMER_ResolveToggle)) << (2U * whichIO); base->RES = reg; } @@ -611,8 +661,8 @@ void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t * brief Setup capture of the counter value on trigger of a selected event * * param base SCTimer peripheral base address - * param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. + * param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. * param captureRegister Pointer to a variable where the capture register number will be returned. User * can read the captured value from this register when the specified event is triggered. * param event Event number that will trigger the capture @@ -625,37 +675,60 @@ status_t SCTIMER_SetupCaptureAction(SCT_Type *base, uint32_t *captureRegister, uint32_t event) { - /* Return an error if we have hit the limit in terms of number of capture/match registers used */ - if (s_currentMatch >= FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) - { - return kStatus_Fail; - } + status_t status; + uint32_t temp = 0; - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + if ((kSCTIMER_Counter_L == whichCounter) || (kSCTIMER_Counter_U == whichCounter)) { - /* Set the bit to enable event */ - base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_L(1 << event); + if (s_currentMatch < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + /* Set the bit to enable event */ + base->CAPCTRL_ACCESS16BIT[s_currentMatch].CAPCTRLL |= SCT_CAPCTRLL_CAPCTRLL(1UL << event); - /* Set this resource to be a capture rather than match */ - base->REGMODE |= SCT_REGMODE_REGMOD_L(1 << s_currentMatch); + /* Set this resource to be a capture rather than match */ + base->REGMODE_ACCESS16BIT.REGMODEL |= SCT_REGMODEL_REGMODEL(1UL << s_currentMatch); + + /* Return the match register number */ + *captureRegister = s_currentMatch; + + /* Increase the match register number */ + s_currentMatch++; + + status = kStatus_Success; + } + else + { + /* Return an error if we have hit the limit in terms of number of capture/match registers used */ + status = kStatus_Fail; + } } else { - /* Set bit to enable event */ - base->SCTCAPCTRL[s_currentMatch] |= SCT_SCTCAPCTRL_CAPCONn_H(1 << event); + if (s_currentMatchhigh < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE) + { + /* Set bit to enable event */ + temp = base->CAPCTRL_ACCESS16BIT[s_currentMatchhigh].CAPCTRLL; + base->CAPCTRL[s_currentMatchhigh] = temp | ((uint32_t)((uint32_t)(1UL << event) << 16U) & 0xFFFF000U); + /* Set this resource to be a capture rather than match */ + temp = base->REGMODE_ACCESS16BIT.REGMODEL; + base->REGMODE = temp | ((uint32_t)((uint32_t)(1UL << s_currentMatchhigh) << 16U) & 0xFFFF000U); - /* Set this resource to be a capture rather than match */ - base->REGMODE |= SCT_REGMODE_REGMOD_H(1 << s_currentMatch); + /* Return the match register number */ + *captureRegister = s_currentMatchhigh; + + /* Increase the match register number */ + s_currentMatchhigh++; + + status = kStatus_Success; + } + else + { + /* Return an error if we have hit the limit in terms of number of capture/match registers used */ + status = kStatus_Fail; + } } - /* Return the match register number */ - *captureRegister = s_currentMatch; - - /* Increase the match register number */ - s_currentMatch++; - - return kStatus_Success; + return status; } /*! @@ -685,31 +758,34 @@ void SCTIMER_EventHandleIRQ(SCT_Type *base) /* Only clear the flags whose interrupt field is enabled */ uint32_t clearFlag = (eventFlag & SCT0->EVEN); uint32_t mask = eventFlag; - int i = 0; + uint32_t i; /* Invoke the callback for certain events */ - for (i = 0; (i < FSL_FEATURE_SCT_NUMBER_OF_EVENTS) && (mask != 0); i++) + for (i = 0; i < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS; i++) { - if (mask & 0x1) + if ((mask & 0x1U) != 0U) { if (s_eventCallback[i] != NULL) { s_eventCallback[i](); } } - mask >>= 1; + mask >>= 1UL; + + if (0U == mask) + { + /* All events have been handled. */ + break; + } } /* Clear event interrupt flag */ SCT0->EVFLAG = clearFlag; } +void SCT0_DriverIRQHandler(void); void SCT0_DriverIRQHandler(void) { s_sctimerIsr(SCT0); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h index db9865f079..283a5b7019 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sctimer.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,9 +23,13 @@ /*! @name Driver version */ /*@{*/ -#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0 */ +#define FSL_SCTIMER_DRIVER_VERSION (MAKE_VERSION(2, 4, 4)) /*!< Version */ /*@}*/ +#ifndef SCT_EV_STATE_STATEMSKn +#define SCT_EV_STATE_STATEMSKn(x) (((uint32_t)(x) & (1UL << FSL_FEATURE_SCT_NUMBER_OF_STATES) - 1UL)) +#endif + /*! @brief SCTimer PWM operation modes */ typedef enum _sctimer_pwm_mode { @@ -33,11 +37,12 @@ typedef enum _sctimer_pwm_mode kSCTIMER_CenterAlignedPwm /*!< Center-aligned PWM */ } sctimer_pwm_mode_t; -/*! @brief SCTimer counters when working as two independent 16-bit counters */ +/*! @brief SCTimer counters type. */ typedef enum _sctimer_counter { - kSCTIMER_Counter_L = 0U, /*!< Counter L */ - kSCTIMER_Counter_H /*!< Counter H */ + kSCTIMER_Counter_L = (1U << 0), /*!< 16-bit Low counter. */ + kSCTIMER_Counter_H = (1U << 1), /*!< 16-bit High counter. */ + kSCTIMER_Counter_U = (1U << 2), /*!< 32-bit Unified counter. */ } sctimer_counter_t; /*! @brief List of SCTimer input pins */ @@ -80,7 +85,8 @@ typedef struct _sctimer_pwm_signal_param { sctimer_out_t output; /*!< The output pin to use to generate the PWM signal */ sctimer_pwm_level_select_t level; /*!< PWM output active level select. */ - uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 1 to 100 + uint8_t dutyCyclePercent; /*!< PWM pulse width, value should be between 0 to 100 + 0 = always inactive signal (0% duty cycle) 100 = always active signal (100% duty cycle).*/ } sctimer_pwm_signal_param_t; @@ -128,65 +134,73 @@ typedef enum _sctimer_conflict_resolution kSCTIMER_ResolveToggle /*!< Toggle output */ } sctimer_conflict_resolution_t; +/*! @brief List of SCTimer event generation active direction when the counters are operating in BIDIR mode. */ +typedef enum _sctimer_event_active_direction +{ + kSCTIMER_ActiveIndependent = 0U, /*!< This event is triggered regardless of the count direction. */ + kSCTIMER_ActiveInCountUp, /*!< This event is triggered only during up-counting when BIDIR = 1. */ + kSCTIMER_ActiveInCountDown /*!< This event is triggered only during down-counting when BIDIR = 1. */ +} sctimer_event_active_direction_t; + /*! @brief List of SCTimer event types */ typedef enum _sctimer_event { kSCTIMER_InputLowOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_InputRiseOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_InputFallOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_InputHighOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_MatchEventOnly = - (1 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (1 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_InputLowEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_InputRiseEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_InputFallEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_InputHighEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_InputLowAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_InputRiseAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_InputFallAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_InputHighAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (0 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (0 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputLowOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputRiseOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputFallOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputHighOrMatchEvent = - (0 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (0 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputLowEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputRiseEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputFallEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputHighEvent = - (2 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (2 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputLowAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (0 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (0 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputRiseAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (1 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (1 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputFallAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (2 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT), + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (2 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT), kSCTIMER_OutputHighAndMatchEvent = - (3 << SCT_EVENT_CTRL_COMBMODE_SHIFT) + (3 << SCT_EVENT_CTRL_IOCOND_SHIFT) + (1 << SCT_EVENT_CTRL_OUTSEL_SHIFT) + (3 << SCT_EV_CTRL_COMBMODE_SHIFT) + (3 << SCT_EV_CTRL_IOCOND_SHIFT) + (1 << SCT_EV_CTRL_OUTSEL_SHIFT) } sctimer_event_t; /*! @brief SCTimer callback typedef. */ @@ -244,7 +258,10 @@ typedef enum _sctimer_status_flags typedef struct _sctimer_config { bool enableCounterUnify; /*!< true: SCT operates as a unified 32-bit counter; - false: SCT operates as two 16-bit counters */ + false: SCT operates as two 16-bit counters. + User can use the 16-bit low counter and the 16-bit high counters at the + same time; for Hardware limit, user can not use unified 32-bit counter + and any 16-bit low/high counter at the same time. */ sctimer_clock_mode_t clockMode; /*!< SCT clock mode value */ sctimer_clock_select_t clockSelect; /*!< SCT clock select value */ bool enableBidirection_l; /*!< true: Up-down count mode for the L or unified counter @@ -268,10 +285,10 @@ typedef struct _sctimer_config How User to set the the value for the member inputsync. IE: delay for input0, and input 1, bypasses for input 2 and input 3 MACRO definition in user level. - #define INPUTSYNC0 (0U) - #define INPUTSYNC1 (1U) - #define INPUTSYNC2 (2U) - #define INPUTSYNC3 (3U) + \#define INPUTSYNC0 (0U) + \#define INPUTSYNC1 (1U) + \#define INPUTSYNC2 (2U) + \#define INPUTSYNC3 (3U) User Code. sctimerInfo.inputsync = (1 << INPUTSYNC2) | (1 << INPUTSYNC3); */ } sctimer_config_t; @@ -373,6 +390,8 @@ status_t SCTIMER_SetupPwm(SCT_Type *base, /*! * @brief Updates the duty cycle of an active PWM signal. * + * Before calling this function, the counter is set to operate as one 32-bit counter (unify bit is set to 1). + * * @param base SCTimer peripheral base address * @param output The output to configure * @param dutyCyclePercent New PWM pulse width; the value should be between 1 to 100 @@ -475,21 +494,44 @@ static inline void SCTIMER_ClearStatusFlags(SCT_Type *base, uint32_t mask) /*! * @brief Starts the SCTimer counter. * - * @param base SCTimer peripheral base address - * @param countertoStart SCTimer counter to start; if unify mode is set then function always - * writes to HALT_L bit + * @note In 16-bit mode, we can enable both Counter_L and Counter_H, In 32-bit mode, we only can select Counter_U. + * + * @param base SCTimer peripheral base address + * @param countertoStart The SCTimer counters to enable. This is a logical OR of members of the + * enumeration ::sctimer_counter_t. */ -static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countertoStart) +static inline void SCTIMER_StartTimer(SCT_Type *base, uint32_t countertoStart) { - /* Clear HALT_L bit if counter is operating in 32-bit mode or user wants to start L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStart == kSCTIMER_Counter_L)) + switch (countertoStart) { - base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); - } - else - { - /* Start H counter */ - base->CTRL &= ~(SCT_CTRL_HALT_H_MASK); + case (uint32_t)kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L bit when user wants to start the Low counter */ + base->CTRL_ACCESS16BIT.CTRLL &= ~((uint16_t)SCT_CTRLL_HALT_L_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_H bit when user wants to start the High counter */ + base->CTRL_ACCESS16BIT.CTRLH &= ~((uint16_t)SCT_CTRLH_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ + base->CTRL &= ~(SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ + base->CTRL &= ~(SCT_CTRL_HALT_L_MASK); + break; + + default: + /* Counter_L/Counter_H can't work together with Counter_U. */ + assert(false); + break; } } @@ -497,20 +539,41 @@ static inline void SCTIMER_StartTimer(SCT_Type *base, sctimer_counter_t countert * @brief Halts the SCTimer counter. * * @param base SCTimer peripheral base address - * @param countertoStop SCTimer counter to stop; if unify mode is set then function always - * writes to HALT_L bit + * @param countertoStop The SCTimer counters to stop. This is a logical OR of members of the + * enumeration ::sctimer_counter_t. */ -static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t countertoStop) +static inline void SCTIMER_StopTimer(SCT_Type *base, uint32_t countertoStop) { - /* Set HALT_L bit if counter is operating in 32-bit mode or user wants to stop L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (countertoStop == kSCTIMER_Counter_L)) + switch (countertoStop) { - base->CTRL |= (SCT_CTRL_HALT_L_MASK); - } - else - { - /* Stop H counter */ - base->CTRL |= (SCT_CTRL_HALT_H_MASK); + case (uint32_t)kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Set HALT_L bit when user wants to start the Low counter */ + base->CTRL_ACCESS16BIT.CTRLL |= (SCT_CTRLL_HALT_L_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Set HALT_H bit when user wants to start the High counter */ + base->CTRL_ACCESS16BIT.CTRLH |= (SCT_CTRLH_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_L | (uint32_t)kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Clear HALT_L/HALT_H bit when user wants to H counter and L counter at same time */ + base->CTRL |= (SCT_CTRL_HALT_L_MASK | SCT_CTRL_HALT_H_MASK); + break; + + case (uint32_t)kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Set HALT_L bit when the counter is operating in 32-bit mode (unify counter). */ + base->CTRL |= (SCT_CTRL_HALT_L_MASK); + break; + + default: + /* Counter_L/Counter_H can't work together with Counter_U. */ + assert(false); + break; } } @@ -535,9 +598,9 @@ static inline void SCTIMER_StopTimer(SCT_Type *base, sctimer_counter_t counterto * @param howToMonitor Event type; options are available in the enumeration ::sctimer_interrupt_enable_t * @param matchValue The match value that will be programmed to a match register * @param whichIO The input or output that will be involved in event triggering. This field - * is ignored if the event type is "match only" - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as we have only 1 unified counter; hence ignored. + * is ignored if the event type is "match only" + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. * @param event Pointer to a variable where the new event number is stored * * @return kStatus_Success on success @@ -589,6 +652,94 @@ status_t SCTIMER_IncreaseState(SCT_Type *base); */ uint32_t SCTIMER_GetCurrentState(SCT_Type *base); +/*! + * @brief Set the counter current state. + * + * The function is to set the state variable bit field of STATE register. Writing to the STATE_L, STATE_H, or unified + * register is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param state The counter current state number (only support range from 0~31). + */ +static inline void SCTIMER_SetCounterState(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t state) +{ + /* SCT only support 0 ~ FSL_FEATURE_SCT_NUMBER_OF_STATES state value. */ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + + SCTIMER_StopTimer(base, (uint32_t)whichCounter); + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when user wants to setup the Low counter */ + base->STATE_ACCESS16BIT.STATEL = SCT_STATEL_STATEL(state); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_H bits when user wants to start the High counter */ + base->STATE_ACCESS16BIT.STATEH = SCT_STATEH_STATEH(state); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ + base->STATE = SCT_STATE_STATE_L(state); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + SCTIMER_StartTimer(base, (uint32_t)whichCounter); +} + +/*! + * @brief Get the counter current state value. + * + * The function is to get the state variable bit field of STATE register. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @return The the counter current state value. + */ +static inline uint16_t SCTIMER_GetCounterState(SCT_Type *base, sctimer_counter_t whichCounter) +{ + uint16_t regs; + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when user wants to setup the Low counter */ + regs = base->STATE_ACCESS16BIT.STATEL & SCT_STATEL_STATEL_MASK; + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_H bits when user wants to start the High counter */ + regs = base->STATE_ACCESS16BIT.STATEH & SCT_STATEH_STATEH_MASK; + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use STATE_L bits when counter is operating in 32-bit mode (unify counter). */ + regs = (uint16_t)(base->STATE & SCT_STATE_STATE_L_MASK); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + return regs; +} + /*! @}*/ /*! @@ -600,10 +751,10 @@ uint32_t SCTIMER_GetCurrentState(SCT_Type *base); * @brief Setup capture of the counter value on trigger of a selected event * * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. * @param captureRegister Pointer to a variable where the capture register number will be returned. User - * can read the captured value from this register when the specified event is triggered. + * can read the captured value from this register when the specified event is triggered. * @param event Event number that will trigger the capture * * @return kStatus_Success on success @@ -627,8 +778,71 @@ status_t SCTIMER_SetupCaptureAction(SCT_Type *base, void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint32_t event); +/*! + * @brief Change the load method of transition to the specified state. + * + * Change the load method of transition, it will be triggered by the event number that is passed in by the user. + * + * @param base SCTimer peripheral base address + * @param event Event number that will change the method to trigger the state transition + * @param fgLoad The method to load highest-numbered event occurring for that state to the STATE register. + * - true: Load the STATEV value to STATE when the event occurs to be the next state. + * - false: Add the STATEV value to STATE when the event occurs to be the next state. + */ +static inline void SCTIMER_SetupStateLdMethodAction(SCT_Type *base, uint32_t event, bool fgLoad) +{ + uint32_t reg = base->EV[event].CTRL; + + if (fgLoad) + { + /* Load the STATEV value to STATE when the event occurs to be the next state */ + reg |= SCT_EV_CTRL_STATELD_MASK; + } + else + { + /* Add the STATEV value to STATE when the event occurs to be the next state */ + reg &= ~SCT_EV_CTRL_STATELD_MASK; + } + + base->EV[event].CTRL = reg; +} + +/*! + * @brief Transition to the specified state with Load method. + * + * This transition will be triggered by the event number that is passed in by the user, the method decide how to load + * the highest-numbered event occurring for that state to the STATE register. + * + * @param base SCTimer peripheral base address + * @param nextState The next state SCTimer will transition to + * @param event Event number that will trigger the state transition + * @param fgLoad The method to load the highest-numbered event occurring for that state to the STATE register. + * - true: Load the STATEV value to STATE when the event occurs to be the next state. + * - false: Add the STATEV value to STATE when the event occurs to be the next state. + */ +static inline void SCTIMER_SetupNextStateActionwithLdMethod(SCT_Type *base, + uint32_t nextState, + uint32_t event, + bool fgLoad) +{ + uint32_t reg = base->EV[event].CTRL; + + reg &= ~(SCT_EV_CTRL_STATEV_MASK | SCT_EV_CTRL_STATELD_MASK); + + reg |= SCT_EV_CTRL_STATEV(nextState); + + if (fgLoad) + { + /* Load the STATEV value when the event occurs to be the next state */ + reg |= SCT_EV_CTRL_STATELD_MASK; + } + + base->EV[event].CTRL = reg; +} + /*! * @brief Transition to the specified state. + * @deprecated Do not use this function. It has been superceded by @ref SCTIMER_SetupNextStateActionwithLdMethod * * This transition will be triggered by the event number that is passed in by the user. * @@ -638,13 +852,33 @@ void SCTIMER_SetCallback(SCT_Type *base, sctimer_event_callback_t callback, uint */ static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextState, uint32_t event) { - uint32_t reg = base->EVENT[event].CTRL; + uint32_t reg = base->EV[event].CTRL; - reg &= ~(SCT_EVENT_CTRL_STATEV_MASK); + reg &= ~(SCT_EV_CTRL_STATEV_MASK); /* Load the STATEV value when the event occurs to be the next state */ - reg |= SCT_EVENT_CTRL_STATEV(nextState) | SCT_EVENT_CTRL_STATELD_MASK; + reg |= SCT_EV_CTRL_STATEV(nextState) | SCT_EV_CTRL_STATELD_MASK; - base->EVENT[event].CTRL = reg; + base->EV[event].CTRL = reg; +} + +/*! + * @brief Setup event active direction when the counters are operating in BIDIR mode. + * + * @param base SCTimer peripheral base address + * @param activeDirection Event generation active direction, see @ref sctimer_event_active_direction_t. + * @param event Event number that need setup the active direction. + */ +static inline void SCTIMER_SetupEventActiveDirection(SCT_Type *base, + sctimer_event_active_direction_t activeDirection, + uint32_t event) +{ + uint32_t reg = base->EV[event].CTRL; + + reg &= ~(SCT_EV_CTRL_DIRECTION_MASK); + + reg |= SCT_EV_CTRL_DIRECTION(activeDirection); + + base->EV[event].CTRL = reg; } /*! @@ -658,9 +892,9 @@ static inline void SCTIMER_SetupNextStateAction(SCT_Type *base, uint32_t nextSta */ static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO, uint32_t event) { - assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - base->OUT[whichIO].SET |= (1U << event); + base->OUT[whichIO].SET |= (1UL << event); } /*! @@ -674,9 +908,9 @@ static inline void SCTIMER_SetupOutputSetAction(SCT_Type *base, uint32_t whichIO */ static inline void SCTIMER_SetupOutputClearAction(SCT_Type *base, uint32_t whichIO, uint32_t event) { - assert(whichIO < FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); + assert(whichIO < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS); - base->OUT[whichIO].CLR |= (1U << event); + base->OUT[whichIO].CLR |= (1UL << event); } /*! @@ -696,20 +930,35 @@ void SCTIMER_SetupOutputToggleAction(SCT_Type *base, uint32_t whichIO, uint32_t * The counter is limited when the event number that is passed in by the user is triggered. * * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. * @param event Event number that will trigger the counter to be limited */ static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) { - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + switch (whichCounter) { - base->LIMIT |= SCT_LIMIT_LIMMSK_L(1U << event); - } - else - { - base->LIMIT |= SCT_LIMIT_LIMMSK_H(1U << event); + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->LIMIT_ACCESS16BIT.LIMITL |= SCT_LIMITL_LIMITL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->LIMIT_ACCESS16BIT.LIMITH |= SCT_LIMITH_LIMITH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->LIMIT |= SCT_LIMIT_LIMMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; } } @@ -719,20 +968,35 @@ static inline void SCTIMER_SetupCounterLimitAction(SCT_Type *base, sctimer_count * The counter is stopped when the event number that is passed in by the user is triggered. * * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. * @param event Event number that will trigger the counter to be stopped */ static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) { - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + switch (whichCounter) { - base->STOP |= SCT_STOP_STOPMSK_L(1U << event); - } - else - { - base->STOP |= SCT_STOP_STOPMSK_H(1U << event); + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->STOP_ACCESS16BIT.STOPL |= SCT_STOPL_STOPL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->STOP_ACCESS16BIT.STOPH |= SCT_STOPH_STOPH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->STOP |= SCT_STOP_STOPMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; } } @@ -742,20 +1006,35 @@ static inline void SCTIMER_SetupCounterStopAction(SCT_Type *base, sctimer_counte * The counter will re-start when the event number that is passed in by the user is triggered. * * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. * @param event Event number that will trigger the counter to re-start */ static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) { - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + switch (whichCounter) { - base->START |= SCT_START_STARTMSK_L(1U << event); - } - else - { - base->START |= SCT_START_STARTMSK_H(1U << event); + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->START_ACCESS16BIT.STARTL |= SCT_STARTL_STARTL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->START_ACCESS16BIT.STARTH |= SCT_STARTH_STARTH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->START |= SCT_START_STARTMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; } } @@ -767,20 +1046,35 @@ static inline void SCTIMER_SetupCounterStartAction(SCT_Type *base, sctimer_count * can only be removed by calling the SCTIMER_StartTimer() function. * * @param base SCTimer peripheral base address - * @param whichCounter SCTimer counter to use when operating in 16-bit mode. In 32-bit mode, this - * field has no meaning as only the Counter_L bits are used. + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. * @param event Event number that will trigger the counter to be halted */ static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t event) { - /* Use Counter_L bits if counter is operating in 32-bit mode or user wants to setup the L counter */ - if ((base->CONFIG & SCT_CONFIG_UNIFY_MASK) || (whichCounter == kSCTIMER_Counter_L)) + switch (whichCounter) { - base->HALT |= SCT_HALT_HALTMSK_L(1U << event); - } - else - { - base->HALT |= SCT_HALT_HALTMSK_H(1U << event); + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->HALT_ACCESS16BIT.HALTL |= SCT_HALTL_HALTL(1UL << event); + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->HALT_ACCESS16BIT.HALTH |= SCT_HALTH_HALTH(1UL << event); + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->HALT |= SCT_HALT_HALTMSK_L(1UL << event); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; } } @@ -796,17 +1090,156 @@ static inline void SCTIMER_SetupCounterHaltAction(SCT_Type *base, sctimer_counte */ static inline void SCTIMER_SetupDmaTriggerAction(SCT_Type *base, uint32_t dmaNumber, uint32_t event) { - if (dmaNumber == 0) + if (dmaNumber == 0U) { - base->DMA0REQUEST |= (1U << event); + base->DMAREQ0 |= (1UL << event); } else { - base->DMA1REQUEST |= (1U << event); + base->DMAREQ1 |= (1UL << event); } } #endif /* FSL_FEATURE_SCT_HAS_NO_DMA_REQUEST */ +/*! + * @brief Set the value of counter. + * + * The function is to set the value of Count register, Writing to the COUNT_L, COUNT_H, or unified register + * is only allowed when the corresponding counter is halted (HALT bits are set to 1 in the CTRL register). + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @param value the counter value update to the COUNT register. + */ +static inline void SCTIMER_SetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter, uint32_t value) +{ + SCTIMER_StopTimer(base, (uint32_t)whichCounter); + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(value <= 0xFFFFU); + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + base->COUNT_ACCESS16BIT.COUNTL = (uint16_t)value; + break; + + case kSCTIMER_Counter_H: + assert(value <= 0xFFFFU); + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + base->COUNT_ACCESS16BIT.COUNTH = (uint16_t)value; + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + base->COUNT &= ~SCT_COUNT_CTR_L_MASK; + base->COUNT |= SCT_COUNT_CTR_L(value); + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + SCTIMER_StartTimer(base, (uint32_t)whichCounter); +} + +/*! + * @brief Get the value of counter. + * + * The function is to read the value of Count register, software can read the counter registers at any time.. + * + * @param base SCTimer peripheral base address + * @param whichCounter SCTimer counter to use. In 16-bit mode, we can select Counter_L and Counter_H, + * In 32-bit mode, we can select Counter_U. + * @return The value of counter selected. + */ +static inline uint32_t SCTIMER_GetCOUNTValue(SCT_Type *base, sctimer_counter_t whichCounter) +{ + uint32_t value; + + switch (whichCounter) + { + case kSCTIMER_Counter_L: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when user wants to setup the Low counter */ + value = base->COUNT_ACCESS16BIT.COUNTL; + break; + + case kSCTIMER_Counter_H: + assert(0U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_H bits when user wants to start the High counter */ + value = base->COUNT_ACCESS16BIT.COUNTH; + break; + + case kSCTIMER_Counter_U: + assert(1U == (base->CONFIG & SCT_CONFIG_UNIFY_MASK)); + /* Use Counter_L bits when counter is operating in 32-bit mode (unify counter). */ + value = base->COUNT; + break; + + default: + /* Fix the MISRA C-2012 issue rule 16.4. */ + break; + } + + return value; +} + +/*! + * @brief Set the state mask bit field of EV_STATE register. + * + * @param base SCTimer peripheral base address + * @param event The EV_STATE register be set. + * @param state The state value in which the event is enabled to occur. + */ +static inline void SCTIMER_SetEventInState(SCT_Type *base, uint32_t event, uint32_t state) +{ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); + + base->EV[event].STATE |= SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); +} + +/*! + * @brief Clear the state mask bit field of EV_STATE register. + * + * @param base SCTimer peripheral base address + * @param event The EV_STATE register be clear. + * @param state The state value in which the event is disabled to occur. + */ +static inline void SCTIMER_ClearEventInState(SCT_Type *base, uint32_t event, uint32_t state) +{ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); + + base->EV[event].STATE &= ~SCT_EV_STATE_STATEMSKn((uint32_t)1U << state); +} + +/*! + * @brief Get the state mask bit field of EV_STATE register. + * + * @note This function is to check whether the event is enabled in a specific state. + * + * @param base SCTimer peripheral base address + * @param event The EV_STATE register be read. + * @param state The state value. + * + * @return The the state mask bit field of EV_STATE register. + * - true: The event is enable in state. + * - false: The event is disable in state. + */ +static inline bool SCTIMER_GetEventInState(SCT_Type *base, uint32_t event, uint32_t state) +{ + assert(state < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_STATES); + assert(event < (uint32_t)FSL_FEATURE_SCT_NUMBER_OF_EVENTS); + + return (0U != (base->EV[event].STATE & SCT_EV_STATE_STATEMSKn((uint32_t)1U << state))); +} + /*! * @brief SCTimer interrupt handler. * diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.c index f00f74fc1f..ba2fbafd71 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -47,7 +47,8 @@ typedef void (*sdif_isr_t)(SDIF_Type *base, sdif_handle_t *handle); #define SDIF_RX_WATERMARK (15U) /*! @brief TX water mark value */ #define SDIF_TX_WATERMARK (16U) - +/*! @brief check flag avalibility */ +#define IS_SDIF_FLAG_SET(reg, flag) (((reg) & ((uint32_t)flag)) != 0UL) /******************************************************************************* * Prototypes ******************************************************************************/ @@ -180,6 +181,17 @@ static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle */ static status_t SDIF_SetCommandRegister(SDIF_Type *base, uint32_t cmdIndex, uint32_t argument, uint32_t timeout); +/* + * @brief SDIF sync clock command function. + * + * This function will try to recovery the host while sending clock command failed. + * + * @param base SDIF base addres + * + * @return kStatus_Success, kStatus_SDIF_SyncCmdTimeout + */ +static status_t SDIF_SyncClockCommand(SDIF_Type *base); + /******************************************************************************* * Variables ******************************************************************************/ @@ -193,7 +205,11 @@ static SDIF_Type *const s_sdifBase[] = SDIF_BASE_PTRS; static const IRQn_Type s_sdifIRQ[] = SDIF_IRQS; /* SDIF ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static sdif_isr_t s_sdifIsr = (sdif_isr_t)DefaultISR; +#else static sdif_isr_t s_sdifIsr; +#endif /******************************************************************************* * Code @@ -217,7 +233,7 @@ static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer, sdif_command_t *command = transfer->command; sdif_data_t *data = transfer->data; - if ((command == NULL) || (data && (data->blockSize > SDIF_BLKSIZ_BLOCK_SIZE_MASK))) + if ((command == NULL) || ((data != NULL) && (data->blockSize > SDIF_BLKSIZ_BLOCK_SIZE_MASK))) { return kStatus_SDIF_InvalidArgument; } @@ -230,11 +246,11 @@ static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer, /* config the byte count register */ base->BYTCNT = SDIF_BYTCNT_BYTE_COUNT(data->blockSize * data->blockCount); - command->flags |= kSDIF_DataExpect; /* need transfer data flag */ + command->flags |= (uint32_t)kSDIF_DataExpect; /* need transfer data flag */ if (data->txData != NULL) { - command->flags |= kSDIF_DataWriteToCard; /* data transfer direction */ + command->flags |= (uint32_t)kSDIF_DataWriteToCard; /* data transfer direction */ } else { @@ -251,48 +267,63 @@ static status_t SDIF_TransferConfig(SDIF_Type *base, sdif_transfer_t *transfer, if (data->streamTransfer) { - command->flags |= kSDIF_DataStreamTransfer; /* indicate if use stream transfer or block transfer */ + command->flags |= + (uint32_t)kSDIF_DataStreamTransfer; /* indicate if use stream transfer or block transfer */ } if ((data->enableAutoCommand12) && - (data->blockCount > 1U)) /* indicate if auto stop will send after the data transfer done */ + (data->blockCount > 1UL)) /* indicate if auto stop will send after the data transfer done */ { - command->flags |= kSDIF_DataTransferAutoStop; - } - - if (enDMA) - { - base->INTMASK &= ~(kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest); - } - else - { - base->INTMASK |= (kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest); + command->flags |= (uint32_t)kSDIF_DataTransferAutoStop; } } /* R2 response length long */ - if (command->responseType == kCARD_ResponseTypeR2) + if (command->responseType == (uint32_t)kCARD_ResponseTypeR2) { - command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseLengthLong | kSDIF_CmdResponseExpect); + command->flags |= ((uint32_t)kSDIF_CmdCheckResponseCRC | (uint32_t)kSDIF_CmdResponseLengthLong | + (uint32_t)kSDIF_CmdResponseExpect); } - else if ((command->responseType == kCARD_ResponseTypeR3) || (command->responseType == kCARD_ResponseTypeR4)) + else if ((command->responseType == (uint32_t)kCARD_ResponseTypeR3) || + (command->responseType == (uint32_t)kCARD_ResponseTypeR4)) { - command->flags |= kSDIF_CmdResponseExpect; /* response R3 do not check Response CRC */ + command->flags |= (uint32_t)kSDIF_CmdResponseExpect; /* response R3 do not check Response CRC */ } else { - if (command->responseType != kCARD_ResponseTypeNone) + if (command->responseType != (uint32_t)kCARD_ResponseTypeNone) { - command->flags |= (kSDIF_CmdCheckResponseCRC | kSDIF_CmdResponseExpect); + command->flags |= ((uint32_t)kSDIF_CmdCheckResponseCRC | (uint32_t)kSDIF_CmdResponseExpect); } } - if (command->type == kCARD_CommandTypeAbort) + if (command->type == (uint32_t)kCARD_CommandTypeAbort) { - command->flags |= kSDIF_TransferStopAbort; + command->flags |= (uint32_t)kSDIF_TransferStopAbort; } /* wait pre-transfer complete */ - command->flags |= kSDIF_WaitPreTransferComplete | kSDIF_CmdDataUseHoldReg; + command->flags |= (uint32_t)kSDIF_WaitPreTransferComplete | (uint32_t)kSDIF_CmdDataUseHoldReg; + + /* handle interrupt and status mask */ + if (data != NULL) + { + SDIF_ClearInterruptStatus(base, (uint32_t)kSDIF_AllInterruptStatus); + if (enDMA) + { + SDIF_ClearInternalDMAStatus(base, kSDIF_DMAAllStatus); + SDIF_EnableDmaInterrupt(base, kSDIF_DMAAllStatus); + SDIF_EnableInterrupt(base, (uint32_t)kSDIF_CommandTransferStatus); + } + else + { + SDIF_EnableInterrupt(base, (uint32_t)kSDIF_CommandTransferStatus | (uint32_t)kSDIF_DataTransferStatus); + } + } + else + { + SDIF_ClearInterruptStatus(base, kSDIF_CommandTransferStatus); + SDIF_EnableInterrupt(base, kSDIF_CommandTransferStatus); + } return kStatus_Success; } @@ -304,18 +335,19 @@ static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *comman { /* read response */ command->response[0U] = base->RESP[0U]; - if (command->responseType == kCARD_ResponseTypeR2) + if (command->responseType == (uint32_t)kCARD_ResponseTypeR2) { command->response[1U] = base->RESP[1U]; command->response[2U] = base->RESP[2U]; command->response[3U] = base->RESP[3U]; } - if ((command->responseErrorFlags != 0U) && - ((command->responseType == kCARD_ResponseTypeR1) || (command->responseType == kCARD_ResponseTypeR1b) || - (command->responseType == kCARD_ResponseTypeR6) || (command->responseType == kCARD_ResponseTypeR5))) + if ((command->responseErrorFlags != 0U) && ((command->responseType == (uint32_t)kCARD_ResponseTypeR1) || + (command->responseType == (uint32_t)kCARD_ResponseTypeR1b) || + (command->responseType == (uint32_t)kCARD_ResponseTypeR6) || + (command->responseType == (uint32_t)kCARD_ResponseTypeR5))) { - if (((command->responseErrorFlags) & (command->response[0U])) != 0U) + if (((command->responseErrorFlags) & (command->response[0U])) != 0UL) { return kStatus_SDIF_ResponseError; } @@ -327,16 +359,18 @@ static status_t SDIF_ReadCommandResponse(SDIF_Type *base, sdif_command_t *comman static status_t SDIF_WaitCommandDone(SDIF_Type *base, sdif_command_t *command) { - uint32_t status = 0U; + uint32_t status = 0U; + uint32_t errorStatus = (uint32_t)kSDIF_ResponseError | (uint32_t)kSDIF_ResponseTimeout | + (uint32_t)kSDIF_DataStartBitError | (uint32_t)kSDIF_HardwareLockError | + (uint32_t)kSDIF_ResponseCRCError; do { status = SDIF_GetInterruptStatus(base); - } while ((status & kSDIF_CommandDone) != kSDIF_CommandDone); + } while ((status & (errorStatus | (uint32_t)kSDIF_CommandDone)) == 0UL); /* clear interrupt status flag first */ - SDIF_ClearInterruptStatus(base, status & kSDIF_CommandTransferStatus); - if ((status & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout | kSDIF_HardwareLockError)) != - 0u) + SDIF_ClearInterruptStatus(base, status & (uint32_t)kSDIF_CommandTransferStatus); + if ((status & errorStatus) != 0UL) { return kStatus_SDIF_SendCmdFail; } @@ -353,14 +387,19 @@ static status_t SDIF_SetCommandRegister(SDIF_Type *base, uint32_t cmdIndex, uint base->CMDARG = argument; base->CMD = cmdIndex | SDIF_CMD_START_CMD_MASK; - while (((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK) && syncTimeout) + while ((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK) { - --syncTimeout; + if (timeout == 0U) + { + break; + } - if (!syncTimeout) + if (0UL == syncTimeout) { return kStatus_SDIF_SyncCmdTimeout; } + + --syncTimeout; } return kStatus_Success; @@ -379,15 +418,15 @@ status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig sdif_dma_descriptor_t *dmaDesAddr; uint32_t *tempDMADesBuffer = dmaConfig->dmaDesBufferStartAddr; - uint32_t dmaDesBufferSize = 0U; + uint32_t dmaDesBufferSize = 0UL; - dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer; + dmaDesAddr = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; /* chain descriptor mode */ if (dmaConfig->mode == kSDIF_ChainDMAMode) { - while (((dmaDesAddr->dmaDesAttribute & SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG) != - SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG) && + while (((dmaDesAddr->dmaDesAttribute & SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) != + SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) && (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) { /* set the OWN bit */ @@ -405,11 +444,11 @@ status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig /* dual descriptor mode */ else { - while (((dmaDesAddr->dmaDesAttribute & SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG) != - SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG) && + while (((dmaDesAddr->dmaDesAttribute & SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) != + SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG) && (dmaDesBufferSize < dmaConfig->dmaDesBufferLen * sizeof(uint32_t))) { - dmaDesAddr = (sdif_dma_descriptor_t *)tempDMADesBuffer; + dmaDesAddr = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; dmaDesAddr->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG; tempDMADesBuffer += dmaConfig->dmaDesSkipLen; } @@ -433,7 +472,7 @@ static uint32_t SDIF_ReadDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t t uint32_t wordsCanBeRead; /* The words can be read at this time. */ uint32_t readWatermark = ((base->FIFOTH & SDIF_FIFOTH_RX_WMARK_MASK) >> SDIF_FIFOTH_RX_WMARK_SHIFT); - if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0U) + if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0UL) { if (data->blockSize % sizeof(uint32_t) != 0U) { @@ -480,7 +519,7 @@ static uint32_t SDIF_WriteDataPort(SDIF_Type *base, sdif_data_t *data, uint32_t uint32_t wordsCanBeWrite; /* The words can be read at this time. */ uint32_t writeWatermark = ((base->FIFOTH & SDIF_FIFOTH_TX_WMARK_MASK) >> SDIF_FIFOTH_TX_WMARK_SHIFT); - if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0U) + if ((base->CTRL & SDIF_CTRL_USE_INTERNAL_DMAC_MASK) == 0UL) { if (data->blockSize % sizeof(uint32_t) != 0U) { @@ -528,7 +567,7 @@ static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data) uint32_t status; bool transferOver = false; - if (data->blockSize % sizeof(uint32_t) != 0U) + if (data->blockSize % sizeof(uint32_t) != 0UL) { data->blockSize += sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ @@ -542,7 +581,7 @@ static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data) do { status = SDIF_GetInterruptStatus(base); - if (status & kSDIF_DataTransferError) + if (IS_SDIF_FLAG_SET(status, kSDIF_DataTransferError)) { if (!(data->enableIgnoreError)) { @@ -550,9 +589,10 @@ static status_t SDIF_ReadDataPortBlocking(SDIF_Type *base, sdif_data_t *data) break; } } - } while (((status & (kSDIF_DataTransferOver | kSDIF_ReadFIFORequest)) == 0U) && (!transferOver)); + } while (!IS_SDIF_FLAG_SET(status, ((uint32_t)kSDIF_DataTransferOver | (uint32_t)kSDIF_ReadFIFORequest)) && + (!transferOver)); - if ((status & kSDIF_DataTransferOver) == kSDIF_DataTransferOver) + if (IS_SDIF_FLAG_SET(status, kSDIF_DataTransferOver)) { transferOver = true; } @@ -576,7 +616,7 @@ static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data) status_t error = kStatus_Success; uint32_t status; - if (data->blockSize % sizeof(uint32_t) != 0U) + if (data->blockSize % sizeof(uint32_t) != 0UL) { data->blockSize += sizeof(uint32_t) - (data->blockSize % sizeof(uint32_t)); /* make the block size as word-aligned */ @@ -590,14 +630,14 @@ static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data) do { status = SDIF_GetInterruptStatus(base); - if (status & kSDIF_DataTransferError) + if (IS_SDIF_FLAG_SET(status, kSDIF_DataTransferError)) { if (!(data->enableIgnoreError)) { error = kStatus_Fail; } } - } while ((status & kSDIF_WriteFIFORequest) == 0U); + } while (!(IS_SDIF_FLAG_SET(status, kSDIF_WriteFIFORequest))); if (error == kStatus_Success) { @@ -608,18 +648,18 @@ static status_t SDIF_WriteDataPortBlocking(SDIF_Type *base, sdif_data_t *data) SDIF_ClearInterruptStatus(base, status); } - while ((SDIF_GetInterruptStatus(base) & kSDIF_DataTransferOver) != kSDIF_DataTransferOver) + while ((SDIF_GetInterruptStatus(base) & (uint32_t)kSDIF_DataTransferOver) != (uint32_t)kSDIF_DataTransferOver) { } - if (SDIF_GetInterruptStatus(base) & kSDIF_DataTransferError) + if (IS_SDIF_FLAG_SET(SDIF_GetInterruptStatus(base), kSDIF_DataTransferError)) { if (!(data->enableIgnoreError)) { error = kStatus_Fail; } } - SDIF_ClearInterruptStatus(base, (kSDIF_DataTransferOver | kSDIF_DataTransferError)); + SDIF_ClearInterruptStatus(base, ((uint32_t)kSDIF_DataTransferOver | (uint32_t)kSDIF_DataTransferError)); return error; } @@ -636,30 +676,30 @@ bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout) /* reset through CTRL */ base->CTRL |= mask; /* DMA software reset */ - if (mask & kSDIF_ResetDMAInterface) + if (IS_SDIF_FLAG_SET(mask, kSDIF_ResetDMAInterface)) { /* disable DMA first then do DMA software reset */ base->BMOD = (base->BMOD & (~SDIF_BMOD_DE_MASK)) | SDIF_BMOD_SWR_MASK; } /* check software DMA reset here for DMA reset also need to check this bit */ - while ((base->CTRL & mask) != 0U) + while ((base->CTRL & mask) != 0UL) { - if (!timeout) + if (0UL == timeout) { break; } timeout--; } - return timeout ? true : false; + return timeout != 0UL ? true : false; } static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bool isDMA) { assert(NULL != data); - uint32_t dmaStatus = 0U; + uint32_t dmaStatus = 0UL; status_t error = kStatus_Success; /* in DMA mode, only need to wait the complete flag and check error */ @@ -668,15 +708,17 @@ static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bo do { dmaStatus = SDIF_GetInternalDMAStatus(base); - if ((dmaStatus & kSDIF_DMAFatalBusError) == kSDIF_DMAFatalBusError) + if (IS_SDIF_FLAG_SET(dmaStatus, (uint32_t)kSDIF_DMAFatalBusError)) { - SDIF_ClearInternalDMAStatus(base, kSDIF_DMAFatalBusError | kSDIF_AbnormalInterruptSummary); + SDIF_ClearInternalDMAStatus( + base, (uint32_t)kSDIF_DMAFatalBusError | (uint32_t)kSDIF_AbnormalInterruptSummary); error = kStatus_SDIF_DMATransferFailWithFBE; /* in this condition,need reset */ } /* Card error summary, include EBE,SBE,Data CRC,RTO,DRTO,Response error */ - if ((dmaStatus & kSDIF_DMACardErrorSummary) == kSDIF_DMACardErrorSummary) + if (IS_SDIF_FLAG_SET(dmaStatus, (uint32_t)kSDIF_DMACardErrorSummary)) { - SDIF_ClearInternalDMAStatus(base, kSDIF_DMACardErrorSummary | kSDIF_AbnormalInterruptSummary); + SDIF_ClearInternalDMAStatus( + base, (uint32_t)kSDIF_DMACardErrorSummary | (uint32_t)kSDIF_AbnormalInterruptSummary); if (!(data->enableIgnoreError)) { error = kStatus_SDIF_DataTransferFail; @@ -685,27 +727,42 @@ static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bo /* if error occur, then return */ break; } - } while ((dmaStatus & (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor)) == 0U); + } while (!(IS_SDIF_FLAG_SET( + dmaStatus, ((uint32_t)kSDIF_DMATransFinishOneDescriptor | (uint32_t)kSDIF_DMARecvFinishOneDescriptor)))); /* clear the corresponding status bit */ - SDIF_ClearInternalDMAStatus(base, (kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | - kSDIF_NormalInterruptSummary)); + SDIF_ClearInternalDMAStatus( + base, ((uint32_t)kSDIF_DMATransFinishOneDescriptor | (uint32_t)kSDIF_DMARecvFinishOneDescriptor | + (uint32_t)kSDIF_NormalInterruptSummary)); SDIF_ClearInterruptStatus(base, SDIF_GetInterruptStatus(base)); + + if (error != kStatus_Success) + { + return kStatus_SDIF_DataTransferFail; + } } else { if (data->rxData != NULL) { error = SDIF_ReadDataPortBlocking(base, data); + if (error != kStatus_Success) + { + return kStatus_SDIF_DataTransferFail; + } } else { error = SDIF_WriteDataPortBlocking(base, data); + if (error != kStatus_Success) + { + return kStatus_SDIF_DataTransferFail; + } } } - return error; + return kStatus_Success; } /*! @@ -714,23 +771,16 @@ static status_t SDIF_TransferDataBlocking(SDIF_Type *base, sdif_data_t *data, bo * This api include polling the status of the bit START_COMMAND, if 0 used as timeout value, then this function * will return directly without polling the START_CMD status. * param base SDIF peripheral base address. - * param command configuration collection - * param timeout not used in this function + * param command configuration collection. + * param timeout the timeout value of polling START_CMD auto clear status. * return command excute status */ status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout) { assert(NULL != cmd); - base->CMDARG = cmd->argument; - base->CMD = SDIF_CMD_CMD_INDEX(cmd->index) | SDIF_CMD_START_CMD_MASK | (cmd->flags & (~SDIF_CMD_CMD_INDEX_MASK)); - - /* wait start_cmd bit auto clear within timeout */ - while ((base->CMD & SDIF_CMD_START_CMD_MASK) == SDIF_CMD_START_CMD_MASK) - { - } - - return kStatus_Success; + return SDIF_SetCommandRegister(base, SDIF_CMD_CMD_INDEX(cmd->index) | (cmd->flags & (~SDIF_CMD_CMD_INDEX_MASK)), + cmd->argument, timeout); } /*! @@ -748,20 +798,23 @@ bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout) enINT = true; base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; } + SDIF_ClearInterruptStatus(base, kSDIF_CommandDone); + SDIF_EnableInterrupt(base, kSDIF_CommandDone); /* send initialization command */ - if (SDIF_SetCommandRegister(base, SDIF_CMD_SEND_INITIALIZATION_MASK, 0U, timeout) != kStatus_Success) + if (SDIF_SetCommandRegister(base, SDIF_CMD_SEND_INITIALIZATION_MASK, 0UL, timeout) != kStatus_Success) { return false; } /* wait command done */ - while ((SDIF_GetInterruptStatus(base) & kSDIF_CommandDone) != kSDIF_CommandDone) + while ((SDIF_GetInterruptStatus(base) & (uint32_t)kSDIF_CommandDone) != (uint32_t)kSDIF_CommandDone) { } /* clear status */ SDIF_ClearInterruptStatus(base, kSDIF_CommandDone); + SDIF_DisableInterrupt(base, kSDIF_CommandDone); /* add for conflict with interrupt mode */ if (enINT) @@ -785,6 +838,10 @@ void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider) { uint32_t sdioClkCtrl = SYSCON->SDIOCLKCTRL; + sdioClkCtrl = SYSCON->SDIOCLKCTRL & + (~(SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK | + SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK | SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)); + if (target_HZ >= SDIF_CLOCK_RANGE_NEED_DELAY) { #ifdef SDIF_HIGHSPEED_SAMPLE_DELAY @@ -811,6 +868,35 @@ void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider) SYSCON->SDIOCLKCTRL = sdioClkCtrl; } +static status_t SDIF_SyncClockCommand(SDIF_Type *base) +{ + uint32_t syncTimeout = 10000U; + uint32_t sendCommandRetry = 3U; + + do + { + /* update the clock register and wait the pre-transfer complete */ + if (SDIF_SetCommandRegister( + base, (uint32_t)kSDIF_CmdUpdateClockRegisterOnly | (uint32_t)kSDIF_WaitPreTransferComplete, 0UL, + syncTimeout) == kStatus_Success) + { + break; + } + /* if send clock command timeout, it means that polling START_CMD cleared failed, CIU cannot take command at + * this comment, so reset the host controller to recover the CIU interface and state machine. + */ + (void)SDIF_Reset(base, kSDIF_ResetController, syncTimeout); + sendCommandRetry--; + } while (sendCommandRetry != 0U); + + if (sendCommandRetry == 0U) + { + return kStatus_Fail; + } + + return kStatus_Success; +} + /*! * brief Sets the card bus clock frequency. * @@ -821,8 +907,7 @@ void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider) */ uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ) { - uint32_t divider = 0U, targetFreq = target_HZ; - uint32_t syncTimeout = SDIF_TIMEOUT_VALUE; + uint32_t divider = 0UL, targetFreq = target_HZ; /* if target freq bigger than the source clk, set the target_HZ to src clk, this interface can run up to 52MHZ with card */ @@ -833,9 +918,8 @@ uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t targe /* disable the clock first,need sync to CIU*/ SDIF_EnableCardClock(base, false); - /* update the clock register and wait the pre-transfer complete */ - if (SDIF_SetCommandRegister(base, kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete, 0U, - syncTimeout) != kStatus_Success) + + if (SDIF_SyncClockCommand(base) != kStatus_Success) { return 0U; } @@ -843,30 +927,39 @@ uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t targe /*calculate the divider*/ if (targetFreq != srcClock_Hz) { - divider = (srcClock_Hz / targetFreq + 1U) / 2U; + divider = srcClock_Hz / targetFreq; + while (srcClock_Hz / divider > targetFreq) + { + divider++; + } + + if (divider > (SDIF_CLKDIV_CLK_DIVIDER0_MASK * 2UL)) + { + /* Note: if assert occur here, it means that the source clock frequency is too high, the suggestion is + * reconfigure the SDIF divider in SYSCON to get a properly source clock */ + assert(false); + divider = (SDIF_CLKDIV_CLK_DIVIDER0_MASK * 2UL); + } + + divider = (divider + 1UL) / 2UL; } /* load the clock divider */ base->CLKDIV = SDIF_CLKDIV_CLK_DIVIDER0(divider); /* update the divider to CIU */ - if (SDIF_SetCommandRegister(base, kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete, 0U, - syncTimeout) != kStatus_Success) + if (SDIF_SyncClockCommand(base) != kStatus_Success) { return 0U; } /* enable the card clock and sync to CIU */ SDIF_EnableCardClock(base, true); - if (SDIF_SetCommandRegister(base, kSDIF_CmdUpdateClockRegisterOnly | kSDIF_WaitPreTransferComplete, 0U, - syncTimeout) != kStatus_Success) - { - return 0U; - } + (void)SDIF_SyncClockCommand(base); /* config the clock delay to meet the hold time and setup time */ SDIF_ConfigClockDelay(target_HZ, divider); /* return the actual card clock freq */ - return (divider != 0U) ? (srcClock_Hz / (divider * 2U)) : srcClock_Hz; + return (divider != 0UL) ? (srcClock_Hz / (divider * 2UL)) : srcClock_Hz; } /*! @@ -885,14 +978,14 @@ bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout) /* polling the bit self clear */ while ((base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK) == SDIF_CTRL_ABORT_READ_DATA_MASK) { - if (!timeout) + if (0UL == timeout) { break; } timeout--; } - return base->CTRL & SDIF_CTRL_ABORT_READ_DATA_MASK ? false : true; + return IS_SDIF_FLAG_SET(base->CTRL, SDIF_CTRL_ABORT_READ_DATA_MASK) ? false : true; } /*! @@ -907,20 +1000,20 @@ status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, cons assert(NULL != config); assert(NULL != data); - uint32_t dmaEntry = 0U, i, dmaBufferSize = 0U, dmaBuffer1Size = 0U; + uint32_t dmaEntry = 0UL, i, dmaBufferSize = 0UL, dmaBuffer1Size = 0UL; uint32_t *tempDMADesBuffer = config->dmaDesBufferStartAddr; const uint32_t *dataBuffer = data; sdif_dma_descriptor_t *descriptorPoniter = NULL; - uint32_t maxDMABuffer = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE * (config->mode); + uint32_t maxDMABuffer = (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE * ((uint32_t)config->mode); - if ((((uint32_t)data % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0U) || - (((uint32_t)tempDMADesBuffer % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0U)) + if ((((uint32_t)data % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0UL) || + (((uint32_t)tempDMADesBuffer % SDIF_INTERNAL_DMA_ADDR_ALIGN) != 0UL)) { return kStatus_SDIF_DMAAddrNotAlign; } /* check the read/write data size,must be a multiple of 4 */ - if (dataSize % sizeof(uint32_t) != 0U) + if (dataSize % sizeof(uint32_t) != 0UL) { dataSize += sizeof(uint32_t) - (dataSize % sizeof(uint32_t)); } @@ -935,11 +1028,11 @@ status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, cons /* if data size smaller than one descriptor buffer size */ if (dataSize > maxDMABuffer) { - dmaEntry = dataSize / maxDMABuffer + (dataSize % maxDMABuffer ? 1U : 0U); + dmaEntry = dataSize / maxDMABuffer + ((dataSize % maxDMABuffer) != 0UL ? 1UL : 0UL); } else /* need one dma descriptor */ { - dmaEntry = 1U; + dmaEntry = 1UL; } /* check the DMA descriptor buffer len one more time,it is user's responsibility to make sure the DMA descriptor @@ -950,95 +1043,98 @@ status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, cons return kStatus_SDIF_DescriptorBufferLenError; } - switch (config->mode) + if (config->mode == kSDIF_DualDMAMode) { - case kSDIF_DualDMAMode: - base->BMOD |= SDIF_BMOD_DSL(config->dmaDesSkipLen); /* config the distance between the DMA descriptor */ - for (i = 0U; i < dmaEntry; i++) + base->BMOD |= SDIF_BMOD_DSL(config->dmaDesSkipLen); /* config the distance between the DMA descriptor */ + for (i = 0UL; i < dmaEntry; i++) + { + if (dataSize > (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) { - if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) - { - dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - dataSize -= dmaBufferSize; - dmaBuffer1Size = dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE ? - FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE : - dataSize; - dataSize -= dmaBuffer1Size; - } - else - { - dmaBufferSize = dataSize; - dmaBuffer1Size = 0U; - } + dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; + dataSize -= dmaBufferSize; + dmaBuffer1Size = dataSize > (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE ? + (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE : + dataSize; + dataSize -= dmaBuffer1Size; + } + else + { + dmaBufferSize = dataSize; + dmaBuffer1Size = 0UL; + } - descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer; - if (i == 0U) - { - descriptorPoniter->dmaDesAttribute = SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG; - } - descriptorPoniter->dmaDesAttribute |= + descriptorPoniter = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; + if (i == 0UL) + { + descriptorPoniter->dmaDesAttribute = SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG | + SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | + SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; + } + else + { + descriptorPoniter->dmaDesAttribute = SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - descriptorPoniter->dmaDataBufferSize = - SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize) | SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(dmaBuffer1Size); - - descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; - descriptorPoniter->dmaDataBufferAddr1 = dataBuffer + dmaBufferSize / sizeof(uint32_t); - dataBuffer += (dmaBufferSize + dmaBuffer1Size) / sizeof(uint32_t); - - /* descriptor skip length */ - tempDMADesBuffer += config->dmaDesSkipLen + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); } - /* enable the completion interrupt when reach the last descriptor */ - descriptorPoniter->dmaDesAttribute &= ~SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - descriptorPoniter->dmaDesAttribute |= - SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG | SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG; - break; + descriptorPoniter->dmaDataBufferSize = + SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize) | SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(dmaBuffer1Size); - case kSDIF_ChainDMAMode: - for (i = 0U; i < dmaEntry; i++) + descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; + descriptorPoniter->dmaDataBufferAddr1 = dataBuffer + dmaBufferSize / sizeof(uint32_t); + dataBuffer += (dmaBufferSize + dmaBuffer1Size) / sizeof(uint32_t); + + /* descriptor skip length */ + tempDMADesBuffer += config->dmaDesSkipLen + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); + } + /* enable the completion interrupt when reach the last descriptor */ + descriptorPoniter->dmaDesAttribute &= ~SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; + descriptorPoniter->dmaDesAttribute |= + SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG | SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG; + } + else + { + for (i = 0UL; i < dmaEntry; i++) + { + if (dataSize > (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) { - if (dataSize > FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE) - { - dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - dataSize -= FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; - } - else - { - dmaBufferSize = dataSize; - } - - descriptorPoniter = (sdif_dma_descriptor_t *)tempDMADesBuffer; - if (i == 0U) - { - descriptorPoniter->dmaDesAttribute = SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG; - } - descriptorPoniter->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | - SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG | - SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - descriptorPoniter->dmaDataBufferSize = - SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize); /* use only buffer 1 for data buffer*/ - descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; - dataBuffer += dmaBufferSize / sizeof(uint32_t); - tempDMADesBuffer += - sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); /* calculate the next descriptor address */ - /* this descriptor buffer2 pointer to the next descriptor address */ - descriptorPoniter->dmaDataBufferAddr1 = tempDMADesBuffer; + dmaBufferSize = FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; + dataSize -= (uint32_t)FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE; + } + else + { + dmaBufferSize = dataSize; } - /* enable the completion interrupt when reach the last descriptor */ - descriptorPoniter->dmaDesAttribute &= ~SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; - descriptorPoniter->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG; - break; - default: - break; + descriptorPoniter = (sdif_dma_descriptor_t *)(uint32_t)tempDMADesBuffer; + if (i == 0UL) + { + descriptorPoniter->dmaDesAttribute = + SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG | SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | + SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG | SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; + } + else + { + descriptorPoniter->dmaDesAttribute = SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG | + SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG | + SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; + } + descriptorPoniter->dmaDataBufferSize = + SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(dmaBufferSize); /* use only buffer 1 for data buffer*/ + descriptorPoniter->dmaDataBufferAddr0 = dataBuffer; + dataBuffer += dmaBufferSize / sizeof(uint32_t); + tempDMADesBuffer += + sizeof(sdif_dma_descriptor_t) / sizeof(uint32_t); /* calculate the next descriptor address */ + /* this descriptor buffer2 pointer to the next descriptor address */ + descriptorPoniter->dmaDataBufferAddr1 = tempDMADesBuffer; + } + /* enable the completion interrupt when reach the last descriptor */ + descriptorPoniter->dmaDesAttribute &= ~SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG; + descriptorPoniter->dmaDesAttribute |= SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG; } /* use internal DMA interface */ base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK; /* enable the internal SD/MMC DMA */ base->BMOD |= SDIF_BMOD_DE_MASK; - /* enable DMA status check */ - base->IDINTEN |= kSDIF_DMAAllStatus; /* load DMA descriptor buffer address */ base->DBADDR = (uint32_t)config->dmaDesBufferStartAddr; @@ -1053,19 +1149,17 @@ status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, cons */ void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) { - switch (type) + if (type == kSDIF_Bus1BitWidth) { - case kSDIF_Bus1BitWidth: - base->CTYPE &= ~(SDIF_CTYPE_CARD0_WIDTH0_MASK | SDIF_CTYPE_CARD0_WIDTH1_MASK); - break; - case kSDIF_Bus4BitWidth: - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD0_WIDTH1_MASK)) | SDIF_CTYPE_CARD0_WIDTH0_MASK; - break; - case kSDIF_Bus8BitWidth: - base->CTYPE |= SDIF_CTYPE_CARD0_WIDTH1_MASK; - break; - default: - break; + base->CTYPE &= ~(SDIF_CTYPE_CARD0_WIDTH0_MASK | SDIF_CTYPE_CARD0_WIDTH1_MASK); + } + else if (type == kSDIF_Bus4BitWidth) + { + base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD0_WIDTH1_MASK)) | SDIF_CTYPE_CARD0_WIDTH0_MASK; + } + else + { + base->CTYPE |= SDIF_CTYPE_CARD0_WIDTH1_MASK; } } @@ -1076,19 +1170,17 @@ void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) */ void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type) { - switch (type) + if (type == kSDIF_Bus1BitWidth) { - case kSDIF_Bus1BitWidth: - base->CTYPE &= ~(SDIF_CTYPE_CARD1_WIDTH0_MASK | SDIF_CTYPE_CARD1_WIDTH1_MASK); - break; - case kSDIF_Bus4BitWidth: - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD1_WIDTH1_MASK)) | SDIF_CTYPE_CARD1_WIDTH0_MASK; - break; - case kSDIF_Bus8BitWidth: - base->CTYPE |= SDIF_CTYPE_CARD1_WIDTH1_MASK; - break; - default: - break; + base->CTYPE &= ~(SDIF_CTYPE_CARD1_WIDTH0_MASK | SDIF_CTYPE_CARD1_WIDTH1_MASK); + } + else if (type == kSDIF_Bus4BitWidth) + { + base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD1_WIDTH1_MASK)) | SDIF_CTYPE_CARD1_WIDTH0_MASK; + } + else + { + base->CTYPE |= SDIF_CTYPE_CARD1_WIDTH1_MASK; } } #else @@ -1099,19 +1191,17 @@ void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type) */ void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) { - switch (type) + if (type == kSDIF_Bus1BitWidth) { - case kSDIF_Bus1BitWidth: - base->CTYPE &= ~(SDIF_CTYPE_CARD_WIDTH0_MASK | SDIF_CTYPE_CARD_WIDTH1_MASK); - break; - case kSDIF_Bus4BitWidth: - base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD_WIDTH1_MASK)) | SDIF_CTYPE_CARD_WIDTH0_MASK; - break; - case kSDIF_Bus8BitWidth: - base->CTYPE |= SDIF_CTYPE_CARD_WIDTH1_MASK; - break; - default: - break; + base->CTYPE &= ~(SDIF_CTYPE_CARD_WIDTH0_MASK | SDIF_CTYPE_CARD_WIDTH1_MASK); + } + else if (type == kSDIF_Bus4BitWidth) + { + base->CTYPE = (base->CTYPE & (~SDIF_CTYPE_CARD_WIDTH1_MASK)) | SDIF_CTYPE_CARD_WIDTH0_MASK; + } + else + { + base->CTYPE |= SDIF_CTYPE_CARD_WIDTH1_MASK; } } #endif @@ -1148,8 +1238,8 @@ void SDIF_Init(SDIF_Type *base, sdif_config_t *config) base->FIFOTH = SDIF_FIFOTH_TX_WMARK(SDIF_TX_WATERMARK) | SDIF_FIFOTH_RX_WMARK(SDIF_RX_WATERMARK) | SDIF_FIFOTH_DMA_MTS(1U); - /* enable the interrupt status */ - SDIF_EnableInterrupt(base, kSDIF_AllInterruptStatus); + /* disable all the interrupt */ + SDIF_DisableInterrupt(base, kSDIF_AllInterruptStatus); /* clear all interrupt/DMA status */ SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); @@ -1177,7 +1267,7 @@ status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sd /* if need transfer data in dma mode, config the DMA descriptor first */ if ((data != NULL) && (dmaConfig != NULL)) { - if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData, + if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData != NULL ? data->rxData : data->txData, data->blockSize * data->blockCount)) == kStatus_SDIF_DescriptorBufferLenError) { @@ -1198,9 +1288,6 @@ status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sd if (!enDMA) { SDIF_EnableInternalDMA(base, false); - /* reset FIFO and clear RAW status for host transfer */ - SDIF_Reset(base, kSDIF_ResetFIFO, SDIF_RESET_TIMEOUT_VALUE); - SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); } /* config the transfer parameter */ @@ -1211,19 +1298,21 @@ status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sd /* send command first, do not wait start bit auto cleared, command done bit should wait while sending normal command */ - SDIF_SendCommand(base, transfer->command, 0U); - - /* wait the command transfer done and check if error occurs */ - if (SDIF_WaitCommandDone(base, transfer->command) != kStatus_Success) + if (SDIF_SendCommand(base, transfer->command, 0UL) != kStatus_Success) { return kStatus_SDIF_SendCmdFail; } + if (SDIF_WaitCommandDone(base, transfer->command) != kStatus_Success) + { + return kStatus_SDIF_SendCmdFail; + } /* if use DMA transfer mode ,check the corresponding status bit */ if (data != NULL) { /* handle data transfer */ - if (SDIF_TransferDataBlocking(base, data, enDMA) != kStatus_Success) + error = SDIF_TransferDataBlocking(base, data, enDMA); + if (error != kStatus_Success) { return kStatus_SDIF_DataTransferFail; } @@ -1266,7 +1355,7 @@ status_t SDIF_TransferNonBlocking(SDIF_Type *base, if ((data != NULL) && (dmaConfig != NULL)) { /* use internal DMA mode to transfer between the card and host*/ - if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData ? data->rxData : data->txData, + if ((error = SDIF_InternalDMAConfig(base, dmaConfig, data->rxData != NULL ? data->rxData : data->txData, data->blockSize * data->blockCount)) == kStatus_SDIF_DescriptorBufferLenError) { @@ -1287,9 +1376,6 @@ status_t SDIF_TransferNonBlocking(SDIF_Type *base, if (!enDMA) { SDIF_EnableInternalDMA(base, false); - /* reset FIFO and clear RAW status for host transfer */ - SDIF_Reset(base, kSDIF_ResetFIFO, SDIF_RESET_TIMEOUT_VALUE); - SDIF_ClearInterruptStatus(base, kSDIF_AllInterruptStatus); } /* config the transfer parameter */ @@ -1300,9 +1386,7 @@ status_t SDIF_TransferNonBlocking(SDIF_Type *base, /* send command first, do not wait start bit auto cleared, command done bit should wait while sending normal command */ - SDIF_SendCommand(base, transfer->command, 0U); - - return kStatus_Success; + return SDIF_SendCommand(base, transfer->command, 0UL); } /*! @@ -1318,11 +1402,11 @@ void SDIF_TransferCreateHandle(SDIF_Type *base, sdif_transfer_callback_t *callback, void *userData) { - assert(handle); - assert(callback); + assert(handle != NULL); + assert(callback != NULL); /* reset the handle. */ - memset(handle, 0U, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); /* Set the callback. */ handle->callback.SDIOInterrupt = callback->SDIOInterrupt; @@ -1330,6 +1414,7 @@ void SDIF_TransferCreateHandle(SDIF_Type *base, handle->callback.CommandReload = callback->CommandReload; handle->callback.TransferComplete = callback->TransferComplete; handle->callback.cardInserted = callback->cardInserted; + handle->callback.cardRemoved = callback->cardRemoved; handle->userData = userData; /* Save the handle in global variables to support the double weak mechanism. */ @@ -1341,7 +1426,7 @@ void SDIF_TransferCreateHandle(SDIF_Type *base, /* enable the global interrupt */ SDIF_EnableGlobalInterrupt(base, true); - EnableIRQ(s_sdifIRQ[SDIF_GetInstance(base)]); + (void)EnableIRQ(s_sdifIRQ[SDIF_GetInstance(base)]); } /*! @@ -1354,25 +1439,26 @@ void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability) assert(NULL != capability); /* Initializes the configure structure to zero. */ - memset(capability, 0, sizeof(*capability)); + (void)memset(capability, 0, sizeof(*capability)); capability->sdVersion = SDIF_SUPPORT_SD_VERSION; capability->mmcVersion = SDIF_SUPPORT_MMC_VERSION; capability->maxBlockLength = SDIF_BLKSIZ_BLOCK_SIZE_MASK; /* set the max block count = max byte count / max block size */ capability->maxBlockCount = SDIF_BYTCNT_BYTE_COUNT_MASK / SDIF_BLKSIZ_BLOCK_SIZE_MASK; - capability->flags = kSDIF_SupportHighSpeedFlag | kSDIF_SupportDmaFlag | kSDIF_SupportSuspendResumeFlag | - kSDIF_SupportV330Flag | kSDIF_Support4BitFlag | kSDIF_Support8BitFlag; + capability->flags = (uint32_t)kSDIF_SupportHighSpeedFlag | (uint32_t)kSDIF_SupportDmaFlag | + (uint32_t)kSDIF_SupportSuspendResumeFlag | (uint32_t)kSDIF_SupportV330Flag | + (uint32_t)kSDIF_Support4BitFlag | (uint32_t)kSDIF_Support8BitFlag; } static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) { - assert(handle->command); + assert(handle->command != NULL); /* cmd buffer full, in this condition user need re-send the command */ - if (interruptFlags & kSDIF_HardwareLockError) + if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_HardwareLockError)) { - if (handle->callback.CommandReload) + if (handle->callback.CommandReload != NULL) { handle->callback.CommandReload(base, handle->userData); } @@ -1380,101 +1466,133 @@ static void SDIF_TransferHandleCommand(SDIF_Type *base, sdif_handle_t *handle, u /* transfer command done */ else { - if ((kSDIF_CommandDone & interruptFlags) != 0U) + if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_CommandDone)) { /* transfer error */ - if (interruptFlags & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout)) + if ((IS_SDIF_FLAG_SET(interruptFlags, ((uint32_t)kSDIF_ResponseError | (uint32_t)kSDIF_ResponseCRCError | + (uint32_t)kSDIF_ResponseTimeout))) || + (SDIF_ReadCommandResponse(base, handle->command) != kStatus_Success)) { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData); + if (handle->callback.TransferComplete != NULL) + { + handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData); + } } else { - SDIF_ReadCommandResponse(base, handle->command); - if (((handle->data) == NULL) && (handle->callback.TransferComplete)) + if (handle->callback.TransferComplete != NULL) { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdSuccess, handle->userData); } } } } + + SDIF_DisableInterrupt(base, kSDIF_CommandTransferStatus); + handle->command = NULL; } static void SDIF_TransferHandleData(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) { - assert(handle->data); + assert(handle->data != NULL); + + status_t transferStatus = kStatus_SDIF_BusyTransferring; + uint32_t transferredWords = handle->transferredWords; /* data starvation by host time out, software should read/write FIFO*/ - if (interruptFlags & kSDIF_DataStarvationByHostTimeout) + if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataStarvationByHostTimeout)) { if (handle->data->rxData != NULL) { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); + handle->transferredWords = SDIF_ReadDataPort(base, handle->data, transferredWords); } else if (handle->data->txData != NULL) { - handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords); + handle->transferredWords = SDIF_WriteDataPort(base, handle->data, transferredWords); } else { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); + transferStatus = kStatus_SDIF_DataTransferFail; } } /* data transfer fail */ - else if (interruptFlags & kSDIF_DataTransferError) + else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataTransferError)) { if (!handle->data->enableIgnoreError) { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); + transferStatus = kStatus_SDIF_DataTransferFail; + } + else + { + transferStatus = kStatus_SDIF_DataTransferSuccess; } } /* need fill data to FIFO */ - else if (interruptFlags & kSDIF_WriteFIFORequest) + else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_WriteFIFORequest)) { - handle->transferredWords = SDIF_WriteDataPort(base, handle->data, handle->transferredWords); + handle->transferredWords = SDIF_WriteDataPort(base, handle->data, transferredWords); } /* need read data from FIFO */ - else if (interruptFlags & kSDIF_ReadFIFORequest) + else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_ReadFIFORequest)) { - handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); + handle->transferredWords = SDIF_ReadDataPort(base, handle->data, transferredWords); } else { + /* Intentional empty */ } /* data transfer over */ - if (interruptFlags & kSDIF_DataTransferOver) + if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataTransferOver)) { - while ((handle->data->rxData != NULL) && ((base->STATUS & SDIF_STATUS_FIFO_COUNT_MASK) != 0U)) + while ((handle->data->rxData != NULL) && ((base->STATUS & SDIF_STATUS_FIFO_COUNT_MASK) != 0UL)) { handle->transferredWords = SDIF_ReadDataPort(base, handle->data, handle->transferredWords); } - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + transferStatus = kStatus_SDIF_DataTransferSuccess; + } + + if ((handle->callback.TransferComplete != NULL) && (transferStatus != kStatus_SDIF_BusyTransferring)) + { + handle->callback.TransferComplete(base, handle, transferStatus, handle->userData); + handle->data = NULL; } } static void SDIF_TransferHandleDMA(SDIF_Type *base, sdif_handle_t *handle, uint32_t interruptFlags) { - if (interruptFlags & kSDIF_DMAFatalBusError) + status_t transferStatus = kStatus_SDIF_DataTransferFail; + + if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DMAFatalBusError)) { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DMATransferFailWithFBE, handle->userData); + transferStatus = kStatus_SDIF_DMATransferFailWithFBE; } - else if (interruptFlags & kSDIF_DMADescriptorUnavailable) + else if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DMADescriptorUnavailable)) { - if (handle->callback.DMADesUnavailable) + if (handle->callback.DMADesUnavailable != NULL) { handle->callback.DMADesUnavailable(base, handle->userData); } } - else if ((interruptFlags & (kSDIF_AbnormalInterruptSummary | kSDIF_DMACardErrorSummary)) && + else if (IS_SDIF_FLAG_SET(interruptFlags, + ((uint32_t)kSDIF_AbnormalInterruptSummary | (uint32_t)kSDIF_DMACardErrorSummary)) && (!handle->data->enableIgnoreError)) { - handle->callback.TransferComplete(base, handle, kStatus_SDIF_DataTransferFail, handle->userData); + transferStatus = kStatus_SDIF_DataTransferFail; } /* card normal summary */ else { - handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData); + transferStatus = kStatus_SDIF_DataTransferSuccess; } + + if (handle->callback.TransferComplete != NULL) + { + handle->callback.TransferComplete(base, handle, transferStatus, handle->userData); + handle->data = NULL; + } + + SDIF_DisableDmaInterrupt(base, kSDIF_DMAAllStatus); } static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle) @@ -1487,7 +1605,7 @@ static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *han static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle) { - if (SDIF_DetectCardInsert(base, false)) + if (SDIF_DetectCardInsert(base, false) == 1UL) { if ((handle->callback.cardInserted) != NULL) { @@ -1505,30 +1623,30 @@ static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle static void SDIF_TransferHandleIRQ(SDIF_Type *base, sdif_handle_t *handle) { - assert(handle); + assert(handle != NULL); uint32_t interruptFlags, dmaInterruptFlags; interruptFlags = SDIF_GetEnabledInterruptStatus(base); dmaInterruptFlags = SDIF_GetEnabledDMAInterruptStatus(base); - if ((interruptFlags & kSDIF_CommandTransferStatus) != 0U) + if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_CommandTransferStatus)) { - SDIF_TransferHandleCommand(base, handle, (interruptFlags & kSDIF_CommandTransferStatus)); + SDIF_TransferHandleCommand(base, handle, interruptFlags); } - if ((interruptFlags & kSDIF_DataTransferStatus) != 0U) + if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_DataTransferStatus)) { - SDIF_TransferHandleData(base, handle, (interruptFlags & kSDIF_DataTransferStatus)); + SDIF_TransferHandleData(base, handle, interruptFlags); } - if (interruptFlags & kSDIF_SDIOInterrupt) + if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_SDIOInterrupt)) { SDIF_TransferHandleSDIOInterrupt(base, handle); } - if (dmaInterruptFlags & kSDIF_DMAAllStatus) + if (IS_SDIF_FLAG_SET(dmaInterruptFlags, kSDIF_DMAAllStatus)) { SDIF_TransferHandleDMA(base, handle, dmaInterruptFlags); } - if (interruptFlags & kSDIF_CardDetect) + if (IS_SDIF_FLAG_SET(interruptFlags, kSDIF_CardDetect)) { SDIF_TransferHandleCardDetect(base, handle); } @@ -1559,15 +1677,12 @@ void SDIF_Deinit(SDIF_Type *base) } #if defined(SDIF) +void SDIF_DriverIRQHandler(void); void SDIF_DriverIRQHandler(void) { - assert(s_sdifHandle[0]); + assert(s_sdifHandle[0] != NULL); s_sdifIsr(SDIF, s_sdifHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.h index e8149629cd..9c1a7ea5b6 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sdif.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief Driver version 2.0.11. */ -#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 11U)) +/*! @brief Driver version 2.0.15. */ +#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 1U, 0U)) /*@}*/ /*! @brief SDIOCLKCTRL setting @@ -47,7 +47,7 @@ #endif /*! @brief High speed mode clk_drv fixed delay */ #ifndef SDIF_HIGHSPEED_DRV_DELAY -#define SDIF_HIGHSPEED_DRV_DELAY (0x1FU) /*!< 31 * 250ps = 7.75ns */ +#define SDIF_HIGHSPEED_DRV_DELAY (31U) /*!< 31 * 250ps = 7.75ns */ #endif /* @@ -67,7 +67,7 @@ #endif /*! @brief default mode sample fixed delay */ #ifndef SDIF_DEFAULT_MODE_SAMPLE_DELAY -#define SDIF_DEFAULT_MODE_SAMPLE_DELAY (31U) /*!< 31 * 250ps = 7.75ns */ +#define SDIF_DEFAULT_MODE_SAMPLE_DELAY (12U) /*!< 12 * 250ps = 3ns */ #endif #ifndef SDIF_DEFAULT_MODE_DRV_DELAY @@ -77,15 +77,15 @@ /*! @brief SDIF internal DMA descriptor address and the data buffer address align */ #define SDIF_INTERNAL_DMA_ADDR_ALIGN (4U) /*! @brief SDIF DMA descriptor flag */ -#define SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG (1U << 1U) -#define SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG (1U << 2U) -#define SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG (1U << 3U) -#define SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG (1U << 4U) -#define SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG (1U << 5U) -#define SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG (1U << 31U) +#define SDIF_DMA_DESCRIPTOR_DISABLE_COMPLETE_INT_FLAG (1UL << 1U) +#define SDIF_DMA_DESCRIPTOR_DATA_BUFFER_END_FLAG (1UL << 2U) +#define SDIF_DMA_DESCRIPTOR_DATA_BUFFER_START_FLAG (1UL << 3U) +#define SDIF_DMA_DESCRIPTOR_SECOND_ADDR_CHAIN_FLAG (1UL << 4U) +#define SDIF_DMA_DESCRIPTOR_DESCRIPTOR_END_FLAG (1UL << 5U) +#define SDIF_DMA_DESCRIPTOR_OWN_BY_DMA_FLAG (1UL << 31U) -/*! @brief SDIF status */ -enum _sdif_status +/*! @brief _sdif_status SDIF status */ +enum { kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */ kStatus_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U), /*!< invalid argument status */ @@ -98,14 +98,18 @@ enum _sdif_status MAKE_STATUS(kStatusGroup_SDIF, 5U), /*!< DMA transfer data fail with fatal bus error , to do with this error :issue a hard reset/controller reset*/ kStatus_SDIF_DMATransferDescriptorUnavailable = - MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< DMA descriptor unavailable */ - kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< transfer data fail */ - kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U), /*!< response error */ - kStatus_SDIF_DMAAddrNotAlign = MAKE_STATUS(kStatusGroup_SDIF, 8U), /*!< DMA address not align */ + MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< DMA descriptor unavailable */ + kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< transfer data fail */ + kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U), /*!< response error */ + kStatus_SDIF_DMAAddrNotAlign = MAKE_STATUS(kStatusGroup_SDIF, 8U), /*!< DMA address not align */ + kStatus_SDIF_BusyTransferring = MAKE_STATUS(kStatusGroup_SDIF, 9U), /*!< SDIF transfer busy status */ + kStatus_SDIF_DataTransferSuccess = MAKE_STATUS(kStatusGroup_SDIF, 10U), /*!< transfer data success */ + kStatus_SDIF_SendCmdSuccess = MAKE_STATUS(kStatusGroup_SDIF, 11U), /*!< transfer command success */ + }; -/*! @brief Host controller capabilities flag mask */ -enum _sdif_capability_flag +/*! @brief _sdif_capability_flag Host controller capabilities flag mask */ +enum { kSDIF_SupportHighSpeedFlag = 0x1U, /*!< Support high-speed */ kSDIF_SupportDmaFlag = 0x2U, /*!< Support DMA */ @@ -115,14 +119,14 @@ enum _sdif_capability_flag kSDIF_Support8BitFlag = 0x20U, /*!< Support 8 bit mode */ }; -/*! @brief define the reset type */ -enum _sdif_reset_type +/*! @brief _sdif_reset_type define the reset type */ +enum { kSDIF_ResetController = SDIF_CTRL_CONTROLLER_RESET_MASK, /*!< reset controller,will reset: BIU/CIU interface CIU and state machine,ABORT_READ_DATA,SEND_IRQ_RESPONSE and READ_WAIT bits of control register,START_CMD bit of the command register*/ - kSDIF_ResetFIFO = SDIF_CTRL_FIFO_RESET_MASK, /*!< reset data FIFO*/ + kSDIF_ResetFIFO = SDIF_CTRL_FIFO_RESET_MASK, /*!< reset data FIFO*/ kSDIF_ResetDMAInterface = SDIF_CTRL_DMA_RESET_MASK, /*!< reset DMA interface */ kSDIF_ResetAll = kSDIF_ResetController | kSDIF_ResetFIFO | /*!< reset all*/ @@ -138,8 +142,8 @@ typedef enum _sdif_bus_width kSDIF_Bus8BitWidth = 2U, /*!< support 8 bit mode */ } sdif_bus_width_t; -/*! @brief define the command flags */ -enum _sdif_command_flags +/*! @brief _sdif_command_flags define the command flags */ +enum { kSDIF_CmdResponseExpect = SDIF_CMD_RESPONSE_EXPECT_MASK, /*!< command request response*/ kSDIF_CmdResponseLengthLong = SDIF_CMD_RESPONSE_LENGTH_MASK, /*!< command response length long */ @@ -168,8 +172,8 @@ enum _sdif_command_flags kSDIF_CmdDataUseHoldReg = SDIF_CMD_USE_HOLD_REG_MASK, /*!< cmd and data send to card through the HOLD register*/ }; -/*! @brief The command type */ -enum _sdif_command_type +/*! @brief _sdif_command_type The command type */ +enum { kCARD_CommandTypeNormal = 0U, /*!< Normal command */ kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ @@ -178,11 +182,11 @@ enum _sdif_command_type }; /*! - * @brief The command response type. + * @brief _sdif_response_type The command response type. * * Define the command response type from card to host controller. */ -enum _sdif_response_type +enum { kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ @@ -196,8 +200,8 @@ enum _sdif_response_type kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ }; -/*! @brief define the interrupt mask flags */ -enum _sdif_interrupt_mask +/*! @brief _sdif_interrupt_mask define the interrupt mask flags */ +enum { kSDIF_CardDetect = SDIF_INTMASK_CDET_MASK, /*!< mask for card detect */ kSDIF_ResponseError = SDIF_INTMASK_RE_MASK, /*!< command response error */ @@ -218,20 +222,20 @@ enum _sdif_interrupt_mask kSDIF_SDIOInterrupt = SDIF_INTMASK_SDIO_INT_MASK_MASK, /*!< interrupt from the SDIO card */ kSDIF_CommandTransferStatus = kSDIF_ResponseError | kSDIF_CommandDone | kSDIF_ResponseCRCError | - kSDIF_ResponseTimeout | + kSDIF_ResponseTimeout | kSDIF_DataStartBitError | kSDIF_HardwareLockError, /*!< command transfer status collection*/ kSDIF_DataTransferStatus = kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest | kSDIF_DataCRCError | kSDIF_DataReadTimeout | kSDIF_DataStarvationByHostTimeout | - kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | - kSDIF_AutoCmdDone, /*!< data transfer status collection */ + kSDIF_FIFOError | kSDIF_DataStartBitError | + kSDIF_DataEndBitError, /*!< data transfer status collection */ kSDIF_DataTransferError = kSDIF_DataCRCError | kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | kSDIF_DataReadTimeout, kSDIF_AllInterruptStatus = 0x1FFFFU, /*!< all interrupt mask */ }; -/*! @brief define the internal DMA status flags */ -enum _sdif_dma_status +/*! @brief _sdif_dma_status define the internal DMA status flags */ +enum { kSDIF_DMATransFinishOneDescriptor = SDIF_IDSTS_TI_MASK, /*!< DMA transfer finished for one DMA descriptor */ kSDIF_DMARecvFinishOneDescriptor = SDIF_IDSTS_RI_MASK, /*!< DMA receive finished for one DMA descriptor */ @@ -247,10 +251,10 @@ enum _sdif_dma_status }; -/*! @brief define the internal DMA descriptor flag +/*! @brief _sdif_dma_descriptor_flag define the internal DMA descriptor flag * @deprecated Do not use this enum anymore, please use SDIF_DMA_DESCRIPTOR_XXX_FLAG instead. */ -enum _sdif_dma_descriptor_flag +enum { kSDIF_DisableCompleteInterrupt = 0x2U, /*!< disable the complete interrupt flag for the ends in the buffer pointed to by this descriptor*/ @@ -346,8 +350,6 @@ typedef struct _sdif_config uint8_t responseTimeout; /*!< command response timeout value */ uint32_t cardDetDebounce_Clock; /*!< define the debounce clock count which will used in card detect logic,typical value is 5-25ms */ - uint32_t endianMode; /*!< define endian mode ,this field is not used in this - module actually, keep for compatible with middleware*/ uint32_t dataTimeout; /*!< data timeout value */ } sdif_config_t; @@ -417,8 +419,7 @@ typedef struct _sdif_host * API ************************************************************************************************/ #if defined(__cplusplus) -extern "C" -{ +extern "C" { #endif /*! @@ -440,7 +441,7 @@ void SDIF_Deinit(SDIF_Type *base); /*! * @brief SDIF send initialize 80 clocks for SD card after initial * @param base SDIF peripheral base address. - * @param timeout value + * @param timeout timeout value */ bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout); @@ -448,7 +449,7 @@ bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout); /*! * @brief SDIF module enable/disable card0 clock. * @param base SDIF peripheral base address. - * @param enable/disable flag + * @param enable enable/disable flag */ static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) { @@ -465,7 +466,7 @@ static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) /*! * @brief SDIF module enable/disable card1 clock. * @param base SDIF peripheral base address. - * @param enable/disable flag + * @param enable enable/disable flag */ static inline void SDIF_EnableCard1Clock(SDIF_Type *base, bool enable) { @@ -484,7 +485,7 @@ static inline void SDIF_EnableCard1Clock(SDIF_Type *base, bool enable) * to enter low power mode when card is idle,for SDIF cards, if * interrupts must be detected, clock should not be stopped * @param base SDIF peripheral base address. - * @param enable/disable flag + * @param enable enable/disable flag */ static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) { @@ -503,7 +504,7 @@ static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) * to enter low power mode when card is idle,for SDIF cards, if * interrupts must be detected, clock should not be stopped * @param base SDIF peripheral base address. - * @param enable/disable flag + * @param enable enable/disable flag */ static inline void SDIF_EnableCard1LowPowerMode(SDIF_Type *base, bool enable) { @@ -522,7 +523,7 @@ static inline void SDIF_EnableCard1LowPowerMode(SDIF_Type *base, bool enable) * once turn power on, software should wait for regulator/switch * ramp-up time before trying to initialize card. * @param base SDIF peripheral base address. - * @param enable/disable flag. + * @param enable enable/disable flag. */ static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) { @@ -541,7 +542,7 @@ static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) * once turn power on, software should wait for regulator/switch * ramp-up time before trying to initialize card. * @param base SDIF peripheral base address. - * @param enable/disable flag. + * @param enable enable/disable flag. */ static inline void SDIF_EnableCard1Power(SDIF_Type *base, bool enable) { @@ -558,14 +559,14 @@ static inline void SDIF_EnableCard1Power(SDIF_Type *base, bool enable) /*! * @brief set card0 data bus width * @param base SDIF peripheral base address. - * @param data bus width type + * @param type data bus width type */ void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type); /*! * @brief set card1 data bus width * @param base SDIF peripheral base address. - * @param data bus width type + * @param type data bus width type */ void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type); @@ -580,11 +581,11 @@ static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3) { if (data3) { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U; + return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0UL; } else { - return (base->CDETECT & SDIF_CDETECT_CARD0_DETECT_MASK) == 0U ? 1U : 0U; + return (base->CDETECT & SDIF_CDETECT_CARD0_DETECT_MASK) == 0UL ? 1UL : 0UL; } } @@ -599,18 +600,18 @@ static inline uint32_t SDIF_DetectCard1Insert(SDIF_Type *base, bool data3) { if (data3) { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U; + return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0UL; } else { - return (base->CDETECT & SDIF_CDETECT_CARD1_DETECT_MASK) == 0U ? 1U : 0U; + return (base->CDETECT & SDIF_CDETECT_CARD1_DETECT_MASK) == 0UL ? 1UL : 0UL; } } #else /*! * @brief SDIF module enable/disable card clock. * @param base SDIF peripheral base address. - * @param enable/disable flag + * @param enable enable/disable flag */ static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) { @@ -629,7 +630,7 @@ static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) * to enter low power mode when card is idle,for SDIF cards, if * interrupts must be detected, clock should not be stopped * @param base SDIF peripheral base address. - * @param enable/disable flag + * @param enable enable/disable flag */ static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) { @@ -648,7 +649,7 @@ static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) * once turn power on, software should wait for regulator/switch * ramp-up time before trying to initialize card. * @param base SDIF peripheral base address. - * @param enable/disable flag. + * @param enable enable/disable flag. */ static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) { @@ -665,7 +666,7 @@ static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) /*! * @brief set card data bus width * @param base SDIF peripheral base address. - * @param data bus width type + * @param type bus width type */ void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type); @@ -680,11 +681,11 @@ static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3) { if (data3) { - return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U; + return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1UL : 0UL; } else { - return (base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK) == 0U ? 1U : 0U; + return (base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK) == 0UL ? 1UL : 0UL; } } #endif @@ -703,7 +704,7 @@ uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t targe * @brief reset the different block of the interface. * @param base SDIF peripheral base address. * @param mask indicate which block to reset. - * @param timeout value,set to wait the bit self clear + * @param timeout timeout value,set to wait the bit self clear * @return reset result. */ bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout); @@ -733,8 +734,8 @@ static inline void SDIF_AssertHardwareReset(SDIF_Type *base) * This api include polling the status of the bit START_COMMAND, if 0 used as timeout value, then this function * will return directly without polling the START_CMD status. * @param base SDIF peripheral base address. - * @param command configuration collection - * @param timeout not used in this function + * @param cmd configuration collection + * @param timeout the timeout value of polling START_CMD auto clear status. * @return command excute status */ status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout); @@ -742,7 +743,7 @@ status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout /*! * @brief SDIF enable/disable global interrupt * @param base SDIF peripheral base address. - * @param enable/disable flag + * @param enable enable/disable flag */ static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable) { @@ -759,7 +760,7 @@ static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable) /*! * @brief SDIF enable interrupt * @param base SDIF peripheral base address. - * @param interrupt mask + * @param mask mask */ static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask) { @@ -769,7 +770,7 @@ static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask) /*! * @brief SDIF disable interrupt * @param base SDIF peripheral base address. - * @param interrupt mask + * @param mask mask */ static inline void SDIF_DisableInterrupt(SDIF_Type *base, uint32_t mask) { @@ -791,13 +792,15 @@ static inline uint32_t SDIF_GetInterruptStatus(SDIF_Type *base) */ static inline uint32_t SDIF_GetEnabledInterruptStatus(SDIF_Type *base) { - return (base->MINTSTS) & (base->INTMASK); + uint32_t intStatus = base->MINTSTS; + + return intStatus & base->INTMASK; } /*! * @brief SDIF clear interrupt status * @param base SDIF peripheral base address. - * @param status mask to clear + * @param mask mask to clear */ static inline void SDIF_ClearInterruptStatus(SDIF_Type *base, uint32_t mask) { @@ -820,7 +823,7 @@ void SDIF_TransferCreateHandle(SDIF_Type *base, /*! * @brief SDIF enable DMA interrupt * @param base SDIF peripheral base address. - * @param interrupt mask to set + * @param mask mask to set */ static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask) { @@ -830,7 +833,7 @@ static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask) /*! * @brief SDIF disable DMA interrupt * @param base SDIF peripheral base address. - * @param interrupt mask to clear + * @param mask mask to clear */ static inline void SDIF_DisableDmaInterrupt(SDIF_Type *base, uint32_t mask) { @@ -854,12 +857,14 @@ static inline uint32_t SDIF_GetInternalDMAStatus(SDIF_Type *base) */ static inline uint32_t SDIF_GetEnabledDMAInterruptStatus(SDIF_Type *base) { - return (base->IDSTS) & (base->IDINTEN); + uint32_t intStatus = base->IDSTS; + + return intStatus & base->IDINTEN; } /*! * @brief SDIF clear internal DMA status * @param base SDIF peripheral base address. - * @param status mask to clear + * @param mask mask to clear */ static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask) { @@ -869,14 +874,11 @@ static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask) /*! * @brief SDIF internal DMA config function * @param base SDIF peripheral base address. - * @param internal DMA configuration collection + * @param config DMA configuration collection * @param data buffer pointer - * @param data buffer size + * @param dataSize buffer size */ -status_t SDIF_InternalDMAConfig(SDIF_Type *base, - sdif_dma_config_t *config, - const uint32_t *data, - uint32_t dataSize); +status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize); /*! * @brief SDIF internal DMA enable @@ -916,7 +918,7 @@ static inline void SDIF_SendReadWait(SDIF_Type *base) * next blocking data,used in SDIO card suspend sequence,should call after suspend * cmd send * @param base SDIF peripheral base address. - * @param timeout value to wait this bit self clear which indicate the data machine + * @param timeout timeout value to wait this bit self clear which indicate the data machine * reset to idle */ bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout); @@ -925,7 +927,7 @@ bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout); * @brief SDIF enable/disable CE-ATA card interrupt * this bit should set together with the card register * @param base SDIF peripheral base address. - * @param enable/disable flag + * @param enable enable/disable flag */ static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable) { @@ -945,14 +947,14 @@ static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable) * must call SDIF_TransferCreateHandle first, all status check through * interrupt * @param base SDIF peripheral base address. - * @param sdif handle - * @param DMA config structure + * @param handle handle + * @param dmaConfig config structure * This parameter can be config as: * 1. NULL In this condition, polling transfer mode is selected 2. avaliable DMA config In this condition, DMA transfer mode is selected - * @param sdif transfer configuration collection + * @param transfer transfer configuration collection */ status_t SDIF_TransferNonBlocking(SDIF_Type *base, sdif_handle_t *handle, @@ -962,12 +964,12 @@ status_t SDIF_TransferNonBlocking(SDIF_Type *base, /*! * @brief SDIF transfer function data/cmd in a blocking way * @param base SDIF peripheral base address. - * @param DMA config structure + * @param dmaConfig config structure * 1. NULL * In this condition, polling transfer mode is selected * 2. avaliable DMA config * In this condition, DMA transfer mode is selected - * @param sdif transfer configuration collection + * @param transfer transfer configuration collection */ status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer); @@ -975,14 +977,14 @@ status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sd * @brief SDIF release the DMA descriptor to DMA engine * this function should be called when DMA descriptor unavailable status occurs * @param base SDIF peripheral base address. - * @param sdif DMA config pointer + * @param dmaConfig DMA config pointer */ status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig); /*! * @brief SDIF return the controller capability * @param base SDIF peripheral base address. - * @param sdif capability pointer + * @param capability capability pointer */ void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability); @@ -998,7 +1000,7 @@ static inline uint32_t SDIF_GetControllerStatus(SDIF_Type *base) /*! * @brief SDIF send command complete signal disable to CE-ATA card * @param base SDIF peripheral base address. - * @param send auto stop flag + * @param withAutoStop auto stop flag */ static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop) { @@ -1018,7 +1020,7 @@ static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop) * sample and driver the data ,should meet the min setup * time and hold time, and user need to config this parameter * according to your board setting - * @param target freq work mode + * @param target_HZ freq work mode * @param divider not used in this function anymore, use DELAY value instead of phase directly. */ void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider); diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.c index 30d433097f..456361e620 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -30,7 +30,22 @@ * range <0,15>. Range <8,15> represents 2B transfer */ #define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U)) #define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U)) +#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) +#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK)) +#else #define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK)) +#endif /*FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE*/ + +/*! + * @brief Used for conversion from `flexcomm_irq_handler_t` to `flexcomm_spi_master_irq_handler_t` and + * `flexcomm_spi_slave_irq_handler_t`. + */ +typedef union spi_to_flexcomm +{ + flexcomm_spi_master_irq_handler_t spi_master_handler; + flexcomm_spi_slave_irq_handler_t spi_slave_handler; + flexcomm_irq_handler_t flexcomm_handler; +} spi_to_flexcomm_t; /******************************************************************************* * Variables @@ -54,18 +69,18 @@ volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0}; /*! brief Returns instance number for SPI peripheral base address. */ uint32_t SPI_GetInstance(SPI_Type *base) { - int i; + uint32_t i; - for (i = 0; i < FSL_FEATURE_SOC_SPI_COUNT; i++) + for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT; i++) { if ((uint32_t)base == s_spiBaseAddrs[i]) { - return i; + break; } } - assert(false); - return 0; + assert(i < (uint32_t)FSL_FEATURE_SOC_SPI_COUNT); + return i; } /*! @@ -89,12 +104,8 @@ void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData) */ void *SPI_GetConfig(SPI_Type *base) { - int32_t instance; + uint32_t instance; instance = SPI_GetInstance(base); - if (instance < 0) - { - return NULL; - } return &g_configs[instance]; } @@ -118,7 +129,7 @@ void SPI_MasterGetDefaultConfig(spi_master_config_t *config) assert(NULL != config); /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); config->enableLoopback = false; config->enableMaster = true; @@ -128,8 +139,8 @@ void SPI_MasterGetDefaultConfig(spi_master_config_t *config) config->baudRate_Bps = 500000U; config->dataWidth = kSPI_Data8Bits; config->sselNum = kSPI_Ssel0; - config->txWatermark = kSPI_TxFifo0; - config->rxWatermark = kSPI_RxFifo1; + config->txWatermark = (uint8_t)kSPI_TxFifo0; + config->rxWatermark = (uint8_t)kSPI_RxFifo1; config->sselPol = kSPI_SpolActiveAllLow; config->delayConfig.preDelay = 0U; config->delayConfig.postDelay = 0U; @@ -157,19 +168,19 @@ void SPI_MasterGetDefaultConfig(spi_master_config_t *config) */ status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz) { - int32_t result = 0, instance = 0; - uint32_t tmp; + status_t result = kStatus_Success; + uint32_t instance; + uint32_t tmpConfig; /* assert params */ - assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) { return kStatus_InvalidArgument; } /* initialize flexcomm to SPI mode */ result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - assert(kStatus_Success == result); if (kStatus_Success != result) { return result; @@ -181,27 +192,27 @@ status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint3 { return result; } + /* get instance number */ instance = SPI_GetInstance(base); - assert(instance >= 0); /* configure SPI mode */ - tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | - SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); + tmpConfig = base->CFG; + tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); /* phase */ - tmp |= SPI_CFG_CPHA(config->phase); + tmpConfig |= SPI_CFG_CPHA(config->phase); /* polarity */ - tmp |= SPI_CFG_CPOL(config->polarity); + tmpConfig |= SPI_CFG_CPOL(config->polarity); /* direction */ - tmp |= SPI_CFG_LSBF(config->direction); + tmpConfig |= SPI_CFG_LSBF(config->direction); /* master mode */ - tmp |= SPI_CFG_MASTER(1); + tmpConfig |= SPI_CFG_MASTER(1); /* loopback */ - tmp |= SPI_CFG_LOOP(config->enableLoopback); + tmpConfig |= SPI_CFG_LOOP(config->enableLoopback); /* configure active level for all CS */ - tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmp; + tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmpConfig; /* store configuration */ g_configs[instance].dataWidth = config->dataWidth; @@ -210,12 +221,12 @@ status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint3 base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; /* trigger level - empty txFIFO, one item in rxFIFO */ - tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); /* enable generating interrupts for FIFOTRIG levels */ - tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; /* set FIFOTRIG */ - base->FIFOTRIG = tmp; + base->FIFOTRIG = tmpConfig; /* Set the delay configuration. */ SPI_SetTransferDelay(base, &config->delayConfig); @@ -244,15 +255,15 @@ void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) assert(NULL != config); /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); config->enableSlave = true; config->polarity = kSPI_ClockPolarityActiveHigh; config->phase = kSPI_ClockPhaseFirstEdge; config->direction = kSPI_MsbFirst; config->dataWidth = kSPI_Data8Bits; - config->txWatermark = kSPI_TxFifo0; - config->rxWatermark = kSPI_RxFifo1; + config->txWatermark = (uint8_t)kSPI_TxFifo0; + config->rxWatermark = (uint8_t)kSPI_RxFifo1; config->sselPol = kSPI_SpolActiveAllLow; } @@ -278,8 +289,9 @@ void SPI_SlaveGetDefaultConfig(spi_slave_config_t *config) */ status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) { - int32_t result = 0, instance; - uint32_t tmp; + status_t result = kStatus_Success; + uint32_t instance; + uint32_t tmpConfig; /* assert params */ assert(!((NULL == base) || (NULL == config))); @@ -289,7 +301,6 @@ status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) } /* configure flexcomm to SPI, enable clock gate */ result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_SPI); - assert(kStatus_Success == result); if (kStatus_Success != result) { return result; @@ -298,18 +309,18 @@ status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) instance = SPI_GetInstance(base); /* configure SPI mode */ - tmp = base->CFG; - tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK | - SPI_SSELPOL_MASK); + tmpConfig = base->CFG; + tmpConfig &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | + SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK); /* phase */ - tmp |= SPI_CFG_CPHA(config->phase); + tmpConfig |= SPI_CFG_CPHA(config->phase); /* polarity */ - tmp |= SPI_CFG_CPOL(config->polarity); + tmpConfig |= SPI_CFG_CPOL(config->polarity); /* direction */ - tmp |= SPI_CFG_LSBF(config->direction); + tmpConfig |= SPI_CFG_LSBF(config->direction); /* configure active level for all CS */ - tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); - base->CFG = tmp; + tmpConfig |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK)); + base->CFG = tmpConfig; /* store configuration */ g_configs[instance].dataWidth = config->dataWidth; @@ -317,12 +328,12 @@ status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config) base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; base->FIFOCFG |= SPI_FIFOCFG_ENABLETX_MASK | SPI_FIFOCFG_ENABLERX_MASK; /* trigger level - empty txFIFO, one item in rxFIFO */ - tmp = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); - tmp |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); + tmpConfig = base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_TXLVL_MASK)); + tmpConfig |= SPI_FIFOTRIG_TXLVL(config->txWatermark) | SPI_FIFOTRIG_RXLVL(config->rxWatermark); /* enable generating interrupts for FIFOTRIG levels */ - tmp |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; + tmpConfig |= SPI_FIFOTRIG_TXLVLENA_MASK | SPI_FIFOTRIG_RXLVLENA_MASK; /* set FIFOTRIG */ - base->FIFOTRIG = tmp; + base->FIFOTRIG = tmpConfig; SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA); @@ -394,23 +405,23 @@ void SPI_EnableRxDMA(SPI_Type *base, bool enable) */ status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz) { - uint32_t tmp; + uint32_t tmpDiv; /* assert params */ - assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); - if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) + assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); + if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) { return kStatus_InvalidArgument; } - /* calculate baudrate */ - tmp = (srcClock_Hz / baudrate_Bps) - 1; - if (tmp > 0xFFFF) + /* calculate baudrate, round up the result */ + tmpDiv = ((srcClock_Hz * 10U) / baudrate_Bps + 5U) / 10U - 1U; + if (tmpDiv > 0xFFFFU) { return kStatus_SPI_BaudrateNotSupport; } base->DIV &= ~SPI_DIV_DIVVAL_MASK; - base->DIV |= SPI_DIV_DIVVAL(tmp); + base->DIV |= SPI_DIV_DIVVAL(tmpDiv); return kStatus_Success; } @@ -423,27 +434,22 @@ status_t SPI_MasterSetBaud(SPI_Type *base, uint32_t baudrate_Bps, uint32_t srcCl */ void SPI_WriteData(SPI_Type *base, uint16_t data, uint32_t configFlags) { - uint32_t control = 0; - int32_t instance; + uint32_t control = 0U; + uint32_t instance; /* check params */ assert(NULL != base); /* get and check instance */ instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return; - } /* set data width */ - control |= SPI_FIFOWR_LEN(g_configs[instance].dataWidth); + control |= (uint32_t)SPI_FIFOWR_LEN((g_configs[instance].dataWidth)); /* set sssel */ - control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); + control |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); /* mask configFlags */ - control |= (configFlags & SPI_FIFOWR_FLAGS_MASK); + control |= (configFlags & (uint32_t)SPI_FIFOWR_FLAGS_MASK); /* control should not affect lower 16 bits */ - assert(!(control & 0xFFFF)); + assert(0U == (control & 0xFFFFU)); base->FIFOWR = data | control; } @@ -463,49 +469,40 @@ status_t SPI_MasterTransferCreateHandle(SPI_Type *base, spi_master_callback_t callback, void *userData) { - int32_t instance = 0; - /* check 'base' */ - assert(!(NULL == base)); - if (NULL == base) - { - return kStatus_InvalidArgument; - } + assert(NULL != base); /* check 'handle' */ - assert(!(NULL == handle)); - if (NULL == handle) - { - return kStatus_InvalidArgument; - } + assert(NULL != handle); + + uint32_t instance; + spi_to_flexcomm_t handler; + /* get flexcomm instance by 'base' param */ instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return kStatus_InvalidArgument; - } - memset(handle, 0, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); /* Initialize the handle */ - if (base->CFG & SPI_CFG_MASTER_MASK) + if ((base->CFG & SPI_CFG_MASTER_MASK) != 0U) { - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_MasterTransferHandleIRQ, handle); + handler.spi_master_handler = SPI_MasterTransferHandleIRQ; + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); } else { - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)SPI_SlaveTransferHandleIRQ, handle); + handler.spi_slave_handler = SPI_SlaveTransferHandleIRQ; + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); } - handle->dataWidth = g_configs[instance].dataWidth; + handle->dataWidth = (uint8_t)(g_configs[instance].dataWidth); /* in slave mode, the sselNum is not important */ - handle->sselNum = g_configs[instance].sselNum; - handle->txWatermark = (spi_txfifo_watermark_t)SPI_FIFOTRIG_TXLVL_GET(base); - handle->rxWatermark = (spi_rxfifo_watermark_t)SPI_FIFOTRIG_RXLVL_GET(base); + handle->sselNum = (uint8_t)(g_configs[instance].sselNum); + handle->txWatermark = (uint8_t)SPI_FIFOTRIG_TXLVL_GET(base); + handle->rxWatermark = (uint8_t)SPI_FIFOTRIG_RXLVL_GET(base); handle->callback = callback; handle->userData = userData; /* Enable SPI NVIC */ - EnableIRQ(s_spiIRQ[instance]); + (void)EnableIRQ(s_spiIRQ[instance]); return kStatus_Success; } @@ -517,15 +514,19 @@ status_t SPI_MasterTransferCreateHandle(SPI_Type *base, * param xfer pointer to spi_xfer_config_t structure * retval kStatus_Success Successfully start a transfer. * retval kStatus_InvalidArgument Input argument is invalid. + * retval kStatus_SPI_Timeout The transfer timed out and was aborted. */ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) { - int32_t instance; - uint32_t tx_ctrl = 0, last_ctrl = 0; + uint32_t instance; + uint32_t tx_ctrl = 0U, last_ctrl = 0U; uint32_t tmp32, rxRemainingBytes, txRemainingBytes, dataWidth; uint32_t toReceiveCount = 0; uint8_t *txData, *rxData; uint32_t fifoDepth; +#if SPI_RETRY_TIMES + uint32_t waitTimes = SPI_RETRY_TIMES; +#endif /* check params */ assert(!((NULL == base) || (NULL == xfer) || ((NULL == xfer->txData) && (NULL == xfer->rxData)))); @@ -537,16 +538,14 @@ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) fifoDepth = SPI_FIFO_DEPTH(base); txData = xfer->txData; rxData = xfer->rxData; - txRemainingBytes = txData ? xfer->dataSize : 0; - rxRemainingBytes = rxData ? xfer->dataSize : 0; + txRemainingBytes = (txData != NULL) ? xfer->dataSize : 0U; + rxRemainingBytes = (rxData != NULL) ? xfer->dataSize : 0U; - instance = SPI_GetInstance(base); - assert(instance >= 0); - dataWidth = g_configs[instance].dataWidth; + instance = SPI_GetInstance(base); + dataWidth = (uint32_t)(g_configs[instance].dataWidth); /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); - if ((dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) + if ((dataWidth > (uint32_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) { return kStatus_InvalidArgument; } @@ -555,60 +554,67 @@ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum))); + tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL((uint32_t)(g_configs[instance].sselNum)))); /* set width of data - range asserted at entry */ tx_ctrl |= SPI_FIFOWR_LEN(dataWidth); /* delay for frames */ - tx_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; + tx_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; /* end of transfer */ - last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; + last_ctrl |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; /* last index of loop */ - while (txRemainingBytes || rxRemainingBytes || toReceiveCount) + while ((txRemainingBytes != 0U) || (rxRemainingBytes != 0U) || (toReceiveCount != 0U)) { +#if SPI_RETRY_TIMES + if (--waitTimes == 0U) + { + return kStatus_SPI_Timeout; + } +#endif /* if rxFIFO is not empty */ - if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) { tmp32 = base->FIFORD; /* rxBuffer is not empty */ - if (rxRemainingBytes) + if (rxRemainingBytes != 0U) { - *(rxData++) = tmp32; + *(rxData++) = (uint8_t)tmp32; rxRemainingBytes--; /* read 16 bits at once */ - if (dataWidth > 8) + if (dataWidth > 8U) { - *(rxData++) = tmp32 >> 8; + *(rxData++) = (uint8_t)(tmp32 >> 8); rxRemainingBytes--; } } /* decrease number of data expected to receive */ - toReceiveCount -= 1; + toReceiveCount -= 1U; } /* transmit if txFIFO is not full and data to receive does not exceed FIFO depth */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (toReceiveCount < fifoDepth) && - ((txRemainingBytes) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)))) + if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && (toReceiveCount < fifoDepth) && + ((txRemainingBytes != 0U) || (rxRemainingBytes >= SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)))) { /* txBuffer is not empty */ - if (txRemainingBytes) + if (txRemainingBytes != 0U) { tmp32 = *(txData++); txRemainingBytes--; /* write 16 bit at once */ - if (dataWidth > 8) + if (dataWidth > 8U) { tmp32 |= ((uint32_t)(*(txData++))) << 8U; txRemainingBytes--; } - if (!txRemainingBytes) + if (txRemainingBytes == 0U) { tx_ctrl |= last_ctrl; } } else { - tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); + tmp32 = (uint32_t)s_dummyData[instance]; + tmp32 |= (uint32_t)s_dummyData[instance] << 8U; /* last transfer */ - if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1)) + if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1U)) { tx_ctrl |= last_ctrl; } @@ -616,13 +622,24 @@ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer) /* send data */ tmp32 = tx_ctrl | tmp32; base->FIFOWR = tmp32; - toReceiveCount += 1; + toReceiveCount += 1U; } } /* wait if TX FIFO of previous transfer is not empty */ - while (!(base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) +#if SPI_RETRY_TIMES + waitTimes = SPI_RETRY_TIMES; + while ((0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) && (0U != --waitTimes)) +#else + while (0U == (base->FIFOSTAT & SPI_FIFOSTAT_TXEMPTY_MASK)) +#endif { } +#if SPI_RETRY_TIMES + if (waitTimes == 0U) + { + return kStatus_SPI_Timeout; + } +#endif return kStatus_Success; } @@ -647,14 +664,14 @@ status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *hand } /* dataSize (in bytes) is not aligned to 16bit (2B) transfer */ - assert(!((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1))); - if ((handle->dataWidth > kSPI_Data8Bits) && (xfer->dataSize & 0x1)) + assert(!((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U))); + if ((handle->dataWidth > (uint8_t)kSPI_Data8Bits) && ((xfer->dataSize & 0x1U) != 0U)) { return kStatus_InvalidArgument; } /* Check if SPI is busy */ - if (handle->state == kStatus_SPI_Busy) + if (handle->state == (uint32_t)kStatus_SPI_Busy) { return kStatus_SPI_Busy; } @@ -663,14 +680,14 @@ status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *hand handle->txData = xfer->txData; handle->rxData = xfer->rxData; /* set count */ - handle->txRemainingBytes = xfer->txData ? xfer->dataSize : 0; - handle->rxRemainingBytes = xfer->rxData ? xfer->dataSize : 0; + handle->txRemainingBytes = (xfer->txData != NULL) ? xfer->dataSize : 0U; + handle->rxRemainingBytes = (xfer->rxData != NULL) ? xfer->dataSize : 0U; handle->totalByteCount = xfer->dataSize; /* other options */ handle->toReceiveCount = 0; handle->configFlags = xfer->configFlags; /* Set the SPI state to busy */ - handle->state = kStatus_SPI_Busy; + handle->state = (uint32_t)kStatus_SPI_Busy; /* clear FIFOs when transfer starts */ base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; @@ -692,7 +709,7 @@ status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *hand */ status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer) { - assert(xfer); + assert(xfer != NULL); spi_transfer_t tempXfer = {0}; status_t status; @@ -712,11 +729,11 @@ status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_tr /* If the pcs pin keep assert between transmit and receive. */ if (xfer->isPcsAssertInTransfer) { - tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); } else { - tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; } status = SPI_MasterTransferBlocking(base, &tempXfer); @@ -763,8 +780,8 @@ status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_half_duplex_transfer_t *xfer) { - assert(xfer); - assert(handle); + assert(xfer != NULL); + assert(handle != NULL); spi_transfer_t tempXfer = {0}; status_t status; @@ -783,11 +800,11 @@ status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base, /* If the PCS pin keep assert between transmit and receive. */ if (xfer->isPcsAssertInTransfer) { - tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); } else { - tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; } status = SPI_MasterTransferBlocking(base, &tempXfer); @@ -829,13 +846,13 @@ status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, { assert(NULL != handle); - if (!count) + if (NULL == count) { return kStatus_InvalidArgument; } /* Catch when there is not an active transfer. */ - if (handle->state != kStatus_SPI_Busy) + if (handle->state != (uint32_t)kStatus_SPI_Busy) { *count = 0; return kStatus_NoTransferInProgress; @@ -862,52 +879,56 @@ void SPI_MasterTransferAbort(SPI_Type *base, spi_master_handle_t *handle) /* Empty FIFOs */ base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; - handle->state = kStatus_SPI_Idle; - handle->txRemainingBytes = 0; - handle->rxRemainingBytes = 0; + handle->state = (uint32_t)kStatus_SPI_Idle; + handle->txRemainingBytes = 0U; + handle->rxRemainingBytes = 0U; } static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *handle) { - uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32; + uint32_t tx_ctrl = 0U, last_ctrl = 0U, tmp32; bool loopContinue; uint32_t fifoDepth; /* Get flexcomm instance by 'base' param */ uint32_t instance = SPI_GetInstance(base); + size_t txRemainingBytes; + size_t rxRemainingBytes; + uint8_t toReceiveCount; /* check params */ assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData))); fifoDepth = SPI_FIFO_DEPTH(base); /* select slave to talk with */ - tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum)); + tx_ctrl |= ((uint32_t)SPI_DEASSERT_ALL & (uint32_t)SPI_ASSERTNUM_SSEL(handle->sselNum)); /* set width of data */ tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth); /* delay for frames */ - tx_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0; + tx_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; /* end of transfer */ - last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0; + last_ctrl |= ((handle->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; do { loopContinue = false; /* rxFIFO is not empty */ - if (base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) + if ((base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) != 0U) { tmp32 = base->FIFORD; /* rxBuffer is not empty */ - if (handle->rxRemainingBytes) + if (handle->rxRemainingBytes != 0U) { /* low byte must go first */ - *(handle->rxData++) = tmp32; + *(handle->rxData++) = (uint8_t)tmp32; handle->rxRemainingBytes--; /* read 16 bits at once */ - if (handle->dataWidth > kSPI_Data8Bits) + if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) { - *(handle->rxData++) = tmp32 >> 8; + *(handle->rxData++) = (uint8_t)(tmp32 >> 8); handle->rxRemainingBytes--; } } + /* decrease number of data expected to receive */ handle->toReceiveCount -= 1; loopContinue = true; @@ -917,33 +938,39 @@ static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *h * - we cannot cause rxFIFO overflow by sending more data than is the depth of FIFO * - txBuffer is not empty or the next 'toReceiveCount' data can fit into rxBuffer */ - if ((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) && (handle->toReceiveCount < fifoDepth) && - ((handle->txRemainingBytes) || - (handle->rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)))) + txRemainingBytes = handle->txRemainingBytes; + rxRemainingBytes = handle->rxRemainingBytes; + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + if (((base->FIFOSTAT & SPI_FIFOSTAT_TXNOTFULL_MASK) != 0U) && ((uint32_t)toReceiveCount < fifoDepth) && + ((txRemainingBytes != 0U) || + (rxRemainingBytes >= SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)))) { /* txBuffer is not empty */ - if (handle->txRemainingBytes) + if ((txRemainingBytes != 0U) && (handle->txData != NULL)) { /* low byte must go first */ tmp32 = *(handle->txData++); handle->txRemainingBytes--; + txRemainingBytes = handle->txRemainingBytes; /* write 16 bit at once */ - if (handle->dataWidth > kSPI_Data8Bits) + if (handle->dataWidth > (uint8_t)kSPI_Data8Bits) { tmp32 |= ((uint32_t)(*(handle->txData++))) << 8U; handle->txRemainingBytes--; + txRemainingBytes = handle->txRemainingBytes; } /* last transfer */ - if (!handle->txRemainingBytes) + if (handle->txRemainingBytes == 0U) { tx_ctrl |= last_ctrl; } } else { - tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance])); + tmp32 = (uint32_t)s_dummyData[instance]; + tmp32 |= (uint32_t)s_dummyData[instance] << 8U; /* last transfer */ - if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1)) + if (rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, (uint32_t)toReceiveCount + 1U)) { tx_ctrl |= last_ctrl; } @@ -953,7 +980,8 @@ static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *h base->FIFOWR = tmp32; /* increase number of expected data to receive */ handle->toReceiveCount += 1; - loopContinue = true; + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + loopContinue = true; } } while (loopContinue); } @@ -967,6 +995,8 @@ static void SPI_TransferHandleIRQInternal(SPI_Type *base, spi_master_handle_t *h void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) { assert((NULL != base) && (NULL != handle)); + size_t txRemainingBytes; + uint8_t toReceiveCount; /* IRQ behaviour: * - first interrupt is triggered by empty txFIFO. The transfer function @@ -982,13 +1012,13 @@ void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) */ /* Data to send or read or expected to receive */ - if ((handle->txRemainingBytes) || (handle->rxRemainingBytes) || (handle->toReceiveCount)) + if ((handle->txRemainingBytes != 0U) || (handle->rxRemainingBytes != 0U) || (handle->toReceiveCount != 0)) { /* Transmit or receive data */ SPI_TransferHandleIRQInternal(base, handle); /* No data to send or read or receive. Transfer ends. Set txTrigger to 0 level and * enable txIRQ to confirm when txFIFO becomes empty */ - if ((!handle->txRemainingBytes) && (!handle->rxRemainingBytes) && (!handle->toReceiveCount)) + if ((0U == handle->txRemainingBytes) && (0U == handle->rxRemainingBytes) && (0 == handle->toReceiveCount)) { base->FIFOTRIG = base->FIFOTRIG & (~SPI_FIFOTRIG_TXLVL_MASK); base->FIFOINTENSET |= SPI_FIFOINTENSET_TXLVL_MASK; @@ -998,28 +1028,30 @@ void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) uint32_t rxRemainingCount = SPI_BYTES_TO_COUNT(handle->dataWidth, handle->rxRemainingBytes); /* If, there are no data to send or rxFIFO is already filled with necessary number of dummy data, * disable txIRQ. From this point only rxIRQ is used to receive data without any transmission */ - if ((!handle->txRemainingBytes) && (rxRemainingCount <= handle->toReceiveCount)) + toReceiveCount = (handle->toReceiveCount > 0) ? (uint8_t)handle->toReceiveCount : 0U; + if ((0U == handle->txRemainingBytes) && (rxRemainingCount <= toReceiveCount)) { base->FIFOINTENCLR = SPI_FIFOINTENCLR_TXLVL_MASK; } /* Nothing to receive or transmit, but we still have pending data which are bellow rxLevel. * Cannot clear rxFIFO, txFIFO might be still active */ - if (rxRemainingCount == 0) + if (rxRemainingCount == 0U) { - if ((handle->txRemainingBytes == 0) && (handle->toReceiveCount != 0) && - (handle->toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1)) + txRemainingBytes = handle->txRemainingBytes; + if ((txRemainingBytes == 0U) && (toReceiveCount != 0U) && + (toReceiveCount < SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) { - base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(handle->toReceiveCount - 1); + base->FIFOTRIG = (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | + SPI_FIFOTRIG_RXLVL((uint32_t)toReceiveCount - 1U); } } - /* Expected to receive less data than rxLevel value, we have to update rxLevel */ else { - if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1)) + /* Expected to receive less data than rxLevel value, we have to update rxLevel */ + if (rxRemainingCount < (SPI_FIFOTRIG_RXLVL_GET(base) + 1U)) { base->FIFOTRIG = - (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1); + (base->FIFOTRIG & (~SPI_FIFOTRIG_RXLVL_MASK)) | SPI_FIFOTRIG_RXLVL(rxRemainingCount - 1U); } } } @@ -1031,8 +1063,8 @@ void SPI_MasterTransferHandleIRQ(SPI_Type *base, spi_master_handle_t *handle) base->FIFOTRIG = (base->FIFOTRIG & (~(SPI_FIFOTRIG_RXLVL_MASK | SPI_FIFOTRIG_RXLVL_MASK))) | SPI_FIFOTRIG_RXLVL(handle->rxWatermark) | SPI_FIFOTRIG_TXLVL(handle->txWatermark); /* set idle state and call user callback */ - handle->state = kStatus_SPI_Idle; - if (handle->callback) + handle->state = (uint32_t)kStatus_SPI_Idle; + if (handle->callback != NULL) { (handle->callback)(base, handle, handle->state, handle->userData); } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.h index 6da8f899e6..2320e574cc 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -24,8 +24,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief SPI driver version 2.0.3. */ -#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*! @brief SPI driver version. */ +#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*@}*/ /*! @brief Global variable for dummy data value setting. */ @@ -36,12 +36,17 @@ extern volatile uint8_t s_dummyData[]; #define SPI_DUMMYDATA (0xFFU) #endif -#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF) -#define SPI_CTRLMASK (0xFFFF0000) +/*! @brief Retry times for waiting flag. */ +#ifndef SPI_RETRY_TIMES +#define SPI_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */ +#endif -#define SPI_ASSERTNUM_SSEL(n) ((~(1U << ((n) + 16))) & 0xF0000) -#define SPI_DEASSERTNUM_SSEL(n) (1U << ((n) + 16)) -#define SPI_DEASSERT_ALL (0xF0000) +#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFFUL) +#define SPI_CTRLMASK (0xFFFF0000U) + +#define SPI_ASSERTNUM_SSEL(n) ((~(1UL << ((n) + 16UL))) & 0xF0000UL) +#define SPI_DEASSERTNUM_SSEL(n) (1UL << ((n) + 16UL)) +#define SPI_DEASSERT_ALL (0xF0000UL) #define SPI_FIFOWR_FLAGS_MASK (~(SPI_DEASSERT_ALL | SPI_FIFOWR_TXDATA_MASK | SPI_FIFOWR_LEN_MASK)) @@ -137,9 +142,13 @@ typedef enum _spi_spol kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1), kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1), kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1), +#if defined(FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) && (FSL_FEATURE_SPI_IS_SSEL_PIN_COUNT_EQUAL_TO_THREE) + kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh), +#else kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1), kSPI_SpolActiveAllHigh = (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh), +#endif kSPI_SpolActiveAllLow = 0, } spi_spol_t; @@ -161,41 +170,42 @@ typedef struct _spi_delay_config /*! @brief SPI master user configure structure.*/ typedef struct _spi_master_config { - bool enableLoopback; /*!< Enable loopback for test purpose */ - bool enableMaster; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_ssel_t sselNum; /*!< Slave select number */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ - spi_delay_config_t delayConfig; /*!< Delay configuration. */ + bool enableLoopback; /*!< Enable loopback for test purpose */ + bool enableMaster; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_ssel_t sselNum; /*!< Slave select number */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ + spi_delay_config_t delayConfig; /*!< Delay configuration. */ } spi_master_config_t; /*! @brief SPI slave user configure structure.*/ typedef struct _spi_slave_config { - bool enableSlave; /*!< Enable SPI at initialization time */ - spi_clock_polarity_t polarity; /*!< Clock polarity */ - spi_clock_phase_t phase; /*!< Clock phase */ - spi_shift_direction_t direction; /*!< MSB or LSB */ - spi_data_width_t dataWidth; /*!< Width of the data */ - spi_spol_t sselPol; /*!< Configure active CS polarity */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + bool enableSlave; /*!< Enable SPI at initialization time */ + spi_clock_polarity_t polarity; /*!< Clock polarity */ + spi_clock_phase_t phase; /*!< Clock phase */ + spi_shift_direction_t direction; /*!< MSB or LSB */ + spi_data_width_t dataWidth; /*!< Width of the data */ + spi_spol_t sselPol; /*!< Configure active CS polarity */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ } spi_slave_config_t; /*! @brief SPI transfer status.*/ -enum _spi_status +enum { kStatus_SPI_Busy = MAKE_STATUS(kStatusGroup_LPC_SPI, 0), /*!< SPI bus is busy */ kStatus_SPI_Idle = MAKE_STATUS(kStatusGroup_LPC_SPI, 1), /*!< SPI is idle */ kStatus_SPI_Error = MAKE_STATUS(kStatusGroup_LPC_SPI, 2), /*!< SPI error */ kStatus_SPI_BaudrateNotSupport = - MAKE_STATUS(kStatusGroup_LPC_SPI, 3) /*!< Baudrate is not support in current clock source */ + MAKE_STATUS(kStatusGroup_LPC_SPI, 3), /*!< Baudrate is not support in current clock source */ + kStatus_SPI_Timeout = MAKE_STATUS(kStatusGroup_LPC_SPI, 4) /*!< SPI timeout polling status flags. */ }; /*! @brief SPI interrupt sources.*/ @@ -262,24 +272,34 @@ struct _spi_master_handle uint8_t *volatile rxData; /*!< Receive buffer */ volatile size_t txRemainingBytes; /*!< Number of data to be transmitted [in bytes] */ volatile size_t rxRemainingBytes; /*!< Number of data to be received [in bytes] */ - volatile size_t toReceiveCount; /*!< Receive data remaining in bytes */ - size_t totalByteCount; /*!< A number of transfer bytes */ - volatile uint32_t state; /*!< SPI internal state */ - spi_master_callback_t callback; /*!< SPI callback */ - void *userData; /*!< Callback parameter */ - uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ + volatile int8_t toReceiveCount; /*!< The number of data expected to receive in data width. Since the received count + and sent count should be the same to complete the transfer, if the sent count is + x and the received count is y, toReceiveCount is x-y. */ + size_t totalByteCount; /*!< A number of transfer bytes */ + volatile uint32_t state; /*!< SPI internal state */ + spi_master_callback_t callback; /*!< SPI callback */ + void *userData; /*!< Callback parameter */ + uint8_t dataWidth; /*!< Width of the data [Valid values: 1 to 16] */ uint8_t sselNum; /*!< Slave select number to be asserted when transferring data [Valid values: 0 to 3] */ uint32_t configFlags; /*!< Additional option to control transfer */ - spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ }; +/*! @brief Typedef for master interrupt handler. */ +typedef void (*flexcomm_spi_master_irq_handler_t)(SPI_Type *base, spi_master_handle_t *handle); + +/*! @brief Typedef for slave interrupt handler. */ +typedef void (*flexcomm_spi_slave_irq_handler_t)(SPI_Type *base, spi_slave_handle_t *handle); +/*! @} */ + +/******************************************************************************* + * API + ******************************************************************************/ + #if defined(__cplusplus) extern "C" { #endif -/******************************************************************************* - * API - ******************************************************************************/ /*! @brief Returns instance number for SPI peripheral base address. */ uint32_t SPI_GetInstance(SPI_Type *base); @@ -564,6 +584,7 @@ status_t SPI_MasterTransferCreateHandle(SPI_Type *base, * @param xfer pointer to spi_xfer_config_t structure * @retval kStatus_Success Successfully start a transfer. * @retval kStatus_InvalidArgument Input argument is invalid. + * @retval kStatus_SPI_Timeout The transfer timed out and was aborted. */ status_t SPI_MasterTransferBlocking(SPI_Type *base, spi_transfer_t *xfer); diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c index 3e725909c0..ed0aaa6a9f 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -37,8 +37,12 @@ typedef struct _spi_dma_txdummy uint32_t word; } spi_dma_txdummy_t; +/*! @brief Array to map SPI instance number to base address. */ +static const uint32_t s_spiBaseAddrs[] = SPI_BASE_ADDRS; + /*configFlags & (uint32_t)kSPI_FrameDelay ? (uint32_t)kSPI_FrameDelay : 0; - *fifowr |= xfer->configFlags & (uint32_t)kSPI_FrameAssert ? (uint32_t)kSPI_FrameAssert : 0; + *fifowr |= ((xfer->configFlags & (uint32_t)kSPI_FrameDelay) != 0U) ? (uint32_t)kSPI_FrameDelay : 0U; + *fifowr |= ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) ? (uint32_t)kSPI_FrameAssert : 0U; } static void SpiConfigToFifoWR(spi_config_t *config, uint32_t *fifowr) { - *fifowr |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(config->sselNum))); + *fifowr |= ((uint32_t)SPI_DEASSERT_ALL & (~(uint32_t)SPI_DEASSERTNUM_SSEL((uint32_t)config->sselNum))); /* set width of data - range asserted at entry */ *fifowr |= SPI_FIFOWR_LEN(config->dataWidth); } @@ -113,11 +117,11 @@ static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_co { if (config->dataWidth > kSPI_Data8Bits) { - *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1] << 8U) | (xfer->txData[xfer->dataSize - 2])); + *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1U] << 8U) | (xfer->txData[xfer->dataSize - 2U])); } else { - *txLastWord = xfer->txData[xfer->dataSize - 1]; + *txLastWord = xfer->txData[xfer->dataSize - 1U]; } XferToFifoWR(xfer, txLastWord); SpiConfigToFifoWR(config, txLastWord); @@ -125,15 +129,19 @@ static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_co static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p) { - uint32_t instance = SPI_GetInstance(base); - dummy->word = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); - dummy->lastWord = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]); + uint32_t instance = SPI_GetInstance(base); + uint32_t dummydata = (uint32_t)s_dummyData[instance]; + dummydata |= (uint32_t)s_dummyData[instance] << 8U; + + dummy->word = dummydata; + dummy->lastWord = dummydata; + XferToFifoWR(xfer, &dummy->word); XferToFifoWR(xfer, &dummy->lastWord); SpiConfigToFifoWR(spi_config_p, &dummy->word); SpiConfigToFifoWR(spi_config_p, &dummy->lastWord); /* Clear the end of transfer bit for continue word transfer. */ - dummy->word &= (uint32_t)(~kSPI_FrameAssert); + dummy->word &= (~(uint32_t)kSPI_FrameAssert); } /*! @@ -156,7 +164,7 @@ status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, dma_handle_t *txHandle, dma_handle_t *rxHandle) { - int32_t instance = 0; + uint32_t instance; /* check 'base' */ assert(!(NULL == base)); @@ -173,7 +181,7 @@ status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, instance = SPI_GetInstance(base); - memset(handle, 0, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); /* Set spi base to handle */ handle->txHandle = txHandle; handle->rxHandle = rxHandle; @@ -181,10 +189,10 @@ status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, handle->userData = userData; /* Set SPI state to idle */ - handle->state = kSPI_Idle; + handle->state = (uint8_t)kSPI_Idle; /* Set handle to global state */ - s_dmaPrivateHandle[instance].base = base; + s_dmaPrivateHandle[instance].base = base; s_dmaPrivateHandle[instance].handle = handle; /* Install callback for Tx dma channel */ @@ -209,98 +217,101 @@ status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base, */ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer) { - int32_t instance; + assert(!((NULL == handle) || (NULL == xfer))); + + uint32_t instance; status_t result = kStatus_Success; spi_config_t *spi_config_p; + uint32_t address; - assert(!((NULL == handle) || (NULL == xfer))); if ((NULL == handle) || (NULL == xfer)) { return kStatus_InvalidArgument; } /* Byte size is zero. */ - assert(!(xfer->dataSize == 0)); - if (xfer->dataSize == 0) + if (xfer->dataSize == 0U) { return kStatus_InvalidArgument; } /* cannot get instance from base address */ instance = SPI_GetInstance(base); - assert(!(instance < 0)); - if (instance < 0) - { - return kStatus_InvalidArgument; - } /* Check if the device is busy */ - if (handle->state == kSPI_Busy) + if (handle->state == (uint8_t)kSPI_Busy) { return kStatus_SPI_Busy; } else { - uint32_t tmp; - dma_transfer_config_t xferConfig = {0}; - spi_config_p = (spi_config_t *)SPI_GetConfig(base); + /* Clear FIFOs before transfer. */ + base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK; + base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK; - handle->state = kStatus_SPI_Busy; + dma_transfer_config_t xferConfig = {0}; + spi_config_p = (spi_config_t *)SPI_GetConfig(base); + + handle->state = (uint8_t)kSPI_Busy; handle->transferSize = xfer->dataSize; /* receive */ SPI_EnableRxDMA(base, true); - if (xfer->rxData) + address = (uint32_t)&base->FIFORD; + if (xfer->rxData != NULL) { - DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->rxData, + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->rxData, ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), xfer->dataSize, kDMA_PeripheralToMemory, NULL); } else { - DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), &s_rxDummy, + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, &s_rxDummy, ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), xfer->dataSize, kDMA_StaticToStatic, NULL); } - DMA_SubmitTransfer(handle->rxHandle, &xferConfig); + (void)DMA_SubmitTransfer(handle->rxHandle, &xferConfig); handle->rxInProgress = true; DMA_StartTransfer(handle->rxHandle); /* transmit */ SPI_EnableTxDMA(base, true); - - if (xfer->txData) + address = (uint32_t)&base->FIFOWR; + if (xfer->txData != NULL) { - if (xfer->configFlags & kSPI_FrameAssert) + if ((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) { PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p); } /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma * descriptor to send the last data. */ - if ((xfer->configFlags & kSPI_FrameAssert) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) + if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) { - dma_xfercfg_t tmp_xfercfg = {0}; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; + dma_xfercfg_t tmp_xfercfg; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = 4U; + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; tmp_xfercfg.transferCount = 1; + tmp_xfercfg.reload = false; + tmp_xfercfg.clrtrig = false; + tmp_xfercfg.intB = false; /* Create chained descriptor to transmit last word */ DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance], - ((void *)((uint32_t)&base->FIFOWR)), NULL); + (uint32_t *)address, NULL); DMA_PrepareTransfer( - &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), + &xferConfig, xfer->txData, (uint32_t *)address, ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]); /* Disable interrupts for first descriptor to avoid calling callback twice. */ xferConfig.xfercfg.intA = false; xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); if (result != kStatus_Success) { return result; @@ -309,40 +320,43 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra else { DMA_PrepareTransfer( - &xferConfig, xfer->txData, ((void *)((uint32_t)&base->FIFOWR)), + &xferConfig, xfer->txData, (uint32_t *)address, ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), xfer->dataSize, kDMA_MemoryToPeripheral, NULL); - DMA_SubmitTransfer(handle->txHandle, &xferConfig); + (void)DMA_SubmitTransfer(handle->txHandle, &xferConfig); } } else { /* Setup tx dummy data. */ SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p); - if ((xfer->configFlags & kSPI_FrameAssert) && - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1))) + if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2U) : (xfer->dataSize > 1U))) { - dma_xfercfg_t tmp_xfercfg = {0}; - tmp_xfercfg.valid = true; - tmp_xfercfg.swtrig = true; - tmp_xfercfg.intA = true; - tmp_xfercfg.byteWidth = sizeof(uint32_t); - tmp_xfercfg.srcInc = 0; - tmp_xfercfg.dstInc = 0; + dma_xfercfg_t tmp_xfercfg; + tmp_xfercfg.valid = true; + tmp_xfercfg.swtrig = true; + tmp_xfercfg.intA = true; + tmp_xfercfg.byteWidth = (uint8_t)sizeof(uint32_t); + tmp_xfercfg.srcInc = 0; + tmp_xfercfg.dstInc = 0; tmp_xfercfg.transferCount = 1; + tmp_xfercfg.reload = false; + tmp_xfercfg.clrtrig = false; + tmp_xfercfg.intB = false; /* Create chained descriptor to transmit last word */ DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord, - (void *)((uint32_t)&base->FIFOWR), NULL); + (uint32_t *)address, NULL); /* Use common API to setup first descriptor */ DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), + &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), - ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)), + ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2U) : (xfer->dataSize - 1U)), kDMA_StaticToStatic, &s_spi_descriptor_table[instance]); /* Disable interrupts for first descriptor to avoid calling callback twice */ xferConfig.xfercfg.intA = false; xferConfig.xfercfg.intB = false; - result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); + result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); if (result != kStatus_Success) { return result; @@ -351,7 +365,7 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra else { DMA_PrepareTransfer( - &xferConfig, &s_txDummy[instance].word, ((void *)((uint32_t)&base->FIFOWR)), + &xferConfig, &s_txDummy[instance].word, (uint32_t *)address, ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))), xfer->dataSize, kDMA_StaticToStatic, NULL); result = DMA_SubmitTransfer(handle->txHandle, &xferConfig); @@ -362,26 +376,27 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra } } - handle->txInProgress = true; - tmp = 0; - XferToFifoWR(xfer, &tmp); - SpiConfigToFifoWR(spi_config_p, &tmp); + handle->txInProgress = true; + uint32_t tmpData = 0U; + uint32_t writeAddress = (uint32_t) & (base->FIFOWR) + 2UL; + XferToFifoWR(xfer, &tmpData); + SpiConfigToFifoWR(spi_config_p, &tmpData); /* Setup the control info. * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO. * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR * will push the data and the current control bits into the FIFO. */ - if ((xfer->configFlags & kSPI_FrameAssert) && + if (((xfer->configFlags & (uint32_t)kSPI_FrameAssert) != 0U) && ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U))) { - *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); + *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); } else { /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */ - tmp &= (uint32_t)(~kSPI_FrameAssert); - *(((uint16_t *)((uint32_t) & (base->FIFOWR))) + 1) = (uint16_t)(tmp >> 16U); + tmpData &= (~(uint32_t)kSPI_FrameAssert); + *(uint16_t *)writeAddress = (uint16_t)(tmpData >> 16U); } DMA_StartTransfer(handle->txHandle); @@ -405,31 +420,30 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra */ status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer) { - assert(xfer); - assert(handle); + assert((xfer != NULL) && (handle != NULL)); spi_transfer_t tempXfer = {0}; status_t status; if (xfer->isTransmitFirst) { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; tempXfer.dataSize = xfer->txDataSize; } else { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; tempXfer.dataSize = xfer->rxDataSize; } /* If the pcs pin keep assert between transmit and receive. */ if (xfer->isPcsAssertInTransfer) { - tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert); + tempXfer.configFlags = (xfer->configFlags) & (~(uint32_t)kSPI_FrameAssert); } else { - tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert; + tempXfer.configFlags = (xfer->configFlags) | (uint32_t)kSPI_FrameAssert; } status = SPI_MasterTransferBlocking(base, &tempXfer); @@ -440,14 +454,14 @@ status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handl if (xfer->isTransmitFirst) { - tempXfer.txData = NULL; - tempXfer.rxData = xfer->rxData; + tempXfer.txData = NULL; + tempXfer.rxData = xfer->rxData; tempXfer.dataSize = xfer->rxDataSize; } else { - tempXfer.txData = xfer->txData; - tempXfer.rxData = NULL; + tempXfer.txData = xfer->txData; + tempXfer.rxData = NULL; tempXfer.dataSize = xfer->txDataSize; } tempXfer.configFlags = xfer->configFlags; @@ -460,8 +474,8 @@ status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handl static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) { spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; /* change the state */ spiHandle->rxInProgress = false; @@ -469,8 +483,8 @@ static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transfe /* All finished, call the callback */ if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) { - spiHandle->state = kSPI_Idle; - if (spiHandle->callback) + spiHandle->state = (uint8_t)kSPI_Idle; + if (spiHandle->callback != NULL) { (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); } @@ -480,8 +494,8 @@ static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transfe static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode) { spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData; - spi_dma_handle_t *spiHandle = privHandle->handle; - SPI_Type *base = privHandle->base; + spi_dma_handle_t *spiHandle = privHandle->handle; + SPI_Type *base = privHandle->base; /* change the state */ spiHandle->txInProgress = false; @@ -489,8 +503,8 @@ static void SPI_TxDMACallback(dma_handle_t *handle, void *userData, bool transfe /* All finished, call the callback */ if ((spiHandle->txInProgress == false) && (spiHandle->rxInProgress == false)) { - spiHandle->state = kSPI_Idle; - if (spiHandle->callback) + spiHandle->state = (uint8_t)kSPI_Idle; + if (spiHandle->callback != NULL) { (spiHandle->callback)(base, spiHandle, kStatus_Success, spiHandle->userData); } @@ -515,7 +529,7 @@ void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) /* Set the handle state */ handle->txInProgress = false; handle->rxInProgress = false; - handle->state = kSPI_Idle; + handle->state = (uint8_t)kSPI_Idle; } /*! @@ -530,15 +544,15 @@ void SPI_MasterTransferAbortDMA(SPI_Type *base, spi_dma_handle_t *handle) */ status_t SPI_MasterTransferGetCountDMA(SPI_Type *base, spi_dma_handle_t *handle, size_t *count) { - assert(handle); + assert(handle != NULL); - if (!count) + if (NULL == count) { return kStatus_InvalidArgument; } /* Catch when there is not an active transfer. */ - if (handle->state != kSPI_Busy) + if (handle->state != (uint8_t)kSPI_Busy) { *count = 0; return kStatus_NoTransferInProgress; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h index 9fd388a7a8..614c37d791 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_dma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -24,8 +24,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief SPI DMA driver version 2.0.3. */ -#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*! @brief SPI DMA driver version 2.1.1. */ +#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) /*@}*/ typedef struct _spi_dma_handle spi_dma_handle_t; @@ -105,7 +105,7 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra * * @param base SPI base pointer * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. - * @param transfer A pointer to the spi_half_duplex_transfer_t structure. + * @param xfer A pointer to the spi_half_duplex_transfer_t structure. * @return status of status_t. */ status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.c new file mode 100644 index 0000000000..8250107418 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.c @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_spi_freertos.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_spi_freertos" +#endif + +static void SPI_RTOS_Callback(SPI_Type *base, spi_master_handle_t *drv_handle, status_t status, void *userData) +{ + spi_rtos_handle_t *handle = (spi_rtos_handle_t *)userData; + BaseType_t reschedule; + handle->async_status = status; + (void)xSemaphoreGiveFromISR(handle->event, &reschedule); + portYIELD_FROM_ISR(reschedule); +} + +/*! + * brief Initializes SPI. + * + * This function initializes the SPI module and related RTOS context. + * + * param handle The RTOS SPI handle, the pointer to an allocated space for RTOS context. + * param base The pointer base address of the SPI instance to initialize. + * param masterConfig Configuration structure to set-up SPI in master mode. + * param srcClock_Hz Frequency of input clock of the SPI module. + * return status of the operation. + */ +status_t SPI_RTOS_Init(spi_rtos_handle_t *handle, + SPI_Type *base, + const spi_master_config_t *masterConfig, + uint32_t srcClock_Hz) +{ + status_t status; + + if (handle == NULL) + { + return kStatus_InvalidArgument; + } + + if (base == NULL) + { + return kStatus_InvalidArgument; + } + + (void)memset(handle, 0, sizeof(spi_rtos_handle_t)); + + handle->mutex = xSemaphoreCreateMutex(); + if (handle->mutex == NULL) + { + return kStatus_Fail; + } + + handle->event = xSemaphoreCreateBinary(); + if (handle->event == NULL) + { + vSemaphoreDelete(handle->mutex); + return kStatus_Fail; + } + + handle->base = base; + + (void)SPI_MasterInit(handle->base, masterConfig, srcClock_Hz); + status = SPI_MasterTransferCreateHandle(handle->base, &handle->drv_handle, SPI_RTOS_Callback, (void *)handle); + + return status; +} + +/*! + * brief Deinitializes the SPI. + * + * This function deinitializes the SPI module and related RTOS context. + * + * param handle The RTOS SPI handle. + */ +status_t SPI_RTOS_Deinit(spi_rtos_handle_t *handle) +{ + SPI_Deinit(handle->base); + vSemaphoreDelete(handle->event); + vSemaphoreDelete(handle->mutex); + + return kStatus_Success; +} + +/*! + * brief Performs SPI transfer. + * + * This function performs an SPI transfer according to data given in the transfer structure. + * + * param handle The RTOS SPI handle. + * param transfer Structure specifying the transfer parameters. + * return status of the operation. + */ +status_t SPI_RTOS_Transfer(spi_rtos_handle_t *handle, spi_transfer_t *transfer) +{ + status_t status; + + /* Lock resource mutex */ + if (xSemaphoreTake(handle->mutex, portMAX_DELAY) != pdTRUE) + { + return kStatus_SPI_Busy; + } + + /* Initiate transfer */ + status = SPI_MasterTransferNonBlocking(handle->base, &handle->drv_handle, transfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->mutex); + return status; + } + + /* Wait for transfer to finish */ + if (xSemaphoreTake(handle->event, portMAX_DELAY) != pdTRUE) + { + return kStatus_SPI_Error; + } + + /* Retrieve status before releasing mutex */ + status = handle->async_status; + + /* Unlock resource mutex */ + (void)xSemaphoreGive(handle->mutex); + + /* Translate status of underlying driver */ + if (status == kStatus_SPI_Idle) + { + status = kStatus_Success; + } + + return status; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.h new file mode 100644 index 0000000000..c5a0efa2cc --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_spi_freertos.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __FSL_SPI_FREERTOS_H__ +#define __FSL_SPI_FREERTOS_H__ + +#include "FreeRTOS.h" +#include "portable.h" +#include "semphr.h" + +#include "fsl_spi.h" + +/*! + * @addtogroup spi_freertos_driver + * @{ + */ + +/*! @file */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief SPI FreeRTOS driver version 2.1.0. */ +#define FSL_SPI_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*@}*/ + +/*! @brief SPI FreeRTOS handle */ +typedef struct _spi_rtos_handle +{ + SPI_Type *base; /*!< SPI base address */ + spi_master_handle_t drv_handle; /*!< Handle of the underlying driver, treated as opaque by the RTOS layer */ + status_t async_status; + SemaphoreHandle_t mutex; /*!< Mutex to lock the handle during a trasfer */ + SemaphoreHandle_t event; /*!< Semaphore to notify and unblock task when transfer ends */ +} spi_rtos_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SPI RTOS Operation + * @{ + */ + +/*! + * @brief Initializes SPI. + * + * This function initializes the SPI module and related RTOS context. + * + * @param handle The RTOS SPI handle, the pointer to an allocated space for RTOS context. + * @param base The pointer base address of the SPI instance to initialize. + * @param masterConfig Configuration structure to set-up SPI in master mode. + * @param srcClock_Hz Frequency of input clock of the SPI module. + * @return status of the operation. + */ +status_t SPI_RTOS_Init(spi_rtos_handle_t *handle, + SPI_Type *base, + const spi_master_config_t *masterConfig, + uint32_t srcClock_Hz); + +/*! + * @brief Deinitializes the SPI. + * + * This function deinitializes the SPI module and related RTOS context. + * + * @param handle The RTOS SPI handle. + */ +status_t SPI_RTOS_Deinit(spi_rtos_handle_t *handle); + +/*! + * @brief Performs SPI transfer. + * + * This function performs an SPI transfer according to data given in the transfer structure. + * + * @param handle The RTOS SPI handle. + * @param transfer Structure specifying the transfer parameters. + * @return status of the operation. + */ +status_t SPI_RTOS_Transfer(spi_rtos_handle_t *handle, spi_transfer_t *transfer); + +/*! + * @} + */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* __FSL_SPI_FREERTOS_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c index c62f96dacb..1d0dd9ccf6 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.c @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2019 NXP * All rights reserved. * * @@ -109,8 +109,8 @@ void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrl { uint32_t tempReg = base->FCCTRLSEL[flexCommIndex]; - tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK << signal); - tempReg |= (set + 1U) << signal; + tempReg &= ~((uint32_t)SYSCTL_FCCTRLSEL_SCKINSEL_MASK << (uint32_t)signal); + tempReg |= (set + 1U) << (uint32_t)signal; SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg); } @@ -155,24 +155,21 @@ void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, uint32_t sckShareSrc, uint32_t wsShareSrc, uint32_t dataInShareSrc, - uint32_t dataOutMask) + uint32_t dataOutShareSrc) { uint32_t tempReg = base->SHAREDCTRLSET[setIndex]; /* WS,SCK,DATA IN */ - tempReg &= - ~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK | - SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK); - tempReg |= SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) | - SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) | - SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc); + tempReg &= ~(SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_MASK | + SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_MASK); + tempReg |= SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) | SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) | + SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc); /* data out */ - tempReg &= - ~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK | - SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK | - SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK); - tempReg |= dataOutMask; + tempReg &= ~(SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK | + SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK | SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK | + SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK); + tempReg |= dataOutShareSrc; SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); } @@ -194,12 +191,12 @@ void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, if (signal == kSYSCTL_SharedCtrlSignalDataOut) { - tempReg |= 1 << (signal + shareSrc); + tempReg |= 1UL << ((uint32_t)signal + shareSrc); } else { - tempReg &= ~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK << signal); - tempReg |= shareSrc << signal; + tempReg &= ~((uint32_t)SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_MASK << (uint32_t)signal); + tempReg |= shareSrc << (uint32_t)signal; } SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg); diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h index edeb0ecd21..0a1be88469 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_sysctl.h @@ -1,5 +1,5 @@ /* - * Copyright 2018 NXP + * Copyright 2019 NXP * All rights reserved. * * @@ -29,7 +29,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief Group sysctl driver version for SDK */ -#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */ +#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*!< Version 2.0.5. */ /*@}*/ /*! @brief SYSCTL share set*/ @@ -63,22 +63,22 @@ enum _sysctl_share_src /*! @brief SYSCTL shared data out mask */ enum _sysctl_dataout_mask { - kSYSCTL_Flexcomm0DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */ - kSYSCTL_Flexcomm1DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */ - kSYSCTL_Flexcomm2DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK, /*!< share set 2 */ - kSYSCTL_Flexcomm4DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */ - kSYSCTL_Flexcomm5DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */ - kSYSCTL_Flexcomm6DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */ - kSYSCTL_Flexcomm7DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */ + kSYSCTL_Flexcomm0DataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */ + kSYSCTL_Flexcomm1DataOut = SYSCTL_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */ + kSYSCTL_Flexcomm2DataOut = SYSCTL_SHAREDCTRLSET_FC2DATAOUTEN_MASK, /*!< share set 2 */ + kSYSCTL_Flexcomm4DataOut = SYSCTL_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */ + kSYSCTL_Flexcomm5DataOut = SYSCTL_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */ + kSYSCTL_Flexcomm6DataOut = SYSCTL_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */ + kSYSCTL_Flexcomm7DataOut = SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */ }; /*! @brief SYSCTL flexcomm signal */ typedef enum _sysctl_sharedctrlset_signal { - kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */ - kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */ - kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */ - kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */ + kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */ + kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */ + kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */ + kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */ } sysctl_sharedctrlset_signal_t; /******************************************************************************* * API @@ -138,7 +138,7 @@ void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base, * @param base Base address of the SYSCTL peripheral * @param flexCommIndex index of flexcomm,reference _sysctl_share_src * @param signal FCCTRLSEL signal shift - * @param setIndex share set for sck, reference _sysctl_share_set_index + * @param set share set for sck, reference _sysctl_share_set_index * */ void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set); @@ -166,7 +166,8 @@ void SYSCTL_SetShareSetSrc(SYSCTL_Type *base, * * @param base Base address of the SYSCTL peripheral * @param setIndex index of share set, reference _sysctl_share_set_index - * @param sckShareSrc sck source fro this share set,reference _sysctl_share_src + * @param signal FCCTRLSEL signal shift + * @param shareSrc sck source fro this share set,reference _sysctl_share_src * */ void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base, diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.c index 5df14ed839..3286174f27 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2022 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -10,12 +10,25 @@ #include "fsl_device_registers.h" #include "fsl_flexcomm.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID #define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart" #endif -enum _usart_transfer_states +/*! + * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t` + */ +typedef union usart_to_flexcomm +{ + flexcomm_usart_irq_handler_t usart_master_handler; + flexcomm_irq_handler_t flexcomm_handler; +} usart_to_flexcomm_t; + +enum { kUSART_TxIdle, /* TX idle. */ kUSART_TxBusy, /* TX busy. */ @@ -41,18 +54,18 @@ static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE /*! brief Returns instance number for USART peripheral base address. */ uint32_t USART_GetInstance(USART_Type *base) { - int i; + uint32_t i; - for (i = 0; i < FSL_FEATURE_SOC_USART_COUNT; i++) + for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++) { if ((uint32_t)base == s_usartBaseAddrs[i]) { - return i; + break; } } - assert(false); - return 0; + assert(i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT); + return i; } /*! @@ -67,14 +80,16 @@ size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle) /* Check arguments */ assert(NULL != handle); + uint16_t rxRingBufferHead = handle->rxRingBufferHead; + uint16_t rxRingBufferTail = handle->rxRingBufferTail; - if (handle->rxRingBufferTail > handle->rxRingBufferHead) + if (rxRingBufferTail > rxRingBufferHead) { - size = (size_t)(handle->rxRingBufferHead + handle->rxRingBufferSize - handle->rxRingBufferTail); + size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail; } else { - size = (size_t)(handle->rxRingBufferHead - handle->rxRingBufferTail); + size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail; } return size; } @@ -127,7 +142,7 @@ void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uin handle->rxRingBufferHead = 0U; handle->rxRingBufferTail = 0U; /* ring buffer is ready we can start receiving data */ - base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; } /*! @@ -144,7 +159,7 @@ void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle) assert(NULL != base); assert(NULL != handle); - if (handle->rxState == kUSART_RxIdle) + if (handle->rxState == (uint8_t)kUSART_RxIdle) { base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK; } @@ -180,8 +195,8 @@ status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t src int result; /* check arguments */ - assert(!((NULL == base) || (NULL == config) || (0 == srcClock_Hz))); - if ((NULL == base) || (NULL == config) || (0 == srcClock_Hz)) + assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz))); + if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz)) { return kStatus_InvalidArgument; } @@ -217,14 +232,29 @@ status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t src /* setup configuration and enable USART */ base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) | USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) | - USART_CFG_SYNCEN(config->syncMode >> 1) | USART_CFG_SYNCMST(config->syncMode) | - USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_ENABLE_MASK; + USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) | + USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_MODE32K(config->enableMode32k) | + USART_CFG_CTSEN(config->enableHardwareFlowControl) | USART_CFG_ENABLE_MASK; /* Setup baudrate */ - result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); - if (kStatus_Success != result) + if (config->enableMode32k) { - return result; + if ((9600U % config->baudRate_Bps) == 0U) + { + base->BRG = 9600U / config->baudRate_Bps; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } } /* Setting continuous Clock configuration. used for synchronous mode. */ USART_EnableContinuousSCLK(base, config->enableContinuousSCLK); @@ -243,7 +273,7 @@ void USART_Deinit(USART_Type *base) { /* Check arguments */ assert(NULL != base); - while (!(base->STAT & USART_STAT_TXIDLE_MASK)) + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) { } /* Disable interrupts, disable dma requests, disable peripheral */ @@ -274,21 +304,23 @@ void USART_GetDefaultConfig(usart_config_t *config) assert(NULL != config); /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); /* Set always all members ! */ - config->baudRate_Bps = 115200U; - config->parityMode = kUSART_ParityDisabled; - config->stopBitCount = kUSART_OneStopBit; - config->bitCountPerChar = kUSART_8BitsPerChar; - config->loopback = false; - config->enableRx = false; - config->enableTx = false; - config->txWatermark = kUSART_TxFifo0; - config->rxWatermark = kUSART_RxFifo1; - config->syncMode = kUSART_SyncModeDisabled; - config->enableContinuousSCLK = false; - config->clockPolarity = kUSART_RxSampleOnFallingEdge; + config->baudRate_Bps = 115200U; + config->parityMode = kUSART_ParityDisabled; + config->stopBitCount = kUSART_OneStopBit; + config->bitCountPerChar = kUSART_8BitsPerChar; + config->loopback = false; + config->enableRx = false; + config->enableTx = false; + config->enableMode32k = false; + config->txWatermark = kUSART_TxFifo0; + config->rxWatermark = kUSART_RxFifo1; + config->syncMode = kUSART_SyncModeDisabled; + config->enableContinuousSCLK = false; + config->clockPolarity = kUSART_RxSampleOnFallingEdge; + config->enableHardwareFlowControl = false; } /*! @@ -313,19 +345,19 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src uint32_t osrval, brgval, diff, baudrate; /* check arguments */ - assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz))); - if ((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)) + assert(!((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))); + if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz)) { return kStatus_InvalidArgument; } /* If synchronous master mode is enabled, only configure the BRG value. */ - if (base->CFG & USART_CFG_SYNCEN_MASK) + if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U) { - if (base->CFG & USART_CFG_SYNCMST_MASK) + if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U) { brgval = srcClock_Hz / baudrate_Bps; - base->BRG = brgval - 1; + base->BRG = brgval - 1U; } } else @@ -334,15 +366,15 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src * Smaller values of OSR can make the sampling position within a data bit less accurate and may * potentially cause more noise errors or incorrect data. */ - for (osrval = best_osrval; osrval >= 8; osrval--) + for (osrval = best_osrval; osrval >= 8U; osrval--) { - brgval = (srcClock_Hz / ((osrval + 1) * baudrate_Bps)) - 1; - if (brgval > 0xFFFF) + brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U; + if (brgval > 0xFFFFU) { continue; } - baudrate = srcClock_Hz / ((osrval + 1) * (brgval + 1)); - diff = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate; + baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U)); + diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); if (diff < best_diff) { best_diff = diff; @@ -351,8 +383,17 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src } } + /* Check to see if actual baud rate is within 3% of desired baud rate + * based on the best calculated OSR and BRG value */ + baudrate = srcClock_Hz / ((best_osrval + 1U) * (best_brgval + 1U)); + diff = (baudrate_Bps < baudrate) ? (baudrate - baudrate_Bps) : (baudrate_Bps - baudrate); + if (diff > ((baudrate_Bps / 100U) * 3U)) + { + return kStatus_USART_BaudrateNotSupport; + } + /* value over range */ - if (best_brgval > 0xFFFF) + if (best_brgval > 0xFFFFU) { return kStatus_USART_BaudrateNotSupport; } @@ -364,6 +405,93 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src return kStatus_Success; } +/*! + * brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source. + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * param base USART peripheral base address. + * param baudRate_Bps USART baudrate to be set.. + * param enableMode32k true is 32k mode, false is normal mode. + * param srcClock_Hz USART clock source frequency in HZ. + * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * retval kStatus_Success Set baudrate succeed. + * retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz) +{ + status_t result = kStatus_Success; + base->CFG &= ~(USART_CFG_ENABLE_MASK); + if (enableMode32k) + { + base->CFG |= USART_CFG_MODE32K_MASK; + if ((9600U % baudRate_Bps) == 0U) + { + base->BRG = 9600U / baudRate_Bps - 1U; + } + else + { + return kStatus_USART_BaudrateNotSupport; + } + } + else + { + base->CFG &= ~(USART_CFG_MODE32K_MASK); + result = USART_SetBaudRate(base, baudRate_Bps, srcClock_Hz); + if (kStatus_Success != result) + { + return result; + } + } + base->CFG |= USART_CFG_ENABLE_MASK; + return result; +} + +/*! + * brief Enable 9-bit data mode for USART. + * + * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. + * + * param base USART peripheral base address. + * param enable true to enable, false to disable. + */ +void USART_Enable9bitMode(USART_Type *base, bool enable) +{ + assert(base != NULL); + + uint32_t temp = 0U; + + if (enable) + { + /* Set USART 9-bit mode, disable parity. */ + temp = base->CFG & ~((uint32_t)USART_CFG_DATALEN_MASK | (uint32_t)USART_CFG_PARITYSEL_MASK); + temp |= (uint32_t)USART_CFG_DATALEN(0x2U); + base->CFG = temp; + } + else + { + /* Set USART to 8-bit mode. */ + base->CFG &= ~((uint32_t)USART_CFG_DATALEN_MASK); + base->CFG |= (uint32_t)USART_CFG_DATALEN(0x1U); + } +} + +/*! + * brief Transmit an address frame in 9-bit data mode. + * + * param base USART peripheral base address. + * param address USART slave address. + */ +void USART_SendAddress(USART_Type *base, uint8_t address) +{ + assert(base != NULL); + base->FIFOWR = ((uint32_t)address | 0x100UL); +} + /*! * brief Writes to the TX register using a blocking method. * @@ -373,33 +501,62 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src * param base USART peripheral base address. * param data Start address of the data to write. * param length Size of the data to write. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. + * retval kStatus_InvalidArgument Invalid argument. + * retval kStatus_Success Successfully wrote all data. */ -void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) { /* Check arguments */ assert(!((NULL == base) || (NULL == data))); +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif if ((NULL == base) || (NULL == data)) { - return; + return kStatus_InvalidArgument; } /* Check whether txFIFO is enabled */ - if (!(base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) + if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK)) { - return; + return kStatus_InvalidArgument; } - for (; length > 0; length--) + for (; length > 0U; length--) { /* Loop until txFIFO get some space for new data */ - while (!(base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) +#endif { } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif base->FIFOWR = *data; data++; } /* Wait to finish transfer */ - while (!(base->STAT & USART_STAT_TXIDLE_MASK)) +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while ((0U == (base->STAT & USART_STAT_TXIDLE_MASK)) && (--waitTimes != 0U)) +#else + while (0U == (base->STAT & USART_STAT_TXIDLE_MASK)) +#endif { } +#if UART_RETRY_TIMES + if (0U == waitTimes) + { + return kStatus_USART_Timeout; + } +#endif + return kStatus_Success; } /*! @@ -415,11 +572,16 @@ void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length) * retval kStatus_USART_ParityError Noise error happened while receiving data. * retval kStatus_USART_NoiseError Framing error happened while receiving data. * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * retval kStatus_USART_Timeout Transmission timed out and was aborted. * retval kStatus_Success Successfully received all data. */ status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) { - uint32_t status; + uint32_t statusFlag; + status_t status = kStatus_Success; +#if UART_RETRY_TIMES + uint32_t waitTimes; +#endif /* check arguments */ assert(!((NULL == base) || (NULL == data))); @@ -429,45 +591,64 @@ status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length) } /* Check whether rxFIFO is enabled */ - if (!(base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK)) + if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U) { return kStatus_Fail; } - for (; length > 0; length--) + for (; length > 0U; length--) { /* loop until rxFIFO have some data to read */ - while (!(base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) +#if UART_RETRY_TIMES + waitTimes = UART_RETRY_TIMES; + while (((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) && (--waitTimes != 0U)) +#else + while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U) +#endif { } - /* check receive status */ - status = base->STAT; - if (status & USART_STAT_FRAMERRINT_MASK) +#if UART_RETRY_TIMES + if (waitTimes == 0U) { - base->STAT |= USART_STAT_FRAMERRINT_MASK; - return kStatus_USART_FramingError; + status = kStatus_USART_Timeout; + break; } - if (status & USART_STAT_PARITYERRINT_MASK) - { - base->STAT |= USART_STAT_PARITYERRINT_MASK; - return kStatus_USART_ParityError; - } - if (status & USART_STAT_RXNOISEINT_MASK) - { - base->STAT |= USART_STAT_RXNOISEINT_MASK; - return kStatus_USART_NoiseError; - } - /* check rxFIFO status */ - if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) +#endif + /* check rxFIFO statusFlag */ + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) { base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; - return kStatus_USART_RxError; + status = kStatus_USART_RxError; + break; + } + /* check receive statusFlag */ + statusFlag = base->STAT; + /* Clear all status flags */ + base->STAT |= statusFlag; + if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U) + { + status = kStatus_USART_ParityError; + } + if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U) + { + status = kStatus_USART_FramingError; + } + if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U) + { + status = kStatus_USART_NoiseError; } - *data = base->FIFORD; - data++; + if (kStatus_Success == status) + { + *data = (uint8_t)base->FIFORD; + data++; + } + else + { + break; + } } - return kStatus_Success; + return status; } /*! @@ -487,10 +668,13 @@ status_t USART_TransferCreateHandle(USART_Type *base, usart_transfer_callback_t callback, void *userData) { - int32_t instance = 0; - /* Check 'base' */ assert(!((NULL == base) || (NULL == handle))); + + uint32_t instance = 0; + usart_to_flexcomm_t handler; + handler.usart_master_handler = USART_TransferHandleIRQ; + if ((NULL == base) || (NULL == handle)) { return kStatus_InvalidArgument; @@ -498,20 +682,20 @@ status_t USART_TransferCreateHandle(USART_Type *base, instance = USART_GetInstance(base); - memset(handle, 0, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); /* Set the TX/RX state. */ - handle->rxState = kUSART_RxIdle; - handle->txState = kUSART_TxIdle; + handle->rxState = (uint8_t)kUSART_RxIdle; + handle->txState = (uint8_t)kUSART_TxIdle; /* Set the callback and user data. */ handle->callback = callback; handle->userData = userData; - handle->rxWatermark = (usart_rxfifo_watermark_t)USART_FIFOTRIG_RXLVL_GET(base); - handle->txWatermark = (usart_txfifo_watermark_t)USART_FIFOTRIG_TXLVL_GET(base); + handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base); + handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base); - FLEXCOMM_SetIRQHandler(base, (flexcomm_irq_handler_t)USART_TransferHandleIRQ, handle); + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); /* Enable interrupt in NVIC. */ - EnableIRQ(s_usartIRQ[instance]); + (void)EnableIRQ(s_usartIRQ[instance]); return kStatus_Success; } @@ -524,13 +708,9 @@ status_t USART_TransferCreateHandle(USART_Type *base, * all data is written to the TX register in the IRQ handler, the USART driver calls the callback * function and passes the ref kStatus_USART_TxIdle as status parameter. * - * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. - * * param base USART peripheral base address. * param handle USART handle pointer. - * param xfer USART transfer structure. See #usart_transfer_t. + * param xfer USART transfer structure. See #usart_transfer_t. * retval kStatus_Success Successfully start the data transmission. * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet. * retval kStatus_InvalidArgument Invalid argument. @@ -544,25 +724,29 @@ status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, return kStatus_InvalidArgument; } /* Check xfer members */ - assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); - if ((0 == xfer->dataSize) || (NULL == xfer->data)) + assert(!((0U == xfer->dataSize) || (NULL == xfer->txData))); + if ((0U == xfer->dataSize) || (NULL == xfer->txData)) { return kStatus_InvalidArgument; } /* Return error if current TX busy. */ - if (kUSART_TxBusy == handle->txState) + if ((uint8_t)kUSART_TxBusy == handle->txState) { return kStatus_USART_TxBusy; } else { - handle->txData = xfer->data; + /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up the + * handle value. */ + uint32_t interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + handle->txData = xfer->txData; handle->txDataSize = xfer->dataSize; handle->txDataSizeAll = xfer->dataSize; - handle->txState = kUSART_TxBusy; - /* Enable transmiter interrupt. */ - base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK; + handle->txState = (uint8_t)kUSART_TxBusy; + /* Enable transmiter interrupt and the previously disabled interrupt. */ + USART_EnableInterrupts(base, interruptMask | (uint32_t)kUSART_TxLevelInterruptEnable); } return kStatus_Success; } @@ -581,19 +765,18 @@ void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle) assert(NULL != handle); /* Disable interrupts */ - USART_DisableInterrupts(base, kUSART_TxLevelInterruptEnable); + USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable); /* Empty txFIFO */ base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK; - handle->txDataSize = 0; - handle->txState = kUSART_TxIdle; + handle->txDataSize = 0U; + handle->txState = (uint8_t)kUSART_TxIdle; } /*! - * brief Get the number of bytes that have been written to USART TX register. + * brief Get the number of bytes that have been sent out to bus. * - * This function gets the number of bytes that have been written to USART TX - * register by interrupt method. + * This function gets the number of bytes that have been sent out to bus by interrupt method. * * param base USART peripheral base address. * param handle USART handle pointer. @@ -607,12 +790,13 @@ status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, ui assert(NULL != handle); assert(NULL != count); - if (kUSART_TxIdle == handle->txState) + if ((uint8_t)kUSART_TxIdle == handle->txState) { return kStatus_NoTransferInProgress; } - *count = handle->txDataSizeAll - handle->txDataSize; + *count = handle->txDataSizeAll - handle->txDataSize - + ((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); return kStatus_Success; } @@ -655,7 +839,7 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base, size_t bytesToReceive; /* How many bytes currently have received. */ size_t bytesCurrentReceived; - uint32_t regPrimask = 0U; + uint32_t interruptMask = 0U; /* Check arguments */ assert(!((NULL == base) || (NULL == handle) || (NULL == xfer))); @@ -664,12 +848,18 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base, return kStatus_InvalidArgument; } /* Check xfer members */ - assert(!((0 == xfer->dataSize) || (NULL == xfer->data))); - if ((0 == xfer->dataSize) || (NULL == xfer->data)) + assert(!((0U == xfer->dataSize) || (NULL == xfer->rxData))); + if ((0U == xfer->dataSize) || (NULL == xfer->rxData)) { return kStatus_InvalidArgument; } + /* Enable address detect when address match is enabled. */ + if ((base->CFG & (uint32_t)USART_CFG_AUTOADDR_MASK) != 0U) + { + base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; + } + /* How to get data: 1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize to uart handle, enable interrupt to store received data to xfer->data. When @@ -679,7 +869,7 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base, If there are not enough data in ring buffer, copy all of them to xfer->data, save the xfer->data remained empty space to uart handle, receive data to this empty space and trigger callback when finished. */ - if (kUSART_RxBusy == handle->rxState) + if ((uint8_t)kUSART_RxBusy == handle->rxState) { return kStatus_USART_RxBusy; } @@ -688,22 +878,24 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base, bytesToReceive = xfer->dataSize; bytesCurrentReceived = 0U; /* If RX ring buffer is used. */ - if (handle->rxRingBuffer) + if (handle->rxRingBuffer != NULL) { /* Disable IRQ, protect ring buffer. */ - regPrimask = DisableGlobalIRQ(); + interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + /* How many bytes in RX ring buffer currently. */ bytesToCopy = USART_TransferGetRxRingBufferLength(handle); - if (bytesToCopy) + if (bytesToCopy != 0U) { bytesToCopy = MIN(bytesToReceive, bytesToCopy); bytesToReceive -= bytesToCopy; /* Copy data from ring buffer to user memory. */ for (i = 0U; i < bytesToCopy; i++) { - xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; + xfer->rxData[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail]; /* Wrap to 0. Not use modulo (%) because it might be large and slow. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) { handle->rxRingBufferTail = 0U; } @@ -714,20 +906,20 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base, } } /* If ring buffer does not have enough data, still need to read more data. */ - if (bytesToReceive) + if (bytesToReceive != 0U) { /* No data in ring buffer, save the request to UART handle. */ - handle->rxData = xfer->data + bytesCurrentReceived; + handle->rxData = xfer->rxData + bytesCurrentReceived; handle->rxDataSize = bytesToReceive; - handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUSART_RxBusy; + handle->rxDataSizeAll = xfer->dataSize; + handle->rxState = (uint8_t)kUSART_RxBusy; } - /* Enable IRQ if previously enabled. */ - EnableGlobalIRQ(regPrimask); + /* Re-enable IRQ. */ + USART_EnableInterrupts(base, interruptMask); /* Call user callback since all data are received. */ - if (0 == bytesToReceive) + if (0U == bytesToReceive) { - if (handle->callback) + if (handle->callback != NULL) { handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); } @@ -736,16 +928,22 @@ status_t USART_TransferReceiveNonBlocking(USART_Type *base, /* Ring buffer not used. */ else { - handle->rxData = xfer->data + bytesCurrentReceived; + /* Disable IRQ when configuring transfer handle, in case interrupt occurs during the process and messes up + * the handle value. */ + interruptMask = USART_GetEnabledInterrupts(base); + USART_DisableInterrupts(base, interruptMask); + handle->rxData = xfer->rxData + bytesCurrentReceived; handle->rxDataSize = bytesToReceive; handle->rxDataSizeAll = bytesToReceive; - handle->rxState = kUSART_RxBusy; + handle->rxState = (uint8_t)kUSART_RxBusy; /* Enable RX interrupt. */ - base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK; + base->FIFOINTENSET = USART_FIFOINTENSET_RXLVL_MASK; + /* Re-enable IRQ. */ + USART_EnableInterrupts(base, interruptMask); } /* Return the how many bytes have read. */ - if (receivedBytes) + if (receivedBytes != NULL) { *receivedBytes = bytesCurrentReceived; } @@ -767,16 +965,16 @@ void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle) assert(NULL != handle); /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */ - if (!handle->rxRingBuffer) + if (NULL == handle->rxRingBuffer) { /* Disable interrupts */ - USART_DisableInterrupts(base, kUSART_RxLevelInterruptEnable); + USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable); /* Empty rxFIFO */ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; } handle->rxDataSize = 0U; - handle->rxState = kUSART_RxIdle; + handle->rxState = (uint8_t)kUSART_RxIdle; } /*! @@ -796,7 +994,7 @@ status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, assert(NULL != handle); assert(NULL != count); - if (kUSART_RxIdle == handle->rxState) + if ((uint8_t)kUSART_RxIdle == handle->rxState) { return kStatus_NoTransferInProgress; } @@ -819,43 +1017,98 @@ void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) /* Check arguments */ assert((NULL != base) && (NULL != handle)); - bool receiveEnabled = (handle->rxDataSize) || (handle->rxRingBuffer); - bool sendEnabled = handle->txDataSize; + bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + bool sendEnabled = (handle->txDataSize != 0U); + uint8_t rxdata; + size_t tmpsize; /* If RX overrun. */ - if (base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) + if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U) { /* Clear rx error state. */ base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK; /* clear rxFIFO */ base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; /* Trigger callback. */ - if (handle->callback) + if (handle->callback != NULL) { handle->callback(base, handle, kStatus_USART_RxError, handle->userData); } } - while ((receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) || - (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))) + /* TX under run, happens when slave is in synchronous mode and the data is not written in tx register in time. */ + if ((base->FIFOSTAT & USART_FIFOSTAT_TXERR_MASK) != 0U) + { + /* Clear tx error state. */ + base->FIFOSTAT |= USART_FIFOSTAT_TXERR_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxError, handle->userData); + } + } + /* If noise error. */ + if ((base->STAT & USART_STAT_RXNOISEINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_RXNOISEINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_NoiseError, handle->userData); + } + } + /* If framing error. */ + if ((base->STAT & USART_STAT_FRAMERRINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_FRAMERRINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_FramingError, handle->userData); + } + } + /* If parity error. */ + if ((base->STAT & USART_STAT_PARITYERRINT_MASK) != 0U) + { + /* Clear rx error state. */ + base->STAT |= USART_STAT_PARITYERRINT_MASK; + /* clear rxFIFO */ + base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK; + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_ParityError, handle->userData); + } + } + while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) || + (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))) { /* Receive data */ - if (receiveEnabled && (base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK)) + if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) { + /* Clear address detect when RXFIFO has data. */ + base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; /* Receive to app bufffer if app buffer is present */ - if (handle->rxDataSize) + if (handle->rxDataSize != 0U) { - *handle->rxData = base->FIFORD; + rxdata = (uint8_t)base->FIFORD; + *handle->rxData = rxdata; handle->rxDataSize--; handle->rxData++; - receiveEnabled = ((handle->rxDataSize != 0) || (handle->rxRingBuffer)); - if (!handle->rxDataSize) + receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL)); + if (0U == handle->rxDataSize) { - if (!handle->rxRingBuffer) + if (NULL == handle->rxRingBuffer) { base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK; } - handle->rxState = kUSART_RxIdle; - if (handle->callback) + handle->rxState = (uint8_t)kUSART_RxIdle; + if (handle->callback != NULL) { handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData); } @@ -864,12 +1117,12 @@ void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) /* Otherwise receive to ring buffer if ring buffer is present */ else { - if (handle->rxRingBuffer) + if (handle->rxRingBuffer != NULL) { /* If RX ring buffer is full, trigger callback to notify over run. */ if (USART_TransferIsRxRingBufferFull(handle)) { - if (handle->callback) + if (handle->callback != NULL) { handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData); } @@ -878,7 +1131,7 @@ void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) if (USART_TransferIsRxRingBufferFull(handle)) { /* Increase handle->rxRingBufferTail to make room for new data. */ - if (handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) + if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize) { handle->rxRingBufferTail = 0U; } @@ -888,9 +1141,10 @@ void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) } } /* Read data. */ - handle->rxRingBuffer[handle->rxRingBufferHead] = base->FIFORD; + rxdata = (uint8_t)base->FIFORD; + handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata; /* Increase handle->rxRingBufferHead. */ - if (handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) + if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize) { handle->rxRingBufferHead = 0U; } @@ -902,38 +1156,51 @@ void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle) } } /* Send data */ - if (sendEnabled && (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK)) + if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)) { base->FIFOWR = *handle->txData; handle->txDataSize--; handle->txData++; - sendEnabled = handle->txDataSize != 0; + sendEnabled = handle->txDataSize != 0U; if (!sendEnabled) { base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK; - handle->txState = kUSART_TxIdle; - if (handle->callback) - { - handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); - } + + base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; } } } + /* Tx idle and the interrupt is enabled. */ + if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) && (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK))) + { + /* Set txState to idle only when all data has been sent out to bus. */ + handle->txState = (uint8_t)kUSART_TxIdle; + /* Disable tx idle interrupt */ + base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; + + /* Trigger callback. */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } + } + /* ring buffer is not used */ if (NULL == handle->rxRingBuffer) { + tmpsize = handle->rxDataSize; + /* restore if rx transfer ends and rxLevel is different from default value */ - if ((handle->rxDataSize == 0) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) + if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark)) { base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark); } /* decrease level if rx transfer is bellow */ - if ((handle->rxDataSize != 0) && (handle->rxDataSize < (USART_FIFOTRIG_RXLVL_GET(base) + 1))) + if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U))) { - base->FIFOTRIG = - (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(handle->rxDataSize - 1)); + base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U)); } } } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.h index 8a6c5d4c13..ef4715c4c5 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2022NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,15 +21,20 @@ /*! @name Driver version */ /*@{*/ -/*! @brief USART driver version 2.1.0. */ -#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) +/*! @brief USART driver version. */ +#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 7, 0)) /*@}*/ #define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT) #define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT) +/*! @brief Retry times for waiting flag. */ +#ifndef UART_RETRY_TIMES +#define UART_RETRY_TIMES 0U /* Defining to zero means to keep waiting for the flag until it is assert/deassert. */ +#endif + /*! @brief Error codes for the USART driver. */ -enum _usart_status +enum { kStatus_USART_TxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 0), /*!< Transmitter is busy. */ kStatus_USART_RxBusy = MAKE_STATUS(kStatusGroup_LPC_USART, 1), /*!< Receiver is busy. */ @@ -43,6 +48,9 @@ enum _usart_status kStatus_USART_ParityError = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */ kStatus_USART_BaudrateNotSupport = MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */ +#if UART_RETRY_TIMES + kStatus_USART_Timeout = MAKE_STATUS(kStatusGroup_LPC_USART, 14), /*!< USART time out. */ +#endif }; /*! @brief USART synchronous mode. */ @@ -117,6 +125,22 @@ enum _usart_interrupt_enable kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK), kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK), kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK), + kUSART_TxIdleInterruptEnable = (USART_INTENSET_TXIDLEEN_MASK << 16U), /*!< Transmitter idle. */ + kUSART_CtsChangeInterruptEnable = + (USART_INTENSET_DELTACTSEN_MASK << 16U), /*!< Change in the state of the CTS input. */ + kUSART_RxBreakChangeInterruptEnable = + (USART_INTENSET_DELTARXBRKEN_MASK), /*!< Break condition asserted or deasserted. */ + kUSART_RxStartInterruptEnable = (USART_INTENSET_STARTEN_MASK), /*!< Rx start bit detected. */ + kUSART_FramingErrorInterruptEnable = (USART_INTENSET_FRAMERREN_MASK), /*!< Framing error detected. */ + kUSART_ParityErrorInterruptEnable = (USART_INTENSET_PARITYERREN_MASK), /*!< Parity error detected. */ + kUSART_NoiseErrorInterruptEnable = (USART_INTENSET_RXNOISEEN_MASK), /*!< Noise error detected. */ + kUSART_AutoBaudErrorInterruptEnable = (USART_INTENSET_ABERREN_MASK), /*!< Auto baudrate error detected. */ + + kUSART_AllInterruptEnables = + kUSART_TxErrorInterruptEnable | kUSART_RxErrorInterruptEnable | kUSART_TxLevelInterruptEnable | + kUSART_RxLevelInterruptEnable | kUSART_TxIdleInterruptEnable | kUSART_CtsChangeInterruptEnable | + kUSART_RxBreakChangeInterruptEnable | kUSART_RxStartInterruptEnable | kUSART_FramingErrorInterruptEnable | + kUSART_ParityErrorInterruptEnable | kUSART_NoiseErrorInterruptEnable | kUSART_AutoBaudErrorInterruptEnable, }; /*! @@ -126,12 +150,29 @@ enum _usart_interrupt_enable */ enum _usart_flags { - kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ - kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ - kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ - kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ - kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ - kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ + kUSART_TxError = (USART_FIFOSTAT_TXERR_MASK), /*!< TEERR bit, sets if TX buffer is error */ + kUSART_RxError = (USART_FIFOSTAT_RXERR_MASK), /*!< RXERR bit, sets if RX buffer is error */ + kUSART_TxFifoEmptyFlag = (USART_FIFOSTAT_TXEMPTY_MASK), /*!< TXEMPTY bit, sets if TX buffer is empty */ + kUSART_TxFifoNotFullFlag = (USART_FIFOSTAT_TXNOTFULL_MASK), /*!< TXNOTFULL bit, sets if TX buffer is not full */ + kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */ + kUSART_RxFifoFullFlag = (USART_FIFOSTAT_RXFULL_MASK), /*!< RXFULL bit, sets if RX buffer is full */ + kUSART_RxIdleFlag = (USART_STAT_RXIDLE_MASK << 16U), /*!< Receiver idle. */ + kUSART_TxIdleFlag = (USART_STAT_TXIDLE_MASK << 16U), /*!< Transmitter idle. */ + kUSART_CtsAssertFlag = (USART_STAT_CTS_MASK << 16U), /*!< CTS signal high. */ + kUSART_CtsChangeFlag = (USART_STAT_DELTACTS_MASK << 16U), /*!< CTS signal changed interrupt status. */ + kUSART_BreakDetectFlag = (USART_STAT_RXBRK_MASK), /*!< Break detected. Self cleared when rx pin goes high again. */ + kUSART_BreakDetectChangeFlag = (USART_STAT_DELTARXBRK_MASK), /*!< Break detect change interrupt flag. A change in + the state of receiver break detection. */ + kUSART_RxStartFlag = (USART_STAT_START_MASK), /*!< Rx start bit detected interrupt flag. */ + kUSART_FramingErrorFlag = (USART_STAT_FRAMERRINT_MASK), /*!< Framing error interrupt flag. */ + kUSART_ParityErrorFlag = (USART_STAT_PARITYERRINT_MASK), /*!< parity error interrupt flag. */ + kUSART_NoiseErrorFlag = (USART_STAT_RXNOISEINT_MASK), /*!< Noise error interrupt flag. */ + kUSART_AutobaudErrorFlag = (USART_STAT_ABERR_MASK), /*!< Auto baudrate error interrupt flag, caused by the baudrate + counter timeout before the end of start bit. */ + + kUSART_AllClearFlags = kUSART_TxError | kUSART_RxError | kUSART_CtsChangeFlag | kUSART_BreakDetectChangeFlag | + kUSART_RxStartFlag | kUSART_FramingErrorFlag | kUSART_ParityErrorFlag | + kUSART_NoiseErrorFlag | kUSART_AutobaudErrorFlag, }; /*! @brief USART configuration structure. */ @@ -145,6 +186,8 @@ typedef struct _usart_config bool enableRx; /*!< Enable RX */ bool enableTx; /*!< Enable TX */ bool enableContinuousSCLK; /*!< USART continuous Clock generation enable in synchronous master mode. */ + bool enableMode32k; /*!< USART uses 32 kHz clock from the RTC oscillator as the clock source. */ + bool enableHardwareFlowControl; /*!< Enable hardware control RTS/CTS */ usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */ @@ -154,7 +197,16 @@ typedef struct _usart_config /*! @brief USART transfer structure. */ typedef struct _usart_transfer { - uint8_t *data; /*!< The buffer of data to be transfer.*/ + /* + * Use separate TX and RX data pointer, because TX data is const data. + * The member data is kept for backward compatibility. + */ + union + { + uint8_t *data; /*!< The buffer of data to be transfer.*/ + uint8_t *rxData; /*!< The buffer to receive data. */ + const uint8_t *txData; /*!< The buffer of data to be sent. */ + }; size_t dataSize; /*!< The byte count to be transfer. */ } usart_transfer_t; @@ -167,12 +219,12 @@ typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *hand /*! @brief USART handle structure. */ struct _usart_handle { - uint8_t *volatile txData; /*!< Address of remaining data to send. */ - volatile size_t txDataSize; /*!< Size of the remaining data to send. */ - size_t txDataSizeAll; /*!< Size of the data to send out. */ - uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ - volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ - size_t rxDataSizeAll; /*!< Size of the data to receive. */ + const uint8_t *volatile txData; /*!< Address of remaining data to send. */ + volatile size_t txDataSize; /*!< Size of the remaining data to send. */ + size_t txDataSizeAll; /*!< Size of the data to send out. */ + uint8_t *volatile rxData; /*!< Address of remaining data to receive. */ + volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */ + size_t rxDataSizeAll; /*!< Size of the data to receive. */ uint8_t *rxRingBuffer; /*!< Start address of the receiver ring buffer. */ size_t rxRingBufferSize; /*!< Size of the ring buffer. */ @@ -185,10 +237,13 @@ struct _usart_handle volatile uint8_t txState; /*!< TX transfer state. */ volatile uint8_t rxState; /*!< RX transfer state */ - usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */ - usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */ + uint8_t txWatermark; /*!< txFIFO watermark */ + uint8_t rxWatermark; /*!< rxFIFO watermark */ }; +/*! @brief Typedef for usart interrupt handler. */ +typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle); + /******************************************************************************* * API ******************************************************************************/ @@ -272,6 +327,77 @@ void USART_GetDefaultConfig(usart_config_t *config); */ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz); +/*! + * @brief Enable 32 kHz mode which USART uses clock from the RTC oscillator as the clock source + * + * Please note that in order to use a 32 kHz clock to operate USART properly, the RTC oscillator + * and its 32 kHz output must be manully enabled by user, by calling RTC_Init and setting + * SYSCON_RTCOSCCTRL_EN bit to 1. + * And in 32kHz clocking mode the USART can only work at 9600 baudrate or at the baudrate that + * 9600 can evenly divide, eg: 4800, 3200. + * + * @param base USART peripheral base address. + * @param baudRate_Bps USART baudrate to be set.. + * @param enableMode32k true is 32k mode, false is normal mode. + * @param srcClock_Hz USART clock source frequency in HZ. + * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source. + * @retval kStatus_Success Set baudrate succeed. + * @retval kStatus_InvalidArgument One or more arguments are invalid. + */ +status_t USART_Enable32kMode(USART_Type *base, uint32_t baudRate_Bps, bool enableMode32k, uint32_t srcClock_Hz); + +/*! + * @brief Enable 9-bit data mode for USART. + * + * This function set the 9-bit mode for USART module. The 9th bit is not used for parity thus can be modified by user. + * + * @param base USART peripheral base address. + * @param enable true to enable, false to disable. + */ +void USART_Enable9bitMode(USART_Type *base, bool enable); + +/*! + * @brief Set the USART slave address. + * + * This function configures the address for USART module that works as slave in 9-bit data mode. When the address + * detection is enabled, the frame it receices with MSB being 1 is considered as an address frame, otherwise it is + * considered as data frame. Once the address frame matches slave's own addresses, this slave is addressed. This + * address frame and its following data frames are stored in the receive buffer, otherwise the frames will be discarded. + * To un-address a slave, just send an address frame with unmatched address. + * + * @note Any USART instance joined in the multi-slave system can work as slave. The position of the address mark is the + * same as the parity bit when parity is enabled for 8 bit and 9 bit data formats. + * + * @param base USART peripheral base address. + * @param address USART slave address. + */ +static inline void USART_SetMatchAddress(USART_Type *base, uint8_t address) +{ + /* Configure match address. */ + base->ADDR = (uint32_t)address; +} + +/*! + * @brief Enable the USART match address feature. + * + * @param base USART peripheral base address. + * @param match true to enable match address, false to disable. + */ +static inline void USART_EnableMatchAddress(USART_Type *base, bool match) +{ + /* Configure match address enable bit. */ + if (match) + { + base->CFG |= (uint32_t)USART_CFG_AUTOADDR_MASK; + base->CTL |= (uint32_t)USART_CTL_ADDRDET_MASK; + } + else + { + base->CFG &= ~(uint32_t)USART_CFG_AUTOADDR_MASK; + base->CTL &= ~(uint32_t)USART_CTL_ADDRDET_MASK; + } +} + /* @} */ /*! @@ -298,7 +424,7 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src */ static inline uint32_t USART_GetStatusFlags(USART_Type *base) { - return base->FIFOSTAT; + return (base->FIFOSTAT & 0xFFUL) | (base->STAT & 0xFFUL) << 16U | (base->STAT & 0xFFFF00UL); } /*! @@ -318,6 +444,9 @@ static inline uint32_t USART_GetStatusFlags(USART_Type *base) */ static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) { + mask &= (uint32_t)kUSART_AllClearFlags; + /* Clear the clearable status in STAT register. */ + base->STAT = (mask & 0xFFFF00UL) | ((mask & 0xFF0000UL) >> 16U); /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */ base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK); } @@ -328,7 +457,6 @@ static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) * @name Interrupts * @{ */ - /*! * @brief Enables USART interrupts according to the provided mask. * @@ -344,7 +472,9 @@ static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask) */ static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) { - base->FIFOINTENSET = mask & 0xF; + mask &= (uint32_t)kUSART_AllInterruptEnables; + base->INTENSET = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); + base->FIFOINTENSET = mask & 0xFUL; } /*! @@ -362,7 +492,9 @@ static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask) */ static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) { - base->FIFOINTENCLR = mask & 0xF; + mask &= (uint32_t)kUSART_AllInterruptEnables; + base->INTENCLR = (mask & 0x1FF00UL) | ((mask & 0xFF0000UL) >> 16U); + base->FIFOINTENCLR = mask & 0xFUL; } /*! @@ -374,7 +506,7 @@ static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask) */ static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base) { - return base->FIFOINTENSET; + return (base->INTENSET & 0x1FF00UL) | ((base->INTENSET & 0xFFUL) << 16UL) | (base->FIFOINTENSET & 0xFUL); } /*! @@ -466,6 +598,30 @@ static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable) base->CTL &= ~USART_CTL_CLRCCONRX_MASK; } } + +/*! + * @brief Sets the rx FIFO watermark. + * + * @param base USART peripheral base address. + * @param water Rx FIFO watermark. + */ +static inline void USART_SetRxFifoWatermark(USART_Type *base, uint8_t water) +{ + assert(water <= (USART_FIFOTRIG_RXLVL_MASK >> USART_FIFOTRIG_RXLVL_SHIFT)); + base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_RXLVL_MASK) | USART_FIFOTRIG_RXLVL(water); +} + +/*! + * @brief Sets the tx FIFO watermark. + * + * @param base USART peripheral base address. + * @param water Tx FIFO watermark. + */ +static inline void USART_SetTxFifoWatermark(USART_Type *base, uint8_t water) +{ + assert(water <= (USART_FIFOTRIG_TXLVL_MASK >> USART_FIFOTRIG_TXLVL_SHIFT)); + base->FIFOTRIG = (base->FIFOTRIG & ~USART_FIFOTRIG_TXLVL_MASK) | USART_FIFOTRIG_TXLVL(water); +} /* @} */ /*! @@ -498,9 +654,39 @@ static inline void USART_WriteByte(USART_Type *base, uint8_t data) */ static inline uint8_t USART_ReadByte(USART_Type *base) { - return base->FIFORD; + return (uint8_t)base->FIFORD; } +/*! + * @brief Gets the rx FIFO data count. + * + * @param base USART peripheral base address. + * @return rx FIFO data count. + */ +static inline uint8_t USART_GetRxFifoCount(USART_Type *base) +{ + return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_RXLVL_MASK) >> USART_FIFOSTAT_RXLVL_SHIFT); +} + +/*! + * @brief Gets the tx FIFO data count. + * + * @param base USART peripheral base address. + * @return tx FIFO data count. + */ +static inline uint8_t USART_GetTxFifoCount(USART_Type *base) +{ + return (uint8_t)((base->FIFOSTAT & USART_FIFOSTAT_TXLVL_MASK) >> USART_FIFOSTAT_TXLVL_SHIFT); +} + +/*! + * @brief Transmit an address frame in 9-bit data mode. + * + * @param base USART peripheral base address. + * @param address USART slave address. + */ +void USART_SendAddress(USART_Type *base, uint8_t address); + /*! * @brief Writes to the TX register using a blocking method. * @@ -510,8 +696,11 @@ static inline uint8_t USART_ReadByte(USART_Type *base) * @param base USART peripheral base address. * @param data Start address of the data to write. * @param length Size of the data to write. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_Success Successfully wrote all data. */ -void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); +status_t USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); /*! * @brief Read RX data register using a blocking method. @@ -526,6 +715,7 @@ void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length); * @retval kStatus_USART_ParityError Noise error happened while receiving data. * @retval kStatus_USART_NoiseError Framing error happened while receiving data. * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened. + * @retval kStatus_USART_Timeout Transmission timed out and was aborted. * @retval kStatus_Success Successfully received all data. */ status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length); @@ -562,10 +752,6 @@ status_t USART_TransferCreateHandle(USART_Type *base, * all data is written to the TX register in the IRQ handler, the USART driver calls the callback * function and passes the @ref kStatus_USART_TxIdle as status parameter. * - * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written - * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX, - * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished. - * * @param base USART peripheral base address. * @param handle USART handle pointer. * @param xfer USART transfer structure. See #usart_transfer_t. @@ -627,10 +813,9 @@ size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle); void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle); /*! - * @brief Get the number of bytes that have been written to USART TX register. + * @brief Get the number of bytes that have been sent out to bus. * - * This function gets the number of bytes that have been written to USART TX - * register by interrupt method. + * This function gets the number of bytes that have been sent out to bus by interrupt method. * * @param base USART peripheral base address. * @param handle USART handle pointer. diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c index 82c969f816..60c2d5284c 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.c @@ -17,14 +17,10 @@ #define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_dma" #endif -/*base, false); - usartPrivateHandle->handle->txState = kUSART_TxIdle; - - if (usartPrivateHandle->handle->callback) - { - usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_TxIdle, - usartPrivateHandle->handle->userData); - } + /* Enable tx idle interrupt */ + usartPrivateHandle->base->INTENSET = USART_INTENSET_TXIDLEEN_MASK; } static void USART_TransferReceiveDMACallback(dma_handle_t *handle, void *param, bool transferDone, uint32_t intmode) { - assert(handle); - assert(param); + assert(handle != NULL); + assert(param != NULL); usart_dma_private_handle_t *usartPrivateHandle = (usart_dma_private_handle_t *)param; /* Disable UART RX DMA. */ USART_EnableRxDMA(usartPrivateHandle->base, false); - usartPrivateHandle->handle->rxState = kUSART_RxIdle; + usartPrivateHandle->handle->rxState = (uint8_t)kUSART_RxIdle; - if (usartPrivateHandle->handle->callback) + if (usartPrivateHandle->handle->callback != NULL) { usartPrivateHandle->handle->callback(usartPrivateHandle->base, usartPrivateHandle->handle, kStatus_USART_RxIdle, usartPrivateHandle->handle->userData); @@ -93,7 +123,7 @@ status_t USART_TransferCreateHandleDMA(USART_Type *base, dma_handle_t *txDmaHandle, dma_handle_t *rxDmaHandle) { - int32_t instance = 0; + uint32_t instance = 0; /* check 'base' */ assert(!(NULL == base)); @@ -110,14 +140,14 @@ status_t USART_TransferCreateHandleDMA(USART_Type *base, instance = USART_GetInstance(base); - memset(handle, 0, sizeof(*handle)); + (void)memset(handle, 0, sizeof(*handle)); /* assign 'base' and 'handle' */ s_dmaPrivateHandle[instance].base = base; s_dmaPrivateHandle[instance].handle = handle; /* set tx/rx 'idle' state */ - handle->rxState = kUSART_RxIdle; - handle->txState = kUSART_TxIdle; + handle->rxState = (uint8_t)kUSART_RxIdle; + handle->txState = (uint8_t)kUSART_TxIdle; handle->callback = callback; handle->userData = userData; @@ -125,14 +155,21 @@ status_t USART_TransferCreateHandleDMA(USART_Type *base, handle->rxDmaHandle = rxDmaHandle; handle->txDmaHandle = txDmaHandle; + /* Set USART_TransferDMAHandleIRQ as DMA IRQ handler */ + usart_dma_to_flexcomm_t handler; + handler.usart_dma_handler = USART_TransferDMAHandleIRQ; + FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle); + /* Enable NVIC IRQ. */ + (void)EnableIRQ(s_usartIRQ[instance]); + /* Configure TX. */ - if (txDmaHandle) + if (txDmaHandle != NULL) { DMA_SetCallback(txDmaHandle, USART_TransferSendDMACallback, &s_dmaPrivateHandle[instance]); } /* Configure RX. */ - if (rxDmaHandle) + if (rxDmaHandle != NULL) { DMA_SetCallback(rxDmaHandle, USART_TransferReceiveDMACallback, &s_dmaPrivateHandle[instance]); } @@ -155,34 +192,35 @@ status_t USART_TransferCreateHandleDMA(USART_Type *base, */ status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) { - assert(handle); - assert(handle->txDmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); + assert(handle != NULL); + assert(handle->txDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); dma_transfer_config_t xferConfig; status_t status; + uint32_t address = (uint32_t)&base->FIFOWR; /* If previous TX not finished. */ - if (kUSART_TxBusy == handle->txState) + if ((uint8_t)kUSART_TxBusy == handle->txState) { status = kStatus_USART_TxBusy; } else { - handle->txState = kUSART_TxBusy; + handle->txState = (uint8_t)kUSART_TxBusy; handle->txDataSizeAll = xfer->dataSize; /* Enable DMA request from txFIFO */ USART_EnableTxDMA(base, true); /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, xfer->data, ((void *)((uint32_t)&base->FIFOWR)), sizeof(uint8_t), - xfer->dataSize, kDMA_MemoryToPeripheral, NULL); + DMA_PrepareTransfer(&xferConfig, xfer->data, (uint32_t *)address, sizeof(uint8_t), xfer->dataSize, + kDMA_MemoryToPeripheral, NULL); /* Submit transfer. */ - DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); + (void)DMA_SubmitTransfer(handle->txDmaHandle, &xferConfig); DMA_StartTransfer(handle->txDmaHandle); status = kStatus_Success; @@ -206,34 +244,35 @@ status_t USART_TransferSendDMA(USART_Type *base, usart_dma_handle_t *handle, usa */ status_t USART_TransferReceiveDMA(USART_Type *base, usart_dma_handle_t *handle, usart_transfer_t *xfer) { - assert(handle); - assert(handle->rxDmaHandle); - assert(xfer); - assert(xfer->data); - assert(xfer->dataSize); + assert(handle != NULL); + assert(handle->rxDmaHandle != NULL); + assert(xfer != NULL); + assert(xfer->data != NULL); + assert(xfer->dataSize != 0U); dma_transfer_config_t xferConfig; status_t status; + uint32_t address = (uint32_t)&base->FIFORD; /* If previous RX not finished. */ - if (kUSART_RxBusy == handle->rxState) + if ((uint8_t)kUSART_RxBusy == handle->rxState) { status = kStatus_USART_RxBusy; } else { - handle->rxState = kUSART_RxBusy; + handle->rxState = (uint8_t)kUSART_RxBusy; handle->rxDataSizeAll = xfer->dataSize; /* Enable DMA request from rxFIFO */ USART_EnableRxDMA(base, true); /* Prepare transfer. */ - DMA_PrepareTransfer(&xferConfig, ((void *)((uint32_t)&base->FIFORD)), xfer->data, sizeof(uint8_t), - xfer->dataSize, kDMA_PeripheralToMemory, NULL); + DMA_PrepareTransfer(&xferConfig, (uint32_t *)address, xfer->data, sizeof(uint8_t), xfer->dataSize, + kDMA_PeripheralToMemory, NULL); /* Submit transfer. */ - DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); + (void)DMA_SubmitTransfer(handle->rxDmaHandle, &xferConfig); DMA_StartTransfer(handle->rxDmaHandle); status = kStatus_Success; @@ -257,7 +296,7 @@ void USART_TransferAbortSendDMA(USART_Type *base, usart_dma_handle_t *handle) /* Stop transfer. */ DMA_AbortTransfer(handle->txDmaHandle); - handle->txState = kUSART_TxIdle; + handle->txState = (uint8_t)kUSART_TxIdle; } /*! @@ -275,7 +314,7 @@ void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) /* Stop transfer. */ DMA_AbortTransfer(handle->rxDmaHandle); - handle->rxState = kUSART_RxIdle; + handle->rxState = (uint8_t)kUSART_RxIdle; } /*! @@ -292,11 +331,11 @@ void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) */ status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) { - assert(handle); - assert(handle->rxDmaHandle); - assert(count); + assert(NULL != handle); + assert(NULL != handle->rxDmaHandle); + assert(NULL != count); - if (kUSART_RxIdle == handle->rxState) + if ((uint8_t)kUSART_RxIdle == handle->rxState) { return kStatus_NoTransferInProgress; } @@ -305,3 +344,49 @@ status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t * return kStatus_Success; } + +/*! + * brief Get the number of bytes that have been sent. + * + * This function gets the number of bytes that have been sent. + * + * param base USART peripheral base address. + * param handle USART handle pointer. + * param count Sent bytes count. + * retval kStatus_NoTransferInProgress No receive in progress. + * retval kStatus_InvalidArgument Parameter is invalid. + * retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count) +{ + assert(NULL != handle); + assert(NULL != handle->txDmaHandle); + assert(NULL != count); + + if ((uint8_t)kUSART_TxIdle == handle->txState) + { + return kStatus_NoTransferInProgress; + } + + *count = handle->txDataSizeAll - DMA_GetRemainingBytes(handle->txDmaHandle->base, handle->txDmaHandle->channel); + + return kStatus_Success; +} + +void USART_TransferDMAHandleIRQ(USART_Type *base, usart_dma_handle_t *handle) +{ + /* Check arguments */ + assert((NULL != base) && (NULL != handle)); + + /* Tx idle interrupt happens means that all the tx data have been sent out to bus, set the tx state to idle */ + handle->txState = (uint8_t)kUSART_TxIdle; + + /* Disable tx idle interrupt */ + base->INTENCLR = USART_INTENCLR_TXIDLECLR_MASK; + + /* Invoke callback */ + if (handle->callback != NULL) + { + handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData); + } +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h index e2ee65798e..2166803b5f 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_dma.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -25,8 +25,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief USART dma driver version 2.0.1. */ -#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @brief USART dma driver version. */ +#define FSL_USART_DMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) /*@}*/ /* Forward declaration of the handle typedef. */ @@ -150,6 +150,20 @@ void USART_TransferAbortReceiveDMA(USART_Type *base, usart_dma_handle_t *handle) */ status_t USART_TransferGetReceiveCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); +/*! + * @brief Get the number of bytes that have been sent. + * + * This function gets the number of bytes that have been sent. + * + * @param base USART peripheral base address. + * @param handle USART handle pointer. + * @param count Sent bytes count. + * @retval kStatus_NoTransferInProgress No receive in progress. + * @retval kStatus_InvalidArgument Parameter is invalid. + * @retval kStatus_Success Get successfully through the parameter \p count; + */ +status_t USART_TransferGetSendCountDMA(USART_Type *base, usart_dma_handle_t *handle, uint32_t *count); + /* @} */ #if defined(__cplusplus) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.c new file mode 100644 index 0000000000..b6eae5bd14 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.c @@ -0,0 +1,368 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_usart_freertos.h" +#include +#include +#include + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart_freertos" +#endif + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +static void USART_RTOS_Callback(USART_Type *base, usart_handle_t *state, status_t status, void *param) +{ + usart_rtos_handle_t *handle = (usart_rtos_handle_t *)param; + BaseType_t xHigherPriorityTaskWoken, xResult; + + xHigherPriorityTaskWoken = pdFALSE; + xResult = pdFAIL; + + if (status == kStatus_USART_RxIdle) + { + xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_USART_COMPLETE, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_USART_TxIdle) + { + xResult = xEventGroupSetBitsFromISR(handle->txEvent, RTOS_USART_COMPLETE, &xHigherPriorityTaskWoken); + } + else if (status == kStatus_USART_RxRingBufferOverrun) + { + xResult = xEventGroupSetBitsFromISR(handle->rxEvent, RTOS_USART_RING_BUFFER_OVERRUN, &xHigherPriorityTaskWoken); + } + else + { + xResult = pdFAIL; + } + + if (xResult != pdFAIL) + { + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : USART_RTOS_Init + * Description : Initializes the USART instance for application + * + *END**************************************************************************/ +/*! + * brief Initializes a USART instance for operation in RTOS. + * + * param handle The RTOS USART handle, the pointer to allocated space for RTOS context. + * param t_handle The pointer to allocated space where to store transactional layer internal state. + * param cfg The pointer to the parameters required to configure the USART after initialization. + * return kStatus_Success, others fail. + */ +int USART_RTOS_Init(usart_rtos_handle_t *handle, usart_handle_t *t_handle, const struct rtos_usart_config *cfg) +{ + status_t status; + usart_config_t defcfg; + + if (NULL == handle) + { + return kStatus_InvalidArgument; + } + if (NULL == t_handle) + { + return kStatus_InvalidArgument; + } + if (NULL == cfg) + { + return kStatus_InvalidArgument; + } + if (NULL == cfg->base) + { + return kStatus_InvalidArgument; + } + if (0U == cfg->srcclk) + { + return kStatus_InvalidArgument; + } + if (0U == cfg->baudrate) + { + return kStatus_InvalidArgument; + } + + handle->base = cfg->base; + handle->t_state = t_handle; + + handle->txSemaphore = xSemaphoreCreateMutex(); + if (NULL == handle->txSemaphore) + { + return kStatus_Fail; + } + handle->rxSemaphore = xSemaphoreCreateMutex(); + if (NULL == handle->rxSemaphore) + { + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + handle->txEvent = xEventGroupCreate(); + if (NULL == handle->txEvent) + { + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + handle->rxEvent = xEventGroupCreate(); + if (NULL == handle->rxEvent) + { + vEventGroupDelete(handle->txEvent); + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + USART_GetDefaultConfig(&defcfg); + + defcfg.baudRate_Bps = cfg->baudrate; + defcfg.parityMode = cfg->parity; + defcfg.enableTx = true; + defcfg.enableRx = true; + + status = USART_Init(handle->base, &defcfg, cfg->srcclk); + if (status != kStatus_Success) + { + vEventGroupDelete(handle->rxEvent); + vEventGroupDelete(handle->txEvent); + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + status = USART_TransferCreateHandle(handle->base, handle->t_state, USART_RTOS_Callback, handle); + if (status != kStatus_Success) + { + vEventGroupDelete(handle->rxEvent); + vEventGroupDelete(handle->txEvent); + vSemaphoreDelete(handle->rxSemaphore); + vSemaphoreDelete(handle->txSemaphore); + return kStatus_Fail; + } + USART_TransferStartRingBuffer(handle->base, handle->t_state, cfg->buffer, cfg->buffer_size); + return kStatus_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : USART_RTOS_Deinit + * Description : Deinitializes the USART instance and frees resources + * + *END**************************************************************************/ +/*! + * brief Deinitializes a USART instance for operation. + * + * This function deinitializes the USART module, sets all register values to reset value, + * and releases the resources. + * + * param handle The RTOS USART handle. + */ +int USART_RTOS_Deinit(usart_rtos_handle_t *handle) +{ + USART_Deinit(handle->base); + + vEventGroupDelete(handle->txEvent); + vEventGroupDelete(handle->rxEvent); + + /* Give the semaphore. This is for functional safety */ + (void)xSemaphoreGive(handle->txSemaphore); + (void)xSemaphoreGive(handle->rxSemaphore); + + vSemaphoreDelete(handle->txSemaphore); + vSemaphoreDelete(handle->rxSemaphore); + + /* Invalidate the handle */ + handle->base = NULL; + handle->t_state = NULL; + + return kStatus_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : USART_RTOS_Send + * Description : Initializes the USART instance for application + * + *END**************************************************************************/ +/*! + * brief Sends data in the background. + * + * This function sends data. It is a synchronous API. + * If the hardware buffer is full, the task is in the blocked state. + * + * param handle The RTOS USART handle. + * param buffer The pointer to buffer to send. + * param length The number of bytes to send. + */ +int USART_RTOS_Send(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length) +{ + EventBits_t ev; + int retval = kStatus_Success; + status_t status; + + if (NULL == handle->base) + { + /* Invalid handle. */ + return kStatus_Fail; + } + if (0U == length) + { + return kStatus_Success; + } + if (NULL == buffer) + { + return kStatus_InvalidArgument; + } + + if (pdFALSE == xSemaphoreTake(handle->txSemaphore, 0)) + { + /* We could not take the semaphore, exit with 0 data received */ + return kStatus_Fail; + } + + handle->txTransfer.data = (uint8_t *)buffer; + handle->txTransfer.dataSize = (uint32_t)length; + + /* Non-blocking call */ + status = USART_TransferSendNonBlocking(handle->base, handle->t_state, &handle->txTransfer); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->txSemaphore); + return kStatus_Fail; + } + + ev = xEventGroupWaitBits(handle->txEvent, RTOS_USART_COMPLETE, pdTRUE, pdFALSE, portMAX_DELAY); + if ((ev & RTOS_USART_COMPLETE) == 0U) + { + retval = kStatus_Fail; + } + + if (pdFALSE == xSemaphoreGive(handle->txSemaphore)) + { + /* We could not post the semaphore, exit with error */ + retval = kStatus_Fail; + } + + return retval; +} + +/*FUNCTION********************************************************************** + * + * Function Name : USART_RTOS_Recv + * Description : Receives chars for the application + * + *END**************************************************************************/ +/*! + * brief Receives data. + * + * This function receives data from USART. It is a synchronous API. If data is immediately available, + * it is returned immediately and the number of bytes received. + * + * param handle The RTOS USART handle. + * param buffer The pointer to buffer where to write received data. + * param length The number of bytes to receive. + * param received The pointer to a variable of size_t where the number of received data is filled. + */ +int USART_RTOS_Receive(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received) +{ + EventBits_t ev; + size_t n = 0; + int retval = kStatus_Fail; + size_t local_received = 0; + status_t status; + + if (NULL == handle->base) + { + /* Invalid handle. */ + return kStatus_Fail; + } + if (0U == length) + { + if (received != NULL) + { + *received = n; + } + return kStatus_Success; + } + if (NULL == buffer) + { + return kStatus_InvalidArgument; + } + + /* New transfer can be performed only after current one is finished */ + if (pdFALSE == xSemaphoreTake(handle->rxSemaphore, portMAX_DELAY)) + { + /* We could not take the semaphore, exit with 0 data received */ + return kStatus_Fail; + } + + handle->rxTransfer.data = buffer; + handle->rxTransfer.dataSize = (uint32_t)length; + + /* Non-blocking call */ + status = USART_TransferReceiveNonBlocking(handle->base, handle->t_state, &handle->rxTransfer, &n); + if (status != kStatus_Success) + { + (void)xSemaphoreGive(handle->rxSemaphore); + return kStatus_Fail; + } + + ev = xEventGroupWaitBits(handle->rxEvent, RTOS_USART_COMPLETE | RTOS_USART_RING_BUFFER_OVERRUN, pdTRUE, pdFALSE, + portMAX_DELAY); + if ((ev & RTOS_USART_RING_BUFFER_OVERRUN) != 0U) + { + /* Stop data transfer to application buffer, ring buffer is still active */ + USART_TransferAbortReceive(handle->base, handle->t_state); + /* Prevent false indication of successful transfer in next call of USART_RTOS_Receive. + RTOS_USART_COMPLETE flag could be set meanwhile overrun is handled */ + (void)xEventGroupClearBits(handle->rxEvent, RTOS_USART_COMPLETE); + retval = kStatus_USART_RxRingBufferOverrun; + local_received = 0; + } + else if ((ev & RTOS_USART_COMPLETE) != 0U) + { + retval = kStatus_Success; + local_received = length; + } + else + { + retval = kStatus_USART_RxError; + local_received = 0; + } + + /* Prevent repetitive NULL check */ + if (received != NULL) + { + *received = local_received; + } + + /* Enable next transfer. Current one is finished */ + if (pdFALSE == xSemaphoreGive(handle->rxSemaphore)) + { + /* We could not post the semaphore, exit with error */ + retval = kStatus_Fail; + } + return retval; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.h new file mode 100644 index 0000000000..0b21386ad3 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_usart_freertos.h @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __FSL_USART_FREERTOS_H__ +#define __FSL_USART_FREERTOS_H__ + +#include "fsl_usart.h" +#include +#include +#include + +/*! + * @addtogroup usart_freertos_driver + * @{ + */ + +/*! @file*/ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @name Driver version */ +/*@{*/ +/*! @brief USART FreeRTOS driver version. */ +#define FSL_USART_FREERTOS_DRIVER_VERSION (MAKE_VERSION(2, 6, 0)) +/*@}*/ + +/*! @brief FLEX USART configuration structure */ +struct rtos_usart_config +{ + USART_Type *base; /*!< USART base address */ + uint32_t srcclk; /*!< USART source clock in Hz*/ + uint32_t baudrate; /*!< Desired communication speed */ + usart_parity_mode_t parity; /*!< Parity setting */ + usart_stop_bit_count_t stopbits; /*!< Number of stop bits to use */ + uint8_t *buffer; /*!< Buffer for background reception */ + uint32_t buffer_size; /*!< Size of buffer for background reception */ +}; + +/*! @brief FLEX USART FreeRTOS handle */ +typedef struct _usart_rtos_handle +{ + USART_Type *base; /*!< USART base address */ + usart_transfer_t txTransfer; /*!< TX transfer structure */ + usart_transfer_t rxTransfer; /*!< RX transfer structure */ + SemaphoreHandle_t rxSemaphore; /*!< RX semaphore for resource sharing */ + SemaphoreHandle_t txSemaphore; /*!< TX semaphore for resource sharing */ +#define RTOS_USART_COMPLETE 0x1U +#define RTOS_USART_RING_BUFFER_OVERRUN 0x2U +#define RTOS_USART_HARDWARE_BUFFER_OVERRUN 0x4U + EventGroupHandle_t rxEvent; /*!< RX completion event */ + EventGroupHandle_t txEvent; /*!< TX completion event */ + void *t_state; /*!< Transactional state of the underlying driver */ +} usart_rtos_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name USART RTOS Operation + * @{ + */ + +/*! + * @brief Initializes a USART instance for operation in RTOS. + * + * @param handle The RTOS USART handle, the pointer to allocated space for RTOS context. + * @param t_handle The pointer to allocated space where to store transactional layer internal state. + * @param cfg The pointer to the parameters required to configure the USART after initialization. + * @return 0 succeed, others fail. + */ +int USART_RTOS_Init(usart_rtos_handle_t *handle, usart_handle_t *t_handle, const struct rtos_usart_config *cfg); + +/*! + * @brief Deinitializes a USART instance for operation. + * + * This function deinitializes the USART module, sets all register values to reset value, + * and releases the resources. + * + * @param handle The RTOS USART handle. + */ +int USART_RTOS_Deinit(usart_rtos_handle_t *handle); + +/*! + * @name USART transactional Operation + * @{ + */ + +/*! + * @brief Sends data in the background. + * + * This function sends data. It is a synchronous API. + * If the hardware buffer is full, the task is in the blocked state. + * + * @param handle The RTOS USART handle. + * @param buffer The pointer to buffer to send. + * @param length The number of bytes to send. + */ +int USART_RTOS_Send(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length); + +/*! + * @brief Receives data. + * + * This function receives data from USART. It is a synchronous API. If data is immediately available, + * it is returned immediately and the number of bytes received. + * + * @param handle The RTOS USART handle. + * @param buffer The pointer to buffer where to write received data. + * @param length The number of bytes to receive. + * @param received The pointer to a variable of size_t where the number of received data is filled. + */ +int USART_RTOS_Receive(usart_rtos_handle_t *handle, uint8_t *buffer, uint32_t length, size_t *received); + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_USART_FREERTOS_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.c index 8014834d86..0eea419cd3 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.c @@ -1,13 +1,15 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2019, 2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include "fsl_utick.h" +#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG) #include "fsl_power.h" +#endif /******************************************************************************* * Definitions ******************************************************************************/ @@ -52,7 +54,11 @@ static const reset_ip_name_t s_utickResets[] = UTICK_RSTS; #endif /* UTICK ISR for transactional APIs. */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +static utick_isr_t s_utickIsr = (utick_isr_t)DefaultISR; +#else static utick_isr_t s_utickIsr; +#endif /******************************************************************************* * Code @@ -95,7 +101,12 @@ void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_ca /* Save the handle in global variables to support the double weak mechanism. */ s_utickHandle[instance] = cb; +#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) && \ + !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)) EnableDeepSleepIRQ(s_utickIRQ[instance]); +#else + (void)EnableIRQ(s_utickIRQ[instance]); +#endif /* FSL_FEATURE_SOC_SYSCON_COUNT && !FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ base->CTRL = count | UTICK_CTRL_REPEAT(mode); } @@ -179,42 +190,41 @@ void UTICK_ClearStatusFlags(UTICK_Type *base) void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb) { UTICK_ClearStatusFlags(base); - if (cb) + if (cb != NULL) { cb(); } } #if defined(UTICK0) +void UTICK0_DriverIRQHandler(void); void UTICK0_DriverIRQHandler(void) { s_utickIsr(UTICK0, s_utickHandle[0]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(UTICK1) +void UTICK1_DriverIRQHandler(void); void UTICK1_DriverIRQHandler(void) { s_utickIsr(UTICK1, s_utickHandle[1]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; } #endif #if defined(UTICK2) +void UTICK2_DriverIRQHandler(void); void UTICK2_DriverIRQHandler(void) { s_utickIsr(UTICK2, s_utickHandle[2]); -/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping - exception return operation might vector to incorrect interrupt */ -#if defined __CORTEX_M && (__CORTEX_M == 4U) - __DSB(); -#endif + SDK_ISR_EXIT_BARRIER; +} +#endif +#if defined(UTICK) +void UTICK_DriverIRQHandler(void); +void UTICK_DriverIRQHandler(void) +{ + s_utickIsr(UTICK, s_utickHandle[0]); + SDK_ISR_EXIT_BARRIER; } #endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.h index 7db3ca4157..48c7d6b86d 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_utick.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2019, 2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -22,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief UTICK driver version 2.0.2. */ -#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*! @brief UTICK driver version 2.0.5. */ +#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*@}*/ /*! @brief UTICK timer operational mode. */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c index 6b510371a4..6680148acf 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -91,10 +91,10 @@ static uint32_t WWDT_GetInstance(WWDT_Type *base) */ void WWDT_GetDefaultConfig(wwdt_config_t *config) { - assert(config); + assert(NULL != config); /* Initializes the configure structure to zero. */ - memset(config, 0, sizeof(*config)); + (void)memset(config, 0, sizeof(*config)); /* Enable the watch dog */ config->enableWwdt = true; @@ -134,12 +134,11 @@ void WWDT_GetDefaultConfig(wwdt_config_t *config) */ void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) { - assert(config); - /* The config->clockFreq_Hz must be set in order to config the delay time. */ - assert(config->clockFreq_Hz); + assert(NULL != config); - uint32_t value = 0U; - uint32_t DelayUs = 0U; + uint32_t value = 0U; + uint32_t DelayUs = 0U; + uint32_t primaskValue = 0U; #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Enable the WWDT clock */ @@ -151,6 +150,14 @@ void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) /* Reset the module. */ RESET_PeripheralReset(s_wwdtResets[WWDT_GetInstance(base)]); #endif + +#if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) + /* PMC RESETCAUSE: set bit to clear it by write 1. */ + PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; + /* Enable the watchdog reset event to affect the system in the Power Management Controller */ + PMC->CTRL |= PMC_CTRL_WDTRESETENABLE_MASK; +#endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ + #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) @@ -159,20 +166,40 @@ void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) #else value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset); #endif + /* Clear legacy flag in the MOD register by software writing a "1" to this bit field.. */ + if (0U != (base->MOD & WWDT_MOD_WDINT_MASK)) + { + value |= WWDT_MOD_WDINT_MASK; + } /* Set configuration */ - base->TC = WWDT_TC_COUNT(config->timeoutValue); - base->MOD |= value; + primaskValue = DisableGlobalIRQ(); + base->TC = WWDT_TC_COUNT(config->timeoutValue); + base->MOD = value; base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); base->WARNINT = WWDT_WARNINT_WARNINT(config->warningValue); - WWDT_Refresh(base); - /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ - if ((base->MOD & WWDT_MOD_WDPROTECT_MASK) == 0U) + /* Refreshes the WWDT timer. */ + base->FEED = WWDT_FIRST_WORD_OF_REFRESH; + base->FEED = WWDT_SECOND_WORD_OF_REFRESH; + EnableGlobalIRQ(primaskValue); + /* Read counter value to wait wwdt timer start*/ + if (config->enableWwdt) { + while (base->TV == 0xFFUL) + { + } + } + + /* This WDPROTECT bit can be set once by software and is only cleared by a reset */ + if (config->enableWatchdogProtect && (0U == (base->MOD & WWDT_MOD_WDPROTECT_MASK))) + { + /* The config->clockFreq_Hz must be set in order to config the delay time. */ + assert(0U != config->clockFreq_Hz); + /* Set the WDPROTECT bit after the Feed Sequence (0xAA, 0x55) with 3 WDCLK delay */ DelayUs = FREQUENCY_3MHZ / config->clockFreq_Hz + 1U; - SDK_DelayAtLeastUs(DelayUs); + SDK_DelayAtLeastUs(DelayUs, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - base->MOD |= WWDT_MOD_WDPROTECT(config->enableWatchdogProtect); + base->MOD |= WWDT_MOD_WDPROTECT(1U); } } @@ -185,8 +212,6 @@ void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config) */ void WWDT_Deinit(WWDT_Type *base) { - WWDT_Disable(base); - #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) /* Disable the WWDT clock */ CLOCK_DisableClock(s_wwdtClocks[WWDT_GetInstance(base)]); @@ -231,17 +256,17 @@ void WWDT_ClearStatusFlags(WWDT_Type *base, uint32_t mask) uint32_t reg = (base->MOD & (~WWDT_MOD_WDINT_MASK)); /* Clear timeout by writing a zero */ - if (mask & kWWDT_TimeoutFlag) + if (0U != (mask & (uint32_t)kWWDT_TimeoutFlag)) { reg &= ~WWDT_MOD_WDTOF_MASK; #if defined(FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) && (FSL_FEATURE_WWDT_WDTRESET_FROM_PMC) /* PMC RESETCAUSE: set bit to clear it */ - PMC->RESETCAUSE |= PMC_RESETCAUSE_WDTRESET_MASK; + PMC->RESETCAUSE = PMC_RESETCAUSE_WDTRESET_MASK; #endif /*FSL_FEATURE_WWDT_WDTRESET_FROM_PMC*/ } /* Clear warning interrupt flag by writing a one */ - if (mask & kWWDT_WarningFlag) + if (0U != (mask & (uint32_t)kWWDT_WarningFlag)) { reg |= WWDT_MOD_WDINT_MASK; } diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h index 7cccdf41d4..2546253496 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/drivers/fsl_wwdt.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -23,13 +23,13 @@ /*! @name Driver version */ /*@{*/ -/*! @brief Defines WWDT driver version 2.1.2. */ -#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) +/*! @brief Defines WWDT driver version. */ +#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9)) /*@}*/ /*! @name Refresh sequence */ /*@{*/ -#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ +#define WWDT_FIRST_WORD_OF_REFRESH (0xAAU) /*!< First word of refresh sequence */ #define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */ /*@}*/ @@ -149,6 +149,8 @@ static inline void WWDT_Enable(WWDT_Type *base) /*! * @brief Disables the WWDT module. + * @deprecated Do not use this function. It will be deleted in next release version, for + * once the bit field of WDEN written with a 1, it can not be re-written with a 0. * * This function write value into WWDT_MOD register to disable the WWDT. * diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/fsl_device_registers.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/fsl_device_registers.h index 1455785a81..d75a93b2d7 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/fsl_device_registers.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/fsl_device_registers.h @@ -1,6 +1,6 @@ /* * Copyright 2014-2016 Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2019 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -15,7 +15,8 @@ * * The CPU macro should be declared in the project or makefile. */ -#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JET98_cm33_core0)) +#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JBD64_cm33_core0) || \ + defined(CPU_LPC55S69JEV98_cm33_core0)) #define LPC55S69_cm33_core0_SERIES @@ -24,7 +25,8 @@ /* CPU specific feature definitions */ #include "LPC55S69_cm33_core0_features.h" -#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JET98_cm33_core1)) +#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JBD64_cm33_core1) || \ + defined(CPU_LPC55S69JEV98_cm33_core1)) #define LPC55S69_cm33_core1_SERIES @@ -34,7 +36,7 @@ #include "LPC55S69_cm33_core1_features.h" #else - #error "No valid CPU defined!" +#error "No valid CPU defined!" #endif #endif /* __FSL_DEVICE_REGISTERS_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld index 90f8ee7db1..ef9bc99b69 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash.ld @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: GNU C Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b210928 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -35,9 +36,9 @@ RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000140 - m_text (RX) : ORIGIN = 0x00000140, LENGTH = 0x00071EC0 - m_core1_image (RX) : ORIGIN = 0x00072000, LENGTH = 0x00026000 + m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x00000200, LENGTH = 0x00071E00 + m_core1_image (RX) : ORIGIN = 0x00072000, LENGTH = 0x0002B800 m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00033000 - RPMSG_SHMEM_SIZE rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 @@ -47,19 +48,21 @@ MEMORY SECTIONS { /* section for storing the secondary core image */ - .m0code : + .core1_code : { . = ALIGN(4) ; - KEEP (*(.m0code)) - *(.m0code*) + KEEP (*(.core1_code)) + *(.core1_code*) . = ALIGN(4) ; } > m_core1_image /* NOINIT section for rpmsg_sh_mem */ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) { + __RPMSG_SH_MEM_START__ = .; *(.noinit.$rpmsg_sh_mem*) . = ALIGN(4) ; + __RPMSG_SH_MEM_END__ = .; } > rpmsg_sh_mem /* The startup code goes first into internal flash */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_ns.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_ns.ld index cbf9e37793..22dd623ec5 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_ns.ld +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_ns.ld @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: GNU C Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190926 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2019 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -35,10 +36,10 @@ RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x00010000, LENGTH = 0x00000140 - m_text (RX) : ORIGIN = 0x00010140, LENGTH = 0x00061EC0 - m_core1_image (RX) : ORIGIN = 0x00072000, LENGTH = 0x00026000 - m_data (RW) : ORIGIN = 0x20008000, LENGTH = 0x00028000 + m_interrupts (RX) : ORIGIN = 0x00010000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x00010200, LENGTH = 0x00061E00 + m_core1_image (RX) : ORIGIN = 0x00072000, LENGTH = 0x0002B800 + m_data (RW) : ORIGIN = 0x20008000, LENGTH = 0x0002A800 - RPMSG_SHMEM_SIZE rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 } @@ -47,19 +48,21 @@ MEMORY SECTIONS { /* section for storing the secondary core image */ - .m0code : + .core1_code : { . = ALIGN(4) ; - KEEP (*(.m0code)) - *(.m0code*) + KEEP (*(.core1_code)) + *(.core1_code*) . = ALIGN(4) ; } > m_core1_image /* NOINIT section for rpmsg_sh_mem */ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) { + __RPMSG_SH_MEM_START__ = .; *(.noinit.$rpmsg_sh_mem*) . = ALIGN(4) ; + __RPMSG_SH_MEM_END__ = .; } > rpmsg_sh_mem /* The startup code goes first into internal flash */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_s.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_s.ld index bfd82ab056..69edc592d2 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_s.ld +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_flash_s.ld @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: GNU C Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190926 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2019 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -35,10 +36,10 @@ RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x10000000, LENGTH = 0x00000140 - m_text (RX) : ORIGIN = 0x10000140, LENGTH = 0x0000FCC0 + m_interrupts (RX) : ORIGIN = 0x10000000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x10000200, LENGTH = 0x0000FC00 m_veneer_table (RX) : ORIGIN = 0x1000FE00, LENGTH = 0x00000200 - m_core1_image (RX) : ORIGIN = 0x10072000, LENGTH = 0x00026000 + m_core1_image (RX) : ORIGIN = 0x10072000, LENGTH = 0x0002B800 m_data (RW) : ORIGIN = 0x30000000, LENGTH = 0x00008000 rpmsg_sh_mem (RW) : ORIGIN = 0x30033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE m_usb_sram (RW) : ORIGIN = 0x50100000, LENGTH = 0x00004000 @@ -48,19 +49,21 @@ MEMORY SECTIONS { /* section for storing the secondary core image */ - .m0code : + .core1_code : { . = ALIGN(4) ; - KEEP (*(.m0code)) - *(.m0code*) + KEEP (*(.core1_code)) + *(.core1_code*) . = ALIGN(4) ; } > m_core1_image /* NOINIT section for rpmsg_sh_mem */ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) { + __RPMSG_SH_MEM_START__ = .; *(.noinit.$rpmsg_sh_mem*) . = ALIGN(4) ; + __RPMSG_SH_MEM_END__ = .; } > rpmsg_sh_mem /* The startup code goes first into internal flash */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld index 3fbe35bf32..c2d4269000 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core0_ram.ld @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: GNU C Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b200722 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -35,9 +36,9 @@ RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x04000000, LENGTH = 0x00000140 - m_text (RX) : ORIGIN = 0x04000140, LENGTH = 0x00007EC0 - m_core1_image (RX) : ORIGIN = 0x20033000, LENGTH = 0x00008800 + m_interrupts (RX) : ORIGIN = 0x04000000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x04000200, LENGTH = 0x00007E00 + m_core1_image (RX) : ORIGIN = 0x20033000, LENGTH = 0x0000C800 m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00033000 - RPMSG_SHMEM_SIZE rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 @@ -47,19 +48,21 @@ MEMORY SECTIONS { /* section for storing the secondary core image */ - .m0code : + .core1_code : { . = ALIGN(4) ; - KEEP (*(.m0code)) - *(.m0code*) + KEEP (*(.core1_code)) + *(.core1_code*) . = ALIGN(4) ; } > m_core1_image /* NOINIT section for rpmsg_sh_mem */ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) { + __RPMSG_SH_MEM_START__ = .; *(.noinit.$rpmsg_sh_mem*) . = ALIGN(4) ; + __RPMSG_SH_MEM_END__ = .; } > rpmsg_sh_mem /* The startup code goes first into internal flash */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld index ffbca1ee1c..159b7b1f15 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_flash.ld @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compiler: GNU C Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b210928 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -35,9 +36,9 @@ RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x00072000, LENGTH = 0x00000140 - m_text (RX) : ORIGIN = 0x00072140, LENGTH = 0x00025EC0 - m_data (RW) : ORIGIN = 0x20033000, LENGTH = 0x00010800 + m_interrupts (RX) : ORIGIN = 0x00072000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x00072200, LENGTH = 0x0002B600 + m_data (RW) : ORIGIN = 0x20033000, LENGTH = 0x00011000 rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 } @@ -48,8 +49,10 @@ SECTIONS /* NOINIT section for rpmsg_sh_mem */ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) { + __RPMSG_SH_MEM_START__ = .; *(.noinit.$rpmsg_sh_mem*) . = ALIGN(4) ; + __RPMSG_SH_MEM_END__ = .; } > rpmsg_sh_mem /* The startup code goes first into internal flash */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld index 71c2ba04e8..2539c1e32c 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram.ld @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compiler: GNU C Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b200722 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -35,9 +36,9 @@ RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x20033000, LENGTH = 0x00000140 - m_text (RX) : ORIGIN = 0x20033140, LENGTH = 0x0000B6C0 - m_data (RW) : ORIGIN = 0x2003E800, LENGTH = 0x00005800 + m_interrupts (RX) : ORIGIN = 0x20033000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x20033200, LENGTH = 0x0000C600 + m_data (RW) : ORIGIN = 0x2003F800, LENGTH = 0x00004800 rpmsg_sh_mem (RW) : ORIGIN = 0x20033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00004000 } @@ -48,8 +49,10 @@ SECTIONS /* NOINIT section for rpmsg_sh_mem */ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) { + __RPMSG_SH_MEM_START__ = .; *(.noinit.$rpmsg_sh_mem*) . = ALIGN(4) ; + __RPMSG_SH_MEM_END__ = .; } > rpmsg_sh_mem /* The startup code goes first into internal flash */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld index fe9b7a27f7..8efdda2364 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/LPC55S69_cm33_core1_ram_s.ld @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compiler: GNU C Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190926 ** ** Abstract: ** Linker file for the GNU C Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2019 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -35,9 +36,9 @@ RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x1800 : 0; /* Specify the memory areas */ MEMORY { - m_interrupts (RX) : ORIGIN = 0x30033000, LENGTH = 0x00000140 - m_text (RX) : ORIGIN = 0x30033140, LENGTH = 0x0000B6C0 - m_data (RW) : ORIGIN = 0x3003E800, LENGTH = 0x00005800 + m_interrupts (RX) : ORIGIN = 0x30033000, LENGTH = 0x00000200 + m_text (RX) : ORIGIN = 0x30033200, LENGTH = 0x0000C600 + m_data (RW) : ORIGIN = 0x3003F800, LENGTH = 0x00004800 rpmsg_sh_mem (RW) : ORIGIN = 0x30033000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE m_usb_sram (RW) : ORIGIN = 0x50100000, LENGTH = 0x00004000 } @@ -48,8 +49,10 @@ SECTIONS /* NOINIT section for rpmsg_sh_mem */ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4) { + __RPMSG_SH_MEM_START__ = .; *(.noinit.$rpmsg_sh_mem*) . = ALIGN(4) ; + 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z>uf&$WgI@n&f+-s(eA@iiRHiI_<4=(PVPq24*{0FJdXv-%FBA=En+=uJbP=?&s_sFy_tPFJa!-uWo5fDYaZnAveKhK5kD z0dWHs1e)GG2nyq>aE{KFiJOC`Y6}7_j^8hY^^FAeF+by2Ust5p1-%T~%}kHqGvL3}`VsdVz7sODzCOGN z^Ik+=4*%nJ!R08;dpgqVsq@#?Snr1@?(&Kx`Hl%>miKI&_fuRev4YHtN3_zsmm|I7 ztCQpvX%VLPbELQZbARtgJsyX){l+7`hYJ3hN-dh{jYWD_pf`**>fsTNRPPQPu=XCl zA3y(`Jc4a)W_{BT7jEbNK7X%3y$lws?_TNIvGfj3I1geQno*An$7_)m_w{R2w+s9E zJr8Nt@H*}}g9hfM@q3}LzUpKCo{sfZW3l@3h{HK|Gv7n&e#1|8@4bm!Oo7nUMiAEs lkt|wp=s3L@Aag=5wIw*wH3#+COWZn5io1sT8iNED_b=CM7!v>h diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core0.S b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core0.S index 5c547b8e32..0992cb7655 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core0.S +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core0.S @@ -7,7 +7,7 @@ /* --------------------------------------------------------------------------*/ /* */ /* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2019 NXP */ +/* Copyright 2016-2021 NXP */ /* All rights reserved. */ /* */ /* SPDX-License-Identifier: BSD-3-Clause */ @@ -87,7 +87,7 @@ __Vectors: .long Reserved59_IRQHandler /* Reserved interrupt */ .long Reserved60_IRQHandler /* Reserved interrupt */ .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_UTMI_IRQHandler /* USB1_UTMI */ + .long USB1_PHY_IRQHandler /* USB1_PHY */ .long USB1_IRQHandler /* USB1 interrupt */ .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ @@ -114,6 +114,15 @@ __Vectors: .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: + cpsid i /* Mask interrupts */ + .equ VTOR, 0xE000ED08 + ldr r0, =VTOR + ldr r1, =__Vectors + str r1, [r0] + ldr r2, [r1] + msr msp, r2 + ldr R0, =__StackLimit + msr msplim, R0 #ifndef __NO_SYSTEM_INIT ldr r0,=SystemInit blx r0 @@ -199,7 +208,7 @@ Reset_Handler: #else ldr r0,=__libc_init_array blx r0 - ldr r0,=entry + ldr r0,=main bx r0 #endif .pool @@ -674,12 +683,12 @@ Reserved61_IRQHandler: .align 1 .thumb_func - .weak USB1_UTMI_IRQHandler - .type USB1_UTMI_IRQHandler, %function -USB1_UTMI_IRQHandler: - ldr r0,=USB1_UTMI_DriverIRQHandler + .weak USB1_PHY_IRQHandler + .type USB1_PHY_IRQHandler, %function +USB1_PHY_IRQHandler: + ldr r0,=USB1_PHY_DriverIRQHandler bx r0 - .size USB1_UTMI_IRQHandler, . - USB1_UTMI_IRQHandler + .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler .align 1 .thumb_func @@ -857,7 +866,7 @@ FLEXCOMM8_IRQHandler: def_irq_handler Reserved59_DriverIRQHandler def_irq_handler Reserved60_DriverIRQHandler def_irq_handler Reserved61_DriverIRQHandler - def_irq_handler USB1_UTMI_DriverIRQHandler + def_irq_handler USB1_PHY_DriverIRQHandler def_irq_handler USB1_DriverIRQHandler def_irq_handler USB1_NEEDCLK_DriverIRQHandler def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core1.S b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core1.S index fff53798ff..375866a8d5 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core1.S +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/gcc/startup_LPC55S69_cm33_core1.S @@ -87,7 +87,7 @@ __Vectors: .long Reserved59_IRQHandler /* Reserved interrupt */ .long Reserved60_IRQHandler /* Reserved interrupt */ .long Reserved61_IRQHandler /* Reserved interrupt */ - .long USB1_UTMI_IRQHandler /* USB1_UTMI */ + .long USB1_PHY_IRQHandler /* USB1_PHY */ .long USB1_IRQHandler /* USB1 interrupt */ .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ .long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */ @@ -674,12 +674,12 @@ Reserved61_IRQHandler: .align 1 .thumb_func - .weak USB1_UTMI_IRQHandler - .type USB1_UTMI_IRQHandler, %function -USB1_UTMI_IRQHandler: - ldr r0,=USB1_UTMI_DriverIRQHandler + .weak USB1_PHY_IRQHandler + .type USB1_PHY_IRQHandler, %function +USB1_PHY_IRQHandler: + ldr r0,=USB1_PHY_DriverIRQHandler bx r0 - .size USB1_UTMI_IRQHandler, . - USB1_UTMI_IRQHandler + .size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler .align 1 .thumb_func @@ -857,7 +857,7 @@ FLEXCOMM8_IRQHandler: def_irq_handler Reserved59_DriverIRQHandler def_irq_handler Reserved60_DriverIRQHandler def_irq_handler Reserved61_DriverIRQHandler - def_irq_handler USB1_UTMI_DriverIRQHandler + def_irq_handler USB1_PHY_DriverIRQHandler def_irq_handler USB1_DriverIRQHandler def_irq_handler USB1_NEEDCLK_DriverIRQHandler def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash.icf index 4d5f2e6ee4..f2d43da382 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash.icf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash.icf @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b210928 ** ** Abstract: ** Linker file for the IAR ANSI C/C++ Compiler for ARM ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -40,13 +41,13 @@ if (isdefinedsymbol(__heap_size__)) { } define symbol m_interrupts_start = 0x00000000; -define symbol m_interrupts_end = 0x0000013F; +define symbol m_interrupts_end = 0x000001FF; -define symbol m_text_start = 0x00000140; +define symbol m_text_start = 0x00000200; define symbol m_text_end = 0x00071FFF; define exported symbol core1_image_start = 0x00072000; -define exported symbol core1_image_end = 0x00097FFF; +define exported symbol core1_image_end = 0x0009D7FF; if (isdefinedsymbol(__use_shmem__)) { define symbol m_data_start = 0x20000000; @@ -77,7 +78,7 @@ define block RW { readwrite }; define block ZI { zi }; define region core1_region = mem:[from core1_image_start to core1_image_end]; -define block SEC_CORE_IMAGE_BLOCK { section __sec_core }; +define block CORE1_IMAGE_WBLOCK { section __core1_image }; /* regions for USB */ define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; @@ -107,5 +108,5 @@ place in CSTACK_region { block CSTACK }; if (isdefinedsymbol(__use_shmem__)) { place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; } -place in core1_region { block SEC_CORE_IMAGE_BLOCK }; +place in core1_region { block CORE1_IMAGE_WBLOCK }; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_ns.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_ns.icf index 6f890542c3..0d7697ebf9 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_ns.icf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_ns.icf @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190926 ** ** Abstract: ** Linker file for the IAR ANSI C/C++ Compiler for ARM ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2019 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -40,17 +41,17 @@ if (isdefinedsymbol(__heap_size__)) { } define symbol m_interrupts_start = 0x00010000; -define symbol m_interrupts_end = 0x0001013F; +define symbol m_interrupts_end = 0x000101FF; -define symbol m_text_start = 0x00010140; +define symbol m_text_start = 0x00010200; define symbol m_text_end = 0x00071FFF; define exported symbol core1_image_start = 0x00072000; -define exported symbol core1_image_end = 0x00097FFF; +define exported symbol core1_image_end = 0x0009D7FF; if (isdefinedsymbol(__use_shmem__)) { define symbol m_data_start = 0x20008000; - define symbol m_data_end = 0x2002FFFF; + define symbol m_data_end = 0x20030FFF; define exported symbol rpmsg_sh_mem_start = 0x20031800; define exported symbol rpmsg_sh_mem_end = 0x20032FFF; } else { @@ -77,7 +78,7 @@ define block RW { readwrite }; define block ZI { zi }; define region core1_region = mem:[from core1_image_start to core1_image_end]; -define block SEC_CORE_IMAGE_BLOCK { section __sec_core }; +define block CORE1_IMAGE_WBLOCK { section __core1_image }; /* regions for USB */ define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; @@ -107,5 +108,5 @@ place in CSTACK_region { block CSTACK }; if (isdefinedsymbol(__use_shmem__)) { place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; } -place in core1_region { block SEC_CORE_IMAGE_BLOCK }; +place in core1_region { block CORE1_IMAGE_WBLOCK }; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf index 2090bb8013..6be960151a 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_flash_s.icf @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190926 ** ** Abstract: ** Linker file for the IAR ANSI C/C++ Compiler for ARM ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2019 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -41,13 +42,13 @@ if (isdefinedsymbol(__heap_size__)) { /* Only the first 64kB of flash is used as secure memory. */ define symbol m_interrupts_start = 0x10000000; -define symbol m_interrupts_end = 0x1000013F; +define symbol m_interrupts_end = 0x100001FF; -define symbol m_text_start = 0x10000140; +define symbol m_text_start = 0x10000200; define symbol m_text_end = 0x1000FDFF; -define exported symbol core1_image_start = 0x00072000; -define exported symbol core1_image_end = 0x00097FFF; +define exported symbol core1_image_start = 0x10072000; +define exported symbol core1_image_end = 0x1009D7FF; /* Only first 32kB of data RAM is used as secure memory. */ if (isdefinedsymbol(__use_shmem__)) { @@ -85,7 +86,7 @@ define block RW { readwrite }; define block ZI { zi }; define region core1_region = mem:[from core1_image_start to core1_image_end]; -define block SEC_CORE_IMAGE_BLOCK { section __sec_core }; +define block CORE1_IMAGE_WBLOCK { section __core1_image }; /* regions for USB */ define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; @@ -117,5 +118,5 @@ place in VENEER_TABLE_region { section Veneer$$CMSE }; if (isdefinedsymbol(__use_shmem__)) { place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; } -place in core1_region { block SEC_CORE_IMAGE_BLOCK }; +place in core1_region { block CORE1_IMAGE_WBLOCK }; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf index d76623985f..59e107cb9d 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core0_ram.icf @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b200722 ** ** Abstract: ** Linker file for the IAR ANSI C/C++ Compiler for ARM ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -40,13 +41,13 @@ if (isdefinedsymbol(__heap_size__)) { } define symbol m_interrupts_start = 0x04000000; -define symbol m_interrupts_end = 0x0400013F; +define symbol m_interrupts_end = 0x040001FF; -define symbol m_text_start = 0x04000140; +define symbol m_text_start = 0x04000200; define symbol m_text_end = 0x04007FFF; define exported symbol core1_image_start = 0x20033000; -define exported symbol core1_image_end = 0x2003B7FF; +define exported symbol core1_image_end = 0x2003F7FF; if (isdefinedsymbol(__use_shmem__)) { define symbol m_data_start = 0x20000000; @@ -77,7 +78,7 @@ define block RW { readwrite }; define block ZI { zi }; define region core1_region = mem:[from core1_image_start to core1_image_end]; -define block SEC_CORE_IMAGE_BLOCK { section __sec_core }; +define block CORE1_IMAGE_WBLOCK { section __core1_image }; /* regions for USB */ define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1]; @@ -107,5 +108,5 @@ place in CSTACK_region { block CSTACK }; if (isdefinedsymbol(__use_shmem__)) { place in rpmsg_sh_mem_region { section rpmsg_sh_mem_section }; } -place in core1_region { block SEC_CORE_IMAGE_BLOCK }; +place in core1_region { block CORE1_IMAGE_WBLOCK }; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_flash.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_flash.icf index bbd8748a6f..fa8b4bdf7c 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_flash.icf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_flash.icf @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b210928 ** ** Abstract: ** Linker file for the IAR ANSI C/C++ Compiler for ARM ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -40,10 +41,10 @@ if (isdefinedsymbol(__heap_size__)) { } define symbol m_interrupts_start = 0x00072000; -define symbol m_interrupts_end = 0x0007213F; +define symbol m_interrupts_end = 0x000721FF; -define symbol m_text_start = 0x00072140; -define symbol m_text_end = 0x00097FFF; +define symbol m_text_start = 0x00072200; +define symbol m_text_end = 0x0009D7FF; define symbol m_data_start = 0x20033000; diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf index 661476cab4..72b086d479 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram.icf @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b200722 ** ** Abstract: ** Linker file for the IAR ANSI C/C++ Compiler for ARM ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2020 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -40,13 +41,13 @@ if (isdefinedsymbol(__heap_size__)) { } define symbol m_interrupts_start = 0x20033000; -define symbol m_interrupts_end = 0x2003313F; +define symbol m_interrupts_end = 0x200331FF; -define symbol m_text_start = 0x20033140; -define symbol m_text_end = 0x2003E7FF; +define symbol m_text_start = 0x20033200; +define symbol m_text_end = 0x2003F7FF; -define symbol m_data_start = 0x2003E800; +define symbol m_data_start = 0x2003F800; define symbol m_data_end = 0x20043FFF; if (isdefinedsymbol(__use_shmem__)) { diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram_s.icf b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram_s.icf index 3591babb59..13d49a18da 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram_s.icf +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/LPC55S69_cm33_core1_ram_s.icf @@ -1,18 +1,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compiler: IAR ANSI C/C++ Compiler for ARM -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b180921 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b190926 ** ** Abstract: ** Linker file for the IAR ANSI C/C++ Compiler for ARM ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2019 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -40,13 +41,13 @@ if (isdefinedsymbol(__heap_size__)) { } define symbol m_interrupts_start = 0x30033000; -define symbol m_interrupts_end = 0x3003313F; +define symbol m_interrupts_end = 0x300331FF; -define symbol m_text_start = 0x30033140; -define symbol m_text_end = 0x3003E7FF; +define symbol m_text_start = 0x30033200; +define symbol m_text_end = 0x3003F7FF; -define symbol m_data_start = 0x3003E800; +define symbol m_data_start = 0x3003F800; define symbol m_data_end = 0x30043FFF; if (isdefinedsymbol(__use_shmem__)) { diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/iar_lib_power_cm33_core0.a b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/iar/iar_lib_power_cm33_core0.a deleted file mode 100644 index ce1d68e47057a140b54c9c556879ef82f37c148c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 13510 zcmeHNeRNypd4KMeEXj(U$Z--JCl1#i0SB-n+mhqZKxNAxapJ@#As+*^l5ESC6Il|H zoDXQR6G8}Epy6XcSy#5vozbpm%khD>+aWaJur)BCA;8K<%M9go#2H0NTES`+J_}KJW8>-uHc_;#K}wSMXZvawRiWIh|E2ohuwQHHu;vs?>L_ z!y#CWvr2uyXC~Ulpe<-TtV*(;wbGMORb3J$Q45F5DOK#sdj&e0Mw% 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zm+{(7D36i*hjBB}Z#f^AY6fpdyX#oSh)%E5aWmtssE3Ym#w|pLbbJwgI&Ulbl@USm zF5`Bhi;O$qFVNbLa^U+sY?yL@%$Mj`${0X>aI)%it3u)*dnbv0&sfFG_y-=Di@cJYo-MV_Ypvi@lxLGh>bs z>rlDAXU6yylM}`-wgE&KzbKOM&tg=-SR;xS8)7WS=s10Ejd8i0IpP7Xh>bFqMKSo{ zlGrF~jEE<=Mud1OX2ke|i$sX`Qbwn66_b^|H%EKJWwEg?V{Fv->P`Ayy;Qi=6mOtGmO z?spMGy698jD1wHc{kksWKIi_G?fn`7bwmW2uA~D(DfynI^IZs}cjX6lIrkI$Xrwm8 zs>>h}B7}sVh-2J;8+toM5GR#HyyKSJSFZE_EETUJNhSOmdI*`ca?f8z4_%w4_aXGY zld?8-^R;PuhY`@C52sYb-7fr!F{jH(+g^-8AXn=ST(aI-=p9AHSkI8N-t=-0 zVc^Wve$&hSCG?DP(KRB?WbaqdtJm{om~O9N#gsiUM?iTddu7nuCL7Z4r`x+zvWKn~ zX(oF|W@&F!vM1&!Se(gTVwUzAS5DPe%yE~ow+(u;iGyLuo|q#qWADjX+Iw5FhmaL% zruzP7miEdp@fz{MW1G`V_UfQFoBGBjduVczX0mq(db5gW$sTSmYwuUcoQ;3^+Ejgu zKF3}O^jh_N8K%c`5PC-YmFS8y)%Q;5&1SqElkBbf9D6TAZ#ModK_w0U#2N{kGx>K7 z^k!o(EZJN0IsOeo56kao()9K_DcQp|L!_DfI}5$p^slXWs=noty>H{*q#t>)Sc9I2 zZ>FX1gJ(;!A?PL4 //#define SYSCON_BASE ((uint32_t) 0x40000000) -#define SYSCON_BASE ((uint32_t) 0x50000000) +#define SYSCON_BASE ((uint32_t)0x50000000) -#define CPBOOT (((volatile uint32_t *) (SYSCON_BASE + 0x804))) -#define CPUCTRL (((volatile uint32_t *) (SYSCON_BASE + 0x800))) -#define CPUCFG (((volatile uint32_t *) (SYSCON_BASE + 0xFD4))) - -#define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16)) -#define CORE1_CLK_ENA (1<<3) -#define CORE1_RESET_ENA (1<<5) -#define CORE1_ENABLE (1 <<2) +#define CPBOOT (((volatile uint32_t *)(SYSCON_BASE + 0x804))) +#define CPUCTRL (((volatile uint32_t *)(SYSCON_BASE + 0x800))) +#define CPUCFG (((volatile uint32_t *)(SYSCON_BASE + 0xFD4))) +#define CPUCTRL_KEY ((uint32_t)(0x0000C0C4 << 16)) +#define CORE1_CLK_ENA (1 << 3) +#define CORE1_RESET_ENA (1 << 5) +#define CORE1_ENABLE (1 << 2) extern uint8_t __core_m33slave_START__; -void boot_multicore_slave(void) { - +void boot_multicore_slave(void) +{ volatile uint32_t *u32REG, u32Val; - unsigned int *slavevectortable_ptr = - (uint32_t *) &__core_m33slave_START__; + unsigned int *slavevectortable_ptr = (unsigned int *)&__core_m33slave_START__; // Enable CPU1 in SYSCON->CPUCFG - *CPUCFG |= CORE1_ENABLE; + *CPUCFG |= CORE1_ENABLE; - // Set CPU1 boot address in SYSCON->CPBoot - *CPBOOT = (uint32_t) slavevectortable_ptr; + // Set CPU1 boot address in SYSCON->CPBoot + *CPBOOT = (uint32_t)slavevectortable_ptr; - // Read SYSCON->CPUCTRL and set key value in bits 31:16 - u32REG = (uint32_t *) CPUCTRL; - u32Val = *u32REG | CPUCTRL_KEY; + // Read SYSCON->CPUCTRL and set key value in bits 31:16 + u32REG = (uint32_t *)CPUCTRL; + u32Val = *u32REG | CPUCTRL_KEY; - // Enable slave clock and reset in SYSCON->CPUCTRL - *u32REG = u32Val | CORE1_CLK_ENA | CORE1_RESET_ENA; - - // Clear slave reset in SYSCON->CPUCTRL - *u32REG = (u32Val | CORE1_CLK_ENA) & (~CORE1_RESET_ENA); + // Enable slave clock and reset in SYSCON->CPUCTRL + *u32REG = u32Val | CORE1_CLK_ENA | CORE1_RESET_ENA; + // Clear slave reset in SYSCON->CPUCTRL + *u32REG = (u32Val | CORE1_CLK_ENA) & (~CORE1_RESET_ENA); } -#endif //defined (__MULTICORE_MASTER) +#endif // defined (__MULTICORE_MASTER) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/boot_multicore_slave.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/boot_multicore_slave.h index 2e1f9761a0..173fa0b72e 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/boot_multicore_slave.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/boot_multicore_slave.h @@ -4,37 +4,17 @@ // Header for functions used for booting of slave core in multicore system //***************************************************************************** // -// Copyright 2014, NXP +// Copyright 2016-2019 NXP // All rights reserved. // -// Software that is described herein is for illustrative purposes only -// which provides customers with programming information regarding the -// LPC products. This software is supplied "AS IS" without any warranties of -// any kind, and NXP Semiconductors and its licensor disclaim any and -// all warranties, express or implied, including all implied warranties of -// merchantability, fitness for a particular purpose and non-infringement of -// intellectual property rights. NXP Semiconductors assumes no responsibility -// or liability for the use of the software, conveys no license or rights under any -// patent, copyright, mask work right, or any other intellectual property rights in -// or to any products. NXP Semiconductors reserves the right to make changes -// in the software without notification. NXP Semiconductors also makes no -// representation or warranty that such application will be suitable for the -// specified use without further testing or modification. -// -// Permission to use, copy, modify, and distribute this software and its -// documentation is hereby granted, under NXP Semiconductors' and its -// licensor's relevant copyrights in the software, without fee, provided that it -// is used in conjunction with NXP Semiconductors microcontrollers. This -// copyright, permission, and disclaimer notice must appear in all copies of -// this code. +// SPDX-License-Identifier: BSD-3-Clause //***************************************************************************** #ifndef BOOT_MULTICORE_SLAVE_H_ #define BOOT_MULTICORE_SLAVE_H_ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif void boot_multicore_slave(void); diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.c index 6227ec529d..c6b7bdc571 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.c @@ -1,10 +1,10 @@ //***************************************************************************** // LPC55S69_cm33_core0 startup code for use with MCUXpresso IDE // -// Version : 240619 +// Version : 010621 //***************************************************************************** // -// Copyright 2016-2019 NXP +// Copyright 2016-2021 NXP // All rights reserved. // // SPDX-License-Identifier: BSD-3-Clause @@ -44,6 +44,7 @@ extern "C" { // by the linker when "Enable Code Read Protect" selected. // See crp.h header for more information //***************************************************************************** + //***************************************************************************** // Declaration of external SystemInit function //***************************************************************************** @@ -124,7 +125,7 @@ WEAK void SDIO_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); WEAK void Reserved61_IRQHandler(void); -WEAK void USB1_UTMI_IRQHandler(void); +WEAK void USB1_PHY_IRQHandler(void); WEAK void USB1_IRQHandler(void); WEAK void USB1_NEEDCLK_IRQHandler(void); WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); @@ -191,7 +192,7 @@ void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB1_UTMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_PHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); @@ -224,6 +225,7 @@ extern void _vStackTop(void); // External declaration for LPC MCU vector table checksum from Linker Script //***************************************************************************** WEAK extern void __valid_user_code_checksum(); +extern void _vStackBase(void); //***************************************************************************** //***************************************************************************** @@ -234,6 +236,9 @@ WEAK extern void __valid_user_code_checksum(); // The vector table. // This relies on the linker script to place at correct location in memory. //***************************************************************************** + + + extern void (* const g_pfnVectors[])(void); extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); @@ -304,7 +309,7 @@ void (* const g_pfnVectors[])(void) = { Reserved59_IRQHandler, // 59: Reserved interrupt Reserved60_IRQHandler, // 60: Reserved interrupt Reserved61_IRQHandler, // 61: Reserved interrupt - USB1_UTMI_IRQHandler, // 62: USB1_UTMI + USB1_PHY_IRQHandler, // 62: USB1_PHY USB1_IRQHandler, // 63: USB1 interrupt USB1_NEEDCLK_IRQHandler, // 64: USB1 activity SEC_HYPERVISOR_CALL_IRQHandler, // 65: SEC_HYPERVISOR_CALL interrupt @@ -319,6 +324,7 @@ void (* const g_pfnVectors[])(void) = { DMA1_IRQHandler, // 74: DMA1 interrupt FLEXCOMM8_IRQHandler, // 75: Flexcomm Interface 8 (SPI, , FLEXCOMM) + }; /* End of g_pfnVectors */ //***************************************************************************** @@ -361,12 +367,24 @@ extern unsigned int __bss_section_table_end; // Sets up a simple runtime environment and initializes the C/C++ // library. //***************************************************************************** -__attribute__ ((section(".after_vectors.reset"))) +__attribute__ ((naked, section(".after_vectors.reset"))) void ResetISR(void) { + // Disable interrupts __asm volatile ("cpsid i"); + // Config VTOR & MSPLIM register + __asm volatile ("LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(g_pfnVectors), "r"(_vStackBase) + : "r0", "r1"); + + #if defined (__USE_CMSIS) @@ -681,8 +699,8 @@ WEAK void Reserved61_IRQHandler(void) { Reserved61_DriverIRQHandler(); } -WEAK void USB1_UTMI_IRQHandler(void) -{ USB1_UTMI_DriverIRQHandler(); +WEAK void USB1_PHY_IRQHandler(void) +{ USB1_PHY_DriverIRQHandler(); } WEAK void USB1_IRQHandler(void) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.cpp b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.cpp index 6227ec529d..c6b7bdc571 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.cpp +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core0.cpp @@ -1,10 +1,10 @@ //***************************************************************************** // LPC55S69_cm33_core0 startup code for use with MCUXpresso IDE // -// Version : 240619 +// Version : 010621 //***************************************************************************** // -// Copyright 2016-2019 NXP +// Copyright 2016-2021 NXP // All rights reserved. // // SPDX-License-Identifier: BSD-3-Clause @@ -44,6 +44,7 @@ extern "C" { // by the linker when "Enable Code Read Protect" selected. // See crp.h header for more information //***************************************************************************** + //***************************************************************************** // Declaration of external SystemInit function //***************************************************************************** @@ -124,7 +125,7 @@ WEAK void SDIO_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); WEAK void Reserved61_IRQHandler(void); -WEAK void USB1_UTMI_IRQHandler(void); +WEAK void USB1_PHY_IRQHandler(void); WEAK void USB1_IRQHandler(void); WEAK void USB1_NEEDCLK_IRQHandler(void); WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); @@ -191,7 +192,7 @@ void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB1_UTMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_PHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); @@ -224,6 +225,7 @@ extern void _vStackTop(void); // External declaration for LPC MCU vector table checksum from Linker Script //***************************************************************************** WEAK extern void __valid_user_code_checksum(); +extern void _vStackBase(void); //***************************************************************************** //***************************************************************************** @@ -234,6 +236,9 @@ WEAK extern void __valid_user_code_checksum(); // The vector table. // This relies on the linker script to place at correct location in memory. //***************************************************************************** + + + extern void (* const g_pfnVectors[])(void); extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); @@ -304,7 +309,7 @@ void (* const g_pfnVectors[])(void) = { Reserved59_IRQHandler, // 59: Reserved interrupt Reserved60_IRQHandler, // 60: Reserved interrupt Reserved61_IRQHandler, // 61: Reserved interrupt - USB1_UTMI_IRQHandler, // 62: USB1_UTMI + USB1_PHY_IRQHandler, // 62: USB1_PHY USB1_IRQHandler, // 63: USB1 interrupt USB1_NEEDCLK_IRQHandler, // 64: USB1 activity SEC_HYPERVISOR_CALL_IRQHandler, // 65: SEC_HYPERVISOR_CALL interrupt @@ -319,6 +324,7 @@ void (* const g_pfnVectors[])(void) = { DMA1_IRQHandler, // 74: DMA1 interrupt FLEXCOMM8_IRQHandler, // 75: Flexcomm Interface 8 (SPI, , FLEXCOMM) + }; /* End of g_pfnVectors */ //***************************************************************************** @@ -361,12 +367,24 @@ extern unsigned int __bss_section_table_end; // Sets up a simple runtime environment and initializes the C/C++ // library. //***************************************************************************** -__attribute__ ((section(".after_vectors.reset"))) +__attribute__ ((naked, section(".after_vectors.reset"))) void ResetISR(void) { + // Disable interrupts __asm volatile ("cpsid i"); + // Config VTOR & MSPLIM register + __asm volatile ("LDR R0, =0xE000ED08 \n" + "STR %0, [R0] \n" + "LDR R1, [%0] \n" + "MSR MSP, R1 \n" + "MSR MSPLIM, %1 \n" + : + : "r"(g_pfnVectors), "r"(_vStackBase) + : "r0", "r1"); + + #if defined (__USE_CMSIS) @@ -681,8 +699,8 @@ WEAK void Reserved61_IRQHandler(void) { Reserved61_DriverIRQHandler(); } -WEAK void USB1_UTMI_IRQHandler(void) -{ USB1_UTMI_DriverIRQHandler(); +WEAK void USB1_PHY_IRQHandler(void) +{ USB1_PHY_DriverIRQHandler(); } WEAK void USB1_IRQHandler(void) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.c index ed5a436068..5bd89fd75b 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.c @@ -1,10 +1,10 @@ //***************************************************************************** // LPC55S69_cm33_core1 startup code for use with MCUXpresso IDE // -// Version : 240619 +// Version : 160420 //***************************************************************************** // -// Copyright 2016-2019 NXP +// Copyright 2016-2020 NXP // All rights reserved. // // SPDX-License-Identifier: BSD-3-Clause @@ -124,7 +124,7 @@ WEAK void SDIO_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); WEAK void Reserved61_IRQHandler(void); -WEAK void USB1_UTMI_IRQHandler(void); +WEAK void USB1_PHY_IRQHandler(void); WEAK void USB1_IRQHandler(void); WEAK void USB1_NEEDCLK_IRQHandler(void); WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); @@ -191,7 +191,7 @@ void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB1_UTMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_PHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); @@ -234,6 +234,9 @@ WEAK extern void __valid_user_code_checksum(); // The vector table. // This relies on the linker script to place at correct location in memory. //***************************************************************************** + + + extern void (* const g_pfnVectors[])(void); extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); @@ -304,7 +307,7 @@ void (* const g_pfnVectors[])(void) = { Reserved59_IRQHandler, // 59: Reserved interrupt Reserved60_IRQHandler, // 60: Reserved interrupt Reserved61_IRQHandler, // 61: Reserved interrupt - USB1_UTMI_IRQHandler, // 62: USB1_UTMI + USB1_PHY_IRQHandler, // 62: USB1_PHY USB1_IRQHandler, // 63: USB1 interrupt USB1_NEEDCLK_IRQHandler, // 64: USB1 activity SEC_HYPERVISOR_CALL_IRQHandler, // 65: SEC_HYPERVISOR_CALL interrupt @@ -319,6 +322,7 @@ void (* const g_pfnVectors[])(void) = { DMA1_IRQHandler, // 74: DMA1 interrupt FLEXCOMM8_IRQHandler, // 75: Flexcomm Interface 8 (SPI, , FLEXCOMM) + }; /* End of g_pfnVectors */ //***************************************************************************** @@ -361,7 +365,7 @@ extern unsigned int __bss_section_table_end; // Sets up a simple runtime environment and initializes the C/C++ // library. //***************************************************************************** -__attribute__ ((section(".after_vectors.reset"))) +__attribute__ ((naked, section(".after_vectors.reset"))) void ResetISR(void) { // Disable interrupts @@ -681,8 +685,8 @@ WEAK void Reserved61_IRQHandler(void) { Reserved61_DriverIRQHandler(); } -WEAK void USB1_UTMI_IRQHandler(void) -{ USB1_UTMI_DriverIRQHandler(); +WEAK void USB1_PHY_IRQHandler(void) +{ USB1_PHY_DriverIRQHandler(); } WEAK void USB1_IRQHandler(void) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.cpp b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.cpp index ed5a436068..5bd89fd75b 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.cpp +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/mcuxpresso/startup_lpc55s69_cm33_core1.cpp @@ -1,10 +1,10 @@ //***************************************************************************** // LPC55S69_cm33_core1 startup code for use with MCUXpresso IDE // -// Version : 240619 +// Version : 160420 //***************************************************************************** // -// Copyright 2016-2019 NXP +// Copyright 2016-2020 NXP // All rights reserved. // // SPDX-License-Identifier: BSD-3-Clause @@ -124,7 +124,7 @@ WEAK void SDIO_IRQHandler(void); WEAK void Reserved59_IRQHandler(void); WEAK void Reserved60_IRQHandler(void); WEAK void Reserved61_IRQHandler(void); -WEAK void USB1_UTMI_IRQHandler(void); +WEAK void USB1_PHY_IRQHandler(void); WEAK void USB1_IRQHandler(void); WEAK void USB1_NEEDCLK_IRQHandler(void); WEAK void SEC_HYPERVISOR_CALL_IRQHandler(void); @@ -191,7 +191,7 @@ void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved59_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved60_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void Reserved61_DriverIRQHandler(void) ALIAS(IntDefaultHandler); -void USB1_UTMI_DriverIRQHandler(void) ALIAS(IntDefaultHandler); +void USB1_PHY_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler); void SEC_HYPERVISOR_CALL_DriverIRQHandler(void) ALIAS(IntDefaultHandler); @@ -234,6 +234,9 @@ WEAK extern void __valid_user_code_checksum(); // The vector table. // This relies on the linker script to place at correct location in memory. //***************************************************************************** + + + extern void (* const g_pfnVectors[])(void); extern void * __Vectors __attribute__ ((alias ("g_pfnVectors"))); @@ -304,7 +307,7 @@ void (* const g_pfnVectors[])(void) = { Reserved59_IRQHandler, // 59: Reserved interrupt Reserved60_IRQHandler, // 60: Reserved interrupt Reserved61_IRQHandler, // 61: Reserved interrupt - USB1_UTMI_IRQHandler, // 62: USB1_UTMI + USB1_PHY_IRQHandler, // 62: USB1_PHY USB1_IRQHandler, // 63: USB1 interrupt USB1_NEEDCLK_IRQHandler, // 64: USB1 activity SEC_HYPERVISOR_CALL_IRQHandler, // 65: SEC_HYPERVISOR_CALL interrupt @@ -319,6 +322,7 @@ void (* const g_pfnVectors[])(void) = { DMA1_IRQHandler, // 74: DMA1 interrupt FLEXCOMM8_IRQHandler, // 75: Flexcomm Interface 8 (SPI, , FLEXCOMM) + }; /* End of g_pfnVectors */ //***************************************************************************** @@ -361,7 +365,7 @@ extern unsigned int __bss_section_table_end; // Sets up a simple runtime environment and initializes the C/C++ // library. //***************************************************************************** -__attribute__ ((section(".after_vectors.reset"))) +__attribute__ ((naked, section(".after_vectors.reset"))) void ResetISR(void) { // Disable interrupts @@ -681,8 +685,8 @@ WEAK void Reserved61_IRQHandler(void) { Reserved61_DriverIRQHandler(); } -WEAK void USB1_UTMI_IRQHandler(void) -{ USB1_UTMI_DriverIRQHandler(); +WEAK void USB1_PHY_IRQHandler(void) +{ USB1_PHY_DriverIRQHandler(); } WEAK void USB1_IRQHandler(void) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/board.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/board.c new file mode 100644 index 0000000000..6aeed9baf1 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/board.c @@ -0,0 +1,31 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include "fsl_common.h" +#include "fsl_debug_console.h" +#include "board.h" + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/* Initialize debug console. */ +void BOARD_InitDebugConsole(void) +{ + /* attach 12 MHz clock to FLEXCOMM0 (debug console) */ + CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH); + + RESET_ClearPeripheralReset(BOARD_DEBUG_UART_RST); + + uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ; + + DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/board.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/board.h new file mode 100644 index 0000000000..870d99aeb4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/board.h @@ -0,0 +1,251 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#include "clock_config.h" +#include "fsl_common.h" +#include "fsl_reset.h" +#include "fsl_gpio.h" +#include "fsl_iocon.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The board name */ +#define BOARD_NAME "LPCXpresso55S69" + +/*! @brief The UART to use for debug messages. */ +/* TODO: rename UART to USART */ +#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart +#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0 +#define BOARD_DEBUG_UART_INSTANCE 0U +#define BOARD_DEBUG_UART_CLK_FREQ 12000000U +#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0 +#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn +#define BOARD_DEBUG_UART_CLKSRC kCLOCK_Flexcomm0 +#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler +#define BOARD_UART_IRQ FLEXCOMM0_IRQn + +#define BOARD_ACCEL_I2C_BASEADDR I2C4 +#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000 + +#define BOARD_DEBUG_UART_TYPE_CORE1 kSerialPort_Uart +#define BOARD_DEBUG_UART_BASEADDR_CORE1 (uint32_t) USART1 +#define BOARD_DEBUG_UART_INSTANCE_CORE1 1U +#define BOARD_DEBUG_UART_CLK_FREQ_CORE1 12000000U +#define BOARD_DEBUG_UART_CLK_ATTACH_CORE1 kFRO12M_to_FLEXCOMM1 +#define BOARD_DEBUG_UART_RST_CORE1 kFC1_RST_SHIFT_RSTn +#define BOARD_DEBUG_UART_CLKSRC_CORE1 kCLOCK_Flexcomm1 +#define BOARD_UART_IRQ_HANDLER_CORE1 FLEXCOMM1_IRQHandler +#define BOARD_UART_IRQ_CORE1 FLEXCOMM1_IRQn + +#ifndef BOARD_DEBUG_UART_BAUDRATE +#define BOARD_DEBUG_UART_BAUDRATE 115200U +#endif /* BOARD_DEBUG_UART_BAUDRATE */ + +#ifndef BOARD_DEBUG_UART_BAUDRATE_CORE1 +#define BOARD_DEBUG_UART_BAUDRATE_CORE1 115200U +#endif /* BOARD_DEBUG_UART_BAUDRATE_CORE1 */ + +#define BOARD_CODEC_I2C_BASEADDR I2C4 +#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000 + +#ifndef BOARD_LED_RED_GPIO +#define BOARD_LED_RED_GPIO GPIO +#endif +#define BOARD_LED_RED_GPIO_PORT 1U +#ifndef BOARD_LED_RED_GPIO_PIN +#define BOARD_LED_RED_GPIO_PIN 6U +#endif + +#ifndef BOARD_LED_BLUE_GPIO +#define BOARD_LED_BLUE_GPIO GPIO +#endif +#define BOARD_LED_BLUE_GPIO_PORT 1U +#ifndef BOARD_LED_BLUE_GPIO_PIN +#define BOARD_LED_BLUE_GPIO_PIN 4U +#endif + +#ifndef BOARD_LED_GREEN_GPIO +#define BOARD_LED_GREEN_GPIO GPIO +#endif +#define BOARD_LED_GREEN_GPIO_PORT 1U +#ifndef BOARD_LED_GREEN_GPIO_PIN +#define BOARD_LED_GREEN_GPIO_PIN 7U +#endif + +#ifndef BOARD_SW1_GPIO +#define BOARD_SW1_GPIO GPIO +#endif +#define BOARD_SW1_GPIO_PORT 0U +#ifndef BOARD_SW1_GPIO_PIN +#define BOARD_SW1_GPIO_PIN 5U +#endif +#define BOARD_SW1_NAME "SW1" +#define BOARD_SW1_IRQ PIN_INT0_IRQn +#define BOARD_SW1_IRQ_HANDLER PIN_INT0_IRQHandler + +#ifndef BOARD_SW2_GPIO +#define BOARD_SW2_GPIO GPIO +#endif +#define BOARD_SW2_GPIO_PORT 1U +#ifndef BOARD_SW2_GPIO_PIN +#define BOARD_SW2_GPIO_PIN 18U +#endif +#define BOARD_SW2_NAME "SW2" +#define BOARD_SW2_IRQ PIN_INT1_IRQn +#define BOARD_SW2_IRQ_HANDLER PIN_INT1_IRQHandler +#define BOARD_SW2_GPIO_PININT_INDEX 1 + +#ifndef BOARD_SW3_GPIO +#define BOARD_SW3_GPIO GPIO +#endif +#define BOARD_SW3_GPIO_PORT 1U +#ifndef BOARD_SW3_GPIO_PIN +#define BOARD_SW3_GPIO_PIN 9U +#endif +#define BOARD_SW3_NAME "SW3" +#define BOARD_SW3_IRQ PIN_INT1_IRQn +#define BOARD_SW3_IRQ_HANDLER PIN_INT1_IRQHandler +#define BOARD_SW3_GPIO_PININT_INDEX 1 + +#define BOARD_SDIF_BASEADDR SDIF +#define BOARD_SDIF_CLKSRC kCLOCK_SDio +#define BOARD_SDIF_CLK_FREQ CLOCK_GetSdioClkFreq() +#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK +#define BOARD_SDIF_IRQ SDIO_IRQn +#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360 +#define BOARD_SD_CARD_DETECT_PIN 17 +#define BOARD_SD_CARD_DETECT_PORT 0 +#define BOARD_SD_CARD_DETECT_GPIO GPIO +#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD + +#define BOARD_SDIF_CD_GPIO_INIT() \ + { \ + CLOCK_EnableClock(kCLOCK_Gpio2); \ + GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \ + } +#define BOARD_SDIF_CD_STATUS() \ + GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN) + +/* Board led color mapping */ +#define LOGIC_LED_ON 0U +#define LOGIC_LED_OFF 1U + +#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK + +#define LED_RED_INIT(output) \ + { \ + IOCON_PinMuxSet(IOCON, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \ + (IOCON_PIO_FUNC0 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | \ + IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI)); \ + GPIO_PinInit(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, BOARD_LED_RED_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \ + } +#define LED_RED_ON() \ + GPIO_PortClear(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ + 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn on target LED1 */ +#define LED_RED_OFF() \ + GPIO_PortSet(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ + 1U << BOARD_LED_RED_GPIO_PIN) /*!< Turn off target LED1 \ \ \ \ \ \ \ \ \ \ \ + */ +#define LED_RED_TOGGLE() \ + GPIO_PortToggle(BOARD_LED_RED_GPIO, BOARD_LED_RED_GPIO_PORT, \ + 1U << BOARD_LED_RED_GPIO_PIN) /*!< Toggle on target LED1 */ + +#define LED_BLUE_INIT(output) \ + { \ + IOCON_PinMuxSet(IOCON, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \ + (IOCON_PIO_FUNC0 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | \ + IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI)); \ + GPIO_PinInit(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, BOARD_LED_BLUE_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}); /*!< Enable target LED1 */ \ + } +#define LED_BLUE_ON() \ + GPIO_PortClear(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ + 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn on target LED1 */ +#define LED_BLUE_OFF() \ + GPIO_PortSet(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ + 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Turn off target LED1 */ +#define LED_BLUE_TOGGLE() \ + GPIO_PortToggle(BOARD_LED_BLUE_GPIO, BOARD_LED_BLUE_GPIO_PORT, \ + 1U << BOARD_LED_BLUE_GPIO_PIN) /*!< Toggle on target LED1 */ + +#define LED_GREEN_INIT(output) \ + GPIO_PinInit(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, BOARD_LED_GREEN_GPIO_PIN, \ + &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */ +#define LED_GREEN_ON() \ + GPIO_PortClear(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ + 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn on target LED1 */ +#define LED_GREEN_OFF() \ + GPIO_PortSet(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ + 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Turn off target LED1 */ +#define LED_GREEN_TOGGLE() \ + GPIO_PortToggle(BOARD_LED_GREEN_GPIO, BOARD_LED_GREEN_GPIO_PORT, \ + 1U << BOARD_LED_GREEN_GPIO_PIN) /*!< Toggle on target LED1 */ + +/*! @brief The WIFI-QCA shield pin. */ +#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO +#define BOARD_INITGT202SHIELD_PWRON_PORT 1U +#define BOARD_INITGT202SHIELD_PWRON_PIN 8U + +#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO +#define BOARD_INITGT202SHIELD_IRQ_PORT 1U +#define BOARD_INITGT202SHIELD_IRQ_PIN 9U + +/*! @brief The WIFI-QCA shield pin. */ +#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO +#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 1U +#define BOARD_INITSILEX2401SHIELD_PWRON_PIN 7U + +#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO +#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 0U +#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 15U + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +void BOARD_InitDebugConsole(void); +void BOARD_InitDebugConsole_Core1(void); +#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED +void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz); +status_t BOARD_I2C_Send(I2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *txBuff, + uint8_t txBuffSize); +status_t BOARD_I2C_Receive(I2C_Type *base, + uint8_t deviceAddress, + uint32_t subAddress, + uint8_t subaddressSize, + uint8_t *rxBuff, + uint8_t rxBuffSize); +void BOARD_Accel_I2C_Init(void); +status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff); +status_t BOARD_Accel_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); +void BOARD_Codec_I2C_Init(void); +status_t BOARD_Codec_I2C_Send( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize); +status_t BOARD_Codec_I2C_Receive( + uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize); +#endif /* SDK_I2C_BASED_COMPONENT_USED */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/clock_config.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/clock_config.c new file mode 100644 index 0000000000..1d45e5319b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/clock_config.c @@ -0,0 +1,374 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ +/* + * How to set up clock using clock driver functions: + * + * 1. Setup clock sources. + * + * 2. Set up wait states of the flash. + * + * 3. Set up all dividers. + * + * 4. Set up all selectors to provide selected clocks. + */ + +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v7.0 +processor: LPC55S69 +mcu_data: ksdk2_0 +processor_version: 0.7.2 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +#include "fsl_power.h" +#include "fsl_clock.h" +#include "clock_config.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* System clock frequency. */ +extern uint32_t SystemCoreClock; + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ +void BOARD_InitBootClocks(void) +{ + BOARD_BootClockPLL150M(); +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFRO12M +outputs: +- {id: System_clock.outFreq, value: 12 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +void BOARD_BootClockFRO12M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq( + 12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockFROHF96M +outputs: +- {id: System_clock.outFreq, value: 96 MHz} +settings: +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +void BOARD_BootClockFROHF96M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + POWER_SetVoltageForFreq( + 96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL100M +outputs: +- {id: System_clock.outFreq, value: 100 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ANALOG_CONTROL_FRO192M_CTRL_ENDI_FRO_96M_CFG, value: Enable} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true} +sources: +- {id: ANACTRL.fro_hf.outFreq, value: 96 MHz} +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +void BOARD_BootClockPLL100M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq( + 100000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(26U), + .pllndec = SYSCON_PLL0NDEC_NDIV(4U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(2U), + .pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 100000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL150M +called_from_default_init: true +outputs: +- {id: System_clock.outFreq, value: 150 MHz} +settings: +- {id: PLL0_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS} +- {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL0M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL0N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL0_PDEC.scale, value: '2', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq( + 150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL */ + CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ + POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); + const pll_setup_t pll0Setup = { + .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), + .pllndec = SYSCON_PLL0NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL0PDEC_PDIV(1U), + .pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(150U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)}, + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK}; + CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK; +#endif +} + +/******************************************************************************* + ******************* Configuration BOARD_BootClockPLL1_150M ******************** + ******************************************************************************/ +/* clang-format off */ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockPLL1_150M +outputs: +- {id: System_clock.outFreq, value: 150 MHz} +settings: +- {id: PLL1_Mode, value: Normal} +- {id: ENABLE_CLKIN_ENA, value: Enabled} +- {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled} +- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL1_BYPASS} +- {id: SYSCON.PLL1CLKSEL.sel, value: SYSCON.CLK_IN_EN} +- {id: SYSCON.PLL1M_MULT.scale, value: '150', locked: true} +- {id: SYSCON.PLL1N_DIV.scale, value: '8', locked: true} +- {id: SYSCON.PLL1_PDEC.scale, value: '2', locked: true} +sources: +- {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* clang-format on */ + +/******************************************************************************* + * Variables for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +/******************************************************************************* + * Code for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +void BOARD_BootClockPLL1_150M(void) +{ +#ifndef SDK_SECONDARY_CORE + /*!< Set up the clock sources */ + /*!< Configure FRO192M */ + POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */ + CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */ + CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */ + + /*!< Configure XTAL32M */ + POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */ + POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */ + CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */ + SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */ + ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */ + + POWER_SetVoltageForFreq(150000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */ + CLOCK_SetFLASHAccessCyclesForFreq(150000000U); /*!< Set FLASH wait states for core */ + + /*!< Set up PLL1 */ + CLOCK_AttachClk(kEXT_CLK_to_PLL1); /*!< Switch PLL1CLKSEL to EXT_CLK */ + POWER_DisablePD(kPDRUNCFG_PD_PLL1); /* Ensure PLL is on */ + const pll_setup_t pll1Setup = { + .pllctrl = SYSCON_PLL1CTRL_CLKEN_MASK | SYSCON_PLL1CTRL_SELI(53U) | SYSCON_PLL1CTRL_SELP(31U), + .pllndec = SYSCON_PLL1NDEC_NDIV(8U), + .pllpdec = SYSCON_PLL1PDEC_PDIV(1U), + .pllmdec = SYSCON_PLL1MDEC_MDIV(150U), + .pllRate = 150000000U, + .flags = PLL_SETUPFLAG_WAITLOCK + }; + CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */ + + /*!< Set up dividers */ + CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */ + + /*!< Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */ + + /*< Set SystemCoreClock variable. */ + SystemCoreClock = BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK; +#endif +} + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/clock_config.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/clock_config.h new file mode 100644 index 0000000000..1e37f41b56 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/clock_config.h @@ -0,0 +1,167 @@ +/* + * Copyright 2017-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _CLOCK_CONFIG_H_ +#define _CLOCK_CONFIG_H_ + +#include "fsl_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define BOARD_XTAL0_CLK_HZ 16000000U /*!< Board xtal frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */ + +/******************************************************************************* + ************************ BOARD_InitBootClocks function ************************ + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes default configuration of clocks. + * + */ +void BOARD_InitBootClocks(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockFRO12M ********************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFRO12M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFRO12M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockFROHF96M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency: 96000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockFROHF96M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockFROHF96M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL100M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockPLL100M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL100M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************** Configuration BOARD_BootClockPLL150M ********************* + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ + +/******************************************************************************* + * API for BOARD_BootClockPLL150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +/******************************************************************************* + ******************* Configuration BOARD_BootClockPLL1_150M ******************** + ******************************************************************************/ +/******************************************************************************* + * Definitions for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +#define BOARD_BOOTCLOCKPLL1_150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */ + + +/******************************************************************************* + * API for BOARD_BootClockPLL1_150M configuration + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus*/ + +/*! + * @brief This function executes configuration of clocks. + * + */ +void BOARD_BootClockPLL1_150M(void); + +#if defined(__cplusplus) +} +#endif /* __cplusplus*/ + +#endif /* _CLOCK_CONFIG_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/peripherals.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/peripherals.c new file mode 100644 index 0000000000..e0c5222bca --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/peripherals.c @@ -0,0 +1,23 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Peripherals v1.0 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Included files + ******************************************************************************/ +#include "peripherals.h" + +/******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void) +{ +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/peripherals.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/peripherals.h new file mode 100644 index 0000000000..3df053a6a6 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/peripherals.h @@ -0,0 +1,23 @@ +/* + * Copyright 2017-2018 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _PERIPHERALS_H_ +#define _PERIPHERALS_H_ + +#if defined(__cplusplus) +extern "C" { +#endif /*_cplusplus. */ +/******************************************************************************* + * BOARD_InitBootPeripherals function + ******************************************************************************/ +void BOARD_InitBootPeripherals(void); + +#if defined(__cplusplus) +} +#endif /*_cplusplus. */ + +#endif /* _PERIPHERALS_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/pin_mux.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/pin_mux.c new file mode 100644 index 0000000000..c8d2cb3271 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/pin_mux.c @@ -0,0 +1,61 @@ +/* + * Copyright 2019 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v6.0 +processor: LPC55S69 +mcu_data: ksdk2_0 +processor_version: 0.1.11 + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', enableClock: 'true'} +- pin_list: [] + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +/* Function assigned for the Cortex-M33 (Core #0) */ +void BOARD_InitPins(void) +{ +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/pin_mux.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/pin_mux.h new file mode 100644 index 0000000000..28df852653 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/project_template/pin_mux.h @@ -0,0 +1,52 @@ +/* + * Copyright 2019 NXP. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef _PIN_MUX_H_ +#define _PIN_MUX_H_ + +/*! + * @addtogroup pin_mux + * @{ + */ + +/*********************************************************************************************************************** + * API + **********************************************************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Calls initialization functions. + * + */ +void BOARD_InitBootPins(void); + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitPins(void); + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ +#endif /* _PIN_MUX_H_ */ + +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.c index aedd4504f9..4bb076478a 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.c @@ -1,16 +1,17 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181219 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b220117 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -29,14 +30,16 @@ ** Revisions: ** - rev. 1.0 (2018-08-22) ** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM ** ** ################################################################### */ /*! * @file LPC55S69_cm33_core0 - * @version 1.0 - * @date 2018-08-22 + * @version 1.1 + * @date 2019-05-16 * @brief Device specific configuration file for LPC55S69_cm33_core0 * (implementation file) * @@ -57,15 +60,15 @@ /* Get predivider (N) from PLL0 NDEC setting */ static uint32_t findPll0PreDiv(void) { - uint32_t preDiv = 1; + uint32_t preDiv = 1UL; /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0) + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) { preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0) + if (preDiv == 0UL) { - preDiv = 1; + preDiv = 1UL; } } return preDiv; @@ -76,19 +79,19 @@ static uint32_t findPll0PostDiv(void) { uint32_t postDiv = 1; - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0) + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) { - if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) { postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; } else { - postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); } - if (postDiv == 0) + if (postDiv == 0UL) { - postDiv = 2; + postDiv = 2UL; } } return postDiv; @@ -97,23 +100,25 @@ static uint32_t findPll0PostDiv(void) /* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ static float findPll0MMult(void) { - float mMult = 1; + float mMult = 1.0F; float mMult_fract; uint32_t mMult_int; - if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) { - mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT; + mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); } else { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); - mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M)/(1 << PLL_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; } - if (mMult == 0) + if (0ULL == ((uint64_t)mMult)) { - mMult = 1; + mMult = 1.0F; } return mMult; } @@ -121,15 +126,15 @@ static float findPll0MMult(void) /* Get predivider (N) from PLL1 NDEC setting */ static uint32_t findPll1PreDiv(void) { - uint32_t preDiv = 1; + uint32_t preDiv = 1UL; /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0) + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) { preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0) + if (preDiv == 0UL) { - preDiv = 1; + preDiv = 1UL; } } return preDiv; @@ -138,21 +143,21 @@ static uint32_t findPll1PreDiv(void) /* Get postdivider (P) from PLL1 PDEC setting */ static uint32_t findPll1PostDiv(void) { - uint32_t postDiv = 1; + uint32_t postDiv = 1UL; - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0) + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) { - if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) { postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; } else { - postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); + postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); } - if (postDiv == 0) + if (postDiv == 0UL) { - postDiv = 2; + postDiv = 2UL; } } return postDiv; @@ -161,13 +166,13 @@ static uint32_t findPll1PostDiv(void) /* Get multiplier (M) from PLL1 MDEC settings */ static uint32_t findPll1MMult(void) { - uint32_t mMult = 1; + uint32_t mMult = 1UL; mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; - if (mMult == 0) + if (mMult == 0UL) { - mMult = 1; + mMult = 1UL; } return mMult; } @@ -176,51 +181,47 @@ static uint32_t findPll1MMult(void) /*! brief Return Frequency of FRO 12MHz * return Frequency of FRO 12MHz */ -static uint32_t CLOCK_GetFro12MFreq(void) +static uint32_t GetFro12MFreq(void) { - return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? - 0 : - (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U; + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; } /* Get FRO 1M Clk */ /*! brief Return Frequency of FRO 1MHz * return Frequency of FRO 1MHz */ -static uint32_t CLOCK_GetFro1MFreq(void) +static uint32_t GetFro1MFreq(void) { - return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U; + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; } /* Get EXT OSC Clk */ /*! brief Return Frequency of External Clock * return Frequency of External Clock. If no external clock is used returns 0. */ -static uint32_t CLOCK_GetExtClkFreq(void) +static uint32_t GetExtClkFreq(void) { - return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U; + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U; } /* Get HF FRO Clk */ /*! brief Return Frequency of High-Freq output of FRO * return Frequency of High-Freq output of FRO */ -static uint32_t CLOCK_GetFroHfFreq(void) +static uint32_t GetFroHfFreq(void) { - return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? - 0 : - (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U; + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; } /* Get RTC OSC Clk */ /*! brief Return Frequency of 32kHz osc * return Frequency of 32kHz osc */ -static uint32_t CLOCK_GetOsc32KFreq(void) +static uint32_t GetOsc32KFreq(void) { - return ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (!(PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? CLK_RTC_32K_CLK : - ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK)) ? + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? CLK_RTC_32K_CLK : 0U; } @@ -239,10 +240,16 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; __attribute__ ((weak)) void SystemInit (void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ + #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ - SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access (enable PowerQuad) */ + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ @@ -252,6 +259,12 @@ __attribute__ ((weak)) void SystemInit (void) { #else extern void *__Vectors; SCB->VTOR = (uint32_t) &__Vectors; +#endif + SYSCON->TRACECLKDIV = 0; +/* Optionally enable RAM banks that may be off by default at reset */ +#if !defined(DONT_ENABLE_DISABLED_RAMBANKS) + SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK + | SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK; #endif SystemInitHook(); } @@ -263,7 +276,7 @@ __attribute__ ((weak)) void SystemInit (void) { void SystemCoreClockUpdate (void) { uint32_t clkRate = 0; uint32_t prediv, postdiv; - float workRate; + uint64_t workRate; uint64_t workRate1; switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) @@ -272,16 +285,16 @@ void SystemCoreClockUpdate (void) { switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) { case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLOCK_GetFro12MFreq(); + clkRate = GetFro12MFreq(); break; case 0x01: /* CLKIN (clk_in) */ - clkRate = CLOCK_GetExtClkFreq(); + clkRate = GetExtClkFreq(); break; case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = CLOCK_GetFro1MFreq(); + clkRate = GetFro1MFreq(); break; default: /* = 0x03 = FRO 96 MHz (fro_hf) */ - clkRate = CLOCK_GetFroHfFreq(); + clkRate = GetFroHfFreq(); break; } break; @@ -289,50 +302,52 @@ void SystemCoreClockUpdate (void) { switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) { case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLOCK_GetFro12MFreq(); + clkRate = GetFro12MFreq(); break; case 0x01: /* CLKIN (clk_in) */ - clkRate = CLOCK_GetExtClkFreq(); + clkRate = GetExtClkFreq(); break; case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = CLOCK_GetFro1MFreq(); + clkRate = GetFro1MFreq(); break; case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLOCK_GetOsc32KFreq(); + clkRate = GetOsc32KFreq(); break; default: + clkRate = 0UL; break; } - if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0)) + if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) { prediv = findPll0PreDiv(); postdiv = findPll0PostDiv(); /* Adjust input clock */ clkRate = clkRate / prediv; /* MDEC used for rate */ - workRate = (float)clkRate * (float)findPll0MMult(); - clkRate = (uint32_t)(workRate / ((float)postdiv)); + workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult(); + clkRate = (uint32_t)(workRate / ((uint64_t)postdiv)); } break; case 0x02: /* PLL1 clock (pll1_clk)*/ switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) { case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLOCK_GetFro12MFreq(); + clkRate = GetFro12MFreq(); break; case 0x01: /* CLKIN (clk_in) */ - clkRate = CLOCK_GetExtClkFreq(); + clkRate = GetExtClkFreq(); break; case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = CLOCK_GetFro1MFreq(); + clkRate = GetFro1MFreq(); break; case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLOCK_GetOsc32KFreq(); + clkRate = GetOsc32KFreq(); break; default: + clkRate = 0UL; break; } - if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0)) + if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) { /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ prediv = findPll1PreDiv(); @@ -342,16 +357,17 @@ void SystemCoreClockUpdate (void) { /* MDEC used for rate */ workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); - clkRate = workRate1 / ((uint64_t)postdiv); + clkRate = (uint32_t)(workRate1 / ((uint64_t)postdiv)); } break; case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLOCK_GetOsc32KFreq(); + clkRate = GetOsc32KFreq(); break; default: + clkRate = 0UL; break; } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); } /* ---------------------------------------------------------------------------- diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.h index 705e6508a4..21f7692759 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core0.h @@ -1,16 +1,17 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181219 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b220117 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -29,14 +30,16 @@ ** Revisions: ** - rev. 1.0 (2018-08-22) ** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM ** ** ################################################################### */ /*! * @file LPC55S69_cm33_core0 - * @version 1.0 - * @date 2018-08-22 + * @version 1.1 + * @date 2019-05-16 * @brief Device specific configuration file for LPC55S69_cm33_core0 (header * file) * diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.c index 0b684c5177..ee18841534 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.c +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.c @@ -1,16 +1,17 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181219 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b220117 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -29,14 +30,16 @@ ** Revisions: ** - rev. 1.0 (2018-08-22) ** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM ** ** ################################################################### */ /*! * @file LPC55S69_cm33_core1 - * @version 1.0 - * @date 2018-08-22 + * @version 1.1 + * @date 2019-05-16 * @brief Device specific configuration file for LPC55S69_cm33_core1 * (implementation file) * @@ -57,15 +60,15 @@ /* Get predivider (N) from PLL0 NDEC setting */ static uint32_t findPll0PreDiv(void) { - uint32_t preDiv = 1; + uint32_t preDiv = 1UL; /* Direct input is not used? */ - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0) + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0UL) { preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK; - if (preDiv == 0) + if (preDiv == 0UL) { - preDiv = 1; + preDiv = 1UL; } } return preDiv; @@ -76,19 +79,19 @@ static uint32_t findPll0PostDiv(void) { uint32_t postDiv = 1; - if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0) + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0UL) { - if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) + if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK) != 0UL) { postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK; } else { - postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); + postDiv = 2UL * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK); } - if (postDiv == 0) + if (postDiv == 0UL) { - postDiv = 2; + postDiv = 2UL; } } return postDiv; @@ -97,23 +100,25 @@ static uint32_t findPll0PostDiv(void) /* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */ static float findPll0MMult(void) { - float mMult = 1; + float mMult = 1.0F; float mMult_fract; uint32_t mMult_int; - if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) + if ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK) != 0UL) { - mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT; + mMult = (float)(uint32_t)((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT); } else { - mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); - mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M)/(1 << PLL_SSCG_MD_INT_P)); - mMult = (float)mMult_int + mMult_fract; + mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U); + mMult_int = mMult_int | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P); + mMult_fract = ((float)(uint32_t)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M) / + (float)(uint32_t)(1UL << PLL_SSCG_MD_INT_P)); + mMult = (float)mMult_int + mMult_fract; } - if (mMult == 0) + if (0ULL == ((uint64_t)mMult)) { - mMult = 1; + mMult = 1.0F; } return mMult; } @@ -121,15 +126,15 @@ static float findPll0MMult(void) /* Get predivider (N) from PLL1 NDEC setting */ static uint32_t findPll1PreDiv(void) { - uint32_t preDiv = 1; + uint32_t preDiv = 1UL; /* Direct input is not used? */ - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0) + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0UL) { preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK; - if (preDiv == 0) + if (preDiv == 0UL) { - preDiv = 1; + preDiv = 1UL; } } return preDiv; @@ -138,21 +143,21 @@ static uint32_t findPll1PreDiv(void) /* Get postdivider (P) from PLL1 PDEC setting */ static uint32_t findPll1PostDiv(void) { - uint32_t postDiv = 1; + uint32_t postDiv = 1UL; - if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0) + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0UL) { - if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) + if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK) != 0UL) { postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK; } else { - postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); + postDiv = 2UL * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK); } - if (postDiv == 0) + if (postDiv == 0UL) { - postDiv = 2; + postDiv = 2UL; } } return postDiv; @@ -161,13 +166,13 @@ static uint32_t findPll1PostDiv(void) /* Get multiplier (M) from PLL1 MDEC settings */ static uint32_t findPll1MMult(void) { - uint32_t mMult = 1; + uint32_t mMult = 1UL; mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK; - if (mMult == 0) + if (mMult == 0UL) { - mMult = 1; + mMult = 1UL; } return mMult; } @@ -176,51 +181,47 @@ static uint32_t findPll1MMult(void) /*! brief Return Frequency of FRO 12MHz * return Frequency of FRO 12MHz */ -static uint32_t CLOCK_GetFro12MFreq(void) +static uint32_t GetFro12MFreq(void) { - return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? - 0 : - (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U; + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) != 0UL) ? 12000000U : 0U; } /* Get FRO 1M Clk */ /*! brief Return Frequency of FRO 1MHz * return Frequency of FRO 1MHz */ -static uint32_t CLOCK_GetFro1MFreq(void) +static uint32_t GetFro1MFreq(void) { - return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U; + return ((SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) != 0UL) ? 1000000U : 0U; } /* Get EXT OSC Clk */ /*! brief Return Frequency of External Clock * return Frequency of External Clock. If no external clock is used returns 0. */ -static uint32_t CLOCK_GetExtClkFreq(void) +static uint32_t GetExtClkFreq(void) { - return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U; + return ((ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) != 0UL) ? CLK_CLK_IN : 0U; } /* Get HF FRO Clk */ /*! brief Return Frequency of High-Freq output of FRO * return Frequency of High-Freq output of FRO */ -static uint32_t CLOCK_GetFroHfFreq(void) +static uint32_t GetFroHfFreq(void) { - return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ? - 0 : - (ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U; + return ((ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) != 0UL) ? 96000000U : 0U; } /* Get RTC OSC Clk */ /*! brief Return Frequency of 32kHz osc * return Frequency of 32kHz osc */ -static uint32_t CLOCK_GetOsc32KFreq(void) +static uint32_t GetOsc32KFreq(void) { - return ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (!(PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? + return ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (0UL == (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK))) ? CLK_RTC_32K_CLK : - ((!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK)) ? + ((0UL == (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && ((PMC->RTCOSC32K & PMC_RTCOSC32K_SEL_MASK) != 0UL)) ? CLK_RTC_32K_CLK : 0U; } @@ -237,9 +238,12 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; -- SystemInit() ---------------------------------------------------------------------------- */ -void SystemInit (void) { +__attribute__ ((weak)) void SystemInit (void) { - SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access (enable PowerQuad) */ + SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */ +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access in Normal mode (enable PowerQuad) */ +#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */ @@ -266,7 +270,7 @@ void SystemInit (void) { void SystemCoreClockUpdate (void) { uint32_t clkRate = 0; uint32_t prediv, postdiv; - float workRate; + uint64_t workRate; uint64_t workRate1; switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK) @@ -275,16 +279,16 @@ void SystemCoreClockUpdate (void) { switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK) { case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLOCK_GetFro12MFreq(); + clkRate = GetFro12MFreq(); break; case 0x01: /* CLKIN (clk_in) */ - clkRate = CLOCK_GetExtClkFreq(); + clkRate = GetExtClkFreq(); break; case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = CLOCK_GetFro1MFreq(); + clkRate = GetFro1MFreq(); break; default: /* = 0x03 = FRO 96 MHz (fro_hf) */ - clkRate = CLOCK_GetFroHfFreq(); + clkRate = GetFroHfFreq(); break; } break; @@ -292,50 +296,52 @@ void SystemCoreClockUpdate (void) { switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK) { case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLOCK_GetFro12MFreq(); + clkRate = GetFro12MFreq(); break; case 0x01: /* CLKIN (clk_in) */ - clkRate = CLOCK_GetExtClkFreq(); + clkRate = GetExtClkFreq(); break; case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = CLOCK_GetFro1MFreq(); + clkRate = GetFro1MFreq(); break; case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLOCK_GetOsc32KFreq(); + clkRate = GetOsc32KFreq(); break; default: + clkRate = 0UL; break; } - if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0)) + if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0UL)) { prediv = findPll0PreDiv(); postdiv = findPll0PostDiv(); /* Adjust input clock */ clkRate = clkRate / prediv; /* MDEC used for rate */ - workRate = (float)clkRate * (float)findPll0MMult(); - clkRate = (uint32_t)(workRate / ((float)postdiv)); + workRate = (uint64_t)clkRate * (uint64_t)findPll0MMult(); + clkRate = (uint32_t)(workRate / ((uint64_t)postdiv)); } break; case 0x02: /* PLL1 clock (pll1_clk)*/ switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK) { case 0x00: /* FRO 12 MHz (fro_12m) */ - clkRate = CLOCK_GetFro12MFreq(); + clkRate = GetFro12MFreq(); break; case 0x01: /* CLKIN (clk_in) */ - clkRate = CLOCK_GetExtClkFreq(); + clkRate = GetExtClkFreq(); break; case 0x02: /* Fro 1MHz (fro_1m) */ - clkRate = CLOCK_GetFro1MFreq(); + clkRate = GetFro1MFreq(); break; case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLOCK_GetOsc32KFreq(); + clkRate = GetOsc32KFreq(); break; default: + clkRate = 0UL; break; } - if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0)) + if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0UL) && ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) != 0UL) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0UL)) { /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */ prediv = findPll1PreDiv(); @@ -345,16 +351,17 @@ void SystemCoreClockUpdate (void) { /* MDEC used for rate */ workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult(); - clkRate = workRate1 / ((uint64_t)postdiv); + clkRate = (uint32_t)(workRate1 / ((uint64_t)postdiv)); } break; case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */ - clkRate = CLOCK_GetOsc32KFreq(); + clkRate = GetOsc32KFreq(); break; default: + clkRate = 0UL; break; } - SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1); + SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL); } /* ---------------------------------------------------------------------------- diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.h index 8da7ec5bdd..b86cf98b2e 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/system_LPC55S69_cm33_core1.h @@ -1,16 +1,17 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core1 -** LPC55S69JET98_cm33_core1 +** LPC55S69JBD64_cm33_core1 +** LPC55S69JEV98_cm33_core1 ** ** Compilers: GNU C Compiler ** IAR ANSI C/C++ Compiler for ARM ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181219 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b220117 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -18,7 +19,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2022 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -29,14 +30,16 @@ ** Revisions: ** - rev. 1.0 (2018-08-22) ** Initial version based on v0.2UM +** - rev. 1.1 (2019-05-16) +** Initial A1 version based on v1.3UM ** ** ################################################################### */ /*! * @file LPC55S69_cm33_core1 - * @version 1.0 - * @date 2018-08-22 + * @version 1.1 + * @date 2019-05-16 * @brief Device specific configuration file for LPC55S69_cm33_core1 (header * file) * diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/template/RTE_Device.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/template/RTE_Device.h new file mode 100644 index 0000000000..8b682345f9 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/template/RTE_Device.h @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _RTE_DEVICE_H +#define _RTE_DEVICE_H + +#include "pin_mux.h" + +/* UART Select, UART0-UART7. */ +/* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART + * instance. */ +#define RTE_USART0 0 +#define RTE_USART0_DMA_EN 0 +#define RTE_USART1 0 +#define RTE_USART1_DMA_EN 0 +#define RTE_USART2 0 +#define RTE_USART2_DMA_EN 0 +#define RTE_USART3 0 +#define RTE_USART3_DMA_EN 0 +#define RTE_USART4 0 +#define RTE_USART4_DMA_EN 0 +#define RTE_USART5 0 +#define RTE_USART5_DMA_EN 0 +#define RTE_USART6 0 +#define RTE_USART6_DMA_EN 0 +#define RTE_USART7 0 +#define RTE_USART7_DMA_EN 0 + +/* USART configuration. */ +#define USART_RX_BUFFER_LEN 64 +#define USART0_RX_BUFFER_ENABLE 0 +#define USART1_RX_BUFFER_ENABLE 0 +#define USART2_RX_BUFFER_ENABLE 0 +#define USART3_RX_BUFFER_ENABLE 0 +#define USART4_RX_BUFFER_ENABLE 0 +#define USART5_RX_BUFFER_ENABLE 0 +#define USART6_RX_BUFFER_ENABLE 0 +#define USART7_RX_BUFFER_ENABLE 0 + +#define RTE_USART0_PIN_INIT USART0_InitPins +#define RTE_USART0_PIN_DEINIT USART0_DeinitPins +#define RTE_USART0_DMA_TX_CH 5 +#define RTE_USART0_DMA_TX_DMA_BASE DMA0 +#define RTE_USART0_DMA_RX_CH 4 +#define RTE_USART0_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART1_PIN_INIT USART1_InitPins +#define RTE_USART1_PIN_DEINIT USART1_DeinitPins +#define RTE_USART1_DMA_TX_CH 7 +#define RTE_USART1_DMA_TX_DMA_BASE DMA0 +#define RTE_USART1_DMA_RX_CH 6 +#define RTE_USART1_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART2_PIN_INIT USART2_InitPins +#define RTE_USART2_PIN_DEINIT USART2_DeinitPins +#define RTE_USART2_DMA_TX_CH 8 +#define RTE_USART2_DMA_TX_DMA_BASE DMA0 +#define RTE_USART2_DMA_RX_CH 9 +#define RTE_USART2_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART3_PIN_INIT USART3_InitPins +#define RTE_USART3_PIN_DEINIT USART3_DeinitPins +#define RTE_USART3_DMA_TX_CH 10 +#define RTE_USART3_DMA_TX_DMA_BASE DMA0 +#define RTE_USART3_DMA_RX_CH 11 +#define RTE_USART3_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART4_PIN_INIT USART4_InitPins +#define RTE_USART4_PIN_DEINIT USART4_DeinitPins +#define RTE_USART4_DMA_TX_CH 13 +#define RTE_USART4_DMA_TX_DMA_BASE DMA0 +#define RTE_USART4_DMA_RX_CH 12 +#define RTE_USART4_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART5_PIN_INIT USART5_InitPins +#define RTE_USART5_PIN_DEINIT USART5_DeinitPins +#define RTE_USART5_DMA_TX_CH 15 +#define RTE_USART5_DMA_TX_DMA_BASE DMA0 +#define RTE_USART5_DMA_RX_CH 14 +#define RTE_USART5_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART6_PIN_INIT USART6_InitPins +#define RTE_USART6_PIN_DEINIT USART6_DeinitPins +#define RTE_USART6_DMA_TX_CH 17 +#define RTE_USART6_DMA_TX_DMA_BASE DMA0 +#define RTE_USART6_DMA_RX_CH 16 +#define RTE_USART6_DMA_RX_DMA_BASE DMA0 + +#define RTE_USART7_PIN_INIT USART7_InitPins +#define RTE_USART7_PIN_DEINIT USART7_DeinitPins +#define RTE_USART7_DMA_TX_CH 19 +#define RTE_USART7_DMA_TX_DMA_BASE DMA0 +#define RTE_USART7_DMA_RX_CH 18 +#define RTE_USART7_DMA_RX_DMA_BASE DMA0 + +/* I2C Select, I2C0 -I2C7*/ +/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. + */ +#define RTE_I2C0 0 +#define RTE_I2C0_DMA_EN 0 +#define RTE_I2C1 0 +#define RTE_I2C1_DMA_EN 0 +#define RTE_I2C2 0 +#define RTE_I2C2_DMA_EN 0 +#define RTE_I2C3 0 +#define RTE_I2C3_DMA_EN 0 +#define RTE_I2C4 0 +#define RTE_I2C4_DMA_EN 0 +#define RTE_I2C5 0 +#define RTE_I2C5_DMA_EN 0 +#define RTE_I2C6 0 +#define RTE_I2C6_DMA_EN 0 +#define RTE_I2C7 0 +#define RTE_I2C7_DMA_EN 0 + +/*I2C configuration*/ +#define RTE_I2C0_Master_DMA_BASE DMA0 +#define RTE_I2C0_Master_DMA_CH 1 + +#define RTE_I2C1_Master_DMA_BASE DMA0 +#define RTE_I2C1_Master_DMA_CH 3 + +#define RTE_I2C2_Master_DMA_BASE DMA0 +#define RTE_I2C2_Master_DMA_CH 5 + +#define RTE_I2C3_Master_DMA_BASE DMA0 +#define RTE_I2C3_Master_DMA_CH 7 + +#define RTE_I2C4_Master_DMA_BASE DMA0 +#define RTE_I2C4_Master_DMA_CH 9 + +#define RTE_I2C5_Master_DMA_BASE DMA0 +#define RTE_I2C5_Master_DMA_CH 11 + +#define RTE_I2C6_Master_DMA_BASE DMA0 +#define RTE_I2C6_Master_DMA_CH 13 + +#define RTE_I2C7_Master_DMA_BASE DMA0 +#define RTE_I2C7_Master_DMA_CH 15 + +/* SPI select, SPI0 - SPI7.*/ +/* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. + */ +#define RTE_SPI0 0 +#define RTE_SPI0_DMA_EN 0 +#define RTE_SPI1 0 +#define RTE_SPI1_DMA_EN 0 +#define RTE_SPI2 0 +#define RTE_SPI2_DMA_EN 0 +#define RTE_SPI3 0 +#define RTE_SPI3_DMA_EN 0 +#define RTE_SPI4 0 +#define RTE_SPI4_DMA_EN 0 +#define RTE_SPI5 0 +#define RTE_SPI5_DMA_EN 0 +#define RTE_SPI6 0 +#define RTE_SPI6_DMA_EN 0 +#define RTE_SPI7 0 +#define RTE_SPI7_DMA_EN 0 + +/* SPI configuration. */ +#define RTE_SPI0_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI0_PIN_INIT SPI0_InitPins +#define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins +#define RTE_SPI0_DMA_TX_CH 1 +#define RTE_SPI0_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI0_DMA_RX_CH 0 +#define RTE_SPI0_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI1_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI1_PIN_INIT SPI1_InitPins +#define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins +#define RTE_SPI1_DMA_TX_CH 3 +#define RTE_SPI1_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI1_DMA_RX_CH 2 +#define RTE_SPI1_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI2_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI2_PIN_INIT SPI2_InitPins +#define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins +#define RTE_SPI2_DMA_TX_CH 5 +#define RTE_SPI2_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI2_DMA_RX_CH 4 +#define RTE_SPI2_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI3_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI3_PIN_INIT SPI3_InitPins +#define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins +#define RTE_SPI3_DMA_TX_CH 7 +#define RTE_SPI3_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI3_DMA_RX_CH 6 +#define RTE_SPI3_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI4_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI4_PIN_INIT SPI4_InitPins +#define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins +#define RTE_SPI4_DMA_TX_CH 9 +#define RTE_SPI4_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI4_DMA_RX_CH 8 +#define RTE_SPI4_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI5_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI5_PIN_INIT SPI5_InitPins +#define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins +#define RTE_SPI5_DMA_TX_CH 11 +#define RTE_SPI5_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI5_DMA_RX_CH 10 +#define RTE_SPI5_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI6_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI6_PIN_INIT SPI6_InitPins +#define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins +#define RTE_SPI6_DMA_TX_CH 13 +#define RTE_SPI6_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI6_DMA_RX_CH 12 +#define RTE_SPI6_DMA_RX_DMA_BASE DMA0 + +#define RTE_SPI7_SSEL_NUM kSPI_Ssel0 +#define RTE_SPI7_PIN_INIT SPI7_InitPins +#define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins +#define RTE_SPI7_DMA_TX_CH 15 +#define RTE_SPI7_DMA_TX_DMA_BASE DMA0 +#define RTE_SPI7_DMA_RX_CH 14 +#define RTE_SPI7_DMA_RX_DMA_BASE DMA0 + +#endif /* _RTE_DEVICE_H */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console/fsl_debug_console.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console/fsl_debug_console.c new file mode 100644 index 0000000000..1efdbbbbdf --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console/fsl_debug_console.c @@ -0,0 +1,1417 @@ +/* + * This is a modified version of the file printf.c, which was distributed + * by Motorola as part of the M5407C3BOOT.zip package used to initialize + * the M5407C3 evaluation board. + * + * Copyright: + * 1999-2000 MOTOROLA, INC. All Rights Reserved. + * You are hereby granted a copyright license to use, modify, and + * distribute the SOFTWARE so long as this entire notice is + * retained without alteration in any modified and/or redistributed + * versions, and that such modified versions are clearly identified + * as such. No licenses are granted by implication, estoppel or + * otherwise under any patents or trademarks of Motorola, Inc. This + * software is provided on an "AS IS" basis and without warranty. + * + * To the maximum extent permitted by applicable law, MOTOROLA + * DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING + * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR + * PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE + * SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY + * ACCOMPANYING WRITTEN MATERIALS. + * + * To the maximum extent permitted by applicable law, IN NO EVENT + * SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING + * WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS + * INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY + * LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE. + * + * Motorola assumes no responsibility for the maintenance and support + * of this software + + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#include +#endif + +#ifdef SDK_OS_FREE_RTOS +#include "FreeRTOS.h" +#include "semphr.h" +#include "task.h" +#endif + +#include "fsl_debug_console_conf.h" +#include "fsl_str.h" + +#include "fsl_common.h" +#include "fsl_component_serial_manager.h" + +#include "fsl_debug_console.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#ifndef NDEBUG +#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U)) +#undef assert +#define assert(n) +#else +/* MISRA C-2012 Rule 17.2 */ +#undef assert +#define assert(n) \ + while (!(n)) \ + { \ + ; \ + } +#endif +#endif + +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) +#define DEBUG_CONSOLE_FUNCTION_PREFIX +#else +#define DEBUG_CONSOLE_FUNCTION_PREFIX static +#endif + +/*! @brief character backspace ASCII value */ +#define DEBUG_CONSOLE_BACKSPACE 127U + +/* lock definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +static SemaphoreHandle_t s_debugConsoleReadSemaphore; +#if configSUPPORT_STATIC_ALLOCATION +static StaticSemaphore_t s_debugConsoleReadSemaphoreStatic; +#endif +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static SemaphoreHandle_t s_debugConsoleReadWaitSemaphore; +#if configSUPPORT_STATIC_ALLOCATION +static StaticSemaphore_t s_debugConsoleReadWaitSemaphoreStatic; +#endif +#endif + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +static volatile bool s_debugConsoleReadWaitSemaphore; +#endif + +#else + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +/*! @brief get current runing environment is ISR or not */ +#ifdef __CA7_REV +#define IS_RUNNING_IN_ISR() SystemGetIRQNestingLevel() +#else +#define IS_RUNNING_IN_ISR() __get_IPSR() +#endif /* __CA7_REV */ + +/* semaphore definition */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + +/* mutex semaphore */ +/* clang-format off */ +#if configSUPPORT_STATIC_ALLOCATION +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex, stack) ((mutex) = xSemaphoreCreateMutexStatic(stack)) +#else +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) ((mutex) = xSemaphoreCreateMutex()) +#endif +#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) \ + do \ + { \ + if(NULL != (mutex)) \ + { \ + vSemaphoreDelete(mutex); \ + (mutex) = NULL; \ + } \ + } while(false) + +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreGive(mutex); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + (void)xSemaphoreTake(mutex, portMAX_DELAY); \ + } \ +} + +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) \ +{ \ + if (IS_RUNNING_IN_ISR() == 0U) \ + { \ + result = xSemaphoreTake(mutex, 0U); \ + } \ + else \ + { \ + result = 1U; \ + } \ +} + +/* Binary semaphore */ +#if configSUPPORT_STATIC_ALLOCATION +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary,stack) ((binary) = xSemaphoreCreateBinaryStatic(stack)) +#else +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) ((binary) = xSemaphoreCreateBinary()) +#endif +#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) \ + do \ + { \ + if(NULL != (binary)) \ + { \ + vSemaphoreDelete((binary)); \ + (binary) = NULL; \ + } \ + } while(false) +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) ((void)xSemaphoreTake((binary), portMAX_DELAY)) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) ((void)xSemaphoreGiveFromISR((binary), NULL)) + +#elif (DEBUG_CONSOLE_SYNCHRONIZATION_BM == DEBUG_CONSOLE_SYNCHRONIZATION_MODE) + +#define DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(mutex) (void)(mutex) +#define DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(mutex) (void)(mutex) +#define DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_NONBLOCKING(mutex, result) (result = 1U) + +#define DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(binary) (void)(binary) +#define DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(binary) (void)(binary) +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) \ + { \ + while (!(binary)) \ + { \ + } \ + (binary) = false; \ + } +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) \ + do \ + { \ + (binary) = true; \ + } while(false) +#else +#define DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(binary) (void)(binary) +#define DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(binary) (void)(binary) +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +/* clang-format on */ + +/* add other implementation here + *such as : + * #elif(DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DDEBUG_CONSOLE_SYNCHRONIZATION_xxx) + */ + +#else + +#error RTOS type is not defined by DEBUG_CONSOLE_SYNCHRONIZATION_MODE. + +#endif /* DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS */ + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/* receive state structure */ +typedef struct _debug_console_write_ring_buffer +{ + uint32_t ringBufferSize; + volatile uint32_t ringHead; + volatile uint32_t ringTail; + uint8_t ringBuffer[DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN]; +} debug_console_write_ring_buffer_t; +#endif + +typedef struct _debug_console_state_struct +{ + serial_handle_t serialHandle; /*!< serial manager handle */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING + SERIAL_MANAGER_HANDLE_DEFINE(serialHandleBuffer); + debug_console_write_ring_buffer_t writeRingBuffer; + uint8_t readRingBuffer[DEBUG_CONSOLE_RECEIVE_BUFFER_LEN]; + SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialWriteHandleBuffer); + SERIAL_MANAGER_WRITE_HANDLE_DEFINE(serialWriteHandleBuffer2); + SERIAL_MANAGER_READ_HANDLE_DEFINE(serialReadHandleBuffer); +#else + SERIAL_MANAGER_BLOCK_HANDLE_DEFINE(serialHandleBuffer); + SERIAL_MANAGER_WRITE_BLOCK_HANDLE_DEFINE(serialWriteHandleBuffer); + SERIAL_MANAGER_READ_BLOCK_HANDLE_DEFINE(serialReadHandleBuffer); +#endif +} debug_console_state_struct_t; + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/*! @brief Debug console state information. */ +#if (defined(DATA_SECTION_IS_CACHEABLE) && (DATA_SECTION_IS_CACHEABLE > 0)) +AT_NONCACHEABLE_SECTION(static debug_console_state_struct_t s_debugConsoleState); +#else +static debug_console_state_struct_t s_debugConsoleState; +#endif +serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief This is a printf call back function which is used to relocate the log to buffer + * or print the log immediately when the local buffer is full. + * + * @param[in] buf Buffer to store log. + * @param[in] indicator Buffer index. + * @param[in] val Target character to store. + * @param[in] len length of the character + * + */ +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len); +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch); +int DbgConsole_SendData(uint8_t *ch, size_t size); +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size); +int DbgConsole_ReadLine(uint8_t *buf, size_t size); +int DbgConsole_ReadCharacter(uint8_t *ch); + +#if ((SDK_DEBUGCONSOLE != DEBUGCONSOLE_REDIRECT_TO_SDK) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void); +#endif +/******************************************************************************* + * Code + ******************************************************************************/ + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +static status_t DbgConsole_SerialManagerPerformTransfer(debug_console_state_struct_t *ioState) +{ + serial_manager_status_t ret = kStatus_SerialManager_Error; + uint32_t sendDataLength; + uint32_t startIndex; + uint32_t regPrimask; + + regPrimask = DisableGlobalIRQ(); + if (ioState->writeRingBuffer.ringTail != ioState->writeRingBuffer.ringHead) + { + if (ioState->writeRingBuffer.ringHead > ioState->writeRingBuffer.ringTail) + { + sendDataLength = ioState->writeRingBuffer.ringHead - ioState->writeRingBuffer.ringTail; + startIndex = ioState->writeRingBuffer.ringTail; + } + else + { + sendDataLength = ioState->writeRingBuffer.ringBufferSize - ioState->writeRingBuffer.ringTail; + startIndex = ioState->writeRingBuffer.ringTail; + if (0U != ioState->writeRingBuffer.ringHead) + { + ret = SerialManager_WriteNonBlocking(((serial_write_handle_t)&ioState->serialWriteHandleBuffer2[0]), + &ioState->writeRingBuffer.ringBuffer[startIndex], sendDataLength); + sendDataLength = ioState->writeRingBuffer.ringHead - 0U; + startIndex = 0U; + } + } + ret = SerialManager_WriteNonBlocking(((serial_write_handle_t)&ioState->serialWriteHandleBuffer[0]), + &ioState->writeRingBuffer.ringBuffer[startIndex], sendDataLength); + } + EnableGlobalIRQ(regPrimask); + return (status_t)ret; +} + +static void DbgConsole_SerialManagerTxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + debug_console_state_struct_t *ioState; + + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + ioState = (debug_console_state_struct_t *)callbackParam; + + ioState->writeRingBuffer.ringTail += message->length; + if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize) + { + ioState->writeRingBuffer.ringTail = 0U; + } + + if (kStatus_SerialManager_Success == status) + { + (void)DbgConsole_SerialManagerPerformTransfer(ioState); + } + else if (kStatus_SerialManager_Canceled == status) + { + ioState->writeRingBuffer.ringTail = 0U; + ioState->writeRingBuffer.ringHead = 0U; + } + else + { + /*MISRA rule 16.4*/ + } +} + +static void DbgConsole_SerialManagerTx2Callback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + debug_console_state_struct_t *ioState; + + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + ioState = (debug_console_state_struct_t *)callbackParam; + + ioState->writeRingBuffer.ringTail += message->length; + if (ioState->writeRingBuffer.ringTail >= ioState->writeRingBuffer.ringBufferSize) + { + ioState->writeRingBuffer.ringTail = 0U; + } + + if (kStatus_SerialManager_Success == status) + { + /* Empty block*/ + } + else if (kStatus_SerialManager_Canceled == status) + { + /* Empty block*/ + } + else + { + /*MISRA rule 16.4*/ + } +} + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +static void DbgConsole_SerialManagerRxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + if ((NULL == callbackParam) || (NULL == message)) + { + return; + } + + if (kStatus_SerialManager_Notify == status) + { + } + else if (kStatus_SerialManager_Success == status) + { + /* release s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_GIVE_BINARY_SEMAPHORE_FROM_ISR(s_debugConsoleReadWaitSemaphore); + } + else + { + /*MISRA rule 16.4*/ + } +} +#endif + +#endif + +status_t DbgConsole_ReadOneCharacter(uint8_t *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + return (status_t)kStatus_Fail; +#else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \ + DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/ + serial_manager_status_t status = kStatus_SerialManager_Error; + +/* recieve one char every time */ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + status = + SerialManager_ReadNonBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#else /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/ + status = SerialManager_ReadBlocking(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), ch, 1); +#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING)*/ + if (kStatus_SerialManager_Success != status) + { + status = (serial_manager_status_t)kStatus_Fail; + } + else + { + /* wait s_debugConsoleReadWaitSemaphore from RX callback */ + DEBUG_CONSOLE_TAKE_BINARY_SEMAPHORE_BLOCKING(s_debugConsoleReadWaitSemaphore); + status = (serial_manager_status_t)kStatus_Success; + } + return (status_t)status; +#endif /*defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == \ + DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED)*/ + +#else /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/ + + return (status_t)kStatus_Fail; + +#endif /*(defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U))*/ +} + +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION +static status_t DbgConsole_EchoCharacter(uint8_t *ch, bool isGetChar, int *index) +{ + /* Due to scanf take \n and \r as end of string,should not echo */ + if (((*ch != (uint8_t)'\r') && (*ch != (uint8_t)'\n')) || (isGetChar)) + { + /* recieve one char every time */ + if (1 != DbgConsole_SendDataReliable(ch, 1U)) + { + return (status_t)kStatus_Fail; + } + } + + if ((!isGetChar) && (index != NULL)) + { + if (DEBUG_CONSOLE_BACKSPACE == *ch) + { + if ((*index >= 2)) + { + *index -= 2; + } + else + { + *index = 0; + } + } + } + + return (status_t)kStatus_Success; +} +#endif + +int DbgConsole_SendData(uint8_t *ch, size_t size) +{ + status_t status; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t sendDataLength; + int txBusy = 0; +#endif + assert(NULL != ch); + assert(0U != size); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + txBusy = 1; + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U; + if (sendDataLength < size) + { + EnableGlobalIRQ(regPrimask); + return -1; + } + for (int i = 0; i < (int)size; i++) + { + s_debugConsoleState.writeRingBuffer.ringBuffer[s_debugConsoleState.writeRingBuffer.ringHead++] = ch[i]; + if (s_debugConsoleState.writeRingBuffer.ringHead >= s_debugConsoleState.writeRingBuffer.ringBufferSize) + { + s_debugConsoleState.writeRingBuffer.ringHead = 0U; + } + } + + status = (status_t)kStatus_SerialManager_Success; + + if (txBusy == 0) + { + status = DbgConsole_SerialManagerPerformTransfer(&s_debugConsoleState); + } + EnableGlobalIRQ(regPrimask); +#else + status = (status_t)SerialManager_WriteBlocking( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); +#endif + return (((status_t)kStatus_Success == status) ? (int)size : -1); +} + +int DbgConsole_SendDataReliable(uint8_t *ch, size_t size) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + serial_manager_status_t status = kStatus_SerialManager_Error; + uint32_t sendDataLength; + uint32_t totalLength = size; + int sentLength; +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ +#else /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + serial_manager_status_t status; +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + + assert(NULL != ch); + + if (0U == size) + { + return 0; + } + + if (NULL == g_serialHandle) + { + return 0; + } + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)) + do + { + uint32_t regPrimask = DisableGlobalIRQ(); + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + sendDataLength = + (s_debugConsoleState.writeRingBuffer.ringHead + s_debugConsoleState.writeRingBuffer.ringBufferSize - + s_debugConsoleState.writeRingBuffer.ringTail) % + s_debugConsoleState.writeRingBuffer.ringBufferSize; + } + else + { + sendDataLength = 0U; + } + sendDataLength = s_debugConsoleState.writeRingBuffer.ringBufferSize - sendDataLength - 1U; + + if ((sendDataLength > 0U) && ((sendDataLength >= totalLength) || + (totalLength >= (s_debugConsoleState.writeRingBuffer.ringBufferSize - 1U)))) + { + if (sendDataLength > totalLength) + { + sendDataLength = totalLength; + } + + sentLength = DbgConsole_SendData(&ch[size - totalLength], (size_t)sendDataLength); + if (sentLength > 0) + { + totalLength = totalLength - (uint32_t)sentLength; + } + } + EnableGlobalIRQ(regPrimask); + + if (totalLength != 0U) + { + status = (serial_manager_status_t)DbgConsole_Flush(); + if (kStatus_SerialManager_Success != status) + { + break; + } + } + } while (totalLength != 0U); + return ((int)size - (int)totalLength); +#else /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + return DbgConsole_SendData(ch, size); +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + +#else /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + status = + SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), ch, size); + return ((kStatus_SerialManager_Success == status) ? (int)size : -1); +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +} + +int DbgConsole_ReadLine(uint8_t *buf, size_t size) +{ + int i = 0; + + assert(buf != NULL); + + if (NULL == g_serialHandle) + { + return -1; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + + do + { + /* recieve one char every time */ + if ((status_t)kStatus_Success != DbgConsole_ReadOneCharacter(&buf[i])) + { + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + i = -1; + break; + } +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(&buf[i], false, &i); +#endif + /* analysis data */ + if (((uint8_t)'\r' == buf[i]) || ((uint8_t)'\n' == buf[i])) + { + /* End of Line. */ + if (0 == i) + { + buf[i] = (uint8_t)'\0'; + continue; + } + else + { + break; + } + } + i++; + } while (i < (int)size); + + /* get char should not add '\0'*/ + if (i == (int)size) + { + buf[i] = (uint8_t)'\0'; + } + else + { + buf[i + 1] = (uint8_t)'\0'; + } + + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return i; +} + +int DbgConsole_ReadCharacter(uint8_t *ch) +{ + int ret; + + assert(ch); + + if (NULL == g_serialHandle) + { + return -1; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + /* read one character */ + if ((status_t)kStatus_Success == DbgConsole_ReadOneCharacter(ch)) + { + ret = 1; +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter(ch, true, NULL); +#endif + } + else + { + ret = -1; + } + + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return ret; +} + +#if SDK_DEBUGCONSOLE +static void DbgConsole_PrintCallback(char *buf, int32_t *indicator, char dbgVal, int len) +{ + int i = 0; + + for (i = 0; i < len; i++) + { + if (((uint32_t)*indicator + 1UL) >= (uint32_t)DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN) + { + (void)DbgConsole_SendDataReliable((uint8_t *)buf, (size_t)(*indicator)); + *indicator = 0; + } + + buf[*indicator] = dbgVal; + (*indicator)++; + } +} +#endif + +/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U)) +#include "board.h" +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +static const serial_port_uart_config_t uartConfig = {.instance = BOARD_DEBUG_UART_INSTANCE, + .clockRate = BOARD_DEBUG_UART_CLK_FREQ, + .baudRate = BOARD_DEBUG_UART_BAUDRATE, + .parityMode = kSerialManager_UartParityDisabled, + .stopBitCount = kSerialManager_UartOneStopBit, + .enableRx = 1U, + .enableTx = 1U, + .enableRxRTS = 0U, + .enableTxCTS = 0U, +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + .txFifoWatermark = 0U, + .rxFifoWatermark = 0U +#endif +}; +#endif +#endif +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq) +{ + serial_manager_config_t serialConfig = {0}; + serial_manager_status_t status = kStatus_SerialManager_Success; + +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE == 0U)) +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) + serial_port_uart_config_t uartConfig = { + .instance = instance, + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .parityMode = kSerialManager_UartParityDisabled, + .stopBitCount = kSerialManager_UartOneStopBit, + .enableRx = 1, + .enableTx = 1, + .enableRxRTS = 0U, + .enableTxCTS = 0U, +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + .txFifoWatermark = 0U, + .rxFifoWatermark = 0U +#endif + }; +#endif +#endif + +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serial_port_usb_cdc_config_t usbCdcConfig = { + .controllerIndex = (serial_port_usb_cdc_controller_index_t)instance, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serial_port_swo_config_t swoConfig = { + .clockRate = clkSrcFreq, + .baudRate = baudRate, + .port = instance, + .protocol = kSerialManager_SwoProtocolNrz, + }; +#endif + +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + serial_port_virtual_config_t serialPortVirtualConfig = { + .controllerIndex = (serial_port_virtual_controller_index_t)instance, + }; +#endif + + serialConfig.type = device; +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + serialConfig.ringBuffer = &s_debugConsoleState.readRingBuffer[0]; + serialConfig.ringBufferSize = DEBUG_CONSOLE_RECEIVE_BUFFER_LEN; + serialConfig.blockType = kSerialManager_NonBlocking; +#else + serialConfig.blockType = kSerialManager_Blocking; +#endif + + if (kSerialPort_Uart == device) + { +#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U)) +#if (defined(SERIAL_USE_CONFIGURE_STRUCTURE) && (SERIAL_USE_CONFIGURE_STRUCTURE > 0U)) + serialConfig.portConfig = (void *)&uartConfig; +#else + serialConfig.portConfig = &uartConfig; +#endif +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_UsbCdc == device) + { +#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U)) + serialConfig.portConfig = &usbCdcConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_Swo == device) + { +#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U)) + serialConfig.portConfig = &swoConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else if (kSerialPort_Virtual == device) + { +#if (defined(SERIAL_PORT_TYPE_VIRTUAL) && (SERIAL_PORT_TYPE_VIRTUAL > 0U)) + serialConfig.portConfig = &serialPortVirtualConfig; +#else + status = kStatus_SerialManager_Error; +#endif + } + else + { + status = kStatus_SerialManager_Error; + } + + if (kStatus_SerialManager_Error != status) + { + (void)memset(&s_debugConsoleState, 0, sizeof(s_debugConsoleState)); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + s_debugConsoleState.writeRingBuffer.ringBufferSize = DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN; +#endif + + s_debugConsoleState.serialHandle = (serial_handle_t)&s_debugConsoleState.serialHandleBuffer[0]; + status = SerialManager_Init(s_debugConsoleState.serialHandle, &serialConfig); + + assert(kStatus_SerialManager_Success == status); + +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) +#if configSUPPORT_STATIC_ALLOCATION + DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore, &s_debugConsoleReadSemaphoreStatic); +#else + DEBUG_CONSOLE_CREATE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif +#endif +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) && configSUPPORT_STATIC_ALLOCATION + DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore, &s_debugConsoleReadWaitSemaphoreStatic); +#else + DEBUG_CONSOLE_CREATE_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore); +#endif +#endif + + { + status = + SerialManager_OpenWriteHandle(s_debugConsoleState.serialHandle, + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallTxCallback( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + DbgConsole_SerialManagerTxCallback, &s_debugConsoleState); + status = SerialManager_OpenWriteHandle( + s_debugConsoleState.serialHandle, + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0])); + assert(kStatus_SerialManager_Success == status); + (void)SerialManager_InstallTxCallback( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0]), + DbgConsole_SerialManagerTx2Callback, &s_debugConsoleState); +#endif + } + +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + status = + SerialManager_OpenReadHandle(s_debugConsoleState.serialHandle, + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + assert(kStatus_SerialManager_Success == status); +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_InstallRxCallback( + ((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), + DbgConsole_SerialManagerRxCallback, &s_debugConsoleState); +#endif + } +#endif + + g_serialHandle = s_debugConsoleState.serialHandle; + } + return (status_t)status; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_EnterLowpower(void) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + if (s_debugConsoleState.serialHandle != NULL) + { + status = SerialManager_EnterLowpower(s_debugConsoleState.serialHandle); + } + return (status_t)status; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_ExitLowpower(void) +{ + serial_manager_status_t status = kStatus_SerialManager_Error; + + if (s_debugConsoleState.serialHandle != NULL) + { + status = SerialManager_ExitLowpower(s_debugConsoleState.serialHandle); + } + return (status_t)status; +} +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Deinit(void) +{ + { + if (s_debugConsoleState.serialHandle != NULL) + { +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_CloseWriteHandle( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer2[0])); +#endif + (void)SerialManager_CloseWriteHandle( + ((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); + } + } +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + { + if (s_debugConsoleState.serialHandle != NULL) + { + (void)SerialManager_CloseReadHandle(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0])); + } + } +#endif + if (NULL != s_debugConsoleState.serialHandle) + { + if (kStatus_SerialManager_Success == SerialManager_Deinit(s_debugConsoleState.serialHandle)) + { + s_debugConsoleState.serialHandle = NULL; + g_serialHandle = NULL; + } + } +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + DEBUG_CONSOLE_DESTROY_BINARY_SEMAPHORE(s_debugConsoleReadWaitSemaphore); +#endif +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_DESTROY_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + + return (status_t)kStatus_Success; +} +#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ + +#if (((defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE > DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN))) || \ + ((SDK_DEBUGCONSOLE == 0U) && defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) && \ + (defined(DEBUG_CONSOLE_TX_RELIABLE_ENABLE) && (DEBUG_CONSOLE_TX_RELIABLE_ENABLE > 0U)))) +DEBUG_CONSOLE_FUNCTION_PREFIX status_t DbgConsole_Flush(void) +{ +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_BM) && defined(OSA_USED) + + if (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { + return (status_t)kStatus_Fail; + } + +#else + + while (s_debugConsoleState.writeRingBuffer.ringHead != s_debugConsoleState.writeRingBuffer.ringTail) + { +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + if (0U == IS_RUNNING_IN_ISR()) + { + if (taskSCHEDULER_RUNNING == xTaskGetSchedulerState()) + { + vTaskDelay(1); + } + } + else + { + return (status_t)kStatus_Fail; + } +#endif + } + +#endif + +#endif + return (status_t)kStatus_Success; +} +#endif + +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Printf(const char *fmt_s, ...) +{ + va_list ap; + int result = 0; + + va_start(ap, fmt_s); + result = DbgConsole_Vprintf(fmt_s, ap); + va_end(ap); + + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg) +{ + int logLength = 0, result = 0; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'}; + + if (NULL != g_serialHandle) + { + /* format print log first */ + logLength = StrFormatPrintf(fmt_s, formatStringArg, printBuf, DbgConsole_PrintCallback); + /* print log */ + result = DbgConsole_SendDataReliable((uint8_t *)printBuf, (size_t)logLength); + } + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Putchar(int ch) +{ + /* print char */ + return DbgConsole_SendDataReliable((uint8_t *)&ch, 1U); +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Scanf(char *fmt_s, ...) +{ + va_list ap; + int formatResult; + char scanfBuf[DEBUG_CONSOLE_SCANF_MAX_LOG_LEN + 1U] = {'\0'}; + + /* scanf log */ + (void)DbgConsole_ReadLine((uint8_t *)scanfBuf, DEBUG_CONSOLE_SCANF_MAX_LOG_LEN); + /* get va_list */ + va_start(ap, fmt_s); + /* format scanf log */ + formatResult = StrFormatScanf(scanfBuf, fmt_s, ap); + + va_end(ap); + + return formatResult; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_BlockingPrintf(const char *fmt_s, ...) +{ + va_list ap; + int result = 0; + + va_start(ap, fmt_s); + result = DbgConsole_BlockingVprintf(fmt_s, ap); + va_end(ap); + + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_BlockingVprintf(const char *fmt_s, va_list formatStringArg) +{ + status_t status; + int logLength = 0, result = 0; + char printBuf[DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN] = {'\0'}; + + if (NULL == g_serialHandle) + { + return 0; + } + + /* format print log first */ + logLength = StrFormatPrintf(fmt_s, formatStringArg, printBuf, DbgConsole_PrintCallback); + +#if defined(DEBUG_CONSOLE_TRANSFER_NON_BLOCKING) + (void)SerialManager_CancelWriting(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0])); +#endif + /* print log */ + status = + (status_t)SerialManager_WriteBlocking(((serial_write_handle_t)&s_debugConsoleState.serialWriteHandleBuffer[0]), + (uint8_t *)printBuf, (size_t)logLength); + result = (((status_t)kStatus_Success == status) ? (int)logLength : -1); + + return result; +} + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +status_t DbgConsole_TryGetchar(char *ch) +{ +#if (defined(DEBUG_CONSOLE_RX_ENABLE) && (DEBUG_CONSOLE_RX_ENABLE > 0U)) + uint32_t length = 0; + status_t status = (status_t)kStatus_Fail; + + assert(ch); + + if (NULL == g_serialHandle) + { + return kStatus_Fail; + } + + /* take mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_TAKE_MUTEX_SEMAPHORE_BLOCKING(s_debugConsoleReadSemaphore); +#endif + + if (kStatus_SerialManager_Success == + SerialManager_TryRead(((serial_read_handle_t)&s_debugConsoleState.serialReadHandleBuffer[0]), (uint8_t *)ch, 1, + &length)) + { + if (length != 0U) + { +#if DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION + (void)DbgConsole_EchoCharacter((uint8_t *)ch, true, NULL); +#endif + status = (status_t)kStatus_Success; + } + } + /* release mutex lock function */ +#if (DEBUG_CONSOLE_SYNCHRONIZATION_MODE == DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS) + DEBUG_CONSOLE_GIVE_MUTEX_SEMAPHORE(s_debugConsoleReadSemaphore); +#endif + return status; +#else + return (status_t)kStatus_Fail; +#endif +} +#endif + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Getchar(void) +{ + int ret = -1; + uint8_t ch = 0U; + + /* Get char */ + if (DbgConsole_ReadCharacter(&ch) > 0) + { + ret = (int)ch; + } + + return ret; +} + +#endif /* SDK_DEBUGCONSOLE */ + +/*************Code to support toolchain's printf, scanf *******************************/ +/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ +#if (defined(__ICCARM__)) +#if defined(SDK_DEBUGCONSOLE_UART) +#pragma weak __write +size_t __write(int handle, const unsigned char *buffer, size_t size); +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + size_t ret; + if (NULL == buffer) + { + /* + * This means that we should flush internal buffers. Since we don't we just return. + * (Remember, "handle" == -1 means that all handles should be flushed.) + */ + ret = 0U; + } + else if ((handle != 1) && (handle != 2)) + { + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. + */ + ret = (size_t)-1; + } + else + { + /* Send data. */ + uint8_t buff[512]; + (void)memcpy(buff, buffer, size); + (void)DbgConsole_SendDataReliable((uint8_t *)buff, size); + + ret = size; + } + return ret; +} + +#pragma weak __read +size_t __read(int handle, unsigned char *buffer, size_t size); +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + uint8_t ch = 0U; + int actualSize = 0; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (0 != handle) + { + actualSize = -1; + } + else + { + /* Receive data.*/ + for (; size > 0U; size--) + { + (void)DbgConsole_ReadCharacter(&ch); + if (0U == ch) + { + break; + } + + *buffer++ = ch; + actualSize++; + } + } + return (size_t)actualSize; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* support LPC Xpresso with RedLib */ +#elif (defined(__REDLIB__)) + +#if (defined(SDK_DEBUGCONSOLE_UART)) +int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + DbgConsole_SendDataReliable((uint8_t *)buffer, size); + + return 0; +} + +int __attribute__((weak)) __sys_readc(void) +{ + char tmp; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&tmp); + + return tmp; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if defined(SDK_DEBUGCONSOLE_UART) +#if defined(__CC_ARM) +struct __FILE +{ + int handle; + /* + * Whatever you require here. If the only file you are using is standard output using printf() for debugging, + * no file handling is required. + */ +}; +#endif + +/* FILE is typedef in stdio.h. */ +#pragma weak __stdout +#pragma weak __stdin +FILE __stdout; +FILE __stdin; + +#pragma weak fputc +int fputc(int ch, FILE *f) +{ + /* Send data. */ + return DbgConsole_SendDataReliable((uint8_t *)(&ch), 1); +} + +#pragma weak fgetc +int fgetc(FILE *f) +{ + char ch; + + /* Receive data. */ + DbgConsole_ReadCharacter((uint8_t *)&ch); + + return ch; +} + +/* + * Terminate the program, passing a return code back to the user. + * This function may not return. + */ +void _sys_exit(int returncode) +{ + while (1) + { + } +} + +/* + * Writes a character to the output channel. This function is used + * for last-resort error message output. + */ +void _ttywrch(int ch) +{ + char ench = ch; + DbgConsole_SendDataReliable((uint8_t *)(&ench), 1); +} + +char *_sys_command_string(char *cmd, int len) +{ + return (cmd); +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ +#elif (defined(__GNUC__)) + +#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ + (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART)))) +int __attribute__((weak)) _write(int handle, char *buffer, int size); +int __attribute__((weak)) _write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Send data. */ + (void)DbgConsole_SendDataReliable((uint8_t *)buffer, (size_t)size); + + return size; +} + +int __attribute__((weak)) _read(int handle, char *buffer, int size); +int __attribute__((weak)) _read(int handle, char *buffer, int size) +{ + uint8_t ch = 0U; + int actualSize = 0; + + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Receive data. */ + for (; size > 0; size--) + { + if (DbgConsole_ReadCharacter(&ch) < 0) + { + break; + } + + *buffer++ = (char)ch; + actualSize++; + + if ((ch == 0U) || (ch == (uint8_t)'\n') || (ch == (uint8_t)'\r')) + { + break; + } + } + + return (actualSize > 0) ? actualSize : -1; +} +#endif + +#endif /* __ICCARM__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console/fsl_debug_console.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console/fsl_debug_console.h new file mode 100644 index 0000000000..374148ff85 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console/fsl_debug_console.h @@ -0,0 +1,317 @@ +/* + * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2018, 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Debug console shall provide input and output functions to scan and print formatted data. + * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" + * - [flags] :'-', '+', '#', ' ', '0' + * - [width]: number (0,1...) + * - [.precision]: number (0,1...) + * - [length]: do not support + * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' + * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" + * - [*]: is supported. + * - [width]: number (0,1...) + * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') + * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' + */ + +#ifndef _FSL_DEBUGCONSOLE_H_ +#define _FSL_DEBUGCONSOLE_H_ + +#include "fsl_common.h" +#include "fsl_component_serial_manager.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +extern serial_handle_t g_serialHandle; /*!< serial manager handle */ + +/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */ +#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */ +#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */ +#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */ + +/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support + * to be redefined in project setting. + */ +#ifndef SDK_DEBUGCONSOLE +#define SDK_DEBUGCONSOLE DEBUGCONSOLE_REDIRECT_TO_SDK +#endif + +#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) +#include +#else +#include +#endif + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. + * + * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf. + * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf. + * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function. + */ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */ +static inline int DbgConsole_Disabled(void) +{ + return -1; +} +#define PRINTF(...) DbgConsole_Disabled() +#define SCANF(...) DbgConsole_Disabled() +#define PUTCHAR(...) DbgConsole_Disabled() +#define GETCHAR() DbgConsole_Disabled() +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */ +#define PRINTF DbgConsole_Printf +#define SCANF DbgConsole_Scanf +#define PUTCHAR DbgConsole_Putchar +#define GETCHAR DbgConsole_Getchar +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \ + */ +#define PRINTF printf +#define SCANF scanf +#define PUTCHAR putchar +#define GETCHAR getchar +#endif /* SDK_DEBUGCONSOLE */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +/*! + * @brief Initializes the peripheral used for debug messages. + * + * Call this function to enable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * After this function has returned, stdout and stdin are connected to the selected peripheral. + * + * @param instance The instance of the module.If the device is kSerialPort_Uart, + * the instance is UART peripheral instance. The UART hardware peripheral + * type is determined by UART adapter. For example, if the instance is 1, + * if the lpuart_adapter.c is added to the current project, the UART periheral + * is LPUART1. + * If the uart_adapter.c is added to the current project, the UART periheral + * is UART1. + * @param baudRate The desired baud rate in bits per second. + * @param device Low level device type for the debug console, can be one of the following. + * @arg kSerialPort_Uart, + * @arg kSerialPort_UsbCdc + * @param clkSrcFreq Frequency of peripheral source clock. + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq); + +/*! + * @brief De-initializes the peripheral used for debug messages. + * + * Call this function to disable debug log messages to be output via the specified peripheral + * initialized by the serial manager module. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_Deinit(void); +/*! + * @brief Prepares to enter low power consumption. + * + * This function is used to prepare to enter low power consumption. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_EnterLowpower(void); + +/*! + * @brief Restores from low power consumption. + * + * This function is used to restore from low power consumption. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_ExitLowpower(void); + +#else +/*! + * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Init(uint8_t instance, + uint32_t baudRate, + serial_port_type_t device, + uint32_t clkSrcFreq) +{ + (void)instance; + (void)baudRate; + (void)device; + (void)clkSrcFreq; + return (status_t)kStatus_Fail; +} +/*! + * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Deinit(void) +{ + return (status_t)kStatus_Fail; +} + +/*! + * Use an error to replace the DbgConsole_EnterLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_EnterLowpower(void) +{ + return (status_t)kStatus_Fail; +} + +/*! + * Use an error to replace the DbgConsole_ExitLowpower when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_ExitLowpower(void) +{ + return (status_t)kStatus_Fail; +} + +#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ + +#if (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK)) +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Printf(const char *fmt_s, ...); + +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @param formatStringArg Format arguments. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg); + +/*! + * @brief Writes a character to stdout. + * + * Call this function to write a character to stdout. + * + * @param ch Character to be written. + * @return Returns the character written. + */ +int DbgConsole_Putchar(int ch); + +/*! + * @brief Reads formatted data from the standard input stream. + * + * Call this function to read formatted data from the standard input stream. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @param fmt_s Format control string. + * @return Returns the number of fields successfully converted and assigned. + */ +int DbgConsole_Scanf(char *fmt_s, ...); + +/*! + * @brief Reads a character from standard input. + * + * Call this function to read a character from standard input. + * + * @note Due the limitation in the BM OSA environment (CPU is blocked in the function, + * other tasks will not be scheduled), the function cannot be used when the + * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment. + * And an error is returned when the function called in this case. The suggestion + * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char. + * + * @return Returns the character read. + */ +int DbgConsole_Getchar(void); + +/*! + * @brief Writes formatted output to the standard output stream with the blocking mode. + * + * Call this function to write a formatted output to the standard output stream with the blocking mode. + * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set + * or not. + * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set. + * + * @param fmt_s Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_BlockingPrintf(const char *fmt_s, ...); + +/*! + * @brief Writes formatted output to the standard output stream with the blocking mode. + * + * Call this function to write a formatted output to the standard output stream with the blocking mode. + * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set + * or not. + * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set. + * + * @param fmt_s Format control string. + * @param formatStringArg Format arguments. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_BlockingVprintf(const char *fmt_s, va_list formatStringArg); + +/*! + * @brief Debug console flush. + * + * Call this function to wait the tx buffer empty. + * If interrupt transfer is using, make sure the global IRQ is enable before call this function + * This function should be called when + * 1, before enter power down mode + * 2, log is required to print to terminal immediately + * @return Indicates whether wait idle was successful or not. + */ +status_t DbgConsole_Flush(void); + +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! + * @brief Debug console try to get char + * This function provides a API which will not block current task, if character is + * available return it, otherwise return fail. + * @param ch the address of char to receive + * @return Indicates get char was successful or not. + */ +status_t DbgConsole_TryGetchar(char *ch); +#endif + +#endif /* SDK_DEBUGCONSOLE */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console/fsl_debug_console_conf.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console/fsl_debug_console_conf.h new file mode 100644 index 0000000000..fd235b1e54 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console/fsl_debug_console_conf.h @@ -0,0 +1,160 @@ +/* + * Copyright 2017 - 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef _FSL_DEBUG_CONSOLE_CONF_H_ +#define _FSL_DEBUG_CONSOLE_CONF_H_ + +#include "fsl_common.h" + +/****************Debug console configuration********************/ + +/*! @brief If Non-blocking mode is needed, please define it at project setting, + * otherwise blocking mode is the default transfer mode. + * Warning: If you want to use non-blocking transfer,please make sure the corresponding + * IO interrupt is enable, otherwise there is no output. + * And non-blocking is combine with buffer, no matter bare-metal or rtos. + * Below shows how to configure in your project if you want to use non-blocking mode. + * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols". + * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define". + * For ARMGCC, open CmakeLists.txt and add the following lines, + * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target. + * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target. + * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C + * Complier->Preprocessor". + * + */ +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically + * when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed , because the log will not be + * buffered if the buffer is full, and the print will return immediately with -1. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN +#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U) +#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */ + +/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when + * non-blocking transfer is using, + * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement. + * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small. + * And this value should be multiple of 4 to meet memory alignment. + * + */ +#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN +#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U) +#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */ + +/*!@ brief Whether enable the reliable TX function + * If the macro is zero, the reliable TX function of the debug console is disabled. + * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full. + */ +#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE +#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U) +#endif /* DEBUG_CONSOLE_TX_RELIABLE_ENABLE */ + +#else +#define DEBUG_CONSOLE_TRANSFER_BLOCKING +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ + +/*!@ brief Whether enable the RX function + * If the macro is zero, the receive function of the debug console is disabled. + */ +#ifndef DEBUG_CONSOLE_RX_ENABLE +#define DEBUG_CONSOLE_RX_ENABLE (1U) +#endif /* DEBUG_CONSOLE_RX_ENABLE */ + +/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log + * length can not bigger than this value. + * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if + * the buffer is too big and current task stack size not big enough. + */ +#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN +#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U) +#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */ + +/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log + * length can not bigger than this value. + * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN. + */ +#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN +#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U) +#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */ + +/*! @brief Debug console synchronization + * User should not change these macro for synchronization mode, but add the + * corresponding synchronization mechanism per different software environment. + * Such as, if another RTOS is used, + * add: + * \#define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3 + * in this configuration file and implement the synchronization in fsl.log.c. + */ +/*! @brief synchronization for baremetal software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0 +/*! @brief synchronization for freertos software */ +#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1 + +/*! @brief RTOS synchronization mechanism disable + * If not defined, default is enable, to avoid multitask log print mess. + * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c + * If synchronization is disabled, log maybe messed on terminal. + */ +#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION +#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING +#ifdef SDK_OS_FREE_RTOS +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* SDK_OS_FREE_RTOS */ +#else +#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM +#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */ +#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */ + +/*! @brief echo function support + * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO + * at your project setting. + */ +#ifndef DEBUG_CONSOLE_ENABLE_ECHO +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0 +#else +#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1 +#endif /* DEBUG_CONSOLE_ENABLE_ECHO */ + +/*********************************************************************/ + +/***************Debug console other configuration*********************/ +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/*! @brief Definition to select virtual com(USB CDC) as the debug console. */ +#ifndef BOARD_USE_VIRTUALCOM +#define BOARD_USE_VIRTUALCOM 0U +#endif +/*******************************************************************/ + +#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/fsl_assert.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/fsl_assert.c new file mode 100644 index 0000000000..bb9127acdf --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/fsl_assert.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#else + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#endif + + for (;;) + { + __BKPT(0); + } +} +#elif (defined(__GNUC__)) +#if defined(__REDLIB__) +void __assertion_failed(char *failedExpr) +{ + (void)PRINTF("ASSERT ERROR \" %s \n", failedExpr); + for (;;) + { + __BKPT(0); + } +} +#else +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, + func); + for (;;) + { + __BKPT(0); + } +} +#endif /* defined(__REDLIB__) */ +#else /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ + +#if (defined(__DSC__) && defined(__CW__)) + +void __msl_assertion_failed(char const *failedExpr, char const *file, char const *func, int line) +{ + PRINTF("\r\nASSERT ERROR\r\n"); + PRINTF(" File : %s\r\n", file); + PRINTF(" Function : %s\r\n", func); /*compiler not support func name yet*/ + PRINTF(" Line : %u\r\n", (uint32_t)line); + PRINTF(" failedExpr: %s\r\n", failedExpr); + asm(DEBUGHLT); +} + +#endif /* (defined(__DSC__) && defined (__CW__)) */ + +#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ +#endif /* NDEBUG */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/fsl_debug_console.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/fsl_debug_console.c new file mode 100644 index 0000000000..64804089cf --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/fsl_debug_console.c @@ -0,0 +1,1956 @@ +/* + * Copyright 2017-2018, 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include +#include +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) +#include +#endif +#include +#include "fsl_debug_console.h" +#include "fsl_adapter_uart.h" + +/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ +#if defined(__CC_ARM) +#pragma diag_suppress 1256 +#endif /* __CC_ARM */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief This definition is maximum line that debugconsole can scanf each time.*/ +#define IO_MAXLINE 20U + +/*! @brief The overflow value.*/ +#ifndef HUGE_VAL +#define HUGE_VAL (99.e99) +#endif /* HUGE_VAL */ + +/*! @brief State structure storing debug console. */ +typedef struct DebugConsoleState +{ + uint8_t uartHandleBuffer[HAL_UART_HANDLE_SIZE]; + hal_uart_status_t (*putChar)(hal_uart_handle_t handle, + const uint8_t *data, + size_t length); /*!< put char function pointer */ + hal_uart_status_t (*getChar)(hal_uart_handle_t handle, + uint8_t *data, + size_t length); /*!< get char function pointer */ + serial_port_type_t serial_port_type; /*!< The initialized port of the debug console. */ +} debug_console_state_t; + +/*! @brief Type of KSDK printf function pointer. */ +typedef int (*PUTCHAR_FUNC)(int a); + +#if PRINTF_ADVANCED_ENABLE +/*! @brief Specification modifier flags for printf. */ +enum _debugconsole_printf_flag +{ + kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ + kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ + kPRINTF_Space = 0x04U, /*!< Space Flag. */ + kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ + kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ + kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ + kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ + kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ + kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ +}; +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Specification modifier flags for scanf. */ +enum _debugconsole_scanf_flag +{ + kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ + kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ + kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ + kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ + kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ + kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ + kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ + kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ +#if SCANF_ADVANCED_ENABLE + kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ + kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ + kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ + kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ +#endif /*SCANF_FLOAT_ENABLE */ + kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ +}; + +/******************************************************************************* + * Variables + ******************************************************************************/ +#if SDK_DEBUGCONSOLE +/*! @brief Debug UART state information. */ +static debug_console_state_t s_debugConsole; +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if SDK_DEBUGCONSOLE +static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap); +static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr); +#endif /* SDK_DEBUGCONSOLE */ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*************Code for DbgConsole Init, Deinit, Printf, Scanf *******************************/ + +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq) +{ + hal_uart_config_t usrtConfig; + + if (kSerialPort_Uart != device) + { + return kStatus_Fail; + } + + /* Set debug console to initialized to avoid duplicated initialized operation. */ + s_debugConsole.serial_port_type = device; + + usrtConfig.srcClock_Hz = clkSrcFreq; + usrtConfig.baudRate_Bps = baudRate; + usrtConfig.parityMode = kHAL_UartParityDisabled; + usrtConfig.stopBitCount = kHAL_UartOneStopBit; + usrtConfig.enableRx = 1U; + usrtConfig.enableTx = 1U; + usrtConfig.enableRxRTS = 0U; + usrtConfig.enableTxCTS = 0U; + usrtConfig.instance = instance; +#if (defined(HAL_UART_ADAPTER_FIFO) && (HAL_UART_ADAPTER_FIFO > 0u)) + usrtConfig.txFifoWatermark = 0U; + usrtConfig.rxFifoWatermark = 0U; +#endif + /* Enable clock and initial UART module follow user configure structure. */ + (void)HAL_UartInit((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], &usrtConfig); + /* Set the function pointer for send and receive for this kind of device. */ + s_debugConsole.putChar = HAL_UartSendBlocking; + s_debugConsole.getChar = HAL_UartReceiveBlocking; + + return kStatus_Success; +} + +/* See fsl_debug_console.h for documentation of this function. */ +status_t DbgConsole_Deinit(void) +{ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return kStatus_Success; + } + + (void)HAL_UartDeinit((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0]); + + s_debugConsole.serial_port_type = kSerialPort_None; + + return kStatus_Success; +} +#endif /* DEBUGCONSOLE_REDIRECT_TO_SDK */ + +#if SDK_DEBUGCONSOLE +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Printf(const char *fmt_s, ...) +{ + va_list ap; + int result = 0; + + va_start(ap, fmt_s); + result = DbgConsole_Vprintf(fmt_s, ap); + va_end(ap); + + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg) +{ + int result = 0; + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + + result = DbgConsole_PrintfFormattedData(DbgConsole_Putchar, fmt_s, formatStringArg); + + return result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Putchar(int ch) +{ + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1); + + return 1; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Scanf(char *fmt_s, ...) +{ + /* Plus one to store end of string char */ + char temp_buf[IO_MAXLINE + 1]; + va_list ap; + int32_t i; + char result; + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + va_start(ap, fmt_s); + temp_buf[0] = '\0'; + + i = 0; + while (true) + { + if (i >= (int32_t)IO_MAXLINE) + { + break; + } + + result = (char)DbgConsole_Getchar(); + temp_buf[i] = result; + + if ((result == '\r') || (result == '\n')) + { + /* End of Line. */ + if (i == 0) + { + temp_buf[i] = '\0'; + i = -1; + } + else + { + break; + } + } + + i++; + } + + if (i == (int32_t)IO_MAXLINE) + { + temp_buf[i] = '\0'; + } + else + { + temp_buf[i + 1] = '\0'; + } + result = (char)DbgConsole_ScanfFormattedData(temp_buf, fmt_s, ap); + va_end(ap); + + return (int)result; +} + +/* See fsl_debug_console.h for documentation of this function. */ +int DbgConsole_Getchar(void) +{ + char ch; + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + while (kStatus_HAL_UartSuccess != + s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1)) + { + return -1; + } + + return (int)ch; +} + +/*************Code for process formatted data*******************************/ +/*! + * @brief Scanline function which ignores white spaces. + * + * @param[in] s The address of the string pointer to update. + * @return String without white spaces. + */ +static uint32_t DbgConsole_ScanIgnoreWhiteSpace(const char **s) +{ + uint8_t count = 0; + char c; + + c = **s; + while ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) + { + count++; + (*s)++; + c = **s; + } + return count; +} + +/*! + * @brief This function puts padding character. + * + * @param[in] c Padding character. + * @param[in] curlen Length of current formatted string . + * @param[in] width Width of expected formatted string. + * @param[in] count Number of characters. + * @param[in] func_ptr Function to put character out. + */ +static void DbgConsole_PrintfPaddingCharacter( + char c, int32_t curlen, int32_t width, int32_t *count, PUTCHAR_FUNC func_ptr) +{ + int32_t i; + + for (i = curlen; i < width; i++) + { + (void)func_ptr(c); + (*count)++; + } +} + +/*! + * @brief Converts a radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] neg Polarity of the number. + * @param[in] radix The radix to be converted to. + * @param[in] use_caps Used to identify %x/X output format. + + * @return Length of the converted string. + */ +static int32_t DbgConsole_ConvertRadixNumToString(char *numstr, void *nump, int32_t neg, int32_t radix, bool use_caps) +{ +#if PRINTF_ADVANCED_ENABLE + long long int a; + long long int b; + long long int c; + + unsigned long long int ua; + unsigned long long int ub; + unsigned long long int uc; + unsigned long long int uc_param; +#else + int a; + int b; + int c; + + unsigned int ua; + unsigned int ub; + unsigned int uc; + unsigned int uc_param; +#endif /* PRINTF_ADVANCED_ENABLE */ + + int32_t nlen; + char *nstrp; + + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + +#if !(PRINTF_ADVANCED_ENABLE > 0) + neg = 0; +#endif + +#if PRINTF_ADVANCED_ENABLE + a = 0; + b = 0; + c = 0; + ua = 0ULL; + ub = 0ULL; + uc = 0ULL; + uc_param = 0ULL; +#else + a = 0; + b = 0; + c = 0; + ua = 0U; + ub = 0U; + uc = 0U; + uc_param = 0U; +#endif /* PRINTF_ADVANCED_ENABLE */ + + (void)a; + (void)b; + (void)c; + (void)ua; + (void)ub; + (void)uc; + (void)uc_param; + (void)neg; + /* + * Fix MISRA issue: CID 15985711 (#15 of 15): MISRA C-2012 Control Flow Expressions (MISRA C-2012 Rule 14.3) + * misra_c_2012_rule_14_3_violation: Execution cannot reach this statement: a = *((int *)nump); + */ +#if PRINTF_ADVANCED_ENABLE + if (0 != neg) + { +#if PRINTF_ADVANCED_ENABLE + a = *(long long int *)nump; +#else + a = *(int *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (a == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (a != 0) + { +#if PRINTF_ADVANCED_ENABLE + b = (long long int)a / (long long int)radix; + c = (long long int)a - ((long long int)b * (long long int)radix); + if (c < 0) + { + uc = (unsigned long long int)c; + uc_param = ~uc; + c = (long long int)uc_param + 1 + (long long int)'0'; + } +#else + b = (int)a / (int)radix; + c = (int)a - ((int)b * (int)radix); + if (c < 0) + { + uc = (unsigned int)c; + uc_param = ~uc; + c = (int)uc_param + 1 + (int)'0'; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + c = c + (int)'0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { +#if PRINTF_ADVANCED_ENABLE + ua = *(unsigned long long int *)nump; +#else + ua = *(unsigned int *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (ua == 0U) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (ua != 0U) + { +#if PRINTF_ADVANCED_ENABLE + ub = (unsigned long long int)ua / (unsigned long long int)radix; + uc = (unsigned long long int)ua - ((unsigned long long int)ub * (unsigned long long int)radix); +#else + ub = ua / (unsigned int)radix; + uc = ua - (ub * (unsigned int)radix); +#endif /* PRINTF_ADVANCED_ENABLE */ + + if (uc < 10U) + { + uc = uc + (unsigned int)'0'; + } + else + { + uc = uc - 10U + (unsigned int)(use_caps ? 'A' : 'a'); + } + ua = ub; + *nstrp++ = (char)uc; + ++nlen; + } + } + return nlen; +} + +#if PRINTF_FLOAT_ENABLE +/*! + * @brief Converts a floating radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] radix The radix to be converted to. + * @param[in] precision_width Specify the precision width. + + * @return Length of the converted string. + */ +static int32_t DbgConsole_ConvertFloatRadixNumToString(char *numstr, + void *nump, + int32_t radix, + uint32_t precision_width) +{ + int32_t a; + int32_t b; + int32_t c; + uint32_t i; + double fa; + double dc; + double fb; + double r; + double fractpart; + double intpart; + + int32_t nlen; + char *nstrp; + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + r = *(double *)nump; + if (0.0 == r) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + fractpart = modf((double)r, (double *)&intpart); + /* Process fractional part. */ + for (i = 0; i < precision_width; i++) + { + fractpart *= (double)radix; + } + if (r >= 0.0) + { + fa = fractpart + (double)0.5; + if (fa >= pow((double)10, (double)precision_width)) + { + intpart++; + } + } + else + { + fa = fractpart - (double)0.5; + if (fa <= -pow((double)10, (double)precision_width)) + { + intpart--; + } + } + for (i = 0; i < precision_width; i++) + { + fb = fa / (double)radix; + dc = (fa - (double)(long long int)fb * (double)radix); + c = (int32_t)dc; + if (c < 0) + { + c = (int32_t)'0' - c; + } + else + { + c = c + '0'; + } + fa = fb; + *nstrp++ = (char)c; + ++nlen; + } + *nstrp++ = (char)'.'; + ++nlen; + a = (int32_t)intpart; + if (a == 0) + { + *nstrp++ = '0'; + ++nlen; + } + else + { + while (a != 0) + { + b = (int32_t)a / (int32_t)radix; + c = (int32_t)a - ((int32_t)b * (int32_t)radix); + if (c < 0) + { + c = (int32_t)'0' - c; + } + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + return nlen; +} +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! + * @brief This function outputs its parameters according to a formatted string. + * + * @note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * @param[in] func_ptr Function to put character out. + * @param[in] fmt Format string for printf. + * @param[in] ap Arguments to printf. + * + * @return Number of characters + */ +static int DbgConsole_PrintfFormattedData(PUTCHAR_FUNC func_ptr, const char *fmt, va_list ap) +{ + /* va_list ap; */ + const char *p; + char c; + + char vstr[33]; + char *vstrp = NULL; + int32_t vlen = 0; + + bool done; + int32_t count = 0; + + uint32_t field_width; + uint32_t precision_width; + char *sval; + int32_t cval; + bool use_caps; + uint8_t radix = 0; + +#if PRINTF_ADVANCED_ENABLE + uint32_t flags_used; + char schar; + bool dschar; + long long int ival; + unsigned long long int uval = 0; + bool valid_precision_width; +#else + int ival; + unsigned int uval = 0; +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_FLOAT_ENABLE + double fval; +#endif /* PRINTF_FLOAT_ENABLE */ + + /* Start parsing apart the format string and display appropriate formats and data. */ + p = fmt; + while (true) + { + if ('\0' == *p) + { + break; + } + c = *p; + /* + * All formats begin with a '%' marker. Special chars like + * '\n' or '\t' are normally converted to the appropriate + * character by the __compiler__. Thus, no need for this + * routine to account for the '\' character. + */ + if (c != '%') + { + (void)func_ptr(c); + count++; + p++; + /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ + continue; + } + + use_caps = true; + +#if PRINTF_ADVANCED_ENABLE + /* First check for specification modifier flags. */ + flags_used = 0; + done = false; + while (!done) + { + switch (*++p) + { + case '-': + flags_used |= (uint32_t)kPRINTF_Minus; + break; + case '+': + flags_used |= (uint32_t)kPRINTF_Plus; + break; + case ' ': + flags_used |= (uint32_t)kPRINTF_Space; + break; + case '0': + flags_used |= (uint32_t)kPRINTF_Zero; + break; + case '#': + flags_used |= (uint32_t)kPRINTF_Pound; + break; + default: + /* We've gone one char too far. */ + --p; + done = true; + break; + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + + /* Next check for minimum field width. */ + field_width = 0; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + field_width = (field_width * 10U) + ((uint32_t)c - (uint32_t)'0'); + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + field_width = (uint32_t)va_arg(ap, unsigned int); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + /* Next check for the width and precision field separator. */ +#if (PRINTF_ADVANCED_ENABLE || PRINTF_FLOAT_ENABLE) + precision_width = 6U; /* MISRA C-2012 Rule 2.2 */ +#endif +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = false; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (*++p == '.') + { + /* Must get precision field width, if present. */ + precision_width = 0U; + done = false; + while (!done) + { + c = *++p; + if ((c >= '0') && (c <= '9')) + { + precision_width = (precision_width * 10U) + ((uint32_t)c - (uint32_t)'0'); +#if PRINTF_ADVANCED_ENABLE + valid_precision_width = true; +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + precision_width = (uint32_t)va_arg(ap, unsigned int); + valid_precision_width = true; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = true; + } + } + } + else + { + /* We've gone one char too far. */ + --p; + } +#if PRINTF_ADVANCED_ENABLE + /* + * Check for the length modifier. + */ + switch (/* c = */ *++p) + { + case 'h': + if (*++p != 'h') + { + flags_used |= (uint32_t)kPRINTF_LengthShortInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthChar; + } + break; + case 'l': + if (*++p != 'l') + { + flags_used |= (uint32_t)kPRINTF_LengthLongInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthLongLongInt; + } + break; + default: + /* we've gone one char too far */ + --p; + break; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + /* Now we're ready to examine the format. */ + c = *++p; + { + if ((c == 'd') || (c == 'i') || (c == 'f') || (c == 'F') || (c == 'x') || (c == 'X') || (c == 'o') || + (c == 'b') || (c == 'p') || (c == 'u')) + { + if ((c == 'd') || (c == 'i')) + { +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + ival = (long long int)va_arg(ap, long long int); + } + else if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongInt)) + { + ival = (long int)va_arg(ap, long int); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + ival = (int)va_arg(ap, int); + } + vlen = DbgConsole_ConvertRadixNumToString(vstr, &ival, 1, 10, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (ival < 0) + { + schar = '-'; + ++vlen; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Plus)) + { + schar = '+'; + ++vlen; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Space)) + { + schar = ' '; + ++vlen; + } + else + { + schar = '\0'; + } + } + } + dschar = false; + /* Do the ZERO pad. */ + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if ('\0' != schar) + { + (void)func_ptr(schar); + count++; + } + dschar = true; + + DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr); + vlen = (int32_t)field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + if ('\0' != schar) + { + (void)func_ptr(schar); + count++; + } + dschar = true; + } + } + /* The string was built in reverse order, now display in correct order. */ + if ((!dschar) && ('\0' != schar)) + { + (void)func_ptr(schar); + count++; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + +#if PRINTF_FLOAT_ENABLE + if ((c == 'f') || (c == 'F')) + { + fval = (double)va_arg(ap, double); + vlen = DbgConsole_ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + if (fval < 0.0) + { + schar = '-'; + ++vlen; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Plus)) + { + schar = '+'; + ++vlen; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Space)) + { + schar = ' '; + ++vlen; + } + else + { + schar = '\0'; + } + } + } + dschar = false; + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if ('\0' != schar) + { + (void)func_ptr(schar); + count++; + } + dschar = true; + DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr); + vlen = (int32_t)field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + if ('\0' != schar) + { + (void)func_ptr(schar); + count++; + } + dschar = true; + } + } + if ((!dschar) && ('\0' != schar)) + { + (void)func_ptr(schar); + count++; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#endif /* PRINTF_FLOAT_ENABLE */ + if ((c == 'X') || (c == 'x')) + { + if (c == 'x') + { + use_caps = false; + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + uval = (unsigned long long int)va_arg(ap, unsigned long long int); + } + else if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongInt)) + { + uval = (unsigned long int)va_arg(ap, unsigned long int); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (unsigned int)va_arg(ap, unsigned int); + } + vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, 0, 16, use_caps); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + dschar = false; + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + (void)func_ptr('0'); + (void)func_ptr((use_caps ? 'X' : 'x')); + count += 2; + /*vlen += 2;*/ + dschar = true; + } + DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr); + vlen = (int32_t)field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Pound)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + vlen += 2; + } + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + (void)func_ptr('0'); + (void)func_ptr(use_caps ? 'X' : 'x'); + count += 2; + + dschar = true; + } + } + } + + if ((0U != (flags_used & (uint32_t)kPRINTF_Pound)) && (!dschar)) + { + (void)func_ptr('0'); + (void)func_ptr(use_caps ? 'X' : 'x'); + count += 2; + vlen += 2; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) + { + if ('p' == c) + { + /* + * Fix MISRA issue: CID 16209727 (#15 of 15): MISRA C-2012 Pointer Type Conversions (MISRA + * C-2012 Rule 11.6) + * 1. misra_c_2012_rule_11_6_violation: The expression va_arg (ap, void *) of type void * is + * cast to type unsigned int. + * + * Orignal code: uval = (unsigned int)va_arg(ap, void *); + */ + void *pval; + pval = (void *)va_arg(ap, void *); + (void)memcpy((void *)&uval, (void *)&pval, sizeof(void *)); + } + else + { +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + uval = (unsigned long long int)va_arg(ap, unsigned long long int); + } + else if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongInt)) + { + uval = (unsigned long int)va_arg(ap, unsigned long int); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (unsigned int)va_arg(ap, unsigned int); + } + } + switch (c) + { + case 'o': + radix = 8; + break; + case 'b': + radix = 2; + break; + case 'p': + radix = 16; + break; + case 'u': + radix = 10; + break; + default: + /* MISRA C-2012 Rule 16.4 */ + break; + } + vlen = DbgConsole_ConvertRadixNumToString(vstr, &uval, 0, (int32_t)radix, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + DbgConsole_PrintfPaddingCharacter('0', vlen, (int32_t)field_width, &count, func_ptr); + vlen = (int32_t)field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if !PRINTF_ADVANCED_ENABLE + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); +#endif /* !PRINTF_ADVANCED_ENABLE */ + if (vstrp != NULL) + { + while ('\0' != *vstrp) + { + (void)func_ptr(*vstrp--); + count++; + } + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + else if (c == 'c') + { + cval = (int32_t)va_arg(ap, unsigned int); + (void)func_ptr(cval); + count++; + } + else if (c == 's') + { + sval = (char *)va_arg(ap, char *); + if (NULL != sval) + { +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + vlen = (int32_t)precision_width; + } + else + { + vlen = (int32_t)strlen(sval); + } +#else + vlen = (int32_t)strlen(sval); +#endif /* PRINTF_ADVANCED_ENABLE */ +#if PRINTF_ADVANCED_ENABLE + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) +#endif /* PRINTF_ADVANCED_ENABLE */ + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + } + +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + while (('\0' != *sval) && (vlen > 0)) + { + (void)func_ptr(*sval++); + count++; + vlen--; + } + /* In case that vlen sval is shorter than vlen */ + vlen = (int32_t)precision_width - vlen; + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != *sval) + { + (void)func_ptr(*sval++); + count++; + } +#if PRINTF_ADVANCED_ENABLE + } +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + DbgConsole_PrintfPaddingCharacter(' ', vlen, (int32_t)field_width, &count, func_ptr); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + } + else + { + (void)func_ptr(c); + count++; + } + } + p++; + } + return (int)count; +} + +/*! + * @brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * @param[in] line_ptr The input line of ASCII data. + * @param[in] format Format first points to the format string. + * @param[in] args_ptr The list of parameters. + * + * @return Number of input items converted and assigned. + * @retval IO_EOF When line_ptr is empty string "". + */ +static int DbgConsole_ScanfFormattedData(const char *line_ptr, char *format, va_list args_ptr) +{ + uint8_t base; + int8_t neg; + /* Identifier for the format string. */ + char *c = format; + char temp; + char *buf; + /* Flag telling the conversion specification. */ + uint32_t flag = 0; + /* Filed width for the matching input streams. */ + uint32_t field_width; + /* How many arguments are assigned except the suppress. */ + uint32_t nassigned = 0; + bool match_failure = false; + /* How many characters are read from the input streams. */ + uint32_t n_decode = 0; + + int32_t val; + + const char *s; + /* Identifier for the input string. */ + const char *p = line_ptr; + +#if SCANF_FLOAT_ENABLE + double fnum = 0.0; +#endif /* SCANF_FLOAT_ENABLE */ + + /* Return EOF error before any conversion. */ + if (*p == '\0') + { + return -1; + } + + /* Decode directives. */ + while (('\0' != (*c)) && ('\0' != (*p))) + { + /* Ignore all white-spaces in the format strings. */ + if (0U != DbgConsole_ScanIgnoreWhiteSpace((const char **)(void *)&c)) + { + n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); + } + else if ((*c != '%') || ((*c == '%') && (*(c + 1) == '%'))) + { + /* Ordinary characters. */ + c++; + if (*p == *c) + { + n_decode++; + p++; + c++; + } + else + { + /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. + * However, it is deserted now. */ + break; + } + } + else + { + /* convernsion specification */ + c++; + /* Reset. */ + flag = 0; + field_width = 0; + base = 0; + + /* Loop to get full conversion specification. */ + while (('\0' != *c) && (0U == (flag & (uint32_t)kSCANF_DestMask))) + { + switch (*c) + { +#if SCANF_ADVANCED_ENABLE + case '*': + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + /* Match failure. */ + match_failure = true; + break; + } + flag |= (uint32_t)kSCANF_Suppress; + c++; + break; + case 'h': + if (0U != (flag & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + match_failure = true; + break; + } + + if (c[1] == 'h') + { + flag |= (uint32_t)kSCANF_LengthChar; + c++; + } + else + { + flag |= (uint32_t)kSCANF_LengthShortInt; + } + c++; + break; + case 'l': + if (0U != (flag & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + match_failure = true; + break; + } + + if (c[1] == 'l') + { + flag |= (uint32_t)kSCANF_LengthLongLongInt; + c++; + } + else + { + flag |= (uint32_t)kSCANF_LengthLongInt; + } + c++; + break; +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + case 'L': + if (flag & (uint32_t)kSCANF_LengthMask) + { + /* Match failure. */ + match_failure = true; + break; + } + flag |= (uint32_t)kSCANF_LengthLongLongDouble; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case '0': + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + if (0U != field_width) + { + /* Match failure. */ + match_failure = true; + break; + } + do + { + field_width = field_width * 10U + ((uint32_t)*c - (uint32_t)'0'); + c++; + } while ((*c >= '0') && (*c <= '9')); + break; + case 'd': + base = 10; + flag |= (uint32_t)kSCANF_TypeSinged; + flag |= (uint32_t)kSCANF_DestInt; + c++; + break; + case 'u': + base = 10; + flag |= (uint32_t)kSCANF_DestInt; + c++; + break; + case 'o': + base = 8; + flag |= (uint32_t)kSCANF_DestInt; + c++; + break; + case 'x': + case 'X': + base = 16; + flag |= (uint32_t)kSCANF_DestInt; + c++; + break; + case 'i': + base = 0; + flag |= (uint32_t)kSCANF_DestInt; + c++; + break; +#if SCANF_FLOAT_ENABLE + case 'a': + case 'A': + case 'e': + case 'E': + case 'f': + case 'F': + case 'g': + case 'G': + flag |= kSCANF_DestFloat; + c++; + break; +#endif /* SCANF_FLOAT_ENABLE */ + case 'c': + flag |= (uint32_t)kSCANF_DestChar; + if (0U == field_width) + { + field_width = 1; + } + c++; + break; + case 's': + flag |= (uint32_t)kSCANF_DestString; + c++; + break; + default: + /* Match failure. */ + match_failure = true; + break; + } + + /* Match failure. */ + if (match_failure) + { + return (int)nassigned; + } + } + + if (0U == (flag & (uint32_t)kSCANF_DestMask)) + { + /* Format strings are exhausted. */ + return (int)nassigned; + } + + if (0U == field_width) + { + /* Large than length of a line. */ + field_width = 99; + } + + /* Matching strings in input streams and assign to argument. */ + switch (flag & (uint32_t)kSCANF_DestMask) + { + case (uint32_t)kSCANF_DestChar: + s = (const char *)p; + buf = va_arg(args_ptr, char *); + while (((field_width--) > 0U) && ('\0' != *p)) + { + if (0U == (flag & (uint32_t)kSCANF_Suppress)) + { + *buf++ = *p++; + } + else + { + p++; + } + n_decode++; + } + + if ((0U == (flag & (uint32_t)kSCANF_Suppress)) && (s != p)) + { + nassigned++; + } + break; + case (uint32_t)kSCANF_DestString: + n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); + s = p; + buf = va_arg(args_ptr, char *); + while ((field_width-- > 0U) && (*p != '\0') && (*p != ' ') && (*p != '\t') && (*p != '\n') && + (*p != '\r') && (*p != '\v') && (*p != '\f')) + { + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + p++; + } + else + { + *buf++ = *p++; + } + n_decode++; + } + + if ((0U == (flag & (uint32_t)kSCANF_Suppress)) && (s != p)) + { + /* Add NULL to end of string. */ + *buf = '\0'; + nassigned++; + } + break; + case (uint32_t)kSCANF_DestInt: + n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); + s = p; + val = 0; + if ((base == 0U) || (base == 16U)) + { + if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) + { + base = 16U; + if (field_width >= 1U) + { + p += 2; + n_decode += 2U; + field_width -= 2U; + } + } + } + + if (base == 0U) + { + if (s[0] == '0') + { + base = 8U; + } + else + { + base = 10U; + } + } + + neg = 1; + switch (*p) + { + case '-': + neg = -1; + n_decode++; + p++; + field_width--; + break; + case '+': + neg = 1; + n_decode++; + p++; + field_width--; + break; + default: + /* MISRA C-2012 Rule 16.4 */ + break; + } + + while ((field_width-- > 0U) && (*p > '\0')) + { + if ((*p <= '9') && (*p >= '0')) + { + temp = *p - '0' + (char)0; + } + else if ((*p <= 'f') && (*p >= 'a')) + { + temp = *p - 'a' + (char)10; + } + else if ((*p <= 'F') && (*p >= 'A')) + { + temp = *p - 'A' + (char)10; + } + else + { + temp = (char)base; + } + + if ((uint8_t)temp >= base) + { + break; + } + else + { + val = (int32_t)base * val + (int32_t)temp; + } + p++; + n_decode++; + } + val *= neg; + if (0U == (flag & (uint32_t)kSCANF_Suppress)) + { +#if SCANF_ADVANCED_ENABLE + switch (flag & (uint32_t)kSCANF_LengthMask) + { + case (uint32_t)kSCANF_LengthChar: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed char *) = (signed char)val; + } + else + { + *va_arg(args_ptr, unsigned char *) = (unsigned char)val; + } + break; + case (uint32_t)kSCANF_LengthShortInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed short *) = (signed short)val; + } + else + { + *va_arg(args_ptr, unsigned short *) = (unsigned short)val; + } + break; + case (uint32_t)kSCANF_LengthLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed long int *) = (signed long int)val; + } + else + { + *va_arg(args_ptr, unsigned long int *) = (unsigned long int)val; + } + break; + case (uint32_t)kSCANF_LengthLongLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed long long int *) = (signed long long int)val; + } + else + { + *va_arg(args_ptr, unsigned long long int *) = (unsigned long long int)val; + } + break; + default: + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } + break; + } +#else + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(args_ptr, unsigned int *) = (unsigned int)val; + } +#endif /* SCANF_ADVANCED_ENABLE */ + nassigned++; + } + break; +#if SCANF_FLOAT_ENABLE + case (uint32_t)kSCANF_DestFloat: + n_decode += DbgConsole_ScanIgnoreWhiteSpace(&p); + fnum = strtod(p, (char **)&s); + + if ((fnum >= HUGE_VAL) || (fnum <= -HUGE_VAL)) + { + break; + } + + n_decode += (int)(s) - (int)(p); + p = s; + if (0U == (flag & (uint32_t)kSCANF_Suppress)) + { + if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble)) + { + *va_arg(args_ptr, double *) = fnum; + } + else + { + *va_arg(args_ptr, float *) = (float)fnum; + } + nassigned++; + } + break; +#endif /* SCANF_FLOAT_ENABLE */ + default: + /* Match failure. */ + match_failure = true; + break; + } + + /* Match failure. */ + if (match_failure) + { + return (int)nassigned; + } + } + } + return (int)nassigned; +} +#endif /* SDK_DEBUGCONSOLE */ + +/*************Code to support toolchain's printf, scanf *******************************/ +/* These function __write and __read is used to support IAR toolchain to printf and scanf*/ +#if (defined(__ICCARM__)) +#if defined(SDK_DEBUGCONSOLE_UART) +#pragma weak __write +size_t __write(int handle, const unsigned char *buffer, size_t size); +size_t __write(int handle, const unsigned char *buffer, size_t size) +{ + size_t ret; + if (NULL == buffer) + { + /* + * This means that we should flush internal buffers. Since we don't we just return. + * (Remember, "handle" == -1 means that all handles should be flushed.) + */ + ret = (size_t)0; + } + else if ((handle != 1) && (handle != 2)) + { + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. + */ + ret = (size_t)-1; + } + else if (kSerialPort_None == s_debugConsole.serial_port_type) + { + /* Do nothing if the debug UART is not initialized. */ + ret = (size_t)-1; + } + else + { + /* Send data. */ + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], buffer, size); + ret = size; + } + return ret; +} + +#pragma weak __read +size_t __read(int handle, unsigned char *buffer, size_t size); +size_t __read(int handle, unsigned char *buffer, size_t size) +{ + size_t ret; + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + ret = ((size_t)-1); + } + else if (kSerialPort_None == s_debugConsole.serial_port_type) + { + /* Do nothing if the debug UART is not initialized. */ + ret = ((size_t)-1); + } + else + { + /* Receive data. */ + (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], buffer, size); + ret = size; + } + return ret; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* support LPC Xpresso with RedLib */ +#elif (defined(__REDLIB__)) + +#if (defined(SDK_DEBUGCONSOLE_UART)) +int __attribute__((weak)) __sys_write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + + /* Send data. */ + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size); + + return 0; +} + +int __attribute__((weak)) __sys_readc(void) +{ + char tmp; + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + + /* Receive data. */ + s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)&tmp, sizeof(tmp)); + + return tmp; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function fputc and fgetc is used to support KEIL toolchain to printf and scanf*/ +#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) +#if defined(SDK_DEBUGCONSOLE_UART) +#if defined(__CC_ARM) +struct __FILE +{ + int handle; + /* + * Whatever you require here. If the only file you are using is standard output using printf() for debugging, + * no file handling is required. + */ +}; +#endif + +/* FILE is typedef in stdio.h. */ +#pragma weak __stdout +#pragma weak __stdin +FILE __stdout; +FILE __stdin; + +#pragma weak fputc +int fputc(int ch, FILE *f) +{ + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + + /* Send data. */ + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1); + return 1; +} + +#pragma weak fgetc +int fgetc(FILE *f) +{ + char ch; + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + + /* Receive data. */ + s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ch), 1); + return ch; +} + +/* + * Terminate the program, passing a return code back to the user. + * This function may not return. + */ +void _sys_exit(int returncode) +{ + while (1) + { + } +} + +/* + * Writes a character to the output channel. This function is used + * for last-resort error message output. + */ +void _ttywrch(int ch) +{ + char ench = ch; + /* Send data. */ + s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)(&ench), 1); +} + +char *_sys_command_string(char *cmd, int len) +{ + return (cmd); +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function __write_r and __read_r are used to support Xtensa Clang toolchain to printf and scanf */ +#elif defined(__XTENSA__) && defined(__XT_CLANG__) +#if defined(SDK_DEBUGCONSOLE_UART) + +int __attribute__((weak)) _write_r(void *ptr, int handle, char *buffer, int size); +int __attribute__((weak)) _write_r(void *ptr, int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + + /* Send data. */ + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size); + + return size; +} + +int __attribute__((weak)) _read_r(void *ptr, int handle, char *buffer, int size); +int __attribute__((weak)) _read_r(void *ptr, int handle, char *buffer, int size) +{ + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + + /* Receive data. */ + (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size); + return size; +} +#endif /* SDK_DEBUGCONSOLE_UART */ + +/* These function __write and __read is used to support ARM_GCC, KDS, Atollic toolchains to printf and scanf*/ +#elif (defined(__GNUC__)) + +#if ((defined(__GNUC__) && (!defined(__MCUXPRESSO)) && (defined(SDK_DEBUGCONSOLE_UART))) || \ + (defined(__MCUXPRESSO) && (defined(SDK_DEBUGCONSOLE_UART)))) +int __attribute__((weak)) _write(int handle, char *buffer, int size); +int __attribute__((weak)) _write(int handle, char *buffer, int size) +{ + if (NULL == buffer) + { + /* return -1 if error. */ + return -1; + } + + /* This function only writes to "standard out" and "standard err" for all other file handles it returns failure. */ + if ((handle != 1) && (handle != 2)) + { + return -1; + } + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + + /* Send data. */ + (void)s_debugConsole.putChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size); + + return size; +} + +int __attribute__((weak)) _read(int handle, char *buffer, int size); +int __attribute__((weak)) _read(int handle, char *buffer, int size) +{ + /* This function only reads from "standard in", for all other file handles it returns failure. */ + if (handle != 0) + { + return -1; + } + + /* Do nothing if the debug UART is not initialized. */ + if (kSerialPort_None == s_debugConsole.serial_port_type) + { + return -1; + } + + /* Receive data. */ + (void)s_debugConsole.getChar((hal_uart_handle_t)&s_debugConsole.uartHandleBuffer[0], (uint8_t *)buffer, size); + return size; +} +#endif + +#endif /* __ICCARM__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/fsl_debug_console.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/fsl_debug_console.h new file mode 100644 index 0000000000..bd4bb51de5 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/fsl_debug_console.h @@ -0,0 +1,260 @@ +/* + * Copyright 2017-2018, 2020, 2022 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Debug console shall provide input and output functions to scan and print formatted data. + * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier" + * - [flags] :'-', '+', '#', ' ', '0' + * - [width]: number (0,1...) + * - [.precision]: number (0,1...) + * - [length]: do not support + * - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n' + * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier" + * - [*]: is supported. + * - [width]: number (0,1...) + * - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t') + * - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's' + */ + +#ifndef _FSL_DEBUGCONSOLE_H_ +#define _FSL_DEBUGCONSOLE_H_ + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsolelite + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */ +#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */ +#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U /*!< Select SDK version printf, scanf. */ +#define DEBUGCONSOLE_DISABLE 2U /*!< Disable debugconsole function. */ + +/*! @brief Definition to select sdk or toolchain printf, scanf. */ +#ifndef SDK_DEBUGCONSOLE +#define SDK_DEBUGCONSOLE DEBUGCONSOLE_REDIRECT_TO_SDK +#endif + +#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE) +#include +#else +#include +#endif + +/*! @brief Definition to printf the float number. */ +#ifndef PRINTF_FLOAT_ENABLE +#define PRINTF_FLOAT_ENABLE 0U +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! @brief Definition to scanf the float number. */ +#ifndef SCANF_FLOAT_ENABLE +#define SCANF_FLOAT_ENABLE 0U +#endif /* SCANF_FLOAT_ENABLE */ + +/*! @brief Definition to support advanced format specifier for printf. */ +#ifndef PRINTF_ADVANCED_ENABLE +#define PRINTF_ADVANCED_ENABLE 0U +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Definition to support advanced format specifier for scanf. */ +#ifndef SCANF_ADVANCED_ENABLE +#define SCANF_ADVANCED_ENABLE 0U +#endif /* SCANF_ADVANCED_ENABLE */ + +/*! @brief Definition to select redirect toolchain printf, scanf to uart or not. + * + * if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf. + * if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf. + * if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function. + */ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */ +static inline int DbgConsole_Disabled(void) +{ + return -1; +} +#define PRINTF(...) DbgConsole_Disabled() +#define SCANF(...) DbgConsole_Disabled() +#define PUTCHAR(...) DbgConsole_Disabled() +#define GETCHAR() DbgConsole_Disabled() +#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */ +#define PRINTF DbgConsole_Printf +#define SCANF DbgConsole_Scanf +#define PUTCHAR DbgConsole_Putchar +#define GETCHAR DbgConsole_Getchar +#elif SDK_DEBUGCONSOLE == \ + DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ */ +#define PRINTF printf +#define SCANF scanf +#define PUTCHAR putchar +#define GETCHAR getchar +#endif /* SDK_DEBUGCONSOLE */ +/*! @} */ + +/*! @brief serial port type + * + * The serial port type aligned with the definition in serial manager, but please note + * only kSerialPort_Uart can be supported in debug console lite. + */ +#ifndef _SERIAL_PORT_T_ +#define _SERIAL_PORT_T_ +typedef enum _serial_port_type +{ + kSerialPort_None = 0U, /*!< Serial port is none */ + kSerialPort_Uart = 1U, /*!< Serial port UART */ + kSerialPort_UsbCdc, /*!< Serial port USB CDC */ + kSerialPort_Swo, /*!< Serial port SWO */ + kSerialPort_Virtual, /*!< Serial port Virtual */ + kSerialPort_Rpmsg, /*!< Serial port RPMSG */ + kSerialPort_UartDma, /*!< Serial port UART DMA*/ + kSerialPort_SpiMaster, /*!< Serial port SPIMASTER*/ + kSerialPort_SpiSlave, /*!< Serial port SPISLAVE*/ +} serial_port_type_t; +#endif + +/*! + * @addtogroup debugconsolelite + * @{ + */ +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! @name Initialization*/ +/* @{ */ + +#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) +/*! + * @brief Initializes the peripheral used for debug messages. + * + * Call this function to enable debug log messages to be output via the specified peripheral, + * frequency of peripheral source clock, and base address at the specified baud rate. + * After this function has returned, stdout and stdin are connected to the selected peripheral. + * + * @param instance The instance of the module.If the device is kSerialPort_Uart, + * the instance is UART peripheral instance. The UART hardware peripheral + * type is determined by UART adapter. For example, if the instance is 1, + * if the lpuart_adapter.c is added to the current project, the UART periheral + * is LPUART1. + * If the uart_adapter.c is added to the current project, the UART periheral + * is UART1. + * @param baudRate The desired baud rate in bits per second. + * @param device Low level device type for the debug console, can be one of the following. + * @arg kSerialPort_Uart. + * @param clkSrcFreq Frequency of peripheral source clock. + * + * @return Indicates whether initialization was successful or not. + * @retval kStatus_Success Execution successfully + * @retval kStatus_Fail Execution failure + */ +status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq); + +/*! + * @brief De-initializes the peripheral used for debug messages. + * + * Call this function to disable debug log messages to be output via the specified peripheral + * base address and at the specified baud rate. + * + * @return Indicates whether de-initialization was successful or not. + */ +status_t DbgConsole_Deinit(void); + +#else +/*! + * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Init(uint8_t instance, + uint32_t baudRate, + serial_port_type_t device, + uint32_t clkSrcFreq) +{ + (void)instance; + (void)baudRate; + (void)device; + (void)clkSrcFreq; + return (status_t)kStatus_Fail; +} +/*! + * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and + * SDK_DEBUGCONSOLE_UART is not defined. + */ +static inline status_t DbgConsole_Deinit(void) +{ + return (status_t)kStatus_Fail; +} + +#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */ + +#if SDK_DEBUGCONSOLE +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Printf(const char *fmt_s, ...); + +/*! + * @brief Writes formatted output to the standard output stream. + * + * Call this function to write a formatted output to the standard output stream. + * + * @param fmt_s Format control string. + * @param formatStringArg Format arguments. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ +int DbgConsole_Vprintf(const char *fmt_s, va_list formatStringArg); + +/*! + * @brief Writes a character to stdout. + * + * Call this function to write a character to stdout. + * + * @param ch Character to be written. + * @return Returns the character written. + */ +int DbgConsole_Putchar(int ch); + +/*! + * @brief Reads formatted data from the standard input stream. + * + * Call this function to read formatted data from the standard input stream. + * + * @param fmt_s Format control string. + * @return Returns the number of fields successfully converted and assigned. + */ +int DbgConsole_Scanf(char *fmt_s, ...); + +/*! + * @brief Reads a character from standard input. + * + * Call this function to read a character from standard input. + * + * @return Returns the character read. + */ +int DbgConsole_Getchar(void); + +#endif /* SDK_DEBUGCONSOLE */ + +/*! @} */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ +#endif /* _FSL_DEBUGCONSOLE_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_assert_lite_LPC55S69_cm33_core0.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_assert_lite_LPC55S69_cm33_core0.cmake new file mode 100644 index 0000000000..da3cbd7364 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_assert_lite_LPC55S69_cm33_core0.cmake @@ -0,0 +1,10 @@ +include_guard() +message("utility_assert_lite component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_assert.c +) + + +include(utility_debug_console_lite_LPC55S69_cm33_core0) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_assert_lite_LPC55S69_cm33_core1.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_assert_lite_LPC55S69_cm33_core1.cmake new file mode 100644 index 0000000000..2c58f8bd26 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_assert_lite_LPC55S69_cm33_core1.cmake @@ -0,0 +1,10 @@ +include_guard() +message("utility_assert_lite component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_assert.c +) + + +include(utility_debug_console_lite_LPC55S69_cm33_core1) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_debug_console_lite_LPC55S69_cm33_core0.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_debug_console_lite_LPC55S69_cm33_core0.cmake new file mode 100644 index 0000000000..f4333d8018 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_debug_console_lite_LPC55S69_cm33_core0.cmake @@ -0,0 +1,17 @@ +include_guard() +message("utility_debug_console_lite component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_debug_console.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(component_usart_adapter_LPC55S69_cm33_core0) + +include(driver_common_LPC55S69_cm33_core0) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_debug_console_lite_LPC55S69_cm33_core1.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_debug_console_lite_LPC55S69_cm33_core1.cmake new file mode 100644 index 0000000000..4b18b67b81 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/debug_console_lite/utility_debug_console_lite_LPC55S69_cm33_core1.cmake @@ -0,0 +1,17 @@ +include_guard() +message("utility_debug_console_lite component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_debug_console.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(component_usart_adapter_LPC55S69_cm33_core1) + +include(driver_common_LPC55S69_cm33_core1) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_assert.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_assert.c new file mode 100644 index 0000000000..bb9127acdf --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_assert.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_common.h" +#include "fsl_debug_console.h" + +#ifndef NDEBUG +#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__)) +void __aeabi_assert(const char *failedExpr, const char *file, int line) +{ +#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE + PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#else + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line); +#endif + + for (;;) + { + __BKPT(0); + } +} +#elif (defined(__GNUC__)) +#if defined(__REDLIB__) +void __assertion_failed(char *failedExpr) +{ + (void)PRINTF("ASSERT ERROR \" %s \n", failedExpr); + for (;;) + { + __BKPT(0); + } +} +#else +void __assert_func(const char *file, int line, const char *func, const char *failedExpr) +{ + (void)PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, + func); + for (;;) + { + __BKPT(0); + } +} +#endif /* defined(__REDLIB__) */ +#else /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ + +#if (defined(__DSC__) && defined(__CW__)) + +void __msl_assertion_failed(char const *failedExpr, char const *file, char const *func, int line) +{ + PRINTF("\r\nASSERT ERROR\r\n"); + PRINTF(" File : %s\r\n", file); + PRINTF(" Function : %s\r\n", func); /*compiler not support func name yet*/ + PRINTF(" Line : %u\r\n", (uint32_t)line); + PRINTF(" failedExpr: %s\r\n", failedExpr); + asm(DEBUGHLT); +} + +#endif /* (defined(__DSC__) && defined (__CW__)) */ + +#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */ +#endif /* NDEBUG */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_memcpy.S b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_memcpy.S new file mode 100644 index 0000000000..de2b4d674d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_memcpy.S @@ -0,0 +1,279 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .syntax unified + + .text + .thumb + + .align 2 + +#ifndef MSDK_MISC_OVERRIDE_MEMCPY +#define MSDK_MISC_OVERRIDE_MEMCPY 1 +#endif + +/* + This mempcy function is used to replace the GCC newlib function for these purposes: + 1. The newlib nano memcpy function use byte by byte copy, it is slow. + 2. The newlib memcpy function for CM4, CM7, CM33 does't check address alignment, + so it may run to fault when the address is unaligned, and the memory region + is device memory, which does not support unaligned access. + + This function is manually optimized base on assembly result of the c function. + The workflow is: + 1. Return directly if length is 0. + 2. If the source address is not 4-byte aligned, copy the unaligned part first byte by byte. + 3. If the destination address is 4-byte aligned, then copy the 16-byte aligned part first, + copy 16-byte each loop, and then copy 8-byte, 4-byte, 2-byte and 1-byte. + 4. If the destination address is not 4-byte aligned, load source data into register word + by word first, then store to memory based on alignement requirement. For the left part, + copy them byte by byte. + + The source code of the c function is: + + #define __CPY_WORD(dst, src) \ + *(uint32_t *)(dst) = *(uint32_t *)(src); \ + (dst) = ((uint32_t *)dst) + 1; \ + (src) = ((uint32_t *)src) + 1 + + #define __CPY_HWORD(dst, src) \ + *(uint16_t *)(dst) = *(uint16_t *)(src); \ + (dst) = ((uint16_t *)dst) + 1; \ + (src) = ((uint16_t *)src) + 1 + + #define __CPY_BYTE(dst, src) \ + *(uint8_t *)(dst) = *(uint8_t *)(src); \ + (dst) = ((uint8_t *)dst) + 1; \ + (src) = ((uint8_t *)src) + 1 + + void * memcpy(void *restrict dst, const void * restrict src, size_t n) + { + void *ret = dst; + uint32_t tmp; + + if (0 == n) return ret; + + while (((uintptr_t)src & 0x03UL) != 0UL) + { + __CPY_BYTE(dst, src); + n--; + + if (0 == n) return ret; + } + + if (((uintptr_t)dst & 0x03UL) == 0UL) + { + while (n >= 16UL) + { + __CPY_WORD(dst, src); + __CPY_WORD(dst, src); + __CPY_WORD(dst, src); + __CPY_WORD(dst, src); + n-= 16UL; + } + + if ((n & 0x08UL) != 0UL) + { + __CPY_WORD(dst, src); + __CPY_WORD(dst, src); + } + + if ((n & 0x04UL) != 0UL) + { + __CPY_WORD(dst, src); + } + + if ((n & 0x02UL) != 0UL) + { + __CPY_HWORD(dst, src); + } + + if ((n & 0x01UL) != 0UL) + { + __CPY_BYTE(dst, src); + } + } + else + { + if (((uintptr_t)dst & 1UL) == 0UL) + { + while (n >= 4) + { + tmp = *(uint32_t *)src; + src = ((uint32_t *)src) + 1; + + *(volatile uint16_t *)dst = (uint16_t)tmp; + dst = ((uint16_t *)dst) + 1; + *(volatile uint16_t *)dst = (uint16_t)(tmp>>16U); + dst = ((uint16_t *)dst) + 1; + + n-=4; + } + } + else + { + while (n >= 4) + { + tmp = *(uint32_t *)src; + src = ((uint32_t *)src) + 1; + + *(volatile uint8_t *)dst = (uint8_t)tmp; + dst = ((uint8_t *)dst) + 1; + *(volatile uint16_t *)dst = (uint16_t)(tmp>>8U); + dst = ((uint16_t *)dst) + 1; + *(volatile uint8_t *)dst = (uint8_t)(tmp>>24U); + dst = ((uint8_t *)dst) + 1; + n-=4; + } + } + + while (n > 0) + { + __CPY_BYTE(dst, src); + n--; + } + } + + return ret; + } + + The test function is: + + void test_memcpy(uint8_t *dst, const uint8_t * src, size_t n) + { + uint8_t * ds; + uint8_t * de; + const uint8_t *ss; + const uint8_t *se; + uint8_t * ret; + + for (ss = src; ss < src+n; ss++) + { + for (se = ss; se < src + n; se ++) + { + size_t nn = (uintptr_t)se - (uintptr_t)ss; + + for (ds = dst; ds + nn < dst+n; ds++) + { + de = ds + nn; + + memset(dst, 0, n); + + ret = memcpy(ds, ss, nn); + + assert(ret == ds); + + for (const uint8_t *data = dst; data < ds; data++) + { + assert(0 == *data); + } + + for (const uint8_t *data = de; data < dst+n; data++) + { + assert(0 == *data); + } + + assert(memcmp(ds, ss, nn) == 0); + } + } + } + } + + test_memcpy((uint8_t *)0x20240000, (const uint8_t *)0x202C0000, 48); + + */ + +#if MSDK_MISC_OVERRIDE_MEMCPY + + .thumb_func + .align 2 + .global memcpy + .type memcpy, %function + +memcpy: + push {r0, r4, r5, r6, r7, lr} + cmp r2, #0 + beq ret /* If copy size is 0, return. */ + +src_word_unaligned: + ands r3, r1, #3 /* Make src 4-byte align. */ + beq.n src_word_aligned /* src is 4-byte aligned, jump. */ + ldrb r4, [r1], #1 + subs r2, r2, #1 /* n-- */ + strb r4, [r0], #1 + beq.n ret /* n=0, return. */ + b.n src_word_unaligned + +src_word_aligned: + ands r3, r0, #3 /* Check dest 4-byte align. */ + bne.n dst_word_unaligned + +dst_word_aligned: + cmp r2, #16 + blt.n size_ge_8 +size_ge_16: /* size greater or equal than 16, use ldm and stm. */ + subs r2, r2, #16 /* n -= 16 */ + ldmia r1!, { r4, r5, r6, r7 } + cmp r2, #16 + stmia r0!, { r4, r5, r6, r7 } + bcs.n size_ge_16 +size_ge_8: /* size greater or equal than 8 */ + lsls r3, r2, #28 + itt mi + ldmiami r1!, { r4, r5 } + stmiami r0!, { r4, r5 } +size_ge_4: /* size greater or equal than 4 */ + lsls r3, r2, #29 + itt mi + ldrmi r4, [r1], #4 + strmi r4, [r0], #4 +size_ge_2: /* size greater or equal than 2 */ + lsls r3, r2, #30 + itt mi + ldrhmi r4, [r1], #2 + strhmi r4, [r0], #2 +size_ge_1: /* size greater or equal than 1 */ + lsls r3, r2, #31 + itt mi + ldrbmi r4, [r1] + strbmi r4, [r0] + b.n ret + +dst_word_unaligned: + lsls r3, r0, #31 + bmi.n dst_half_word_unaligned +dst_half_word_aligned: + cmp r2, #4 + bcc.n size_lt_4 + ldr r4, [r1], #4 + subs r2, r2, #4 + strh r4, [r0], #2 + lsrs r5, r4, #16 + strh r5, [r0], #2 + b dst_half_word_aligned +dst_half_word_unaligned: + cmp r2, #4 + bcc.n size_lt_4 + ldr r4, [r1], #4 + subs r2, r2, #4 + strb r4, [r0], #1 + lsrs r5, r4, #8 + strh r5, [r0], #2 + lsrs r6, r4, #24 + strb r6, [r0], #1 + b dst_half_word_unaligned +size_lt_4: /* size less than 4. */ + cmp r2, #0 + ittt ne + ldrbne r4, [r1], #1 + strbne r4, [r0], #1 + subne r2, r2, #1 + bne size_lt_4 +ret: + pop {r0, r4, r5, r6, r7, pc} + +#endif /* MSDK_MISC_OVERRIDE_MEMCPY */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_notifier.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_notifier.c new file mode 100644 index 0000000000..7b7c02dc3d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_notifier.c @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_notifier.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*! + * brief Creates a Notifier handle. + * + * param notifierHandle A pointer to the notifier handle. + * param configs A pointer to an array with references to all configurations which is handled by the Notifier. + * param configsNumber Number of configurations. Size of the configuration array. + * param callbacks A pointer to an array of callback configurations. + * If there are no callbacks to register during Notifier initialization, use NULL value. + * param callbacksNumber Number of registered callbacks. Size of the callbacks array. + * param userFunction User function. + * param userData User data passed to user function. + * return An error Code or kStatus_Success. + */ +status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle, + notifier_user_config_t **configs, + uint8_t configsNumber, + notifier_callback_config_t *callbacks, + uint8_t callbacksNumber, + notifier_user_function_t userFunction, + void *userData) +{ + /* Check input parameter - at least one configuration is required and userFunction must exist */ + if ((configs == NULL) || (configsNumber == 0U) || (userFunction == NULL)) + { + return kStatus_Fail; + } + /* Initialize handle structure */ + (void)memset(notifierHandle, 0, sizeof(notifier_handle_t)); + /* Store references to user-defined configurations */ + notifierHandle->configsTable = configs; + notifierHandle->configsNumber = configsNumber; + /* Store references to user-defined callback configurations */ + if (callbacks != NULL) + { + notifierHandle->callbacksTable = callbacks; + notifierHandle->callbacksNumber = callbacksNumber; + /* If all callbacks return success, then the errorCallbackIndex is callbacksNumber */ + notifierHandle->errorCallbackIndex = callbacksNumber; + } + notifierHandle->userFunction = userFunction; + notifierHandle->userData = userData; + + return kStatus_Success; +} + +/*! + * brief Switches the configuration according to a pre-defined structure. + * + * This function sets the system to the target configuration. Before transition, + * the Notifier sends notifications to all callbacks registered to the callback table. + * Callbacks are invoked in the following order: All registered callbacks are notified + * ordered by index in the callbacks array. The same order is used for before and after switch notifications. + * The notifications before the configuration switch can be used to obtain confirmation about + * the change from registered callbacks. If any registered callback denies the + * configuration change, further execution of this function depends on the notifier policy: the + * configuration change is either forced (kNOTIFIER_PolicyForcible) or exited (kNOTIFIER_PolicyAgreement). + * When configuration change is forced, the result of the before switch notifications are ignored. If an + * agreement is required, if any callback returns an error code, further notifications + * before switch notifications are cancelled and all already notified callbacks are re-invoked. + * The index of the callback which returned error code during pre-switch notifications is stored + * (any error codes during callbacks re-invocation are ignored) and NOTIFIER_GetErrorCallback() can be used to get it. + * Regardless of the policies, if any callback returns an error code, an error code indicating in which phase + * the error occurred is returned when NOTIFIER_SwitchConfig() exits. + * param notifierHandle pointer to notifier handle + * param configIndex Index of the target configuration. + * param policy Transaction policy, kNOTIFIER_PolicyAgreement or kNOTIFIER_PolicyForcible. + * + * return An error code or kStatus_Success. + * + */ +status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy) +{ + uint8_t currentStaticCallback = 0U; /* Index to array of statically registered call-backs */ + status_t returnCode = kStatus_Success; /* Function return */ + + notifier_notification_block_t notifyBlock; /* Callback notification block */ + notifier_callback_config_t *callbackConfig; /* Pointer to callback configuration */ + + /* Set errorcallbackindex as callbacksNumber, which means no callback error now */ + notifierHandle->errorCallbackIndex = notifierHandle->callbacksNumber; + + /* Requested configuration availability check */ + if (configIndex >= notifierHandle->configsNumber) + { + return kStatus_OutOfRange; + } + + /* Initialization of local variables from the Notifier handle structure */ + + notifyBlock.policy = policy; + notifyBlock.targetConfig = notifierHandle->configsTable[configIndex]; + notifyBlock.notifyType = kNOTIFIER_NotifyBefore; + + /* From all statically registered call-backs... */ + for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; currentStaticCallback++) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + /* ...notify only those which asked to be called before the configuration switch */ + if (((uint32_t)callbackConfig->callbackType & (uint32_t)kNOTIFIER_CallbackBefore) != 0U) + { + /* In case that call-back returned error code mark it, store the call-back handle and eventually cancel + * the configuration switch */ + if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success) + { + returnCode = (status_t)kStatus_NOTIFIER_ErrorNotificationBefore; + notifierHandle->errorCallbackIndex = currentStaticCallback; + /* If not forcing configuration switch, call all already notified call-backs to revert their state + * as the switch is canceled */ + if (policy != kNOTIFIER_PolicyForcible) + { + break; + } + } + } + } + + /* Set configuration */ + + /* In case that any call-back returned error code and policy doesn't force the configuration set, go to after + * switch call-backs */ + if ((policy == kNOTIFIER_PolicyForcible) || (returnCode == kStatus_Success)) + { + returnCode = notifierHandle->userFunction(notifierHandle->configsTable[configIndex], notifierHandle->userData); + if (returnCode != kStatus_Success) + { + return returnCode; + } + /* Update current configuration index */ + notifierHandle->currentConfigIndex = configIndex; + notifyBlock.notifyType = kNOTIFIER_NotifyAfter; + /* From all statically registered call-backs... */ + for (currentStaticCallback = 0U; currentStaticCallback < notifierHandle->callbacksNumber; + currentStaticCallback++) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + /* ...notify only those which asked to be called after the configuration switch */ + if (((uint32_t)callbackConfig->callbackType & (uint32_t)kNOTIFIER_CallbackAfter) != 0U) + { + /* In case that call-back returned error code mark it and store the call-back handle */ + if (callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData) != kStatus_Success) + { + returnCode = (status_t)kStatus_NOTIFIER_ErrorNotificationAfter; + notifierHandle->errorCallbackIndex = currentStaticCallback; + if (policy != kNOTIFIER_PolicyForcible) + { + break; + } + } + } + } + } + else + { + /* End of unsuccessful switch */ + notifyBlock.notifyType = kNOTIFIER_NotifyRecover; + while (currentStaticCallback-- > 0U) + { + callbackConfig = &(notifierHandle->callbacksTable[currentStaticCallback]); + if (((uint32_t)callbackConfig->callbackType & (uint32_t)kNOTIFIER_CallbackBefore) != 0U) + { + (void)callbackConfig->callback(¬ifyBlock, callbackConfig->callbackData); + } + } + } + + return returnCode; +} + +/*! + * brief This function returns the last failed notification callback. + * + * This function returns an index of the last callback that failed during the configuration switch while + * the last NOTIFIER_SwitchConfig() was called. If the last NOTIFIER_SwitchConfig() call ended successfully + * value equal to callbacks number is returned. The returned value represents an index in the array of + * static call-backs. + * + * param notifierHandle Pointer to the notifier handle + * return Callback Index of the last failed callback or value equal to callbacks count. + */ +uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle) +{ + return notifierHandle->errorCallbackIndex; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_notifier.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_notifier.h new file mode 100644 index 0000000000..d93578c13f --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_notifier.h @@ -0,0 +1,237 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_NOTIFIER_H_ +#define _FSL_NOTIFIER_H_ + +#include "fsl_common.h" +/*! + * @addtogroup notifier + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! + * @brief Notifier error codes. + * + * Used as return value of Notifier functions. + */ +enum _notifier_status +{ + kStatus_NOTIFIER_ErrorNotificationBefore = + MAKE_STATUS(kStatusGroup_NOTIFIER, 0), /*!< An error occurs during send "BEFORE" notification. */ + kStatus_NOTIFIER_ErrorNotificationAfter = + MAKE_STATUS(kStatusGroup_NOTIFIER, 1), /*!< An error occurs during send "AFTER" notification. */ +}; + +/*! + * @brief Notifier policies. + * + * Defines whether the user function execution is forced or not. + * For kNOTIFIER_PolicyForcible, the user function is executed regardless of the callback results, + * while kNOTIFIER_PolicyAgreement policy is used to exit NOTIFIER_SwitchConfig() + * when any of the callbacks returns error code. + * See also NOTIFIER_SwitchConfig() description. + */ +typedef enum _notifier_policy +{ + kNOTIFIER_PolicyAgreement, /*!< NOTIFIER_SwitchConfig() method is exited when any of the callbacks returns error + code. */ + kNOTIFIER_PolicyForcible, /*!< The user function is executed regardless of the results. */ +} notifier_policy_t; + +/*! @brief Notification type. Used to notify registered callbacks */ +typedef enum _notifier_notification_type +{ + kNOTIFIER_NotifyRecover = 0x00U, /*!< Notify IP to recover to previous work state. */ + kNOTIFIER_NotifyBefore = 0x01U, /*!< Notify IP that configuration setting is going to change. */ + kNOTIFIER_NotifyAfter = 0x02U, /*!< Notify IP that configuration setting has been changed. */ +} notifier_notification_type_t; + +/*! + * @brief The callback type, which indicates kinds of notification the callback handles. + * + * Used in the callback configuration structure (notifier_callback_config_t) + * to specify when the registered callback is called during configuration switch initiated by the + * NOTIFIER_SwitchConfig(). + * Callback can be invoked in following situations. + * - Before the configuration switch (Callback return value can affect NOTIFIER_SwitchConfig() + * execution. See the NOTIFIER_SwitchConfig() and notifier_policy_t documentation). + * - After an unsuccessful attempt to switch configuration + * - After a successful configuration switch + */ +typedef enum _notifier_callback_type +{ + kNOTIFIER_CallbackBefore = 0x01U, /*!< Callback handles BEFORE notification. */ + kNOTIFIER_CallbackAfter = 0x02U, /*!< Callback handles AFTER notification. */ + kNOTIFIER_CallbackBeforeAfter = 0x03U, /*!< Callback handles BEFORE and AFTER notification. */ +} notifier_callback_type_t; + +/*! @brief Notifier user configuration type. + * + * Reference of the user defined configuration is stored in an array; the notifier switches between these configurations + * based on this array. + */ +typedef void notifier_user_config_t; + +/*! @brief Notifier user function prototype + * Use this function to execute specific operations in configuration switch. + * Before and after this function execution, different notification is sent to registered callbacks. + * If this function returns any error code, NOTIFIER_SwitchConfig() exits. + * + * @param targetConfig target Configuration. + * @param userData Refers to other specific data passed to user function. + * @return An error code or kStatus_Success. + */ +typedef status_t (*notifier_user_function_t)(notifier_user_config_t *targetConfig, void *userData); + +/*! @brief notification block passed to the registered callback function. */ +typedef struct _notifier_notification_block +{ + notifier_user_config_t *targetConfig; /*!< Pointer to target configuration. */ + notifier_policy_t policy; /*!< Configure transition policy. */ + notifier_notification_type_t notifyType; /*!< Configure notification type. */ +} notifier_notification_block_t; + +/*! + * @brief Callback prototype. + * + * Declaration of a callback. It is common for registered callbacks. + * Reference to function of this type is part of the notifier_callback_config_t callback configuration structure. + * Depending on callback type, function of this prototype is called (see NOTIFIER_SwitchConfig()) + * before configuration switch, after it or in both use cases to notify about + * the switch progress (see notifier_callback_type_t). When called, the type of the notification + * is passed as a parameter along with the reference to the target configuration structure (see + * notifier_notification_block_t) and any data passed during the callback registration. When notified before the + * configuration switch, depending on the configuration switch policy (see notifier_policy_t), the callback may deny the + * execution of the user function by returning an error code different than kStatus_Success (see + * NOTIFIER_SwitchConfig()). + * + * @param notify Notification block. + * @param data Callback data. Refers to the data passed during callback registration. Intended to + * pass any driver or application data such as internal state information. + * @return An error code or kStatus_Success. + */ +typedef status_t (*notifier_callback_t)(notifier_notification_block_t *notify, void *data); + +/*! + * @brief Callback configuration structure. + * + * This structure holds the configuration of callbacks. + * Callbacks of this type are expected to be statically allocated. + * This structure contains the following application-defined data. + * callback - pointer to the callback function + * callbackType - specifies when the callback is called + * callbackData - pointer to the data passed to the callback. + */ +typedef struct _notifier_callback_config +{ + notifier_callback_t callback; /*!< Pointer to the callback function. */ + notifier_callback_type_t callbackType; /*!< Callback type. */ + void *callbackData; /*!< Pointer to the data passed to the callback. */ +} notifier_callback_config_t; + +/*! + * @brief Notifier handle structure. + * + * Notifier handle structure. Contains data necessary for the Notifier proper function. + * Stores references to registered configurations, callbacks, information about their numbers, + * user function, user data, and other internal data. + * NOTIFIER_CreateHandle() must be called to initialize this handle. + */ +typedef struct _notifier_handle +{ + notifier_user_config_t **configsTable; /*!< Pointer to configure table. */ + uint8_t configsNumber; /*!< Number of configurations. */ + notifier_callback_config_t *callbacksTable; /*!< Pointer to callback table. */ + uint8_t callbacksNumber; /*!< Maximum number of callback configurations. */ + uint8_t errorCallbackIndex; /*!< Index of callback returns error. */ + uint8_t currentConfigIndex; /*!< Index of current configuration. */ + notifier_user_function_t userFunction; /*!< User function. */ + void *userData; /*!< User data passed to user function. */ +} notifier_handle_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Creates a Notifier handle. + * + * @param notifierHandle A pointer to the notifier handle. + * @param configs A pointer to an array with references to all configurations which is handled by the Notifier. + * @param configsNumber Number of configurations. Size of the configuration array. + * @param callbacks A pointer to an array of callback configurations. + * If there are no callbacks to register during Notifier initialization, use NULL value. + * @param callbacksNumber Number of registered callbacks. Size of the callbacks array. + * @param userFunction User function. + * @param userData User data passed to user function. + * @return An error Code or kStatus_Success. + */ +status_t NOTIFIER_CreateHandle(notifier_handle_t *notifierHandle, + notifier_user_config_t **configs, + uint8_t configsNumber, + notifier_callback_config_t *callbacks, + uint8_t callbacksNumber, + notifier_user_function_t userFunction, + void *userData); + +/*! + * @brief Switches the configuration according to a pre-defined structure. + * + * This function sets the system to the target configuration. Before transition, + * the Notifier sends notifications to all callbacks registered to the callback table. + * Callbacks are invoked in the following order: All registered callbacks are notified + * ordered by index in the callbacks array. The same order is used for before and after switch notifications. + * The notifications before the configuration switch can be used to obtain confirmation about + * the change from registered callbacks. If any registered callback denies the + * configuration change, further execution of this function depends on the notifier policy: the + * configuration change is either forced (kNOTIFIER_PolicyForcible) or exited (kNOTIFIER_PolicyAgreement). + * When configuration change is forced, the result of the before switch notifications are ignored. If an + * agreement is required, if any callback returns an error code, further notifications + * before switch notifications are cancelled and all already notified callbacks are re-invoked. + * The index of the callback which returned error code during pre-switch notifications is stored + * (any error codes during callbacks re-invocation are ignored) and NOTIFIER_GetErrorCallback() can be used to get it. + * Regardless of the policies, if any callback returns an error code, an error code indicating in which phase + * the error occurred is returned when NOTIFIER_SwitchConfig() exits. + * @param notifierHandle pointer to notifier handle + * @param configIndex Index of the target configuration. + * @param policy Transaction policy, kNOTIFIER_PolicyAgreement or kNOTIFIER_PolicyForcible. + * + * @return An error code or kStatus_Success. + * + */ +status_t NOTIFIER_SwitchConfig(notifier_handle_t *notifierHandle, uint8_t configIndex, notifier_policy_t policy); + +/*! + * @brief This function returns the last failed notification callback. + * + * This function returns an index of the last callback that failed during the configuration switch while + * the last NOTIFIER_SwitchConfig() was called. If the last NOTIFIER_SwitchConfig() call ended successfully + * value equal to callbacks number is returned. The returned value represents an index in the array of + * static call-backs. + * + * @param notifierHandle Pointer to the notifier handle + * @return Callback Index of the last failed callback or value equal to callbacks count. + */ +uint8_t NOTIFIER_GetErrorCallbackIndex(notifier_handle_t *notifierHandle); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @}*/ + +#endif /* _FSL_NOTIFIER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_sbrk.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_sbrk.c new file mode 100644 index 0000000000..55363fd59e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_sbrk.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#if defined(__GNUC__) +#include +#include +#endif + +#if defined(__GNUC__) +/*! + * @brief Function to override ARMGCC default function _sbrk + * + * _sbrk is called by malloc. ARMGCC default _sbrk compares "SP" register and + * heap end, if heap end is larger than "SP", then _sbrk returns error and + * memory allocation failed. This function changes to compare __HeapLimit with + * heap end. + */ +caddr_t _sbrk(int incr); +caddr_t _sbrk(int incr) +{ + extern char end __asm("end"); + extern char heap_limit __asm("__HeapLimit"); + static char *heap_end; + char *prev_heap_end; + caddr_t ret; + + if (heap_end == NULL) + { + heap_end = &end; + } + + prev_heap_end = heap_end; + + if ((uintptr_t)heap_end + (uintptr_t)incr > (uintptr_t)(&heap_limit)) + { + errno = ENOMEM; + + ret = (caddr_t)-1; + } + else + { + heap_end = (char *)((uintptr_t)heap_end + (uintptr_t)incr); + + ret = (caddr_t)prev_heap_end; + } + + return ret; +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_shell.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_shell.c new file mode 100644 index 0000000000..5057050a29 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_shell.c @@ -0,0 +1,1153 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * POSIX getopt for Windows + * Code given out at the 1985 UNIFORUM conference in Dallas. + * + * From std-unix@ut-sally.UUCP (Moderator, John Quarterman) Sun Nov 3 14:34:15 1985 + * Relay-Version: version B 2.10.3 4.3bsd-beta 6/6/85; site gatech.CSNET + * Posting-Version: version B 2.10.2 9/18/84; site ut-sally.UUCP + * Path: gatech!akgua!mhuxv!mhuxt!mhuxr!ulysses!allegra!mit-eddie!genrad!panda!talcott!harvard!seismo!ut-sally!std-unix + * From: std-unix@ut-sally.UUCP (Moderator, John Quarterman) + * Newsgroups: mod.std.unix + * Subject: public domain AT&T getopt source + * Message-ID: <3352@ut-sally.UUCP> + * Date: 3 Nov 85 19:34:15 GMT + * Date-Received: 4 Nov 85 12:25:09 GMT + * Organization: IEEE/P1003 Portable Operating System Environment Committee + * Lines: 91 + * Approved: jsq@ut-sally.UUC + * Here's something you've all been waiting for: the AT&T public domain + * source for getopt(3). It is the code which was given out at the 1985 + * UNIFORUM conference in Dallas. I obtained it by electronic mail + * directly from AT&T. The people there assure me that it is indeed + * in the public domain + * There is no manual page. That is because the one they gave out at + * UNIFORUM was slightly different from the current System V Release 2 + * manual page. The difference apparently involved a note about the + * famous rules 5 and 6, recommending using white space between an option + * and its first argument, and not grouping options that have arguments. + * Getopt itself is currently lenient about both of these things White + * space is allowed, but not mandatory, and the last option in a group can + * have an argument. That particular version of the man page evidently + * has no official existence, and my source at AT&T did not send a copy. + * The current SVR2 man page reflects the actual behavor of this getopt. + * However, I am not about to post a copy of anything licensed by AT&T. + */ + +#include +#include +#include +#include + +#include "fsl_common.h" +#include "fsl_str.h" + +#include "fsl_component_generic_list.h" +#include "fsl_component_serial_manager.h" + +#include "fsl_shell.h" + +/* + * The OSA_USED macro can only be defined when the OSA component is used. + * If the source code of the OSA component does not exist, the OSA_USED cannot be defined. + * OR, If OSA component is not added into project event the OSA source code exists, the OSA_USED + * also cannot be defined. + * The source code path of the OSA component is /components/osa. + * + */ +#if defined(OSA_USED) +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) +#include "fsl_component_common_task.h" +#else +#include "fsl_os_abstraction.h" +#endif + +#endif + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#if defined(OSA_USED) +#define SHELL_WRITEX SHELL_WriteSynchronization +#else +#define SHELL_WRITEX SHELL_Write +#endif + +#if defined(OSA_USED) +#if (defined(USE_RTOS) && (USE_RTOS > 0U)) +static OSA_MUTEX_HANDLE_DEFINE(s_shellMutex); +#define SHELL_MUTEX_CREATE() (void)OSA_MutexCreate(s_shellMutex) +#define SHELL_ENTER_CRITICAL() (void)OSA_MutexLock(s_shellMutex, osaWaitForever_c) +#define SHELL_EXIT_CRITICAL() (void)OSA_MutexUnlock(s_shellMutex) +#else +#define SHELL_MUTEX_CREATE() +#define SHELL_ENTER_CRITICAL() +#define SHELL_EXIT_CRITICAL() +#endif +#else +#ifdef SDK_OS_FREE_RTOS +#include "FreeRTOS.h" +#include "queue.h" +#include "semphr.h" +static QueueHandle_t s_shellMutex; + +#define SHELL_MUTEX_CREATE() s_shellMutex = xSemaphoreCreateMutex() +#define SHELL_ENTER_CRITICAL() (void)xSemaphoreTakeRecursive(s_shellMutex, portMAX_DELAY) +#define SHELL_EXIT_CRITICAL() (void)xSemaphoreGiveRecursive(s_shellMutex) +#else /* BM case*/ +#define SHELL_MUTEX_CREATE() +#define SHELL_ENTER_CRITICAL() +#define SHELL_EXIT_CRITICAL() +#endif +#endif + +#define KEY_ESC (0x1BU) +#define KET_DEL (0x7FU) + +#define SHELL_EVENT_DATA_ARRIVED (1U << 0) +#define SHELL_EVENT_DATA_SENT (1U << 1) + +#define SHELL_SPRINTF_BUFFER_SIZE (64U) + +/*! @brief A type for the handle special key. */ +typedef enum _fun_key_status +{ + kSHELL_Normal = 0U, /*!< Normal key */ + kSHELL_Special = 1U, /*!< Special key */ + kSHELL_Function = 2U, /*!< Function key */ +} fun_key_status_t; + +/*! @brief Data structure for Shell environment. */ +typedef struct _shell_context_handle +{ + list_label_t commandContextListHead; /*!< Command shellContextHandle list queue head */ + serial_handle_t serialHandle; /*!< Serial manager handle */ + uint8_t + serialWriteHandleBuffer[SERIAL_MANAGER_WRITE_HANDLE_SIZE]; /*!< The buffer for serial manager write handle */ + serial_write_handle_t serialWriteHandle; /*!< The serial manager write handle */ + uint8_t serialReadHandleBuffer[SERIAL_MANAGER_READ_HANDLE_SIZE]; /*!< The buffer for serial manager read handle */ + serial_read_handle_t serialReadHandle; /*!< The serial manager read handle */ + char *prompt; /*!< Prompt string */ +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) + common_task_message_t commontaskMsg; /*!< Message for common task */ +#else + uint8_t event[OSA_EVENT_HANDLE_SIZE]; /*!< Event instance */ + uint8_t taskId[OSA_TASK_HANDLE_SIZE]; /*!< Task handle */ +#endif + +#endif + +#endif + char line[SHELL_BUFFER_SIZE]; /*!< Consult buffer */ + char hist_buf[SHELL_HISTORY_COUNT][SHELL_BUFFER_SIZE]; /*!< History buffer*/ + char printBuffer[SHELL_SPRINTF_BUFFER_SIZE]; /*!< Buffer for print */ + uint32_t printLength; /*!< All length has been printed */ + uint16_t hist_current; /*!< Current history command in hist buff*/ + uint16_t hist_count; /*!< Total history command in hist buff*/ + enum _fun_key_status stat; /*!< Special key status */ + uint8_t cmd_num; /*!< Number of user commands */ + uint8_t l_pos; /*!< Total line position */ + uint8_t c_pos; /*!< Current line position */ + volatile uint8_t notificationPost; /*!< The serial manager notification is post */ + uint8_t exit; /*!< Exit Flag*/ + uint8_t printBusy : 1; /*!< Print is busy */ + uint8_t taskBusy : 1; /*!< Task is busy */ +} shell_context_handle_t; + +#if 0 +#define SHELL_STRUCT_OFFSET(type, field) ((size_t) & (((type *)0)->field)) +#define SHEEL_COMMAND_POINTER(node) \ + ((shell_command_t *)(((uint32_t)(node)) - SHELL_STRUCT_OFFSET(shell_command_t, link))) +#else +#define SHEEL_COMMAND_POINTER(node) \ + ((shell_command_t *)(((uint32_t)(node)) - (sizeof(shell_command_t) - sizeof(list_element_t)))) +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +static shell_status_t SHELL_HelpCommand(shell_handle_t shellHandle, int32_t argc, char **argv); /*!< help command */ + +static shell_status_t SHELL_ExitCommand(shell_handle_t shellHandle, int32_t argc, char **argv); /*!< exit command */ + +static int32_t SHELL_ParseLine(const char *cmd, uint32_t len, char *argv[]); /*!< parse line command */ + +static int32_t SHELL_StringCompare(const char *str1, const char *str2, int32_t count); /*!< compare string command */ + +static void SHELL_ProcessCommand(shell_context_handle_t *shellContextHandle, const char *cmd); /*!< process a command */ + +static void SHELL_GetHistoryCommand(shell_context_handle_t *shellContextHandle, + uint8_t hist_pos); /*!< get commands history */ + +static void SHELL_AutoComplete(shell_context_handle_t *shellContextHandle); /*!< auto complete command */ + +static shell_status_t SHELL_GetChar(shell_context_handle_t *shellContextHandle, + uint8_t *ch); /*!< get a char from communication interface */ + +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) +static void SHELL_Task(void *param); /*!< Shell task*/ +#endif + +/******************************************************************************* + * Variables + ******************************************************************************/ + +static SHELL_COMMAND_DEFINE(help, "\r\n\"help\": List all the registered commands\r\n", SHELL_HelpCommand, 0); +static SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0); + +static char s_paramBuffer[SHELL_BUFFER_SIZE]; + +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) +#if defined(OSA_USED) +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) +#else +/* + * \brief Defines the serial manager task's stack + */ +static OSA_TASK_DEFINE(SHELL_Task, SHELL_TASK_PRIORITY, 1, SHELL_TASK_STACK_SIZE, false); +#endif +#endif /* OSA_USED */ +#endif /* SHELL_NON_BLOCKING_MODE */ +/******************************************************************************* + * Code + ******************************************************************************/ + +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) +static void SHELL_SerialManagerRxCallback(void *callbackParam, + serial_manager_callback_message_t *message, + serial_manager_status_t status) +{ + shell_context_handle_t *shellHandle; + + assert(callbackParam); + assert(message); + + shellHandle = (shell_context_handle_t *)callbackParam; + + if (0U == shellHandle->notificationPost) + { + shellHandle->notificationPost = 1U; +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) + shellHandle->commontaskMsg.callback = SHELL_Task; + shellHandle->commontaskMsg.callbackParam = shellHandle; + (void)COMMON_TASK_post_message(&shellHandle->commontaskMsg); +#else + (void)OSA_EventSet((osa_event_handle_t)shellHandle->event, SHELL_EVENT_DATA_ARRIVED); +#endif + +#else + SHELL_Task(shellHandle); +#endif + } +} +#endif + +static void SHELL_WriteBuffer(char *buffer, int32_t *indicator, char val, int len) +{ + shell_context_handle_t *shellContextHandle; + int i = 0; + shellContextHandle = (shell_context_handle_t *)(void *)buffer; + + for (i = 0; i < len; i++) + { + if ((*indicator + 1) >= (int32_t)SHELL_SPRINTF_BUFFER_SIZE) + { +#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1))) + if (NULL == shellContextHandle->serialHandle) + { + for (uint32_t index = 0; index < ((uint32_t)*indicator); index++) + { + (void)putchar(shellContextHandle->printBuffer[index]); + } + } + else +#endif + { + (void)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle, + (uint8_t *)shellContextHandle->printBuffer, (uint32_t)*indicator); + } + + shellContextHandle->printLength += (uint32_t)*indicator; + *indicator = 0; + } + + shellContextHandle->printBuffer[*indicator] = val; + (*indicator)++; + } +} + +static int SHELL_Sprintf(void *buffer, const char *formatString, va_list ap) +{ + shell_context_handle_t *shellContextHandle; + uint32_t length; + shellContextHandle = (shell_context_handle_t *)buffer; + + length = (uint32_t)StrFormatPrintf(formatString, ap, (char *)buffer, SHELL_WriteBuffer); + shellContextHandle->printLength += length; + return (int32_t)length; +} + +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) +static void SHELL_Task(void *param) +#else +void SHELL_Task(shell_handle_t shellHandle) +#endif +{ +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)param; +#else + shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle; +#endif + uint8_t ch; + + if (NULL != shellContextHandle) + { + uint32_t osaCurrentSr = 0U; + + osaCurrentSr = DisableGlobalIRQ(); + shellContextHandle->notificationPost = 0U; + if (shellContextHandle->taskBusy > 0U) + { + EnableGlobalIRQ(osaCurrentSr); + return; + } + shellContextHandle->taskBusy = 1U; + EnableGlobalIRQ(osaCurrentSr); +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) +#else + osa_event_flags_t ev = 0; + + do + { + if (KOSA_StatusSuccess == OSA_EventWait((osa_event_handle_t)shellContextHandle->event, osaEventFlagsAll_c, + 0U, osaWaitForever_c, &ev)) + { + if (0U != (ev & SHELL_EVENT_DATA_ARRIVED)) +#endif + +#endif + +#endif + { + shellContextHandle->notificationPost = 0U; + do + { + if ((bool)shellContextHandle->exit) + { + if (shellContextHandle->serialReadHandle != NULL) + { + (void)SerialManager_CloseReadHandle(shellContextHandle->serialReadHandle); + shellContextHandle->serialReadHandle = NULL; + } + if (shellContextHandle->serialWriteHandle != NULL) + { + (void)SerialManager_CloseWriteHandle(shellContextHandle->serialWriteHandle); + shellContextHandle->serialWriteHandle = NULL; + } + break; + } + if (kStatus_SHELL_Success != (shell_status_t)SHELL_GetChar(shellContextHandle, &ch)) + { + /* If error occurred when getting a char, exit the task and waiting the new data arriving. */ + break; + } + + /* Special key */ + if (ch == KEY_ESC) + { + shellContextHandle->stat = kSHELL_Special; + continue; + } + else if (shellContextHandle->stat == kSHELL_Special) + { + /* Function key */ + if ((char)ch == '[') + { + shellContextHandle->stat = kSHELL_Function; + continue; + } + shellContextHandle->stat = kSHELL_Normal; + } + else if (shellContextHandle->stat == kSHELL_Function) + { + shellContextHandle->stat = kSHELL_Normal; + + switch ((char)ch) + { + /* History operation here */ + case 'A': /* Up key */ + SHELL_GetHistoryCommand(shellContextHandle, (uint8_t)shellContextHandle->hist_current); + if (shellContextHandle->hist_current < (shellContextHandle->hist_count - 1U)) + { + shellContextHandle->hist_current++; + } + break; + case 'B': /* Down key */ + SHELL_GetHistoryCommand(shellContextHandle, (uint8_t)shellContextHandle->hist_current); + if (shellContextHandle->hist_current > 0U) + { + shellContextHandle->hist_current--; + } + break; + case 'D': /* Left key */ + if ((bool)shellContextHandle->c_pos) + { + (void)SHELL_WRITEX(shellContextHandle, "\b", 1); + shellContextHandle->c_pos--; + } + break; + case 'C': /* Right key */ + if (shellContextHandle->c_pos < shellContextHandle->l_pos) + { + (void)SHELL_WRITEX(shellContextHandle, + &shellContextHandle->line[shellContextHandle->c_pos], 1); + shellContextHandle->c_pos++; + } + break; + default: + /* MISRA C-2012 Rule 16.4 */ + break; + } + continue; + } + /* Handle tab key */ + else if ((char)ch == '\t') + { +#if SHELL_AUTO_COMPLETE + /* Move the cursor to the beginning of line */ + uint32_t i; + for (i = 0; i < (uint32_t)shellContextHandle->c_pos; i++) + { + (void)SHELL_WRITEX(shellContextHandle, "\b", 1); + } + /* Do auto complete */ + SHELL_AutoComplete(shellContextHandle); + /* Move position to end */ + shellContextHandle->l_pos = (uint8_t)strlen(shellContextHandle->line); + shellContextHandle->c_pos = shellContextHandle->l_pos; +#endif + continue; + } + /* Handle backspace key */ + else if ((ch == KET_DEL) || ((char)ch == '\b')) + { + /* There must be at last one char */ + if (shellContextHandle->c_pos == 0U) + { + continue; + } + + shellContextHandle->l_pos--; + shellContextHandle->c_pos--; + + if (shellContextHandle->l_pos > shellContextHandle->c_pos) + { + (void)memmove(&shellContextHandle->line[shellContextHandle->c_pos], + &shellContextHandle->line[shellContextHandle->c_pos + 1U], + (uint32_t)shellContextHandle->l_pos - (uint32_t)shellContextHandle->c_pos); + shellContextHandle->line[shellContextHandle->l_pos] = '\0'; + (void)SHELL_WRITEX(shellContextHandle, "\b", 1); + (void)SHELL_WRITEX(shellContextHandle, &shellContextHandle->line[shellContextHandle->c_pos], + strlen(&shellContextHandle->line[shellContextHandle->c_pos])); + (void)SHELL_WRITEX(shellContextHandle, " \b", 3); + + /* Reset position */ + uint32_t i; + for (i = (uint32_t)shellContextHandle->c_pos; i <= (uint32_t)shellContextHandle->l_pos; i++) + { + (void)SHELL_WRITEX(shellContextHandle, "\b", 1); + } + } + else /* Normal backspace operation */ + { + (void)SHELL_WRITEX(shellContextHandle, "\b \b", 3); + shellContextHandle->line[shellContextHandle->l_pos] = '\0'; + } + continue; + } + else + { + /* MISRA C-2012 Rule 15.7 */ + } + + /* Input too long */ + if (shellContextHandle->l_pos >= (SHELL_BUFFER_SIZE - 1U)) + { + shellContextHandle->l_pos = 0U; + } + + /* Handle end of line, break */ + if (((char)ch == '\r') || ((char)ch == '\n')) + { + static char endoflinechar = '\0'; + + if (((uint8_t)endoflinechar != 0U) && ((uint8_t)endoflinechar != ch)) + { + continue; + } + else + { + endoflinechar = (char)ch; + /* Print new line. */ + (void)SHELL_WRITEX(shellContextHandle, "\r\n", 2U); + /* If command line is not NULL, will start process it. */ + if (0U != strlen(shellContextHandle->line)) + { + SHELL_ProcessCommand(shellContextHandle, shellContextHandle->line); + } + /* Print prompt. */ + (void)SHELL_WRITEX(shellContextHandle, shellContextHandle->prompt, + strlen(shellContextHandle->prompt)); + /* Reset all params */ + shellContextHandle->c_pos = shellContextHandle->l_pos = 0; + shellContextHandle->hist_current = 0; + (void)memset(shellContextHandle->line, 0, sizeof(shellContextHandle->line)); + continue; + } + } + + /* Normal character */ + if (shellContextHandle->c_pos < shellContextHandle->l_pos) + { + (void)memmove(&shellContextHandle->line[shellContextHandle->c_pos + 1U], + &shellContextHandle->line[shellContextHandle->c_pos], + (uint32_t)shellContextHandle->l_pos - (uint32_t)shellContextHandle->c_pos); + shellContextHandle->line[shellContextHandle->c_pos] = (char)ch; + (void)SHELL_WRITEX(shellContextHandle, &shellContextHandle->line[shellContextHandle->c_pos], + strlen(&shellContextHandle->line[shellContextHandle->c_pos])); + /* Move the cursor to new position */ + uint32_t i; + for (i = (uint32_t)shellContextHandle->c_pos; i < (uint32_t)shellContextHandle->l_pos; i++) + { + (void)SHELL_WRITEX(shellContextHandle, "\b", 1); + } + } + else + { + shellContextHandle->line[shellContextHandle->l_pos] = (char)ch; + (void)SHELL_WRITEX(shellContextHandle, &shellContextHandle->line[shellContextHandle->l_pos], 1); + } + + ch = 0; + shellContextHandle->l_pos++; + shellContextHandle->c_pos++; + } while (0U == shellContextHandle->exit); + } +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) +#else + } + } while (1U == gUseRtos_c); /* USE_RTOS = 0 for BareMetal and 1 for OS */ +#endif + +#endif + +#endif + osaCurrentSr = DisableGlobalIRQ(); + shellContextHandle->taskBusy = 0U; + EnableGlobalIRQ(osaCurrentSr); + } +} + +static shell_status_t SHELL_HelpCommand(shell_handle_t shellHandle, int32_t argc, char **argv) +{ + shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle; + shell_command_t *shellCommandContextHandle; + list_element_handle_t p = LIST_GetHead(&shellContextHandle->commandContextListHead); + + while (p != NULL) + { + shellCommandContextHandle = SHEEL_COMMAND_POINTER(p); + if ((shellCommandContextHandle->pcHelpString != NULL) && (bool)strlen(shellCommandContextHandle->pcHelpString)) + { + (void)SHELL_WRITEX(shellContextHandle, shellCommandContextHandle->pcHelpString, + strlen(shellCommandContextHandle->pcHelpString)); + } + + p = LIST_GetNext(p); + } + return kStatus_SHELL_Success; +} + +static shell_status_t SHELL_ExitCommand(shell_handle_t shellHandle, int32_t argc, char **argv) +{ + shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle; + /* Skip warning */ + (void)SHELL_WRITEX(shellContextHandle, "\r\nSHELL exited\r\n", strlen("\r\nSHELL exited\r\n")); + shellContextHandle->exit = (uint8_t) true; + return kStatus_SHELL_Success; +} + +static void SHELL_ProcessCommand(shell_context_handle_t *shellContextHandle, const char *cmd) +{ + shell_command_t *tmpCommand = NULL; + const char *tmpCommandString; + int32_t argc; + char *argv[SHELL_BUFFER_SIZE] = {0}; + list_element_handle_t p; + uint8_t flag = 1; + uint8_t tmpCommandLen; + uint8_t tmpLen; + uint8_t i = 0; + + tmpLen = (uint8_t)strlen(cmd); + argc = SHELL_ParseLine(cmd, tmpLen, argv); + + if ((argc > 0)) + { + p = LIST_GetHead(&shellContextHandle->commandContextListHead); + while (p != NULL) + { + tmpCommand = SHEEL_COMMAND_POINTER(p); + tmpCommandString = tmpCommand->pcCommand; + tmpCommandLen = (uint8_t)strlen(tmpCommandString); + /* Compare with space or end of string */ + if ((cmd[tmpCommandLen] == ' ') || (cmd[tmpCommandLen] == (char)0x00)) + { + if (SHELL_StringCompare(tmpCommandString, argv[0], (int32_t)tmpCommandLen) == 0) + { + /* support commands with optional number of parameters */ + if (tmpCommand->cExpectedNumberOfParameters == (uint8_t)SHELL_IGNORE_PARAMETER_COUNT) + { + flag = 0; + } + else if ((tmpCommand->cExpectedNumberOfParameters == 0U) && (argc == 1)) + { + flag = 0; + } + else if (tmpCommand->cExpectedNumberOfParameters > 0U) + { + if ((argc - 1) == (int32_t)tmpCommand->cExpectedNumberOfParameters) + { + flag = 0; + } + } + else + { + flag = 1; + } + break; + } + } + p = LIST_GetNext(p); + } + if (NULL == p) + { + tmpCommand = NULL; + } + } + + if ((tmpCommand != NULL) && (flag == 1U)) + { + (void)SHELL_Write( + shellContextHandle, + "\r\nIncorrect command parameter(s). Enter \"help\" to view a list of available commands.\r\n\r\n", + strlen( + "\r\nIncorrect command parameter(s). Enter \"help\" to view a list of available commands.\r\n\r\n")); + } + else if (tmpCommand != NULL) + { + tmpLen = (uint8_t)strlen(cmd); + /* Compare with last command. Push back to history buffer if different */ + if (tmpLen != (uint8_t)SHELL_StringCompare(cmd, shellContextHandle->hist_buf[0], (int32_t)strlen(cmd))) + { + for (i = SHELL_HISTORY_COUNT - 1U; i > 0U; i--) + { + (void)memset(shellContextHandle->hist_buf[i], (int)'\0', SHELL_BUFFER_SIZE); + tmpLen = (uint8_t)strlen(shellContextHandle->hist_buf[i - 1U]); + (void)memcpy(shellContextHandle->hist_buf[i], shellContextHandle->hist_buf[i - 1U], tmpLen); + } + (void)memset(shellContextHandle->hist_buf[0], (int)'\0', SHELL_BUFFER_SIZE); + tmpLen = (uint8_t)strlen(cmd); + (void)memcpy(shellContextHandle->hist_buf[0], cmd, tmpLen); + if (shellContextHandle->hist_count < SHELL_HISTORY_COUNT) + { + shellContextHandle->hist_count++; + } + } + (void)tmpCommand->pFuncCallBack(shellContextHandle, argc, argv); + } + else + { + (void)SHELL_Write( + shellContextHandle, + "\r\nCommand not recognized. Enter 'help' to view a list of available commands.\r\n\r\n", + strlen("\r\nCommand not recognized. Enter 'help' to view a list of available commands.\r\n\r\n")); + } +} + +static void SHELL_GetHistoryCommand(shell_context_handle_t *shellContextHandle, uint8_t hist_pos) +{ + uint32_t i; + uint32_t tmp; + + if (shellContextHandle->hist_buf[0][0] == '\0') + { + shellContextHandle->hist_current = 0; + return; + } + +#if 0 /*hist_pos is passed from hist_current. And hist_current is only changed in case 'A'/'B',as hist_count is 3 \ + most, it can't be more than 3 */ + if (hist_pos >= SHELL_HISTORY_COUNT) + { + hist_pos = SHELL_HISTORY_COUNT - 1U; + } +#endif + + tmp = strlen(shellContextHandle->line); + /* Clear current if have */ + if (tmp > 0U) + { + (void)memset(shellContextHandle->line, (int)'\0', tmp); + for (i = 0U; i < tmp; i++) + { + (void)SHELL_WRITEX(shellContextHandle, "\b \b", 3); + } + } + + shellContextHandle->l_pos = (uint8_t)strlen(shellContextHandle->hist_buf[hist_pos]); + shellContextHandle->c_pos = shellContextHandle->l_pos; + (void)memcpy(shellContextHandle->line, shellContextHandle->hist_buf[hist_pos], shellContextHandle->l_pos); + (void)SHELL_WRITEX(shellContextHandle, shellContextHandle->hist_buf[hist_pos], + strlen(shellContextHandle->hist_buf[hist_pos])); +} + +static void SHELL_AutoComplete(shell_context_handle_t *shellContextHandle) +{ + int32_t minLen; + list_element_handle_t p; + shell_command_t *tmpCommand = NULL; + const char *namePtr; + const char *cmdName; + + minLen = (int32_t)SHELL_BUFFER_SIZE; + namePtr = NULL; + + /* Empty tab, list all commands */ + if (shellContextHandle->line[0] == '\0') + { + (void)SHELL_HelpCommand(shellContextHandle, 0, NULL); + return; + } + + (void)SHELL_WRITEX(shellContextHandle, "\r\n", 2); + + /* Do auto complete */ + p = LIST_GetHead(&shellContextHandle->commandContextListHead); + while (p != NULL) + { + tmpCommand = SHEEL_COMMAND_POINTER(p); + cmdName = tmpCommand->pcCommand; + if (SHELL_StringCompare(shellContextHandle->line, cmdName, (int32_t)strlen(shellContextHandle->line)) == 0) + { + /* Show possible matches */ + (void)SHELL_Printf(shellContextHandle, "%s ", cmdName); + if (minLen > ((int32_t)strlen(cmdName))) + { + namePtr = cmdName; + minLen = (int32_t)strlen(namePtr); + } + } + p = LIST_GetNext(p); + } + /* Auto complete string */ + if (namePtr != NULL) + { + (void)memcpy(shellContextHandle->line, namePtr, (uint32_t)minLen); + } + SHELL_PrintPrompt(shellContextHandle); + (void)SHELL_WRITEX(shellContextHandle, shellContextHandle->line, strlen(shellContextHandle->line)); + return; +} + +static int32_t SHELL_StringCompare(const char *str1, const char *str2, int32_t count) +{ + while ((bool)(count--)) + { + if (*str1++ != *str2++) + { + return (int32_t)(*(str1 - 1) - *(str2 - 1)); + } + } + return 0; +} + +static int32_t SHELL_ParseLine(const char *cmd, uint32_t len, char *argv[]) +{ + uint32_t argc; + char *p; + uint32_t position; + + /* Init params */ + (void)memset(s_paramBuffer, (int)'\0', len + 1U); + (void)memcpy(s_paramBuffer, cmd, len); + + p = s_paramBuffer; + position = 0; + argc = 0; + + while (position < len) + { + /* Skip all blanks */ + while ((position < len) && ((char)(*p) == ' ')) + { + *p = '\0'; + p++; + position++; + } + + if (position >= len) + { + break; + } + + /* Process begin of a string */ + if (*p == '"') + { + p++; + position++; + argv[argc] = p; + argc++; + /* Skip this string */ + while ((*p != '"') && (position < len)) + { + p++; + position++; + } + /* Skip '"' */ + *p = '\0'; + p++; + position++; + } + else /* Normal char */ + { + argv[argc] = p; + argc++; + while (((char)*p != ' ') && (position < len)) + { + p++; + position++; + } + } + } + return (int32_t)argc; +} + +static shell_status_t SHELL_GetChar(shell_context_handle_t *shellContextHandle, uint8_t *ch) +{ + shell_status_t status; + +#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1))) + if (NULL == shellContextHandle->serialHandle) + { + int ret; + ret = getchar(); + if (ret > 0) + { + *ch = (uint8_t)ret; + status = kStatus_SHELL_Success; + } + else + { + status = kStatus_SHELL_Error; + } + } + else +#endif + { +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + uint32_t length = 0; + + (void)SerialManager_TryRead(shellContextHandle->serialReadHandle, ch, 1, &length); + + if (length > 0U) + { + status = kStatus_SHELL_Success; + } + else + { + status = kStatus_SHELL_Error; + } +#else + status = (shell_status_t)SerialManager_ReadBlocking(shellContextHandle->serialReadHandle, ch, 1); +#endif + } + + return status; +} + +shell_status_t SHELL_Init(shell_handle_t shellHandle, serial_handle_t serialHandle, char *prompt) +{ + shell_context_handle_t *shellContextHandle; + serial_manager_status_t status = kStatus_SerialManager_Error; + (void)status; + + assert(shellHandle); +#if !(!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1))) + assert(serialHandle); +#endif + assert(prompt); + assert(SHELL_HANDLE_SIZE >= sizeof(shell_context_handle_t)); + + shellContextHandle = (shell_context_handle_t *)shellHandle; + + /* memory set for shellHandle */ + (void)memset(shellHandle, 0, SHELL_HANDLE_SIZE); + +#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1))) + if (NULL == serialHandle) + { + } + else +#endif + { +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + +#if defined(OSA_USED) + +#if (defined(SHELL_USE_COMMON_TASK) && (SHELL_USE_COMMON_TASK > 0U)) + (void)COMMON_TASK_init(); +#else + if (KOSA_StatusSuccess != OSA_EventCreate((osa_event_handle_t)shellContextHandle->event, 1U)) + { + return kStatus_SHELL_Error; + } + + if (KOSA_StatusSuccess != + OSA_TaskCreate((osa_task_handle_t)shellContextHandle->taskId, OSA_TASK(SHELL_Task), shellContextHandle)) + { + return kStatus_SHELL_Error; + } +#endif + +#endif + +#endif + } + + shellContextHandle->prompt = prompt; + shellContextHandle->serialHandle = serialHandle; + +#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1))) + if (NULL == serialHandle) + { + } + else +#endif + { + shellContextHandle->serialWriteHandle = (serial_write_handle_t)&shellContextHandle->serialWriteHandleBuffer[0]; + status = SerialManager_OpenWriteHandle(shellContextHandle->serialHandle, shellContextHandle->serialWriteHandle); + assert(kStatus_SerialManager_Success == status); + + shellContextHandle->serialReadHandle = (serial_read_handle_t)&shellContextHandle->serialReadHandleBuffer[0]; + status = SerialManager_OpenReadHandle(shellContextHandle->serialHandle, shellContextHandle->serialReadHandle); + assert(kStatus_SerialManager_Success == status); + +#if (defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + status = SerialManager_InstallRxCallback(shellContextHandle->serialReadHandle, SHELL_SerialManagerRxCallback, + shellContextHandle); + assert(kStatus_SerialManager_Success == status); +#endif + (void)status; + } + + (void)SHELL_RegisterCommand(shellContextHandle, SHELL_COMMAND(help)); + (void)SHELL_RegisterCommand(shellContextHandle, SHELL_COMMAND(exit)); + SHELL_MUTEX_CREATE(); + (void)SHELL_Write(shellContextHandle, "\r\nCopyright 2022 NXP\r\n", strlen("\r\nCopyright 2022 NXP\r\n")); + SHELL_PrintPrompt(shellContextHandle); + + return kStatus_SHELL_Success; +} + +shell_status_t SHELL_RegisterCommand(shell_handle_t shellHandle, shell_command_t *shellCommand) +{ + shell_context_handle_t *shellContextHandle = (shell_context_handle_t *)shellHandle; + assert(shellHandle); + assert(shellCommand); + + /* memory set for shellHandle */ + (void)memset(&shellCommand->link, 0, sizeof(shellCommand->link)); + + (void)LIST_AddTail(&shellContextHandle->commandContextListHead, &shellCommand->link); + + return kStatus_SHELL_Success; +} + +shell_status_t SHELL_UnregisterCommand(shell_command_t *shellCommand) +{ + assert(shellCommand); + + (void)LIST_RemoveElement(&shellCommand->link); + + /* memory set for shellHandle */ + (void)memset(&shellCommand->link, 0, sizeof(shellCommand->link)); + + return kStatus_SHELL_Success; +} + +shell_status_t SHELL_Write(shell_handle_t shellHandle, const char *buffer, uint32_t length) +{ + shell_context_handle_t *shellContextHandle; + uint32_t primask; + shell_status_t status; + + assert(shellHandle); + assert(buffer); + + if (!(bool)length) + { + return kStatus_SHELL_Success; + } + + shellContextHandle = (shell_context_handle_t *)shellHandle; + + primask = DisableGlobalIRQ(); + if ((bool)shellContextHandle->printBusy) + { + EnableGlobalIRQ(primask); + return kStatus_SHELL_Error; + } + shellContextHandle->printBusy = 1U; + EnableGlobalIRQ(primask); +#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1))) + if (NULL == shellContextHandle->serialHandle) + { + status = kStatus_SHELL_Success; + for (uint32_t index = 0; index < length; index++) + { + (void)putchar(buffer[index]); + } + } + else +#endif + { + status = (shell_status_t)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle, (uint8_t *)buffer, + length); + } + + shellContextHandle->printBusy = 0U; + + return status; +} + +int SHELL_Printf(shell_handle_t shellHandle, const char *formatString, ...) +{ + shell_context_handle_t *shellContextHandle; + uint32_t length; + uint32_t primask; + va_list ap; + + assert(shellHandle); + assert(formatString); + + shellContextHandle = (shell_context_handle_t *)shellHandle; + + primask = DisableGlobalIRQ(); + if ((bool)shellContextHandle->printBusy) + { + EnableGlobalIRQ(primask); + return -1; + } + shellContextHandle->printBusy = 1U; + EnableGlobalIRQ(primask); + + va_start(ap, formatString); + + shellContextHandle->printLength = 0U; + length = (uint32_t)SHELL_Sprintf(shellHandle, formatString, ap); +#if (!defined(SDK_DEBUGCONSOLE_UART) && (defined(SDK_DEBUGCONSOLE) && (SDK_DEBUGCONSOLE != 1))) + if (NULL == shellContextHandle->serialHandle) + { + for (uint32_t index = 0; index < length; index++) + { + (void)putchar(shellContextHandle->printBuffer[index]); + } + } + else +#endif + { + (void)SerialManager_WriteBlocking(shellContextHandle->serialWriteHandle, + (uint8_t *)shellContextHandle->printBuffer, length); + } + va_end(ap); + + shellContextHandle->printBusy = 0U; + return (int32_t)shellContextHandle->printLength; +} + +shell_status_t SHELL_WriteSynchronization(shell_handle_t shellHandle, const char *buffer, uint32_t length) +{ + shell_status_t status; + + assert(SHELL_checkRunningInIsr() == false); + + SHELL_ENTER_CRITICAL(); + status = SHELL_Write(shellHandle, buffer, length); + + SHELL_EXIT_CRITICAL(); + + return status; +} + +int SHELL_PrintfSynchronization(shell_handle_t shellHandle, const char *formatString, ...) +{ + shell_status_t status; + shell_context_handle_t *shellContextHandle; + va_list ap; + uint32_t length; + + assert(SHELL_checkRunningInIsr() == false); + + shellContextHandle = (shell_context_handle_t *)shellHandle; + + SHELL_ENTER_CRITICAL(); + va_start(ap, formatString); + length = (uint32_t)SHELL_Sprintf(shellHandle, formatString, ap); + + status = SHELL_Write(shellHandle, (const char *)shellContextHandle->printBuffer, length); + va_end(ap); + SHELL_EXIT_CRITICAL(); + + return (status == kStatus_SHELL_Success) ? (int)length : 0; +} +void SHELL_ChangePrompt(shell_handle_t shellHandle, char *prompt) +{ + shell_context_handle_t *shellContextHandle; + assert(shellHandle); + assert(prompt); + + shellContextHandle = (shell_context_handle_t *)shellHandle; + + shellContextHandle->prompt = prompt; + SHELL_PrintPrompt(shellContextHandle); +} + +void SHELL_PrintPrompt(shell_handle_t shellHandle) +{ + shell_context_handle_t *shellContextHandle; + assert(shellHandle); + + shellContextHandle = (shell_context_handle_t *)shellHandle; + + (void)SHELL_Write(shellContextHandle, "\r\n", 2U); + (void)SHELL_Write(shellContextHandle, shellContextHandle->prompt, strlen(shellContextHandle->prompt)); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_shell.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_shell.h new file mode 100644 index 0000000000..313df41311 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/fsl_shell.h @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __FSL_SHELL_H__ +#define __FSL_SHELL_H__ + +/*! + * @addtogroup SHELL + * @{ + */ + +#include "fsl_common.h" +#include "fsl_component_serial_manager.h" +#include "fsl_component_generic_list.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Whether use non-blocking mode. */ +#ifndef SHELL_NON_BLOCKING_MODE +#define SHELL_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE +#endif + +/*! @brief Macro to set on/off auto-complete feature. */ +#define SHELL_AUTO_COMPLETE (1U) + +/*! @brief Macro to set console buffer size. */ +#ifndef SHELL_BUFFER_SIZE +#define SHELL_BUFFER_SIZE (64U) +#endif + +/*! @brief Macro to set maximum arguments in command. */ +#define SHELL_MAX_ARGS (8U) + +/*! @brief Macro to set maximum count of history commands. */ +#ifndef SHELL_HISTORY_COUNT +#define SHELL_HISTORY_COUNT (3U) +#endif + +/*! @brief Macro to bypass arguments check */ +#define SHELL_IGNORE_PARAMETER_COUNT (0xFF) + +/*! @brief The handle size of the shell module. It is the sum of the SHELL_HISTORY_COUNT * SHELL_BUFFER_SIZE + + * SHELL_BUFFER_SIZE + SERIAL_MANAGER_READ_HANDLE_SIZE + SERIAL_MANAGER_WRITE_HANDLE_SIZE*/ +#define SHELL_HANDLE_SIZE \ + (160U + SHELL_HISTORY_COUNT * SHELL_BUFFER_SIZE + SHELL_BUFFER_SIZE + SERIAL_MANAGER_READ_HANDLE_SIZE + \ + SERIAL_MANAGER_WRITE_HANDLE_SIZE) + +/*! @brief Macro to determine whether use common task. */ +#ifndef SHELL_USE_COMMON_TASK +#define SHELL_USE_COMMON_TASK (0U) +#endif + +/*! @brief Macro to set shell task priority. */ +#ifndef SHELL_TASK_PRIORITY +#define SHELL_TASK_PRIORITY (2U) +#endif + +/*! @brief Macro to set shell task stack size. */ +#ifndef SHELL_TASK_STACK_SIZE +#define SHELL_TASK_STACK_SIZE (1000U) +#endif + +/*! @brief Shell status */ +typedef enum _shell_status +{ + kStatus_SHELL_Success = kStatus_Success, /*!< Success */ + kStatus_SHELL_Error = MAKE_STATUS(kStatusGroup_SHELL, 1), /*!< Failed */ + kStatus_SHELL_OpenWriteHandleFailed = MAKE_STATUS(kStatusGroup_SHELL, 2), /*!< Open write handle failed */ + kStatus_SHELL_OpenReadHandleFailed = MAKE_STATUS(kStatusGroup_SHELL, 3), /*!< Open read handle failed */ +} shell_status_t; + +/*! @brief The handle of the shell module */ +typedef void *shell_handle_t; + +/*! @brief User command function prototype. */ +typedef shell_status_t (*cmd_function_t)(shell_handle_t shellHandle, int32_t argc, char **argv); + +/*! @brief User command data configuration structure. */ +typedef struct _shell_command +{ + const char *pcCommand; /*!< The command that is executed. For example "help". It must be all lower case. */ + char *pcHelpString; /*!< String that describes how to use the command. It should start with the command itself, + and end with "\r\n". For example "help: Returns a list of all the commands\r\n". */ + const cmd_function_t + pFuncCallBack; /*!< A pointer to the callback function that returns the output generated by the command. */ + uint8_t cExpectedNumberOfParameters; /*!< Commands expect a fixed number of parameters, which may be zero. */ + list_element_t link; /*!< link of the element */ +} shell_command_t; + +/*! + * @brief Defines the shell handle + * + * This macro is used to define a 4 byte aligned shell handle. + * Then use "(shell_handle_t)name" to get the shell handle. + * + * The macro should be global and could be optional. You could also define shell handle by yourself. + * + * This is an example, + * @code + * SHELL_HANDLE_DEFINE(shellHandle); + * @endcode + * + * @param name The name string of the shell handle. + */ +#define SHELL_HANDLE_DEFINE(name) uint32_t name[((SHELL_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))] + +#if defined(__ICCARM__) +/* disable misra 19.13 */ +_Pragma("diag_suppress=Pm120") +#endif +/*! + * @brief Defines the shell command structure + * + * This macro is used to define the shell command structure #shell_command_t. + * And then uses the macro SHELL_COMMAND to get the command structure pointer. + * The macro should not be used in any function. + * + * This is a example, + * @code + * SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0); + * SHELL_RegisterCommand(s_shellHandle, SHELL_COMMAND(exit)); + * @endcode + * + * @param command The command string of the command. The double quotes do not need. Such as exit for "exit", + * help for "Help", read for "read". + * @param descriptor The description of the command is used for showing the command usage when "help" is typing. + * @param callback The callback of the command is used to handle the command line when the input command is matched. + * @param paramCount The max parameter count of the current command. + */ +#define SHELL_COMMAND_DEFINE(command, descriptor, callback, paramCount) \ + \ + shell_command_t g_shellCommand##command = { \ + (#command), (descriptor), (callback), (paramCount), {0}, \ + } + +/*! + * @brief Gets the shell command pointer + * + * This macro is used to get the shell command pointer. The macro should not be used before the macro + * SHELL_COMMAND_DEFINE is used. + * + * @param command The command string of the command. The double quotes do not need. Such as exit for "exit", + * help for "Help", read for "read". + */ +#define SHELL_COMMAND(command) &g_shellCommand##command + +#if defined(__ICCARM__) + _Pragma("diag_default=Pm120") +#endif + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) + extern "C" +{ +#endif /* _cplusplus */ + + /*! + * @name Shell functional operation + * @{ + */ + + /*! + * @brief Initializes the shell module + * + * This function must be called before calling all other Shell functions. + * Call operation the Shell commands with user-defined settings. + * The example below shows how to set up the Shell and + * how to call the SHELL_Init function by passing in these parameters. + * This is an example. + * @code + * static SHELL_HANDLE_DEFINE(s_shellHandle); + * SHELL_Init((shell_handle_t)s_shellHandle, (serial_handle_t)s_serialHandle, "Test@SHELL>"); + * @endcode + * @param shellHandle Pointer to point to a memory space of size #SHELL_HANDLE_SIZE allocated by the caller. + * The handle should be 4 byte aligned, because unaligned access doesn't be supported on some devices. + * You can define the handle in the following two ways: + * #SHELL_HANDLE_DEFINE(shellHandle); + * or + * uint32_t shellHandle[((SHELL_HANDLE_SIZE + sizeof(uint32_t) - 1U) / sizeof(uint32_t))]; + * @param serialHandle The serial manager module handle pointer. + * @param prompt The string prompt pointer of Shell. Only the global variable can be passed. + * @retval kStatus_SHELL_Success The shell initialization succeed. + * @retval kStatus_SHELL_Error An error occurred when the shell is initialized. + * @retval kStatus_SHELL_OpenWriteHandleFailed Open the write handle failed. + * @retval kStatus_SHELL_OpenReadHandleFailed Open the read handle failed. + */ + shell_status_t SHELL_Init(shell_handle_t shellHandle, serial_handle_t serialHandle, char *prompt); + + /*! + * @brief Registers the shell command + * + * This function is used to register the shell command by using the command configuration shell_command_config_t. + * This is a example, + * @code + * SHELL_COMMAND_DEFINE(exit, "\r\n\"exit\": Exit program\r\n", SHELL_ExitCommand, 0); + * SHELL_RegisterCommand(s_shellHandle, SHELL_COMMAND(exit)); + * @endcode + * @param shellHandle The shell module handle pointer. + * @param shellCommand The command element. + * @retval kStatus_SHELL_Success Successfully register the command. + * @retval kStatus_SHELL_Error An error occurred. + */ + shell_status_t SHELL_RegisterCommand(shell_handle_t shellHandle, shell_command_t * shellCommand); + + /*! + * @brief Unregisters the shell command + * + * This function is used to unregister the shell command. + * + * @param shellCommand The command element. + * @retval kStatus_SHELL_Success Successfully unregister the command. + */ + shell_status_t SHELL_UnregisterCommand(shell_command_t * shellCommand); + + /*! + * @brief Sends data to the shell output stream. + * + * This function is used to send data to the shell output stream. + * + * @param shellHandle The shell module handle pointer. + * @param buffer Start address of the data to write. + * @param length Length of the data to write. + * @retval kStatus_SHELL_Success Successfully send data. + * @retval kStatus_SHELL_Error An error occurred. + */ + shell_status_t SHELL_Write(shell_handle_t shellHandle, const char *buffer, uint32_t length); + + /*! + * @brief Writes formatted output to the shell output stream. + * + * Call this function to write a formatted output to the shell output stream. + * + * @param shellHandle The shell module handle pointer. + * + * @param formatString Format string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ + int SHELL_Printf(shell_handle_t shellHandle, const char *formatString, ...); + /*! + * @brief Sends data to the shell output stream with OS synchronization. + * + * This function is used to send data to the shell output stream with OS synchronization, note the function could + * not be called in ISR. + * + * @param shellHandle The shell module handle pointer. + * @param buffer Start address of the data to write. + * @param length Length of the data to write. + * @retval kStatus_SHELL_Success Successfully send data. + * @retval kStatus_SHELL_Error An error occurred. + */ + shell_status_t SHELL_WriteSynchronization(shell_handle_t shellHandle, const char *buffer, uint32_t length); + + /*! + * @brief Writes formatted output to the shell output stream with OS synchronization. + * + * Call this function to write a formatted output to the shell output stream with OS synchronization, note the + * function could not be called in ISR. + * + * @param shellHandle The shell module handle pointer. + * + * @param formatString Format string. + * @return Returns the number of characters printed or a negative value if an error occurs. + */ + int SHELL_PrintfSynchronization(shell_handle_t shellHandle, const char *formatString, ...); + /*! + * @brief Change shell prompt. + * + * Call this function to change shell prompt. + * + * @param shellHandle The shell module handle pointer. + * + * @param prompt The string which will be used for command prompt + * @return NULL. + */ + void SHELL_ChangePrompt(shell_handle_t shellHandle, char *prompt); + + /*! + * @brief Print shell prompt. + * + * Call this function to print shell prompt. + * + * @param shellHandle The shell module handle pointer. + * + * @return NULL. + */ + void SHELL_PrintPrompt(shell_handle_t shellHandle); + +/*! + * @brief The task function for Shell. + * The task function for Shell; The function should be polled by upper layer. + * This function does not return until Shell command exit was called. + * + * @param shellHandle The shell module handle pointer. + */ +#if !(defined(SHELL_NON_BLOCKING_MODE) && (SHELL_NON_BLOCKING_MODE > 0U)) + void SHELL_Task(shell_handle_t shellHandle); +#endif + + /*! + * @brief Check if code is running in ISR. + * + * This function is used to check if code running in ISR. + * + * @retval TRUE if code runing in ISR. + */ + static inline bool SHELL_checkRunningInIsr(void) + { +#if (defined(__DSC__) && defined(__CW__)) + return !(isIRQAllowed()); +#elif defined(__GIC_PRIO_BITS) + return (0x13 == (__get_CPSR() & CPSR_M_Msk)); +#elif defined(__get_IPSR) + return (0U != __get_IPSR()); +#else + return false; +#endif + } + + /* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __FSL_SHELL_H__ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/incbin/fsl_incbin.S b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/incbin/fsl_incbin.S new file mode 100644 index 0000000000..99114bcb6d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/incbin/fsl_incbin.S @@ -0,0 +1,37 @@ +;/* +; * Copyright 2020 NXP +; * +; * All rights reserved. +; * +; * SPDX-License-Identifier: BSD-3-Clause +; */ + +#if defined(__CC_ARM) + + AREA core1_code, DATA, READONLY, PREINIT_ARRAY, ALIGN=3 + EXPORT core1_image_start + EXPORT core1_image_end +core1_image_start + INCBIN core1_image.bin +core1_image_end + END + +#elif defined(__GNUC__) || defined(__ARMCC_VERSION) + + .section .core1_code, "ax" @progbits @preinit_array + .global core1_image_start + .type core1_image_start, %object + .align 4 +core1_image_start: + .incbin "core1_image.bin" + .global core1_image_end + .type core1_image_end, %object +core1_image_end: + .global core1_image_size + .type core1_image_size, %object + .align 4 +core1_image_size: + .int core1_image_end - core1_image_start + .end + +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/incbin/utility_incbin_LPC55S69_cm33_core0.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/incbin/utility_incbin_LPC55S69_cm33_core0.cmake new file mode 100644 index 0000000000..02f1702e2c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/incbin/utility_incbin_LPC55S69_cm33_core0.cmake @@ -0,0 +1,8 @@ +include_guard() +message("utility_incbin component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_incbin.S +) + + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/str/fsl_str.c b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/str/fsl_str.c new file mode 100644 index 0000000000..1c0dccf905 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/str/fsl_str.c @@ -0,0 +1,1638 @@ +/* + * Copyright 2017, 2020 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include +#include +#include +#include /* MISRA C-2012 Rule 22.9 */ +#include "fsl_str.h" +#include "fsl_debug_console_conf.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief The overflow value.*/ +#ifndef HUGE_VAL +#define HUGE_VAL (99.e99) +#endif /* HUGE_VAL */ + +#ifndef MAX_FIELD_WIDTH +#define MAX_FIELD_WIDTH 99U +#endif + +#if PRINTF_ADVANCED_ENABLE +/*! @brief Specification modifier flags for printf. */ +enum _debugconsole_printf_flag +{ + kPRINTF_Minus = 0x01U, /*!< Minus FLag. */ + kPRINTF_Plus = 0x02U, /*!< Plus Flag. */ + kPRINTF_Space = 0x04U, /*!< Space Flag. */ + kPRINTF_Zero = 0x08U, /*!< Zero Flag. */ + kPRINTF_Pound = 0x10U, /*!< Pound Flag. */ + kPRINTF_LengthChar = 0x20U, /*!< Length: Char Flag. */ + kPRINTF_LengthShortInt = 0x40U, /*!< Length: Short Int Flag. */ + kPRINTF_LengthLongInt = 0x80U, /*!< Length: Long Int Flag. */ + kPRINTF_LengthLongLongInt = 0x100U, /*!< Length: Long Long Int Flag. */ +}; +#endif /* PRINTF_ADVANCED_ENABLE */ + +/*! @brief Specification modifier flags for scanf. */ +enum _debugconsole_scanf_flag +{ + kSCANF_Suppress = 0x2U, /*!< Suppress Flag. */ + kSCANF_DestMask = 0x7cU, /*!< Destination Mask. */ + kSCANF_DestChar = 0x4U, /*!< Destination Char Flag. */ + kSCANF_DestString = 0x8U, /*!< Destination String FLag. */ + kSCANF_DestSet = 0x10U, /*!< Destination Set Flag. */ + kSCANF_DestInt = 0x20U, /*!< Destination Int Flag. */ + kSCANF_DestFloat = 0x30U, /*!< Destination Float Flag. */ + kSCANF_LengthMask = 0x1f00U, /*!< Length Mask Flag. */ +#if SCANF_ADVANCED_ENABLE + kSCANF_LengthChar = 0x100U, /*!< Length Char Flag. */ + kSCANF_LengthShortInt = 0x200U, /*!< Length ShortInt Flag. */ + kSCANF_LengthLongInt = 0x400U, /*!< Length LongInt Flag. */ + kSCANF_LengthLongLongInt = 0x800U, /*!< Length LongLongInt Flag. */ +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + kSCANF_LengthLongLongDouble = 0x1000U, /*!< Length LongLongDuoble Flag. */ +#endif /*PRINTF_FLOAT_ENABLE */ + kSCANF_TypeSinged = 0x2000U, /*!< TypeSinged Flag. */ +}; + +/*! @brief Keil: suppress ellipsis warning in va_arg usage below. */ +#if defined(__CC_ARM) +#pragma diag_suppress 1256 +#endif /* __CC_ARM */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Scanline function which ignores white spaces. + * + * @param[in] s The address of the string pointer to update. + * @return String without white spaces. + */ +static uint32_t ScanIgnoreWhiteSpace(const char **s); + +/*! + * @brief Converts a radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] neg Polarity of the number. + * @param[in] radix The radix to be converted to. + * @param[in] use_caps Used to identify %x/X output format. + + * @return Length of the converted string. + */ +static int32_t ConvertRadixNumToString(char *numstr, void *nump, unsigned int neg, unsigned int radix, bool use_caps); + +#if PRINTF_FLOAT_ENABLE +/*! + * @brief Converts a floating radix number to a string and return its length. + * + * @param[in] numstr Converted string of the number. + * @param[in] nump Pointer to the number. + * @param[in] radix The radix to be converted to. + * @param[in] precision_width Specify the precision width. + + * @return Length of the converted string. + */ +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width); + +#endif /* PRINTF_FLOAT_ENABLE */ + +/*************Code for process formatted data*******************************/ +#if PRINTF_ADVANCED_ENABLE +static uint8_t PrintGetSignChar(long long int ival, uint32_t flags_used, char *schar) +{ + uint8_t len = 1U; + if (ival < 0) + { + *schar = '-'; + } + else + { + if (0U != (flags_used & (uint32_t)kPRINTF_Plus)) + { + *schar = '+'; + } + else if (0U != (flags_used & (uint32_t)kPRINTF_Space)) + { + *schar = ' '; + } + else + { + *schar = '\0'; + len = 0U; + } + } + return len; +} +#endif /* PRINTF_ADVANCED_ENABLE */ + +static uint32_t PrintGetWidth(const char **p, va_list *ap) +{ + uint32_t field_width = 0; + uint8_t done = 0U; + char c; + + while (0U == done) + { + c = *(++(*p)); + if ((c >= '0') && (c <= '9')) + { + (field_width) = ((field_width)*10U) + ((uint32_t)c - (uint32_t)'0'); + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + (field_width) = (uint32_t)va_arg(*ap, uint32_t); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --(*p); + done = 1U; + } + } + return field_width; +} + +static uint32_t PrintGetPrecision(const char **s, va_list *ap, bool *valid_precision_width) +{ + const char *p = *s; + uint32_t precision_width = 6U; + uint8_t done = 0U; + +#if PRINTF_ADVANCED_ENABLE + if (NULL != valid_precision_width) + { + *valid_precision_width = false; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + if (*++p == '.') + { + /* Must get precision field width, if present. */ + precision_width = 0U; + done = 0U; + while (0U == done) + { + char c = *++p; + if ((c >= '0') && (c <= '9')) + { + precision_width = (precision_width * 10U) + ((uint32_t)c - (uint32_t)'0'); +#if PRINTF_ADVANCED_ENABLE + if (NULL != valid_precision_width) + { + *valid_precision_width = true; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } +#if PRINTF_ADVANCED_ENABLE + else if (c == '*') + { + precision_width = (uint32_t)va_arg(*ap, uint32_t); + if (NULL != valid_precision_width) + { + *valid_precision_width = true; + } + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + /* We've gone one char too far. */ + --p; + done = 1U; + } + } + } + else + { + /* We've gone one char too far. */ + --p; + } + *s = p; + return precision_width; +} + +static uint32_t PrintIsobpu(const char c) +{ + uint32_t ret = 0U; + if ((c == 'o') || (c == 'b') || (c == 'p') || (c == 'u')) + { + ret = 1U; + } + return ret; +} + +static uint32_t PrintIsdi(const char c) +{ + uint32_t ret = 0U; + if ((c == 'd') || (c == 'i')) + { + ret = 1U; + } + return ret; +} + +static void PrintOutputdifFobpu(uint32_t flags_used, + uint32_t field_width, + uint32_t vlen, + char schar, + char *vstrp, + printfCb cb, + char *buf, + int32_t *count) +{ +#if PRINTF_ADVANCED_ENABLE + /* Do the ZERO pad. */ + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if ('\0' != schar) + { + cb(buf, count, schar, 1); + schar = '\0'; + } + cb(buf, count, '0', (int)field_width - (int)vlen); + vlen = field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + if ('\0' != schar) + { + cb(buf, count, schar, 1); + schar = '\0'; + } + } + } + /* The string was built in reverse order, now display in correct order. */ + if ('\0' != schar) + { + cb(buf, count, schar, 1); + } +#else + cb(buf, count, ' ', (int)field_width - (int)vlen); +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*vstrp)) + { + cb(buf, count, *vstrp--, 1); + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ +} + +static void PrintOutputxX(uint32_t flags_used, + uint32_t field_width, + uint32_t vlen, + bool use_caps, + char *vstrp, + printfCb cb, + char *buf, + int32_t *count) +{ +#if PRINTF_ADVANCED_ENABLE + uint8_t dschar = 0; + if (0U != (flags_used & (uint32_t)kPRINTF_Zero)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + dschar = 1U; + } + cb(buf, count, '0', (int)field_width - (int)vlen); + vlen = field_width; + } + else + { + if (0U == (flags_used & (uint32_t)kPRINTF_Minus)) + { + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + vlen += 2U; + } + cb(buf, count, ' ', (int)field_width - (int)vlen); + if (0U != (flags_used & (uint32_t)kPRINTF_Pound)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + dschar = 1U; + } + } + } + + if ((0U != (flags_used & (uint32_t)kPRINTF_Pound)) && (0U == dschar)) + { + cb(buf, count, '0', 1); + cb(buf, count, (use_caps ? 'X' : 'x'), 1); + vlen += 2U; + } +#else + cb(buf, count, ' ', (int)field_width - (int)vlen); +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*vstrp)) + { + cb(buf, count, *vstrp--, 1); + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_Minus)) + { + cb(buf, count, ' ', (int)field_width - (int)vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ +} + +static uint32_t PrintIsfF(const char c) +{ + uint32_t ret = 0U; + if ((c == 'f') || (c == 'F')) + { + ret = 1U; + } + return ret; +} + +static uint32_t PrintIsxX(const char c) +{ + uint32_t ret = 0U; + if ((c == 'x') || (c == 'X')) + { + ret = 1U; + } + return ret; +} + +#if PRINTF_ADVANCED_ENABLE +static uint32_t PrintCheckFlags(const char **s) +{ + const char *p = *s; + /* First check for specification modifier flags. */ + uint32_t flags_used = 0U; + bool done = false; + while (false == done) + { + switch (*++p) + { + case '-': + flags_used |= (uint32_t)kPRINTF_Minus; + break; + case '+': + flags_used |= (uint32_t)kPRINTF_Plus; + break; + case ' ': + flags_used |= (uint32_t)kPRINTF_Space; + break; + case '0': + flags_used |= (uint32_t)kPRINTF_Zero; + break; + case '#': + flags_used |= (uint32_t)kPRINTF_Pound; + break; + default: + /* We've gone one char too far. */ + --p; + done = true; + break; + } + } + *s = p; + return flags_used; +} +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE +/* + * Check for the length modifier. + */ +static uint32_t PrintGetLengthFlag(const char **s) +{ + const char *p = *s; + /* First check for specification modifier flags. */ + uint32_t flags_used = 0U; + + switch (/* c = */ *++p) + { + case 'h': + if (*++p != 'h') + { + flags_used |= (uint32_t)kPRINTF_LengthShortInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthChar; + } + break; + case 'l': + if (*++p != 'l') + { + flags_used |= (uint32_t)kPRINTF_LengthLongInt; + --p; + } + else + { + flags_used |= (uint32_t)kPRINTF_LengthLongLongInt; + } + break; + default: + /* we've gone one char too far */ + --p; + break; + } + *s = p; + return flags_used; +} +#else +static void PrintFilterLengthFlag(const char **s) +{ + const char *p = *s; + char ch; + + do + { + ch = *++p; + } while ((ch == 'h') || (ch == 'l')); + + *s = --p; +} +#endif /* PRINTF_ADVANCED_ENABLE */ + +static uint8_t PrintGetRadixFromobpu(const char c) +{ + uint8_t radix; + + if (c == 'o') + { + radix = 8U; + } + else if (c == 'b') + { + radix = 2U; + } + else if (c == 'p') + { + radix = 16U; + } + else + { + radix = 10U; + } + return radix; +} + +static uint32_t ScanIsWhiteSpace(const char c) +{ + uint32_t ret = 0U; + if ((c == ' ') || (c == '\t') || (c == '\n') || (c == '\r') || (c == '\v') || (c == '\f')) + { + ret = 1U; + } + return ret; +} + +static uint32_t ScanIgnoreWhiteSpace(const char **s) +{ + uint32_t count = 0U; + char c; + + c = **s; + while (1U == ScanIsWhiteSpace(c)) + { + count++; + (*s)++; + c = **s; + } + return count; +} + +static int32_t ConvertRadixNumToString(char *numstr, void *nump, unsigned int neg, unsigned int radix, bool use_caps) +{ +#if PRINTF_ADVANCED_ENABLE + long long int a; + long long int b; + long long int c; + + unsigned long long int ua; + unsigned long long int ub; + unsigned long long int uc; + unsigned long long int uc_param; +#else + int a; + int b; + int c; + + unsigned int ua; + unsigned int ub; + unsigned int uc; + unsigned int uc_param; +#endif /* PRINTF_ADVANCED_ENABLE */ + + int32_t nlen; + char *nstrp; + + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + +#if !(PRINTF_ADVANCED_ENABLE > 0) + neg = 0U; +#endif + +#if PRINTF_ADVANCED_ENABLE + a = 0; + b = 0; + c = 0; + ua = 0ULL; + ub = 0ULL; + uc = 0ULL; + uc_param = 0ULL; +#else + a = 0; + b = 0; + c = 0; + ua = 0U; + ub = 0U; + uc = 0U; + uc_param = 0U; +#endif /* PRINTF_ADVANCED_ENABLE */ + + (void)a; + (void)b; + (void)c; + (void)ua; + (void)ub; + (void)uc; + (void)uc_param; + (void)neg; + /* + * Fix MISRA issue: CID 15972928 (#15 of 15): MISRA C-2012 Control Flow Expressions (MISRA C-2012 Rule 14.3) + * misra_c_2012_rule_14_3_violation: Execution cannot reach this statement: a = *((int *)nump); + */ +#if PRINTF_ADVANCED_ENABLE + if (0U != neg) + { +#if PRINTF_ADVANCED_ENABLE + a = *(long long int *)nump; +#else + a = *(int *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (a == 0) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (a != 0) + { +#if PRINTF_ADVANCED_ENABLE + b = (long long int)a / (long long int)radix; + c = (long long int)a - ((long long int)b * (long long int)radix); + if (c < 0) + { + uc = (unsigned long long int)c; + uc_param = ~uc; + c = (long long int)uc_param + 1 + (long long int)'0'; + } +#else + b = (int)a / (int)radix; + c = (int)a - ((int)b * (int)radix); + if (c < 0) + { + uc = (unsigned int)c; + uc_param = ~uc; + c = (int)uc_param + 1 + (int)'0'; + } +#endif /* PRINTF_ADVANCED_ENABLE */ + else + { + c = c + (int)'0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { +#if PRINTF_ADVANCED_ENABLE + ua = *(unsigned long long int *)nump; +#else + ua = *(unsigned int *)nump; +#endif /* PRINTF_ADVANCED_ENABLE */ + if (ua == 0U) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + while (ua != 0U) + { +#if PRINTF_ADVANCED_ENABLE + ub = (unsigned long long int)ua / (unsigned long long int)radix; + uc = (unsigned long long int)ua - ((unsigned long long int)ub * (unsigned long long int)radix); +#else + ub = ua / (unsigned int)radix; + uc = ua - (ub * (unsigned int)radix); +#endif /* PRINTF_ADVANCED_ENABLE */ + + if (uc < 10U) + { + uc = uc + (unsigned int)'0'; + } + else + { + uc = uc - 10U + (unsigned int)(use_caps ? 'A' : 'a'); + } + ua = ub; + *nstrp++ = (char)uc; + ++nlen; + } + } + return nlen; +} + +#if PRINTF_FLOAT_ENABLE +static int32_t ConvertFloatRadixNumToString(char *numstr, void *nump, int32_t radix, uint32_t precision_width) +{ + int32_t a; + int32_t b; + int32_t c; + int32_t i; + uint32_t uc; + double fa; + double dc; + double fb; + double r; + double fractpart; + double intpart; + + int32_t nlen; + char *nstrp; + nlen = 0; + nstrp = numstr; + *nstrp++ = '\0'; + r = *(double *)nump; + if (0.0 == r) + { + *nstrp = '0'; + ++nlen; + return nlen; + } + fractpart = modf((double)r, (double *)&intpart); + /* Process fractional part. */ + for (i = 0; i < (int32_t)precision_width; i++) + { + fractpart *= (double)radix; + } + if (r >= (double)0.0) + { + fa = fractpart + (double)0.5; + if (fa >= pow((double)10, (double)precision_width)) + { + intpart++; + } + } + else + { + fa = fractpart - (double)0.5; + if (fa <= -pow((double)10, (double)precision_width)) + { + intpart--; + } + } + for (i = 0; i < (int32_t)precision_width; i++) + { + fb = fa / (double)radix; + dc = (fa - (double)(long long int)fb * (double)radix); + c = (int32_t)dc; + if (c < 0) + { + uc = (uint32_t)c; + uc = ~uc; + c = (int32_t)uc; + c += (int32_t)1; + c += (int32_t)'0'; + } + else + { + c = c + '0'; + } + fa = fb; + *nstrp++ = (char)c; + ++nlen; + } + *nstrp++ = (char)'.'; + ++nlen; + a = (int32_t)intpart; + if (a == 0) + { + *nstrp++ = '0'; + ++nlen; + } + else + { + while (a != 0) + { + b = (int32_t)a / (int32_t)radix; + c = (int32_t)a - ((int32_t)b * (int32_t)radix); + if (c < 0) + { + uc = (uint32_t)c; + uc = ~uc; + c = (int32_t)uc; + c += (int32_t)1; + c += (int32_t)'0'; + } + else + { + c = c + '0'; + } + a = b; + *nstrp++ = (char)c; + ++nlen; + } + } + return nlen; +} +#endif /* PRINTF_FLOAT_ENABLE */ + +/*! + * brief This function outputs its parameters according to a formatted string. + * + * note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * param[in] fmt Format string for printf. + * param[in] ap Arguments to printf. + * param[in] buf pointer to the buffer + * param cb print callback function pointer + * + * return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb) +{ + /* va_list ap; */ + const char *p; + char c; + + char vstr[33]; + char *vstrp = NULL; + int32_t vlen = 0; + + int32_t count = 0; + + uint32_t field_width; + uint32_t precision_width; + char *sval; + int32_t cval; + bool use_caps; + unsigned int radix = 0; + +#if PRINTF_ADVANCED_ENABLE + uint32_t flags_used; + char schar; + long long int ival; + unsigned long long int uval = 0; +#define STR_FORMAT_PRINTF_UVAL_TYPE unsigned long long int +#define STR_FORMAT_PRINTF_IVAL_TYPE long long int + bool valid_precision_width; +#else + int ival; + unsigned int uval = 0; +#define STR_FORMAT_PRINTF_UVAL_TYPE unsigned int +#define STR_FORMAT_PRINTF_IVAL_TYPE int +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_FLOAT_ENABLE + double fval; +#endif /* PRINTF_FLOAT_ENABLE */ + + /* Start parsing apart the format string and display appropriate formats and data. */ + p = fmt; + while (true) + { + if ('\0' == *p) + { + break; + } + c = *p; + /* + * All formats begin with a '%' marker. Special chars like + * '\n' or '\t' are normally converted to the appropriate + * character by the __compiler__. Thus, no need for this + * routine to account for the '\' character. + */ + if (c != '%') + { + cb(buf, &count, c, 1); + p++; + /* By using 'continue', the next iteration of the loop is used, skipping the code that follows. */ + continue; + } + + use_caps = true; + +#if PRINTF_ADVANCED_ENABLE + /* First check for specification modifier flags. */ + flags_used = PrintCheckFlags(&p); +#endif /* PRINTF_ADVANCED_ENABLE */ + + /* Next check for minimum field width. */ + field_width = PrintGetWidth(&p, &ap); + + /* Next check for the width and precision field separator. */ +#if PRINTF_ADVANCED_ENABLE + precision_width = PrintGetPrecision(&p, &ap, &valid_precision_width); +#else + precision_width = PrintGetPrecision(&p, &ap, NULL); + (void)precision_width; +#endif + +#if PRINTF_ADVANCED_ENABLE + /* Check for the length modifier. */ + flags_used |= PrintGetLengthFlag(&p); +#else + /* Filter length modifier. */ + PrintFilterLengthFlag(&p); +#endif + + /* Now we're ready to examine the format. */ + c = *++p; + { + if (1U == PrintIsdi(c)) + { +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongLongInt)) + { + ival = (long long int)va_arg(ap, long long int); + } + else if (0U != (flags_used & (uint32_t)kPRINTF_LengthLongInt)) + { + ival = (long long int)va_arg(ap, long int); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + ival = (STR_FORMAT_PRINTF_IVAL_TYPE)va_arg(ap, int); + } + + vlen = ConvertRadixNumToString((char *)vstr, (void *)&ival, 1, 10, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + vlen += (int)PrintGetSignChar(ival, flags_used, &schar); + PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, schar, vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0U, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count); +#endif + } + else if (1U == PrintIsfF(c)) + { +#if PRINTF_FLOAT_ENABLE + fval = (double)va_arg(ap, double); + vlen = ConvertFloatRadixNumToString(vstr, &fval, 10, precision_width); + vstrp = &vstr[vlen]; + +#if PRINTF_ADVANCED_ENABLE + vlen += (int32_t)PrintGetSignChar(((fval < 0.0) ? ((long long int)-1) : ((long long int)fval)), + flags_used, &schar); + PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, schar, vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count); +#endif + +#else + (void)va_arg(ap, double); +#endif /* PRINTF_FLOAT_ENABLE */ + } + else if (1U == PrintIsxX(c)) + { + if (c == 'x') + { + use_caps = false; + } +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongLongInt)) + { + uval = (unsigned long long int)va_arg(ap, unsigned long long int); + } + else if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongInt)) + { + uval = (unsigned long long int)va_arg(ap, unsigned long int); + } + else +#endif /* PRINTF_ADVANCED_ENABLE */ + { + uval = (STR_FORMAT_PRINTF_UVAL_TYPE)va_arg(ap, unsigned int); + } + + vlen = ConvertRadixNumToString((char *)vstr, (void *)&uval, 0, 16, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + PrintOutputxX(flags_used, field_width, (unsigned int)vlen, use_caps, vstrp, cb, buf, &count); +#else + PrintOutputxX(0U, field_width, (uint32_t)vlen, use_caps, vstrp, cb, buf, &count); +#endif + } + else if (1U == PrintIsobpu(c)) + { + if ('p' == c) + { + /* + * Fix MISRA issue: CID 17205581 (#15 of 15): MISRA C-2012 Pointer Type Conversions (MISRA C-2012 + * Rule 11.6) 1.misra_c_2012_rule_11_6_violation: The expression va_arg (ap, void *) of type void * + * is cast to type uint32_t. + * + * Orignal code: uval = (STR_FORMAT_PRINTF_UVAL_TYPE)(uint32_t)va_arg(ap, void *); + */ + void *pval; + pval = (void *)va_arg(ap, void *); + (void)memcpy((void *)&uval, (void *)&pval, sizeof(void *)); + } + else + { +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongLongInt)) + { + uval = (unsigned long long int)va_arg(ap, unsigned long long int); + } + else if (0U != (flags_used & (unsigned int)kPRINTF_LengthLongInt)) + { + uval = (unsigned long long int)va_arg(ap, unsigned long int); + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + uval = (STR_FORMAT_PRINTF_UVAL_TYPE)va_arg(ap, unsigned int); + } +#if PRINTF_ADVANCED_ENABLE + } +#endif /* PRINTF_ADVANCED_ENABLE */ + + radix = PrintGetRadixFromobpu(c); + + vlen = ConvertRadixNumToString((char *)vstr, (void *)&uval, 0, radix, use_caps); + vstrp = &vstr[vlen]; +#if PRINTF_ADVANCED_ENABLE + PrintOutputdifFobpu(flags_used, field_width, (unsigned int)vlen, '\0', vstrp, cb, buf, &count); +#else + PrintOutputdifFobpu(0U, field_width, (uint32_t)vlen, '\0', vstrp, cb, buf, &count); +#endif + } + else if (c == 'c') + { + cval = (int32_t)va_arg(ap, int); + cb(buf, &count, cval, 1); + } + else if (c == 's') + { + sval = (char *)va_arg(ap, char *); + if (NULL != sval) + { +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + vlen = (int)precision_width; + } + else + { + vlen = (int)strlen(sval); + } +#else + vlen = (int32_t)strlen(sval); +#endif /* PRINTF_ADVANCED_ENABLE */ +#if PRINTF_ADVANCED_ENABLE + if (0U == (flags_used & (unsigned int)kPRINTF_Minus)) +#endif /* PRINTF_ADVANCED_ENABLE */ + { + cb(buf, &count, ' ', (int)field_width - (int)vlen); + } + +#if PRINTF_ADVANCED_ENABLE + if (valid_precision_width) + { + while (('\0' != *sval) && (vlen > 0)) + { + cb(buf, &count, *sval++, 1); + vlen--; + } + /* In case that vlen sval is shorter than vlen */ + vlen = (int)precision_width - vlen; + } + else + { +#endif /* PRINTF_ADVANCED_ENABLE */ + while ('\0' != (*sval)) + { + cb(buf, &count, *sval++, 1); + } +#if PRINTF_ADVANCED_ENABLE + } +#endif /* PRINTF_ADVANCED_ENABLE */ + +#if PRINTF_ADVANCED_ENABLE + if (0U != (flags_used & (unsigned int)kPRINTF_Minus)) + { + cb(buf, &count, ' ', (int)field_width - vlen); + } +#endif /* PRINTF_ADVANCED_ENABLE */ + } + } + else + { + cb(buf, &count, c, 1); + } + } + p++; + } + + return (int)count; +} + +#if SCANF_FLOAT_ENABLE +static uint8_t StrFormatScanIsFloat(char *c) +{ + uint8_t ret = 0U; + if (('a' == (*c)) || ('A' == (*c)) || ('e' == (*c)) || ('E' == (*c)) || ('f' == (*c)) || ('F' == (*c)) || + ('g' == (*c)) || ('G' == (*c))) + { + ret = 1U; + } + return ret; +} +#endif + +static uint8_t StrFormatScanIsFormatStarting(char *c) +{ + uint8_t ret = 1U; + if ((*c != '%')) + { + ret = 0U; + } + else if (*(c + 1) == '%') + { + ret = 0U; + } + else + { + /*MISRA rule 15.7*/ + } + + return ret; +} + +static uint8_t StrFormatScanGetBase(uint8_t base, const char *s) +{ + if (base == 0U) + { + if (s[0] == '0') + { + if ((s[1] == 'x') || (s[1] == 'X')) + { + base = 16; + } + else + { + base = 8; + } + } + else + { + base = 10; + } + } + return base; +} + +static uint8_t StrFormatScanCheckSymbol(const char *p, int8_t *neg) +{ + uint8_t len; + switch (*p) + { + case '-': + *neg = -1; + len = 1; + break; + case '+': + *neg = 1; + len = 1; + break; + default: + *neg = 1; + len = 0; + break; + } + return len; +} + +static uint8_t StrFormatScanFillInteger(uint32_t flag, va_list *args_ptr, int32_t val) +{ +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + return 0u; + } + + switch (flag & (uint32_t)kSCANF_LengthMask) + { + case (uint32_t)kSCANF_LengthChar: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed char *) = (signed char)val; + } + else + { + *va_arg(*args_ptr, unsigned char *) = (unsigned char)val; + } + break; + case (uint32_t)kSCANF_LengthShortInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed short *) = (signed short)val; + } + else + { + *va_arg(*args_ptr, unsigned short *) = (unsigned short)val; + } + break; + case (uint32_t)kSCANF_LengthLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed long int *) = (signed long int)val; + } + else + { + *va_arg(*args_ptr, unsigned long int *) = (unsigned long int)val; + } + break; + case (uint32_t)kSCANF_LengthLongLongInt: + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed long long int *) = (signed long long int)val; + } + else + { + *va_arg(*args_ptr, unsigned long long int *) = (unsigned long long int)val; + } + break; + default: + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(*args_ptr, unsigned int *) = (unsigned int)val; + } + break; + } +#else + /* The default type is the type int. */ + if (0U != (flag & (uint32_t)kSCANF_TypeSinged)) + { + *va_arg(*args_ptr, signed int *) = (signed int)val; + } + else + { + *va_arg(*args_ptr, unsigned int *) = (unsigned int)val; + } +#endif /* SCANF_ADVANCED_ENABLE */ + + return 1u; +} + +#if SCANF_FLOAT_ENABLE +static uint8_t StrFormatScanFillFloat(uint32_t flag, va_list *args_ptr, double fnum) +{ +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + return 0u; + } + else +#endif /* SCANF_ADVANCED_ENABLE */ + { + if (0U != (flag & (uint32_t)kSCANF_LengthLongLongDouble)) + { + *va_arg(*args_ptr, double *) = fnum; + } + else + { + *va_arg(*args_ptr, float *) = (float)fnum; + } + return 1u; + } +} +#endif /* SCANF_FLOAT_ENABLE */ + +static uint8_t StrFormatScanfStringHandling(char **str, uint32_t *flag, uint32_t *field_width, uint8_t *base) +{ + uint8_t exitPending = 0U; + char *c = *str; + + /* Loop to get full conversion specification. */ + while (('\0' != (*c)) && (0U == (*flag & (uint32_t)kSCANF_DestMask))) + { +#if SCANF_ADVANCED_ENABLE + if ('*' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_Suppress)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + (*flag) |= (uint32_t)kSCANF_Suppress; + } + } + else if ('h' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + if (c[1] == 'h') + { + (*flag) |= (uint32_t)kSCANF_LengthChar; + c++; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthShortInt; + } + } + } + else if ('l' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + if (c[1] == 'l') + { + (*flag) |= (uint32_t)kSCANF_LengthLongLongInt; + c++; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthLongInt; + } + } + } + else +#endif /* SCANF_ADVANCED_ENABLE */ +#if SCANF_FLOAT_ENABLE + if ('L' == (*c)) + { + if (0U != ((*flag) & (uint32_t)kSCANF_LengthMask)) + { + /* Match failure. */ + exitPending = 1U; + } + else + { + (*flag) |= (uint32_t)kSCANF_LengthLongLongDouble; + } + } + else +#endif /* SCANF_FLOAT_ENABLE */ + if (((*c) >= '0') && ((*c) <= '9')) + { + { + char *p; + errno = 0; + (*field_width) = strtoul(c, &p, 10); + if (0 != errno) + { + *field_width = 0U; + } + c = p - 1; + } + } + else if ('d' == (*c)) + { + (*base) = 10U; + (*flag) |= (uint32_t)kSCANF_TypeSinged; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('u' == (*c)) + { + (*base) = 10U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('o' == (*c)) + { + (*base) = 8U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if (('x' == (*c))) + { + (*base) = 16U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('X' == (*c)) + { + (*base) = 16U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } + else if ('i' == (*c)) + { + (*base) = 0U; + (*flag) |= (uint32_t)kSCANF_DestInt; + } +#if SCANF_FLOAT_ENABLE + else if (1U == StrFormatScanIsFloat(c)) + { + (*flag) |= (uint32_t)kSCANF_DestFloat; + } +#endif /* SCANF_FLOAT_ENABLE */ + else if ('c' == (*c)) + { + (*flag) |= (uint32_t)kSCANF_DestChar; + if (MAX_FIELD_WIDTH == (*field_width)) + { + (*field_width) = 1; + } + } + else if ('s' == (*c)) + { + (*flag) |= (uint32_t)kSCANF_DestString; + } + else + { + exitPending = 1U; + } + + if (1U == exitPending) + { + break; + } + else + { + c++; + } + } + *str = c; + return exitPending; +} + +/*! + * brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * param[in] line_ptr The input line of ASCII data. + * param[in] format Format first points to the format string. + * param[in] args_ptr The list of parameters. + * + * return Number of input items converted and assigned. + * retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr) +{ + uint8_t base; + int8_t neg; + /* Identifier for the format string. */ + char *c = format; + char *buf; + /* Flag telling the conversion specification. */ + uint32_t flag = 0; + /* Filed width for the matching input streams. */ + uint32_t field_width; + /* How many arguments are assigned except the suppress. */ + uint32_t nassigned = 0; + /* How many characters are read from the input streams. */ + uint32_t n_decode = 0; + + int32_t val; + + uint8_t added; + + uint8_t exitPending = 0; + + const char *s; +#if SCANF_FLOAT_ENABLE + char *s_temp; /* MISRA C-2012 Rule 11.3 */ +#endif + + /* Identifier for the input string. */ + const char *p = line_ptr; + +#if SCANF_FLOAT_ENABLE + double fnum = 0.0; +#endif /* SCANF_FLOAT_ENABLE */ + /* Return EOF error before any conversion. */ + if (*p == '\0') + { + return -1; + } + + /* Decode directives. */ + while (('\0' != (*c)) && ('\0' != (*p))) + { + /* Ignore all white-spaces in the format strings. */ + if (0U != ScanIgnoreWhiteSpace((const char **)((void *)&c))) + { + n_decode += ScanIgnoreWhiteSpace(&p); + } + else if (0U == StrFormatScanIsFormatStarting(c)) + { + /* Ordinary characters. */ + c++; + if (*p == *c) + { + n_decode++; + p++; + c++; + } + else + { + /* Match failure. Misalignment with C99, the unmatched characters need to be pushed back to stream. + * However, it is deserted now. */ + break; + } + } + else + { + /* convernsion specification */ + c++; + /* Reset. */ + flag = 0; + field_width = MAX_FIELD_WIDTH; + base = 0; + added = 0U; + + exitPending = StrFormatScanfStringHandling(&c, &flag, &field_width, &base); + + if (1U == exitPending) + { + /* Format strings are exhausted. */ + break; + } + + /* Matching strings in input streams and assign to argument. */ + if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestChar) + { + s = (const char *)p; + buf = va_arg(args_ptr, char *); + while ((0U != (field_width--)) +#if SCANF_ADVANCED_ENABLE + && ('\0' != (*p)) +#endif + ) + { +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + p++; + } + else +#endif + { + *buf++ = *p++; +#if SCANF_ADVANCED_ENABLE + added = 1u; +#endif + } + n_decode++; + } + +#if SCANF_ADVANCED_ENABLE + if (1u == added) +#endif + { + nassigned++; + } + } + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestString) + { + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + buf = va_arg(args_ptr, char *); + while ((0U != (field_width--)) && (*p != '\0') && (0U == ScanIsWhiteSpace(*p))) + { +#if SCANF_ADVANCED_ENABLE + if (0U != (flag & (uint32_t)kSCANF_Suppress)) + { + p++; + } + else +#endif + { + *buf++ = *p++; +#if SCANF_ADVANCED_ENABLE + added = 1u; +#endif + } + n_decode++; + } + +#if SCANF_ADVANCED_ENABLE + if (1u == added) +#endif + { + /* Add NULL to end of string. */ + *buf = '\0'; + nassigned++; + } + } + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestInt) + { + n_decode += ScanIgnoreWhiteSpace(&p); + s = p; + val = 0; + base = StrFormatScanGetBase(base, s); + + added = StrFormatScanCheckSymbol(p, &neg); + n_decode += added; + p += added; + field_width -= added; + + s = p; + if (strlen(p) > field_width) + { + char temp[12]; + char *tempEnd; + (void)memcpy(temp, p, sizeof(temp) - 1U); + temp[sizeof(temp) - 1U] = '\0'; + errno = 0; + val = (int32_t)strtoul(temp, &tempEnd, (int)base); + if (0 != errno) + { + break; + } + p = p + (tempEnd - temp); + } + else + { + char *tempEnd; + val = 0; + errno = 0; + val = (int32_t)strtoul(p, &tempEnd, (int)base); + if (0 != errno) + { + break; + } + p = tempEnd; + } + n_decode += (uintptr_t)p - (uintptr_t)s; + + val *= neg; + + nassigned += StrFormatScanFillInteger(flag, &args_ptr, val); + } +#if SCANF_FLOAT_ENABLE + else if ((flag & (uint32_t)kSCANF_DestMask) == (uint32_t)kSCANF_DestFloat) + { + n_decode += ScanIgnoreWhiteSpace(&p); + fnum = 0.0; + errno = 0; + + fnum = strtod(p, (char **)&s_temp); + s = s_temp; /* MISRA C-2012 Rule 11.3 */ + + /* MISRA C-2012 Rule 22.9 */ + if (0 != errno) + { + break; + } + + if ((fnum < HUGE_VAL) && (fnum > -HUGE_VAL)) + { + n_decode = (uint32_t)n_decode + (uint32_t)s - (uint32_t)p; + p = s; + nassigned += StrFormatScanFillFloat(flag, &args_ptr, fnum); + } + } +#endif /* SCANF_FLOAT_ENABLE */ + else + { + break; + } + } + } + return (int)nassigned; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/str/fsl_str.h b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/str/fsl_str.h new file mode 100644 index 0000000000..bf7adcc52a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/str/fsl_str.h @@ -0,0 +1,66 @@ +/* + * Copyright 2017 NXP + * All rights reserved. + * + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#ifndef _FSL_STR_H +#define _FSL_STR_H + +#include "fsl_common.h" + +/*! + * @addtogroup debugconsole + * @{ + */ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/*! + * @brief A function pointer which is used when format printf log. + */ +typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len); + +/*! + * @brief This function outputs its parameters according to a formatted string. + * + * @note I/O is performed by calling given function pointer using following + * (*func_ptr)(c); + * + * @param[in] fmt Format string for printf. + * @param[in] ap Arguments to printf. + * @param[in] buf pointer to the buffer + * @param cb print callbck function pointer + * + * @return Number of characters to be print + */ +int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb); + +/*! + * @brief Converts an input line of ASCII characters based upon a provided + * string format. + * + * @param[in] line_ptr The input line of ASCII data. + * @param[in] format Format first points to the format string. + * @param[in] args_ptr The list of parameters. + * + * @return Number of input items converted and assigned. + * @retval IO_EOF When line_ptr is empty string "". + */ +int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/*! @} */ + +#endif /* _FSL_STR_H */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utilities_misc_utilities_LPC55S69_cm33_core0.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utilities_misc_utilities_LPC55S69_cm33_core0.cmake new file mode 100644 index 0000000000..0e77aeb977 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utilities_misc_utilities_LPC55S69_cm33_core0.cmake @@ -0,0 +1,9 @@ +include_guard() +message("utilities_misc_utilities component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_sbrk.c + ${CMAKE_CURRENT_LIST_DIR}/fsl_memcpy.S +) + + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utilities_misc_utilities_LPC55S69_cm33_core1.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utilities_misc_utilities_LPC55S69_cm33_core1.cmake new file mode 100644 index 0000000000..0e77aeb977 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utilities_misc_utilities_LPC55S69_cm33_core1.cmake @@ -0,0 +1,9 @@ +include_guard() +message("utilities_misc_utilities component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_sbrk.c + ${CMAKE_CURRENT_LIST_DIR}/fsl_memcpy.S +) + + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_assert_LPC55S69_cm33_core0.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_assert_LPC55S69_cm33_core0.cmake new file mode 100644 index 0000000000..2da82c466e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_assert_LPC55S69_cm33_core0.cmake @@ -0,0 +1,10 @@ +include_guard() +message("utility_assert component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_assert.c +) + + +include(utility_debug_console_LPC55S69_cm33_core0) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_assert_LPC55S69_cm33_core1.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_assert_LPC55S69_cm33_core1.cmake new file mode 100644 index 0000000000..e5de80d10c --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_assert_LPC55S69_cm33_core1.cmake @@ -0,0 +1,10 @@ +include_guard() +message("utility_assert component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_assert.c +) + + +include(utility_debug_console_LPC55S69_cm33_core1) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_debug_console_LPC55S69_cm33_core0.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_debug_console_LPC55S69_cm33_core0.cmake new file mode 100644 index 0000000000..6d0c7789d4 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_debug_console_LPC55S69_cm33_core0.cmake @@ -0,0 +1,19 @@ +include_guard() +message("utility_debug_console component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/str/fsl_str.c + ${CMAKE_CURRENT_LIST_DIR}/debug_console/fsl_debug_console.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/str + ${CMAKE_CURRENT_LIST_DIR}/debug_console +) + + +include(component_serial_manager_LPC55S69_cm33_core0) + +include(driver_common_LPC55S69_cm33_core0) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_debug_console_LPC55S69_cm33_core1.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_debug_console_LPC55S69_cm33_core1.cmake new file mode 100644 index 0000000000..221c5a846e --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_debug_console_LPC55S69_cm33_core1.cmake @@ -0,0 +1,19 @@ +include_guard() +message("utility_debug_console component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/str/fsl_str.c + ${CMAKE_CURRENT_LIST_DIR}/debug_console/fsl_debug_console.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/str + ${CMAKE_CURRENT_LIST_DIR}/debug_console +) + + +include(component_serial_manager_LPC55S69_cm33_core1) + +include(driver_common_LPC55S69_cm33_core1) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_shell_LPC55S69_cm33_core0.cmake b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_shell_LPC55S69_cm33_core0.cmake new file mode 100644 index 0000000000..fea7106041 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/LPC55S6X/utilities/utility_shell_LPC55S69_cm33_core0.cmake @@ -0,0 +1,19 @@ +include_guard() +message("utility_shell component is included.") + +target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/fsl_shell.c +) + + +target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/. +) + + +include(utility_debug_console_LPC55S69_cm33_core0) + +include(component_lists_LPC55S69_cm33_core0) + +include(driver_common_LPC55S69_cm33_core0) + diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/SConscript b/bsp/lpc55sxx/Libraries/LPC55S6X/SConscript index 4555af0682..ed94a12153 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/SConscript +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/SConscript @@ -2,7 +2,7 @@ Import('rtconfig') from building import * cwd = GetCurrentDir() -path = [cwd + '/CMSIS/Include',cwd + '/components/codec', cwd + '/LPC55S6X', cwd + '/LPC55S6X/drivers', cwd + '/middleware/sdmmc/inc', cwd + '/middleware/sdmmc/port'] +path = [cwd + '/CMSIS/Core/Include',cwd + '/components/codec', cwd + '/LPC55S6X', cwd + '/LPC55S6X/drivers', cwd + '/middleware/sdmmc/inc', cwd + '/middleware/sdmmc/port'] src = Split(''' LPC55S6X/system_LPC55S69_cm33_core0.c ''') @@ -19,6 +19,7 @@ src += ['LPC55S6X/drivers/fsl_casper.c'] src += ['LPC55S6X/drivers/fsl_clock.c'] src += ['LPC55S6X/drivers/fsl_cmp.c'] src += ['LPC55S6X/drivers/fsl_common.c'] +src += ['LPC55S6X/drivers/fsl_common_arm.c'] src += ['LPC55S6X/drivers/fsl_crc.c'] src += ['LPC55S6X/drivers/fsl_ctimer.c'] src += ['LPC55S6X/drivers/fsl_flexcomm.c'] @@ -39,7 +40,6 @@ src += ['LPC55S6X/drivers/fsl_pint.c'] src += ['LPC55S6X/drivers/fsl_plu.c'] src += ['LPC55S6X/drivers/fsl_power.c'] src += ['LPC55S6X/drivers/fsl_powerquad_basic.c'] -src += ['LPC55S6X/drivers/fsl_prince.c'] src += ['LPC55S6X/drivers/fsl_puf.c'] src += ['LPC55S6X/drivers/fsl_reset.c'] src += ['LPC55S6X/drivers/fsl_rng.c'] @@ -53,17 +53,7 @@ src += ['LPC55S6X/drivers/fsl_usart.c'] src += ['LPC55S6X/drivers/fsl_usart_dma.c'] src += ['LPC55S6X/drivers/fsl_utick.c'] src += ['LPC55S6X/drivers/fsl_wwdt.c'] -src += ['middleware/sdmmc/src/fsl_sd.c'] -src += ['middleware/sdmmc/src/fsl_sdmmc_common.c'] -src += ['middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_event.c'] -src += ['middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_host.c'] -if rtconfig.PLATFORM in ['gcc']: - src += ['LPC55S6X/gcc/libpower_hardabi.a'] -elif rtconfig.PLATFORM in ['armcc', 'armclang']: - src += ['LPC55S6X/arm/keil_lib_power_cm33_core0.lib'] -elif rtconfig.PLATFORM in ['iccarm']: - src += ['LPC55S6X/iar/iar_lib_power_cm33_core0.a'] group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.c b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.c deleted file mode 100644 index 95ae10a412..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.c +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright 2017-2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_codec_common.h" -#include "fsl_codec_adapter.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief codec play and record capability */ -#define GET_PLAY_CHANNEL_CAPABILITY(capability) (capability & 0xFFU) -#define GET_PLAY_SOURCE_CAPABILITY(capability) (capability >> 8U) -#define GET_RECORD_SOURCE_CAPABILITY(capability) (capability & 0x3FU) -#define GET_RECORD_CHANNEL_CAPABILITY(capability) (capability >> 6U) -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Codec initilization. - * - * param handle codec handle. - * param config codec configuration. - * return kStatus_Success is success, else initial failed. - */ -status_t CODEC_Init(codec_handle_t *handle, codec_config_t *config) -{ - assert((config != NULL) && (handle != NULL)); - - /* Set the handle information */ - handle->codecConfig = config; - - return HAL_CODEC_Init(handle, config); -} - -/*! - * brief Codec de-initilization. - * - * param handle codec handle. - * return kStatus_Success is success, else de-initial failed. - */ -status_t CODEC_Deinit(codec_handle_t *handle) -{ - assert((handle != NULL) && (handle->codecConfig != NULL)); - - return HAL_CODEC_Deinit(handle); -} - -/*! - * brief set audio data format. - * - * param handle codec handle. - * param mclk master clock frequency in HZ. - * param sampleRate sample rate in HZ. - * param bitWidth bit width. - * return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetFormat(codec_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth) -{ - assert((handle != NULL) && (handle->codecConfig != NULL)); - - return HAL_CODEC_SetFormat(handle, mclk, sampleRate, bitWidth); -} - -/*! - * brief codec module control. - * - * This function is used for codec module control, support switch digital interface cmd, can be expand to support codec - * module specific feature - * - * param handle codec handle. - * param cmd module control cmd, reference _codec_module_ctrl_cmd. - * param data value to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine - * of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference - * codec specific driver for detail configurations. - * return kStatus_Success is success, else configure failed. - */ -status_t CODEC_ModuleControl(codec_handle_t *handle, codec_module_ctrl_cmd_t cmd, uint32_t data) -{ - assert((handle != NULL) && (handle->codecConfig != NULL)); - - switch (cmd) - { - case kCODEC_ModuleSwitchI2SInInterface: - if ((handle->codecCapability.codecModuleCapability & kCODEC_SupportModuleI2SInSwitchInterface) == 0U) - { - return kStatus_CODEC_NotSupport; - } - break; - - default: - return kStatus_CODEC_NotSupport; - } - - return HAL_CODEC_ModuleControl(handle, cmd, data); -} - -/*! - * brief set audio codec module volume. - * - * param handle codec handle. - * param channel audio codec play channel, can be a value or combine value of _codec_play_channel. - * param volume volume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value. - * return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetVolume(codec_handle_t *handle, uint32_t playChannel, uint32_t volume) -{ - assert((handle != NULL) && (handle->codecConfig != NULL)); - assert(volume <= CODEC_VOLUME_MAX_VALUE); - - /* check capability of set volume */ - if ((GET_PLAY_CHANNEL_CAPABILITY(handle->codecCapability.codecPlayCapability) & playChannel) == 0U) - { - return kStatus_CODEC_NotSupport; - } - - return HAL_CODEC_SetVolume(handle, playChannel, volume); -} - -/*! - * brief set audio codec module mute. - * - * param handle codec handle. - * param channel audio codec play channel, can be a value or combine value of _codec_play_channel. - * param mute true is mute, false is unmute. - * return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetMute(codec_handle_t *handle, uint32_t playChannel, bool mute) -{ - assert((handle != NULL) && (handle->codecConfig != NULL)); - - /* check capability of mute */ - if ((GET_PLAY_CHANNEL_CAPABILITY(handle->codecCapability.codecPlayCapability) & playChannel) == 0U) - { - return kStatus_CODEC_NotSupport; - } - - return HAL_CODEC_SetMute(handle, playChannel, mute); -} - -/*! - * brief set audio codec module power. - * - * param handle codec handle. - * param module audio codec module. - * param powerOn true is power on, false is power down. - * return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetPower(codec_handle_t *handle, codec_module_t module, bool powerOn) -{ - assert((handle != NULL) && (handle->codecConfig != NULL)); - - /* check capability of power switch */ - if ((handle->codecCapability.codecModuleCapability & (1U << module)) == 0U) - { - return kStatus_CODEC_NotSupport; - } - - return HAL_CODEC_SetPower(handle, module, powerOn); -} - -/*! - * brief codec set record source. - * - * param handle codec handle. - * param source audio codec record source, can be a value or combine value of _codec_record_source. - * - * return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetRecord(codec_handle_t *handle, uint32_t recordSource) -{ - assert((handle != NULL) && (handle->codecConfig != NULL)); - - /* check capability of record capability */ - if ((GET_RECORD_SOURCE_CAPABILITY(handle->codecCapability.codecRecordCapability) & recordSource) == 0U) - { - return kStatus_CODEC_NotSupport; - } - - return HAL_CODEC_SetRecord(handle, recordSource); -} - -/*! - * brief codec set record channel. - * - * param handle codec handle. - * param leftRecordChannel audio codec record channel, reference _codec_record_channel, can be a value or combine value - of member in _codec_record_channel. - * param rightRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of - member in _codec_record_channel. - - * return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetRecordChannel(codec_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel) -{ - assert((handle != NULL) && (handle->codecConfig != NULL)); - - /* check capability of record capability */ - if ((GET_RECORD_CHANNEL_CAPABILITY(handle->codecCapability.codecRecordCapability) & leftRecordChannel) == 0U) - { - return kStatus_CODEC_NotSupport; - } - - if ((GET_RECORD_CHANNEL_CAPABILITY(handle->codecCapability.codecRecordCapability) & rightRecordChannel) == 0U) - { - return kStatus_CODEC_NotSupport; - } - - return HAL_CODEC_SetRecordChannel(handle, leftRecordChannel, rightRecordChannel); -} - -/*! - * brief codec set play source. - * - * param handle codec handle. - * param playSource audio codec play source, can be a value or combine value of _codec_play_source. - * - * return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetPlay(codec_handle_t *handle, uint32_t playSource) -{ - assert((handle != NULL) && (handle->codecConfig != NULL)); - - /* check capability of record capability */ - if ((GET_PLAY_SOURCE_CAPABILITY(handle->codecCapability.codecPlayCapability) & playSource) == 0U) - { - return kStatus_CODEC_NotSupport; - } - - return HAL_CODEC_SetPlay(handle, playSource); -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.h b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.h deleted file mode 100644 index c285589e83..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/fsl_codec_common.h +++ /dev/null @@ -1,363 +0,0 @@ -/* - * Copyright 2017- 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CODEC_COMMON_H_ -#define _FSL_CODEC_COMMON_H_ - -#include "fsl_common.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @name Driver version */ -/*@{*/ -/*! @brief CLOCK driver version 2.1.0. */ -#define FSL_CODEC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -/*! @brief CODEC handle buffer size */ -#ifndef CODEC_HANDLE_SIZE -#define CODEC_HANDLE_SIZE (128U) -#endif - -/*! @brief codec maximum volume range */ -#define CODEC_VOLUME_MAX_VALUE (100U) - -/*! @brief CODEC status */ -enum _codec_status -{ - kStatus_CODEC_NotSupport = MAKE_STATUS(kStatusGroup_CODEC, 0U), /*!< CODEC not support status */ - kStatus_CODEC_DeviceNotRegistered = MAKE_STATUS(kStatusGroup_CODEC, 1U), /*!< CODEC device register failed status */ - kStatus_CODEC_I2CBusInitialFailed = - MAKE_STATUS(kStatusGroup_CODEC, 2U), /*!< CODEC i2c bus initialization failed status */ - kStatus_CODEC_I2CCommandTransferFailed = - MAKE_STATUS(kStatusGroup_CODEC, 3U), /*!< CODEC i2c bus command transfer failed status */ -}; - -/*! @brief AUDIO format definition. */ -typedef enum _codec_audio_protocol -{ - kCODEC_BusI2S = 0U, /*!< I2S type */ - kCODEC_BusLeftJustified = 1U, /*!< Left justified mode */ - kCODEC_BusRightJustified = 2U, /*!< Right justified mode */ - kCODEC_BusPCMA = 3U, /*!< DSP/PCM A mode */ - kCODEC_BusPCMB = 4U, /*!< DSP/PCM B mode */ - kCODEC_BusTDM = 5U, /*!< TDM mode */ -} codec_audio_protocol_t; - -/*! @brief audio sample rate definition */ -enum _codec_audio_sample_rate -{ - kCODEC_AudioSampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */ - kCODEC_AudioSampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */ - kCODEC_AudioSampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */ - kCODEC_AudioSampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */ - kCODEC_AudioSampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */ - kCODEC_AudioSampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */ - kCODEC_AudioSampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */ - kCODEC_AudioSampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */ - kCODEC_AudioSampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */ - kCODEC_AudioSampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */ - kCODEC_AudioSampleRate192KHz = 192000U, /*!< Sample rate 192000 Hz */ - kCODEC_AudioSampleRate384KHz = 384000U, /*!< Sample rate 384000 Hz */ -}; - -/*! @brief audio bit width */ -enum _codec_audio_bit_width -{ - kCODEC_AudioBitWidth16bit = 16U, /*!< audio bit width 16 */ - kCODEC_AudioBitWidth20bit = 20U, /*!< audio bit width 20 */ - kCODEC_AudioBitWidth24bit = 24U, /*!< audio bit width 24 */ - kCODEC_AudioBitWidth32bit = 32U, /*!< audio bit width 32 */ -}; - -/*! @brief audio codec module*/ -typedef enum _codec_module -{ - kCODEC_ModuleADC = 0U, /*!< codec module ADC */ - kCODEC_ModuleDAC = 1U, /*!< codec module DAC */ - kCODEC_ModulePGA = 2U, /*!< codec module PGA */ - kCODEC_ModuleHeadphone = 3U, /*!< codec module headphone */ - kCODEC_ModuleSpeaker = 4U, /*!< codec module speaker */ - kCODEC_ModuleLinein = 5U, /*!< codec module linein */ - kCODEC_ModuleLineout = 6U, /*!< codec module lineout */ - kCODEC_ModuleVref = 7U, /*!< codec module VREF */ - kCODEC_ModuleMicbias = 8U, /*!< codec module MIC BIAS */ - kCODEC_ModuleMic = 9U, /*!< codec module MIC */ - kCODEC_ModuleI2SIn = 10U, /*!< codec module I2S in */ - kCODEC_ModuleI2SOut = 11U, /*!< codec module I2S out */ - kCODEC_ModuleMxier = 12U, /*!< codec module mixer */ -} codec_module_t; - -/*! @brief audio codec module control cmd */ -typedef enum _codec_module_ctrl_cmd -{ - kCODEC_ModuleSwitchI2SInInterface = 0U, /*!< module digital interface siwtch. */ -} codec_module_ctrl_cmd_t; - -/*! @brief audio codec module digital interface */ -enum _codec_module_ctrl_i2s_in_interface -{ - kCODEC_ModuleI2SInInterfacePCM = 0U, /*!< Pcm interface*/ - kCODEC_ModuleI2SInInterfaceDSD = 1U, /*!< DSD interface */ -}; - -/*! @brief audio codec module record source value */ -enum _codec_record_source -{ - kCODEC_RecordSourceDifferentialLine = 1U, /*!< record source from differential line */ - kCODEC_RecordSourceLineInput = 2U, /*!< record source from line input */ - kCODEC_RecordSourceDifferentialMic = 4U, /*!< record source from differential mic */ - kCODEC_RecordSourceDigitalMic = 8U, /*!< record source from digital microphone */ - kCODEC_RecordSourceSingleEndMic = 16U, /*!< record source from single microphone */ -}; - -/*! @brief audio codec record channel */ -enum _codec_reocrd_channel -{ - kCODEC_RecordChannelLeft1 = 1U, /*!< left record channel 1 */ - kCODEC_RecordChannelLeft2 = 2U, /*!< left record channel 2 */ - kCODEC_RecordChannelLeft3 = 4U, /*!< left record channel 3 */ - kCODEC_RecordChannelRight1 = 1U, /*!< right record channel 1 */ - kCODEC_RecordChannelRight2 = 2U, /*!< right record channel 2 */ - kCODEC_RecordChannelRight3 = 4U, /*!< right record channel 3 */ - kCODEC_RecordChannelDifferentialPositive1 = 1U, /*!< differential positive record channel 1 */ - kCODEC_RecordChannelDifferentialPositive2 = 2U, /*!< differential positive record channel 2 */ - kCODEC_RecordChannelDifferentialPositive3 = 4U, /*!< differential positive record channel 3 */ - kCODEC_RecordChannelDifferentialNegative1 = 8U, /*!< differential negative record channel 1 */ - kCODEC_RecordChannelDifferentialNegative2 = 16U, /*!< differential negative record channel 2 */ - kCODEC_RecordChannelDifferentialNegative3 = 32U, /*!< differential negative record channel 3 */ -}; - -/*! @brief audio codec module play source value */ -enum _codec_play_source -{ - kCODEC_PlaySourcePGA = 1U, /*!< play source PGA, bypass ADC */ - kCODEC_PlaySourceInput = 2U, /*!< play source Input3 */ - kCODEC_PlaySourceDAC = 4U, /*!< play source DAC */ - kCODEC_PlaySourceMixerIn = 1U, /*!< play source mixer in */ - kCODEC_PlaySourceMixerInLeft = 2U, /*!< play source mixer in left */ - kCODEC_PlaySourceMixerInRight = 4U, /*!< play source mixer in right */ - kCODEC_PlaySourceAux = 8U, /*!< play source mixer in AUx */ -}; - -/*! @brief codec play channel */ -enum _codec_play_channel -{ - kCODEC_PlayChannelHeadphoneLeft = 1U, /*!< play channel headphone left */ - kCODEC_PlayChannelHeadphoneRight = 2U, /*!< play channel headphone right */ - kCODEC_PlayChannelSpeakerLeft = 4U, /*!< play channel speaker left */ - kCODEC_PlayChannelSpeakerRight = 8U, /*!< play channel speaker right */ - kCODEC_PlayChannelLineOutLeft = 16U, /*!< play channel lineout left */ - kCODEC_PlayChannelLineOutRight = 32U, /*!< play channel lineout right */ - - kCODEC_PlayChannelLeft0 = 1U, /*!< play channel left0 */ - kCODEC_PlayChannelRight0 = 2U, /*!< play channel right0 */ - kCODEC_PlayChannelLeft1 = 4U, /*!< play channel left1 */ - kCODEC_PlayChannelRight1 = 8U, /*!< play channel right1 */ - kCODEC_PlayChannelLeft2 = 16U, /*!< play channel left2 */ - kCODEC_PlayChannelRight2 = 32U, /*!< play channel right2 */ - kCODEC_PlayChannelLeft3 = 64U, /*!< play channel left3 */ - kCODEC_PlayChannelRight3 = 128U, /*!< play channel right3 */ -}; - -/*! @brief audio codec capability */ -enum _codec_capability_flag -{ - kCODEC_SupportModuleADC = 1U << 0U, /*!< codec capability of module ADC */ - kCODEC_SupportModuleDAC = 1U << 1U, /*!< codec capability of module DAC */ - kCODEC_SupportModulePGA = 1U << 2U, /*!< codec capability of module PGA */ - kCODEC_SupportModuleHeadphone = 1U << 3U, /*!< codec capability of module headphone */ - kCODEC_SupportModuleSpeaker = 1U << 4U, /*!< codec capability of module speaker */ - kCODEC_SupportModuleLinein = 1U << 5U, /*!< codec capability of module linein */ - kCODEC_SupportModuleLineout = 1U << 6U, /*!< codec capability of module lineout */ - kCODEC_SupportModuleVref = 1U << 7U, /*!< codec capability of module vref */ - kCODEC_SupportModuleMicbias = 1U << 8U, /*!< codec capability of module mic bias */ - kCODEC_SupportModuleMic = 1U << 9U, /*!< codec capability of module mic bias */ - kCODEC_SupportModuleI2SIn = 1U << 10U, /*!< codec capability of module I2S in */ - kCODEC_SupportModuleI2SOut = 1U << 11U, /*!< codec capability of module I2S out */ - kCODEC_SupportModuleMixer = 1U << 12U, /*!< codec capability of module mixer */ - kCODEC_SupportModuleI2SInSwitchInterface = 1U << 13U, /*!< codec capability of module I2S in switch interface */ - - kCODEC_SupportPlayChannelLeft0 = 1U << 0U, /*!< codec capability of play channel left 0 */ - kCODEC_SupportPlayChannelRight0 = 1U << 1U, /*!< codec capability of play channel right 0 */ - kCODEC_SupportPlayChannelLeft1 = 1U << 2U, /*!< codec capability of play channel left 1 */ - kCODEC_SupportPlayChannelRight1 = 1U << 3U, /*!< codec capability of play channel right 1 */ - kCODEC_SupportPlayChannelLeft2 = 1U << 4U, /*!< codec capability of play channel left 2 */ - kCODEC_SupportPlayChannelRight2 = 1U << 5U, /*!< codec capability of play channel right 2 */ - kCODEC_SupportPlayChannelLeft3 = 1U << 6U, /*!< codec capability of play channel left 3 */ - kCODEC_SupportPlayChannelRight3 = 1U << 7U, /*!< codec capability of play channel right 3 */ - - kCODEC_SupportPlaySourcePGA = 1U << 8U, /*!< codec capability of set playback source PGA */ - kCODEC_SupportPlaySourceInput = 1U << 9U, /*!< codec capability of set playback source INPUT */ - kCODEC_SupportPlaySourceDAC = 1U << 10U, /*!< codec capability of set playback source DAC */ - kCODEC_SupportPlaySourceMixerIn = 1U << 11U, /*!< codec capability of set play source Mixer in */ - kCODEC_SupportPlaySourceMixerInLeft = 1U << 12U, /*!< codec capability of set play source Mixer in left */ - kCODEC_SupportPlaySourceMixerInRight = 1U << 13U, /*!< codec capability of set play source Mixer in right */ - kCODEC_SupportPlaySourceAux = 1U << 14U, /*!< codec capability of set play source aux */ - - kCODEC_SupportRecordSourceDifferentialLine = 1U << 0U, /*!< codec capability of record source differential line */ - kCODEC_SupportRecordSourceLineInput = 1U << 1U, /*!< codec capability of record source line input */ - kCODEC_SupportRecordSourceDifferentialMic = 1U << 2U, /*!< codec capability of record source differential mic */ - kCODEC_SupportRecordSourceDigitalMic = 1U << 3U, /*!< codec capability of record digital mic */ - kCODEC_SupportRecordSourceSingleEndMic = 1U << 4U, /*!< codec capability of single end mic */ - kCODEC_SupportRecordChannelLeft1 = 1U << 6U, /*!< left record channel 1 */ - kCODEC_SupportRecordChannelLeft2 = 1U << 7U, /*!< left record channel 2 */ - kCODEC_SupportRecordChannelLeft3 = 1U << 8U, /*!< left record channel 3 */ - kCODEC_SupportRecordChannelRight1 = 1U << 9U, /*!< right record channel 1 */ - kCODEC_SupportRecordChannelRight2 = 1U << 10U, /*!< right record channel 2 */ - kCODEC_SupportRecordChannelRight3 = 1U << 11U, /*!< right record channel 3 */ -}; - -/*!@brief codec handle declaration */ -typedef struct codec_handle codec_handle_t; - -/*! @brief Initialize structure of the codec */ -typedef struct _codec_config -{ - uint32_t codecDevType; /*!< codec type */ - void *codecDevConfig; /*!< Codec device specific configuration */ -} codec_config_t; - -/*! @brief codec capability */ -typedef struct _codec_capability -{ - uint32_t codecModuleCapability; /*!< codec module capability */ - uint32_t codecPlayCapability; /*!< codec play capability */ - uint32_t codecRecordCapability; /*!< codec record capability */ -} codec_capability_t; - -/*! @brief Codec handle definition. - * * Application should allocate a buffer with CODEC_HANDLE_SIZE for handle definition, such as - * uint8_t codecHandleBuffer[CODEC_HANDLE_SIZE]; - * codec_handle_t *codecHandle = codecHandleBuffer; - */ -struct codec_handle -{ - codec_config_t *codecConfig; /*!< codec configuration function pointer */ - codec_capability_t codecCapability; /*!< codec capability */ - void *codecDevHandle; /*!< codec device handle */ -}; - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif -/*! - * @brief Codec initilization. - * - * @param handle codec handle. - * @param config codec configurations. - * @return kStatus_Success is success, else de-initial failed. - */ -status_t CODEC_Init(codec_handle_t *handle, codec_config_t *config); - -/*! - * @brief Codec de-initilization. - * - * @param handle codec handle. - * @return kStatus_Success is success, else de-initial failed. - */ -status_t CODEC_Deinit(codec_handle_t *handle); - -/*! - * @brief set audio data format. - * - * @param handle codec handle. - * @param mclk master clock frequency in HZ. - * @param sampleRate sample rate in HZ. - * @param bitWidth bit width. - * @return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetFormat(codec_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth); - -/*! - * @brief codec module control. - * - * This function is used for codec module control, support switch digital interface cmd, can be expand to support codec - * module specific feature. - * - * @param handle codec handle. - * @param cmd module control cmd, reference _codec_module_ctrl_cmd. - * @param data value to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine - * of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference - * codec specific driver for detail configurations. - * @return kStatus_Success is success, else configure failed. - */ -status_t CODEC_ModuleControl(codec_handle_t *handle, codec_module_ctrl_cmd_t cmd, uint32_t data); - -/*! - * @brief set audio codec pl volume. - * - * @param handle codec handle. - * @param channel audio codec play channel, can be a value or combine value of _codec_play_channel. - * @param volume volume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value. - * @return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetVolume(codec_handle_t *handle, uint32_t channel, uint32_t volume); - -/*! - * @brief set audio codec module mute. - * - * @param handle codec handle. - * @param channel audio codec play channel, can be a value or combine value of _codec_play_channel. - * @param mute true is mute, false is unmute. - * @return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetMute(codec_handle_t *handle, uint32_t channel, bool mute); - -/*! - * @brief set audio codec power. - * - * @param handle codec handle. - * @param module audio codec module. - * @param powerOn true is power on, false is power down. - * @return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetPower(codec_handle_t *handle, codec_module_t module, bool powerOn); - -/*! - * @brief codec set record source. - * - * @param handle codec handle. - * @param source audio codec record source, can be a value or combine value of _codec_record_source. - * - * @return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetRecord(codec_handle_t *handle, uint32_t recordRource); - -/*! - * @brief codec set record channel. - * - * @param handle codec handle. - * @param leftRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of - member in _codec_record_channel. - * @param rightRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of - member in _codec_record_channel. - - * @return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetRecordChannel(codec_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel); - -/*! - * @brief codec set play source. - * - * @param handle codec handle. - * @param playSource audio codec play source, can be a value or combine value of _codec_play_source. - * - * @return kStatus_Success is success, else configure failed. - */ -status_t CODEC_SetPlay(codec_handle_t *handle, uint32_t playSource); - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_CODEC_COMMON_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.c b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.c deleted file mode 100644 index dc89cd4ccc..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_codec_i2c.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Codec i2c bus initilization. - * - * param handle i2c master handle. - * param i2CInstance instance number of the i2c bus, such as 0 is corresponding to I2C0. - * param i2cBaudrate i2c baudrate. - * param i2cSourceClockHz i2c source clock frequency. - * return kStatus_HAL_I2cSuccess is success, else initial failed. - */ -status_t CODEC_I2C_Init(void *handle, uint32_t i2cInstance, uint32_t i2cBaudrate, uint32_t i2cSourceClockHz) -{ - hal_i2c_master_config_t masterConfig; - - masterConfig.enableMaster = true; - masterConfig.baudRate_Bps = i2cBaudrate; - masterConfig.srcClock_Hz = i2cSourceClockHz; - masterConfig.instance = i2cInstance; - - return HAL_I2cMasterInit((hal_i2c_master_handle_t *)handle, &masterConfig); -} - -/*! - * brief Codec i2c de-initilization. - * - * param handle i2c master handle. - * return kStatus_HAL_I2cSuccess is success, else deinitial failed. - */ -status_t CODEC_I2C_Deinit(void *handle) -{ - return HAL_I2cMasterDeinit((hal_i2c_master_handle_t *)handle); -} - -/*! - * brief codec i2c send function. - * - * param handle i2c master handle. - * param deviceAddress codec device address. - * param subAddress register address. - * param subaddressSize register address width. - * param txBuff tx buffer pointer. - * param txBuffSize tx buffer size. - * return kStatus_HAL_I2cSuccess is success, else send failed. - */ -status_t CODEC_I2C_Send(void *handle, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *txBuff, - uint8_t txBuffSize) -{ - hal_i2c_master_transfer_t masterXfer; - - masterXfer.slaveAddress = deviceAddress; - masterXfer.direction = kHAL_I2cWrite; - masterXfer.subaddress = (uint32_t)subAddress; - masterXfer.subaddressSize = subaddressSize; - masterXfer.data = txBuff; - masterXfer.dataSize = txBuffSize; - masterXfer.flags = kHAL_I2cTransferDefaultFlag; - - return HAL_I2cMasterTransferBlocking((hal_i2c_master_handle_t *)handle, &masterXfer); -} - -/*! - * brief codec i2c receive function. - * - * param handle i2c master handle. - * param deviceAddress codec device address. - * param subAddress register address. - * param subaddressSize register address width. - * param rxBuff rx buffer pointer. - * param rxBuffSize rx buffer size. - * return kStatus_HAL_I2cSuccess is success, else receive failed. - */ -status_t CODEC_I2C_Receive(void *handle, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize) -{ - hal_i2c_master_transfer_t masterXfer; - - masterXfer.slaveAddress = deviceAddress; - masterXfer.direction = kHAL_I2cRead; - masterXfer.subaddress = (uint32_t)subAddress; - masterXfer.subaddressSize = subaddressSize; - masterXfer.data = rxBuff; - masterXfer.dataSize = rxBuffSize; - masterXfer.flags = kHAL_I2cTransferDefaultFlag; - - return HAL_I2cMasterTransferBlocking((hal_i2c_master_handle_t *)handle, &masterXfer); -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.h b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.h deleted file mode 100644 index 7647a1cc84..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/i2c/fsl_codec_i2c.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CODEC_I2C_H_ -#define _FSL_CODEC_I2C_H_ - -#include "fsl_common.h" -#include "i2c.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @brief CODEC device register address type. */ -typedef enum _codec_reg_addr -{ - kCODEC_RegAddr8Bit = 1U, /*!< 8-bit register address. */ - kCODEC_RegAddr16Bit = 2U, /*!< 16-bit register address. */ -} codec_reg_addr_t; - -/*! @brief CODEC device register width. */ -typedef enum _codec_reg_width -{ - kCODEC_RegWidth8Bit = 1U, /*!< 8-bit register width. */ - kCODEC_RegWidth16Bit = 2U, /*!< 16-bit register width. */ - kCODEC_RegWidth32Bit = 4U, /*!< 32-bit register width. */ -} codec_reg_width_t; - -/*! @brief CODEC I2C configurations structure */ -typedef struct _codec_i2c_config -{ - uint32_t codecI2CInstance; /*!< i2c bus instance */ - uint32_t codecI2CSourceClock; /*!< i2c bus source clock frequency */ -} codec_i2c_config_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief Codec i2c bus initilization. - * - * @param handle i2c master handle. - * @param i2CInstance instance number of the i2c bus, such as 0 is corresponding to I2C0. - * @param i2cBaudrate i2c baudrate. - * @param i2cSourceClockHz i2c source clock frequency. - * @return kStatus_HAL_I2cSuccess is success, else initial failed. - */ -status_t CODEC_I2C_Init(void *handle, uint32_t i2cInstance, uint32_t i2cBaudrate, uint32_t i2cSourceClockHz); - -/*! - * @brief Codec i2c de-initilization. - * - * @param handle i2c master handle. - * @return kStatus_HAL_I2cSuccess is success, else deinitial failed. - */ -status_t CODEC_I2C_Deinit(void *handle); - -/*! - * @brief codec i2c send function. - * - * @param handle i2c master handle. - * @param deviceAddress codec device address. - * @param subAddress register address. - * @param subaddressSize register address width. - * @param txBuff tx buffer pointer. - * @param txBuffSize tx buffer size. - * @return kStatus_HAL_I2cSuccess is success, else send failed. - */ -status_t CODEC_I2C_Send(void *handle, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *txBuff, - uint8_t txBuffSize); - -/*! - * @brief codec i2c receive function. - * - * @param handle i2c master handle. - * @param deviceAddress codec device address. - * @param subAddress register address. - * @param subaddressSize register address width. - * @param rxBuff rx buffer pointer. - * @param rxBuffSize rx buffer size. - * @return kStatus_HAL_I2cSuccess is success, else receive failed. - */ -status_t CODEC_I2C_Receive(void *handle, - uint8_t deviceAddress, - uint32_t subAddress, - uint8_t subaddressSize, - uint8_t *rxBuff, - uint8_t rxBuffSize); - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_CODEC_I2C_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/fsl_codec_adapter.h b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/fsl_codec_adapter.h deleted file mode 100644 index 6006754477..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/fsl_codec_adapter.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright 2017- 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_CODEC_ADAPTER_H_ -#define _FSL_CODEC_ADAPTER_H_ - -#include "fsl_codec_common.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief codec type */ -enum _codec_type -{ - kCODEC_WM8904, /*!< wm8904 */ - kCODEC_WM8960, /*!< wm8960 */ - kCODEC_WM8524, /*!< wm8524 */ - kCODEC_SGTL5000, /*!< sgtl5000 */ - kCODEC_DA7212, /*!< da7212 */ - kCODEC_CS42888, /*!< CS42888 */ - kCODEC_AK4497, /*!< AK4497 */ - kCODEC_AK4458, /*!< ak4458 */ -}; -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif -/*! - * @brief Codec initilization. - * - * @param handle codec handle. - * @param config codec configuration. - * @return kStatus_Success is success, else initial failed. - */ -status_t HAL_CODEC_Init(codec_handle_t *handle, void *config); - -/*! - * @brief Codec de-initilization. - * - * @param handle codec handle. - * @return kStatus_Success is success, else de-initial failed. - */ -status_t HAL_CODEC_Deinit(codec_handle_t *handle); - -/*! - * @brief set audio data format. - * - * @param handle codec handle. - * @param mclk master clock frequency in HZ. - * @param sampleRate sample rate in HZ. - * @param bitWidth bit width. - * @return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetFormat(codec_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth); - -/*! - * @brief set audio codec module volume. - * - * @param handle codec handle. - * @param channel audio codec play channel, can be a value or combine value of _codec_play_channel. - * @param volume volume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value. - * @return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetVolume(codec_handle_t *handle, uint32_t playChannel, uint32_t volume); - -/*! - * @brief set audio codec module mute. - * - * @param handle codec handle. - * @param channel audio codec play channel, can be a value or combine value of _codec_play_channel. - * @param isMute true is mute, false is unmute. - * @return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetMute(codec_handle_t *handle, uint32_t playChannel, bool isMute); - -/*! - * @brief set audio codec module power. - * - * @param handle codec handle. - * @param module audio codec module. - * @param powerOn true is power on, false is power down. - * @return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetPower(codec_handle_t *handle, codec_module_t module, bool powerOn); - -/*! - * @brief codec set record source. - * - * @param handle codec handle. - * @param source audio codec record source, can be a value or combine value of _codec_record_source. - * - * @return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetRecord(codec_handle_t *handle, uint32_t recordSource); - -/*! - * @brief codec set record channel. - * - * @param handle codec handle. - * @param leftRecordChannel audio codec record channel, reference _codec_record_channel, can be a value or combine value - of member in _codec_record_channel. - * @param rightRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of - member in _codec_record_channel. - - * @return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetRecordChannel(codec_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel); - -/*! - * @brief codec set play source. - * - * @param handle codec handle. - * @param playSource audio codec play source, can be a value or combine value of _codec_play_source. - * - * @return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetPlay(codec_handle_t *handle, uint32_t playSource); - -/*! - * @brief codec module control. - * - * This function is used for codec module control, support switch digital interface cmd, can be expand to support codec - * module specific feature - * - * @param handle codec handle. - * @param cmd module control cmd, reference _codec_module_ctrl_cmd. - * @param data value to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine - * of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference - * codec specific driver for detail configurations. - * @return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_ModuleControl(codec_handle_t *handle, codec_module_ctrl_cmd_t cmd, uint32_t data); - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_CODEC_ADAPTER_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/wm8904/fsl_codec_adapter.c b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/wm8904/fsl_codec_adapter.c deleted file mode 100644 index 874d3e754e..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/port/wm8904/fsl_codec_adapter.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_wm8904.h" -#include "fsl_codec_adapter.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief module capability definition */ -#define HAL_WM8904_MODULE_CAPABILITY \ - kCODEC_SupportModuleADC | kCODEC_SupportModuleDAC | kCODEC_SupportModulePGA | kCODEC_SupportModuleHeadphone | \ - kCODEC_SupportModuleLineout -#define HAL_WM8904_PLAY_CAPABILITY \ - kCODEC_SupportPlayChannelLeft0 | kCODEC_SupportPlayChannelRight0 | kCODEC_SupportPlayChannelLeft1 | \ - kCODEC_SupportPlayChannelRight1 | kCODEC_SupportPlaySourcePGA | kCODEC_SupportPlaySourceDAC -#define HAL_WM8904_RECORD_CAPABILITY \ - kCODEC_SupportRecordSourceDifferentialLine | kCODEC_SupportRecordSourceDifferentialMic | \ - kCODEC_SupportRecordSourceLineInput | kCODEC_SupportRecordSourceDigitalMic | \ - kCODEC_SupportRecordChannelLeft1 | kCODEC_SupportRecordChannelLeft2 | kCODEC_SupportRecordChannelLeft3 | \ - kCODEC_SupportRecordChannelRight1 | kCODEC_SupportRecordChannelRight2 | kCODEC_SupportRecordChannelRight3 - -/*! @brief wm8904 map protocol */ -#define HAL_WM8904_MAP_PROTOCOL(protocol) \ - (protocol == kCODEC_BusI2S ? \ - kWM8904_ProtocolI2S : \ - protocol == kCODEC_BusLeftJustified ? \ - kWM8904_ProtocolLeftJustified : \ - protocol == kCODEC_BusRightJustified ? \ - kWM8904_ProtocolRightJustified : \ - protocol == kCODEC_BusPCMA ? kWM8904_ProtocolPCMA : \ - protocol == kCODEC_BusPCMB ? kWM8904_ProtocolPCMB : kWM8904_ProtocolI2S) - -/*! @brief wm8904 map module */ -#define HAL_WM8904_MAP_MODULE(module) \ - (module == kCODEC_ModuleADC ? \ - kWM8904_ModuleADC : \ - module == kCODEC_ModuleDAC ? \ - kWM8904_ModuleDAC : \ - module == kCODEC_ModulePGA ? kWM8904_ModulePGA : \ - module == kCODEC_ModuleHeadphone ? \ - kWM8904_ModuleHeadphone : \ - module == kCODEC_ModuleLineout ? kWM8904_ModuleLineout : kWM8904_ModuleADC) - -/*! @brief wm8904 map protocol */ -#define HAL_WM8904_MAP_SAMPLERATE(sampleRATE) \ - (sampleRATE == kCODEC_AudioSampleRate8KHz ? \ - kWM8904_SampleRate8kHz : \ - sampleRATE == kCODEC_AudioSampleRate12KHz ? \ - kWM8904_SampleRate12kHz : \ - sampleRATE == kCODEC_AudioSampleRate16KHz ? \ - kWM8904_SampleRate16kHz : \ - sampleRATE == kCODEC_AudioSampleRate24KHz ? \ - kWM8904_SampleRate24kHz : \ - sampleRATE == kCODEC_AudioSampleRate32KHz ? kWM8904_SampleRate32kHz : kWM8904_SampleRate48kHz) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ - -/******************************************************************************* - * Variables - ******************************************************************************/ - -/******************************************************************************* - * Code - ******************************************************************************/ -/*! - * brief Codec initilization. - * - * param handle codec handle. - * param config codec configuration. - * return kStatus_Success is success, else initial failed. - */ -status_t HAL_CODEC_Init(codec_handle_t *handle, void *config) -{ - assert((config != NULL) && (handle != NULL)); - assert(CODEC_HANDLE_SIZE >= (sizeof(codec_handle_t) + sizeof(wm8904_handle_t)) + HAL_I2C_MASTER_HANDLE_SIZE); - - codec_config_t *codecConfig = (codec_config_t *)config; - - wm8904_config_t *wm8904Config = (wm8904_config_t *)(codecConfig->codecDevConfig); - wm8904_handle_t *wm8904Handle = (wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)); - - /* load codec capability */ - handle->codecCapability.codecModuleCapability = HAL_WM8904_MODULE_CAPABILITY; - /* add nop to aovid alignment fault, since that the compiler may generate 'strd' instruction to store 64 bit - with one instruction, but the address may not word-aligned - Will remove the __NOP in next release and use a word align address. - */ - __NOP(); - handle->codecCapability.codecPlayCapability = HAL_WM8904_PLAY_CAPABILITY; - /* add nop to aovid alignment fault, since that the compiler may generate 'strd' instruction to store 64 bit - with one instruction, but the address may not word-aligned - Will remove the __NOP in next release and use a word align address. - */ - __NOP(); - handle->codecCapability.codecRecordCapability = HAL_WM8904_RECORD_CAPABILITY; - /* codec device initialization */ - return WM8904_Init(wm8904Handle, wm8904Config); -} - -/*! - * brief Codec de-initilization. - * - * param handle codec handle. - * return kStatus_Success is success, else de-initial failed. - */ -status_t HAL_CODEC_Deinit(codec_handle_t *handle) -{ - assert(handle != NULL); - - return WM8904_Deinit((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle))); -} - -/*! - * brief set audio data format. - * - * param handle codec handle. - * param mclk master clock frequency in HZ. - * param sampleRate sample rate in HZ. - * param bitWidth bit width. - * return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetFormat(codec_handle_t *handle, uint32_t mclk, uint32_t sampleRate, uint32_t bitWidth) -{ - assert(handle != NULL); - - return WM8904_SetAudioFormat((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), mclk, - HAL_WM8904_MAP_SAMPLERATE(sampleRate), bitWidth); -} - -/*! - * brief set audio codec module volume. - * - * param handle codec handle. - * param channel audio codec play channel, can be a value or combine value of _codec_play_channel. - * param volume volume value, support 0 ~ 100, 0 is mute, 100 is the maximum volume value. - * return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetVolume(codec_handle_t *handle, uint32_t playChannel, uint32_t volume) -{ - assert(handle != NULL); - - return WM8904_SetChannelVolume((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), playChannel, volume); -} - -/*! - * brief set audio codec module mute. - * - * param handle codec handle. - * param channel audio codec play channel, can be a value or combine value of _codec_play_channel. - * param isMute true is mute, false is unmute. - * return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetMute(codec_handle_t *handle, uint32_t playChannel, bool isMute) -{ - assert(handle != NULL); - - return WM8904_SetChannelMute((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), playChannel, isMute); -} - -/*! - * brief set audio codec module power. - * - * param handle codec handle. - * param module audio codec module. - * param powerOn true is power on, false is power down. - * return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetPower(codec_handle_t *handle, codec_module_t module, bool powerOn) -{ - assert(handle != NULL); - - return WM8904_SetModulePower((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), - HAL_WM8904_MAP_MODULE(module), powerOn); -} - -/*! - * brief codec set record source. - * - * param handle codec handle. - * param source audio codec record source, can be a value or combine value of _codec_record_source. - * - * return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetRecord(codec_handle_t *handle, uint32_t recordSource) -{ - assert(handle != NULL); - - return WM8904_SetRecord((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), recordSource); -} - -/*! - * brief codec set record channel. - * - * param handle codec handle. - * param leftRecordChannel audio codec record channel, reference _codec_record_channel, can be a value or combine value - of member in _codec_record_channel. - * param rightRecordChannel audio codec record channel, reference _codec_record_channel, can be a value combine of - member in _codec_record_channel. - - * return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetRecordChannel(codec_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel) -{ - assert(handle != NULL); - - return WM8904_SetRecordChannel((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), leftRecordChannel, - rightRecordChannel); -} - -/*! - * brief codec set play source. - * - * param handle codec handle. - * param playSource audio codec play source, can be a value or combine value of _codec_play_source. - * - * return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_SetPlay(codec_handle_t *handle, uint32_t playSource) -{ - assert(handle != NULL); - - return WM8904_SetPlay((wm8904_handle_t *)((uint32_t) & (handle->codecDevHandle)), playSource); -} - -/*! - * brief codec module control. - * - * param handle codec handle. - * param cmd module control cmd, reference _codec_module_ctrl_cmd. - * param data value to write, when cmd is kCODEC_ModuleRecordSourceChannel, the data should be a value combine - * of channel and source, please reference macro CODEC_MODULE_RECORD_SOURCE_CHANNEL(source, LP, LN, RP, RN), reference - * codec specific driver for detail configurations. - * return kStatus_Success is success, else configure failed. - */ -status_t HAL_CODEC_ModuleControl(codec_handle_t *handle, codec_module_ctrl_cmd_t cmd, uint32_t data) -{ - return kStatus_CODEC_NotSupport; -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.c b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.c deleted file mode 100644 index 4581089a50..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.c +++ /dev/null @@ -1,1092 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_wm8904.h" -#if WM8904_DEBUG_REGISTER -#include "fsl_debug_console.h" -#endif -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief wm8904 volume mapping */ -#define WM8904_MAP_DAC_ADC_VOLUME(volume) (volume * (255 / 100U)) -#define WM8904_MAP_PGA_VOLUME(volume) (volume > 0x1FU ? 0x1FU : volume) -#define WM8904_MAP_HEADPHONE_LINEOUT_VOLUME(volume) (volume > 0x3FU ? 0x3FU : volume) -#define WM8904_SWAP_UINT16_BYTE_SEQUENCE(x) (__REV16(x)) -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief WM8904 update format. - * - * @param handle WM8904 handle structure. - * @param format format configurations. - * @return kStatus_Success, else failed. - */ -static status_t WM8904_UpdateFormat(wm8904_handle_t *handle, wm8904_audio_format_t *format); - -/*! - * @brief WM8904 wait on write sequencer. - * - * @param handle WM8904 handle structure. - * @return kStatus_Success, else failed. - */ -static status_t WM8904_WaitOnWriteSequencer(wm8904_handle_t *handle); -/******************************************************************************* - * Variables - ******************************************************************************/ -#if WM8904_DEBUG_REGISTER -/*! @brief register definition */ -static const uint8_t allRegisters[] = { - 0x00, 0x04, 0x05, 0x06, 0x07, 0x0A, 0x0C, 0x0E, 0x0F, 0x12, 0x14, 0x15, 0x16, 0x18, 0x19, 0x1A, 0x1B, - 0x1E, 0x1F, 0x20, 0x21, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x39, - 0x3A, 0x3B, 0x3C, 0x3D, 0x43, 0x44, 0x45, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x5A, 0x5E, 0x62, - 0x68, 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7E, 0x7F, - 0x80, 0x81, 0x82, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E, 0x8F, 0x90, 0x91, 0x92, 0x93, - 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0x9B, 0x9C, 0x9D, 0xC6, 0xF7, 0xF8}; -#endif -/******************************************************************************* - * Code - ******************************************************************************/ -static status_t WM8904_UpdateFormat(wm8904_handle_t *handle, wm8904_audio_format_t *format) -{ - status_t result; - - /* Disable SYSCLK */ - result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_2, 0x00); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* Set Clock ratio and sample rate */ - result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_1, (format->fsRatio << 10) | format->sampleRate); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* Set bit resolution */ - result = WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, 0x000C, format->bitWidth); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* Enable SYSCLK */ - result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_2, 0x1007); - if (result != kStatus_WM8904_Success) - { - return result; - } - - return kStatus_WM8904_Success; -} - -static status_t WM8904_WaitOnWriteSequencer(wm8904_handle_t *handle) -{ - status_t result; - uint16_t value; - - do - { - result = WM8904_ReadRegister(handle, WM8904_WRT_SEQUENCER_4, &value); - } while ((result == kStatus_WM8904_Success) && (value & 1)); - - return result; -} - -/*! - * brief WM8904 write register. - * - * param handle WM8904 handle structure. - * param reg register address. - * param value value to write. - * return kStatus_Success, else failed. - */ -status_t WM8904_WriteRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t value) -{ - assert(handle->config != NULL); - assert(handle->config->slaveAddress != 0U); - - uint16_t writeValue = WM8904_SWAP_UINT16_BYTE_SEQUENCE(value); - - return CODEC_I2C_Send(&(handle->i2cHandle), handle->config->slaveAddress, reg, 1U, (uint8_t *)&writeValue, 2U); -} - -/*! - * brief WM8904 write register. - * - * param handle WM8904 handle structure. - * param reg register address. - * param value value to read. - * return kStatus_Success, else failed. - */ -status_t WM8904_ReadRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t *value) -{ - assert(handle->config != NULL); - assert(handle->config->slaveAddress != 0U); - - uint8_t retval = 0; - uint16_t readValue = 0U; - - retval = CODEC_I2C_Receive(&(handle->i2cHandle), handle->config->slaveAddress, reg, 1U, (uint8_t *)&readValue, 2U); - - *value = WM8904_SWAP_UINT16_BYTE_SEQUENCE(readValue); - - return retval; -} - -/*! - * brief WM8904 modify register. - * - * param handle WM8904 handle structure. - * param reg register address. - * oaram mask register bits mask. - * param value value to write. - * return kStatus_Success, else failed. - */ -status_t WM8904_ModifyRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t mask, uint16_t value) -{ - status_t result; - uint16_t regValue; - - result = WM8904_ReadRegister(handle, reg, ®Value); - if (result != kStatus_WM8904_Success) - { - return result; - } - - regValue &= (uint16_t)~mask; - regValue |= value; - - return WM8904_WriteRegister(handle, reg, regValue); -} - -/*! - * brief Initializes WM8904. - * - * param handle WM8904 handle structure. - * param codec_config WM8904 configuration structure. - */ -status_t WM8904_Init(wm8904_handle_t *handle, wm8904_config_t *wm8904Config) -{ - assert(handle != NULL); - assert(wm8904Config != NULL); - - status_t result; - wm8904_config_t *config = wm8904Config; - handle->config = config; - - /* i2c bus initialization */ - result = CODEC_I2C_Init(&(handle->i2cHandle), wm8904Config->i2cConfig.codecI2CInstance, WM8904_I2C_BITRATE, - wm8904Config->i2cConfig.codecI2CSourceClock); - if (result != kStatus_HAL_I2cSuccess) - { - return kStatus_WM8904_Fail; - } - - /* reset */ - result = WM8904_WriteRegister(handle, WM8904_RESET, 0x0000); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* MCLK_INV=0, SYSCLK_SRC=0, TOCLK_RATE=0, OPCLK_ENA=1, - * CLK_SYS_ENA=1, CLK_DSP_ENA=1, TOCLK_ENA=1 */ - result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_2, 0x000F); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* WSEQ_ENA=1, WSEQ_WRITE_INDEX=0_0000 */ - result = WM8904_WriteRegister(handle, WM8904_WRT_SEQUENCER_0, 0x0100); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* WSEQ_ABORT=0, WSEQ_START=1, WSEQ_START_INDEX=00_0000 */ - result = WM8904_WriteRegister(handle, WM8904_WRT_SEQUENCER_3, 0x0100); - if (result != kStatus_WM8904_Success) - { - return result; - } - - result = WM8904_WaitOnWriteSequencer(handle); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* TOCLK_RATE_DIV16=0, TOCLK_RATE_x4=1, SR_MODE=0, MCLK_DIV=1 - * (Required for MMCs: SGY, KRT see erratum CE000546) */ - result = WM8904_WriteRegister(handle, WM8904_CLK_RATES_0, 0xA45F); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* INL_ENA=1, INR ENA=1 */ - result = WM8904_WriteRegister(handle, WM8904_POWER_MGMT_0, 0x0003); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* HPL_PGA_ENA=1, HPR_PGA_ENA=1 */ - result = WM8904_WriteRegister(handle, WM8904_POWER_MGMT_2, 0x0003); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* DACL_ENA=1, DACR_ENA=1, ADCL_ENA=1, ADCR_ENA=1 */ - result = WM8904_WriteRegister(handle, WM8904_POWER_MGMT_6, 0x000F); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* ADC_OSR128=1 */ - result = WM8904_WriteRegister(handle, WM8904_ANALOG_ADC_0, 0x0001); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* DACL_DATINV=0, DACR_DATINV=0, DAC_BOOST=00, LOOPBACK=0, AIFADCL_SRC=0, - * AIFADCR_SRC=1, AIFDACL_SRC=0, AIFDACR_SRC=1, ADC_COMP=0, ADC_COMPMODE=0, - * DAC_COMP=0, DAC_COMPMODE=0 */ - result = WM8904_WriteRegister(handle, WM8904_AUDIO_IF_0, 0x0050); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* DAC_MONO=0, DAC_SB_FILT-0, DAC_MUTERATE=0, DAC_UNMUTE RAMP=0, - * DAC_OSR128=1, DAC_MUTE=0, DEEMPH=0 (none) */ - result = WM8904_WriteRegister(handle, WM8904_DAC_DIG_1, 0x0040); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* LINMUTE=0, LIN_VOL=0_0101 */ - result = WM8904_WriteRegister(handle, WM8904_ANALOG_LEFT_IN_0, 0x0005); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* RINMUTE=0, RIN VOL=0_0101 LINEOUTL RMV SHORT-1, LINEOUTL ENA_OUTP=1, - * LINEOUTL_ENA_DLY=1, LINEOUTL_ENA=1, LINEOUTR_RMV_SHORT-1, - * LINEOUTR_ENA_OUTP=1 */ - result = WM8904_WriteRegister(handle, WM8904_ANALOG_RIGHT_IN_0, 0x0005); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* HPOUTL_MUTE=0, HPOUT_VU=0, HPOUTLZC=0, HPOUTL_VOL=11_1001 */ - result = WM8904_WriteRegister(handle, WM8904_ANALOG_OUT1_LEFT, 0x0039); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* HPOUTR_MUTE=0, HPOUT_VU=0, HPOUTRZC=0, HPOUTR_VOL=11_1001 */ - result = WM8904_WriteRegister(handle, WM8904_ANALOG_OUT1_RIGHT, 0x0039); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* Enable DC servos for headphone out */ - result = WM8904_WriteRegister(handle, WM8904_DC_SERVO_0, 0x0003); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* HPL_RMV_SHORT=1, HPL_ENA_OUTP=1, HPL_ENA_DLY=1, HPL_ENA=1, - * HPR_RMV_SHORT=1, HPR_ENA_OUTP=1, HPR_ENA_DLY=1, HPR_ENA=1 */ - result = WM8904_WriteRegister(handle, WM8904_ANALOG_HP_0, 0x00FF); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* CP_DYN_PWR=1 */ - result = WM8904_WriteRegister(handle, WM8904_CLS_W_0, 0x0001); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* CP_ENA=1 */ - result = WM8904_WriteRegister(handle, WM8904_CHRG_PUMP_0, 0x0001); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* set wm8904 as slave */ - result = WM8904_SetMasterSlave(handle, config->master); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* set audio format */ - result = WM8904_SetProtocol(handle, config->protocol); - if (result != kStatus_WM8904_Success) - { - return result; - } - - result = WM8904_CheckAudioFormat(handle, &config->format, config->mclk_HZ); - if (result != kStatus_WM8904_Success) - { - return result; - } - - /* set record source and channel */ - result = WM8904_SetRecord(handle, config->recordSource); - if (result != kStatus_WM8904_Success) - { - return result; - } - result = WM8904_SetRecordChannel(handle, config->recordChannelLeft, config->recordChannelRight); - if (result != kStatus_WM8904_Success) - { - return result; - } - /* set play source */ - result = WM8904_SetPlay(handle, config->playSource); - if (result != kStatus_WM8904_Success) - { - return result; - } - - return result; -} - -/*! - * brief Deinitializes the WM8904 codec. - * - * This function resets WM8904. - * - * param handle WM8904 handle structure. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_Deinit(wm8904_handle_t *handle) -{ - /* reset */ - if (WM8904_WriteRegister(handle, WM8904_RESET, 0x0000) == kStatus_WM8904_Success) - { - return CODEC_I2C_Deinit(&(handle->i2cHandle)); - } - - return kStatus_WM8904_Fail; -} - -/*! - * brief Fills the configuration structure with default values. - * - * The default values are: - * - * master = false; - * protocol = kWM8904_ProtocolI2S; - * format.fsRatio = kWM8904_FsRatio64X; - * format.sampleRate = kWM8904_SampleRate48kHz; - * format.bitWidth = kWM8904_BitWidth16; - * - * param handle WM8904 handle structure to be filled with default values. - */ -void WM8904_GetDefaultConfig(wm8904_config_t *config) -{ - memset(config, 0, sizeof(wm8904_config_t)); - - config->master = false; - config->protocol = kWM8904_ProtocolI2S; - config->format.sampleRate = kWM8904_SampleRate48kHz; - config->format.bitWidth = kWM8904_BitWidth16; -} - -/*! - * brief Sets WM8904 as master or slave. - * - * param handle WM8904 handle structure. - * param master true for master, false for slave. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetMasterSlave(wm8904_handle_t *handle, bool master) -{ - if (master) - { - /* only slave currently supported */ - return kStatus_WM8904_Fail; - } - - return kStatus_WM8904_Success; -} - -/*! - * brief Sets the audio data transfer protocol. - * - * param handle WM8904 handle structure. - * param protocol Audio transfer protocol. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetProtocol(wm8904_handle_t *handle, wm8904_protocol_t protocol) -{ - return WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, (0x0003 | (1U << 4U)), (uint16_t)protocol); -} - -/*! - * brief Select LRC polarity. - * - * param handle WM8904 handle structure. - * param polarity LRC clock polarity. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SelectLRCPolarity(wm8904_handle_t *handle, uint32_t polarity) -{ - return WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, 0x0010, polarity); -} - -/*! - * brief Enable WM8904 DAC time slot. - * - * param handle WM8904 handle structure. - * param timeslot timeslot number. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_EnableDACTDMMode(wm8904_handle_t *handle, wm8904_timeslot_t timeSlot) -{ - return WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, 3U << 12U, 1U << 13U | timeSlot << 12U); -} - -/*! - * brief Enable WM8904 ADC time slot. - * - * param handle WM8904 handle structure. - * param timeslot timeslot number. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_EnableADCTDMMode(wm8904_handle_t *handle, wm8904_timeslot_t timeSlot) -{ - return WM8904_ModifyRegister(handle, WM8904_AUDIO_IF_1, 3U << 10U, 1U << 11U | timeSlot << 10U); -} - -/*! - * brief check and update the audio data format. - * This api is used check the fsRatio setting based on the mclk and sample rate, if fsRatio setting - * is not correct, it will correct it according to mclk and sample rate. - * param handle WM8904 handle structure. - * param format audio data format - * param mclkFreq mclk frequency - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_CheckAudioFormat(wm8904_handle_t *handle, wm8904_audio_format_t *format, uint32_t mclkFreq) -{ - assert(handle && format); - - status_t result; - uint16_t mclkDiv = 0U; - uint32_t sampleRate = 0U; - uint32_t fsRatio = 0U; - - result = WM8904_ReadRegister(handle, WM8904_CLK_RATES_0, &mclkDiv); - if (kStatus_WM8904_Success != result) - { - return result; - } - - switch (format->sampleRate) - { - case kWM8904_SampleRate8kHz: - sampleRate = 8000; - break; - case kWM8904_SampleRate12kHz: - sampleRate = 12000; - break; - case kWM8904_SampleRate16kHz: - sampleRate = 16000; - break; - case kWM8904_SampleRate24kHz: - sampleRate = 24000; - break; - case kWM8904_SampleRate32kHz: - sampleRate = 32000; - break; - case kWM8904_SampleRate48kHz: - sampleRate = 48000; - break; - default: - break; - } - - fsRatio = (mclkFreq >> (mclkDiv & 0x1U)) / sampleRate; - - switch (fsRatio) - { - case 64: - format->fsRatio = kWM8904_FsRatio64X; - break; - case 128: - format->fsRatio = kWM8904_FsRatio128X; - break; - case 192: - format->fsRatio = kWM8904_FsRatio192X; - break; - case 256: - format->fsRatio = kWM8904_FsRatio256X; - break; - case 384: - format->fsRatio = kWM8904_FsRatio384X; - break; - case 512: - format->fsRatio = kWM8904_FsRatio512X; - break; - case 768: - format->fsRatio = kWM8904_FsRatio768X; - break; - case 1024: - format->fsRatio = kWM8904_FsRatio1024X; - break; - case 1408: - format->fsRatio = kWM8904_FsRatio1408X; - break; - case 1536: - format->fsRatio = kWM8904_FsRatio1536X; - break; - default: - break; - } - - return WM8904_UpdateFormat(handle, format); -} - -/*! - * brief Sets the audio data format. - * - * param handle WM8904 handle structure. - * param sysclk System clock frequency for codec, user should pay attention to this parater, sysclk is caculate as - * SYSCLK = MCLK / MCLKDIV, MCLKDIV is bit0 of WM8904_CLK_RATES_0. - * param sampleRate Sample rate frequency in Hz. - * param bitWidth Audio data bit width. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetAudioFormat(wm8904_handle_t *handle, uint32_t sysclk, uint32_t sampleRate, uint32_t bitWidth) -{ - status_t result; - wm8904_audio_format_t format; - uint32_t ratio = 0; - - switch (sampleRate) - { - case 8000: - format.sampleRate = kWM8904_SampleRate8kHz; - break; - case 11025: - case 12000: - format.sampleRate = kWM8904_SampleRate12kHz; - break; - case 16000: - format.sampleRate = kWM8904_SampleRate16kHz; - break; - case 22050: - case 24000: - format.sampleRate = kWM8904_SampleRate24kHz; - break; - case 32000: - format.sampleRate = kWM8904_SampleRate32kHz; - break; - case 44100: - case 48000: - format.sampleRate = kWM8904_SampleRate48kHz; - break; - default: - return kStatus_WM8904_Fail; - } - - switch (bitWidth) - { - case 16: - format.bitWidth = kWM8904_BitWidth16; - break; - case 20: - format.bitWidth = kWM8904_BitWidth20; - break; - case 24: - format.bitWidth = kWM8904_BitWidth24; - break; - case 32: - format.bitWidth = kWM8904_BitWidth32; - break; - default: - break; - } - - ratio = sysclk / sampleRate; - switch (ratio) - { - case 64: - format.fsRatio = kWM8904_FsRatio64X; - break; - case 128: - format.fsRatio = kWM8904_FsRatio128X; - break; - case 192: - format.fsRatio = kWM8904_FsRatio192X; - break; - case 256: - format.fsRatio = kWM8904_FsRatio256X; - break; - case 384: - format.fsRatio = kWM8904_FsRatio384X; - break; - case 512: - format.fsRatio = kWM8904_FsRatio512X; - break; - case 768: - format.fsRatio = kWM8904_FsRatio768X; - break; - case 1024: - format.fsRatio = kWM8904_FsRatio1024X; - break; - case 1408: - format.fsRatio = kWM8904_FsRatio1408X; - break; - case 1536: - format.fsRatio = kWM8904_FsRatio1536X; - break; - default: - return kStatus_WM8904_Fail; - } - - result = WM8904_UpdateFormat(handle, &format); - - return result; -} - -/*! - * brief Sets the headphone output volume. - * - * The parameter should be from 0 to 63. - * The resulting volume will be (parameter - 57 dB). - * 0 for -57 dB, 57 for 0 dB, 63 for +6 dB etc. - * - * param handle WM8904 handle structure. - * param volumeLeft Volume of the left channel. - * param volumeRight Volume of the right channel. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetVolume(wm8904_handle_t *handle, uint16_t volumeLeft, uint16_t volumeRight) -{ - status_t result; - - result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_LEFT, 0x3F, volumeLeft); - if (result != kStatus_WM8904_Success) - { - return result; - } - - result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_RIGHT, 0xBF, volumeRight | 0x0080); - if (result != kStatus_WM8904_Success) - { - return result; - } - - return kStatus_WM8904_Success; -} - -/*! - * brief Sets the headphone output mute. - * - * param handle WM8904 handle structure. - * param muteLeft true to mute left channel, false to unmute. - * param muteRight true to mute right channel, false to unmute. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetMute(wm8904_handle_t *handle, bool muteLeft, bool muteRight) -{ - status_t result; - uint16_t left = muteLeft ? 0x0100 : 0x0000; - uint16_t right = muteRight ? 0x0100 : 0x0000; - - result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_LEFT, 0x0100, left); - if (result != kStatus_WM8904_Success) - { - return result; - } - - result = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_RIGHT, 0x0180, right | 0x0080); - if (result != kStatus_WM8904_Success) - { - return result; - } - - return kStatus_WM8904_Success; -} - -#if WM8904_DEBUG_REGISTER -/*! - * brief Reads content of all WM8904 registers and prints it to debug console. - * - * param handle WM8904 handle structure. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_PrintRegisters(wm8904_handle_t *handle) -{ - status_t result; - uint16_t value; - uint32_t i; - - for (i = 0; i < sizeof(allRegisters); i++) - { - result = WM8904_ReadRegister(handle, allRegisters[i], &value); - if (result != kStatus_WM8904_Success) - { - PRINTF("\r\n"); - return result; - } - PRINTF("%s", ((i % 8) == 0) ? "\r\n" : "\t"); - PRINTF("%02X:%04X", allRegisters[i], value); - } - - PRINTF("\r\n"); - return result; -} -#endif - -/*! - * brief Sets the channel output volume. - * - * The parameter should be from 0 to 100. - * The resulting volume will be. - * 0 for mute, 100 for maximum volume value. - * - * param handle codec handle structure. - * param channel codec channel. - * param volume volume value. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetChannelVolume(wm8904_handle_t *handle, uint32_t channel, uint32_t volume) -{ - status_t ret = kStatus_Fail; - volume = WM8904_MAP_HEADPHONE_LINEOUT_VOLUME(volume); - - /* headphone left channel */ - if (channel & kWM8904_HeadphoneLeft) - { - ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_LEFT, volume == 0U ? 0x100U : 0x3FU, - volume == 0U ? 0x100U : (volume)); - } - /* headphone right channel */ - if (channel & kWM8904_HeadphoneRight) - { - ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_RIGHT, volume == 0U ? 0x100U : 0xBFU, - volume == 0U ? 0x100U : (volume | 0x80U)); - } - /* line out left channel */ - if (channel & kWM8904_LineoutLeft) - { - ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT2_LEFT, volume == 0U ? 0x100U : 0x3FU, - volume == 0U ? 0x100U : (volume)); - } - /* line out right channel */ - if (channel & kWM8904_LineoutRight) - { - ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT2_RIGHT, volume == 0U ? 0x100U : 0xBFU, - volume == 0U ? 0x100U : (volume | 0x80U)); - } - - return ret; -} - -/*! - * brief Sets the channel mute. - * - * param handle codec handle structure. - * param channel codec module name. - * param isMute true is mute, false unmute. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetChannelMute(wm8904_handle_t *handle, uint32_t channel, bool isMute) -{ - status_t ret = kStatus_Fail; - uint16_t regValue = 0U, regMask = 0U; - - regValue = isMute ? 0x180U : 0x80U; - regMask = 0x100U; - - /* headphone left channel */ - if (channel & kWM8904_HeadphoneLeft) - { - ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_LEFT, regMask, regValue); - } - - /* headphone right channel */ - if (channel & kWM8904_HeadphoneRight) - { - ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT1_RIGHT, regMask, regValue); - } - - /* line out left channel */ - if (channel & kWM8904_LineoutLeft) - { - ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT2_LEFT, regMask, regValue); - } - - /* line out right channel */ - if (channel & kWM8904_LineoutRight) - { - ret = WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT2_RIGHT, regMask, regValue); - } - - return ret; -} - -/*! - * brief SET the module output power. - * - * param handle WM8904 handle structure. - * param module wm8904 module. - * param isEnabled, true is power on, false is power down. - * - * return kStatus_WM8904_Success if successful, different code otherwise.. - */ -status_t WM8904_SetModulePower(wm8904_handle_t *handle, wm8904_module_t module, bool isEnabled) -{ - uint8_t regAddr = 0, regBitMask = 0U, regValue = 0U; - - switch (module) - { - case kWM8904_ModuleADC: - regAddr = WM8904_POWER_MGMT_6; - regBitMask = 3U; - regValue = isEnabled ? 3U : 0U; - break; - case kWM8904_ModuleDAC: - regAddr = WM8904_POWER_MGMT_6; - regBitMask = 0xCU; - regValue = isEnabled ? 0xCU : 0U; - - break; - case kWM8904_ModulePGA: - regAddr = WM8904_POWER_MGMT_0; - regBitMask = 3U; - regValue = isEnabled ? 3U : 0U; - - break; - case kWM8904_ModuleHeadphone: - regAddr = WM8904_POWER_MGMT_2; - regBitMask = 3U; - regValue = isEnabled ? 3U : 0U; - break; - case kWM8904_ModuleLineout: - regAddr = WM8904_POWER_MGMT_3; - regBitMask = 3U; - regValue = isEnabled ? 3U : 0U; - break; - default: - return kStatus_InvalidArgument; - } - - return WM8904_ModifyRegister(handle, regAddr, regBitMask, regValue); -} - -/*! - * brief SET the WM8904 record source. - * - * param handle WM8904 handle structure. - * param recordSource record source , can be a value of kWM8904_ModuleRecordSourceDifferentialLine, - * kWM8904_ModuleRecordSourceDifferentialMic, kWM8904_ModuleRecordSourceSingleEndMic, - * kWM8904_ModuleRecordSourceDigitalMic. - * - * return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetRecord(wm8904_handle_t *handle, uint32_t recordSource) -{ - uint8_t regLeftAddr = WM8904_ANALOG_LEFT_IN_1, regRightAddr = WM8904_ANALOG_RIGHT_IN_1; - uint16_t regLeftValue = 0U, regRightValue = 0U, regBitMask; - status_t ret = kStatus_Success; - - switch (recordSource) - { - case kWM8904_RecordSourceDifferentialLine: - regLeftValue = 1U; - regRightValue = 1U; - regBitMask = 0x3FU; - break; - case kWM8904_RecordSourceDifferentialMic: - regLeftValue = 2U; - regRightValue = 2U; - regBitMask = 0x3FU; - break; - case kWM8904_RecordSourceLineInput: - regLeftValue = 0U; - regRightValue = 0U; - regBitMask = 0x3FU; - break; - case kWM8904_RecordSourceDigitalMic: - regLeftValue = (1U << 12U); - regLeftAddr = WM8904_DAC_DIG_0; - regRightAddr = 0U; - regBitMask = 1U << 12U; - break; - - default: - return kStatus_InvalidArgument; - } - - ret = WM8904_ModifyRegister(handle, regLeftAddr, regBitMask, regLeftValue); - - if ((ret == kStatus_Success) && (regRightAddr)) - { - return WM8904_ModifyRegister(handle, regRightAddr, regBitMask, regRightValue); - } - - return kStatus_Success; -} - -/*! - * brief SET the WM8904 record source. - * - * param handle WM8904 handle structure. - * param leftRecordChannel channel number of left record channel when using differential source, channel number of - * single end left channel when using single end source, channel number of digital mic when using digital mic source. - * param rightRecordChannel channel number of right record channel when using differential source, channel number - * of single end right channel when using single end source. - * - * return kStatus_WM8904_Success if successful, different code otherwise.. - */ -status_t WM8904_SetRecordChannel(wm8904_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel) -{ - uint8_t regLeftAddr = WM8904_ANALOG_LEFT_IN_1, regRightAddr = WM8904_ANALOG_RIGHT_IN_1; - uint16_t regLeftValue = 0U, regRightValue = 0U, regBitMask; - status_t ret = kStatus_Success; - uint8_t leftPositiveChannel = 0U, leftNegativeChannel = 0U, rightPositiveChannel = 0U, rightNegativeChannel = 0U; - - if (leftRecordChannel & kWM8904_RecordChannelDifferentialPositive1) - { - leftPositiveChannel = 0U; - } - else if (leftRecordChannel & kWM8904_RecordChannelDifferentialPositive2) - { - leftPositiveChannel = 1U; - } - else - { - leftPositiveChannel = 2U; - } - - if (leftRecordChannel & kWM8904_RecordChannelDifferentialNegative1) - { - leftNegativeChannel = 0U; - } - else if (leftRecordChannel & kWM8904_RecordChannelDifferentialNegative2) - { - leftNegativeChannel = 1U; - } - else if (leftRecordChannel & kWM8904_RecordChannelDifferentialNegative3) - { - leftNegativeChannel = 2U; - } - else - { - leftNegativeChannel = leftPositiveChannel; - } - - if (rightRecordChannel & kWM8904_RecordChannelDifferentialPositive1) - { - rightPositiveChannel = 0U; - } - else if (rightRecordChannel & kWM8904_RecordChannelDifferentialPositive2) - { - rightPositiveChannel = 1U; - } - else - { - rightPositiveChannel = 2U; - } - - if (rightRecordChannel & kWM8904_RecordChannelDifferentialNegative1) - { - rightNegativeChannel = 0U; - } - else if (rightRecordChannel & kWM8904_RecordChannelDifferentialNegative2) - { - rightNegativeChannel = 1U; - } - else if (rightRecordChannel & kWM8904_RecordChannelDifferentialNegative3) - { - rightNegativeChannel = 2U; - } - else - { - rightNegativeChannel = rightPositiveChannel; - } - - regLeftValue = ((leftNegativeChannel & 3U) << 4U) | ((leftPositiveChannel & 3U) << 2U); - regRightValue = ((rightNegativeChannel & 3U) << 4U) | ((rightPositiveChannel & 3U) << 2U); - regBitMask = 0x3CU; - - ret = WM8904_ModifyRegister(handle, regLeftAddr, regBitMask, regLeftValue); - - if ((ret == kStatus_Success) && (regRightAddr)) - { - return WM8904_ModifyRegister(handle, regRightAddr, regBitMask, regRightValue); - } - - return kStatus_Success; -} - -/*! - * brief SET the WM8904 play source. - * - * param handle WM8904 handle structure. - * param playSource play source , can be a value of kWM8904_PlaySourcePGA/kWM8904_PlaySourceDAC. - * - * return kStatus_WM8904_Success if successful, different code otherwise.. - */ -status_t WM8904_SetPlay(wm8904_handle_t *handle, uint32_t playSource) -{ - uint16_t regValue = 0U, regBitMask = 0xFU; - - /* source form PGA*/ - if (playSource == kWM8904_PlaySourcePGA) - { - regValue |= (3U << 2U) | 3U; - } - /* source from DAC*/ - if (playSource == kWM8904_PlaySourceDAC) - { - regValue &= ~((3U << 2U) | 3U); - } - - return WM8904_ModifyRegister(handle, WM8904_ANALOG_OUT12_ZC, regBitMask, regValue); -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.h b/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.h deleted file mode 100644 index dc94820dbb..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/components/codec/wm8904/fsl_wm8904.h +++ /dev/null @@ -1,496 +0,0 @@ -/* - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_WM8904_H_ -#define _FSL_WM8904_H_ - -#include "fsl_common.h" -#include "fsl_codec_i2c.h" -/*! - * @addtogroup wm8904 - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @name Driver version */ -/*@{*/ -/*! @brief WM8904 driver version 2.1.0. */ -#define FSL_WM8904_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) -/*@}*/ - -/*! @brief wm8904 handle size */ -#ifndef WM8904_HANDLE_SIZE -#define WM8904_HANDLE_SIZE (100U) -#endif -/*! @brief wm8904 debug macro */ -#ifndef WM8904_DEBUG_REGISTER -#define WM8904_DEBUG_REGISTER 0 -#endif - -/*! @brief WM8904 register map*/ -#define WM8904_RESET (0x00) -#define WM8904_ANALOG_ADC_0 (0x0A) -#define WM8904_POWER_MGMT_0 (0x0C) -#define WM8904_POWER_MGMT_2 (0x0E) -#define WM8904_POWER_MGMT_3 (0x0F) -#define WM8904_POWER_MGMT_6 (0x12) -#define WM8904_CLK_RATES_0 (0x14) -#define WM8904_CLK_RATES_1 (0x15) -#define WM8904_CLK_RATES_2 (0x16) -#define WM8904_AUDIO_IF_0 (0x18) -#define WM8904_AUDIO_IF_1 (0x19) -#define WM8904_AUDIO_IF_2 (0x1A) -#define WM8904_AUDIO_IF_3 (0x1B) -#define WM8904_DAC_DIG_1 (0x21) -#define WM8904_DAC_DIG_0 (0x27) -#define WM8904_ANALOG_LEFT_IN_0 (0x2C) -#define WM8904_ANALOG_RIGHT_IN_0 (0x2D) -#define WM8904_ANALOG_LEFT_IN_1 (0x2E) -#define WM8904_ANALOG_RIGHT_IN_1 (0x2F) -#define WM8904_ANALOG_OUT1_LEFT (0x39) -#define WM8904_ANALOG_OUT1_RIGHT (0x3A) -#define WM8904_ANALOG_OUT12_ZC (0x3D) -#define WM8904_DC_SERVO_0 (0x43) -#define WM8904_ANALOG_HP_0 (0x5A) -#define WM8904_CHRG_PUMP_0 (0x62) -#define WM8904_CLS_W_0 (0x68) -#define WM8904_WRT_SEQUENCER_0 (0x6C) -#define WM8904_WRT_SEQUENCER_3 (0x6F) -#define WM8904_WRT_SEQUENCER_4 (0x70) -#define WM8904_DAC_DIGITAL_VOLUME_LEFT (0x1E) -#define WM8904_DAC_DIGITAL_VOLUME_RIGHT (0x1F) -#define WM8904_ADC_DIGITAL_VOLUME_LEFT (0x24) -#define WM8904_ADC_DIGITAL_VOLUME_RIGHT (0x25) -#define WM8904_ANALOG_OUT2_LEFT (0x3B) -#define WM8904_ANALOG_OUT2_RIGHT (0x3C) - -/*! @brief WM8904 I2C address. */ -#define WM8904_I2C_ADDRESS (0x1A) - -/*! @brief WM8904 I2C bit rate. */ -#define WM8904_I2C_BITRATE (400000U) - -/*! @brief WM8904 status return codes. */ -enum _wm8904_status -{ - kStatus_WM8904_Success = 0x0, /*!< Success */ - kStatus_WM8904_Fail = 0x1 /*!< Failure */ -}; - -/*! @brief WM8904 lrc polarity. */ -enum _wm8904_lrc_polarity -{ - kWM8904_LRCPolarityNormal = 0U, /*!< LRC polarity normal */ - kWM8904_LRCPolarityInverted = 1U << 4U, /*!< LRC polarity inverted */ -}; - -/*! @brief wm8904 module value*/ -typedef enum _wm8904_module -{ - kWM8904_ModuleADC = 0, /*!< moduel ADC */ - kWM8904_ModuleDAC = 1, /*!< module DAC */ - kWM8904_ModulePGA = 2, /*!< module PGA */ - kWM8904_ModuleHeadphone = 3, /*!< module headphone */ - kWM8904_ModuleLineout = 4, /*!< module line out */ -} wm8904_module_t; - -/*! @brief wm8904 play channel */ -enum _wm8904_play_channel -{ - kWM8904_HeadphoneLeft = 1U, - kWM8904_HeadphoneRight = 2U, - kWM8904_LineoutLeft = 4U, - kWM8904_LineoutRight = 8U, -}; - -/*! @brief WM8904 time slot. */ -typedef enum _wm8904_timeslot -{ - kWM8904_TimeSlot0 = 0U, /*!< time slot0 */ - kWM8904_TimeSlot1 = 1U, /*!< time slot1 */ -} wm8904_timeslot_t; - -/*! @brief The audio data transfer protocol. */ -typedef enum _wm8904_protocol -{ - kWM8904_ProtocolI2S = 0x2, /*!< I2S type */ - kWM8904_ProtocolLeftJustified = 0x1, /*!< Left justified mode */ - kWM8904_ProtocolRightJustified = 0x0, /*!< Right justified mode */ - kWM8904_ProtocolPCMA = 0x3, /*!< PCM A mode */ - kWM8904_ProtocolPCMB = 0x3 | (1 << 4), /*!< PCM B mode */ -} wm8904_protocol_t; - -/*! @brief The SYSCLK / fs ratio. */ -typedef enum _wm8904_fs_ratio -{ - kWM8904_FsRatio64X = 0x0, /*!< SYSCLK is 64 * sample rate * frame width */ - kWM8904_FsRatio128X = 0x1, /*!< SYSCLK is 128 * sample rate * frame width */ - kWM8904_FsRatio192X = 0x2, /*!< SYSCLK is 192 * sample rate * frame width */ - kWM8904_FsRatio256X = 0x3, /*!< SYSCLK is 256 * sample rate * frame width */ - kWM8904_FsRatio384X = 0x4, /*!< SYSCLK is 384 * sample rate * frame width */ - kWM8904_FsRatio512X = 0x5, /*!< SYSCLK is 512 * sample rate * frame width */ - kWM8904_FsRatio768X = 0x6, /*!< SYSCLK is 768 * sample rate * frame width */ - kWM8904_FsRatio1024X = 0x7, /*!< SYSCLK is 1024 * sample rate * frame width */ - kWM8904_FsRatio1408X = 0x8, /*!< SYSCLK is 1408 * sample rate * frame width */ - kWM8904_FsRatio1536X = 0x9 /*!< SYSCLK is 1536 * sample rate * frame width */ -} wm8904_fs_ratio_t; - -/*! @brief Sample rate. */ -typedef enum _wm8904_sample_rate -{ - kWM8904_SampleRate8kHz = 0x0, /*!< 8 kHz */ - kWM8904_SampleRate12kHz = 0x1, /*!< 11.025kHz, 12kHz */ - kWM8904_SampleRate16kHz = 0x2, /*!< 16kHz */ - kWM8904_SampleRate24kHz = 0x3, /*!< 22.05kHz, 24kHz */ - kWM8904_SampleRate32kHz = 0x4, /*!< 32kHz */ - kWM8904_SampleRate48kHz = 0x5 /*!< 44.1kHz, 48kHz */ -} wm8904_sample_rate_t; - -/*! @brief Bit width. */ -typedef enum _wm8904_bit_width -{ - kWM8904_BitWidth16 = 0x0, /*!< 16 bits */ - kWM8904_BitWidth20 = 0x1, /*!< 20 bits */ - kWM8904_BitWidth24 = 0x2, /*!< 24 bits */ - kWM8904_BitWidth32 = 0x3 /*!< 32 bits */ -} wm8904_bit_width_t; - -/*! @brief wm8904 record source */ -enum _wm8904_record_source -{ - kWM8904_RecordSourceDifferentialLine = 1U, /*!< record source from differential line */ - kWM8904_RecordSourceLineInput = 2U, /*!< record source from line input */ - kWM8904_RecordSourceDifferentialMic = 4U, /*!< record source from differential mic */ - kWM8904_RecordSourceDigitalMic = 8U, /*!< record source from digital microphone */ -}; - -/*! @brief wm8904 record channel*/ -enum _wm8904_record_channel -{ - kWM8904_RecordChannelLeft1 = 1U, /*!< left record channel 1 */ - kWM8904_RecordChannelLeft2 = 2U, /*!< left record channel 2 */ - kWM8904_RecordChannelLeft3 = 4U, /*!< left record channel 3 */ - kWM8904_RecordChannelRight1 = 1U, /*!< right record channel 1 */ - kWM8904_RecordChannelRight2 = 2U, /*!< right record channel 2 */ - kWM8904_RecordChannelRight3 = 4U, /*!< right record channel 3 */ - kWM8904_RecordChannelDifferentialPositive1 = 1U, /*!< differential positive record channel 1 */ - kWM8904_RecordChannelDifferentialPositive2 = 2U, /*!< differential positive record channel 2 */ - kWM8904_RecordChannelDifferentialPositive3 = 4U, /*!< differential positive record channel 3 */ - kWM8904_RecordChannelDifferentialNegative1 = 8U, /*!< differential negative record channel 1 */ - kWM8904_RecordChannelDifferentialNegative2 = 16U, /*!< differential negative record channel 2 */ - kWM8904_RecordChannelDifferentialNegative3 = 32U, /*!< differential negative record channel 3 */ -}; - -/*! @brief wm8904 play source*/ -enum _wm8904_play_source -{ - kWM8904_PlaySourcePGA = 1U, /*!< play source PGA, bypass ADC */ - kWM8904_PlaySourceDAC = 4U, /*!< play source Input3 */ -}; - -/*! @brief Audio format configuration. */ -typedef struct _wm8904_audio_format -{ - wm8904_fs_ratio_t fsRatio; /*!< SYSCLK / fs ratio */ - wm8904_sample_rate_t sampleRate; /*!< Sample rate */ - wm8904_bit_width_t bitWidth; /*!< Bit width */ -} wm8904_audio_format_t; - -/*! @brief Configuration structure of WM8904.*/ -typedef struct _wm8904_config -{ - bool master; /*!< Master or slave */ - wm8904_protocol_t protocol; /*!< Audio transfer protocol */ - wm8904_audio_format_t format; /*!< Audio format */ - uint32_t mclk_HZ; /*!< MCLK frequency value */ - - uint16_t recordSource; /*!< record source */ - uint16_t recordChannelLeft; /*!< record channel */ - uint16_t recordChannelRight; /*!< record channel */ - uint16_t playSource; /*!< play source */ - - uint8_t slaveAddress; /*!< code device slave address */ - codec_i2c_config_t i2cConfig; /*!< i2c bus configuration */ -} wm8904_config_t; - -/*! @brief wm8904 codec handler - * Applicationi should allocate a buffer with WM8904_HANDLE_SIZE for handle definition, such as - * uint8_t wm8904HandleBuffer[WM8904_HANDLE_SIZE]; - * wm8904_handle_t *wm8904Handle = wm8904HandleBuffer; - */ -typedef struct _wm8904_handle -{ - wm8904_config_t *config; /*!< wm8904 config pointer */ - void *i2cHandle; /*!< i2c handle */ -} wm8904_handle_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @brief WM8904 write register. - * - * @param handle WM8904 handle structure. - * @param reg register address. - * @param value value to write. - * @return kStatus_Success, else failed. - */ -status_t WM8904_WriteRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t value); - -/*! - * @brief WM8904 write register. - * - * @param handle WM8904 handle structure. - * @param reg register address. - * @param value value to read. - * @return kStatus_Success, else failed. - */ -status_t WM8904_ReadRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t *value); - -/*! - * @brief WM8904 modify register. - * - * @param handle WM8904 handle structure. - * @param reg register address. - * @oaram mask register bits mask. - * @param value value to write. - * @return kStatus_Success, else failed. - */ -status_t WM8904_ModifyRegister(wm8904_handle_t *handle, uint8_t reg, uint16_t mask, uint16_t value); - -/*! - * @brief Initializes WM8904. - * - * @param handle WM8904 handle structure. - * @param codec_config WM8904 configuration structure. - */ -status_t WM8904_Init(wm8904_handle_t *handle, wm8904_config_t *wm8904_config); - -/*! - * @brief Deinitializes the WM8904 codec. - * - * This function resets WM8904. - * - * @param handle WM8904 handle structure. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_Deinit(wm8904_handle_t *handle); - -/*! - * @brief Fills the configuration structure with default values. - * - * The default values are: - * - * master = false; - * protocol = kWM8904_ProtocolI2S; - * format.fsRatio = kWM8904_FsRatio64X; - * format.sampleRate = kWM8904_SampleRate48kHz; - * format.bitWidth = kWM8904_BitWidth16; - * - * @param handle WM8904 handle structure to be filled with default values. - */ -void WM8904_GetDefaultConfig(wm8904_config_t *config); - -/*! - * @brief Sets WM8904 as master or slave. - * - * @param handle WM8904 handle structure. - * @param master true for master, false for slave. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetMasterSlave(wm8904_handle_t *handle, bool master); - -/*! - * @brief Sets the audio data transfer protocol. - * - * @param handle WM8904 handle structure. - * @param protocol Audio transfer protocol. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetProtocol(wm8904_handle_t *handle, wm8904_protocol_t protocol); - -/*! - * @brief Sets the audio data format. - * - * @param handle WM8904 handle structure. - * @param sysclk System clock frequency for codec, user should pay attention to this parater, sysclk is caculate as - * SYSCLK = MCLK / MCLKDIV, MCLKDIV is bit0 of WM8904_CLK_RATES_0. - * @param sampleRate Sample rate frequency in Hz. - * @param bitWidth Audio data bit width. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetAudioFormat(wm8904_handle_t *handle, uint32_t sysclk, uint32_t sampleRate, uint32_t bitWidth); - -/*! - * @brief check and update the audio data format. - * This api is used check the fsRatio setting based on the mclk and sample rate, if fsRatio setting - * is not correct, it will correct it according to mclk and sample rate. - * @param handle WM8904 handle structure. - * @param format audio data format - * @param mclkFreq mclk frequency - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_CheckAudioFormat(wm8904_handle_t *handle, wm8904_audio_format_t *format, uint32_t mclkFreq); - -/*! - * @brief Sets the module output volume. - * - * The parameter should be from 0 to 100. - * The resulting volume will be. - * 0 for mute, 100 for maximum volume value. - * - * @param handle WM8904 handle structure. - * @param module wm8904 module name. - * @param volume volume value. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetVolume(wm8904_handle_t *handle, uint16_t volumeLeft, uint16_t volumeRight); - -/*! - * @brief Sets the headphone output mute. - * - * @param handle WM8904 handle structure. - * @param muteLeft true to mute left channel, false to unmute. - * @param muteRight true to mute right channel, false to unmute. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetMute(wm8904_handle_t *handle, bool muteLeft, bool muteRight); - -/*! - * @brief Select LRC polarity. - * - * @param handle WM8904 handle structure. - * @param polarity LRC clock polarity. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SelectLRCPolarity(wm8904_handle_t *handle, uint32_t polarity); - -/*! - * @brief Enable WM8904 DAC time slot. - * - * @param handle WM8904 handle structure. - * @param timeslot timeslot number. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_EnableDACTDMMode(wm8904_handle_t *handle, wm8904_timeslot_t timeSlot); - -/*! - * @brief Enable WM8904 ADC time slot. - * - * @param handle WM8904 handle structure. - * @param timeslot timeslot number. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_EnableADCTDMMode(wm8904_handle_t *handle, wm8904_timeslot_t timeSlot); - -#if WM8904_DEBUG_REGISTER -/*! - * @brief Reads content of all WM8904 registers and prints it to debug console. - * - * @param handle WM8904 handle structure. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_PrintRegisters(wm8904_handle_t *handle); -#endif - -/*! - * brief SET the module output power. - * - * param handle WM8904 handle structure. - * param module wm8904 module. - * param isEnabled, true is power on, false is power down. - * - * return kStatus_WM8904_Success if successful, different code otherwise.. - */ -status_t WM8904_SetModulePower(wm8904_handle_t *handle, wm8904_module_t module, bool isEnabled); - -/*! - * @brief Sets the channel output volume. - * - * The parameter should be from 0 to 100. - * The resulting volume will be. - * 0 for mute, 100 for maximum volume value. - * - * param handle codec handle structure. - * @param channel codec channel. - * @param volume volume value. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetChannelVolume(wm8904_handle_t *handle, uint32_t channel, uint32_t volume); - -/*! - * @brief SET the WM8904 record source. - * - * @param handle WM8904 handle structure. - * @param recordSource record source , can be a value of kCODEC_ModuleRecordSourceDifferentialLine, - * kCODEC_ModuleRecordSourceDifferentialMic, kCODEC_ModuleRecordSourceSingleEndMic, kCODEC_ModuleRecordSourceDigitalMic. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetRecord(wm8904_handle_t *handle, uint32_t recordSource); - -/*! - * @brief SET the WM8904 record source. - * - * @param handle WM8904 handle structure. - * @param leftRecordChannel channel number of left record channel when using differential source, channel number of - * single end left channel when using single end source, channel number of digital mic when using digital mic source. - * @param rightRecordChannel channel number of right record channel when using differential source, channel number - * of single end right channel when using single end source. - * - * @return kStatus_WM8904_Success if successful, different code otherwise.. - */ -status_t WM8904_SetRecordChannel(wm8904_handle_t *handle, uint32_t leftRecordChannel, uint32_t rightRecordChannel); - -/*! - * @brief SET the WM8904 play source. - * - * @param handle WM8904 handle structure. - * @param playSource play source , can be a value of kCODEC_ModuleHeadphoneSourcePGA, - * kCODEC_ModuleHeadphoneSourceDAC, kCODEC_ModuleLineoutSourcePGA, kCODEC_ModuleLineoutSourceDAC. - * - * @return kStatus_WM8904_Success if successful, different code otherwise.. - */ -status_t WM8904_SetPlay(wm8904_handle_t *handle, uint32_t playSource); - -/*! - * @brief Sets the channel mute. - * - * @param handle codec handle structure. - * @param module codec module name. - * @param isMute true is mute, false unmute. - * - * @return kStatus_WM8904_Success if successful, different code otherwise. - */ -status_t WM8904_SetChannelMute(wm8904_handle_t *handle, uint32_t channel, bool isMute); - -#if defined(__cplusplus) -} -#endif - -/*! @} */ - -#endif /* _FSL_WM8904_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/common/fsl_sdmmc_common.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/common/fsl_sdmmc_common.c new file mode 100644 index 0000000000..7ae64f4591 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/common/fsl_sdmmc_common.c @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sdmmc_common.h" +/******************************************************************************* + * Variables + ******************************************************************************/ +#if SDMMCHOST_SUPPORT_DDR50 || SDMMCHOST_SUPPORT_SDR104 || SDMMCHOST_SUPPORT_SDR50 || SDMMCHOST_SUPPORT_HS200 || \ + SDMMCHOST_SUPPORT_HS400 +/* sdmmc tuning block */ +const uint32_t SDMMC_TuningBlockPattern4Bit[16U] = { + 0xFF0FFF00U, 0xFFCCC3CCU, 0xC33CCCFFU, 0xFEFFFEEFU, 0xFFDFFFDDU, 0xFFFBFFFBU, 0xBFFF7FFFU, 0x77F7BDEFU, + 0xFFF0FFF0U, 0x0FFCCC3CU, 0xCC33CCCFU, 0xFFEFFFEEU, 0xFFFDFFFDU, 0xDFFFBFFFU, 0xBBFFF7FFU, 0xF77F7BDEU, +}; +const uint32_t SDMMC_TuningBlockPattern8Bit[32U] = { + 0xffff00ffU, 0xffff0000U, 0xffffccccU, 0xcc33ccccU, 0xcc3333ccU, 0xccccffffU, 0xffeeffffU, 0xffeeeeffU, + 0xffffddffU, 0xffffddddU, 0xffffffbbU, 0xffffffbbU, 0xbbffffffU, 0x77ffffffU, 0x7777ff77U, 0xbbddeeffU, + 0xffffff00U, 0xffffff00U, 0x00ffffccU, 0xcccc33ccU, 0xcccc3333U, 0xccccccffU, 0xffffeeffU, 0xffffeeeeU, + 0xffffffddU, 0xffffffddU, 0xddffffffU, 0xbbffffffU, 0xbbbbffffU, 0xff77ffffU, 0xff7777ffU, 0x77bbddeeU, +}; +#endif +/******************************************************************************* + * Code + ******************************************************************************/ +status_t SDMMC_SelectCard(sdmmchost_t *host, uint32_t relativeAddress, bool isSelected) +{ + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDMMC_SelectCard; + if (isSelected) + { + command.argument = relativeAddress << 16U; + command.responseType = kCARD_ResponseTypeR1; + } + else + { + command.argument = 0U; + command.responseType = kCARD_ResponseTypeNone; + } + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(host, &content); + if ((kStatus_Success != error) || ((command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG) != 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Wait until card to transfer state */ + return kStatus_Success; +} + +status_t SDMMC_SendApplicationCommand(sdmmchost_t *host, uint32_t relativeAddress) +{ + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDMMC_ApplicationCommand; + command.argument = (relativeAddress << 16U); + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(host, &content); + if ((kStatus_Success != error) || ((command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG) != 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + if (0U == (command.response[0U] & SDMMC_MASK(kSDMMC_R1ApplicationCommandFlag))) + { + return kStatus_SDMMC_CardNotSupport; + } + + return kStatus_Success; +} + +status_t SDMMC_SetBlockCount(sdmmchost_t *host, uint32_t blockCount) +{ + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDMMC_SetBlockCount; + command.argument = blockCount; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(host, &content); + if ((kStatus_Success != error) || ((command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG) != 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_GoIdle(sdmmchost_t *host) +{ + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDMMC_GoIdleState; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(host, &content); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_SetBlockSize(sdmmchost_t *host, uint32_t blockSize) +{ + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDMMC_SetBlockLength; + command.argument = blockSize; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(host, &content); + if ((kStatus_Success != error) || ((command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG) != 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDMMC_SetCardInactive(sdmmchost_t *host) +{ + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDMMC_GoInactiveState; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeNone; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(host, &content); + if ((kStatus_Success != error)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_common.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/common/fsl_sdmmc_common.h similarity index 51% rename from bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_common.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/common/fsl_sdmmc_common.h index 11e6e9ae93..7f9bfbb663 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_common.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/common/fsl_sdmmc_common.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -15,15 +15,14 @@ #include "stdlib.h" /*! - * @addtogroup CARD + * @addtogroup sdmmc_common SDMMC Common + * @ingroup card * @{ */ /******************************************************************************* * Definitions ******************************************************************************/ -/*! @brief Middleware version. */ -#define FSL_SDMMC_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 11U)) /*2.2.11*/ /*! @brief Reverse byte sequence in uint32_t */ #define SWAP_WORD_BYTE_SEQUENCE(x) (__REV(x)) @@ -35,14 +34,8 @@ #define FSL_SDMMC_MAX_CMD_RETRIES (10U) /*! @brief Default block size */ #define FSL_SDMMC_DEFAULT_BLOCK_SIZE (512U) -#ifndef SDMMC_GLOBAL_BUFFER_SIZE -/*! @brief SDMMC global data buffer size, word unit*/ -#define SDMMC_GLOBAL_BUFFER_SIZE (128U) -#endif -/*! @brief SDMMC enable software tuning */ -#define SDMMC_ENABLE_SOFTWARE_TUNING (0U) -/* Common definition for cache line size align */ -#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL + +/*! @brief make sure the internal buffer address is cache align */ #if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) #if defined(FSL_FEATURE_L2DCACHE_LINESIZE_BYTE) #define SDMMC_DATA_BUFFER_ALIGN_CACHE MAX(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE, FSL_FEATURE_L2DCACHE_LINESIZE_BYTE) @@ -50,12 +43,16 @@ #define SDMMC_DATA_BUFFER_ALIGN_CACHE FSL_FEATURE_L1DCACHE_LINESIZE_BYTE #endif #else -#define SDMMC_DATA_BUFFER_ALIGN_CACHE 1 -#endif -#else -#define SDMMC_DATA_BUFFER_ALIGN_CACHE 1 +#define SDMMC_DATA_BUFFER_ALIGN_CACHE sizeof(uint32_t) #endif +/*! @brief sdmmc card internal buffer size */ +#define FSL_SDMMC_CARD_INTERNAL_BUFFER_SIZE (FSL_SDMMC_DEFAULT_BLOCK_SIZE + SDMMC_DATA_BUFFER_ALIGN_CACHE) +#define FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(buffer) \ + (uint32_t)((uint32_t)(buffer) + (uint32_t)SDMMC_DATA_BUFFER_ALIGN_CACHE - \ + ((uint32_t)(buffer) & ((uint32_t)SDMMC_DATA_BUFFER_ALIGN_CACHE - 1U))) +/*! @brief get maximum freq */ +#define FSL_SDMMC_CARD_MAX_BUS_FREQ(max, target) ((max) == 0U ? (target) : ((max) > (target) ? (target) : (max))) /*! @brief SD/MMC error log. */ #if defined SDMMC_ENABLE_LOG_PRINT #include "fsl_debug_console.h" @@ -64,8 +61,10 @@ #define SDMMC_LOG(format, ...) #endif -/*! @brief SD/MMC card API's running status. */ -enum _sdmmc_status +/*! @brief SD/MMC card API's running status. + * @anchor _sdmmc_status + */ +enum { kStatus_SDMMC_NotSupportYet = MAKE_STATUS(kStatusGroup_SDMMC, 0U), /*!< Haven't supported */ kStatus_SDMMC_TransferFailed = MAKE_STATUS(kStatusGroup_SDMMC, 1U), /*!< Send command failed */ @@ -116,18 +115,179 @@ enum _sdmmc_status kStatus_SDMMC_HostNotReady = MAKE_STATUS(kStatusGroup_SDMMC, 39U), /*!< host controller not ready */ kStatus_SDMMC_CardDetectFailed = MAKE_STATUS(kStatusGroup_SDMMC, 40U), /*!< card detect failed */ kStatus_SDMMC_AuSizeNotSetProperly = MAKE_STATUS(kStatusGroup_SDMMC, 41U), /*!< AU size not set properly */ + kStatus_SDMMC_PollingCardIdleFailed = MAKE_STATUS(kStatusGroup_SDMMC, 42U), /*!< polling card idle status failed */ + kStatus_SDMMC_DeselectCardFailed = MAKE_STATUS(kStatusGroup_SDMMC, 43U), /*!< deselect card failed */ + kStatus_SDMMC_CardStatusIdle = MAKE_STATUS(kStatusGroup_SDMMC, 44U), /*!< card idle */ + kStatus_SDMMC_CardStatusBusy = MAKE_STATUS(kStatusGroup_SDMMC, 45U), /*!< card busy */ + kStatus_SDMMC_CardInitFailed = MAKE_STATUS(kStatusGroup_SDMMC, 46U), /*!< card init failed */ +}; +/*! @brief sdmmc signal line + * @anchor _sdmmc_signal_line + */ +enum +{ + kSDMMC_SignalLineCmd = 1U, /*!< cmd line */ + kSDMMC_SignalLineData0 = 2U, /*!< data line */ + kSDMMC_SignalLineData1 = 4U, /*!< data line */ + kSDMMC_SignalLineData2 = 8U, /*!< data line */ + kSDMMC_SignalLineData3 = 16U, /*!< data line */ + kSDMMC_SignalLineData4 = 32U, /*!< data line */ + kSDMMC_SignalLineData5 = 64U, /*!< data line */ + kSDMMC_SignalLineData6 = 128U, /*!< data line */ + kSDMMC_SignalLineData7 = 256U, /*!< data line */ }; /*! @brief card operation voltage */ typedef enum _sdmmc_operation_voltage { - kCARD_OperationVoltageNone = 0U, /*!< indicate current voltage setting is not setting by suser*/ - kCARD_OperationVoltage330V = 1U, /*!< card operation voltage around 3.3v */ - kCARD_OperationVoltage300V = 2U, /*!< card operation voltage around 3.0v */ - kCARD_OperationVoltage180V = 3U, /*!< card operation voltage around 1.8v */ + kSDMMC_OperationVoltageNone = 0U, /*!< indicate current voltage setting is not setting by suser*/ + kSDMMC_OperationVoltage330V = 1U, /*!< card operation voltage around 3.3v */ + kSDMMC_OperationVoltage300V = 2U, /*!< card operation voltage around 3.0v */ + kSDMMC_OperationVoltage180V = 3U, /*!< card operation voltage around 1.8v */ } sdmmc_operation_voltage_t; +/*!@brief card bus width + * @anchor _sdmmc_bus_width + */ +enum +{ + kSDMMC_BusWdith1Bit = 0U, /*!< card bus 1 width */ + kSDMMC_BusWdith4Bit = 1U, /*!< card bus 4 width */ + kSDMMC_BusWdith8Bit = 2U, /*!< card bus 8 width */ +}; + +/*!@brief sdmmc capability flag + * @anchor _sdmmc_capability_flag + */ +enum +{ + kSDMMC_Support8BitWidth = 1U, /*!< 8 bit data width capability */ +}; + +/*!@ brief sdmmc data packet format + * @anchor _sdmmc_data_packet_format + */ +enum +{ + kSDMMC_DataPacketFormatLSBFirst, /*!< usual data packet format LSB first, MSB last */ + kSDMMC_DataPacketFormatMSBFirst, /*!< Wide width data packet format MSB first, LSB last */ +}; + +/*! @brief sd card detect type */ +typedef enum _sd_detect_card_type +{ + kSD_DetectCardByGpioCD, /*!< sd card detect by CD pin through GPIO */ + kSD_DetectCardByHostCD, /*!< sd card detect by CD pin through host */ + kSD_DetectCardByHostDATA3, /*!< sd card detect by DAT3 pin through host */ +} sd_detect_card_type_t; + +/*!@ brief SD card detect status + * @anchor _sd_card_cd_status + */ +enum +{ + kSD_Inserted = 1U, /*!< card is inserted*/ + kSD_Removed = 0U, /*!< card is removed */ +}; + +/*!@ brief SD card detect status + * @anchor _sd_card_dat3_pull_status + */ +enum +{ + kSD_DAT3PullDown = 0U, /*!< data3 pull down */ + kSD_DAT3PullUp = 1U, /*!< data3 pull up */ +}; + +/*! @brief card detect aoolication callback definition */ +typedef void (*sd_cd_t)(bool isInserted, void *userData); +/*! @brief card detect status */ +typedef bool (*sd_cd_status_t)(void); +typedef void (*sd_dat3_pull_t)(uint32_t pullStatus); + +/*! @brief sd card detect */ +typedef struct _sd_detect_card +{ + sd_detect_card_type_t type; /*!< card detect type */ + uint32_t cdDebounce_ms; /*!< card detect debounce delay ms */ + sd_cd_t callback; /*!< card inserted callback which is meaningful for interrupt case */ + sd_cd_status_t cardDetected; /*!< used to check sd cd status when card detect through GPIO */ + sd_dat3_pull_t dat3PullFunc; /*!< function pointer of DATA3 pull up/down */ + + void *userData; /*!< user data */ +} sd_detect_card_t; + +/*!@brief io voltage control type*/ +typedef enum _sd_io_voltage_ctrl_type +{ + kSD_IOVoltageCtrlNotSupport = 0U, /*!< io voltage control not support */ + kSD_IOVoltageCtrlByHost = 1U, /*!< io voltage control by host */ + kSD_IOVoltageCtrlByGpio = 2U, /*!< io voltage control by gpio */ +} sd_io_voltage_ctrl_type_t; + +/*! @brief card switch voltage function pointer */ +typedef void (*sd_io_voltage_func_t)(sdmmc_operation_voltage_t voltage); + +/*!@brief io voltage control configuration */ +typedef struct _sd_io_voltage +{ + sd_io_voltage_ctrl_type_t type; /*!< io voltage switch type */ + sd_io_voltage_func_t func; /*!< io voltage switch function */ +} sd_io_voltage_t; + +/*! @brief card power control function pointer */ +typedef void (*sd_pwr_t)(bool enable); +/*! @brief card io strength control */ +typedef void (*sd_io_strength_t)(uint32_t busFreq); +/*! @brief sdcard user parameter */ +typedef struct _sd_usr_param +{ + sd_pwr_t pwr; /*!< power control configuration pointer */ + uint32_t powerOnDelayMS; /*!< power on delay time */ + uint32_t powerOffDelayMS; /*!< power off delay time */ + + sd_io_strength_t ioStrength; /*!< swicth sd io strength */ + sd_io_voltage_t *ioVoltage; /*!< switch io voltage */ + sd_detect_card_t *cd; /*!< card detect */ + + uint32_t maxFreq; /*!< board support maximum frequency */ + uint32_t capability; /*!< board capability flag */ +} sd_usr_param_t; + +/*! @brief card interrupt function pointer */ +typedef void (*sdio_int_t)(void *userData); + +/*! @brief card interrupt application callback */ +typedef struct _sdio_card_int +{ + void *userData; /*!< user data */ + sdio_int_t cardInterrupt; /*!< card int call back */ +} sdio_card_int_t; + +/*! @brief sdio user parameter */ +typedef struct _sdio_usr_param +{ + sd_pwr_t pwr; /*!< power control configuration pointer */ + uint32_t powerOnDelayMS; /*!< power on delay time */ + uint32_t powerOffDelayMS; /*!< power off delay time */ + + sd_io_strength_t ioStrength; /*!< swicth sd io strength */ + sd_io_voltage_t *ioVoltage; /*!< switch io voltage */ + sd_detect_card_t *cd; /*!< card detect */ + sdio_card_int_t *sdioInt; /*!< card int */ + uint32_t maxFreq; /*!< board support maximum frequency */ + uint32_t capability; /*!< board capability flag */ +} sdio_usr_param_t; + +/*! @brief tuning pattern */ +#if SDMMCHOST_SUPPORT_DDR50 || SDMMCHOST_SUPPORT_SDR104 || SDMMCHOST_SUPPORT_SDR50 || SDMMCHOST_SUPPORT_HS200 || \ + SDMMCHOST_SUPPORT_HS400 +/* sdmmc tuning block */ +extern const uint32_t SDMMC_TuningBlockPattern4Bit[16U]; +extern const uint32_t SDMMC_TuningBlockPattern8Bit[32U]; +#endif + /************************************************************************************************* * API ************************************************************************************************/ @@ -142,113 +302,61 @@ extern "C" { /*! * @brief Selects the card to put it into transfer state. * - * @param base SDMMCHOST peripheral base address. - * @param transfer SDMMCHOST transfer function. + * @param host host handler. * @param relativeAddress Relative address. * @param isSelected True to put card into transfer state. * @retval kStatus_SDMMC_TransferFailed Transfer failed. * @retval kStatus_Success Operate successfully. */ -status_t SDMMC_SelectCard(SDMMCHOST_TYPE *base, - SDMMCHOST_TRANSFER_FUNCTION transfer, - uint32_t relativeAddress, - bool isSelected); +status_t SDMMC_SelectCard(sdmmchost_t *host, uint32_t relativeAddress, bool isSelected); /*! * @brief Sends an application command. * - * @param base SDMMCHOST peripheral base address. - * @param transfer SDMMCHOST transfer function. + * @param host host handler. * @param relativeAddress Card relative address. * @retval kStatus_SDMMC_TransferFailed Transfer failed. * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. * @retval kStatus_Success Operate successfully. */ -status_t SDMMC_SendApplicationCommand(SDMMCHOST_TYPE *base, - SDMMCHOST_TRANSFER_FUNCTION transfer, - uint32_t relativeAddress); +status_t SDMMC_SendApplicationCommand(sdmmchost_t *host, uint32_t relativeAddress); /*! * @brief Sets the block count. * - * @param base SDMMCHOST peripheral base address. - * @param transfer SDMMCHOST transfer function. + * @param host host handler. * @param blockCount Block count. * @retval kStatus_SDMMC_TransferFailed Transfer failed. * @retval kStatus_Success Operate successfully. */ -status_t SDMMC_SetBlockCount(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockCount); +status_t SDMMC_SetBlockCount(sdmmchost_t *host, uint32_t blockCount); /*! * @brief Sets the card to be idle state. * - * @param base SDMMCHOST peripheral base address. - * @param transfer SDMMCHOST transfer function. + * @param host host handler. * @retval kStatus_SDMMC_TransferFailed Transfer failed. * @retval kStatus_Success Operate successfully. */ -status_t SDMMC_GoIdle(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer); - +status_t SDMMC_GoIdle(sdmmchost_t *host); /*! * @brief Sets data block size. * - * @param base SDMMCHOST peripheral base address. - * @param transfer SDMMCHOST transfer function. + * @param host host handler. * @param blockSize Block size. * @retval kStatus_SDMMC_TransferFailed Transfer failed. * @retval kStatus_Success Operate successfully. */ -status_t SDMMC_SetBlockSize(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockSize); - +status_t SDMMC_SetBlockSize(sdmmchost_t *host, uint32_t blockSize); /*! * @brief Sets card to inactive status * - * @param base SDMMCHOST peripheral base address. - * @param transfer SDMMCHOST transfer function. + * @param host host handler. * @retval kStatus_SDMMC_TransferFailed Transfer failed. * @retval kStatus_Success Operate successfully. */ -status_t SDMMC_SetCardInactive(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer); +status_t SDMMC_SetCardInactive(sdmmchost_t *host); -/*! - * @brief provide a simple delay function for sdmmc - * - * @param num Delay num*10000. - */ -void SDMMC_Delay(uint32_t num); - -/*! - * @brief provide a voltage switch function for SD/SDIO card - * @deprecated Do not use this function, it has been superceded by SDMMC_SwitchToVoltage. - * @param base SDMMCHOST peripheral base address. - * @param transfer SDMMCHOST transfer function. - */ -status_t SDMMC_SwitchVoltage(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer); - -/*! - * @brief provide a voltage switch function for SD/SDIO card - * - * @param base SDMMCHOST peripheral base address. - * @param transfer SDMMCHOST transfer function. - * @param switchVoltageFunc voltage switch function. - * @return error code. - */ - -status_t SDMMC_SwitchToVoltage(SDMMCHOST_TYPE *base, - SDMMCHOST_TRANSFER_FUNCTION transfer, - sdmmchost_card_switch_voltage_t switchVoltageFunc); -/*! - * @brief excute tuning - * - * @param base SDMMCHOST peripheral base address. - * @param transfer Host transfer function - * @param tuningCmd Tuning cmd - * @param blockSize Tuning block size - */ -status_t SDMMC_ExecuteTuning(SDMMCHOST_TYPE *base, - SDMMCHOST_TRANSFER_FUNCTION transfer, - uint32_t tuningCmd, - uint32_t blockSize); /* @} */ #if defined(__cplusplus) diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_spec.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/common/fsl_sdmmc_spec.h similarity index 89% rename from bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_spec.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/common/fsl_sdmmc_spec.h index b4f21b86c5..f2e602c30c 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_spec.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/common/fsl_sdmmc_spec.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -12,7 +12,8 @@ #include /*! - * @addtogroup CARD + * @addtogroup sdmmc_common SDMMC Common + * @ingroup card * @{ */ @@ -41,10 +42,12 @@ #define MMC_CLOCK_HS400 (400000000U) /*!@brief mask convert */ -#define SDMMC_MASK(bit) (1U << (bit)) +#define SDMMC_MASK(bit) (1UL << (bit)) -/*! @brief Card status bit in R1 */ -enum _sdmmc_r1_card_status_flag +/*! @brief Card status bit in R1 + * @anchor _sdmmc_r1_card_status_flag + */ +enum { kSDMMC_R1OutOfRangeFlag = 31, /*!< Out of range status bit */ kSDMMC_R1AddressErrorFlag = 30, /*!< Address error status bit */ @@ -97,8 +100,10 @@ typedef enum _sdmmc_r1_current_state kSDMMC_R1StateDisconnect = 8U, /*!< R1: current state: disconnect */ } sdmmc_r1_current_state_t; -/*! @brief Error bit in SPI mode R1 */ -enum _sdspi_r1_error_status_flag +/*! @brief Error bit in SPI mode R1 + * @anchor _sdspi_r1_error_status_flag + */ +enum { kSDSPI_R1InIdleStateFlag = (1U << 0U), /*!< In idle state */ kSDSPI_R1EraseResetFlag = (1U << 1U), /*!< Erase reset */ @@ -109,8 +114,10 @@ enum _sdspi_r1_error_status_flag kSDSPI_R1ParameterErrorFlag = (1U << 6U), /*!< Parameter error */ }; -/*! @brief Error bit in SPI mode R2 */ -enum _sdspi_r2_error_status_flag +/*! @brief Error bit in SPI mode R2 + * @anchor _sdspi_r2_error_status_flag + */ +enum { kSDSPI_R2CardLockedFlag = (1U << 0U), /*!< Card is locked */ kSDSPI_R2WriteProtectEraseSkip = (1U << 1U), /*!< Write protect erase skip */ @@ -141,8 +148,10 @@ enum _sdspi_r2_error_status_flag /*! @brief Data error token mask */ #define SDSPI_DATA_ERROR_TOKEN_MASK (0xFU) -/*! @brief Data Error Token mask bit */ -enum _sdspi_data_error_token +/*! @brief Data Error Token mask bit + * @anchor _sdspi_data_error_token + */ +enum { kSDSPI_DataErrorTokenError = (1U << 0U), /*!< Data error */ kSDSPI_DataErrorTokenCardControllerError = (1U << 1U), /*!< Card controller error */ @@ -200,8 +209,10 @@ typedef enum _sd_application_command kSD_ApplicationSendScr = 51U, /*!< Send Scr */ } sd_application_command_t; -/*! @brief SD card command class */ -enum _sdmmc_command_class +/*! @brief SD card command class + * @anchor _sdmmc_command_class + */ +enum { kSDMMC_CommandClassBasic = (1U << 0U), /*!< Card command class 0 */ kSDMMC_CommandClassBlockRead = (1U << 2U), /*!< Card command class 2 */ @@ -214,8 +225,10 @@ enum _sdmmc_command_class kSDMMC_CommandClassSwitch = (1U << 10U), /*!< Card command class 10 */ }; -/*! @brief OCR register in SD card */ -enum _sd_ocr_flag +/*! @brief OCR register in SD card + * @anchor _sd_ocr_flag + */ +enum { kSD_OcrPowerUpBusyFlag = 31, /*!< Power up busy status */ kSD_OcrHostCapacitySupportFlag = 30, /*!< Card capacity status */ @@ -233,8 +246,10 @@ enum _sd_ocr_flag kSD_OcrVdd35_36Flag = 23, /*!< VDD 3.4-3.5 */ }; -/*! @brief SD card specification version number */ -enum _sd_specification_version +/*! @brief SD card specification version number + * @anchor _sd_specification_version + */ +enum { kSD_SpecificationVersion1_0 = (1U << 0U), /*!< SD card version 1.0-1.01 */ kSD_SpecificationVersion1_1 = (1U << 1U), /*!< SD card version 1.10 */ @@ -242,13 +257,6 @@ enum _sd_specification_version kSD_SpecificationVersion3_0 = (1U << 3U), /*!< SD card version 3.0 */ }; -/*! @brief SD card bus width */ -typedef enum _sd_data_bus_width -{ - kSD_DataBusWidth1Bit = 0U, /*!< SD data bus width 1-bit mode */ - kSD_DataBusWidth4Bit = 1U, /*!< SD data bus width 4-bit mode */ -} sd_data_bus_width_t; - /*! @brief SD card switch mode */ typedef enum _sd_switch_mode { @@ -256,8 +264,10 @@ typedef enum _sd_switch_mode kSD_SwitchSet = 1U, /*!< SD switch mode 1: set function */ } sd_switch_mode_t; -/*! @brief SD card CSD register flags */ -enum _sd_csd_flag +/*! @brief SD card CSD register flags + * @anchor _sd_csd_flag + */ +enum { kSD_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed [79:79] */ kSD_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment [78:78] */ @@ -272,15 +282,19 @@ enum _sd_csd_flag kSD_CsdTemporaryWriteProtectFlag = (1U << 10U), /*!< Temporary write protection [12:12] */ }; -/*! @brief SD card SCR register flags */ -enum _sd_scr_flag +/*! @brief SD card SCR register flags + * @anchor _sd_scr_flag + */ +enum { kSD_ScrDataStatusAfterErase = (1U << 0U), /*!< Data status after erases [55:55] */ kSD_ScrSdSpecification3 = (1U << 1U), /*!< Specification version 3.00 or higher [47:47]*/ }; -/*! @brief SD timing function number */ -enum _sd_timing_function +/*! @brief SD timing function number + * @anchor _sd_timing_function + */ +enum { kSD_FunctionSDR12Deafult = 0U, /*!< SDR12 mode & default*/ kSD_FunctionSDR25HighSpeed = 1U, /*!< SDR25 & high speed*/ @@ -289,8 +303,10 @@ enum _sd_timing_function kSD_FunctionDDR50 = 4U, /*!< DDR50 mode*/ }; -/*! @brief SD group number */ -enum _sd_group_num +/*! @brief SD group number + * @anchor _sd_group_num + */ +enum { kSD_GroupTimingMode = 0U, /*!< acess mode group*/ kSD_GroupCommandSystem = 1U, /*!< command system group*/ @@ -361,8 +377,10 @@ typedef enum _sdmmc_command #ifndef SDIO_IO_READY_TIMEOUT_UNIT #define SDIO_IO_READY_TIMEOUT_UNIT (10U) #endif -/*! @brief sdio card cccr register addr */ -enum _sdio_cccr_reg +/*! @brief sdio card cccr register addr + * @anchor _sdio_cccr_reg + */ +enum { kSDIO_RegCCCRSdioVer = 0x00U, /*!< CCCR & SDIO version*/ kSDIO_RegSDVersion = 0x01U, /*!< SD version */ @@ -411,26 +429,28 @@ typedef enum _sdio_func_num kSDIO_FunctionMemory, /*!< for combo card*/ } sdio_func_num_t; -#define SDIO_CMD_ARGUMENT_RW_POS (31U) /*!< read/write flag position */ -#define SDIO_CMD_ARGUMENT_FUNC_NUM_POS (28U) /*!< function number position */ -#define SDIO_DIRECT_CMD_ARGUMENT_RAW_POS (27U) /*!< direct raw flag position */ -#define SDIO_CMD_ARGUMENT_REG_ADDR_POS (9U) /*!< direct reg addr position */ -#define SDIO_CMD_ARGUMENT_REG_ADDR_MASK (0x1FFFFU) /*!< direct reg addr mask */ -#define SDIO_DIRECT_CMD_DATA_MASK (0xFFU) /*!< data mask */ +#define SDIO_CMD_ARGUMENT_RW_POS (31U) /*!< read/write flag position */ +#define SDIO_CMD_ARGUMENT_FUNC_NUM_POS (28U) /*!< function number position */ +#define SDIO_DIRECT_CMD_ARGUMENT_RAW_POS (27U) /*!< direct raw flag position */ +#define SDIO_CMD_ARGUMENT_REG_ADDR_POS (9U) /*!< direct reg addr position */ +#define SDIO_CMD_ARGUMENT_REG_ADDR_MASK (0x1FFFFU) /*!< direct reg addr mask */ +#define SDIO_DIRECT_CMD_DATA_MASK (0xFFU) /*!< data mask */ -#define SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS (27U) /*!< extended command argument block mode bit position */ -#define SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS (26U) /*!< extended command argument OP Code bit position */ -#define SDIO_EXTEND_CMD_BLOCK_MODE_MASK (0x08000000U) /*!< block mode mask */ -#define SDIO_EXTEND_CMD_OP_CODE_MASK (0x04000000U) /*!< op code mask */ -#define SDIO_EXTEND_CMD_COUNT_MASK (0x1FFU) /*!< byte/block count mask */ -#define SDIO_MAX_BLOCK_SIZE (2048U) /*!< max block size */ -#define SDIO_FBR_BASE(x) (x * 0x100U) /*!< function basic register */ -#define SDIO_TPL_CODE_END (0xFFU) /*!< tuple end */ -#define SDIO_TPL_CODE_MANIFID (0x20U) /*!< manufacturer ID */ -#define SDIO_TPL_CODE_FUNCID (0x21U) /*!< function ID */ -#define SDIO_TPL_CODE_FUNCE (0x22U) /*!< function extension tuple*/ -/*! @brief sdio command response flag */ -enum _sdio_status_flag +#define SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS (27U) /*!< extended command argument block mode bit position */ +#define SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS (26U) /*!< extended command argument OP Code bit position */ +#define SDIO_EXTEND_CMD_BLOCK_MODE_MASK (0x08000000U) /*!< block mode mask */ +#define SDIO_EXTEND_CMD_OP_CODE_MASK (0x04000000U) /*!< op code mask */ +#define SDIO_EXTEND_CMD_COUNT_MASK (0x1FFU) /*!< byte/block count mask */ +#define SDIO_MAX_BLOCK_SIZE (2048U) /*!< max block size */ +#define SDIO_FBR_BASE(x) ((x)*0x100U) /*!< function basic register */ +#define SDIO_TPL_CODE_END (0xFFU) /*!< tuple end */ +#define SDIO_TPL_CODE_MANIFID (0x20U) /*!< manufacturer ID */ +#define SDIO_TPL_CODE_FUNCID (0x21U) /*!< function ID */ +#define SDIO_TPL_CODE_FUNCE (0x22U) /*!< function extension tuple*/ +/*! @brief sdio command response flag + * @anchor _sdio_status_flag + */ +enum { kSDIO_StatusCmdCRCError = 0x8000U, /*!< the CRC check of the previous cmd fail*/ kSDIO_StatusIllegalCmd = 0x4000U, /*!< cmd illegal for the card state */ @@ -440,8 +460,10 @@ enum _sdio_status_flag kSDIO_StatusOutofRange = 0x0100U, /*!< cmd argument was out of the allowed range*/ }; -/*! @brief sdio operation condition flag */ -enum _sdio_ocr_flag +/*! @brief sdio operation condition flag + * @anchor _sdio_ocr_flag + */ +enum { kSDIO_OcrPowerUpBusyFlag = 31, /*!< Power up busy status */ kSDIO_OcrIONumber = 28, /*!< number of IO function */ @@ -470,52 +492,56 @@ enum _sdio_ocr_flag /*! @brief sdio ocr reigster IO NUMBER mask */ #define SDIO_OCR_IO_NUM_MASK (7U << kSDIO_OcrIONumber) -/*! @brief sdio capability flag */ -enum _sdio_capability_flag +/*! @brief sdio capability flag + * @anchor _sdio_capability_flag + */ +enum { - kSDIO_CCCRSupportDirectCmdDuringDataTrans = (1U << 0U), /*!< support direct cmd during data transfer */ - kSDIO_CCCRSupportMultiBlock = (1U << 1U), /*!< support multi block mode */ - kSDIO_CCCRSupportReadWait = (1U << 2U), /*!< support read wait */ - kSDIO_CCCRSupportSuspendResume = (1U << 3U), /*!< support suspend resume */ - kSDIO_CCCRSupportIntDuring4BitDataTrans = (1U << 4U), /*!< support interrupt during 4-bit data transfer */ - kSDIO_CCCRSupportLowSpeed1Bit = (1U << 6U), /*!< support low speed 1bit mode */ - kSDIO_CCCRSupportLowSpeed4Bit = (1U << 7U), /*!< support low speed 4bit mode */ - kSDIO_CCCRSupportMasterPowerControl = (1U << 8U), /*!< support master power control */ - kSDIO_CCCRSupportHighSpeed = (1U << 9U), /*!< support high speed */ - kSDIO_CCCRSupportContinuousSPIInt = (1U << 10U), /*!< support continuous SPI interrupt */ + kSDIO_CCCRSupportDirectCmdDuringDataTrans = (1UL << 0U), /*!< support direct cmd during data transfer */ + kSDIO_CCCRSupportMultiBlock = (1UL << 1U), /*!< support multi block mode */ + kSDIO_CCCRSupportReadWait = (1UL << 2U), /*!< support read wait */ + kSDIO_CCCRSupportSuspendResume = (1UL << 3U), /*!< support suspend resume */ + kSDIO_CCCRSupportIntDuring4BitDataTrans = (1UL << 4U), /*!< support interrupt during 4-bit data transfer */ + kSDIO_CCCRSupportLowSpeed1Bit = (1UL << 6U), /*!< support low speed 1bit mode */ + kSDIO_CCCRSupportLowSpeed4Bit = (1UL << 7U), /*!< support low speed 4bit mode */ + kSDIO_CCCRSupportMasterPowerControl = (1UL << 8U), /*!< support master power control */ + kSDIO_CCCRSupportHighSpeed = (1UL << 9U), /*!< support high speed */ + kSDIO_CCCRSupportContinuousSPIInt = (1UL << 10U), /*!< support continuous SPI interrupt */ }; /*! @brief UHS timing mode flag */ -#define SDIO_CCCR_SUPPORT_HIGHSPEED (1u << 9U) -#define SDIO_CCCR_SUPPORT_SDR50 (1U << 11U) -#define SDIO_CCCR_SUPPORT_SDR104 (1U << 12U) -#define SDIO_CCCR_SUPPORT_DDR50 (1U << 13U) -#define SDIO_CCCR_SUPPORT_DRIVER_TYPE_A (1U << 14U) -#define SDIO_CCCR_SUPPORT_DRIVER_TYPE_C (1U << 15U) -#define SDIO_CCCR_SUPPORT_DRIVER_TYPE_D (1U << 16U) -#define SDIO_CCCR_SUPPORT_ASYNC_INT (1U << 17U) +#define SDIO_CCCR_SUPPORT_HIGHSPEED (1UL << 9U) +#define SDIO_CCCR_SUPPORT_SDR50 (1UL << 11U) +#define SDIO_CCCR_SUPPORT_SDR104 (1UL << 12U) +#define SDIO_CCCR_SUPPORT_DDR50 (1UL << 13U) +#define SDIO_CCCR_SUPPORT_DRIVER_TYPE_A (1UL << 14U) +#define SDIO_CCCR_SUPPORT_DRIVER_TYPE_C (1UL << 15U) +#define SDIO_CCCR_SUPPORT_DRIVER_TYPE_D (1UL << 16U) +#define SDIO_CCCR_SUPPORT_ASYNC_INT (1UL << 17U) -#define SDIO_CCCR_BUS_SPEED_MASK (7U << 1U) +#define SDIO_CCCR_BUS_SPEED_MASK (7U << 1U) #define SDIO_CCCR_ENABLE_HIGHSPEED_MODE (1U << 1U) -#define SDIO_CCCR_ENABLE_SDR50_MODE (2U << 1U) -#define SDIO_CCCR_ENABLE_SDR104_MODE (3U << 1U) -#define SDIO_CCCR_ENABLE_DDR50_MODE (4U << 1U) +#define SDIO_CCCR_ENABLE_SDR50_MODE (2U << 1U) +#define SDIO_CCCR_ENABLE_SDR104_MODE (3U << 1U) +#define SDIO_CCCR_ENABLE_DDR50_MODE (4U << 1U) /*! @brief Driver type flag */ -#define SDIO_CCCR_DRIVER_TYPE_MASK (3U << 4U) +#define SDIO_CCCR_DRIVER_TYPE_MASK (3U << 4U) #define SDIO_CCCR_ENABLE_DRIVER_TYPE_B (0U << 4U) #define SDIO_CCCR_ENABLE_DRIVER_TYPE_A (1U << 4U) #define SDIO_CCCR_ENABLE_DRIVER_TYPE_C (2U << 4U) #define SDIO_CCCR_ENABLE_DRIVER_TYPE_D (3U << 4U) /*! @brief aync interrupt flag*/ -#define SDIO_CCCR_ASYNC_INT_MASK (1U) +#define SDIO_CCCR_ASYNC_INT_MASK (1U) #define SDIO_CCCR_ENABLE_AYNC_INT (1U << 1U) /*! @brief 8 bit data bus flag*/ -#define SDIO_CCCR_SUPPORT_8BIT_BUS (1U << 18U) +#define SDIO_CCCR_SUPPORT_8BIT_BUS (1UL << 18U) #define SDIO_CCCR_SUPPORT_LOW_SPEED_4BIT_BUS (1U << 7U) -/*! @brief sdio fbr flag */ -enum _sdio_fbr_flag +/*! @brief sdio fbr flag + * @anchor _sdio_fbr_flag + */ +enum { kSDIO_FBRSupportCSA = (1U << 0U), /*!< function support CSA */ kSDIO_FBRSupportPowerSelection = (1U << 1U), /*!< function support power selection */ @@ -630,13 +656,15 @@ typedef enum _mmc_specification_version /*! @brief Read the value of FREQUENCY UNIT in TRANSFER SPEED. */ #define READ_MMC_TRANSFER_SPEED_FREQUENCY_UNIT(CSD) \ - (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK) >> MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT) + ((((CSD).transferSpeed) & MMC_TRANSFER_SPEED_FREQUENCY_UNIT_MASK) >> MMC_TRANSFER_SPEED_FREQUENCY_UNIT_SHIFT) /*! @brief Read the value of MULTIPLER filed in TRANSFER SPEED. */ #define READ_MMC_TRANSFER_SPEED_MULTIPLIER(CSD) \ - (((CSD.transferSpeed) & MMC_TRANSFER_SPEED_MULTIPLIER_MASK) >> MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT) + ((((CSD).transferSpeed) & MMC_TRANSFER_SPEED_MULTIPLIER_MASK) >> MMC_TRANSFER_SPEED_MULTIPLIER_SHIFT) -/*! @brief MMC card Extended CSD fix version(EXT_CSD_REV in Extended CSD) */ -enum _mmc_extended_csd_revision +/*! @brief MMC card Extended CSD fix version(EXT_CSD_REV in Extended CSD) + * @anchor _mmc_extended_csd_revision + */ +enum { kMMC_ExtendedCsdRevision10 = 0U, /*!< Revision 1.0 */ kMMC_ExtendedCsdRevision11 = 1U, /*!< Revision 1.1 */ @@ -658,8 +686,10 @@ typedef enum _mmc_command_set kMMC_CommandSet4 = 4U, /*!< Command set 4 */ } mmc_command_set_t; -/*! @brief boot support(BOOT_INFO in Extended CSD) */ -enum _mmc_support_boot_mode +/*! @brief boot support(BOOT_INFO in Extended CSD) + * @anchor _mmc_support_boot_mode + */ +enum { kMMC_SupportAlternateBoot = 1U, /*!< support alternative boot mode*/ kMMC_SupportDDRBoot = 2U, /*!< support DDR boot mode*/ @@ -669,14 +699,19 @@ enum _mmc_support_boot_mode #define MMC_POWER_CLASS_4BIT_MASK (0x0FU) /*! @brief The power class current value bit mask when bus in 8 bit mode */ #define MMC_POWER_CLASS_8BIT_MASK (0xF0U) +/*! @brief mmc cache control enable*/ +#define MMC_CACHE_CONTROL_ENABLE (1U) +/*! @brief mmc cache flush */ +#define MMC_CACHE_TRIGGER_FLUSH (1U) /*! @brief MMC card high-speed timing(HS_TIMING in Extended CSD) */ typedef enum _mmc_high_speed_timing { - kMMC_HighSpeedTimingNone = 0U, /*!< MMC card using none high-speed timing */ - kMMC_HighSpeedTiming = 1U, /*!< MMC card using high-speed timing */ - kMMC_HighSpeed200Timing = 2U, /*!< MMC card high speed 200 timing*/ - kMMC_HighSpeed400Timing = 3U, /*!< MMC card high speed 400 timing*/ + kMMC_HighSpeedTimingNone = 0U, /*!< MMC card using none high-speed timing */ + kMMC_HighSpeedTiming = 1U, /*!< MMC card using high-speed timing */ + kMMC_HighSpeed200Timing = 2U, /*!< MMC card high speed 200 timing*/ + kMMC_HighSpeed400Timing = 3U, /*!< MMC card high speed 400 timing*/ + kMMC_EnhanceHighSpeed400Timing = 4U, /*!< MMC card high speed 400 timing*/ } mmc_high_speed_timing_t; /*! @brief The number of data bus width type */ @@ -684,11 +719,12 @@ typedef enum _mmc_high_speed_timing /*! @brief MMC card data bus width(BUS_WIDTH in Extended CSD) */ typedef enum _mmc_data_bus_width { - kMMC_DataBusWidth1bit = 0U, /*!< MMC data bus width is 1 bit */ - kMMC_DataBusWidth4bit = 1U, /*!< MMC data bus width is 4 bits */ - kMMC_DataBusWidth8bit = 2U, /*!< MMC data bus width is 8 bits */ - kMMC_DataBusWidth4bitDDR = 5U, /*!< MMC data bus width is 4 bits ddr */ - kMMC_DataBusWidth8bitDDR = 6U, /*!< MMC data bus width is 8 bits ddr */ + kMMC_DataBusWidth1bit = 0U, /*!< MMC data bus width is 1 bit */ + kMMC_DataBusWidth4bit = 1U, /*!< MMC data bus width is 4 bits */ + kMMC_DataBusWidth8bit = 2U, /*!< MMC data bus width is 8 bits */ + kMMC_DataBusWidth4bitDDR = 5U, /*!< MMC data bus width is 4 bits ddr */ + kMMC_DataBusWidth8bitDDR = 6U, /*!< MMC data bus width is 8 bits ddr */ + kMMC_DataBusWidth8bitDDRSTROBE = 0x86U, /*!< MMC data bus width is 8 bits ddr strobe mode */ } mmc_data_bus_width_t; /*! @brief MMC card boot partition enabled(BOOT_PARTITION_ENABLE in Extended CSD) */ @@ -705,9 +741,9 @@ typedef enum _mmc_boot_partition_enable */ typedef enum _mmc_boot_timing_mode { - kMMC_BootModeSDRWithDefaultTiming = 0U << 3U, /*!< boot mode single data rate with backward compatiable timings */ - kMMC_BootModeSDRWithHighSpeedTiming = 1U << 3U, /*!< boot mode single data rate with high speed timing */ - kMMC_BootModeDDRTiming = 2U << 3U, /*!< boot mode dual date rate */ + kMMC_BootModeSDRWithDefaultTiming = 0U, /*!< boot mode single data rate with backward compatiable timings */ + kMMC_BootModeSDRWithHighSpeedTiming = 1U, /*!< boot mode single data rate with high speed timing */ + kMMC_BootModeDDRTiming = 2U, /*!< boot mode dual date rate */ } mmc_boot_timing_mode_t; /*! @brief MMC card boot partition write protect configurations @@ -738,8 +774,10 @@ typedef enum _mmc_boot_partition_wp 1U, /*!< permanent write protection apply to partition2, power on period write protection apply to partition1 */ } mmc_boot_partition_wp_t; -/*! @brief MMC card boot partition write protect status */ -enum _mmc_boot_partition_wp_status +/*! @brief MMC card boot partition write protect status + * @anchor _mmc_boot_partition_wp_status + */ +enum { kMMC_BootPartitionNotProtected = 0U, /*!< boot partition not protected */ kMMC_BootPartitionPwrProtected = 1U, /*!< boot partition is power on period write protected */ @@ -779,11 +817,15 @@ typedef enum _mmc_access_partition #define MMC_BOOT_BUS_CONDITION_RESET_BUS_CONDITION_SHIFT (2U) /*! @brief The bit mask for BOOT BUS WIDTH RESET field in BOOT CONFIG */ #define MMC_BOOT_BUS_CONDITION_RESET_BUS_CONDITION_MASK (4U) -/*! @brief The bit mask for BOOT BUS WIDTH RESET field in BOOT CONFIG */ +/*! @brief The bit shift for BOOT MODE field in BOOT CONFIG */ +#define MMC_BOOT_BUS_CONDITION_BOOT_MODE_SHIFT (3U) +/*! @brief The bit mask for BOOT MODE field in BOOT CONFIG */ #define MMC_BOOT_BUS_CONDITION_BOOT_MODE_MASK (0x18U) -/*! @brief MMC card CSD register flags */ -enum _mmc_csd_flag +/*! @brief MMC card CSD register flags + * @anchor _mmc_csd_flag + */ +enum { kMMC_CsdReadBlockPartialFlag = (1U << 0U), /*!< Partial blocks for read allowed */ kMMC_CsdWriteBlockMisalignFlag = (1U << 1U), /*!< Write block misalignment */ @@ -810,6 +852,8 @@ typedef enum _mmc_extended_csd_access_mode /*! @brief EXT CSD byte index */ typedef enum _mmc_extended_csd_index { + kMMC_ExtendedCsdIndexFlushCache = 32U, /*!< flush cache */ + kMMC_ExtendedCsdIndexCacheControl = 33U, /*!< cache control */ kMMC_ExtendedCsdIndexBootPartitionWP = 173U, /*!< Boot partition write protect */ kMMC_ExtendedCsdIndexEraseGroupDefinition = 175U, /*!< Erase Group Def */ kMMC_ExtendedCsdIndexBootBusConditions = 177U, /*!< Boot Bus conditions */ @@ -821,8 +865,10 @@ typedef enum _mmc_extended_csd_index kMMC_ExtendedCsdIndexCommandSet = 191U, /*!< Command Set */ } mmc_extended_csd_index_t; -/*! @brief mmc driver strength */ -enum _mmc_driver_strength +/*! @brief mmc driver strength + * @anchor _mmc_driver_strength + */ +enum { kMMC_DriverStrength0 = 0U, /*!< Driver type0 ,nominal impedance 50ohm */ kMMC_DriverStrength1 = 1U, /*!< Driver type1 ,nominal impedance 33ohm */ @@ -844,17 +890,17 @@ typedef enum _mmc_extended_csd_flags } mmc_extended_csd_flags_t; /*! @brief MMC card boot mode */ -enum _mmc_boot_mode +typedef enum _mmc_boot_mode { kMMC_BootModeNormal = 0U, /*!< Normal boot */ kMMC_BootModeAlternative = 1U, /*!< Alternative boot */ -}; +} mmc_boot_mode_t; /*! @brief The length of Extended CSD register, unit as bytes. */ #define MMC_EXTENDED_CSD_BYTES (512U) /*! @brief MMC card default relative address */ -#define MMC_DEFAULT_RELATIVE_ADDRESS (2U) +#define MMC_DEFAULT_RELATIVE_ADDRESS (2UL) /*! @brief SD card product name length united as bytes. */ #define SD_PRODUCT_NAME_BYTES (5U) @@ -1056,7 +1102,7 @@ typedef struct _mmc_extended_csd /*uint8_t ffuStatus;*/ /*!< FFU status [26]*/ /*uint8_t modeOperationCode;*/ /*!< mode operation code[29]*/ /*uint8_t modeConfig;*/ /*!< mode config [30]*/ - /*uint8_t cacheCtrl;*/ /*!< control to turn on/off cache[33]*/ + uint8_t cacheCtrl; /*!< control to turn on/off cache[33]*/ /*uint8_t pwroffNotify;*/ /*!< power off notification[34]*/ /*uint8_t packedCmdFailIndex;*/ /*!< packed cmd fail index [35]*/ /*uint8_t packedCmdStatus;*/ /*!< packed cmd status[36]*/ @@ -1101,7 +1147,7 @@ typedef struct _mmc_extended_csd uint8_t cardType; /*!< Card Type [196] */ uint8_t ioDriverStrength; /*!< IO driver strength [197] */ /*uint8_t OutofInterruptBusyTiming;*/ /*!< out of interrupt busy timing [198] */ - /*uint8_t partitionSwitchTiming;*/ /*!< partition switch timing [199] */ + uint8_t partitionSwitchTimeout; /*!< partition switch timing [199] */ uint8_t powerClass52MHz195V; /*!< Power Class for 52MHz @ 1.95V [200] */ uint8_t powerClass26MHz195V; /*!< Power Class for 26MHz @ 1.95V [201] */ uint8_t powerClass52MHz360V; /*!< Power Class for 52MHz @ 3.6V [202] */ @@ -1139,7 +1185,7 @@ typedef struct _mmc_extended_csd /*uint32_t correctPrgSectorNum;*/ /*!< correct prg sectors number[245-242]*/ /*uint8_t bkOpsStatus;*/ /*!< background operations status[246]*/ /*uint8_t powerOffNotifyTimeout;*/ /*!< power off notification timeout[247]*/ - /*uint8_t genericCMD6Timeout;*/ /*!< generic CMD6 timeout[248]*/ + uint32_t genericCMD6Timeout; /*!< generic CMD6 timeout[248]*/ uint32_t cacheSize; /*!< cache size[252-249]*/ uint8_t powerClass200MHZDDR360V; /*!< power class for 200MHZ, DDR at VCC=2.6V[253]*/ /*uint32_t fwVer[2U];*/ /*!< fw VERSION [261-254]*/ @@ -1195,6 +1241,7 @@ typedef struct _mmc_extended_csd_config /*! @brief MMC card boot configuration definition. */ typedef struct _mmc_boot_config { + mmc_boot_mode_t bootMode; /*!< mmc boot mode */ bool enableBootAck; /*!< Enable boot ACK */ mmc_boot_partition_enable_t bootPartition; /*!< Boot partition */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/ChangeLogKSDK.txt b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/ChangeLogKSDK.txt new file mode 100644 index 0000000000..839e14bb03 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/ChangeLogKSDK.txt @@ -0,0 +1,41 @@ +/*! +@page middleware_log Middleware Change Log + +@section host_sdif Host SDIF driver for MCUXpresso SDK +The current driver version is 2.4.0. + - 2.4.0 + - Improvements + - Removed deprecated api in SDIF host driver. + - Added SDMMCHOST_ConvertDataToLittleEndian api. + - Added capability/maxBlockCount/maxBlockSize in host decriptior. + - Added mutual exclusive access for function init/deinit/reset/transfer function. + - Fixed violations of MISRA C-2012 rule 10.1. + + - 2.3.1 + - Improvements + - Added host instance capability macro. + - Added clear card inserted/removed event when card removed/inserted interrupt generated. + - Increased the reset timeout value to fix the data machine still busy after sdif reset issue. + - Enabled the error recovery function by adding host reset operations. + - Bug Fixes + - Fixed violations of MISRA C-2012 rule 11.9, 15.7, 4.7, 16.4, 10.1, 10.3, 10.4, 11.3, 14.4, 10.6, 17.7, 16.1, 16.3. + + - 2.3.0 + - Improvements + - Merged the host controller driver from polling/freertos/interrupt to non_blocking/blocking. + - Added SDMMC OSA layer to support muxtex access/event/delay. + + + - 2.2.14 + - Bug Fixes + - Fixed uninitialized value Coverity issue. + + - 2.2.13 + - Improvements: + - Added host reset after the card being powered on for host controller SDIF to fix the DATA_BUSY issue. + - Removed the SDIF_Reset from SDMMCHOST_Reset. + + - 2.0.0 + - Initial version + +*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/blocking/fsl_sdmmc_host.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/blocking/fsl_sdmmc_host.c new file mode 100644 index 0000000000..8e7dbd1e88 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/blocking/fsl_sdmmc_host.c @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sdmmc_host.h" +#include "fsl_sdmmc_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT (~0U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief SDMMCHOST error recovery. + * @param base host base address. + */ +static void SDMMCHOST_ErrorRecovery(SDIF_Type *base); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +status_t SDMMCHOST_CardIntInit(sdmmchost_t *host, void *sdioInt) +{ + host->cardInt = sdioInt; + + return kStatus_Success; +} + +status_t SDMMCHOST_CardDetectInit(sdmmchost_t *host, void *cd) +{ + if (cd == NULL) + { + return kStatus_Fail; + } + + host->cd = cd; + + return kStatus_Success; +} + +uint32_t SDMMCHOST_CardDetectStatus(sdmmchost_t *host) +{ + SDIF_Type *base = host->hostController.base; + sd_detect_card_t *sdCD = (sd_detect_card_t *)host->cd; + +#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD + if (((host->hostPort == 0U) && + (SDIF_DetectCardInsert(base, sdCD->type == kSD_DetectCardByHostDATA3 ? true : false) == 1U)) || + ((host->hostPort == 1U) && + (SDIF_DetectCard1Insert(base, sdCD->type == kSD_DetectCardByHostDATA3 ? true : false) == 1U))) +#else + if ((host->hostPort == 0U) && + (SDIF_DetectCardInsert(base, sdCD->type == kSD_DetectCardByHostDATA3 ? true : false) == 1U)) +#endif + { + return kSD_Inserted; + } + + return kSD_Removed; +} + +status_t SDMMCHOST_PollingCardDetectStatus(sdmmchost_t *host, uint32_t waitCardStatus, uint32_t timeout) +{ + assert(host != NULL); + assert(host->cd != NULL); + + sd_detect_card_t *cd = host->cd; + uint32_t cardInsertedStatus = kSD_Removed; + + /* Wait card inserted. */ + do + { + cardInsertedStatus = SDMMCHOST_CardDetectStatus(host); + + if ((waitCardStatus == (uint32_t)kSD_Inserted) && (cardInsertedStatus == (uint32_t)kSD_Inserted)) + { + SDMMC_OSADelay(cd->cdDebounce_ms); + if (SDMMCHOST_CardDetectStatus(host) == (uint32_t)kSD_Inserted) + { + break; + } + } + + if ((cardInsertedStatus == (uint32_t)kSD_Removed) && (waitCardStatus == (uint32_t)kSD_Removed)) + { + break; + } + } while (true); + + return kStatus_Success; +} + +status_t SDMMCHOST_TransferFunction(sdmmchost_t *host, sdmmchost_transfer_t *content) +{ + status_t error = kStatus_Success; + sdif_dma_config_t dmaConfig; + + (void)memset(&dmaConfig, 0, sizeof(dmaConfig)); + + /* user DMA mode transfer data */ + if (content->data != NULL) + { + dmaConfig.enableFixBurstLen = false; + dmaConfig.mode = kSDIF_ChainDMAMode; + dmaConfig.dmaDesBufferStartAddr = host->dmaDesBuffer; + dmaConfig.dmaDesBufferLen = host->dmaDesBufferWordsNum; + dmaConfig.dmaDesSkipLen = 0U; + } + + error = SDIF_TransferBlocking(host->hostController.base, &dmaConfig, content); + + if (error != kStatus_Success) + { + error = kStatus_Fail; + /* host error recovery */ + SDMMCHOST_ErrorRecovery(host->hostController.base); + } + + return error; +} + +static void SDMMCHOST_ErrorRecovery(SDIF_Type *base) +{ + (void)SDIF_Reset(base, kSDIF_ResetAll, SDMMCHOST_RESET_TIMEOUT_VALUE); + /* the host controller clock will be disabled by the reset operation, so re-send the clock sync command to enable + the output clock */ + sdif_command_t clockSync = { + .flags = kSDIF_WaitPreTransferComplete | kSDIF_CmdUpdateClockRegisterOnly, .index = 0U, .argument = 0U}; + (void)SDIF_SendCommand(base, &clockSync, 0U); +} + +void SDMMCHOST_SetCardPower(sdmmchost_t *host, bool enable) +{ + if (host->hostPort == 0U) + { + SDIF_EnableCardPower(host->hostController.base, enable); + } +#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD + else + { + SDIF_EnableCard1Power(host->hostController.base, enable); + } +#endif + + if (enable) + { + /* perform SDIF host controller reset only when DATA BUSY is assert */ + if ((SDIF_GetControllerStatus(host->hostController.base) & SDIF_STATUS_DATA_BUSY_MASK) != 0U) + { + (void)SDIF_Reset(host->hostController.base, kSDIF_ResetAll, SDMMCHOST_RESET_TIMEOUT_VALUE); + } + } +} + +void SDMMCHOST_ConvertDataToLittleEndian(sdmmchost_t *host, uint32_t *data, uint32_t wordSize, uint32_t format) +{ + uint32_t temp = 0U; + + if (format == kSDMMC_DataPacketFormatMSBFirst) + { + for (uint32_t i = 0U; i < wordSize; i++) + { + temp = data[i]; + data[i] = SWAP_WORD_BYTE_SEQUENCE(temp); + } + } +} + +status_t SDMMCHOST_Init(sdmmchost_t *host) +{ + assert(host != NULL); + + sdif_host_t *sdifHost = &(host->hostController); + + /* sdmmc osa init */ + SDMMC_OSAInit(); + /* host capability flags */ + host->capability = (uint32_t)kSDMMCHOST_SupportHighSpeed | (uint32_t)kSDMMCHOST_SupportSuspendResume | + (uint32_t)kSDMMCHOST_SupportVoltage3v3 | (uint32_t)kSDMMCHOST_Support4BitDataWidth | + (uint32_t)kSDMMCHOST_Support8BitDataWidth | (uint32_t)kSDMMCHOST_SupportDetectCardByData3 | + (uint32_t)kSDMMCHOST_SupportDetectCardByCD | (uint32_t)kSDMMCHOST_SupportAutoCmd12; + host->maxBlockCount = SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT; + host->maxBlockSize = SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH; + /* Initialize SDIF. */ + sdifHost->config.responseTimeout = 0xFFU; + sdifHost->config.cardDetDebounce_Clock = 0xFFFFFFU; + sdifHost->config.dataTimeout = 0xFFFFFFU; + SDIF_Init(sdifHost->base, &(sdifHost->config)); + + return kStatus_Success; +} + +void SDMMCHOST_Reset(sdmmchost_t *host) +{ + /* disable all the interrupt */ + SDIF_DisableInterrupt(host->hostController.base, kSDIF_AllInterruptStatus); + /* make sure host controller release all the bus line. */ + (void)SDIF_Reset(host->hostController.base, kSDIF_ResetAll, 100); + /* clear all interrupt/DMA status */ + SDIF_ClearInterruptStatus(host->hostController.base, kSDIF_AllInterruptStatus); + SDIF_ClearInternalDMAStatus(host->hostController.base, kSDIF_DMAAllStatus); +} + +void SDMMCHOST_SetCardBusWidth(sdmmchost_t *host, uint32_t dataBusWidth) +{ + if (host->hostPort == 0U) + { + SDIF_SetCardBusWidth(host->hostController.base, dataBusWidth == (uint32_t)kSDMMC_BusWdith1Bit ? + kSDIF_Bus1BitWidth : + dataBusWidth == (uint32_t)kSDMMC_BusWdith4Bit ? + kSDIF_Bus4BitWidth : + kSDIF_Bus8BitWidth); + } +#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD + else + { + SDIF_SetCard1BusWidth(host->hostController.base, dataBusWidth == (uint32_t)kSDMMC_BusWdith1Bit ? + kSDIF_Bus1BitWidth : + dataBusWidth == (uint32_t)kSDMMC_BusWdith4Bit ? + kSDIF_Bus4BitWidth : + kSDIF_Bus8BitWidth); + } +#endif +} + +void SDMMCHOST_Deinit(sdmmchost_t *host) +{ + sdif_host_t *sdifHost = &host->hostController; + SDIF_Deinit(sdifHost->base); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/fsl_sdmmc_host.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/fsl_sdmmc_host.h new file mode 100644 index 0000000000..a263ef6103 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/fsl_sdmmc_host.h @@ -0,0 +1,405 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SDMMC_HOST_H +#define _FSL_SDMMC_HOST_H + +#include "fsl_common.h" +#include "fsl_sdif.h" +#include "fsl_sdmmc_osa.h" +/*! + * @addtogroup sdmmchost_sdif SDIF HOST Adapter Driver + * @ingroup sdmmchost + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Middleware adapter version. */ +#define FSL_SDMMC_HOST_ADAPTER_VERSION (MAKE_VERSION(2U, 4U, 0U)) /*2.4.0*/ + +/*! @brief sdmmc host capability */ +enum +{ + kSDMMCHOST_SupportHighSpeed = 1U << 0U, /*!< high speed capability */ + kSDMMCHOST_SupportSuspendResume = 1U << 1U, /*!< suspend resume capability */ + kSDMMCHOST_SupportVoltage3v3 = 1U << 2U, /*!< 3V3 capability */ + kSDMMCHOST_SupportVoltage3v0 = 1U << 3U, /*!< 3V0 capability */ + kSDMMCHOST_SupportVoltage1v8 = 1U << 4U, /*!< 1V8 capability */ + kSDMMCHOST_SupportVoltage1v2 = 1U << 5U, /*!< 1V2 capability */ + kSDMMCHOST_Support4BitDataWidth = 1U << 6U, /*!< 4 bit data width capability */ + kSDMMCHOST_Support8BitDataWidth = 1U << 7U, /*!< 8 bit data width capability */ + kSDMMCHOST_SupportDDRMode = 1U << 8U, /*!< DDR mode capability */ + kSDMMCHOST_SupportDetectCardByData3 = 1U << 9U, /*!< data3 detect card capability */ + kSDMMCHOST_SupportDetectCardByCD = 1U << 10U, /*!< CD detect card capability */ + kSDMMCHOST_SupportAutoCmd12 = 1U << 11U, /*!< auto command 12 capability */ + kSDMMCHOST_SupportSDR104 = 1U << 12U, /*!< SDR104 capability */ + kSDMMCHOST_SupportSDR50 = 1U << 13U, /*!< SDR50 capability */ + kSDMMCHOST_SupportHS200 = 1U << 14U, /*!< HS200 capability */ + kSDMMCHOST_SupportHS400 = 1U << 15U, /*!< HS400 capability */ +}; + +/*!@brief host capability */ +#define SDMMCHOST_SUPPORT_HIGH_SPEED (1U) +#define SDMMCHOST_SUPPORT_SUSPEND_RESUME (1U) +#define SDMMCHOST_SUPPORT_VOLTAGE_3V3 (1U) +#define SDMMCHOST_SUPPORT_VOLTAGE_3V0 (0U) +#define SDMMCHOST_SUPPORT_VOLTAGE_1V8 (0U) +#define SDMMCHOST_SUPPORT_VOLTAGE_1V2 (0U) +#define SDMMCHOST_SUPPORT_4_BIT_WIDTH (1U) +#define SDMMCHOST_SUPPORT_8_BIT_WIDTH (1U) +#define SDMMCHOST_SUPPORT_DDR50 (0U) +#define SDMMCHOST_SUPPORT_SDR104 (0U) +#define SDMMCHOST_SUPPORT_SDR50 (0U) +#define SDMMCHOST_SUPPORT_HS200 (0U) +#define SDMMCHOST_SUPPORT_HS400 (0U) +#define SDMMCHOST_SUPPORT_DETECT_CARD_BY_DATA3 (1U) +#define SDMMCHOST_SUPPORT_DETECT_CARD_BY_CD (1U) +#define SDMMCHOST_SUPPORT_AUTO_CMD12 (1U) +#define SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH (SDIF_BLKSIZ_BLOCK_SIZE_MASK) +#define SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT (SDIF_BYTCNT_BYTE_COUNT_MASK / SDIF_BLKSIZ_BLOCK_SIZE_MASK) +/*! @brief sdmmc host instance capability */ +#define SDMMCHOST_INSTANCE_SUPPORT_8_BIT_WIDTH(host) 1U +#define SDMMCHOST_INSTANCE_SUPPORT_HS400(host) 0U +#define SDMMCHOST_INSTANCE_SUPPORT_1V8_SIGNAL(host) 0U +#define SDMMCHOST_INSTANCE_SUPPORT_HS200(host) 0U +#define SDMMCHOST_INSTANCE_SUPPORT_SDR104(host) 0U +#define SDMMCHOST_INSTANCE_SUPPORT_SDR50(host) 0U +#define SDMMCHOST_INSTANCE_SUPPORT_DDR50(host) 0U + +/*!@brief SDMMC host dma descriptor buffer address align size */ +#define SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE (4U) +/*! @brief SDMMC host reset timoue value */ +#define SDMMCHOST_RESET_TIMEOUT_VALUE (1000000U) + +/*! @brief host Endian mode + * corresponding to driver define + */ +enum _sdmmchost_endian_mode +{ + kSDMMCHOST_EndianModeBig = 0U, /*!< Big endian mode */ + kSDMMCHOST_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ + kSDMMCHOST_EndianModeLittle = 2U, /*!< Little endian mode */ +}; + +/*!@brief sdmmc host transfer function */ +typedef sdif_transfer_t sdmmchost_transfer_t; +typedef sdif_command_t sdmmchost_cmd_t; +typedef sdif_data_t sdmmchost_data_t; +typedef struct _sdmmchost_ SDMMCHOST_CONFIG; +typedef SDIF_Type SDMMCHOST_TYPE; +typedef void sdmmchost_detect_card_t; +typedef void sdmmchost_boot_config_t; + +/*!@brief sdmmc host handler */ +typedef struct _sdmmchost_ +{ + sdif_host_t hostController; /*!< host configuration */ + uint8_t hostPort; /*!< host port number, used for one instance support two card */ + void *dmaDesBuffer; /*!< DMA descriptor buffer address */ + uint32_t dmaDesBufferWordsNum; /*!< DMA descriptor buffer size in byte */ + sdif_handle_t handle; /*!< host controller handler */ + + uint32_t capability; /*!< host controller capability */ + uint32_t maxBlockCount; /*!< host controller maximum block count */ + uint32_t maxBlockSize; /*!< host controller maximum block size */ + + sdmmc_osa_event_t hostEvent; /*!< host event handler */ + void *cd; /*!< card detect */ + void *cardInt; /*!< call back function for card interrupt */ + sdmmc_osa_mutex_t lock; /*!< host access lock */ +} sdmmchost_t; + +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SDIF host controller function + * @{ + */ + +/*! + * @brief set data bus width. + * @param host host handler + * @param dataBusWidth data bus width + */ +void SDMMCHOST_SetCardBusWidth(sdmmchost_t *host, uint32_t dataBusWidth); + +/*! + * @brief Send initilization active 80 clocks to card. + * @param host host handler + */ +static inline void SDMMCHOST_SendCardActive(sdmmchost_t *host) +{ + SDIF_SendCardActive(host->hostController.base, 100U); +} + +/*! + * @brief Set card bus clock. + * @param host host handler + * @param targetClock target clock frequency + * @retval actual clock frequency can be reach. + */ +static inline uint32_t SDMMCHOST_SetCardClock(sdmmchost_t *host, uint32_t targetClock) +{ + return SDIF_SetCardClock(host->hostController.base, host->hostController.sourceClock_Hz, targetClock); +} + +/*! + * @brief check card status by DATA0. + * @param host host handler + * @retval true is busy, false is idle. + */ +static inline bool SDMMCHOST_IsCardBusy(sdmmchost_t *host) +{ + return (SDIF_GetControllerStatus(host->hostController.base) & SDIF_STATUS_DATA_BUSY_MASK) == + SDIF_STATUS_DATA_BUSY_MASK ? + true : + false; +} + +/*! + * @brief start read boot data. + * @param host host handler + * @param hostConfig boot configuration + * @param cmd boot command + * @param buffer buffer address + */ +static inline status_t SDMMCHOST_StartBoot(sdmmchost_t *host, + sdmmchost_boot_config_t *hostConfig, + sdmmchost_cmd_t *cmd, + uint8_t *buffer) +{ + /* host not support */ + return kStatus_Fail; +} + +/*! + * @brief read boot data. + * @param host host handler + * @param hostConfig boot configuration + * @param buffer buffer address + */ +static inline status_t SDMMCHOST_ReadBootData(sdmmchost_t *host, sdmmchost_boot_config_t *hostConfig, uint8_t *buffer) +{ + /* host not support */ + return kStatus_Fail; +} + +/*! + * @brief enable boot mode. + * @param host host handler + * @param enable true is enable, false is disable + */ +static inline void SDMMCHOST_EnableBoot(sdmmchost_t *host, bool enable) +{ + /* not support */ +} + +/*! + * @brief enable card interrupt. + * @param host host handler + * @param enable true is enable, false is disable. + */ +static inline void SDMMCHOST_EnableCardInt(sdmmchost_t *host, bool enable) +{ + if (enable) + { + SDIF_EnableInterrupt(host->hostController.base, kSDIF_SDIOInterrupt); + } + else + { + SDIF_DisableInterrupt(host->hostController.base, kSDIF_SDIOInterrupt); + } +} + +/*! + * @brief card interrupt function. + * @param host host handler + * @param sdioInt card interrupt configuration + */ +status_t SDMMCHOST_CardIntInit(sdmmchost_t *host, void *sdioInt); + +/*! + * @brief card detect init function. + * @param host host handler + * @param cd card detect configuration + */ +status_t SDMMCHOST_CardDetectInit(sdmmchost_t *host, void *cd); + +/*! + * @brief Detect card insert, only need for SD cases. + * @param host host handler + * @param waitCardStatus status which user want to wait + * @param timeout wait time out. + * @retval kStatus_Success detect card insert + * @retval kStatus_Fail card insert event fail + */ +status_t SDMMCHOST_PollingCardDetectStatus(sdmmchost_t *host, uint32_t waitCardStatus, uint32_t timeout); + +/*! + * @brief card detect status. + * @param host host handler + * @retval kSD_Inserted, kSD_Removed + */ +uint32_t SDMMCHOST_CardDetectStatus(sdmmchost_t *host); + +/*! + * @brief Init host controller. + * + * Thread safe function, please note that the function will create the mutex lock dynamically by default, + * so to avoid the mutex create redundantly, application must follow bellow sequence for card re-initialization + * @code + * SDMMCHOST_Deinit(host); + * SDMMCHOST_Init(host); + * @endcode + * + * @param host host handler + * @retval kStatus_Success host init success + * @retval kStatus_Fail event fail + */ +status_t SDMMCHOST_Init(sdmmchost_t *host); + +/*! + * @brief Deinit host controller. + * + * Please note it is a thread safe function. + * + * @param host host handler + */ +void SDMMCHOST_Deinit(sdmmchost_t *host); + +/*! + * @brief host power off card function. + * @param host host handler + * @param enable true is power on, false is power down. + */ +void SDMMCHOST_SetCardPower(sdmmchost_t *host, bool enable); + +/*! + * @brief host transfer function. + * + * Please note it is a thread safe function. + * + * @param host host handler + * @param content transfer content. + */ +status_t SDMMCHOST_TransferFunction(sdmmchost_t *host, sdmmchost_transfer_t *content); + +/*! + * @brief host reset function. + * + * Please note it is a thread safe function. + * + * @param host host handler + */ +void SDMMCHOST_Reset(sdmmchost_t *host); + +/*! + * @brief switch to voltage. + * @param host host handler + * @param voltage switch to voltage level. + */ +static inline void SDMMCHOST_SwitchToVoltage(sdmmchost_t *host, uint32_t voltage) +{ + /* host not support */ +} + +/*! + * @brief sdmmc host excute tuning. + * + * @param host host handler + * @param tuningCmd tuning command. + * @param revBuf receive buffer pointer + * @param blockSize tuning data block size. + */ +static inline status_t SDMMCHOST_ExecuteTuning(sdmmchost_t *host, + uint32_t tuningCmd, + uint32_t *revBuf, + uint32_t blockSize) +{ + /* host not support */ + return kStatus_Fail; +} + +/*! + * @brief enable DDR mode. + * @param host host handler + * @param enable true is enable, false is disable. + * @param nibblePos nibble position indictation. 0- the sequence is 'odd high nibble -> even high nibble -> + * odd low nibble -> even low nibble'; 1- the sequence is 'odd high nibble -> odd low nibble -> even high + * nibble -> even low nibble'. + */ +static inline void SDMMCHOST_EnableDDRMode(sdmmchost_t *host, bool enable, uint32_t nibblePos) +{ + /* host not support */ +} + +/*! + * @brief enable HS400 mode. + * @param host host handler + * @param enable true is enable, false is disable. + */ +static inline void SDMMCHOST_EnableHS400Mode(sdmmchost_t *host, bool enable) +{ + /* host not support */ +} + +/*! + * @brief enable STROBE DLL. + * @param host host handler + * @param enable true is enable, false is disable. + */ +static inline void SDMMCHOST_EnableStrobeDll(sdmmchost_t *host, bool enable) +{ + /* host not support */ +} + +/*! + * @brief Get signal line status. + * @param host host handler + * @param signalLine signal line type, reference _sdmmc_signal_line + */ +static inline uint32_t SDMMCHOST_GetSignalLineStatus(sdmmchost_t *host, uint32_t signalLine) +{ + /* host not support */ + return 0U; +} + +/*! + * @brief force card clock on. + * @param host host handler + * @param enable true is enable, false is disable. + */ +static inline void SDMMCHOST_ForceClockOn(sdmmchost_t *host, bool enable) +{ + /* host not support */ +} + +/*! + * @brief sdmmc host convert data sequence to little endian sequence + * + * @param host host handler. + * @param data data buffer address. + * @param wordSize data buffer size in word. + * @param format data packet format. + */ +void SDMMCHOST_ConvertDataToLittleEndian(sdmmchost_t *host, uint32_t *data, uint32_t wordSize, uint32_t format); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/* @} */ +#endif /* _FSL_SDMMC_HOST_H */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/non_blocking/fsl_sdmmc_host.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/non_blocking/fsl_sdmmc_host.c new file mode 100644 index 0000000000..2f694f58ee --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/host/sdif/non_blocking/fsl_sdmmc_host.c @@ -0,0 +1,457 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sdmmc_host.h" +#include "fsl_sdmmc_common.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT (~0U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief SDMMCHOST detect card insert status by host controller. + * @param base host base address. + * @param userData user can register a application card insert callback through userData. + */ +static void SDMMCHOST_DetectCardInsertByHost(SDIF_Type *base, void *userData); + +/*! + * @brief SDMMCHOST detect card remove status by host controller. + * @param base host base address. + * @param userData user can register a application card insert callback through userData. + */ +static void SDMMCHOST_DetectCardRemoveByHost(SDIF_Type *base, void *userData); + +/*! + * @brief SDMMCHOST transfer complete callback. + * @param base host base address. + * @param handle host handle. + * @param status interrupt status. + * @param userData user data. + */ +static void SDMMCHOST_TransferCompleteCallback(SDIF_Type *base, void *handle, status_t status, void *userData); + +/*! + * @brief SDMMCHOST error recovery. + * @param base host base address. + */ +static void SDMMCHOST_ErrorRecovery(SDIF_Type *base); +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +static void SDMMCHOST_DetectCardInsertByHost(SDIF_Type *base, void *userData) +{ + sd_detect_card_t *cd = NULL; + + (void)SDMMC_OSAEventSet(&(((sdmmchost_t *)userData)->hostEvent), SDMMC_OSA_EVENT_CARD_INSERTED); + (void)SDMMC_OSAEventClear(&(((sdmmchost_t *)userData)->hostEvent), SDMMC_OSA_EVENT_CARD_REMOVED); + + if (userData != NULL) + { + cd = (sd_detect_card_t *)(((sdmmchost_t *)userData)->cd); + if (cd != NULL) + { + if (cd->callback != NULL) + { + cd->callback(true, cd->userData); + } + } + } +} + +static void SDMMCHOST_DetectCardRemoveByHost(SDIF_Type *base, void *userData) +{ + sd_detect_card_t *cd = NULL; + + (void)SDMMC_OSAEventSet(&(((sdmmchost_t *)userData)->hostEvent), SDMMC_OSA_EVENT_CARD_REMOVED); + (void)SDMMC_OSAEventClear(&(((sdmmchost_t *)userData)->hostEvent), SDMMC_OSA_EVENT_CARD_INSERTED); + + if (userData != NULL) + { + cd = (sd_detect_card_t *)(((sdmmchost_t *)userData)->cd); + if (cd != NULL) + { + if (cd->callback != NULL) + { + cd->callback(false, cd->userData); + } + } + } +} + +static void SDMMCHOST_CardInterrupt(SDIF_Type *base, void *userData) +{ + sdio_card_int_t *cardInt = NULL; + + /* application callback */ + if (userData != NULL) + { + cardInt = ((sdmmchost_t *)userData)->cardInt; + if ((cardInt != NULL) && (cardInt->cardInterrupt != NULL)) + { + cardInt->cardInterrupt(cardInt->userData); + } + } +} + +status_t SDMMCHOST_CardIntInit(sdmmchost_t *host, void *sdioInt) +{ + host->cardInt = sdioInt; + host->handle.callback.SDIOInterrupt = SDMMCHOST_CardInterrupt; + SDMMCHOST_EnableCardInt(host, true); + + return kStatus_Success; +} + +status_t SDMMCHOST_CardDetectInit(sdmmchost_t *host, void *cd) +{ + SDIF_Type *base = host->hostController.base; + sd_detect_card_t *sdCD = (sd_detect_card_t *)cd; + if (cd == NULL) + { + return kStatus_Fail; + } + + host->cd = cd; + + /* enable card detect interrupt */ + SDIF_EnableInterrupt(base, kSDIF_CardDetect); + + if (SDMMCHOST_CardDetectStatus(host) == (uint32_t)kSD_Inserted) + { + (void)SDMMC_OSAEventSet(&(host->hostEvent), SDMMC_OSA_EVENT_CARD_INSERTED); + /* notify application about the card insertion status */ + if (sdCD->callback != NULL) + { + sdCD->callback(true, sdCD->userData); + } + } + else + { + (void)SDMMC_OSAEventSet(&(host->hostEvent), SDMMC_OSA_EVENT_CARD_REMOVED); + } + + return kStatus_Success; +} + +uint32_t SDMMCHOST_CardDetectStatus(sdmmchost_t *host) +{ + SDIF_Type *base = host->hostController.base; + sd_detect_card_t *sdCD = (sd_detect_card_t *)host->cd; + +#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD + if (((host->hostPort == 0U) && + (SDIF_DetectCardInsert(base, sdCD->type == kSD_DetectCardByHostDATA3 ? true : false) == 1U)) || + ((host->hostPort == 1U) && + (SDIF_DetectCard1Insert(base, sdCD->type == kSD_DetectCardByHostDATA3 ? true : false) == 1U))) +#else + if ((host->hostPort == 0U) && + (SDIF_DetectCardInsert(base, sdCD->type == kSD_DetectCardByHostDATA3 ? true : false) == 1U)) +#endif + { + return kSD_Inserted; + } + + return kSD_Removed; +} + +status_t SDMMCHOST_PollingCardDetectStatus(sdmmchost_t *host, uint32_t waitCardStatus, uint32_t timeout) +{ + assert(host != NULL); + assert(host->cd != NULL); + + sd_detect_card_t *cd = host->cd; + uint32_t event = 0U; + + (void)SDMMC_OSAEventGet(&(host->hostEvent), SDMMC_OSA_EVENT_CARD_INSERTED | SDMMC_OSA_EVENT_CARD_REMOVED, &event); + if ((((event & SDMMC_OSA_EVENT_CARD_INSERTED) == SDMMC_OSA_EVENT_CARD_INSERTED) && + (waitCardStatus == (uint32_t)kSD_Inserted)) || + (((event & SDMMC_OSA_EVENT_CARD_REMOVED) == SDMMC_OSA_EVENT_CARD_REMOVED) && + (waitCardStatus == (uint32_t)kSD_Removed))) + { + return kStatus_Success; + } + + /* Wait card inserted. */ + do + { + if (SDMMC_OSAEventWait(&(host->hostEvent), SDMMC_OSA_EVENT_CARD_INSERTED | SDMMC_OSA_EVENT_CARD_REMOVED, + timeout, &event) != kStatus_Success) + { + return kStatus_Fail; + } + else + { + if ((waitCardStatus == (uint32_t)kSD_Inserted) && + ((event & SDMMC_OSA_EVENT_CARD_INSERTED) == SDMMC_OSA_EVENT_CARD_INSERTED)) + { + SDMMC_OSADelay(cd->cdDebounce_ms); + if (SDMMCHOST_CardDetectStatus(host) == (uint32_t)kSD_Inserted) + { + break; + } + } + + if (((event & SDMMC_OSA_EVENT_CARD_REMOVED) == SDMMC_OSA_EVENT_CARD_REMOVED) && + (waitCardStatus == (uint32_t)kSD_Removed)) + { + break; + } + } + } while (true); + + return kStatus_Success; +} + +static void SDMMCHOST_TransferCompleteCallback(SDIF_Type *base, void *handle, status_t status, void *userData) +{ + uint32_t eventStatus = 0U; + + if (status == kStatus_SDIF_DataTransferFail) + { + eventStatus = SDMMC_OSA_EVENT_TRANSFER_DATA_FAIL; + } + else if (status == kStatus_SDIF_DataTransferSuccess) + { + eventStatus = SDMMC_OSA_EVENT_TRANSFER_DATA_SUCCESS; + } + else if (status == kStatus_SDIF_SendCmdFail) + { + eventStatus = SDMMC_OSA_EVENT_TRANSFER_CMD_FAIL; + } + else + { + eventStatus = SDMMC_OSA_EVENT_TRANSFER_CMD_SUCCESS; + } + + (void)SDMMC_OSAEventSet(&(((sdmmchost_t *)userData)->hostEvent), eventStatus); +} + +status_t SDMMCHOST_TransferFunction(sdmmchost_t *host, sdmmchost_transfer_t *content) +{ + status_t error = kStatus_Success; + uint32_t event = 0U; + sdif_dma_config_t dmaConfig; + + SDMMC_OSAMutexLock(&host->lock, osaWaitForever_c); + + /* clear redundant transfer event flag */ + (void)SDMMC_OSAEventClear(&(host->hostEvent), + SDMMC_OSA_EVENT_TRANSFER_CMD_SUCCESS | SDMMC_OSA_EVENT_TRANSFER_CMD_FAIL | + SDMMC_OSA_EVENT_TRANSFER_DATA_SUCCESS | SDMMC_OSA_EVENT_TRANSFER_DATA_FAIL); + + /* user DMA mode transfer data */ + if (content->data != NULL) + { + (void)memset(&dmaConfig, 0, sizeof(dmaConfig)); + + dmaConfig.enableFixBurstLen = false; + dmaConfig.mode = kSDIF_DualDMAMode; + dmaConfig.dmaDesBufferStartAddr = host->dmaDesBuffer; + dmaConfig.dmaDesBufferLen = host->dmaDesBufferWordsNum; + dmaConfig.dmaDesSkipLen = 0U; + } + + do + { + error = SDIF_TransferNonBlocking(host->hostController.base, &host->handle, &dmaConfig, content); + } while (error == kStatus_SDIF_SyncCmdTimeout); + + if (error == kStatus_Success) + { + /* wait command event */ + if ((kStatus_Fail == + SDMMC_OSAEventWait(&(host->hostEvent), + SDMMC_OSA_EVENT_TRANSFER_CMD_SUCCESS | SDMMC_OSA_EVENT_TRANSFER_CMD_FAIL | + SDMMC_OSA_EVENT_TRANSFER_DATA_SUCCESS | SDMMC_OSA_EVENT_TRANSFER_DATA_FAIL, + SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT, &event)) || + ((event & SDMMC_OSA_EVENT_TRANSFER_CMD_FAIL) != 0U)) + { + error = kStatus_Fail; + } + else + { + if (content->data != NULL) + { + if ((event & SDMMC_OSA_EVENT_TRANSFER_DATA_SUCCESS) == 0U) + { + if (((event & SDMMC_OSA_EVENT_TRANSFER_DATA_FAIL) != 0U) || + (kStatus_Fail == SDMMC_OSAEventWait( + &(host->hostEvent), + SDMMC_OSA_EVENT_TRANSFER_DATA_SUCCESS | SDMMC_OSA_EVENT_TRANSFER_DATA_FAIL, + SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT, &event) || + ((event & SDMMC_OSA_EVENT_TRANSFER_DATA_FAIL) != 0U))) + { + error = kStatus_Fail; + } + } + } + } + } + /* + * error = kStatus_SDIF_DescriptorBufferLenError means that the DMA descriptor buffer not len enough for current + * transfer, application should assign a bigger descriptor memory space. + */ + if (error != kStatus_Success) + { + error = kStatus_Fail; + /* host error recovery */ + SDMMCHOST_ErrorRecovery(host->hostController.base); + } + + SDMMC_OSAMutexUnlock(&host->lock); + + return error; +} + +static void SDMMCHOST_ErrorRecovery(SDIF_Type *base) +{ + (void)SDIF_Reset(base, kSDIF_ResetAll, SDMMCHOST_RESET_TIMEOUT_VALUE); + + /* the host controller clock will be disabled by the reset operation, so re-send the clock sync command to enable + the output clock */ + sdif_command_t clockSync = { + .flags = kSDIF_WaitPreTransferComplete | kSDIF_CmdUpdateClockRegisterOnly, .index = 0U, .argument = 0U}; + (void)SDIF_SendCommand(base, &clockSync, 0U); +} + +void SDMMCHOST_SetCardPower(sdmmchost_t *host, bool enable) +{ + if (host->hostPort == 0U) + { + SDIF_EnableCardPower(host->hostController.base, enable); + } +#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD + else + { + SDIF_EnableCard1Power(host->hostController.base, enable); + } +#endif + + if (enable) + { + /* perform SDIF host controller reset only when DATA BUSY is assert */ + if ((SDIF_GetControllerStatus(host->hostController.base) & SDIF_STATUS_DATA_BUSY_MASK) != 0U) + { + (void)SDIF_Reset(host->hostController.base, kSDIF_ResetAll, SDMMCHOST_RESET_TIMEOUT_VALUE); + } + } +} + +void SDMMCHOST_ConvertDataToLittleEndian(sdmmchost_t *host, uint32_t *data, uint32_t wordSize, uint32_t format) +{ + uint32_t temp = 0U; + + if (format == kSDMMC_DataPacketFormatMSBFirst) + { + for (uint32_t i = 0U; i < wordSize; i++) + { + temp = data[i]; + data[i] = SWAP_WORD_BYTE_SEQUENCE(temp); + } + } +} + +status_t SDMMCHOST_Init(sdmmchost_t *host) +{ + assert(host != NULL); + + sdif_transfer_callback_t sdifCallback = {0}; + sdif_host_t *sdifHost = &(host->hostController); + status_t error = kStatus_Success; + + /* host capability flags */ + host->capability = (uint32_t)kSDMMCHOST_SupportHighSpeed | (uint32_t)kSDMMCHOST_SupportSuspendResume | + (uint32_t)kSDMMCHOST_SupportVoltage3v3 | (uint32_t)kSDMMCHOST_Support4BitDataWidth | + (uint32_t)kSDMMCHOST_Support8BitDataWidth | (uint32_t)kSDMMCHOST_SupportDetectCardByData3 | + (uint32_t)kSDMMCHOST_SupportDetectCardByCD | (uint32_t)kSDMMCHOST_SupportAutoCmd12; + host->maxBlockCount = SDMMCHOST_SUPPORT_MAX_BLOCK_COUNT; + host->maxBlockSize = SDMMCHOST_SUPPORT_MAX_BLOCK_LENGTH; + + /* sdmmc osa init */ + SDMMC_OSAInit(); + + SDMMC_OSAMutexCreate(&host->lock); + SDMMC_OSAMutexLock(&host->lock, osaWaitForever_c); + + /* Initialize SDIF. */ + sdifHost->config.responseTimeout = 0xFFU; + sdifHost->config.cardDetDebounce_Clock = 0xFFFFFFU; + sdifHost->config.dataTimeout = 0xFFFFFFU; + SDIF_Init(sdifHost->base, &(sdifHost->config)); + + /* Create handle for SDIF driver */ + sdifCallback.TransferComplete = SDMMCHOST_TransferCompleteCallback; + sdifCallback.cardInserted = SDMMCHOST_DetectCardInsertByHost; + sdifCallback.cardRemoved = SDMMCHOST_DetectCardRemoveByHost; + SDIF_TransferCreateHandle(sdifHost->base, &host->handle, &sdifCallback, host); + + /* Create transfer event. */ + if (kStatus_Success != SDMMC_OSAEventCreate(&(host->hostEvent))) + { + error = kStatus_Fail; + } + + SDMMC_OSAMutexUnlock(&host->lock); + + return error; +} + +void SDMMCHOST_Reset(sdmmchost_t *host) +{ + SDMMC_OSAMutexLock(&host->lock, osaWaitForever_c); + + /* disable all the interrupt */ + SDIF_DisableInterrupt(host->hostController.base, kSDIF_AllInterruptStatus); + + /* make sure host controller release all the bus line. */ + (void)SDIF_Reset(host->hostController.base, kSDIF_ResetAll, SDMMCHOST_RESET_TIMEOUT_VALUE); + + /* clear all interrupt/DMA status */ + SDIF_ClearInterruptStatus(host->hostController.base, kSDIF_AllInterruptStatus); + SDIF_ClearInternalDMAStatus(host->hostController.base, kSDIF_DMAAllStatus); + + SDMMC_OSAMutexUnlock(&host->lock); +} + +void SDMMCHOST_SetCardBusWidth(sdmmchost_t *host, uint32_t dataBusWidth) +{ + if (host->hostPort == 0U) + { + SDIF_SetCardBusWidth(host->hostController.base, dataBusWidth == (uint32_t)kSDMMC_BusWdith1Bit ? + kSDIF_Bus1BitWidth : + dataBusWidth == (uint32_t)kSDMMC_BusWdith4Bit ? + kSDIF_Bus4BitWidth : + kSDIF_Bus8BitWidth); + } +#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD + else + { + SDIF_SetCard1BusWidth(host->hostController.base, dataBusWidth == (uint32_t)kSDMMC_BusWdith1Bit ? + kSDIF_Bus1BitWidth : + dataBusWidth == (uint32_t)kSDMMC_BusWdith4Bit ? + kSDIF_Bus4BitWidth : + kSDIF_Bus8BitWidth); + } +#endif +} + +void SDMMCHOST_Deinit(sdmmchost_t *host) +{ + SDMMC_OSAMutexLock(&host->lock, osaWaitForever_c); + sdif_host_t *sdifHost = &host->hostController; + SDIF_Deinit(sdifHost->base); + (void)SDMMC_OSAEventDestroy(&(host->hostEvent)); + SDMMC_OSAMutexDestroy(&host->lock); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_mmc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_mmc.h deleted file mode 100644 index 986db0d1e1..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_mmc.h +++ /dev/null @@ -1,321 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_MMC_H_ -#define _FSL_MMC_H_ - -#include "fsl_sdmmc_common.h" - -/*! - * @addtogroup MMCCARD - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief MMC card flags */ -enum _mmc_card_flag -{ - kMMC_SupportHighSpeed26MHZFlag = (1U << 0U), /*!< Support high speed 26MHZ */ - kMMC_SupportHighSpeed52MHZFlag = (1U << 1U), /*!< Support high speed 52MHZ */ - kMMC_SupportHighSpeedDDR52MHZ180V300VFlag = (1 << 2U), /*!< ddr 52MHZ 1.8V or 3.0V */ - kMMC_SupportHighSpeedDDR52MHZ120VFlag = (1 << 3U), /*!< DDR 52MHZ 1.2V */ - kMMC_SupportHS200200MHZ180VFlag = (1 << 4U), /*!< HS200 ,200MHZ,1.8V */ - kMMC_SupportHS200200MHZ120VFlag = (1 << 5U), /*!< HS200, 200MHZ, 1.2V */ - kMMC_SupportHS400DDR200MHZ180VFlag = (1 << 6U), /*!< HS400, DDR, 200MHZ,1.8V */ - kMMC_SupportHS400DDR200MHZ120VFlag = (1 << 7U), /*!< HS400, DDR, 200MHZ,1.2V */ - kMMC_SupportHighCapacityFlag = (1U << 8U), /*!< Support high capacity */ - kMMC_SupportAlternateBootFlag = (1U << 9U), /*!< Support alternate boot */ - kMMC_SupportDDRBootFlag = (1U << 10U), /*!< support DDR boot flag*/ - kMMC_SupportHighSpeedBootFlag = (1U << 11U), /*!< support high speed boot flag*/ -}; - -/*! - * @brief mmc card state - * - * Define the card structure including the necessary fields to identify and describe the card. - */ -typedef struct _mmc_card -{ - SDMMCHOST_CONFIG host; /*!< Host information */ - mmccard_usr_param_t usrParam; /*!< user parameter */ - - bool isHostReady; /*!< Use this flag to indicate if need host re-init or not*/ - bool noInteralAlign; /*!< use this flag to disable sdmmc align. If disable, sdmmc will not make sure the - data buffer address is word align, otherwise all the transfer are align to low level driver */ - uint32_t busClock_Hz; /*!< MMC bus clock united in Hz */ - uint32_t relativeAddress; /*!< Relative address of the card */ - bool enablePreDefinedBlockCount; /*!< Enable PRE-DEFINED block count when read/write */ - uint32_t flags; /*!< Capability flag in _mmc_card_flag */ - uint32_t rawCid[4U]; /*!< Raw CID content */ - uint32_t rawCsd[4U]; /*!< Raw CSD content */ - uint32_t rawExtendedCsd[MMC_EXTENDED_CSD_BYTES / 4U]; /*!< Raw MMC Extended CSD content */ - uint32_t ocr; /*!< Raw OCR content */ - mmc_cid_t cid; /*!< CID */ - mmc_csd_t csd; /*!< CSD */ - mmc_extended_csd_t extendedCsd; /*!< Extended CSD */ - uint32_t blockSize; /*!< Card block size */ - uint32_t userPartitionBlocks; /*!< Card total block number in user partition */ - uint32_t bootPartitionBlocks; /*!< Boot partition size united as block size */ - uint32_t eraseGroupBlocks; /*!< Erase group size united as block size */ - mmc_access_partition_t currentPartition; /*!< Current access partition */ - mmc_voltage_window_t hostVoltageWindowVCCQ; /*!< Host IO voltage window */ - mmc_voltage_window_t hostVoltageWindowVCC; /*!< application must set this value according to board specific */ - mmc_high_speed_timing_t busTiming; /*!< indicate the current work timing mode*/ - mmc_data_bus_width_t busWidth; /*!< indicate the current work bus width */ -} mmc_card_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name MMCCARD Function - * @{ - */ - -/*! - * @brief Initializes the MMC card and host. - * - * @param card Card descriptor. - * - * @retval kStatus_SDMMC_HostNotReady host is not ready. - * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. - * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. - * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. - * @retval kStatus_SDMMC_SetRelativeAddressFailed Set relative address failed. - * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. - * @retval kStatus_SDMMC_CardNotSupport Card not support. - * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. - * @retval kStatus_SDMMC_SendExtendedCsdFailed Send EXT_CSD failed. - * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. - * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. - * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_Init(mmc_card_t *card); - -/*! - * @brief Deinitializes the card and host. - * - * @param card Card descriptor. - */ -void MMC_Deinit(mmc_card_t *card); - -/*! - * @brief intialize the card. - * - * @param card Card descriptor. - * - * @retval kStatus_SDMMC_HostNotReady host is not ready. - * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. - * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. - * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. - * @retval kStatus_SDMMC_SetRelativeAddressFailed Set relative address failed. - * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. - * @retval kStatus_SDMMC_CardNotSupport Card not support. - * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. - * @retval kStatus_SDMMC_SendExtendedCsdFailed Send EXT_CSD failed. - * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. - * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. - * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_CardInit(mmc_card_t *card); - -/*! - * @brief Deinitializes the card. - * - * @param card Card descriptor. - */ -void MMC_CardDeinit(mmc_card_t *card); - -/*! - * @brief initialize the host. - * - * This function deinitializes the specific host. - * - * @param card Card descriptor. - */ -status_t MMC_HostInit(mmc_card_t *card); - -/*! - * @brief Deinitializes the host. - * - * This function deinitializes the host. - * - * @param card Card descriptor. - */ -void MMC_HostDeinit(mmc_card_t *card); - -/*! - * @brief reset the host. - * - * This function reset the specific host. - * - * @param host host descriptor. - */ -void MMC_HostReset(SDMMCHOST_CONFIG *host); - -/*! - * @brief power on card. - * - * The power on operation depend on host or the user define power on function. - * @param base host base address. - * @param pwr user define power control configuration - */ -void MMC_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); - -/*! - * @brief power off card. - * - * The power off operation depend on host or the user define power on function. - * @param base host base address. - * @param pwr user define power control configuration - */ -void MMC_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); - -/*! - * @brief Checks if the card is read-only. - * - * @param card Card descriptor. - * @retval true Card is read only. - * @retval false Card isn't read only. - */ -bool MMC_CheckReadOnly(mmc_card_t *card); - -/*! - * @brief Reads data blocks from the card. - * - * @param card Card descriptor. - * @param buffer The buffer to save data. - * @param startBlock The start block index. - * @param blockCount The number of blocks to read. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_CardNotSupport Card not support. - * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_ReadBlocks(mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief Writes data blocks to the card. - * - * @param card Card descriptor. - * @param buffer The buffer to save data blocks. - * @param startBlock Start block number to write. - * @param blockCount Block count. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_NotSupportYet Not support now. - * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_WriteBlocks(mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief Erases groups of the card. - * - * Erase group is the smallest erase unit in MMC card. The erase range is [startGroup, endGroup]. - * - * @param card Card descriptor. - * @param startGroup Start group number. - * @param endGroup End group number. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_EraseGroups(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup); - -/*! - * @brief Selects the partition to access. - * - * @param card Card descriptor. - * @param partitionNumber The partition number. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_SelectPartition(mmc_card_t *card, mmc_access_partition_t partitionNumber); - -/*! - * @brief Configures the boot activity of the card. - * - * @param card Card descriptor. - * @param config Boot configuration structure. - * @retval kStatus_SDMMC_NotSupportYet Not support now. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure EXT_CSD failed. - * @retval kStatus_SDMMC_ConfigureBootFailed Configure boot failed. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_SetBootConfig(mmc_card_t *card, const mmc_boot_config_t *config); - -/*! - * @brief MMC card start boot. - * - * @param card Card descriptor. - * @param mmcConfig mmc Boot configuration structure. - * @param buffer address to recieve data. - * @param hostConfig host boot configurations. - * @retval kStatus_Fail fail. - * @retval kStatus_SDMMC_TransferFailed transfer fail. - * @retval kStatus_SDMMC_GoIdleFailed reset card fail. - * @retval kStatus_Success Operate successfully. - */ -status_t MMC_StartBoot(mmc_card_t *card, - const mmc_boot_config_t *mmcConfig, - uint8_t *buffer, - SDMMCHOST_BOOT_CONFIG *hostConfig); - -/*! - * @brief MMC card set boot configuration write protect. - * - * @param card Card descriptor. - * @param wp write protect value. - */ -status_t MMC_SetBootConfigWP(mmc_card_t *card, uint8_t wp); - -/*! - * @brief MMC card continous read boot data. - * - * @param card Card descriptor. - * @param buffer buffer address. - * @param hostConfig host boot configurations. - */ -status_t MMC_ReadBootData(mmc_card_t *card, uint8_t *buffer, SDMMCHOST_BOOT_CONFIG *hostConfig); - -/*! - * @brief MMC card stop boot mode. - * - * @param card Card descriptor. - * @param bootMode boot mode. - */ -status_t MMC_StopBoot(mmc_card_t *card, uint32_t bootMode); - -/*! - * @brief MMC card set boot partition write protect. - * - * @param card Card descriptor. - * @param bootPartitionWP boot partition write protect value. - */ -status_t MMC_SetBootPartitionWP(mmc_card_t *card, mmc_boot_partition_wp_t bootPartitionWP); - -/* @} */ -#if defined(__cplusplus) -} -#endif -/*! @} */ -#endif /* _FSL_MMC_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sd.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sd.h deleted file mode 100644 index 16077d7691..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sd.h +++ /dev/null @@ -1,315 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SD_H_ -#define _FSL_SD_H_ - -#include "fsl_sdmmc_common.h" -/*! - * @addtogroup SDCARD - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief SD card flags */ -enum _sd_card_flag -{ - kSD_SupportHighCapacityFlag = (1U << 1U), /*!< Support high capacity */ - kSD_Support4BitWidthFlag = (1U << 2U), /*!< Support 4-bit data width */ - kSD_SupportSdhcFlag = (1U << 3U), /*!< Card is SDHC */ - kSD_SupportSdxcFlag = (1U << 4U), /*!< Card is SDXC */ - kSD_SupportVoltage180v = (1U << 5U), /*!< card support 1.8v voltage*/ - kSD_SupportSetBlockCountCmd = (1U << 6U), /*!< card support cmd23 flag*/ - kSD_SupportSpeedClassControlCmd = (1U << 7U), /*!< card support speed class control flag */ -}; - -/*! - * @brief SD card state - * - * Define the card structure including the necessary fields to identify and describe the card. - */ -typedef struct _sd_card -{ - SDMMCHOST_CONFIG host; /*!< Host information */ - - sdcard_usr_param_t usrParam; /*!< user parameter */ - bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ - bool noInteralAlign; /*!< use this flag to disable sdmmc align. If disable, sdmmc will not make sure the - data buffer address is word align, otherwise all the transfer are align to low level driver */ - uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */ - uint32_t relativeAddress; /*!< Relative address of the card */ - uint32_t version; /*!< Card version */ - uint32_t flags; /*!< Flags in _sd_card_flag */ - uint32_t rawCid[4U]; /*!< Raw CID content */ - uint32_t rawCsd[4U]; /*!< Raw CSD content */ - uint32_t rawScr[2U]; /*!< Raw CSD content */ - uint32_t ocr; /*!< Raw OCR content */ - sd_cid_t cid; /*!< CID */ - sd_csd_t csd; /*!< CSD */ - sd_scr_t scr; /*!< SCR */ - sd_status_t stat; /*!< sd 512 bit status */ - uint32_t blockCount; /*!< Card total block number */ - uint32_t blockSize; /*!< Card block size */ - sd_timing_mode_t currentTiming; /*!< current timing mode */ - sd_driver_strength_t driverStrength; /*!< driver strength */ - sd_max_current_t maxCurrent; /*!< card current limit */ - sdmmc_operation_voltage_t operationVoltage; /*!< card operation voltage */ -} sd_card_t; - -/************************************************************************************************* - * API - ************************************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name SDCARD Function - * @{ - */ - -/*! - * @brief Initializes the card on a specific host controller. - * @deprecated Do not use this function. It has been superceded by @ref SD_HostInit,SD_CardInit. - - * This function initializes the card on a specific host controller, it is consist of - * host init, card detect, card init function, however user can ignore this high level function, - * instead of use the low level function, such as SD_CardInit, SD_HostInit, SD_CardDetect. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_HostNotReady host is not ready. - * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. - * @retval kStatus_SDMMC_NotSupportYet Card not support. - * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. - * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. - * @retval kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed. - * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. - * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. - * @retval kStatus_SDMMC_SendScrFailed Send SCR failed. - * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. - * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. - * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SD_Init(sd_card_t *card); - -/*! - * @brief Deinitializes the card. - * @deprecated Do not use this function. It has been superceded by @ref SD_HostDeinit,SD_CardDeinit. - * This function deinitializes the specific card and host. - * - * @param card Card descriptor. - */ -void SD_Deinit(sd_card_t *card); - -/*! - * @brief Initializes the card. - * - * This function initializes the card only, make sure the host is ready when call this function, - * otherwise it will return kStatus_SDMMC_HostNotReady. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_HostNotReady host is not ready. - * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. - * @retval kStatus_SDMMC_NotSupportYet Card not support. - * @retval kStatus_SDMMC_SendOperationConditionFailed Send operation condition failed. - * @retval kStatus_SDMMC_AllSendCidFailed Send CID failed. - * @retval kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed. - * @retval kStatus_SDMMC_SendCsdFailed Send CSD failed. - * @retval kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. - * @retval kStatus_SDMMC_SendScrFailed Send SCR failed. - * @retval kStatus_SDMMC_SetBusWidthFailed Set bus width failed. - * @retval kStatus_SDMMC_SwitchHighSpeedFailed Switch high speed failed. - * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SD_CardInit(sd_card_t *card); - -/*! - * @brief Deinitializes the card. - * - * This function deinitializes the specific card. - * - * @param card Card descriptor. - */ -void SD_CardDeinit(sd_card_t *card); - -/*! - * @brief initialize the host. - * - * This function deinitializes the specific host. - * - * @param card Card descriptor. - */ -status_t SD_HostInit(sd_card_t *card); - -/*! - * @brief Deinitializes the host. - * - * This function deinitializes the host. - * - * @param card Card descriptor. - */ -void SD_HostDeinit(sd_card_t *card); - -/*! - * @brief reset the host. - * - * This function reset the specific host. - * - * @param host host descriptor. - */ -void SD_HostReset(SDMMCHOST_CONFIG *host); - -/*! - * @brief power on card. - * - * The power on operation depend on host or the user define power on function. - * @param base host base address. - * @param pwr user define power control configuration - */ -void SD_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); - -/*! - * @brief power off card. - * - * The power off operation depend on host or the user define power on function. - * @param base host base address. - * @param pwr user define power control configuration - */ -void SD_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); - -/*! - * @brief sd wait card detect function. - * - * Detect card through GPIO, CD, DATA3. - * - * @param card card descriptor. - * @param card detect configuration - * @param waitCardStatus wait card detect status - */ -status_t SD_WaitCardDetectStatus(SDMMCHOST_TYPE *hostBase, const sdmmchost_detect_card_t *cd, bool waitCardStatus); - -/*! - * @brief sd card present check function. - * - * @param card card descriptor. - */ -bool SD_IsCardPresent(sd_card_t *card); - -/*! - * @brief Checks whether the card is write-protected. - * - * This function checks if the card is write-protected via the CSD register. - * - * @param card The specific card. - * @retval true Card is read only. - * @retval false Card isn't read only. - */ -bool SD_CheckReadOnly(sd_card_t *card); - -/*! - * @brief Send SELECT_CARD command to set the card to be transfer state or not. - * - * @param card Card descriptor. - * @param isSelected True to set the card into transfer state, false to disselect. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SD_SelectCard(sd_card_t *card, bool isSelected); - -/*! - * @brief Send ACMD13 to get the card current status. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_SendApplicationCommandFailed send application command failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SD_ReadStatus(sd_card_t *card); - -/*! - * @brief Reads blocks from the specific card. - * - * This function reads blocks from the specific card with default block size defined by the - * SDHC_CARD_DEFAULT_BLOCK_SIZE. - * - * @param card Card descriptor. - * @param buffer The buffer to save the data read from card. - * @param startBlock The start block index. - * @param blockCount The number of blocks to read. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_CardNotSupport Card not support. - * @retval kStatus_SDMMC_NotSupportYet Not support now. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief Writes blocks of data to the specific card. - * - * This function writes blocks to the specific card with default block size 512 bytes. - * - * @param card Card descriptor. - * @param buffer The buffer holding the data to be written to the card. - * @param startBlock The start block index. - * @param blockCount The number of blocks to write. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_NotSupportYet Not support now. - * @retval kStatus_SDMMC_CardNotSupport Card not support. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief Erases blocks of the specific card. - * - * This function erases blocks of the specific card with default block size 512 bytes. - * - * @param card Card descriptor. - * @param startBlock The start block index. - * @param blockCount The number of blocks to erase. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. - * @retval kStatus_Success Operate successfully. - */ -status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief select card driver strength - * select card driver strength - * @param card Card descriptor. - * @param driverStrength Driver strength - */ -status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength); - -/*! - * @brief select max current - * select max operation current - * @param card Card descriptor. - * @param maxCurrent Max current - */ -status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent); - -/* @} */ - -#if defined(__cplusplus) -} -#endif -/*! @} */ -#endif /* _FSL_SD_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_host.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_host.h deleted file mode 100644 index 0c9075deff..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdmmc_host.h +++ /dev/null @@ -1,780 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SDMMC_HOST_H -#define _FSL_SDMMC_HOST_H - -#include "fsl_common.h" -#include "board.h" -#if defined(FSL_FEATURE_SOC_SDHC_COUNT) && FSL_FEATURE_SOC_SDHC_COUNT > 0U -#include "fsl_sdhc.h" -#elif defined(FSL_FEATURE_SOC_SDIF_COUNT) && FSL_FEATURE_SOC_SDIF_COUNT > 0U -#include "fsl_sdif.h" -#elif defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT > 0U -#include "fsl_usdhc.h" -#endif - -/*! - * @addtogroup SDMMCHOST - * @{ - */ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/* Common definition for support and not support macro */ -#define SDMMCHOST_NOT_SUPPORT 0U /*!< use this define to indicate the host not support feature*/ -#define SDMMCHOST_SUPPORT 1U /*!< use this define to indicate the host support feature*/ - -/* Common definition for board support SDR104/HS200/HS400 frequency */ -/* SDR104 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_SDR104_FREQ -#define SDMMCHOST_SUPPORT_SDR104_FREQ BOARD_SD_HOST_SUPPORT_SDR104_FREQ -#else -#define SDMMCHOST_SUPPORT_SDR104_FREQ SD_CLOCK_208MHZ -#endif -/* HS200 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_HS200_FREQ -#define SDMMCHOST_SUPPORT_HS200_FREQ BOARD_SD_HOST_SUPPORT_HS200_FREQ -#else -#define SDMMCHOST_SUPPORT_HS200_FREQ MMC_CLOCK_HS200 -#endif -/* HS400 mode freq */ -#if defined BOARD_SD_HOST_SUPPORT_HS400_FREQ -#define SDMMCHOST_SUPPORT_HS400_FREQ BOARD_SD_HOST_SUPPORT_HS400_FREQ -#else -#define SDMMCHOST_SUPPORT_HS400_FREQ MMC_CLOCK_HS400 -#endif - -/* Common definition for SDMMCHOST transfer complete timeout */ -#define SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT (500U) -/* Common definition for card detect timeout */ -#define SDMMCHOST_CARD_DETECT_TIMEOUT (~0U) - -/* Common definition for IRQ */ -#if defined(__CORTEX_M) -#define SDMMCHOST_SET_IRQ_PRIORITY(id, priority) (NVIC_SetPriority(id, priority)) -#else -#define SDMMCHOST_SET_IRQ_PRIORITY(id, priority) (GIC_SetPriority(id, priority)) -#endif - -#define SDMMCHOST_ENABLE_IRQ(id) (EnableIRQ(id)) - -/*********************************************************SDHC**********************************************************/ -#if (defined(FSL_FEATURE_SOC_SDHC_COUNT) && (FSL_FEATURE_SOC_SDHC_COUNT > 0U)) - -/*define host baseaddr ,clk freq, IRQ number*/ -#define MMC_HOST_BASEADDR BOARD_SDHC_BASEADDR -#define MMC_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ -#define MMC_HOST_IRQ BOARD_SDHC_IRQ -#define SD_HOST_BASEADDR BOARD_SDHC_BASEADDR -#define SD_HOST_CLK_FREQ BOARD_SDHC_CLK_FREQ -#define SD_HOST_IRQ BOARD_SDHC_IRQ - -/* define for card bus speed/strength cnofig */ -#define CARD_BUS_FREQ_50MHZ (0U) -#define CARD_BUS_FREQ_100MHZ0 (0U) -#define CARD_BUS_FREQ_100MHZ1 (0U) -#define CARD_BUS_FREQ_200MHZ (0U) - -#define CARD_BUS_STRENGTH_0 (0U) -#define CARD_BUS_STRENGTH_1 (0U) -#define CARD_BUS_STRENGTH_2 (0U) -#define CARD_BUS_STRENGTH_3 (0U) -#define CARD_BUS_STRENGTH_4 (0U) -#define CARD_BUS_STRENGTH_5 (0U) -#define CARD_BUS_STRENGTH_6 (0U) -#define CARD_BUS_STRENGTH_7 (0U) - -#define SDMMCHOST_TYPE SDHC_Type -#define SDMMCHOST_CONFIG sdhc_host_t -#define SDMMCHOST_TRANSFER sdhc_transfer_t -#define SDMMCHOST_COMMAND sdhc_command_t -#define SDMMCHOST_DATA sdhc_data_t -#define SDMMCHOST_BUS_WIDTH_TYPE sdhc_data_bus_width_t -#define SDMMCHOST_CAPABILITY sdhc_capability_t -#define SDMMCHOST_BOOT_CONFIG sdhc_boot_config_t - -#define CARD_DATA0_STATUS_MASK (kSDHC_Data0LineLevelFlag) -#define CARD_DATA0_NOT_BUSY (kSDHC_Data0LineLevelFlag) -#define CARD_DATA1_STATUS_MASK (kSDHC_Data1LineLevelFlag) -#define CARD_DATA2_STATUS_MASK (kSDHC_Data2LineLevelFlag) -#define CARD_DATA3_STATUS_MASK (kSDHC_Data3LineLevelFlag) - -#define kSDMMCHOST_DATABUSWIDTH1BIT kSDHC_DataBusWidth1Bit /*!< 1-bit mode */ -#define kSDMMCHOST_DATABUSWIDTH4BIT kSDHC_DataBusWidth4Bit /*!< 4-bit mode */ -#define kSDMMCHOST_DATABUSWIDTH8BIT kSDHC_DataBusWidth8Bit /*!< 8-bit mode */ - -#define SDMMCHOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */ -#define SDMMCHOST_TUINIG_STEP (1U) /*!< standard tuning step */ -#define SDMMCHOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */ -#define SDMMCHOST_TUNING_DELAY_MAX (0x7FU) -#define SDMMCHOST_RETUNING_REQUEST (1U) -#define SDMMCHOST_TUNING_ERROR (2U) - -/* function pointer define */ -#define SDMMCHOST_TRANSFER_FUNCTION sdhc_transfer_function_t -#define GET_SDMMCHOST_CAPABILITY(base, capability) (SDHC_GetCapability(base, capability)) -#define GET_SDMMCHOST_STATUS(base) (SDHC_GetPresentStatusFlags(base)) -#define SDMMCHOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) (SDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ)) -#define SDMMCHOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDHC_SetDataBusWidth(base, busWidth)) -#define SDMMCHOST_SEND_CARD_ACTIVE(base, timeout) (SDHC_SetCardActive(base, timeout)) -#define SDMMCHOST_SWITCH_VOLTAGE180V(base, enable18v) -#define SDMMCHOST_SWITCH_VOLTAGE120V(base, enable12v) -#define SDMMCHOST_CONFIG_IO_STRENGTH(speed, strength) -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) -#define SDMMCHOST_CONFIG_SD_IO(speed, strength) -#define SDMMCHOST_CONFIG_MMC_IO(speed, strength) -#define SDMMCHOST_ENABLE_DDR_MODE(base, flag, nibblePos) -#define SDMMCHOST_FORCE_SDCLOCK_ON(base, enable) -#define SDMMCHOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) -#define SDMMCHOST_ADJUST_MANUAL_TUNING_DELAY(base, delay) -#define SDMMCHOST_AUTO_MANUAL_TUNING_ENABLE(base, flag) -#define SDMMCHOST_ENABLE_CARD_CLOCK(base, enable) (SDHC_EnableSdClock(base, enable)) -#define SDMMCHOST_RESET_TUNING(base, timeout) -#define SDMMCHOST_CHECK_TUNING_ERROR(base) (0U) -#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay) -#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base) -#define SDMMCHOST_TRANSFER_DATA_ERROR kStatus_SDHC_TransferDataFailed -#define SDMMCHOST_TRANSFER_CMD_ERROR kStatus_SDHC_SendCommandFailed -#define SDMMCHOST_ENABLE_HS400_MODE(base, flag) -#define SDMMCHOST_RESET_STROBE_DLL(base) -#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag) -#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval) -#define SDMMCHOST_GET_STROBE_DLL_STATUS(base) -/* sd card power */ -#define SDMMCHOST_INIT_SD_POWER() -#define SDMMCHOST_ENABLE_SD_POWER(enable) -#define SDMMCHOST_SWITCH_VCC_TO_180V() -#define SDMMCHOST_SWITCH_VCC_TO_330V() -/* mmc card power */ -#define SDMMCHOST_INIT_MMC_POWER() -#define SDMMCHOST_ENABLE_MMC_POWER(enable) -#define SDMMCHOST_ENABLE_TUNING_FLAG(data) -#define SDMMCHOST_ENABLE_BOOT_FLAG(data) -#define SDMMCHOST_ENABLE_BOOT_CONTINOUS_FLAG(data) -#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(config) (0U) -#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(config) (0U) -#define SDMMCHOST_GET_HOST_CONFIG_BOOT_MODE(config) (0U) -#define SDMMCHOST_EMPTY_CMD_FLAG(command) -#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_HANDLER BOARD_SDHC_CD_PORT_IRQ_HANDLER -#define SDMMCHOST_CARD_DETECT_IRQ BOARD_SDHC_CD_PORT_IRQ -/* sd card detect through host CD */ -#define SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base) (SDHC_EnableInterruptStatus(base, kSDHC_CardInsertionFlag)) -#define SDMMCHOST_CARD_DETECT_REMOVE_ENABLE(base) (SDHC_EnableInterruptStatus(base, kSDHC_CardRemovalFlag)) -#define SDMMCHOST_CARD_DETECT_INSERT_STATUS(base) (SDHC_GetInterruptStatusFlags(base) & kSDHC_CardInsertionFlag) -#define SDMMCHOST_CARD_DETECT_REMOVE_STATUS(base) (SDHC_GetInterruptStatusFlags(base, kSDHC_CardRemovalFlag)) -#define SDMMCHOST_CARD_DETECT_INSERT_INTERRUPT_ENABLE(base) (SDHC_EnableInterruptSignal(base, kSDHC_CardInsertionFlag)) -#define SDMMCHOST_CARD_DETECT_INSERT_INTERRUPT_DISABLE(base) \ - (SDHC_DisableInterruptSignal(base, kSDHC_CardInsertionFlag)) -#define SDMMCHOST_CARD_DETECT_REMOVE_INTERRUPT_ENABLE(base) (SDHC_EnableInterruptSignal(base, kSDHC_CardRemovalFlag)) -#define SDMMCHOST_CARD_DETECT_DATA3_ENABLE(base, flag) (SDHC_CardDetectByData3(base, flag)) -#define SDMMCHOST_ENABLE_MMC_BOOT(base, flag) -#define SDMMCHOST_SETMMCBOOTCONFIG(base, config) (SDHC_SetMmcBootConfig(base, config)) -/* define card detect pin voltage level when card inserted */ -#if defined BOARD_SDHC_CARD_INSERT_CD_LEVEL -#define SDMMCHOST_CARD_INSERT_CD_LEVEL BOARD_SDHC_CARD_INSERT_CD_LEVEL -#else -#define SDMMCHOST_CARD_INSERT_CD_LEVEL (0U) -#endif -#define SDMMCHOST_AUTO_TUNING_ENABLE(base, flag) -#define SDMMCHOST_ENABLE_SDIO_INT(base) \ - SDHC_EnableInterruptStatus(base, kSDHC_CardInterruptFlag); \ - SDHC_EnableInterruptSignal(base, kSDHC_CardInterruptFlag) -#define SDMMCHOST_DISABLE_SDIO_INT(base) \ - SDHC_DisableInterruptStatus(base, kSDHC_CardInterruptFlag); \ - SDHC_DisableInterruptSignal(base, kSDHC_CardInterruptFlag) - -/*! @brief SDHC host capability*/ -enum _host_capability -{ - kSDMMCHOST_SupportAdma = kSDHC_SupportAdmaFlag, - kSDMMCHOST_SupportHighSpeed = kSDHC_SupportHighSpeedFlag, - kSDMMCHOST_SupportDma = kSDHC_SupportDmaFlag, - kSDMMCHOST_SupportSuspendResume = kSDHC_SupportSuspendResumeFlag, - kSDMMCHOST_SupportV330 = kSDHC_SupportV330Flag, - kSDMMCHOST_SupportV300 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportV180 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportV120 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_Support4BitBusWidth = kSDHC_Support4BitFlag, - kSDMMCHOST_Support8BitBusWidth = kSDHC_Support8BitFlag, - kSDMMCHOST_SupportDDR50 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportSDR104 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportSDR50 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportHS200 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportHS400 = SDMMCHOST_NOT_SUPPORT, -}; - -/* Endian mode. */ -#define SDHC_ENDIAN_MODE kSDHC_EndianModeLittle - -/* DMA mode */ -#define SDHC_DMA_MODE kSDHC_DmaModeAdma2 -/* address align */ -#define SDMMCHOST_DMA_BUFFER_ADDR_ALIGN (SDHC_ADMA2_ADDRESS_ALIGN) - -/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ -#define SDHC_READ_WATERMARK_LEVEL (0x80U) -#define SDHC_WRITE_WATERMARK_LEVEL (0x80U) - -/* ADMA table length united as word. - * - * SD card driver can't support ADMA1 transfer mode currently. - * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time. - * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. - */ -#define SDHC_ADMA_TABLE_WORDS (8U) - -/*********************************************************SDIF**********************************************************/ -#elif (defined(FSL_FEATURE_SOC_SDIF_COUNT) && (FSL_FEATURE_SOC_SDIF_COUNT > 0U)) - -/*define host baseaddr ,clk freq, IRQ number*/ -#define MMC_HOST_BASEADDR BOARD_SDIF_BASEADDR -#define MMC_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ -#define MMC_HOST_IRQ BOARD_SDIF_IRQ -#define SD_HOST_BASEADDR BOARD_SDIF_BASEADDR -#define SD_HOST_CLK_FREQ BOARD_SDIF_CLK_FREQ -#define SD_HOST_IRQ BOARD_SDIF_IRQ - -/* define for card bus speed/strength cnofig */ -#define CARD_BUS_FREQ_50MHZ (0U) -#define CARD_BUS_FREQ_100MHZ0 (0U) -#define CARD_BUS_FREQ_100MHZ1 (0U) -#define CARD_BUS_FREQ_200MHZ (0U) - -#define CARD_BUS_STRENGTH_0 (0U) -#define CARD_BUS_STRENGTH_1 (0U) -#define CARD_BUS_STRENGTH_2 (0U) -#define CARD_BUS_STRENGTH_3 (0U) -#define CARD_BUS_STRENGTH_4 (0U) -#define CARD_BUS_STRENGTH_5 (0U) -#define CARD_BUS_STRENGTH_6 (0U) -#define CARD_BUS_STRENGTH_7 (0U) - -#define SDMMCHOST_TYPE SDIF_Type -#define SDMMCHOST_CONFIG sdif_host_t -#define SDMMCHOST_TRANSFER sdif_transfer_t -#define SDMMCHOST_COMMAND sdif_command_t -#define SDMMCHOST_DATA sdif_data_t -#define SDMMCHOST_BUS_WIDTH_TYPE sdif_bus_width_t -#define SDMMCHOST_CAPABILITY sdif_capability_t -#define SDMMCHOST_BOOT_CONFIG void - -#define CARD_DATA0_STATUS_MASK SDIF_STATUS_DATA_BUSY_MASK -#define CARD_DATA0_NOT_BUSY 0U - -#define CARD_DATA1_STATUS_MASK (0U) -#define CARD_DATA2_STATUS_MASK (0U) -#define CARD_DATA3_STATUS_MASK (0U) - -#define kSDMMCHOST_DATABUSWIDTH1BIT kSDIF_Bus1BitWidth /*!< 1-bit mode */ -#define kSDMMCHOST_DATABUSWIDTH4BIT kSDIF_Bus4BitWidth /*!< 4-bit mode */ -#define kSDMMCHOST_DATABUSWIDTH8BIT kSDIF_Bus8BitWidth /*!< 8-bit mode */ - -#define SDMMCHOST_STANDARD_TUNING_START (0U) /*!< standard tuning start point */ -#define SDMMCHOST_TUINIG_STEP (1U) /*!< standard tuning step */ -#define SDMMCHOST_RETUNING_TIMER_COUNT (4U) /*!< Re-tuning timer */ -#define SDMMCHOST_TUNING_DELAY_MAX (0x7FU) -#define SDMMCHOST_RETUNING_REQUEST (1U) -#define SDMMCHOST_TUNING_ERROR (2U) -/* function pointer define */ -#define SDMMCHOST_TRANSFER_FUNCTION sdif_transfer_function_t -#define GET_SDMMCHOST_CAPABILITY(base, capability) (SDIF_GetCapability(base, capability)) -#define GET_SDMMCHOST_STATUS(base) (SDIF_GetControllerStatus(base)) -#define SDMMCHOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) \ - (SDIF_SetCardClock(base, sourceClock_HZ, busClock_HZ)) -#define SDMMCHOST_SET_CARD_BUS_WIDTH(base, busWidth) (SDIF_SetCardBusWidth(base, busWidth)) -#define SDMMCHOST_SEND_CARD_ACTIVE(base, timeout) (SDIF_SendCardActive(base, timeout)) -#define SDMMCHOST_SWITCH_VOLTAGE180V(base, enable18v) -#define SDMMCHOST_SWITCH_VOLTAGE120V(base, enable12v) -#define SDMMCHOST_CONFIG_IO_STRENGTH(speed, strength) -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) -#define SDMMCHOST_CONFIG_SD_IO(speed, strength) -#define SDMMCHOST_CONFIG_MMC_IO(speed, strength) -#define SDMMCHOST_ENABLE_DDR_MODE(base, flag, nibblePos) -#define SDMMCHOST_FORCE_SDCLOCK_ON(base, enable) -#define SDMMCHOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) -#define SDMMCHOST_ADJUST_MANUAL_TUNING_DELAY(base, delay) -#define SDMMCHOST_AUTO_MANUAL_TUNING_ENABLE(base, flag) -#define SDMMCHOST_ENABLE_CARD_CLOCK(base, enable) (SDIF_EnableCardClock(base, enable)) -#define SDMMCHOST_RESET_TUNING(base, timeout) -#define SDMMCHOST_CHECK_TUNING_ERROR(base) (0U) -#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay) -#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base) - -#define SDMMCHOST_ENABLE_HS400_MODE(base, flag) -#define SDMMCHOST_RESET_STROBE_DLL(base) -#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag) -#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval) -#define SDMMCHOST_GET_STROBE_DLL_STATUS(base) -/* sd card power */ -#define SDMMCHOST_INIT_SD_POWER() -#define SDMMCHOST_ENABLE_SD_POWER(enable) -#define SDMMCHOST_SWITCH_VCC_TO_180V() -#define SDMMCHOST_SWITCH_VCC_TO_330V() -/* mmc card power */ -#define SDMMCHOST_INIT_MMC_POWER() -#define SDMMCHOST_ENABLE_MMC_POWER(enable) -#define SDMMCHOST_ENABLE_TUNING_FLAG(data) -#define SDMMCHOST_ENABLE_MMC_BOOT(base, flag) -#define SDMMCHOST_SETMMCBOOTCONFIG(base, config) -#define SDMMCHOST_ENABLE_BOOT_FLAG(data) -#define SDMMCHOST_ENABLE_BOOT_CONTINOUS_FLAG(data) -#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(config) (0U) -#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(config) (0U) -#define SDMMCHOST_GET_HOST_CONFIG_BOOT_MODE(config) (0U) -#define SDMMCHOST_EMPTY_CMD_FLAG(command) -#define SDMMCHOST_CARD_DETECT_STATUS() BOARD_SDIF_CD_STATUS() -#define SDMMCHOST_CARD_DETECT_INIT() BOARD_SDIF_CD_GPIO_INIT() -#define SDMMCHOST_CARD_DETECT_INTERRUPT_STATUS() BOARD_SDIF_CD_INTERRUPT_STATUS() -#define SDMMCHOST_CARD_DETECT_INTERRUPT_CLEAR(flag) BOARD_SDIF_CD_CLEAR_INTERRUPT(flag) -#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_HANDLER BOARD_SDIF_CD_PORT_IRQ_HANDLER -#define SDMMCHOST_CARD_DETECT_IRQ BOARD_SDIF_CD_PORT_IRQ -#define SDMMCHOST_TRANSFER_DATA_ERROR kStatus_SDIF_DataTransferFail -#define SDMMCHOST_TRANSFER_CMD_ERROR kStatus_SDIF_SendCmdFail -/* define card detect pin voltage level when card inserted */ -#if defined BOARD_SDIF_CARD_INSERT_CD_LEVEL -#define SDMMCHOST_CARD_INSERT_CD_LEVEL BOARD_SDIF_CARD_INSERT_CD_LEVEL -#else -#define SDMMCHOST_CARD_INSERT_CD_LEVEL (0U) -#endif -#define SDMMCHOST_AUTO_TUNING_ENABLE(base, flag) -/* sd card detect through host CD */ -#define SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base) (SDIF_EnableInterrupt(base, kSDIF_CardDetect)) -#define SDMMCHOST_CARD_DETECT_INSERT_STATUS(base, data3) (SDIF_DetectCardInsert(base, data3)) -#define SDMMCHOST_ENABLE_SDIO_INT(base) -#define SDMMCHOST_DISABLE_SDIO_INT(base) -/*! @brief SDIF host capability*/ -enum _host_capability -{ - kSDMMCHOST_SupportHighSpeed = kSDIF_SupportHighSpeedFlag, - kSDMMCHOST_SupportDma = kSDIF_SupportDmaFlag, - kSDMMCHOST_SupportSuspendResume = kSDIF_SupportSuspendResumeFlag, - kSDMMCHOST_SupportV330 = kSDIF_SupportV330Flag, - kSDMMCHOST_SupportV300 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportV180 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportV120 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_Support4BitBusWidth = kSDIF_Support4BitFlag, - kSDMMCHOST_Support8BitBusWidth = - SDMMCHOST_NOT_SUPPORT, /* mask the 8 bit here,user can change depend on your board */ - kSDMMCHOST_SupportDDR50 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportSDR104 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportSDR50 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportHS200 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_SupportHS400 = SDMMCHOST_NOT_SUPPORT, - -}; - -/*! @brief DMA table length united as word - * One dma table item occupy four words which can transfer maximum 2*8188 bytes in dual DMA mode - * and 8188 bytes in chain mode - * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. - * user need check the DMA descriptor table lenght if bigger enough. - */ -#define SDIF_DMA_TABLE_WORDS (0x40U) -/* address align */ -#define SDMMCHOST_DMA_BUFFER_ADDR_ALIGN (4U) - -/*********************************************************USDHC**********************************************************/ -#elif (defined(FSL_FEATURE_SOC_USDHC_COUNT) && (FSL_FEATURE_SOC_USDHC_COUNT > 0U)) - -/*define host baseaddr ,clk freq, IRQ number*/ -#define MMC_HOST_BASEADDR BOARD_MMC_HOST_BASEADDR -#define MMC_HOST_CLK_FREQ BOARD_MMC_HOST_CLK_FREQ -#define MMC_HOST_IRQ BOARD_MMC_HOST_IRQ -#define SD_HOST_BASEADDR BOARD_SD_HOST_BASEADDR -#define SD_HOST_CLK_FREQ BOARD_SD_HOST_CLK_FREQ -#define SD_HOST_IRQ BOARD_SD_HOST_IRQ - -#define SDMMCHOST_TYPE USDHC_Type -#define SDMMCHOST_CONFIG usdhc_host_t -#define SDMMCHOST_TRANSFER usdhc_transfer_t -#define SDMMCHOST_COMMAND usdhc_command_t -#define SDMMCHOST_DATA usdhc_data_t -#define SDMMCHOST_BOOT_CONFIG usdhc_boot_config_t -#define CARD_DATA0_STATUS_MASK (kUSDHC_Data0LineLevelFlag) -#define CARD_DATA1_STATUS_MASK (kUSDHC_Data1LineLevelFlag) -#define CARD_DATA2_STATUS_MASK (kUSDHC_Data2LineLevelFlag) -#define CARD_DATA3_STATUS_MASK (kUSDHC_Data3LineLevelFlag) -#define CARD_DATA0_NOT_BUSY (kUSDHC_Data0LineLevelFlag) - -#define SDMMCHOST_BUS_WIDTH_TYPE usdhc_data_bus_width_t -#define SDMMCHOST_CAPABILITY usdhc_capability_t - -#define kSDMMCHOST_DATABUSWIDTH1BIT kUSDHC_DataBusWidth1Bit /*!< 1-bit mode */ -#define kSDMMCHOST_DATABUSWIDTH4BIT kUSDHC_DataBusWidth4Bit /*!< 4-bit mode */ -#define kSDMMCHOST_DATABUSWIDTH8BIT kUSDHC_DataBusWidth8Bit /*!< 8-bit mode */ - -#define SDMMCHOST_STANDARD_TUNING_START (10U) /*!< standard tuning start point */ -#define SDMMCHOST_TUINIG_STEP (2U) /*!< standard tuning step */ -#define SDMMCHOST_RETUNING_TIMER_COUNT (0U) /*!< Re-tuning timer */ -#define SDMMCHOST_TUNING_DELAY_MAX (0x7FU) -#define SDMMCHOST_RETUNING_REQUEST kStatus_USDHC_ReTuningRequest -#define SDMMCHOST_TUNING_ERROR kStatus_USDHC_TuningError -#define SDMMCHOST_TRANSFER_DATA_ERROR kStatus_USDHC_TransferDataFailed -#define SDMMCHOST_TRANSFER_CMD_ERROR kStatus_USDHC_SendCommandFailed -/* define for card bus speed/strength cnofig */ -#define CARD_BUS_FREQ_50MHZ (0U) -#define CARD_BUS_FREQ_100MHZ0 (1U) -#define CARD_BUS_FREQ_100MHZ1 (2U) -#define CARD_BUS_FREQ_200MHZ (3U) - -#define CARD_BUS_STRENGTH_0 (0U) -#define CARD_BUS_STRENGTH_1 (1U) -#define CARD_BUS_STRENGTH_2 (2U) -#define CARD_BUS_STRENGTH_3 (3U) -#define CARD_BUS_STRENGTH_4 (4U) -#define CARD_BUS_STRENGTH_5 (5U) -#define CARD_BUS_STRENGTH_6 (6U) -#define CARD_BUS_STRENGTH_7 (7U) - -#define SDMMCHOST_STROBE_DLL_DELAY_TARGET (7U) -#define SDMMCHOST_STROBE_DLL_DELAY_UPDATE_INTERVAL (4U) - -/* function pointer define */ -#define SDMMCHOST_TRANSFER_FUNCTION usdhc_transfer_function_t -#define GET_SDMMCHOST_CAPABILITY(base, capability) (USDHC_GetCapability(base, capability)) -#define GET_SDMMCHOST_STATUS(base) (USDHC_GetPresentStatusFlags(base)) -#define SDMMCHOST_SET_CARD_CLOCK(base, sourceClock_HZ, busClock_HZ) \ - (USDHC_SetSdClock(base, sourceClock_HZ, busClock_HZ)) -#define SDMMCHOST_ENABLE_CARD_CLOCK(base, enable) -#define SDMMCHOST_FORCE_SDCLOCK_ON(base, enable) (USDHC_ForceClockOn(base, enable)) -#define SDMMCHOST_SET_CARD_BUS_WIDTH(base, busWidth) (USDHC_SetDataBusWidth(base, busWidth)) -#define SDMMCHOST_SEND_CARD_ACTIVE(base, timeout) (USDHC_SetCardActive(base, timeout)) -#define SDMMCHOST_SWITCH_VOLTAGE180V(base, enable18v) (UDSHC_SelectVoltage(base, enable18v)) -#define SDMMCHOST_SWITCH_VOLTAGE120V(base, enable12v) -#define SDMMCHOST_CONFIG_SD_IO(speed, strength) BOARD_SD_Pin_Config(speed, strength) -#define SDMMCHOST_CONFIG_MMC_IO(speed, strength) BOARD_MMC_Pin_Config(speed, strength) -#define SDMMCHOST_SWITCH_VCC_TO_180V() -#define SDMMCHOST_SWITCH_VCC_TO_330V() - -#if defined(FSL_FEATURE_USDHC_HAS_SDR50_MODE) && (!FSL_FEATURE_USDHC_HAS_SDR50_MODE) -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (0U) -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (1U) -#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base) -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) -#define SDMMCHOST_CHECK_TUNING_ERROR(base) (0U) -#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay) -#else -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, flag) \ - (USDHC_EnableStandardTuning(base, SDMMCHOST_STANDARD_TUNING_START, SDMMCHOST_TUINIG_STEP, flag)) -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) (USDHC_GetExecuteStdTuningStatus(base)) -#define SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) (USDHC_CheckStdTuningResult(base)) -#define SDMMCHOST_AUTO_STANDARD_RETUNING_TIMER(base) (USDHC_SetRetuningTimer(base, SDMMCHOST_RETUNING_TIMER_COUNT)) -#define SDMMCHOST_EXECUTE_MANUAL_TUNING_ENABLE(base, flag) (USDHC_EnableManualTuning(base, flag)) -#define SDMMCHOST_ADJUST_TUNING_DELAY(base, delay) (USDHC_AdjustDelayForManualTuning(base, delay)) -#define SDMMCHOST_AUTO_TUNING_ENABLE(base, flag) (USDHC_EnableAutoTuning(base, flag)) -#define SDMMCHOST_CHECK_TUNING_ERROR(base) (USDHC_CheckTuningError(base)) -#endif - -#define SDMMCHOST_AUTO_TUNING_CONFIG(base) (USDHC_EnableAutoTuningForCmdAndData(base)) -#define SDMMCHOST_RESET_TUNING(base, timeout) \ - { \ - (USDHC_Reset(base, kUSDHC_ResetTuning | kUSDHC_ResetData | kUSDHC_ResetCommand, timeout)); \ - } - -#define SDMMCHOST_ENABLE_DDR_MODE(base, flag, nibblePos) (USDHC_EnableDDRMode(base, flag, nibblePos)) - -#if FSL_FEATURE_USDHC_HAS_HS400_MODE -#define SDMMCHOST_ENABLE_HS400_MODE(base, flag) (USDHC_EnableHS400Mode(base, flag)) -#define SDMMCHOST_RESET_STROBE_DLL(base) (USDHC_ResetStrobeDLL(base)) -#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag) (USDHC_EnableStrobeDLL(base, flag)) -#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval) (USDHC_ConfigStrobeDLL(base, delay, updateInterval)) -#define SDMMCHOST_GET_STROBE_DLL_STATUS (base)(USDHC_GetStrobeDLLStatus(base)) -#else -#define SDMMCHOST_ENABLE_HS400_MODE(base, flag) -#define SDMMCHOST_RESET_STROBE_DLL(base) -#define SDMMCHOST_ENABLE_STROBE_DLL(base, flag) -#define SDMMCHOST_CONFIG_STROBE_DLL(base, delay, updateInterval) -#define SDMMCHOST_GET_STROBE_DLL_STATUS(base) -#endif - -#define SDMMCHOST_ENABLE_MMC_BOOT(base, flag) (USDHC_EnableMmcBoot(base, flag)) -#define SDMMCHOST_SETMMCBOOTCONFIG(base, config) (USDHC_SetMmcBootConfig(base, config)) -/* sd card power */ -#define SDMMCHOST_INIT_SD_POWER() BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() -#define SDMMCHOST_ENABLE_SD_POWER(enable) BOARD_USDHC_SDCARD_POWER_CONTROL(enable) -/* mmc card power */ -#define SDMMCHOST_INIT_MMC_POWER() BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() -#define SDMMCHOST_ENABLE_MMC_POWER(enable) BOARD_USDHC_MMCCARD_POWER_CONTROL(enable) -/* sd card detect through gpio */ -#define SDMMCHOST_CARD_DETECT_GPIO_STATUS() BOARD_USDHC_CD_STATUS() -#define SDMMCHOST_CARD_DETECT_GPIO_INIT() BOARD_USDHC_CD_GPIO_INIT() -#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_STATUS() BOARD_USDHC_CD_INTERRUPT_STATUS() -#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_STATUS_CLEAR(flag) BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) -#define SDMMCHOST_CARD_DETECT_GPIO_INTERRUPT_HANDLER BOARD_USDHC_CD_PORT_IRQ_HANDLER -#define SDMMCHOST_CARD_DETECT_GPIO_IRQ BOARD_USDHC_CD_PORT_IRQ -/* sd card detect through host CD */ -#define SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base) (USDHC_EnableInterruptStatus(base, kUSDHC_CardInsertionFlag)) -#define SDMMCHOST_CARD_DETECT_REMOVE_ENABLE(base) (USDHC_EnableInterruptStatus(base, kUSDHC_CardRemovalFlag)) -#define SDMMCHOST_CARD_DETECT_INSERT_STATUS(base) (USDHC_DetectCardInsert(base)) -#define SDMMCHOST_CARD_DETECT_REMOVE_STATUS(base) (USDHC_GetInterruptStatusFlags(base, kUSDHC_CardRemovalFlag)) -#define SDMMCHOST_CARD_DETECT_INSERT_INTERRUPT_ENABLE(base) \ - (USDHC_EnableInterruptSignal(base, kUSDHC_CardInsertionFlag)) -#define SDMMCHOST_CARD_DETECT_REMOVE_INTERRUPT_ENABLE(base) (USDHC_EnableInterruptSignal(base, kUSDHC_CardRemovalFlag)) -#define SDMMCHOST_CARD_DETECT_DATA3_ENABLE(base, flag) (USDHC_CardDetectByData3(base, flag)) - -/* define card detect pin voltage level when card inserted */ -#if defined BOARD_USDHC_CARD_INSERT_CD_LEVEL -#define SDMMCHOST_CARD_INSERT_CD_LEVEL BOARD_USDHC_CARD_INSERT_CD_LEVEL -#else -#define SDMMCHOST_CARD_INSERT_CD_LEVEL (0U) -#endif -#define SDMMCHOST_ENABLE_TUNING_FLAG(data) (data.dataType = kUSDHC_TransferDataTuning) -#define SDMMCHOST_ENABLE_BOOT_FLAG(data) (data.dataType = kUSDHC_TransferDataBoot) -#define SDMMCHOST_ENABLE_BOOT_CONTINOUS_FLAG(data) (data.dataType = kUSDHC_TransferDataBootcontinous) -#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(config) (config->blockSize) -#define SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(config) (config->blockCount) -#define SDMMCHOST_GET_HOST_CONFIG_BOOT_MODE(config) (config->bootMode) -#define SDMMCHOST_EMPTY_CMD_FLAG(command) (command.type = kCARD_CommandTypeEmpty) -#define SDMMCHOST_ENABLE_SDIO_INT(base) \ - USDHC_EnableInterruptStatus(base, kUSDHC_CardInterruptFlag); \ - USDHC_EnableInterruptSignal(base, kUSDHC_CardInterruptFlag) -#define SDMMCHOST_DISABLE_SDIO_INT(base) \ - USDHC_DisableInterruptStatus(base, kUSDHC_CardInterruptFlag); \ - USDHC_DisableInterruptSignal(base, kUSDHC_CardInterruptFlag) -/*! @brief USDHC host capability*/ -enum _host_capability -{ - kSDMMCHOST_SupportAdma = kUSDHC_SupportAdmaFlag, - kSDMMCHOST_SupportHighSpeed = kUSDHC_SupportHighSpeedFlag, - kSDMMCHOST_SupportDma = kUSDHC_SupportDmaFlag, - kSDMMCHOST_SupportSuspendResume = kUSDHC_SupportSuspendResumeFlag, - kSDMMCHOST_SupportV330 = kUSDHC_SupportV330Flag, /* this define should depend on your board config */ - kSDMMCHOST_SupportV300 = kUSDHC_SupportV300Flag, /* this define should depend on your board config */ -#if defined(BOARD_SD_SUPPORT_180V) && !BOARD_SD_SUPPORT_180V - kSDMMCHOST_SupportV180 = SDMMCHOST_NOT_SUPPORT, /* this define should depend on you board config */ -#else - kSDMMCHOST_SupportV180 = kUSDHC_SupportV180Flag, /* this define should depend on you board config */ -#endif - kSDMMCHOST_SupportV120 = SDMMCHOST_NOT_SUPPORT, - kSDMMCHOST_Support4BitBusWidth = kUSDHC_Support4BitFlag, -#if defined(BOARD_MMC_SUPPORT_8BIT_BUS) -#if BOARD_MMC_SUPPORT_8BIT_BUS - kSDMMCHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag, -#else - kSDMMCHOST_Support8BitBusWidth = SDMMCHOST_NOT_SUPPORT, -#endif -#else - kSDMMCHOST_Support8BitBusWidth = kUSDHC_Support8BitFlag, -#endif - kSDMMCHOST_SupportDDR50 = kUSDHC_SupportDDR50Flag, - kSDMMCHOST_SupportSDR104 = kUSDHC_SupportSDR104Flag, - kSDMMCHOST_SupportSDR50 = kUSDHC_SupportSDR50Flag, - kSDMMCHOST_SupportHS200 = kUSDHC_SupportSDR104Flag, -#if FSL_FEATURE_USDHC_HAS_HS400_MODE - kSDMMCHOST_SupportHS400 = SDMMCHOST_SUPPORT -#else - kSDMMCHOST_SupportHS400 = SDMMCHOST_NOT_SUPPORT, -#endif -}; - -/* Endian mode. */ -#define USDHC_ENDIAN_MODE kUSDHC_EndianModeLittle - -/* DMA mode */ -#define USDHC_DMA_MODE kUSDHC_DmaModeAdma2 -/* address align */ -#define SDMMCHOST_DMA_BUFFER_ADDR_ALIGN (USDHC_ADMA2_ADDRESS_ALIGN) - -/* Read/write watermark level. The bigger value indicates DMA has higher read/write performance. */ -#define USDHC_READ_WATERMARK_LEVEL (0x80U) -#define USDHC_WRITE_WATERMARK_LEVEL (0x80U) - -/* ADMA table length united as word. - * - * One ADMA2 table item occupy two words which can transfer maximum 0xFFFFU bytes one time. - * The more data to be transferred in one time, the bigger value of SDHC_ADMA_TABLE_WORDS need to be set. - */ -#define USDHC_ADMA_TABLE_WORDS (8U) /* define the ADMA descriptor table length */ -#define USDHC_ADMA2_ADDR_ALIGN (4U) /* define the ADMA2 descriptor table addr align size */ -#define USDHC_READ_BURST_LEN (8U) /*!< number of words USDHC read in a single burst */ -#define USDHC_WRITE_BURST_LEN (8U) /*!< number of words USDHC write in a single burst */ -#define USDHC_DATA_TIMEOUT (0xFU) /*!< data timeout counter value */ - -#endif /* (defined(FSL_FEATURE_SOC_SDHC_COUNT) && (FSL_FEATURE_SOC_SDHC_COUNT > 0U)) */ - -/*! @brief card detect callback definition */ -typedef void (*sdmmchost_cd_callback_t)(bool isInserted, void *userData); - -/*! @brief host Endian mode - * corresponding to driver define - */ -enum _sdmmchost_endian_mode -{ - kSDMMCHOST_EndianModeBig = 0U, /*!< Big endian mode */ - kSDMMCHOST_EndianModeHalfWordBig = 1U, /*!< Half word big endian mode */ - kSDMMCHOST_EndianModeLittle = 2U, /*!< Little endian mode */ -}; - -/*! @brief sd card detect type */ -typedef enum _sdmmchost_detect_card_type -{ - kSDMMCHOST_DetectCardByGpioCD, /*!< sd card detect by CD pin through GPIO */ - kSDMMCHOST_DetectCardByHostCD, /*!< sd card detect by CD pin through host */ - kSDMMCHOST_DetectCardByHostDATA3, /*!< sd card detect by DAT3 pin through host */ -} sdmmchost_detect_card_type_t; - -/*! @brief sd card detect */ -typedef struct _sdmmchost_detect_card -{ - sdmmchost_detect_card_type_t cdType; /*!< card detect type */ - uint32_t cdTimeOut_ms; /*!< card detect timeout which allow 0 - 0xFFFFFFF, value 0 will return immediately, value - 0xFFFFFFFF will block until card is insert */ - - sdmmchost_cd_callback_t cardInserted; /*!< card inserted callback which is meaningful for interrupt case */ - sdmmchost_cd_callback_t cardRemoved; /*!< card removed callback which is meaningful for interrupt case */ - - void *userData; /*!< user data */ -} sdmmchost_detect_card_t; - -/*! @brief card power control function pointer */ -typedef void (*sdmmchost_pwr_t)(void); - -/*! @brief card power control */ -typedef struct _sdmmchost_pwr_card -{ - sdmmchost_pwr_t powerOn; /*!< power on function pointer */ - uint32_t powerOnDelay_ms; /*!< power on delay */ - - sdmmchost_pwr_t powerOff; /*!< power off function pointer */ - uint32_t powerOffDelay_ms; /*!< power off delay */ -} sdmmchost_pwr_card_t; - -/*! @brief card interrupt function pointer */ -typedef void (*sdmmchost_card_int_callback_t)(void *userData); -/*! @brief card interrupt application callback */ -typedef struct _sdmmchost_card_int -{ - void *userData; /*!< user data */ - sdmmchost_card_int_callback_t cardInterrupt; /*!< card int call back */ -} sdmmchost_card_int_t; - -/*! @brief card switch voltage function pointer */ -typedef void (*sdmmchost_card_switch_voltage_t)(void); -/*! @brief card switch voltage function collection */ -typedef struct _sdmmchost_card_switch_voltage_func -{ - sdmmchost_card_switch_voltage_t cardSignalLine1V8; /*!< switch to 1.8v function pointer */ - sdmmchost_card_switch_voltage_t cardSignalLine3V3; /*! +#include "fsl_mmc.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ +/*! @brief The divide value used to avoid float point calculation when calculate max speed in normal mode. */ +#define DIVIDER_IN_TRANSFER_SPEED (10U) +/*! @brief MMC CMD1 retry times */ +#ifndef MMC_CMD1_RETRY_TIMES +#define MMC_CMD1_RETRY_TIMES (10000U) +#endif +#ifndef MMC_CMD13_RETRY_TIMES +#define MMC_CMD13_RETRY_TIMES (1000000U) +#endif +#ifndef MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT +#define MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT (10000U) +#endif +/*!@brief power reset delay */ +#define MMC_POWER_RESET_DELAY (500U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Send SELECT_CARD command to set the card enter or exit transfer state. + * + * @param card Card descriptor. + * @param isSelected True to enter transfer state. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static inline status_t MMC_SelectCard(mmc_card_t *card, bool isSelected); + +/*! + * @brief Send SET_BLOCK_COUNT command. + * + * @param card Card descriptor. + * @param blockCount Block count. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static inline status_t MMC_SetBlockCount(mmc_card_t *card, uint32_t blockCount); + +/*! + * @brief Send GO_IDLE command to reset all cards to idle state + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static inline status_t MMC_GoIdle(mmc_card_t *card); + +/*! + * @brief Send STOP_TRANSMISSION command to card to stop ongoing data transferring. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_StopTransmission(mmc_card_t *card); + +/*! + * @brief Send SET_BLOCK_SIZE command to set the block length in bytes for MMC cards. + * + * @param card Card descriptor. + * @param blockSize Block size. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static inline status_t MMC_SetBlockSize(mmc_card_t *card, uint32_t blockSize); + +/*! + * @brief Send SEND_OPERATION_CONDITION command to validate if the card support host's voltage window + * + * @param card Card descriptor. + * @param arg Command argument. + * @retval kStatus_SDMMC_TransferFailed Transfers failed. + * @retval kStatus_Timeout Operation timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SendOperationCondition(mmc_card_t *card, uint32_t arg); + +/*! + * @brief Send SET_RCA command to set the relative address of the card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SetRelativeAddress(mmc_card_t *card); + +/*! + * @brief Decode CSD register content. + * + * @param card Card descriptor. + * @param rawCsd raw CSD register content. + */ +static void MMC_DecodeCsd(mmc_card_t *card, uint32_t *rawCsd); + +/*! + * @brief Set the card to max transfer speed in non-high speed mode. + * + * @param card Card descriptor. + */ +static void MMC_SetMaxFrequency(mmc_card_t *card); + +/*! + * @brief Set erase unit size of the card + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure Extended CSD failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SetMaxEraseUnitSize(mmc_card_t *card); + +/*! + * @brief Send SWITCH command to set the specific byte in Extended CSD. + * + * Example: + @code + mmc_extended_csd_config_t config; + config.accessMode = kMMC_ExtendedCsdAccessModeSetBits; + config.ByteIndex = 1U; + config.ByteValue = 0x033U; + config.commandSet = kMMC_CommandSetStandard; + MMC_SetExtendedCsdConfig(card, &config); + @endcode + * + * @param card Card descriptor. + * @param config Configuration for Extended CSD. + * @param timeout switch command timeout value. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SetExtendedCsdConfig(mmc_card_t *card, const mmc_extended_csd_config_t *config, uint32_t timeout); + +/*! + * @brief Decode the Extended CSD register + * + * @param card Card descriptor. + * @param rawExtendedCsd Raw extended CSD register content. + */ +static void MMC_DecodeExtendedCsd(mmc_card_t *card, uint32_t *rawExtendedCsd); + +/*! + * @brief Send SEND_EXTENDED_CSD command to get the content of the Extended CSD register + * Allow read the special byte index value if targetAddr is not NULL + * @param card Card descriptor. + * @param targetAddr Pointer to store the target byte value. + * @param byteIndex Target byte index. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SendExtendedCsd(mmc_card_t *card, uint8_t *targetAddr, uint32_t byteIndex); + +/*! + * @brief Set the power class of the card at specific bus width and host intended voltage window. + * + * @param card Card descriptor. + * @return The power class switch status. + */ +static status_t MMC_SetPowerClass(mmc_card_t *card); + +/*! + * @brief Send test pattern to get the functional pin in the MMC bus + * + * @param card Card descriptor. + * @param blockSize Test pattern block size. + * @param pattern Test pattern data buffer. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SendTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern); + +/*! + * @brief Receive test pattern reversed by the card. + * + * @param card Card descriptor. + * @param blockSize Test pattern block size. + * @param pattern Test pattern data buffer. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_ReceiveTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern); + +/*! + * @brief Bus test procedure to get the functional data pin in the bus + * + * @param card Card descriptor. + * @param width Data bus width. + * @retval kStatus_SDMMC_SendTestPatternFailed Send test pattern failed. + * @retval kStatus_SDMMC_ReceiveTestPatternFailed Receive test pattern failed. + * @retval kStatus_Fail Test failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_TestDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width); + +/*! + * @brief Send SET_BUS_WIDTH command to set the bus width. + * + * @param card Card descriptor. + * @param width Data bus width. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SetDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width); + +/*! + * @brief Set max the bus width automatically + * + * @param card Card descriptor. + * @param targetTiming switch target timing + * @retval kStatus_SDMMC_SetDataBusWidthFailed switch fail. + * @retval kStatus_Success switch success. + */ +static status_t MMC_SetMaxDataBusWidth(mmc_card_t *card, mmc_high_speed_timing_t targetTiming); + +/*! + * @brief Switch the card to high speed mode + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support high speed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SelectBusTiming(mmc_card_t *card); + +/*! + * @brief select card HS_TIMING value and card driver strength + * + * @param card Card descriptor. + * @param timing Timing interface value. + * @param driverStrength driver strength value. + * @retval kStatus_Success switch success. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed , config extend csd register fail. + */ +static status_t MMC_SwitchHSTiming(mmc_card_t *card, uint8_t timing, uint8_t driverStrength); + +/*! + * @brief switch to HS400 mode. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. + * @retval kStatus_SDMMC_SwitchBusTimingFailed switch bus timing fail. + * @retval kStatus_SDMMC_SetDataBusWidthFailed switch bus width fail. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SwitchToHS400(mmc_card_t *card); + +/*! + * @brief switch to HS200 mode. + * + * @param card Card descriptor. + * @param freq Target frequency. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. + * @retval kStatus_SDMMC_TuningFail tuning fail. + * @retval kStatus_SDMMC_SetDataBusWidthFailed switch bus width fail. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SwitchToHS200(mmc_card_t *card, uint32_t freq); + +/*! + * @brief switch to HS400 mode. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. + * @retval kStatus_SDMMC_SetDataBusWidthFailed switch bus width fail. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SwitchToHighSpeed(mmc_card_t *card); + +/*! + * @brief Decode CID register + * + * @param card Card descriptor. + * @param rawCid Raw CID register content. + */ +static void MMC_DecodeCid(mmc_card_t *card, uint32_t *rawCid); + +/*! + * @brief Send ALL_SEND_CID command + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_AllSendCid(mmc_card_t *card); + +/*! + * @brief Send SEND_CSD command to get CSD from card + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_SendCsd(mmc_card_t *card); + +/*! + * @brief Check if the block range accessed is within current partition. + * + * @param card Card descriptor. + * @param startBlock Start block to access. + * @param blockCount Block count to access. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_CheckBlockRange(mmc_card_t *card, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Check if the erase group range accessed is within current partition. + * + * @param card Card descriptor. + * @param startGroup Start group to access. + * @param endGroup End group to access. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_CheckEraseGroupRange(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup); + +/*! + * @brief MMC excute tuning function. + * + * @param card Card descriptor. + * @retval kStatus_Success Operate successfully. + * @retval kStatus_SDMMC_TuningFail tuning fail. + * @retval kStatus_SDMMC_TransferFailed transfer fail + */ +static inline status_t MMC_ExecuteTuning(mmc_card_t *card); +/*! + * @brief Read data from specific MMC card + * + * @param card Card descriptor. + * @param buffer Buffer to save received data. + * @param startBlock Start block to read. + * @param blockSize Block size. + * @param blockCount Block count to read. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. + * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_Read( + mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); + +/*! + * @brief Write data from specific MMC card + * + * @param card Card descriptor. + * @param buffer Buffer to hold the data to write. + * @param startBlock Start block to write. + * @param blockSize Block size. + * @param blockCount Block count to write. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_Write( + mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); + +/*! + * @brief MMC card erase function + * + * @param card Card descriptor. + * @param startGroupAddress start erase group address. + * @param endGroupAddress end erase group address. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t MMC_Erase(mmc_card_t *card, uint32_t startGroupAddress, uint32_t endGroupAddress); + +/*! + * @brief card transfer function wrapper + * This function is used to do tuning before transfer if the cmd won't casue re-tuning + * request, then you can call host transfer function directly + * @param card Card descriptor. + * @param content Transfer content. + * @param retry Retry times. + * @retval kStatus_SDMMC_TransferFailed transfer fail + * @retval kStatus_SDMMC_TuningFail tuning fail + * @retval kStatus_Success transfer success + */ +static status_t MMC_Transfer(mmc_card_t *card, sdmmchost_transfer_t *content, uint32_t retry); + +/*! + * @brief card validate operation voltage + * This function is used to validate the operation voltage bettwen host and card + * + * @param card Card descriptor. + * @param opcode Retry times. + * @retval kStatus_Fail the operation voltage condition doesn't match between card and host + * @retval kStatus_Success voltage validate successfully + */ +static status_t MMC_ValidateOperationVoltage(mmc_card_t *card, uint32_t *opcode); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/* Frequency unit defined in TRANSFER SPEED field in CSD */ +static const uint32_t g_transerSpeedFrequencyUnit[] = {100000U, 1000000U, 10000000U, 100000000U}; +/* The multiplying value defined in TRANSFER SPEED field in CSD */ +static const uint32_t g_transerSpeedMultiplierFactor[] = {0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, + 35U, 40U, 45U, 52U, 55U, 60U, 70U, 80U}; + +/******************************************************************************* + * Code + ******************************************************************************/ +static inline status_t MMC_SelectCard(mmc_card_t *card, bool isSelected) +{ + assert(card != NULL); + + return SDMMC_SelectCard(card->host, card->relativeAddress, isSelected); +} + +static inline status_t MMC_SetBlockCount(mmc_card_t *card, uint32_t blockCount) +{ + assert(card != NULL); + + return SDMMC_SetBlockCount(card->host, blockCount); +} + +static inline status_t MMC_GoIdle(mmc_card_t *card) +{ + assert(card != NULL); + + return SDMMC_GoIdle(card->host); +} + +static inline status_t MMC_SetBlockSize(mmc_card_t *card, uint32_t blockSize) +{ + assert(card != NULL); + + return SDMMC_SetBlockSize(card->host, blockSize); +} + +static status_t MMC_ExecuteTuning(mmc_card_t *card) +{ + assert(card != NULL); + + uint32_t blockSize = 0U; + + if (card->busWidth == kMMC_DataBusWidth4bit) + { + blockSize = 64U; + } + else if (card->busWidth == kMMC_DataBusWidth8bit) + { + blockSize = 128U; + } + else + { + /* do not need tuning in this situation */ + return kStatus_Success; + } + + return SDMMCHOST_ExecuteTuning(card->host, (uint32_t)kMMC_SendTuningBlock, + (uint32_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer), + blockSize); +} + +static status_t MMC_Transfer(mmc_card_t *card, sdmmchost_transfer_t *content, uint32_t retry) +{ + assert(content != NULL); + status_t error; + uint32_t retuningCount = 3U; + + do + { + error = SDMMCHOST_TransferFunction(card->host, content); + + if (error == kStatus_Success) + { + break; + } + + if (((retry == 0U) && (content->data != NULL)) || (error == kStatus_SDMMC_ReTuningRequest)) + { + /* abort previous transfer firstly */ + (void)MMC_StopTransmission(card); + + if (card->busTiming == kMMC_HighSpeed200Timing) + { + if (--retuningCount == 0U) + { + break; + } + /* perform retuning */ + if (MMC_ExecuteTuning(card) != kStatus_Success) + { + error = kStatus_SDMMC_TuningFail; + SDMMC_LOG("\r\nError: retuning failed."); + break; + } + else + { + SDMMC_LOG("\r\nlog: retuning successfully."); + continue; + } + } + } + + if (retry != 0U) + { + retry--; + } + else + { + break; + } + + } while (true); + + return error; +} + +static status_t MMC_SendStatus(mmc_card_t *card, uint32_t *status) +{ + assert(card != NULL); + status_t error = kStatus_Success; + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + uint32_t retry = 10; + + command.index = (uint32_t)kSDMMC_SendStatus; + command.argument = card->relativeAddress << 16U; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + + while (retry != 0U) + { + error = MMC_Transfer(card, &content, 2U); + if ((--retry == 0U) && (error != kStatus_Success)) + { + return kStatus_SDMMC_TransferFailed; + } + + if (kStatus_Success == error) + { + break; + } + } + + *status = command.response[0U]; + + return error; +} + +status_t MMC_PollingCardStatusBusy(mmc_card_t *card, bool checkStatus, uint32_t timeoutMs) +{ + assert(card != NULL); + + uint32_t statusTimeoutUs = timeoutMs * 1000U; + bool cardBusy = false; + status_t error = kStatus_SDMMC_CardStatusBusy; + uint32_t status = 0U; + + do + { + cardBusy = SDMMCHOST_IsCardBusy(card->host); + + if (cardBusy == false) + { + if (checkStatus) + { + error = MMC_SendStatus(card, &status); + if (kStatus_Success == error) + { + /* check the response error */ + if (0U != (status & (SDMMC_R1_ALL_ERROR_FLAG | SDMMC_MASK(kSDMMC_R1SwitchErrorFlag)))) + { + SDMMC_LOG("\r\nError: CMD13 report switch error %x.", status); + + error = kStatus_SDMMC_SwitchFailed; + } + else if ((0U != (status & SDMMC_MASK(kSDMMC_R1ReadyForDataFlag))) && + (SDMMC_R1_CURRENT_STATE(status) != (uint32_t)kSDMMC_R1StateProgram)) + { + error = kStatus_SDMMC_CardStatusIdle; + break; + } + else + { + SDMMC_LOG("\r\nWarning: CMD13 report busy %x.", status); + error = kStatus_SDMMC_CardStatusBusy; + } + } + else + { + error = kStatus_SDMMC_TransferFailed; + break; + } + } + else + { + error = kStatus_SDMMC_CardStatusIdle; + break; + } + } + + if (statusTimeoutUs != 0U) + { + /* Delay 125us to throttle the polling rate */ + statusTimeoutUs -= SDMMC_OSADelayUs(125U); + } + + } while (statusTimeoutUs != 0U); + + return error; +} + +static status_t MMC_StopTransmission(mmc_card_t *card) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDMMC_StopTransmission; + command.argument = 0U; + command.type = kCARD_CommandTypeAbort; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t MMC_SendOperationCondition(mmc_card_t *card, uint32_t arg) +{ + assert(card != NULL); + + sdmmchost_cmd_t command = {0}; + sdmmchost_transfer_t content = {0}; + status_t error; + uint32_t i = MMC_CMD1_RETRY_TIMES; + + /* Send CMD1 with the intended voltage range in the argument(either 0x00FF8000 or 0x00000080) */ + command.index = (uint32_t)kMMC_SendOperationCondition; + command.argument = arg; + command.responseType = kCARD_ResponseTypeR3; + + content.command = &command; + content.data = NULL; + do + { + error = SDMMCHOST_TransferFunction(card->host, &content); + + if (error == kStatus_Success) + { + /* record OCR register */ + card->ocr = command.response[0U]; + + if ((arg == 0U) && (command.response[0U] != 0U)) + { + error = kStatus_Success; + } + /* Repeat CMD1 until the busy bit is cleared. */ + else if (0U == (command.response[0U] & MMC_OCR_BUSY_MASK)) + { + error = kStatus_Timeout; + } + else + { + error = kStatus_Success; + if (((card->ocr & MMC_OCR_ACCESS_MODE_MASK) >> MMC_OCR_ACCESS_MODE_SHIFT) == + (uint32_t)kMMC_AccessModeSector) + { + card->flags |= (uint32_t)kMMC_SupportHighCapacityFlag; + } + } + } + + SDMMC_OSADelay(10U); + + } while ((0U != i--) && (error != kStatus_Success)); + + return error; +} + +static status_t MMC_SetRelativeAddress(mmc_card_t *card) +{ + assert(card != NULL); + + sdmmchost_cmd_t command = {0}; + sdmmchost_transfer_t content = {0}; + status_t error = kStatus_Success; + + /* Send CMD3 with a chosen relative address, with value greater than 1 */ + command.index = (uint32_t)kMMC_SetRelativeAddress; + command.argument = (MMC_DEFAULT_RELATIVE_ADDRESS << 16U); + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if ((kStatus_Success == error) || (0U == ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG))) + { + card->relativeAddress = MMC_DEFAULT_RELATIVE_ADDRESS; + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static void MMC_DecodeCsd(mmc_card_t *card, uint32_t *rawCsd) +{ + assert(card != NULL); + assert(rawCsd != NULL); + + mmc_csd_t *csd; + uint32_t multiplier; + + csd = &(card->csd); + csd->csdStructureVersion = (uint8_t)((rawCsd[3U] & 0xC0000000U) >> 30U); + csd->systemSpecificationVersion = (uint8_t)((rawCsd[3U] & 0x3C000000U) >> 26U); + csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF0000U) >> 16U); + csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); + csd->transferSpeed = (uint8_t)(rawCsd[3U] & 0xFFU); + csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF00000U) >> 20U); + /* Max block length read/write one time */ + csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF0000U) >> 16U); + if ((rawCsd[2U] & 0x8000U) != 0U) + { + csd->flags |= (uint16_t)kMMC_CsdReadBlockPartialFlag; + } + if ((rawCsd[2U] & 0x4000U) != 0U) + { + csd->flags |= (uint16_t)kMMC_CsdWriteBlockMisalignFlag; + } + if ((rawCsd[2U] & 0x2000U) != 0U) + { + csd->flags |= (uint16_t)kMMC_CsdReadBlockMisalignFlag; + } + if ((rawCsd[2U] & 0x1000U) != 0U) + { + csd->flags |= (uint16_t)kMMC_CsdDsrImplementedFlag; + } + csd->deviceSize = (uint16_t)(((rawCsd[2U] & 0x3FFU) << 2U) + ((rawCsd[1U] & 0xC0000000U) >> 30U)); + csd->readCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x38000000U) >> 27U); + csd->readCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x07000000U) >> 24U); + csd->writeCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x00E00000U) >> 21U); + csd->writeCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x001C0000U) >> 18U); + csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x00038000U) >> 15U); + csd->eraseGroupSize = (uint8_t)((rawCsd[1U] & 0x00007C00U) >> 10U); + csd->eraseGroupSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x000003E0U) >> 5U); + csd->writeProtectGroupSize = (uint8_t)(rawCsd[1U] & 0x0000001FU); + if ((rawCsd[0U] & 0x80000000U) != 0U) + { + csd->flags |= (uint16_t)kMMC_CsdWriteProtectGroupEnabledFlag; + } + csd->defaultEcc = (uint8_t)((rawCsd[0U] & 0x60000000U) >> 29U); + csd->writeSpeedFactor = (uint8_t)((rawCsd[0U] & 0x1C000000U) >> 26U); + csd->maxWriteBlockLength = (uint8_t)((rawCsd[0U] & 0x03C00000U) >> 22U); + if ((rawCsd[0U] & 0x00200000U) != 0U) + { + csd->flags |= (uint16_t)kMMC_CsdWriteBlockPartialFlag; + } + if ((rawCsd[0U] & 0x00010000U) != 0U) + { + csd->flags |= (uint16_t)kMMC_ContentProtectApplicationFlag; + } + if ((rawCsd[0U] & 0x00008000U) != 0U) + { + csd->flags |= (uint16_t)kMMC_CsdFileFormatGroupFlag; + } + if ((rawCsd[0U] & 0x00004000U) != 0U) + { + csd->flags |= (uint16_t)kMMC_CsdCopyFlag; + } + if ((rawCsd[0U] & 0x00002000U) != 0U) + { + csd->flags |= (uint16_t)kMMC_CsdPermanentWriteProtectFlag; + } + if ((rawCsd[0U] & 0x00001000U) != 0U) + { + csd->flags |= (uint16_t)kMMC_CsdTemporaryWriteProtectFlag; + } + csd->fileFormat = (uint8_t)((rawCsd[0U] & 0x00000C00U) >> 10U); + csd->eccCode = (uint8_t)((rawCsd[0U] & 0x00000300U) >> 8U); + + /* Calculate the device total block count. */ + /* For the card capacity of witch higher than 2GB, the maximum possible value should be set to this register + is 0xFFF. */ + if (card->csd.deviceSize != 0xFFFU) + { + multiplier = (2UL << (card->csd.deviceSizeMultiplier + 2U - 1U)); + card->userPartitionBlocks = (((card->csd.deviceSize + 1UL) * multiplier) / FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + + card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; +} + +static void MMC_SetMaxFrequency(mmc_card_t *card) +{ + assert(card != NULL); + + uint32_t frequencyUnit; + uint32_t multiplierFactor; + uint32_t maxBusClock_Hz; + + /* g_fsdhcCommandUnitInTranSpeed and g_transerSpeedMultiplierFactor are used to calculate the max speed in normal + mode not high speed mode. + For cards supporting version 4.0, 4.1, and 4.2 of the specification, the value shall be 20MHz(0x2A). + For cards supporting version 4.3, the value shall be 26 MHz (0x32H). In High speed mode, the max + frequency is decided by CARD_TYPE in Extended CSD. */ + frequencyUnit = g_transerSpeedFrequencyUnit[READ_MMC_TRANSFER_SPEED_FREQUENCY_UNIT(card->csd)]; + multiplierFactor = g_transerSpeedMultiplierFactor[READ_MMC_TRANSFER_SPEED_MULTIPLIER(card->csd)]; + maxBusClock_Hz = (frequencyUnit * multiplierFactor) / DIVIDER_IN_TRANSFER_SPEED; + card->busClock_Hz = SDMMCHOST_SetCardClock(card->host, maxBusClock_Hz); +} + +static status_t MMC_SetMaxEraseUnitSize(mmc_card_t *card) +{ + assert(card != NULL); + + uint32_t erase_group_size; + uint32_t erase_group_multiplier; + mmc_extended_csd_config_t extendedCsdconfig; + + /* Legacy mmc card , do not support the command */ + if ((card->csd.systemSpecificationVersion == (uint32_t)kMMC_SpecificationVersion3) && + (card->csd.csdStructureVersion == (uint32_t)kMMC_CsdStrucureVersion12)) + { + return kStatus_Success; + } + + if (((0U == (card->flags & (uint32_t)kMMC_SupportHighCapacityFlag)) || + (card->extendedCsd.highCapacityEraseUnitSize == 0U)) || + (card->extendedCsd.highCapacityEraseTimeout == 0U)) + { + erase_group_size = card->csd.eraseGroupSize; + erase_group_multiplier = card->csd.eraseGroupSizeMultiplier; + card->eraseGroupBlocks = ((erase_group_size + 1U) * (erase_group_multiplier + 1U)); + } + else + { + /* Erase Unit Size = 512Kbyte * HC_ERASE_GRP_SIZE. Block size is 512 bytes. */ + card->eraseGroupBlocks = (card->extendedCsd.highCapacityEraseUnitSize * 1024UL); + /* Enable high capacity erase unit size. */ + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeSetBits; + extendedCsdconfig.ByteIndex = (uint8_t)kMMC_ExtendedCsdIndexEraseGroupDefinition; + extendedCsdconfig.ByteValue = 0x01U; /* The high capacity erase unit size enable bit is bit 0 */ + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig, 0U)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + } + + return kStatus_Success; +} + +static status_t MMC_SetExtendedCsdConfig(mmc_card_t *card, const mmc_extended_csd_config_t *config, uint32_t timeout) +{ + assert(card != NULL); + assert(config != NULL); + + status_t error = kStatus_Success; + uint32_t parameter = 0U; + sdmmchost_cmd_t command = {0}; + sdmmchost_transfer_t content = {0}; + uint32_t timeoutMS = timeout == 0U ? card->extendedCsd.genericCMD6Timeout : timeout; + + parameter |= ((uint32_t)(config->commandSet) << MMC_SWITCH_COMMAND_SET_SHIFT); + parameter |= ((uint32_t)(config->ByteValue) << MMC_SWITCH_VALUE_SHIFT); + parameter |= ((uint32_t)(config->ByteIndex) << MMC_SWITCH_BYTE_INDEX_SHIFT); + parameter |= ((uint32_t)(config->accessMode) << MMC_SWITCH_ACCESS_MODE_SHIFT); + command.index = (uint32_t)kMMC_Switch; + command.argument = parameter; + command.responseType = kCARD_ResponseTypeR1b; /* Send switch command to set the pointed byte in Extended CSD. */ + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG | SDMMC_MASK(kSDMMC_R1SwitchErrorFlag); + + content.command = &command; + content.data = NULL; + error = MMC_Transfer(card, &content, 2U); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Wait for the card write process complete because of that card read process and write process use one buffer. */ + error = MMC_PollingCardStatusBusy(card, true, timeoutMS == 0U ? MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT : timeoutMS); + if (kStatus_SDMMC_CardStatusIdle != error) + { + return kStatus_SDMMC_PollingCardIdleFailed; + } + + return kStatus_Success; +} + +static void MMC_DecodeExtendedCsd(mmc_card_t *card, uint32_t *rawExtendedCsd) +{ + assert(card != NULL); + assert(rawExtendedCsd != NULL); + + uint8_t *buffer = (uint8_t *)rawExtendedCsd; + mmc_extended_csd_t *extendedCsd = &(card->extendedCsd); + + /* Extended CSD is transferred as a data block from least byte indexed 0. */ + extendedCsd->bootPartitionWP = buffer[173U]; + extendedCsd->bootWPStatus = buffer[174U]; + extendedCsd->highDensityEraseGroupDefinition = buffer[175U]; + extendedCsd->bootDataBusConditions = buffer[177U]; + extendedCsd->bootConfigProtect = buffer[178U]; + extendedCsd->partitionConfig = buffer[179U]; + extendedCsd->eraseMemoryContent = buffer[181U]; + extendedCsd->dataBusWidth = buffer[183U]; + extendedCsd->highSpeedTiming = buffer[185U]; + extendedCsd->powerClass = buffer[187U]; + extendedCsd->commandSetRevision = buffer[189U]; + extendedCsd->commandSet = buffer[191U]; + extendedCsd->extendecCsdVersion = buffer[192U]; + extendedCsd->csdStructureVersion = buffer[194U]; + extendedCsd->partitionAttribute = buffer[156U]; + extendedCsd->extPartitionSupport = buffer[494U]; + extendedCsd->cardType = buffer[196U]; + /* This field define the type of the card. The only currently valid values for this field are 0x01 and 0x03. */ + card->flags |= extendedCsd->cardType; + + extendedCsd->ioDriverStrength = buffer[197U]; + + extendedCsd->partitionSwitchTimeout = buffer[199U]; + extendedCsd->powerClass52MHz195V = buffer[200U]; + extendedCsd->powerClass26MHz195V = buffer[201U]; + extendedCsd->powerClass52MHz360V = buffer[202U]; + extendedCsd->powerClass26MHz360V = buffer[203U]; + extendedCsd->powerClass200MHZVCCQ130VVCC360V = buffer[236U]; + extendedCsd->powerClass200MHZVCCQ195VVCC360V = buffer[237U]; + extendedCsd->powerClass52MHZDDR195V = buffer[238U]; + extendedCsd->powerClass52MHZDDR360V = buffer[239U]; + extendedCsd->powerClass200MHZDDR360V = buffer[253U]; + extendedCsd->minimumReadPerformance4Bit26MHz = buffer[205U]; + extendedCsd->minimumWritePerformance4Bit26MHz = buffer[206U]; + extendedCsd->minimumReadPerformance8Bit26MHz4Bit52MHz = buffer[207U]; + extendedCsd->minimumWritePerformance8Bit26MHz4Bit52MHz = buffer[208U]; + extendedCsd->minimumReadPerformance8Bit52MHz = buffer[209U]; + extendedCsd->minimumWritePerformance8Bit52MHz = buffer[210U]; + extendedCsd->minReadPerformance8bitAt52MHZDDR = buffer[234U]; + extendedCsd->minWritePerformance8bitAt52MHZDDR = buffer[235U]; + /* Get user partition size. */ + extendedCsd->sectorCount = ((((uint32_t)buffer[215U]) << 24U) + (((uint32_t)buffer[214U]) << 16U) + + (((uint32_t)buffer[213U]) << 8U) + (uint32_t)buffer[212U]); + if ((card->flags & (uint32_t)kMMC_SupportHighCapacityFlag) != 0U) + { + card->userPartitionBlocks = card->extendedCsd.sectorCount; + } + + extendedCsd->sleepAwakeTimeout = buffer[217U]; + extendedCsd->sleepCurrentVCCQ = buffer[219U]; + extendedCsd->sleepCurrentVCC = buffer[220U]; + extendedCsd->highCapacityWriteProtectGroupSize = buffer[221U]; + extendedCsd->reliableWriteSectorCount = buffer[222U]; + extendedCsd->highCapacityEraseTimeout = buffer[223U]; + extendedCsd->highCapacityEraseUnitSize = buffer[224U]; + extendedCsd->accessSize = buffer[225U]; + + /* Get boot partition size: 128KB * BOOT_SIZE_MULT*/ + card->bootPartitionBlocks = ((128U * 1024U * buffer[226U]) / FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + /* support HS400 data strobe */ + if (buffer[184] == 1U) + { + card->flags |= (uint32_t)kMMC_SupportEnhanceHS400StrobeFlag; + } + + /* Check if card support boot mode. */ + if ((buffer[228U] & 0x1U) != 0U) + { + card->flags |= (uint32_t)kMMC_SupportAlternateBootFlag; + } + else if ((buffer[228U] & 0x2U) != 0U) + { + card->flags |= (uint32_t)kMMC_SupportDDRBootFlag; + } + else if ((buffer[228U] & 0x4U) != 0U) + { + card->flags |= (uint32_t)kMMC_SupportHighSpeedBootFlag; + } + else + { + /* empty with intentional */ + } + /* cache size unit 1kb */ + extendedCsd->cacheSize = (((uint32_t)buffer[252U]) << 24) | (((uint32_t)buffer[251U]) << 16) | + (((uint32_t)buffer[250U]) << 8) | (((uint32_t)buffer[249U])); + + extendedCsd->genericCMD6Timeout = buffer[248U] * 10UL; + extendedCsd->supportedCommandSet = buffer[504U]; +} + +static status_t MMC_SendExtendedCsd(mmc_card_t *card, uint8_t *targetAddr, uint32_t byteIndex) +{ + assert(card != NULL); + + sdmmchost_cmd_t command = {0}; + sdmmchost_transfer_t content = {0}; + sdmmchost_data_t data = {0}; + uint32_t *alignBuffer = (uint32_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + status_t error = kStatus_Success; + + /* Legacy mmc card , do not support the command */ + if ((card->csd.systemSpecificationVersion == (uint32_t)kMMC_SpecificationVersion3) && + (card->csd.csdStructureVersion == (uint32_t)kMMC_CsdStrucureVersion12)) + { + return kStatus_Success; + } + + (void)memset(alignBuffer, 0, MMC_EXTENDED_CSD_BYTES); + + command.index = (uint32_t)kMMC_SendExtendedCsd; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + data.blockCount = 1U; + data.blockSize = MMC_EXTENDED_CSD_BYTES; + data.rxData = alignBuffer; + + content.command = &command; + content.data = &data; + error = SDMMCHOST_TransferFunction(card->host, &content); + if ((kStatus_Success == error) && (0U == (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG))) + { + SDMMCHOST_ConvertDataToLittleEndian(card->host, alignBuffer, MMC_EXTENDED_CSD_BYTES / 4U, + kSDMMC_DataPacketFormatLSBFirst); + if (targetAddr != NULL) + { + *targetAddr = (uint8_t)alignBuffer[byteIndex]; + } + else + { + MMC_DecodeExtendedCsd(card, alignBuffer); + } + + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static status_t MMC_SetPowerClass(mmc_card_t *card) +{ + assert(card != NULL); + + uint8_t mask = 0, shift = 0U; + uint8_t powerClass = 0; + mmc_extended_csd_config_t extendedCsdconfig; + + /* Legacy mmc card , do not support the command */ + if ((card->csd.systemSpecificationVersion == (uint32_t)kMMC_SpecificationVersion3) && + (card->csd.csdStructureVersion == (uint32_t)kMMC_CsdStrucureVersion12)) + { + return kStatus_Success; + } + + if ((card->busWidth == kMMC_DataBusWidth4bit) || (card->busWidth == kMMC_DataBusWidth4bitDDR)) + { + mask = MMC_POWER_CLASS_4BIT_MASK; /* The mask of 4 bit bus width's power class */ + shift = 0U; + } + else if ((card->busWidth == kMMC_DataBusWidth8bit) || (card->busWidth == kMMC_DataBusWidth8bitDDR)) + { + mask = MMC_POWER_CLASS_8BIT_MASK; /* The mask of 8 bit bus width's power class */ + shift = 4U; + } + else + { + return kStatus_Success; + } + + switch (card->hostVoltageWindowVCC) + { + case kMMC_VoltageWindows270to360: + + if (card->busTiming == kMMC_HighSpeed200Timing) + { + if (card->hostVoltageWindowVCCQ == kMMC_VoltageWindow170to195) + { + powerClass = ((card->extendedCsd.powerClass200MHZVCCQ195VVCC360V) & mask); + } + else if (card->hostVoltageWindowVCCQ == kMMC_VoltageWindow120) + { + powerClass = ((card->extendedCsd.powerClass200MHZVCCQ130VVCC360V) & mask); + } + else + { + /* intentional empty */ + } + } + else if (card->busTiming == kMMC_HighSpeed400Timing) + { + powerClass = ((card->extendedCsd.powerClass200MHZDDR360V) & mask); + } + else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busWidth > kMMC_DataBusWidth8bit)) + { + powerClass = ((card->extendedCsd.powerClass52MHZDDR360V) & mask); + } + else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busClock_Hz > MMC_CLOCK_26MHZ)) + { + powerClass = ((card->extendedCsd.powerClass52MHz360V) & mask); + } + else if (card->busTiming == kMMC_HighSpeedTiming) + { + powerClass = ((card->extendedCsd.powerClass26MHz360V) & mask); + } + else + { + /* intentional empty */ + } + + break; + + case kMMC_VoltageWindow170to195: + + if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busClock_Hz <= MMC_CLOCK_26MHZ)) + { + powerClass = ((card->extendedCsd.powerClass26MHz195V) & mask); + } + else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busClock_Hz > MMC_CLOCK_26MHZ)) + { + powerClass = ((card->extendedCsd.powerClass52MHz195V) & mask); + } + else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busWidth > kMMC_DataBusWidth8bit)) + { + powerClass = ((card->extendedCsd.powerClass52MHZDDR195V) & mask); + } + else + { + /* intentional empty */ + } + + break; + default: + powerClass = 0; + break; + } + + /* due to 8bit power class position [7:4] */ + powerClass >>= shift; + + if (powerClass > 0U) + { + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)kMMC_ExtendedCsdIndexPowerClass; + extendedCsdconfig.ByteValue = powerClass; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig, 0U)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + /* restore power class */ + card->extendedCsd.powerClass = powerClass; + } + + return kStatus_Success; +} + +static status_t MMC_SendTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern) +{ + assert(card != NULL); + assert(blockSize <= FSL_SDMMC_DEFAULT_BLOCK_SIZE); + assert(pattern != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + sdmmchost_data_t data = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kMMC_SendingBusTest; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + /* Ignore errors in bus test procedure to improve chances that the test will work. */ + data.enableIgnoreError = true; + data.blockCount = 1U; + data.blockSize = blockSize; + data.txData = pattern; + + content.command = &command; + content.data = &data; + error = SDMMCHOST_TransferFunction(card->host, &content); + if ((kStatus_Success != error) || ((command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG) != 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t MMC_ReceiveTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern) +{ + assert(card != NULL); + assert(blockSize <= FSL_SDMMC_DEFAULT_BLOCK_SIZE); + assert(pattern != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + sdmmchost_data_t data = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kMMC_BusTestRead; + command.responseType = kCARD_ResponseTypeR1; + + /* Ignore errors in bus test procedure to improve chances that the test will work. */ + data.enableIgnoreError = true; + data.blockCount = 1U; + data.blockSize = blockSize; + data.rxData = pattern; + + content.command = &command; + content.data = &data; + error = SDMMCHOST_TransferFunction(card->host, &content); + if ((kStatus_Success != error) || (((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG) != 0U)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t MMC_TestDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width) +{ + assert(card != NULL); + + uint32_t blockSize = 0U; + uint32_t tempsendPattern = 0U; + uint32_t *tempPattern = (uint32_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + uint32_t xorMask = 0U; + uint32_t xorResult = 0U; + + /* For 8 data lines the data block would be (MSB to LSB): 0x0000_0000_0000_AA55, + For 4 data lines the data block would be (MSB to LSB): 0x0000_005A, + For only 1 data line the data block would be: 0x80 */ + switch (width) + { + case kMMC_DataBusWidth8bit: + case kMMC_DataBusWidth8bitDDR: + blockSize = 8U; + tempPattern[0U] = 0xAA55U; + xorMask = 0xFFFFU; + xorResult = 0xFFFFU; + break; + case kMMC_DataBusWidth4bit: + case kMMC_DataBusWidth4bitDDR: + blockSize = 4U; + tempPattern[0U] = 0x5AU; + xorMask = 0xFFU; + xorResult = 0xFFU; + break; + default: + blockSize = 4U; + tempPattern[0U] = 0x80U; + xorMask = 0xFFU; + xorResult = 0xC0U; + break; + } + + SDMMCHOST_ConvertDataToLittleEndian(card->host, &tempPattern[0], 1U, kSDMMC_DataPacketFormatLSBFirst); + SDMMCHOST_ConvertDataToLittleEndian(card->host, &xorMask, 1U, kSDMMC_DataPacketFormatLSBFirst); + SDMMCHOST_ConvertDataToLittleEndian(card->host, &xorResult, 1U, kSDMMC_DataPacketFormatLSBFirst); + + (void)MMC_SendTestPattern(card, blockSize, tempPattern); + /* restore the send pattern */ + tempsendPattern = tempPattern[0U]; + /* reset the global buffer */ + tempPattern[0U] = 0U; + + (void)MMC_ReceiveTestPattern(card, blockSize, tempPattern); + + /* XOR the send pattern and receive pattern */ + if (((tempPattern[0U] ^ tempsendPattern) & xorMask) != xorResult) + { + return kStatus_Fail; + } + + return kStatus_Success; +} + +static status_t MMC_SetDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width) +{ + assert(card != NULL); + + mmc_extended_csd_config_t extendedCsdconfig; + + /* Set data bus width */ + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)kMMC_ExtendedCsdIndexBusWidth; + extendedCsdconfig.ByteValue = (uint8_t)width; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig, 0U)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + /* restore data bus width */ + card->extendedCsd.dataBusWidth = (uint8_t)width; + + return kStatus_Success; +} + +static status_t MMC_SetMaxDataBusWidth(mmc_card_t *card, mmc_high_speed_timing_t targetTiming) +{ + assert(card != NULL); + + status_t error = kStatus_Fail; + + do + { + if (card->busWidth == kMMC_DataBusWidth1bit) + { + card->busWidth = kMMC_DataBusWidth8bitDDR; + } + + if (card->busWidth == kMMC_DataBusWidth8bitDDR) + { + if (((card->host->capability & + ((uint32_t)kSDMMCHOST_Support8BitDataWidth | (uint32_t)kSDMMCHOST_SupportDDRMode)) == + ((uint32_t)kSDMMCHOST_Support8BitDataWidth | (uint32_t)kSDMMCHOST_SupportDDRMode)) && + (0U != (card->flags & ((uint32_t)kMMC_SupportHighSpeedDDR52MHZ180V300VFlag | + (uint32_t)kMMC_SupportHighSpeedDDR52MHZ120VFlag))) && + ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed400Timing)) && + ((card->usrParam.capability & (uint32_t)kSDMMC_Support8BitWidth) != 0U)) + { + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith8Bit); + if (kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth8bitDDR)) + { + if (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth8bitDDR)) + { + error = kStatus_Success; + card->busWidth = kMMC_DataBusWidth8bitDDR; + break; + } + } + + /* HS400 mode only support 8bit data bus */ + if (card->busTiming == kMMC_HighSpeed400Timing) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + } + card->busWidth = kMMC_DataBusWidth4bitDDR; + } + + if (card->busWidth == kMMC_DataBusWidth4bitDDR) + { + if (((card->host->capability & + ((uint32_t)kSDMMCHOST_Support4BitDataWidth | (uint32_t)kSDMMCHOST_SupportDDRMode)) == + ((uint32_t)kSDMMCHOST_Support4BitDataWidth | (uint32_t)kSDMMCHOST_SupportDDRMode)) && + (0U != (card->flags & ((uint32_t)kMMC_SupportHighSpeedDDR52MHZ180V300VFlag | + (uint32_t)kMMC_SupportHighSpeedDDR52MHZ120VFlag))) && + ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed400Timing))) + { + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith4Bit); + if (kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth4bitDDR)) + { + if (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth4bitDDR)) + { + error = kStatus_Success; + card->busWidth = kMMC_DataBusWidth4bitDDR; + break; + } + } + } + card->busWidth = kMMC_DataBusWidth8bit; + } + + if (card->busWidth == kMMC_DataBusWidth8bit) + { + if (((card->host->capability & (uint32_t)kSDMMCHOST_Support8BitDataWidth) != 0U) && + ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed200Timing)) && + ((card->usrParam.capability & (uint32_t)kSDMMC_Support8BitWidth) != 0U)) + { + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith8Bit); + if (kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth8bit)) + { + if (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth8bit)) + { + error = kStatus_Success; + card->busWidth = kMMC_DataBusWidth8bit; + break; + } + } + } + card->busWidth = kMMC_DataBusWidth4bit; + } + + if (card->busWidth == kMMC_DataBusWidth4bit) + { + if (((card->host->capability & (uint32_t)kSDMMCHOST_Support8BitDataWidth) != 0U) && + ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed200Timing))) + { + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith4Bit); + if (kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth4bit)) + { + if (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth4bit)) + { + error = kStatus_Success; + card->busWidth = kMMC_DataBusWidth4bit; + break; + } + } + /* HS200 mode only support 4bit/8bit data bus */ + if (targetTiming == kMMC_HighSpeed200Timing) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + } + } + + } while (false); + + if (error == kStatus_Fail) + { + /* Card's data bus width will be default 1 bit mode. */ + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith1Bit); + card->busWidth = kMMC_DataBusWidth1bit; + } + + return kStatus_Success; +} + +static status_t MMC_SwitchHSTiming(mmc_card_t *card, uint8_t timing, uint8_t driverStrength) +{ + assert(card != NULL); + + uint8_t hsTiming = 0; + + mmc_extended_csd_config_t extendedCsdconfig; + + /* check the target driver strength support or not */ + if (((card->extendedCsd.ioDriverStrength & (1U << driverStrength)) == 0U) && + (card->extendedCsd.extendecCsdVersion >= (uint8_t)kMMC_ExtendedCsdRevision17)) + { + return kStatus_SDMMC_NotSupportYet; + } + /* calucate the register value */ + hsTiming = (timing & 0xFU) | (uint8_t)(driverStrength << 4U); + + /* Switch to high speed timing. */ + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)kMMC_ExtendedCsdIndexHighSpeedTiming; + extendedCsdconfig.ByteValue = hsTiming; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig, 0U)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + + card->extendedCsd.highSpeedTiming = hsTiming; + + return kStatus_Success; +} + +static status_t MMC_SwitchToHighSpeed(mmc_card_t *card) +{ + assert(card != NULL); + + uint32_t freq = 0U; + + if (kStatus_Success != MMC_SwitchHSTiming(card, (uint8_t)kMMC_HighSpeedTiming, kMMC_DriverStrength0)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + if ((card->flags & (uint32_t)kMMC_SupportHighSpeed52MHZFlag) != 0U) + { + freq = FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, MMC_CLOCK_52MHZ); + } + else if ((card->flags & (uint32_t)kMMC_SupportHighSpeed26MHZFlag) != 0U) + { + freq = FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, MMC_CLOCK_26MHZ); + } + else + { + /* Intentional empty */ + } + + card->busClock_Hz = SDMMCHOST_SetCardClock(card->host, freq); + /* config io speed and strength */ + if (card->usrParam.ioStrength != NULL) + { + card->usrParam.ioStrength(MMC_CLOCK_52MHZ); + } + /* Set card data width, it is nessesary to config the the data bus here, to meet emmc5.0 specification, + * when you are working in DDR mode , HS_TIMING must set before set bus width + */ + if (MMC_SetMaxDataBusWidth(card, kMMC_HighSpeedTiming) != kStatus_Success) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + + if ((card->busWidth == kMMC_DataBusWidth4bitDDR) || (card->busWidth == kMMC_DataBusWidth8bitDDR)) + { + SDMMCHOST_EnableDDRMode(card->host, true, 0U); + } + + card->busTiming = kMMC_HighSpeedTiming; + + return kStatus_Success; +} + +static status_t MMC_SwitchToHS200(mmc_card_t *card, uint32_t freq) +{ + assert(card != NULL); + + status_t error = kStatus_Fail; + + if ((card->hostVoltageWindowVCCQ != kMMC_VoltageWindow170to195) && + (card->hostVoltageWindowVCCQ != kMMC_VoltageWindow120)) + { + return kStatus_SDMMC_InvalidVoltage; + } + + /* select bus width before select bus timing for HS200 mode */ + if (MMC_SetMaxDataBusWidth(card, kMMC_HighSpeed200Timing) != kStatus_Success) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + + /* switch to HS200 mode */ + if (kStatus_Success != MMC_SwitchHSTiming(card, (uint8_t)kMMC_HighSpeed200Timing, kMMC_DriverStrength0)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + card->busClock_Hz = SDMMCHOST_SetCardClock(card->host, freq); + /* config io speed and strength */ + if (card->usrParam.ioStrength != NULL) + { + card->usrParam.ioStrength(freq); + } + + /* excute tuning for HS200 */ + if (MMC_ExecuteTuning(card) != kStatus_Success) + { + return kStatus_SDMMC_TuningFail; + } + + card->busTiming = kMMC_HighSpeed200Timing; + + error = MMC_PollingCardStatusBusy(card, true, MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (kStatus_SDMMC_CardStatusIdle != error) + { + return kStatus_SDMMC_PollingCardIdleFailed; + } + + return kStatus_Success; +} + +static status_t MMC_SwitchToHS400(mmc_card_t *card) +{ + assert(card != NULL); + + uint32_t status = 0U; + uint32_t hs400Freq = FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, MMC_CLOCK_HS400); + status_t error = kStatus_Fail; + + if ((card->hostVoltageWindowVCCQ != kMMC_VoltageWindow170to195) && + (card->hostVoltageWindowVCCQ != kMMC_VoltageWindow120)) + { + return kStatus_SDMMC_InvalidVoltage; + } + + if (card->host->hostController.sourceClock_Hz < MMC_CLOCK_HS400) + { + hs400Freq = card->host->hostController.sourceClock_Hz; + } + + if ((card->host->hostController.sourceClock_Hz > MMC_CLOCK_HS400) && + (card->host->hostController.sourceClock_Hz % MMC_CLOCK_HS400 != 0U)) + { + hs400Freq = card->host->hostController.sourceClock_Hz / + (card->host->hostController.sourceClock_Hz / MMC_CLOCK_HS400 + 1U); + } + /* HS400 mode support 8 bit data bus only */ + card->busWidth = kMMC_DataBusWidth8bit; + /* switch to HS200 perform tuning */ + if (kStatus_Success != MMC_SwitchToHS200(card, hs400Freq / 2U)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + /* check data bus width is 8 bit , otherwise return false*/ + if (card->busWidth != kMMC_DataBusWidth8bit) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + /* + * For the issue found in stress test of repeat emmc initialization operation, after HS200 switch complete, the emmc + * status not correct for switching to high speed, normally the emmc should stay in TRAN state, but sometimes the + * emmc status is in DATA state which will cause switch to High speed failed. when such issue happen, software will + * try to use CMD12 to reset the emmc status to TRAN before switch to high speed for HS400. + */ + error = MMC_SendStatus(card, &status); + if (error != kStatus_Success) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + if (SDMMC_R1_CURRENT_STATE(status) == (uint32_t)kSDMMC_R1StateSendData) + { + SDMMC_LOG("status uncorrect for switching to High speed timing, try use CMD12 to get back to TRAN state\r\n"); + /* try to get back to transfer state before switch to High speed */ + (void)MMC_StopTransmission(card); + } + + /*switch to high speed*/ + if (kStatus_Success != MMC_SwitchHSTiming(card, (uint8_t)kMMC_HighSpeedTiming, kMMC_DriverStrength0)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + + /* switch to high speed first */ + card->busClock_Hz = SDMMCHOST_SetCardClock(card->host, MMC_CLOCK_52MHZ); + /* config io strength */ + if (card->usrParam.ioStrength != NULL) + { + card->usrParam.ioStrength(MMC_CLOCK_52MHZ); + } + + card->busTiming = kMMC_HighSpeed400Timing; + /* switch to 8 bit DDR data bus width */ + if (kStatus_Success != MMC_SetDataBusWidth(card, kMMC_DataBusWidth8bitDDR)) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + /* switch to HS400 */ + if (kStatus_Success != MMC_SwitchHSTiming(card, (uint8_t)kMMC_HighSpeed400Timing, kMMC_DriverStrength0)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + /* config to target freq */ + card->busClock_Hz = SDMMCHOST_SetCardClock(card->host, hs400Freq / 2U); + /* config io speed and strength */ + if (card->usrParam.ioStrength != NULL) + { + card->usrParam.ioStrength(MMC_CLOCK_HS200); + } + /* enable HS400 mode */ + SDMMCHOST_EnableHS400Mode(card->host, true); + /* enable DDR mode */ + SDMMCHOST_EnableDDRMode(card->host, true, 0U); + /* config strobe DLL*/ + SDMMCHOST_EnableStrobeDll(card->host, true); + + return kStatus_Success; +} + +static status_t MMC_SelectBusTiming(mmc_card_t *card) +{ + assert(card != NULL); + + /* Legacy mmc card , do not support the command */ + if ((card->csd.systemSpecificationVersion == (uint8_t)kMMC_SpecificationVersion3) && + (card->csd.csdStructureVersion == (uint8_t)kMMC_CsdStrucureVersion12)) + { + return kStatus_Success; + } + + do + { + if (card->busTiming == kMMC_HighSpeedTimingNone) + { + /* if timing not specified, probe card capability from HS400 mode */ + card->busTiming = kMMC_HighSpeed400Timing; + } + + if (card->busTiming == kMMC_EnhanceHighSpeed400Timing) + { + return kStatus_SDMMC_NotSupportYet; + } + + if (card->busTiming == kMMC_HighSpeed400Timing) + { + if (((card->host->capability & (uint32_t)kSDMMCHOST_SupportHS400) != 0U) && + ((card->hostVoltageWindowVCCQ == kMMC_VoltageWindow170to195) || + (card->hostVoltageWindowVCCQ == kMMC_VoltageWindow120)) && + ((card->flags & + ((uint32_t)kMMC_SupportHS400DDR200MHZ180VFlag | (uint32_t)kMMC_SupportHS400DDR200MHZ120VFlag)) != 0U)) + { + /* switch to HS400 */ + if (kStatus_Success != MMC_SwitchToHS400(card)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + break; + } + + card->busTiming = kMMC_HighSpeed200Timing; + } + + if (card->busTiming == kMMC_HighSpeed200Timing) + { + if (((card->host->capability & (uint32_t)kSDMMCHOST_SupportHS200) != 0U) && + ((card->hostVoltageWindowVCCQ == kMMC_VoltageWindow170to195) || + (card->hostVoltageWindowVCCQ == kMMC_VoltageWindow120)) && + (0U != (card->flags & + ((uint32_t)kMMC_SupportHS200200MHZ180VFlag | (uint32_t)kMMC_SupportHS200200MHZ120VFlag)))) + { + if (kStatus_Success != + MMC_SwitchToHS200(card, FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, MMC_CLOCK_HS200))) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + break; + } + + card->busTiming = kMMC_HighSpeedTiming; + } + + if (card->busTiming == kMMC_HighSpeedTiming) + { + if (kStatus_Success != MMC_SwitchToHighSpeed(card)) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + break; + } + } while (false); + + return kStatus_Success; +} + +static void MMC_DecodeCid(mmc_card_t *card, uint32_t *rawCid) +{ + assert(card != NULL); + assert(rawCid != NULL); + + mmc_cid_t *cid; + + cid = &(card->cid); + cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF000000U) >> 24U); + cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFF00U) >> 8U); + + cid->productName[0U] = (uint8_t)((rawCid[3U] & 0xFFU)); + cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); + cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); + cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); + cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFFU)); + + cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24U); + + cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFFFU) << 8U); + cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFF000000U) >> 24U); + + cid->manufacturerData = (uint8_t)((rawCid[0U] & 0xFFF00U) >> 8U); +} + +static status_t MMC_AllSendCid(mmc_card_t *card) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDMMC_AllSendCid; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success == error) + { + (void)memcpy(card->internalBuffer, (uint8_t *)command.response, 16U); + MMC_DecodeCid(card, command.response); + + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static status_t MMC_SendCsd(mmc_card_t *card) +{ + assert(card != NULL); + + sdmmchost_cmd_t command = {0}; + sdmmchost_transfer_t content = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDMMC_SendCsd; + command.argument = (card->relativeAddress << 16U); + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success == error) + { + (void)memcpy(card->internalBuffer, (uint8_t *)command.response, 16U); + /* The response is from bit 127:8 in R2, corresponding to command.response[3][31:0] to + command.response[0U][31:8]. */ + MMC_DecodeCsd(card, (uint32_t *)(uint32_t)card->internalBuffer); + + return kStatus_Success; + } + + return kStatus_SDMMC_TransferFailed; +} + +static status_t MMC_CheckBlockRange(mmc_card_t *card, uint32_t startBlock, uint32_t blockCount) +{ + assert(card != NULL); + assert(blockCount != 0U); + + status_t error = kStatus_Success; + uint32_t partitionBlocks; + + switch (card->currentPartition) + { + case kMMC_AccessPartitionUserAera: + { + partitionBlocks = card->userPartitionBlocks; + break; + } + case kMMC_AccessPartitionBoot1: + case kMMC_AccessPartitionBoot2: + { + /* Boot partition 1 and partition 2 have the same partition size. */ + partitionBlocks = card->bootPartitionBlocks; + break; + } + default: + error = kStatus_InvalidArgument; + break; + } + /* Check if the block range accessed is within current partition's block boundary. */ + if ((error == kStatus_Success) && ((startBlock + blockCount) > partitionBlocks)) + { + error = kStatus_InvalidArgument; + } + + return error; +} + +static status_t MMC_CheckEraseGroupRange(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup) +{ + assert(card != NULL); + + status_t error = kStatus_Success; + uint32_t partitionBlocks; + uint32_t eraseGroupBoundary; + + switch (card->currentPartition) + { + case kMMC_AccessPartitionUserAera: + { + partitionBlocks = card->userPartitionBlocks; + break; + } + case kMMC_AccessPartitionBoot1: + case kMMC_AccessPartitionBoot2: + { + /* Boot partition 1 and partition 2 have the same partition size. */ + partitionBlocks = card->bootPartitionBlocks; + break; + } + default: + error = kStatus_InvalidArgument; + break; + } + + if (error == kStatus_Success) + { + /* Check if current partition's total block count is integer multiples of the erase group size. */ + if ((partitionBlocks % card->eraseGroupBlocks) == 0U) + { + eraseGroupBoundary = (partitionBlocks / card->eraseGroupBlocks); + } + else + { + /* Card will ignore the unavailable blocks within the last erase group automatically. */ + eraseGroupBoundary = (partitionBlocks / card->eraseGroupBlocks + 1U); + } + + /* Check if the group range accessed is within current partition's erase group boundary. */ + if ((startGroup > eraseGroupBoundary) || (endGroup > eraseGroupBoundary)) + { + error = kStatus_InvalidArgument; + } + } + + return error; +} + +static status_t MMC_Read( + mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) +{ + assert(card != NULL); + assert(buffer != NULL); + assert(blockCount != 0U); + assert(blockSize != 0U); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + sdmmchost_cmd_t command = {0}; + sdmmchost_data_t data = {0}; + sdmmchost_transfer_t content = {0}; + status_t error; + + if ((((card->flags & (uint32_t)kMMC_SupportHighCapacityFlag) != 0U) && (blockSize != 512U)) || + (blockSize > card->blockSize) || (blockSize > card->host->maxBlockSize) || (0U != (blockSize % 4U))) + { + return kStatus_SDMMC_CardNotSupport; + } + + error = MMC_PollingCardStatusBusy(card, true, MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (kStatus_SDMMC_CardStatusIdle != error) + { + SDMMC_LOG("Error : read failed with wrong card status\r\n"); + return kStatus_SDMMC_PollingCardIdleFailed; + } + + data.blockSize = blockSize; + data.blockCount = blockCount; + data.rxData = (uint32_t *)(uint32_t)buffer; + data.enableAutoCommand12 = true; + command.index = (uint32_t)kSDMMC_ReadMultipleBlock; + if (data.blockCount == 1U) + { + command.index = (uint32_t)kSDMMC_ReadSingleBlock; + } + else + { + if (card->enablePreDefinedBlockCount) + { + data.enableAutoCommand12 = false; + /* If enabled the pre-define count read/write feature of the card, need to set block count firstly. */ + if (kStatus_Success != MMC_SetBlockCount(card, blockCount)) + { + return kStatus_SDMMC_SetBlockCountFailed; + } + } + } + command.argument = startBlock; + if (0U == (card->flags & (uint32_t)kMMC_SupportHighCapacityFlag)) + { + command.argument *= data.blockSize; + } + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = &data; + + /* should check tuning error during every transfer */ + error = MMC_Transfer(card, &content, 3U); + if (kStatus_Success != error) + { + return error; + } + + /* When host's AUTO_COMMAND12 feature isn't enabled and PRE_DEFINED_COUNT command isn't enabled in multiple + blocks transmission, sends STOP_TRANSMISSION command. */ + if ((blockCount > 1U) && (!(data.enableAutoCommand12)) && (!card->enablePreDefinedBlockCount)) + { + if (kStatus_Success != MMC_StopTransmission(card)) + { + return kStatus_SDMMC_StopTransmissionFailed; + } + } + + return kStatus_Success; +} + +static status_t MMC_Write( + mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) +{ + assert(card != NULL); + assert(buffer != NULL); + assert(blockCount != 0U); + assert(blockSize != 0U); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + sdmmchost_cmd_t command = {0}; + sdmmchost_data_t data = {0}; + sdmmchost_transfer_t content = {0}; + status_t error; + + /* Check address range */ + if ((((card->flags & (uint32_t)kMMC_SupportHighCapacityFlag) != 0U) && (blockSize != 512U)) || + (blockSize > card->blockSize) || (blockSize > card->host->maxBlockSize) || (0U != (blockSize % 4U))) + { + return kStatus_SDMMC_CardNotSupport; + } + + /* send CMD13 to make sure card is ready for data */ + error = MMC_PollingCardStatusBusy(card, true, MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (kStatus_SDMMC_CardStatusIdle != error) + { + SDMMC_LOG("Error : write card busy with wrong card status\r\n"); + return kStatus_SDMMC_PollingCardIdleFailed; + } + + data.blockSize = blockSize; + data.blockCount = blockCount; + data.txData = (const uint32_t *)(uint32_t)buffer; + data.enableAutoCommand12 = true; + + command.index = (uint32_t)kSDMMC_WriteMultipleBlock; + if (data.blockCount == 1U) + { + command.index = (uint32_t)kSDMMC_WriteSingleBlock; + } + else + { + if (card->enablePreDefinedBlockCount) + { + data.enableAutoCommand12 = false; + /* If enabled the pre-define count read/write featue of the card, need to set block count firstly */ + if (kStatus_Success != MMC_SetBlockCount(card, blockCount)) + { + return kStatus_SDMMC_SetBlockCountFailed; + } + } + } + command.argument = startBlock; + if (0U == (card->flags & (uint32_t)kMMC_SupportHighCapacityFlag)) + { + command.argument *= blockSize; + } + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = &data; + + /* should check tuning error during every transfer */ + error = MMC_Transfer(card, &content, 3U); + if (kStatus_Success != error) + { + return error; + } + + /* When host's AUTO_COMMAND12 feature isn't enabled and PRE_DEFINED_COUNT command isn't enabled in multiple + blocks transmission, sends STOP_TRANSMISSION command. */ + if ((blockCount > 1U) && (!(data.enableAutoCommand12)) && (!card->enablePreDefinedBlockCount)) + { + if (kStatus_Success != MMC_StopTransmission(card)) + { + return kStatus_SDMMC_StopTransmissionFailed; + } + } + + return kStatus_Success; +} + +static status_t MMC_ValidateOperationVoltage(mmc_card_t *card, uint32_t *opcode) +{ + status_t status = kStatus_Fail; + + if (card->hostVoltageWindowVCC == kMMC_VoltageWindow170to195) + { + if ((card->ocr & MMC_OCR_V170TO195_MASK) != 0U) + { + *opcode |= MMC_OCR_V170TO195_MASK; + status = kStatus_Success; + } + } + else if (card->hostVoltageWindowVCC == kMMC_VoltageWindows270to360) + { + if ((card->ocr & MMC_OCR_V270TO360_MASK) != 0U) + { + *opcode |= MMC_OCR_V270TO360_MASK; + status = kStatus_Success; + } + } + else + { + /* Intentional empty */ + } + + return status; +} + +static status_t mmccard_init(mmc_card_t *card) +{ + assert(card != NULL); + assert((card->hostVoltageWindowVCC != kMMC_VoltageWindowNone) && + (card->hostVoltageWindowVCC != kMMC_VoltageWindow120)); + assert(card->hostVoltageWindowVCCQ != kMMC_VoltageWindowNone); + + uint32_t opcode = 0U; + status_t error = kStatus_Success; + + if (!card->isHostReady) + { + return kStatus_SDMMC_HostNotReady; + } + /* set DATA bus width */ + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith1Bit); + /* Set clock to 400KHz. */ + card->busClock_Hz = SDMMCHOST_SetCardClock(card->host, SDMMC_CLOCK_400KHZ); + + error = MMC_GoIdle(card); + /* Send CMD0 to reset the bus */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_GoIdleFailed; + } + + /* Hand-shaking with card to validata the voltage range Host first sending its expected + information.*/ + error = MMC_SendOperationCondition(card, 0U); + if (kStatus_Success != error) + { + return kStatus_SDMMC_HandShakeOperationConditionFailed; + } + + error = MMC_ValidateOperationVoltage(card, &opcode); + if (kStatus_Success != error) + { + return kStatus_SDMMC_InvalidVoltage; + } + + /* Get host's access mode. */ + opcode |= (card->host->maxBlockSize >= FSL_SDMMC_DEFAULT_BLOCK_SIZE ? + (uint32_t)kMMC_AccessModeSector << MMC_OCR_ACCESS_MODE_SHIFT : + (uint32_t)kMMC_AccessModeByte << MMC_OCR_ACCESS_MODE_SHIFT); + + error = MMC_SendOperationCondition(card, opcode); + if (kStatus_Success != error) + { + return kStatus_SDMMC_HandShakeOperationConditionFailed; + } + + /* Get card CID */ + error = MMC_AllSendCid(card); + if (kStatus_Success != error) + { + return kStatus_SDMMC_AllSendCidFailed; + } + + error = MMC_SetRelativeAddress(card); + /* Set the card relative address */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_SetRelativeAddressFailed; + } + + error = MMC_SendCsd(card); + /* Get the CSD register content */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_SendCsdFailed; + } + + /* Set to maximum speed in normal mode. */ + MMC_SetMaxFrequency(card); + + /* Send CMD7 with the card's relative address to place the card in transfer state. Puts current selected card in + transfer state. */ + error = MMC_SelectCard(card, true); + if (kStatus_Success != error) + { + return kStatus_SDMMC_SelectCardFailed; + } + + /* Get Extended CSD register content. */ + error = MMC_SendExtendedCsd(card, NULL, 0U); + if (kStatus_Success != error) + { + return kStatus_SDMMC_SendExtendedCsdFailed; + } + + error = MMC_SetMaxEraseUnitSize(card); + /* Set to max erase unit size */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_EnableHighCapacityEraseFailed; + } + + error = MMC_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + /* set block size */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + error = MMC_SelectBusTiming(card); + /* switch to host support speed mode, then switch MMC data bus width and select power class */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + error = MMC_SetPowerClass(card); + /* switch power class */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_SetPowerClassFail; + } + + /* trying to enable the cache */ + (void)MMC_EnableCacheControl(card, true); + + /* Set card default to access non-boot partition */ + card->currentPartition = kMMC_AccessPartitionUserAera; + + return kStatus_Success; +} + +status_t MMC_CardInit(mmc_card_t *card) +{ + assert(card != NULL); + + status_t error = kStatus_Success; + /* create mutex lock */ + (void)SDMMC_OSAMutexCreate(&card->lock); + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + error = mmccard_init(card); + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +void MMC_CardDeinit(mmc_card_t *card) +{ + assert(card != NULL); + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + (void)MMC_SelectCard(card, false); + + (void)SDMMC_OSAMutexDestroy(&card->lock); +} + +status_t MMC_HostInit(mmc_card_t *card) +{ + assert(card != NULL); + + if (!card->isHostReady) + { + if (SDMMCHOST_Init(card->host) != kStatus_Success) + { + return kStatus_Fail; + } + } + + /* set the host status flag, after the card re-plug in, don't need init host again */ + card->isHostReady = true; + + return kStatus_Success; +} + +void MMC_HostDeinit(mmc_card_t *card) +{ + assert(card != NULL); + + SDMMCHOST_Deinit(card->host); + /* should re-init host */ + card->isHostReady = false; +} + +void MMC_HostReset(SDMMCHOST_CONFIG *host) +{ + SDMMCHOST_Reset(host); +} + +void MMC_HostDoReset(mmc_card_t *card) +{ + SDMMCHOST_Reset(card->host); +} + +void MMC_SetCardPower(mmc_card_t *card, bool enable) +{ + SDMMCHOST_SetCardPower(card->host, enable); + SDMMC_OSADelay(MMC_POWER_RESET_DELAY); +} + +status_t MMC_Init(mmc_card_t *card) +{ + assert(card != NULL); + + status_t error = kStatus_Success; + + if (!card->isHostReady) + { + if (MMC_HostInit(card) != kStatus_Success) + { + error = kStatus_SDMMC_HostNotReady; + } + } + else + { + /* reset the host */ + MMC_HostDoReset(card); + } + + if (error == kStatus_Success) + { + /* reset card power */ + MMC_SetCardPower(card, false); + MMC_SetCardPower(card, true); + + error = MMC_CardInit(card); + if (error != kStatus_Success) + { + error = kStatus_SDMMC_CardInitFailed; + } + } + + return error; +} + +void MMC_Deinit(mmc_card_t *card) +{ + assert(card != NULL); + + MMC_CardDeinit(card); + MMC_HostDeinit(card); +} + +bool MMC_CheckReadOnly(mmc_card_t *card) +{ + assert(card != NULL); + + return (((card->csd.flags & (uint16_t)kMMC_CsdPermanentWriteProtectFlag) != 0U) || + ((card->csd.flags & (uint16_t)kMMC_CsdTemporaryWriteProtectFlag) != 0U)); +} + +status_t MMC_SelectPartition(mmc_card_t *card, mmc_access_partition_t partitionNumber) +{ + assert(card != NULL); + + uint8_t bootConfig; + mmc_extended_csd_config_t extendedCsdconfig; + status_t error = kStatus_Success; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + bootConfig = card->extendedCsd.partitionConfig; + bootConfig &= ~(uint8_t)MMC_PARTITION_CONFIG_PARTITION_ACCESS_MASK; + bootConfig |= ((uint8_t)partitionNumber << MMC_PARTITION_CONFIG_PARTITION_ACCESS_SHIFT); + + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)kMMC_ExtendedCsdIndexPartitionConfig; + extendedCsdconfig.ByteValue = bootConfig; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != + MMC_SetExtendedCsdConfig(card, &extendedCsdconfig, (uint32_t)card->extendedCsd.partitionSwitchTimeout * 10U)) + { + error = kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + else + { + /* Save current configuration. */ + card->extendedCsd.partitionConfig = bootConfig; + card->currentPartition = partitionNumber; + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +status_t MMC_ReadBlocks(mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card != NULL); + assert(buffer != NULL); + assert(blockCount != 0U); + + uint32_t blockCountOneTime; /* The block count can be erased in one time sending READ_BLOCKS command. */ + uint32_t blockDone; /* The blocks has been read. */ + uint32_t blockLeft; /* Left blocks to be read. */ + uint8_t *nextBuffer; + bool dataAddrAlign = true; + uint8_t *alignBuffer = (uint8_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + status_t error = kStatus_Success; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + blockLeft = blockCount; + blockDone = 0U; + error = MMC_CheckBlockRange(card, startBlock, blockCount); + if (kStatus_Success != error) + { + error = kStatus_InvalidArgument; + } + else + { + while (blockLeft != 0U) + { + nextBuffer = (uint8_t *)((uint32_t)buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + if (!card->noInteralAlign && (!dataAddrAlign || ((((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U)) != 0U))) + { + blockLeft--; + blockCountOneTime = 1U; + (void)memset(alignBuffer, 0, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + dataAddrAlign = false; + } + else + { + if (blockLeft > card->host->maxBlockCount) + { + blockLeft = (blockLeft - card->host->maxBlockCount); + blockCountOneTime = card->host->maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + } + + error = MMC_Read(card, dataAddrAlign ? nextBuffer : (uint8_t *)alignBuffer, (startBlock + blockDone), + FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime); + if (kStatus_Success != error) + { + error = kStatus_SDMMC_TransferFailed; + break; + } + + blockDone += blockCountOneTime; + + if (!card->noInteralAlign && (!dataAddrAlign)) + { + (void)memcpy(nextBuffer, alignBuffer, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + } + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +status_t MMC_WriteBlocks(mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card != NULL); + assert(buffer != NULL); + assert(blockCount != 0U); + + uint32_t blockCountOneTime; + uint32_t blockLeft; + uint32_t blockDone; + const uint8_t *nextBuffer; + bool dataAddrAlign = true; + uint8_t *alignBuffer = (uint8_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + status_t error = kStatus_Success; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + blockLeft = blockCount; + blockDone = 0U; + + error = MMC_CheckBlockRange(card, startBlock, blockCount); + if (kStatus_Success != error) + { + error = kStatus_InvalidArgument; + } + else + { + while (blockLeft != 0U) + { + nextBuffer = (uint8_t *)((uint32_t)buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + if (!card->noInteralAlign && (!dataAddrAlign || (0U != (((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U))))) + { + blockLeft--; + blockCountOneTime = 1U; + (void)memcpy(alignBuffer, nextBuffer, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + dataAddrAlign = false; + } + else + { + if (blockLeft > card->host->maxBlockCount) + { + blockLeft = (blockLeft - card->host->maxBlockCount); + blockCountOneTime = card->host->maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + } + error = MMC_Write(card, dataAddrAlign ? nextBuffer : (uint8_t *)alignBuffer, (startBlock + blockDone), + FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime); + if (kStatus_Success != error) + { + error = kStatus_SDMMC_TransferFailed; + break; + } + + blockDone += blockCountOneTime; + if (!card->noInteralAlign && (!dataAddrAlign)) + { + (void)memset(alignBuffer, 0, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + } + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +status_t MMC_EnableCacheControl(mmc_card_t *card, bool enable) +{ + assert(card != NULL); + + uint8_t cacheCtrl = 0; + + mmc_extended_csd_config_t extendedCsdconfig; + + /* check the target driver strength support or not */ + if (card->extendedCsd.cacheSize == 0U) + { + SDMMC_LOG("The cache is not supported by the mmc device\r\n"); + return kStatus_SDMMC_NotSupportYet; + } + + if (enable) + { + cacheCtrl = MMC_CACHE_CONTROL_ENABLE; + } + + /* Switch to high speed timing. */ + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)kMMC_ExtendedCsdIndexCacheControl; + extendedCsdconfig.ByteValue = cacheCtrl; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig, 0U)) + { + SDMMC_LOG("cache enabled failed\r\n"); + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + + card->extendedCsd.cacheCtrl = cacheCtrl; + + return kStatus_Success; +} + +status_t MMC_FlushCache(mmc_card_t *card) +{ + assert(card != NULL); + + mmc_extended_csd_config_t extendedCsdconfig; + status_t error = kStatus_Success; + + /* check the target driver strength support or not */ + if ((card->extendedCsd.cacheSize == 0U) || (card->extendedCsd.cacheCtrl != MMC_CACHE_CONTROL_ENABLE)) + { + SDMMC_LOG("The cache is not supported or not enabled, please check\r\n"); + error = kStatus_SDMMC_NotSupportYet; + } + else + { + /* Switch to high speed timing. */ + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)kMMC_ExtendedCsdIndexFlushCache; + extendedCsdconfig.ByteValue = MMC_CACHE_TRIGGER_FLUSH; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig, 0U)) + { + SDMMC_LOG("cache flush failed\r\n"); + error = kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + } + + return error; +} + +status_t MMC_SetSleepAwake(mmc_card_t *card, mmc_sleep_awake_t state) +{ + assert(card != NULL); + status_t error = kStatus_Success; + + sdmmchost_cmd_t command = {0}; + sdmmchost_transfer_t content = {0}; + + if (card->extendedCsd.extendecCsdVersion <= + (uint32_t)kMMC_ExtendedCsdRevision13) /* V4.3 or above version card support boot mode */ + { + return kStatus_SDMMC_NotSupportYet; + } + + error = MMC_PollingCardStatusBusy(card, false, MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (kStatus_SDMMC_CardStatusIdle != error) + { + return kStatus_SDMMC_PollingCardIdleFailed; + } + + /* deselect the card before enter into sleep state */ + if (state == kMMC_Sleep) + { + if (MMC_SelectCard(card, false) != kStatus_Success) + { + return kStatus_SDMMC_DeselectCardFailed; + } + } + + command.index = (uint32_t)kMMC_SleepAwake; + command.argument = ((uint32_t)state << 15U) | (card->relativeAddress << 16U); + command.responseType = kCARD_ResponseTypeR1b; + + content.command = &command; + content.data = NULL; + + error = MMC_Transfer(card, &content, 0U); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Sleep awake timeout value 100ns * 2^sleepAwakeTimeout */ + error = MMC_PollingCardStatusBusy(card, false, (1UL << card->extendedCsd.sleepAwakeTimeout) / 10000U); + if (kStatus_SDMMC_CardStatusIdle != error) + { + return kStatus_SDMMC_PollingCardIdleFailed; + } + + /* select the card after wake up */ + if (state == kMMC_Awake) + { + if (MMC_SelectCard(card, true) != kStatus_Success) + { + return kStatus_SDMMC_SelectCardFailed; + } + } + + return kStatus_Success; +} + +static status_t MMC_Erase(mmc_card_t *card, uint32_t startGroupAddress, uint32_t endGroupAddress) +{ + sdmmchost_cmd_t command = {0}; + sdmmchost_transfer_t content = {0}; + status_t error = kStatus_Success; + + /* Set the start erase group address */ + command.index = (uint32_t)kMMC_EraseGroupStart; + command.argument = startGroupAddress; + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = NULL; + error = MMC_Transfer(card, &content, 0U); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Set the end erase group address */ + command.index = (uint32_t)kMMC_EraseGroupEnd; + command.argument = endGroupAddress; + + content.command = &command; + content.data = NULL; + error = MMC_Transfer(card, &content, 0U); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + /* Start the erase process */ + command.index = (uint32_t)kSDMMC_Erase; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = NULL; + error = MMC_Transfer(card, &content, 0U); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t MMC_EraseGroups(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup) +{ + assert(card != NULL); + + uint32_t startGroupAddress; + uint32_t endGroupAddress; + status_t error = kStatus_Success; + uint32_t eraseTimeout = MMC_CARD_ACCESS_WAIT_IDLE_TIMEOUT; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + error = MMC_CheckEraseGroupRange(card, startGroup, endGroup); + if (kStatus_Success != error) + { + error = kStatus_InvalidArgument; + } + else + { + error = MMC_PollingCardStatusBusy(card, true, 0U); + if (error != kStatus_SDMMC_CardStatusIdle) + { + error = kStatus_SDMMC_PollingCardIdleFailed; + } + } + + if (error == kStatus_SDMMC_CardStatusIdle) + { + /* Calculate the start group address and end group address */ + startGroupAddress = startGroup; + endGroupAddress = endGroup; + if ((card->flags & (uint32_t)kMMC_SupportHighCapacityFlag) != 0U) + { + /* The implementation of a higher than 2GB of density of memory will not be backwards compatible with the + lower densities.First of all the address argument for higher than 2GB of density of memory is changed to + be sector address (512B sectors) instead of byte address */ + startGroupAddress = (startGroupAddress * (card->eraseGroupBlocks)); + endGroupAddress = (endGroupAddress * (card->eraseGroupBlocks)); + } + else + { + /* The address unit is byte when card capacity is lower than 2GB */ + startGroupAddress = (startGroupAddress * (card->eraseGroupBlocks) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + endGroupAddress = (endGroupAddress * (card->eraseGroupBlocks) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + + error = MMC_Erase(card, startGroupAddress, endGroupAddress); + if (error == kStatus_Success) + { + if ((0U != (card->flags & (uint32_t)kMMC_SupportHighCapacityFlag)) && + (card->extendedCsd.highCapacityEraseTimeout != 0U)) + { + eraseTimeout = + (uint32_t)card->extendedCsd.highCapacityEraseTimeout * 300U * (endGroup - startGroup + 1U); + } + + error = MMC_PollingCardStatusBusy(card, true, eraseTimeout); + if (kStatus_SDMMC_CardStatusIdle != error) + { + error = kStatus_SDMMC_PollingCardIdleFailed; + } + else + { + error = kStatus_Success; + } + } + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +status_t MMC_SetBootConfigWP(mmc_card_t *card, uint8_t wp) +{ + assert(card != NULL); + + mmc_extended_csd_config_t extendedCsdconfig; + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)kMMC_ExtendedCsdIndexBootConfigWP; + extendedCsdconfig.ByteValue = wp; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig, 0U)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + + card->extendedCsd.bootConfigProtect = wp; + + return kStatus_Success; +} + +status_t MMC_SetBootPartitionWP(mmc_card_t *card, mmc_boot_partition_wp_t bootPartitionWP) +{ + assert(card != NULL); + + mmc_extended_csd_config_t extendedCsdconfig; + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)kMMC_ExtendedCsdIndexBootPartitionWP; + extendedCsdconfig.ByteValue = (uint8_t)bootPartitionWP; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig, 0U)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + + card->extendedCsd.bootPartitionWP = (uint8_t)bootPartitionWP; + + return kStatus_Success; +} + +status_t MMC_SetBootConfig(mmc_card_t *card, const mmc_boot_config_t *config) +{ + assert(card != NULL); + assert(config != NULL); + + uint8_t bootParameter; + uint8_t bootBusWidth = (uint8_t)config->bootDataBusWidth; + mmc_extended_csd_config_t extendedCsdconfig; + + if (card->extendedCsd.extendecCsdVersion <= + (uint32_t)kMMC_ExtendedCsdRevision13) /* V4.3 or above version card support boot mode */ + { + return kStatus_SDMMC_NotSupportYet; + } + + /* Set the BOOT_CONFIG field of Extended CSD */ + bootParameter = card->extendedCsd.partitionConfig; + bootParameter &= + ~((uint8_t)MMC_PARTITION_CONFIG_BOOT_ACK_MASK | (uint8_t)MMC_PARTITION_CONFIG_PARTITION_ENABLE_MASK); + bootParameter |= ((config->enableBootAck ? 1U : 0U) << MMC_PARTITION_CONFIG_BOOT_ACK_SHIFT); + bootParameter |= ((uint8_t)(config->bootPartition) << MMC_PARTITION_CONFIG_PARTITION_ENABLE_SHIFT); + + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)kMMC_ExtendedCsdIndexPartitionConfig; + extendedCsdconfig.ByteValue = bootParameter; + extendedCsdconfig.commandSet = kMMC_CommandSetStandard; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig, 0U)) + { + return kStatus_SDMMC_ConfigureExtendedCsdFailed; + } + + card->extendedCsd.partitionConfig = bootParameter; + + /* data bus remapping */ + if (bootBusWidth == (uint8_t)kMMC_DataBusWidth1bit) + { + bootBusWidth = 0U; + } + else if ((bootBusWidth == (uint8_t)kMMC_DataBusWidth4bit) || (bootBusWidth == (uint8_t)kMMC_DataBusWidth4bitDDR)) + { + bootBusWidth = 1U; + } + else + { + bootBusWidth = 2U; + } + + /*Set BOOT_BUS_CONDITIONS in Extended CSD */ + bootParameter = card->extendedCsd.bootDataBusConditions; + bootParameter &= (uint8_t) ~(MMC_BOOT_BUS_CONDITION_RESET_BUS_CONDITION_MASK | + MMC_BOOT_BUS_CONDITION_BUS_WIDTH_MASK | MMC_BOOT_BUS_CONDITION_BOOT_MODE_MASK); + bootParameter |= + (uint8_t)((config->retainBootbusCondition ? 1U : 0U) << MMC_BOOT_BUS_CONDITION_RESET_BUS_CONDITION_SHIFT); + bootParameter |= bootBusWidth << MMC_BOOT_BUS_CONDITION_BUS_WIDTH_SHIFT; + bootParameter |= ((uint8_t)(config->bootTimingMode) << MMC_BOOT_BUS_CONDITION_BOOT_MODE_SHIFT) & + MMC_BOOT_BUS_CONDITION_BOOT_MODE_MASK; + + extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; + extendedCsdconfig.ByteIndex = (uint8_t)kMMC_ExtendedCsdIndexBootBusConditions; + extendedCsdconfig.ByteValue = bootParameter; + if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig, 0U)) + { + return kStatus_SDMMC_ConfigureBootFailed; + } + + card->extendedCsd.bootDataBusConditions = bootParameter; + /* check and configure the boot config write protect */ + bootParameter = (uint8_t)config->pwrBootConfigProtection | (((uint8_t)config->premBootConfigProtection) << 4U); + if (bootParameter != (card->extendedCsd.bootConfigProtect)) + { + if (kStatus_Success != MMC_SetBootConfigWP(card, bootParameter)) + { + return kStatus_SDMMC_ConfigureBootFailed; + } + } + /* check and configure the boot partition write protect */ + if (card->extendedCsd.bootPartitionWP != (uint8_t)(config->bootPartitionWP)) + { + if (kStatus_Success != MMC_SetBootPartitionWP(card, config->bootPartitionWP)) + { + return kStatus_SDMMC_ConfigureBootFailed; + } + } + + return kStatus_Success; +} + +status_t MMC_StartBoot(mmc_card_t *card, + const mmc_boot_config_t *mmcConfig, + uint8_t *buffer, + sdmmchost_boot_config_t *hostConfig) +{ + assert(card != NULL); + assert(mmcConfig != NULL); + assert(buffer != NULL); + + sdmmchost_cmd_t command = {0}; + uint32_t tempClock = 0U; + + if (!card->isHostReady) + { + return kStatus_Fail; + } + + /* send card active */ + SDMMCHOST_SendCardActive(card->host); + /* enable MMC boot */ + SDMMCHOST_EnableBoot(card->host, true); + + if (mmcConfig->bootTimingMode == kMMC_BootModeSDRWithDefaultTiming) + { + /* Set clock to 400KHz. */ + tempClock = SDMMC_CLOCK_400KHZ; + } + else + { + /* Set clock to 52MHZ. */ + tempClock = MMC_CLOCK_52MHZ; + } + (void)SDMMCHOST_SetCardClock(card->host, tempClock); + + if (((card->host->capability & (uint32_t)kSDMMCHOST_SupportDDRMode) != 0U) && + (mmcConfig->bootTimingMode == kMMC_BootModeDDRTiming)) + { + /* enable DDR mode */ + SDMMCHOST_EnableDDRMode(card->host, true, 0U); + } + + /* data bus remapping */ + if (mmcConfig->bootDataBusWidth == kMMC_DataBusWidth1bit) + { + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith1Bit); + } + else if ((mmcConfig->bootDataBusWidth == kMMC_DataBusWidth4bit) || + (mmcConfig->bootDataBusWidth == kMMC_DataBusWidth4bitDDR)) + { + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith4Bit); + } + else + { + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith8Bit); + } + + if (kMMC_BootModeAlternative == mmcConfig->bootMode) + { + /* alternative boot mode */ + command.argument = 0xFFFFFFFAU; + } + + command.index = (uint32_t)kSDMMC_GoIdleState; + + /* should check tuning error during every transfer*/ + if (kStatus_Success != SDMMCHOST_StartBoot(card->host, hostConfig, &command, buffer)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t MMC_ReadBootData(mmc_card_t *card, uint8_t *buffer, sdmmchost_boot_config_t *hostConfig) +{ + assert(card != NULL); + assert(buffer != NULL); + + /* should check tuning error during every transfer*/ + if (kStatus_Success != SDMMCHOST_ReadBootData(card->host, hostConfig, buffer)) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t MMC_StopBoot(mmc_card_t *card, uint32_t bootMode) +{ + assert(card != NULL); + /* Disable boot mode */ + if ((uint32_t)kMMC_BootModeAlternative == bootMode) + { + /* Send CMD0 to reset the bus */ + if (kStatus_Success != MMC_GoIdle(card)) + { + return kStatus_SDMMC_GoIdleFailed; + } + } + /* disable MMC boot */ + SDMMCHOST_EnableBoot(card->host, false); + + return kStatus_Success; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/mmc/fsl_mmc.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/mmc/fsl_mmc.h new file mode 100644 index 0000000000..04fdd84879 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/mmc/fsl_mmc.h @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_MMC_H_ +#define _FSL_MMC_H_ + +#include "fsl_sdmmc_common.h" + +/*! + * @addtogroup mmccard MMC Card Driver + * @ingroup card + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Middleware mmc version. */ +#define FSL_MMC_DRIVER_VERSION (MAKE_VERSION(2U, 5U, 0U)) /*2.5.0*/ + +/*! @brief MMC card flags + * @anchor _mmc_card_flag + */ +enum +{ + kMMC_SupportHighSpeed26MHZFlag = (1U << 0U), /*!< Support high speed 26MHZ */ + kMMC_SupportHighSpeed52MHZFlag = (1U << 1U), /*!< Support high speed 52MHZ */ + kMMC_SupportHighSpeedDDR52MHZ180V300VFlag = (1 << 2U), /*!< ddr 52MHZ 1.8V or 3.0V */ + kMMC_SupportHighSpeedDDR52MHZ120VFlag = (1 << 3U), /*!< DDR 52MHZ 1.2V */ + kMMC_SupportHS200200MHZ180VFlag = (1 << 4U), /*!< HS200 ,200MHZ,1.8V */ + kMMC_SupportHS200200MHZ120VFlag = (1 << 5U), /*!< HS200, 200MHZ, 1.2V */ + kMMC_SupportHS400DDR200MHZ180VFlag = (1 << 6U), /*!< HS400, DDR, 200MHZ,1.8V */ + kMMC_SupportHS400DDR200MHZ120VFlag = (1 << 7U), /*!< HS400, DDR, 200MHZ,1.2V */ + kMMC_SupportHighCapacityFlag = (1U << 8U), /*!< Support high capacity */ + kMMC_SupportAlternateBootFlag = (1U << 9U), /*!< Support alternate boot */ + kMMC_SupportDDRBootFlag = (1U << 10U), /*!< support DDR boot flag*/ + kMMC_SupportHighSpeedBootFlag = (1U << 11U), /*!< support high speed boot flag */ + kMMC_SupportEnhanceHS400StrobeFlag = (1U << 12U), /*!< support enhance HS400 strobe */ +}; + +/*! @brief mmccard sleep/awake state */ +typedef enum _mmc_sleep_awake +{ + kMMC_Sleep = 1U, /*!< MMC card sleep */ + kMMC_Awake = 0U, /*!< MMC card awake */ +} mmc_sleep_awake_t; + +/*! @brief card io strength control */ +typedef void (*mmc_io_strength_t)(uint32_t busFreq); + +/*! @brief card user parameter */ +typedef struct _mmc_usr_param +{ + mmc_io_strength_t ioStrength; /*!< switch sd io strength */ + uint32_t maxFreq; /*!< board support maximum frequency */ + uint32_t capability; /*!< board capability flag */ +} mmc_usr_param_t; + +/*! + * @brief mmc card state + * + * Defines the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _mmc_card +{ + sdmmchost_t *host; /*!< Host information */ + mmc_usr_param_t usrParam; /*!< user parameter */ + + bool isHostReady; /*!< Use this flag to indicate if host re-init needed or not*/ + bool noInteralAlign; /*!< Use this flag to disable sdmmc align. If disabled, sdmmc will not make sure the + data buffer address is word align, otherwise all the transfer are aligned to low level driver. */ + uint32_t busClock_Hz; /*!< MMC bus clock united in Hz */ + uint32_t relativeAddress; /*!< Relative address of the card */ + bool enablePreDefinedBlockCount; /*!< Enable PRE-DEFINED block count when read/write */ + uint32_t flags; /*!< Capability flag in @ref _mmc_card_flag */ + + uint8_t internalBuffer[FSL_SDMMC_CARD_INTERNAL_BUFFER_SIZE]; /*!< raw buffer used for mmc driver internal */ + uint32_t ocr; /*!< Raw OCR content */ + mmc_cid_t cid; /*!< CID */ + mmc_csd_t csd; /*!< CSD */ + mmc_extended_csd_t extendedCsd; /*!< Extended CSD */ + uint32_t blockSize; /*!< Card block size */ + uint32_t userPartitionBlocks; /*!< Card total block number in user partition */ + uint32_t bootPartitionBlocks; /*!< Boot partition size united as block size */ + uint32_t eraseGroupBlocks; /*!< Erase group size united as block size */ + mmc_access_partition_t currentPartition; /*!< Current access partition */ + mmc_voltage_window_t hostVoltageWindowVCCQ; /*!< application must set this value according to board specific */ + mmc_voltage_window_t hostVoltageWindowVCC; /*!< application must set this value according to board specific */ + mmc_high_speed_timing_t busTiming; /*!< indicates the current work timing mode*/ + mmc_data_bus_width_t busWidth; /*!< indicates the current work bus width */ + sdmmc_osa_mutex_t lock; /*!< card access lock */ +} mmc_card_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name MMCCARD Function + * @{ + */ + +/*! + * @brief Initializes the MMC card and host. + * + * @param card Card descriptor. + * + * Thread safe function, please note that the function will create the mutex lock dynamically by default, + * so to avoid the mutex to be created redundantly, application must follow bellow sequence for card re-initialization: + * @code + MMC_Deinit(card); + MMC_Init(card); + * @endcode + * + * @retval #kStatus_SDMMC_HostNotReady Host is not ready. + * @retval #kStatus_SDMMC_GoIdleFailed Going idle failed. + * @retval #kStatus_SDMMC_HandShakeOperationConditionFailed Sending operation condition failed. + * @retval #kStatus_SDMMC_AllSendCidFailed Sending CID failed. + * @retval #kStatus_SDMMC_SetRelativeAddressFailed Setging relative address failed. + * @retval #kStatus_SDMMC_SendCsdFailed Sending CSD failed. + * @retval #kStatus_SDMMC_CardNotSupport Card not support. + * @retval #kStatus_SDMMC_SelectCardFailed Sending SELECT_CARD command failed. + * @retval #kStatus_SDMMC_SendExtendedCsdFailed Sending EXT_CSD failed. + * @retval #kStatus_SDMMC_SetDataBusWidthFailed Setting bus width failed. + * @retval #kStatus_SDMMC_SwitchBusTimingFailed Switching high speed failed. + * @retval #kStatus_SDMMC_SetCardBlockSizeFailed Setting card block size failed. + * @retval #kStatus_SDMMC_SetPowerClassFail Setting card power class failed. + * @retval #kStatus_Success Operation succeeded. + */ +status_t MMC_Init(mmc_card_t *card); + +/*! + * @brief Deinitializes the card and host. + * + * @note It is a thread safe function. + * + * @param card Card descriptor. + */ +void MMC_Deinit(mmc_card_t *card); + +/*! + * @brief Initializes the card. + * + * Thread safe function, please note that the function will create the mutex lock dynamically by default, + * so to avoid the mutex to be created redundantly, application must follow bellow sequence for card re-initialization: + * @code + MMC_CardDeinit(card); + MMC_CardInit(card); + * @endcode + * + * @param card Card descriptor. + * + * @retval #kStatus_SDMMC_HostNotReady Host is not ready. + * @retval #kStatus_SDMMC_GoIdleFailed Going idle failed. + * @retval #kStatus_SDMMC_HandShakeOperationConditionFailed Sending operation condition failed. + * @retval #kStatus_SDMMC_AllSendCidFailed Sending CID failed. + * @retval #kStatus_SDMMC_SetRelativeAddressFailed Setting relative address failed. + * @retval #kStatus_SDMMC_SendCsdFailed Sending CSD failed. + * @retval #kStatus_SDMMC_CardNotSupport Card not support. + * @retval #kStatus_SDMMC_SelectCardFailed Sending SELECT_CARD command failed. + * @retval #kStatus_SDMMC_SendExtendedCsdFailed Sending EXT_CSD failed. + * @retval #kStatus_SDMMC_SetDataBusWidthFailed Setting bus width failed. + * @retval #kStatus_SDMMC_SwitchBusTimingFailed Switching high speed failed. + * @retval #kStatus_SDMMC_SetCardBlockSizeFailed Setting card block size failed. + * @retval #kStatus_SDMMC_SetPowerClassFail Setting card power class failed. + * @retval #kStatus_Success Operation succeeded. + */ +status_t MMC_CardInit(mmc_card_t *card); + +/*! + * @brief Deinitializes the card. + * + * @note It is a thread safe function. + * + * @param card Card descriptor. + */ +void MMC_CardDeinit(mmc_card_t *card); + +/*! + * @brief initialize the host. + * + * This function deinitializes the specific host. + * + * @param card Card descriptor. + */ +status_t MMC_HostInit(mmc_card_t *card); + +/*! + * @brief Deinitializes the host. + * + * This function deinitializes the host. + * + * @param card Card descriptor. + */ +void MMC_HostDeinit(mmc_card_t *card); + +/*! + * @brief Resets the host. + * + * This function resets the specific host. + * + * @param card Card descriptor. + */ +void MMC_HostDoReset(mmc_card_t *card); + +/*! + * @brief Resets the host. + * + * @deprecated Do not use this function. It has been superceded by @ref MMC_HostDoReset. + * This function resets the specific host. + * + * @param host Host descriptor. + */ +void MMC_HostReset(SDMMCHOST_CONFIG *host); + +/*! + * @brief Sets card power. + * + * @param card Card descriptor. + * @param enable True is powering on, false is powering off. + */ +void MMC_SetCardPower(mmc_card_t *card, bool enable); + +/*! + * @brief Checks if the card is read-only. + * + * @param card Card descriptor. + * @retval true Card is read only. + * @retval false Card isn't read only. + */ +bool MMC_CheckReadOnly(mmc_card_t *card); + +/*! + * @brief Reads data blocks from the card. + * + * @note It is a thread safe function. + * + * @param card Card descriptor. + * @param buffer The buffer to save data. + * @param startBlock The start block index. + * @param blockCount The number of blocks to read. + * @retval #kStatus_InvalidArgument Invalid argument. + * @retval #kStatus_SDMMC_CardNotSupport Card not support. + * @retval #kStatus_SDMMC_SetBlockCountFailed Setting block count failed. + * @retval #kStatus_SDMMC_TransferFailed Transfer failed. + * @retval #kStatus_SDMMC_StopTransmissionFailed Stopping transmission failed. + * @retval #kStatus_Success Operation succeeded. + */ +status_t MMC_ReadBlocks(mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Writes data blocks to the card. + * + * @note + * 1. It is a thread safe function. + * 2. It is an async write function which means that the card status may still be busy after the function returns. + * Application can call function MMC_PollingCardStatusBusy to wait for the card status to be idle after the write + * operation. + * + * @param card Card descriptor. + * @param buffer The buffer to save data blocks. + * @param startBlock Start block number to write. + * @param blockCount Block count. + * @retval #kStatus_InvalidArgument Invalid argument. + * @retval #kStatus_SDMMC_NotSupportYet Not support now. + * @retval #kStatus_SDMMC_SetBlockCountFailed Setting block count failed. + * @retval #kStatus_SDMMC_WaitWriteCompleteFailed Sending status failed. + * @retval #kStatus_SDMMC_TransferFailed Transfer failed. + * @retval #kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval #kStatus_Success Operation succeeded. + */ +status_t MMC_WriteBlocks(mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Erases groups of the card. + * + * The erase command is best used to erase the entire device or a partition. + * Erase group is the smallest erase unit in MMC card. The erase range is [startGroup, endGroup]. + * + * @note + * 1. It is a thread safe function. + * 2. This function always polls card busy status according to the timeout value defined in the card register after + * all the erase command sent out. + * + * @param card Card descriptor. + * @param startGroup Start group number. + * @param endGroup End group number. + * @retval #kStatus_InvalidArgument Invalid argument. + * @retval #kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval #kStatus_SDMMC_TransferFailed Transfer failed. + * @retval #kStatus_Success Operation succeeded. + */ +status_t MMC_EraseGroups(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup); + +/*! + * @brief Selects the partition to access. + * + * @note It is a thread safe function. + * + * @param card Card descriptor. + * @param partitionNumber The partition number. + * @retval #kStatus_SDMMC_ConfigureExtendedCsdFailed Configuring EXT_CSD failed. + * @retval #kStatus_Success Operation succeeded. + */ +status_t MMC_SelectPartition(mmc_card_t *card, mmc_access_partition_t partitionNumber); + +/*! + * @brief Configures the boot activity of the card. + * + * @param card Card descriptor. + * @param config Boot configuration structure. + * @retval #kStatus_SDMMC_NotSupportYet Not support now. + * @retval #kStatus_SDMMC_ConfigureExtendedCsdFailed Configuring EXT_CSD failed. + * @retval #kStatus_SDMMC_ConfigureBootFailed Configuring boot failed. + * @retval #kStatus_Success Operation succeeded. + */ +status_t MMC_SetBootConfig(mmc_card_t *card, const mmc_boot_config_t *config); + +/*! + * @brief MMC card start boot. + * + * @param card Card descriptor. + * @param mmcConfig The mmc Boot configuration structure. + * @param buffer Address to receive data. + * @param hostConfig Host boot configurations. + * @retval #kStatus_Fail Failed. + * @retval #kStatus_SDMMC_TransferFailed Transfer failed. + * @retval #kStatus_SDMMC_GoIdleFailed Resetting card failed. + * @retval #kStatus_Success Operation succeeded. + */ +status_t MMC_StartBoot(mmc_card_t *card, + const mmc_boot_config_t *mmcConfig, + uint8_t *buffer, + sdmmchost_boot_config_t *hostConfig); + +/*! + * @brief MMC card set boot configuration write protect. + * + * @param card Card descriptor. + * @param wp Write protect value. + */ +status_t MMC_SetBootConfigWP(mmc_card_t *card, uint8_t wp); + +/*! + * @brief MMC card continuous read boot data. + * + * @param card Card descriptor. + * @param buffer Buffer address. + * @param hostConfig Host boot configurations. + */ +status_t MMC_ReadBootData(mmc_card_t *card, uint8_t *buffer, sdmmchost_boot_config_t *hostConfig); + +/*! + * @brief MMC card stop boot mode. + * + * @param card Card descriptor. + * @param bootMode Boot mode. + */ +status_t MMC_StopBoot(mmc_card_t *card, uint32_t bootMode); + +/*! + * @brief MMC card set boot partition write protect. + * + * @param card Card descriptor. + * @param bootPartitionWP Boot partition write protect value. + */ +status_t MMC_SetBootPartitionWP(mmc_card_t *card, mmc_boot_partition_wp_t bootPartitionWP); + +/*! + * @brief MMC card cache control function. + * + * The mmc device's cache is enabled by the driver by default. + * The cache should in typical case reduce the access time (compared to an access to the main nonvolatile storage) for + * both write and read. + * + * @param card Card descriptor. + * @param enable True is enabling the cache, false is disabling the cache. + */ +status_t MMC_EnableCacheControl(mmc_card_t *card, bool enable); + +/*! + * @brief MMC card cache flush function. + * + * A Flush operation refers to the requirement, from the host to the device, to write the cached data to the nonvolatile + * memory. Prior to a flush, the device may autonomously write data to the nonvolatile memory, but after the flush + * operation all data in the volatile area must be written to nonvolatile memory. There is no requirement for flush due + * to switching between the partitions. (Note: This also implies that the cache data shall not be lost when switching + * between partitions). Cached data may be lost in SLEEP state, so host should flush the cache before placing the device + * into SLEEP state. + * + * @param card Card descriptor. + */ +status_t MMC_FlushCache(mmc_card_t *card); + +/*! + * @brief MMC sets card sleep awake state. + * + * The Sleep/Awake command is used to initiate the state transition between Standby state and Sleep state. + * The memory device indicates the transition phase busy by pulling down the DAT0 line. + * The Sleep/Standby state is reached when the memory device stops pulling down the DAT0 line, then the function + * returns. + * + * @param card Card descriptor. + * @param state The sleep/awake command argument, refer to @ref mmc_sleep_awake_t. + * + * @retval kStatus_SDMMC_NotSupportYet Indicates the memory device doesn't support the Sleep/Awake command. + * @retval kStatus_SDMMC_TransferFailed Indicates command transferred fail. + * @retval kStatus_SDMMC_PollingCardIdleFailed Indicates polling DAT0 busy timeout. + * @retval kStatus_SDMMC_DeselectCardFailed Indicates deselect card command failed. + * @retval kStatus_SDMMC_SelectCardFailed Indicates select card command failed. + * @retval kStatus_Success Indicates the card state switched successfully. + */ +status_t MMC_SetSleepAwake(mmc_card_t *card, mmc_sleep_awake_t state); + +/*! + * @brief Polling card idle status. + * + * This function can be used to poll the status from busy to idle, the function will return with the card + * status being idle or timeout or command failed. + * + * @param card Card descriptor. + * @param checkStatus True is send CMD and read DAT0 status to check card status, false is read DAT0 status only. + * @param timeoutMs Polling card status timeout value. + * + * @retval kStatus_SDMMC_CardStatusIdle Card is idle. + * @retval kStatus_SDMMC_CardStatusBusy Card is busy. + * @retval kStatus_SDMMC_TransferFailed Command tranfer failed. + * @retval kStatus_SDMMC_SwitchFailed Status command reports switch error. + */ +status_t MMC_PollingCardStatusBusy(mmc_card_t *card, bool checkStatus, uint32_t timeoutMs); + +/* @} */ +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* _FSL_MMC_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/osa/fsl_sdmmc_osa.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/osa/fsl_sdmmc_osa.c new file mode 100644 index 0000000000..4730bb02e8 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/osa/fsl_sdmmc_osa.c @@ -0,0 +1,275 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sdmmc_osa.h" + +/******************************************************************************* + * Definitons + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ + +/******************************************************************************* + * Variables + ******************************************************************************/ + +/******************************************************************************* + * Code + ******************************************************************************/ +/*! + * brief Initialize OSA. + */ +void SDMMC_OSAInit(void) +{ + /* Intentional empty */ +} + +/*! + * brief OSA Create event. + * param event handle. + * retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAEventCreate(void *eventHandle) +{ + assert(eventHandle != NULL); + +#if defined(SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE) && SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE + (void)OSA_SemaphoreCreate(&(((sdmmc_osa_event_t *)eventHandle)->handle), 0U); +#else + (void)OSA_EventCreate(&(((sdmmc_osa_event_t *)eventHandle)->handle), true); +#endif + + return kStatus_Success; +} + +/*! + * brief Wait event. + * + * param eventHandle The event type + * param eventType Timeout time in milliseconds. + * param timeoutMilliseconds timeout value in ms. + * param event event flags. + * retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAEventWait(void *eventHandle, uint32_t eventType, uint32_t timeoutMilliseconds, uint32_t *event) +{ + assert(eventHandle != NULL); + + osa_status_t status = KOSA_StatusError; + +#if defined(SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE) && SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE + while (true) + { + status = OSA_SemaphoreWait(&(((sdmmc_osa_event_t *)eventHandle)->handle), timeoutMilliseconds); + if (KOSA_StatusTimeout == status) + { + break; + } + + if (KOSA_StatusSuccess == status) + { + (void)SDMMC_OSAEventGet(eventHandle, eventType, event); + if ((*event & eventType) != 0U) + { + return kStatus_Success; + } + } + } + +#else + while (true) + { + status = OSA_EventWait(&(((sdmmc_osa_event_t *)eventHandle)->handle), eventType, 0, timeoutMilliseconds, event); + if ((KOSA_StatusSuccess == status) || (KOSA_StatusTimeout == status)) + { + break; + } + } + + if (KOSA_StatusSuccess == status) + { + return kStatus_Success; + } +#endif + + return kStatus_Fail; +} + +/*! + * brief set event. + * param event event handle. + * param eventType The event type + * retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAEventSet(void *eventHandle, uint32_t eventType) +{ + assert(eventHandle != NULL); + +#if defined(SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE) && SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE + OSA_SR_ALLOC(); + OSA_ENTER_CRITICAL(); + ((sdmmc_osa_event_t *)eventHandle)->eventFlag |= eventType; + OSA_EXIT_CRITICAL(); + + (void)OSA_SemaphorePost(&(((sdmmc_osa_event_t *)eventHandle)->handle)); +#else + (void)OSA_EventSet(&(((sdmmc_osa_event_t *)eventHandle)->handle), eventType); +#endif + + return kStatus_Success; +} + +/*! + * brief Get event flag. + * param eventHandle event handle. + * param eventType The event type + * param flag pointer to store event value. + * retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAEventGet(void *eventHandle, uint32_t eventType, uint32_t *flag) +{ + assert(eventHandle != NULL); + assert(flag != NULL); + +#if defined(SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE) && SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE + *flag = ((sdmmc_osa_event_t *)eventHandle)->eventFlag; +#else + (void)OSA_EventGet(&(((sdmmc_osa_event_t *)eventHandle)->handle), eventType, flag); +#endif + + return kStatus_Success; +} + +/*! + * brief clear event flag. + * param eventHandle event handle. + * param eventType The event type + * retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAEventClear(void *eventHandle, uint32_t eventType) +{ + assert(eventHandle != NULL); + +#if defined(SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE) && SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE + OSA_SR_ALLOC(); + OSA_ENTER_CRITICAL(); + ((sdmmc_osa_event_t *)eventHandle)->eventFlag &= ~eventType; + OSA_EXIT_CRITICAL(); +#else + (void)OSA_EventClear(&(((sdmmc_osa_event_t *)eventHandle)->handle), eventType); +#endif + + return kStatus_Success; +} + +/*! + * brief Delete event. + * param event The event handle. + */ +status_t SDMMC_OSAEventDestroy(void *eventHandle) +{ + assert(eventHandle != NULL); + +#if defined(SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE) && SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE + (void)OSA_SemaphoreDestroy(&(((sdmmc_osa_event_t *)eventHandle)->handle)); +#else + (void)OSA_EventDestroy(&(((sdmmc_osa_event_t *)eventHandle)->handle)); +#endif + + return kStatus_Success; +} + +/*! + * brief Create a mutex. + * param mutexHandle mutex handle. + * retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAMutexCreate(void *mutexHandle) +{ + assert(mutexHandle != NULL); + + (void)OSA_MutexCreate(&((sdmmc_osa_mutex_t *)mutexHandle)->handle); + + return kStatus_Success; +} + +/*! + * brief set event. + * param mutexHandle mutex handle. + * param millisec The maximum number of milliseconds to wait for the mutex. + * If the mutex is locked, Pass the value osaWaitForever_c will + * wait indefinitely, pass 0 will return KOSA_StatusTimeout + * immediately. + * retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAMutexLock(void *mutexHandle, uint32_t millisec) +{ + assert(mutexHandle != NULL); + + (void)OSA_MutexLock(&((sdmmc_osa_mutex_t *)mutexHandle)->handle, millisec); + + return kStatus_Success; +} + +/*! + * brief Get event flag. + * param mutexHandle mutex handle. + * retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAMutexUnlock(void *mutexHandle) +{ + assert(mutexHandle != NULL); + + (void)OSA_MutexUnlock(&((sdmmc_osa_mutex_t *)mutexHandle)->handle); + + return kStatus_Success; +} + +/*! + * brief Delete mutex. + * param mutexHandle The mutex handle. + */ +status_t SDMMC_OSAMutexDestroy(void *mutexHandle) +{ + assert(mutexHandle != NULL); + + (void)OSA_MutexDestroy(&((sdmmc_osa_mutex_t *)mutexHandle)->handle); + + return kStatus_Success; +} + +/*! + * brief sdmmc delay. + * param milliseconds time to delay + */ +void SDMMC_OSADelay(uint32_t milliseconds) +{ +#if (defined FSL_OSA_BM_TIMER_CONFIG) && (FSL_OSA_BM_TIMER_CONFIG == FSL_OSA_BM_TIMER_NONE) + SDK_DelayAtLeastUs(milliseconds * 1000U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); +#else + OSA_TimeDelay(milliseconds); +#endif +} + +/*! + * brief sdmmc delay us. + * param microseconds time to delay + * return actual delayed microseconds + */ +uint32_t SDMMC_OSADelayUs(uint32_t microseconds) +{ +#if (defined FSL_OSA_BM_TIMER_CONFIG) && (FSL_OSA_BM_TIMER_CONFIG == FSL_OSA_BM_TIMER_NONE) + SDK_DelayAtLeastUs(microseconds, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + return microseconds; +#else + uint32_t milliseconds = microseconds / 1000U + ((microseconds % 1000U) == 0U ? 0U : 1U); + OSA_TimeDelay(milliseconds); + return milliseconds * 1000U; +#endif +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/osa/fsl_sdmmc_osa.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/osa/fsl_sdmmc_osa.h new file mode 100644 index 0000000000..2d9101ad8d --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/osa/fsl_sdmmc_osa.h @@ -0,0 +1,170 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SDMMC_OSA_H_ +#define _FSL_SDMMC_OSA_H_ + +#include "fsl_common.h" +#include "fsl_os_abstraction.h" + +/*! + * @addtogroup sdmmc_osa SDMMC OSA + * @ingroup card + * @{ + */ +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*!@brief transfer event */ +#define SDMMC_OSA_EVENT_TRANSFER_CMD_SUCCESS (1UL << 0U) +#define SDMMC_OSA_EVENT_TRANSFER_CMD_FAIL (1UL << 1U) +#define SDMMC_OSA_EVENT_TRANSFER_DATA_SUCCESS (1UL << 2U) +#define SDMMC_OSA_EVENT_TRANSFER_DATA_FAIL (1UL << 3U) +#define SDMMC_OSA_EVENT_TRANSFER_DMA_COMPLETE (1UL << 4U) + +/*!@brief card detect event, start from index 8 */ +#define SDMMC_OSA_EVENT_CARD_INSERTED (1UL << 8U) +#define SDMMC_OSA_EVENT_CARD_REMOVED (1UL << 9U) + +/*!@brief enable semphore by default */ +#ifndef SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE +#define SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE 1 +#endif + +/*!@brief sdmmc osa event */ +typedef struct _sdmmc_osa_event +{ +#if defined(SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE) && SDMMC_OSA_POLLING_EVENT_BY_SEMPHORE + volatile uint32_t eventFlag; + OSA_SEMAPHORE_HANDLE_DEFINE(handle); +#else + OSA_EVENT_HANDLE_DEFINE(handle); +#endif +} sdmmc_osa_event_t; + +/*!@brief sdmmc osa mutex */ +typedef struct _sdmmc_osa_mutex +{ + OSA_MUTEX_HANDLE_DEFINE(handle); +} sdmmc_osa_mutex_t; +/******************************************************************************* + * API + ******************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name sdmmc osa Function + * @{ + */ + +/*! + * @brief Initialize OSA. + */ +void SDMMC_OSAInit(void); + +/*! + * @brief OSA Create event. + * @param eventHandle event handle. + * @retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAEventCreate(void *eventHandle); + +/*! + * @brief Wait event. + * + * @param eventHandle The event type + * @param eventType Timeout time in milliseconds. + * @param timeoutMilliseconds timeout value in ms. + * @param event event flags. + * @retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAEventWait(void *eventHandle, uint32_t eventType, uint32_t timeoutMilliseconds, uint32_t *event); + +/*! + * @brief set event. + * @param eventHandle event handle. + * @param eventType The event type + * @retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAEventSet(void *eventHandle, uint32_t eventType); + +/*! + * @brief Get event flag. + * @param eventHandle event handle. + * @param eventType event type. + * @param flag pointer to store event value. + * @retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAEventGet(void *eventHandle, uint32_t eventType, uint32_t *flag); + +/*! + * @brief clear event flag. + * @param eventHandle event handle. + * @param eventType The event type + * @retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAEventClear(void *eventHandle, uint32_t eventType); + +/*! + * @brief Delete event. + * @param eventHandle The event handle. + */ +status_t SDMMC_OSAEventDestroy(void *eventHandle); + +/*! + * @brief Create a mutex. + * @param mutexHandle mutex handle. + * @retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAMutexCreate(void *mutexHandle); + +/*! + * @brief set event. + * @param mutexHandle mutex handle. + * @param millisec The maximum number of milliseconds to wait for the mutex. + * If the mutex is locked, Pass the value osaWaitForever_c will + * wait indefinitely, pass 0 will return KOSA_StatusTimeout + * immediately. + * @retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAMutexLock(void *mutexHandle, uint32_t millisec); + +/*! + * @brief Get event flag. + * @param mutexHandle mutex handle. + * @retval kStatus_Fail or kStatus_Success. + */ +status_t SDMMC_OSAMutexUnlock(void *mutexHandle); + +/*! + * @brief Delete mutex. + * @param mutexHandle The mutex handle. + */ +status_t SDMMC_OSAMutexDestroy(void *mutexHandle); + +/*! + * @brief sdmmc delay. + * @param milliseconds time to delay + */ +void SDMMC_OSADelay(uint32_t milliseconds); + +/*! + * @brief sdmmc delay us. + * @param microseconds time to delay + * @return actual delayed microseconds + */ +uint32_t SDMMC_OSADelayUs(uint32_t microseconds); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/* @} */ +#endif /* _FSL_SDMMC_OSA_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/fsl_sdmmc_event.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/fsl_sdmmc_event.h deleted file mode 100644 index de5a8f9463..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/fsl_sdmmc_event.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_SDMMC_EVENT_H_ -#define _FSL_SDMMC_EVENT_H_ - -#include "fsl_common.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief Event type */ -typedef enum _sdmmc_event -{ - kSDMMCEVENT_TransferComplete = 0U, /*!< Transfer complete event */ - kSDMMCEVENT_CardDetect = 1U, /*!< Card detect event */ -} sdmmc_event_t; - -/******************************************************************************* - * API - ******************************************************************************/ -#if defined(__cplusplus) -extern "C" { -#endif - -/*! - * @name Event Function - * @{ - */ - -/*! - * @brief Initialize timer to implement wait event timeout. - */ -void SDMMCEVENT_InitTimer(void); - -/* Callback function for SDHC */ - -/*! - * @brief Create event. - * @param eventType The event type - * @retval true Create event successfully. - * @retval false Create event failed. - */ -bool SDMMCEVENT_Create(sdmmc_event_t eventType); - -/*! - * @brief Wait event. - * - * @param eventType The event type - * @param timeoutMilliseconds Timeout time in milliseconds. - * @retval true Wait event successfully. - * @retval false Wait event failed. - */ -bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds); - -/*! - * @brief Notify event. - * @param eventType The event type - * @retval true Notify event successfully. - * @retval false Notify event failed. - */ -bool SDMMCEVENT_Notify(sdmmc_event_t eventType); - -/*! - * @brief Delete event. - * @param eventType The event type - */ -void SDMMCEVENT_Delete(sdmmc_event_t eventType); - -/*! - * @brief sdmmc delay. - * @param milliseconds time to delay - */ -void SDMMCEVENT_Delay(uint32_t milliseconds); - -/* @} */ - -#if defined(__cplusplus) -} -#endif - -#endif /* _FSL_SDMMC_EVENT_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_event.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_event.c deleted file mode 100644 index 4a01760e30..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_event.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include "FreeRTOS.h" -#include "event_groups.h" -#include "fsl_sdmmc_event.h" -#include "semphr.h" - -/******************************************************************************* - * Definitons - ******************************************************************************/ -/*! @brief Convert the milliseconds to ticks in FreeRTOS. */ -#define MSEC_TO_TICK(msec) \ - (((uint32_t)(msec) + 500uL / (uint32_t)configTICK_RATE_HZ) * (uint32_t)configTICK_RATE_HZ / 1000uL) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get event instance. - * @param eventType The event type - * @return The event instance's pointer. - */ -static SemaphoreHandle_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Transfer complete event. */ -static SemaphoreHandle_t g_eventTransferComplete; -/*! @brief Card detect event. */ -static SemaphoreHandle_t g_eventCardDetect; - -/******************************************************************************* - * Code - ******************************************************************************/ -static SemaphoreHandle_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType) -{ - SemaphoreHandle_t *event; - - switch (eventType) - { - case kSDMMCEVENT_TransferComplete: - event = &g_eventTransferComplete; - break; - case kSDMMCEVENT_CardDetect: - event = &g_eventCardDetect; - break; - default: - event = NULL; - break; - } - - return event; -} - -bool SDMMCEVENT_Create(sdmmc_event_t eventType) -{ - SemaphoreHandle_t *event = SDMMCEVENT_GetInstance(eventType); - - if (event) - { - *event = xSemaphoreCreateBinary(); - if (*event == NULL) - { - return false; - } - - return true; - } - else - { - return false; - } -} - -bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds) -{ - uint32_t timeoutTicks; - SemaphoreHandle_t *event = SDMMCEVENT_GetInstance(eventType); - - if (timeoutMilliseconds && event && (*event != 0U)) - { - if (timeoutMilliseconds == ~0U) - { - timeoutTicks = portMAX_DELAY; - } - else - { - timeoutTicks = MSEC_TO_TICK(timeoutMilliseconds); - } - if (xSemaphoreTake(*event, timeoutTicks) == pdFALSE) - { - return false; /* timeout */ - } - else - { - return true; /* event taken */ - } - } - else - { - return false; - } -} - -bool SDMMCEVENT_Notify(sdmmc_event_t eventType) -{ - SemaphoreHandle_t *event = SDMMCEVENT_GetInstance(eventType); - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - BaseType_t xResult = pdFAIL; - - if (event && (*event != 0U)) - { - xResult = xSemaphoreGiveFromISR(*event, &xHigherPriorityTaskWoken); - if (xResult != pdFAIL) - { - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); - return true; - } - else - { - return false; - } - } - else - { - return false; - } -} - -void SDMMCEVENT_Delete(sdmmc_event_t eventType) -{ - SemaphoreHandle_t *event = SDMMCEVENT_GetInstance(eventType); - - if (event && (*event != 0U)) - { - vSemaphoreDelete(*event); - } -} - -void SDMMCEVENT_Delay(uint32_t milliseconds) -{ - vTaskDelay(MSEC_TO_TICK(milliseconds)); -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_host.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_host.c deleted file mode 100644 index c499b2c6de..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/freertos/fsl_sdmmc_host.c +++ /dev/null @@ -1,296 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sdmmc_host.h" -#include "fsl_sdmmc_event.h" -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief SDMMCHOST detect card insert status by host controller. - * @param base host base address. - * @param userData user can register a application card insert callback through userData. - */ -static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, void *userData); - -/*! - * @brief SDMMCHOST detect card remove status by host controller. - * @param base host base address. - * @param userData user can register a application card insert callback through userData. - */ -static void SDMMCHOST_DetectCardRemoveByHost(SDMMCHOST_TYPE *base, void *userData); - -/*! - * @brief SDMMCHOST transfer function. - * @param base host base address. - * @param content transfer configurations. - */ -static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content); - -/*! - * @brief SDMMCHOST transfer complete callback. - * @param base host base address. - * @param handle host handle. - * @param status interrupt status. - * @param userData user data. - */ -static void SDMMCHOST_TransferCompleteCallback(SDMMCHOST_TYPE *base, void *handle, status_t status, void *userData); -/*! - * @brief card detect deinit function. - */ -static void SDMMCHOST_CardDetectDeinit(void); - -/*! - * @brief card detect deinit function. - * @param host base address. - * @param host detect card configuration. - */ -static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd); - -/******************************************************************************* - * Variables - ******************************************************************************/ -static sdif_handle_t s_sdifHandle; -static uint32_t s_sdifDmaTable[SDIF_DMA_TABLE_WORDS]; -static volatile bool s_sdifTransferSuccessFlag = true; -/*! @brief Card detect flag. */ -static volatile bool s_sdInsertedFlag = false; -/******************************************************************************* - * Code - ******************************************************************************/ -static void SDMMCHOST_TransferCompleteCallback(SDMMCHOST_TYPE *base, void *handle, status_t status, void *userData) -{ - /* receive the right status, notify the event */ - if (status == kStatus_Success) - { - s_sdifTransferSuccessFlag = true; - } - else - { - s_sdifTransferSuccessFlag = false; - } - SDMMCEVENT_Notify(kSDMMCEVENT_TransferComplete); -} - -static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content) -{ - status_t error = kStatus_Success; - - sdif_dma_config_t dmaConfig; - - memset(s_sdifDmaTable, 0, sizeof(s_sdifDmaTable)); - memset(&dmaConfig, 0, sizeof(dmaConfig)); - - /* user DMA mode transfer data */ - if (content->data != NULL) - { - dmaConfig.enableFixBurstLen = false; - dmaConfig.mode = kSDIF_DualDMAMode; - dmaConfig.dmaDesBufferStartAddr = s_sdifDmaTable; - dmaConfig.dmaDesBufferLen = SDIF_DMA_TABLE_WORDS; - dmaConfig.dmaDesSkipLen = 0U; - } - - do - { - error = SDIF_TransferNonBlocking(base, &s_sdifHandle, &dmaConfig, content); - } while (error == kStatus_SDIF_SyncCmdTimeout); - - if ((error != kStatus_Success) || - (false == SDMMCEVENT_Wait(kSDMMCEVENT_TransferComplete, SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT)) || - (!s_sdifTransferSuccessFlag)) - { - error = kStatus_Fail; - } - - return error; -} - -static void SDMMCHOST_DetectCardInsertByHost(SDIF_Type *base, void *userData) -{ - s_sdInsertedFlag = true; - SDMMCEVENT_Notify(kSDMMCEVENT_CardDetect); - /* application callback */ - if (userData && (((sdmmhostcard_usr_param_t *)userData)->cd) && - ((sdmmhostcard_usr_param_t *)userData)->cd->cardInserted) - { - ((sdmmhostcard_usr_param_t *)userData) - ->cd->cardInserted(true, ((sdmmhostcard_usr_param_t *)userData)->cd->userData); - } -} - -static void SDMMCHOST_DetectCardRemoveByHost(SDIF_Type *base, void *userData) -{ - s_sdInsertedFlag = false; - /* application callback */ - if (userData && (((sdmmhostcard_usr_param_t *)userData)->cd) && - ((sdmmhostcard_usr_param_t *)userData)->cd->cardRemoved) - { - ((sdmmhostcard_usr_param_t *)userData) - ->cd->cardRemoved(false, ((sdmmhostcard_usr_param_t *)userData)->cd->userData); - } -} - -static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd) -{ - sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByHostCD; - - if (cd != NULL) - { - cdType = cd->cdType; - } - - /* for interrupt case, only kSDMMCHOST_DetectCardByHostCD can generate interrupt, so implement it only */ - if (cdType != kSDMMCHOST_DetectCardByHostCD) - { - return kStatus_Fail; - } - - if (!SDMMCEVENT_Create(kSDMMCEVENT_CardDetect)) - { - return kStatus_Fail; - } - /* enable the card detect interrupt */ - SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base); - /* check if card is inserted */ - if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base, false)) - { - s_sdInsertedFlag = true; - /* application callback */ - if (cd && cd->cardInserted) - { - cd->cardInserted(true, cd->userData); - } - } - - return kStatus_Success; -} - -static void SDMMCHOST_CardDetectDeinit(void) -{ - SDMMCEVENT_Delete(kSDMMCEVENT_CardDetect); - s_sdInsertedFlag = false; -} - -void SDMMCHOST_Delay(uint32_t milliseconds) -{ - SDMMCEVENT_Delay(milliseconds); -} - -status_t SDMMCHOST_WaitCardDetectStatus(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd, bool waitCardStatus) -{ - uint32_t timeout = SDMMCHOST_CARD_DETECT_TIMEOUT; - - if (cd != NULL) - { - timeout = cd->cdTimeOut_ms; - } - - if (waitCardStatus != s_sdInsertedFlag) - { - /* Wait card inserted. */ - do - { - if (!SDMMCEVENT_Wait(kSDMMCEVENT_CardDetect, timeout)) - { - return kStatus_Fail; - } - } while (waitCardStatus != s_sdInsertedFlag); - } - - return kStatus_Success; -} - -bool SDMMCHOST_IsCardPresent(void) -{ - return s_sdInsertedFlag; -} - -void SDMMCHOST_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - if (pwr != NULL) - { - pwr->powerOff(); - SDMMCHOST_Delay(pwr->powerOffDelay_ms); - } - else - { - /* disable the card power */ - SDIF_EnableCardPower(base, false); - /* Delay several milliseconds to make card stable. */ - SDMMCHOST_Delay(500U); - } -} - -void SDMMCHOST_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - /* use user define the power on function */ - if (pwr != NULL) - { - pwr->powerOn(); - SDMMCHOST_Delay(pwr->powerOnDelay_ms); - } - else - { - /* Enable the card power */ - SDIF_EnableCardPower(base, true); - /* Delay several milliseconds to make card stable. */ - SDMMCHOST_Delay(500U); - } -} - -status_t SDMMCHOST_Init(SDMMCHOST_CONFIG *host, void *userData) -{ - sdif_transfer_callback_t sdifCallback = {0}; - sdif_host_t *sdifHost = (sdif_host_t *)host; - - /* Initialize SDIF. */ - sdifHost->config.endianMode = kSDMMCHOST_EndianModeLittle; - sdifHost->config.responseTimeout = 0xFFU; - sdifHost->config.cardDetDebounce_Clock = 0xFFFFFFU; - sdifHost->config.dataTimeout = 0xFFFFFFU; - SDIF_Init(sdifHost->base, &(sdifHost->config)); - - /* Set callback for SDHC driver. */ - sdifCallback.TransferComplete = SDMMCHOST_TransferCompleteCallback; - sdifCallback.cardInserted = SDMMCHOST_DetectCardInsertByHost; - sdifCallback.cardRemoved = SDMMCHOST_DetectCardRemoveByHost; - /* Create handle for SDHC driver */ - SDIF_TransferCreateHandle(sdifHost->base, &s_sdifHandle, &sdifCallback, userData); - - /* Create transfer complete event. */ - if (false == SDMMCEVENT_Create(kSDMMCEVENT_TransferComplete)) - { - return kStatus_Fail; - } - - /* Define transfer function. */ - sdifHost->transfer = SDMMCHOST_TransferFunction; - - /* card detect init */ - SDMMCHOST_CardDetectInit(sdifHost->base, (userData == NULL) ? NULL : (((sdmmhostcard_usr_param_t *)userData)->cd)); - - return kStatus_Success; -} - -void SDMMCHOST_Reset(SDMMCHOST_TYPE *base) -{ - /* reserved for future */ -} - -void SDMMCHOST_Deinit(void *host) -{ - sdif_host_t *sdifHost = (sdif_host_t *)host; - SDIF_Deinit(sdifHost->base); - SDMMCEVENT_Delete(kSDMMCEVENT_TransferComplete); - SDMMCHOST_CardDetectDeinit(); -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_event.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_event.c deleted file mode 100644 index 5f374f813c..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_event.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sdmmc_event.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get event instance. - * @param eventType The event type - * @return The event instance's pointer. - */ -static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Card detect event. */ -static volatile uint32_t g_eventCardDetect; - -/*! @brief transfer complete event. */ -static volatile uint32_t g_eventTransferComplete; - -/*! @brief Time variable unites as milliseconds. */ -volatile uint32_t g_eventTimeMilliseconds; - -/******************************************************************************* - * Code - ******************************************************************************/ -void SDMMCEVENT_InitTimer(void) -{ - /* Set systick reload value to generate 1ms interrupt */ - SysTick_Config(CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000U); -} - -void SysTick_Handler(void) -{ - g_eventTimeMilliseconds++; -} - -static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType) -{ - volatile uint32_t *event; - - switch (eventType) - { - case kSDMMCEVENT_TransferComplete: - event = &g_eventTransferComplete; - break; - case kSDMMCEVENT_CardDetect: - event = &g_eventCardDetect; - break; - default: - event = NULL; - break; - } - - return event; -} - -bool SDMMCEVENT_Create(sdmmc_event_t eventType) -{ - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - - if (event) - { - *event = 0; - return true; - } - else - { - return false; - } -} - -bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds) -{ - uint32_t startTime; - uint32_t elapsedTime; - - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - - if (timeoutMilliseconds && event) - { - startTime = g_eventTimeMilliseconds; - do - { - elapsedTime = (g_eventTimeMilliseconds - startTime); - } while ((*event == 0U) && (elapsedTime < timeoutMilliseconds)); - *event = 0U; - - return ((elapsedTime < timeoutMilliseconds) ? true : false); - } - else - { - return false; - } -} - -bool SDMMCEVENT_Notify(sdmmc_event_t eventType) -{ - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - - if (event) - { - *event = 1U; - return true; - } - else - { - return false; - } -} - -void SDMMCEVENT_Delete(sdmmc_event_t eventType) -{ - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - - if (event) - { - *event = 0U; - } -} - -void SDMMCEVENT_Delay(uint32_t milliseconds) -{ - uint32_t startTime = g_eventTimeMilliseconds; - uint32_t periodTime = 0; - while (periodTime < milliseconds) - { - periodTime = g_eventTimeMilliseconds - startTime; - } -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_host.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_host.c deleted file mode 100644 index 88bf2a7ec2..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/interrupt/fsl_sdmmc_host.c +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_sdmmc_host.h" -#include "fsl_sdmmc_event.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief SDMMCHOST detect card insert status by host controller. - * @param base host base address. - * @param userData user can register a application card insert callback through userData. - */ -static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, void *userData); - -/*! - * @brief SDMMCHOST detect card remove status by host controller. - * @param base host base address. - * @param userData user can register a application card insert callback through userData. - */ -static void SDMMCHOST_DetectCardRemoveByHost(SDMMCHOST_TYPE *base, void *userData); - -/*! - * @brief SDMMCHOST transfer function. - * @param base host base address. - * @param content transfer configurations. - */ -static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content); - -/*! - * @brief SDMMCHOST transfer complete callback. - * @param base host base address. - * @param handle host handle. - * @param status interrupt status. - * @param userData user data. - */ -static void SDMMCHOST_TransferCompleteCallback(SDMMCHOST_TYPE *base, void *handle, status_t status, void *userData); - -/*! - * @brief card detect deinit function. - */ -static void SDMMCHOST_CardDetectDeinit(void); - -/*! - * @brief card detect deinit function. - * @param host base address. - * @param host detect card configuration. - */ -static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd); -/******************************************************************************* - * Variables - ******************************************************************************/ - -sdif_handle_t g_sdifHandle; -static uint32_t s_sdifDmaTable[SDIF_DMA_TABLE_WORDS]; -volatile bool g_sdifTransferSuccessFlag = true; -/*! @brief Card detect flag. */ -static volatile bool s_sdInsertedFlag = false; -/******************************************************************************* - * Code - ******************************************************************************/ -static void SDMMCHOST_DetectCardInsertByHost(SDIF_Type *base, void *userData) -{ - s_sdInsertedFlag = true; - SDMMCEVENT_Notify(kSDMMCEVENT_CardDetect); - /* application callback */ - if (userData && (((sdmmhostcard_usr_param_t *)userData)->cd) && - ((sdmmhostcard_usr_param_t *)userData)->cd->cardInserted) - { - ((sdmmhostcard_usr_param_t *)userData) - ->cd->cardInserted(true, ((sdmmhostcard_usr_param_t *)userData)->cd->userData); - } -} - -static void SDMMCHOST_DetectCardRemoveByHost(SDIF_Type *base, void *userData) -{ - s_sdInsertedFlag = false; - /* application callback */ - if (userData && (((sdmmhostcard_usr_param_t *)userData)->cd) && - ((sdmmhostcard_usr_param_t *)userData)->cd->cardRemoved) - { - ((sdmmhostcard_usr_param_t *)userData) - ->cd->cardRemoved(false, ((sdmmhostcard_usr_param_t *)userData)->cd->userData); - } -} - -/* Transfer complete callback function. */ -static void SDMMCHOST_TransferCompleteCallback(SDMMCHOST_TYPE *base, void *handle, status_t status, void *userData) -{ - /* receive the right status, notify the event */ - if (status == kStatus_Success) - { - g_sdifTransferSuccessFlag = true; - } - else - { - g_sdifTransferSuccessFlag = false; - } - - SDMMCEVENT_Notify(kSDMMCEVENT_TransferComplete); -} - -/* User defined transfer function. */ -static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content) -{ - status_t error = kStatus_Success; - - sdif_dma_config_t dmaConfig; - - memset(s_sdifDmaTable, 0, sizeof(s_sdifDmaTable)); - memset(&dmaConfig, 0, sizeof(dmaConfig)); - - /* make sure the complete event is delete */ - SDMMCEVENT_Delete(kSDMMCEVENT_TransferComplete); - - /* user DMA mode transfer data */ - if (content->data != NULL) - { - dmaConfig.enableFixBurstLen = false; - dmaConfig.mode = kSDIF_DualDMAMode; - dmaConfig.dmaDesBufferStartAddr = s_sdifDmaTable; - dmaConfig.dmaDesBufferLen = SDIF_DMA_TABLE_WORDS; - dmaConfig.dmaDesSkipLen = 0U; - } - - do - { - error = SDIF_TransferNonBlocking(base, &g_sdifHandle, &dmaConfig, content); - } while (error == kStatus_SDIF_SyncCmdTimeout); - - if ((error != kStatus_Success) || - (false == SDMMCEVENT_Wait(kSDMMCEVENT_TransferComplete, SDMMCHOST_TRANSFER_COMPLETE_TIMEOUT)) || - (!g_sdifTransferSuccessFlag)) - { - error = kStatus_Fail; - } - - return error; -} - -static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd) -{ - sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByHostCD; - - if (cd != NULL) - { - cdType = cd->cdType; - } - - /* for interrupt case, only kSDMMCHOST_DetectCardByHostCD can generate interrupt, so implement it only */ - if (cdType != kSDMMCHOST_DetectCardByHostCD) - { - return kStatus_Fail; - } - - if (!SDMMCEVENT_Create(kSDMMCEVENT_CardDetect)) - { - return kStatus_Fail; - } - /* enable the card detect interrupt */ - SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base); - /* check if card is inserted */ - if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base, false)) - { - s_sdInsertedFlag = true; - /* application callback */ - if (cd && cd->cardInserted) - { - cd->cardInserted(true, cd->userData); - } - } - - return kStatus_Success; -} - -static void SDMMCHOST_CardDetectDeinit(void) -{ - SDMMCEVENT_Delete(kSDMMCEVENT_CardDetect); - s_sdInsertedFlag = false; -} - -void SDMMCHOST_Delay(uint32_t milliseconds) -{ - SDMMCEVENT_Delay(milliseconds); -} - -status_t SDMMCHOST_WaitCardDetectStatus(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd, bool waitCardStatus) -{ - uint32_t timeout = SDMMCHOST_CARD_DETECT_TIMEOUT; - - if (cd != NULL) - { - timeout = cd->cdTimeOut_ms; - } - - if (waitCardStatus != s_sdInsertedFlag) - { - /* Wait card inserted. */ - do - { - if (!SDMMCEVENT_Wait(kSDMMCEVENT_CardDetect, timeout)) - { - return kStatus_Fail; - } - } while (waitCardStatus != s_sdInsertedFlag); - } - - return kStatus_Success; -} - -bool SDMMCHOST_IsCardPresent(void) -{ - return s_sdInsertedFlag; -} - -void SDMMCHOST_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - if (pwr != NULL) - { - pwr->powerOff(); - SDMMCHOST_Delay(pwr->powerOffDelay_ms); - } - else - { - /* disable the card power */ - SDIF_EnableCardPower(base, false); - /* Delay several milliseconds to make card stable. */ - SDMMCHOST_Delay(500U); - } -} - -void SDMMCHOST_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - /* use user define the power on function */ - if (pwr != NULL) - { - pwr->powerOn(); - SDMMCHOST_Delay(pwr->powerOnDelay_ms); - } - else - { - /* Enable the card power */ - SDIF_EnableCardPower(base, true); - /* Delay several milliseconds to make card stable. */ - SDMMCHOST_Delay(500U); - } -} - -status_t SDMMCHOST_Init(SDMMCHOST_CONFIG *host, void *userData) -{ - sdif_transfer_callback_t sdifCallback = {0}; - sdif_host_t *sdifHost = (sdif_host_t *)host; - - /* init event timer. */ - SDMMCEVENT_InitTimer(); - - /* Initialize SDIF. */ - sdifHost->config.endianMode = kSDMMCHOST_EndianModeLittle; - sdifHost->config.responseTimeout = 0xFFU; - sdifHost->config.cardDetDebounce_Clock = 0xFFFFFFU; - sdifHost->config.dataTimeout = 0xFFFFFFU; - SDIF_Init(sdifHost->base, &(sdifHost->config)); - - /* Set callback for SDIF driver. */ - sdifCallback.TransferComplete = SDMMCHOST_TransferCompleteCallback; - sdifCallback.cardInserted = SDMMCHOST_DetectCardInsertByHost; - sdifCallback.cardRemoved = SDMMCHOST_DetectCardRemoveByHost; - - /* Create handle for SDIF driver */ - SDIF_TransferCreateHandle(sdifHost->base, &g_sdifHandle, &sdifCallback, userData); - - /* Create transfer complete event. */ - if (false == SDMMCEVENT_Create(kSDMMCEVENT_TransferComplete)) - { - return kStatus_Fail; - } - - /* Define transfer function. */ - sdifHost->transfer = SDMMCHOST_TransferFunction; - - /* card detect init */ - SDMMCHOST_CardDetectInit(sdifHost->base, (userData == NULL) ? NULL : (((sdmmhostcard_usr_param_t *)userData)->cd)); - - return kStatus_Success; -} - -void SDMMCHOST_Reset(SDMMCHOST_TYPE *base) -{ - /* reserved for future */ -} - -void SDMMCHOST_Deinit(void *host) -{ - sdif_host_t *sdifHost = (sdif_host_t *)host; - SDIF_Deinit(sdifHost->base); - SDMMCHOST_CardDetectDeinit(); -} - -void SDMMCHOST_ErrorRecovery(SDMMCHOST_TYPE *base) -{ - /* reserved for future */ -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_event.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_event.c deleted file mode 100644 index 11a5b964fa..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_event.c +++ /dev/null @@ -1,142 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_sdmmc_event.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get event instance. - * @param eventType The event type - * @return The event instance's pointer. - */ -static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Card detect event. */ -static volatile uint32_t g_eventCardDetect; - -/*! @brief transfer complete event. */ -static volatile uint32_t g_eventTransferComplete; - -/*! @brief Time variable unites as milliseconds. */ -volatile uint32_t g_eventTimeMilliseconds; - -/******************************************************************************* - * Code - ******************************************************************************/ -void SDMMCEVENT_InitTimer(void) -{ - /* Set systick reload value to generate 1ms interrupt */ - SysTick_Config(CLOCK_GetFreq(kCLOCK_CoreSysClk) / 1000U); -} - -void SysTick_Handler(void) -{ - g_eventTimeMilliseconds++; -} - -static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType) -{ - volatile uint32_t *event; - - switch (eventType) - { - case kSDMMCEVENT_TransferComplete: - event = &g_eventTransferComplete; - break; - case kSDMMCEVENT_CardDetect: - event = &g_eventCardDetect; - break; - default: - event = NULL; - break; - } - - return event; -} - -bool SDMMCEVENT_Create(sdmmc_event_t eventType) -{ - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - - if (event) - { - *event = 0; - return true; - } - else - { - return false; - } -} - -bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds) -{ - uint32_t startTime; - uint32_t elapsedTime; - - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - - if (timeoutMilliseconds && event) - { - startTime = g_eventTimeMilliseconds; - do - { - elapsedTime = (g_eventTimeMilliseconds - startTime); - } while ((*event == 0U) && (elapsedTime < timeoutMilliseconds)); - *event = 0U; - - return ((elapsedTime < timeoutMilliseconds) ? true : false); - } - else - { - return false; - } -} - -bool SDMMCEVENT_Notify(sdmmc_event_t eventType) -{ - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - - if (event) - { - *event = 1U; - return true; - } - else - { - return false; - } -} - -void SDMMCEVENT_Delete(sdmmc_event_t eventType) -{ - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - - if (event) - { - *event = 0U; - } -} - -void SDMMCEVENT_Delay(uint32_t milliseconds) -{ - uint32_t startTime = g_eventTimeMilliseconds; - uint32_t periodTime = 0; - while (periodTime < milliseconds) - { - periodTime = g_eventTimeMilliseconds - startTime; - } -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_host.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_host.c deleted file mode 100644 index c563786489..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/polling/fsl_sdmmc_host.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sdmmc_host.h" -#include "fsl_sdmmc_event.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief SDMMCHOST detect card insert status by host controller. - * @param base host base address. - * @param data3 flag indicate use data3 to detect card or not. - */ -static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, bool data3); - -/*! - * @brief SDMMCHOST detect card status by GPIO. - */ -static bool SDMMCHOST_DetectCardByGpio(void); - -/*! - * @brief SDMMCHOST transfer function. - * @param base host base address. - * @param content transfer configurations. - */ -static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content); - -/*! - * @brief card detect deinit function. - */ -static void SDMMCHOST_CardDetectDeinit(void); - -/*! - * @brief card detect deinit function. - * @param host base address. - * @param host detect card configuration. - */ -static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Card detect flag. */ -static volatile bool s_sdInsertedFlag = false; -/*! @brief DMA descriptor table. */ -static uint32_t s_sdifDmaTable[SDIF_DMA_TABLE_WORDS]; -/******************************************************************************* - * Code - ******************************************************************************/ -static bool SDMMCHOST_DetectCardByGpio(void) -{ - if (SDMMCHOST_CARD_DETECT_STATUS() != SDMMCHOST_CARD_INSERT_CD_LEVEL) - { - s_sdInsertedFlag = false; - } - else - { - s_sdInsertedFlag = true; - } - - return s_sdInsertedFlag; -} - -static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, bool data3) -{ - if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base, data3)) - { - s_sdInsertedFlag = true; - } -} - -/* User defined transfer function. */ -static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content) -{ - status_t error = kStatus_Success; - - sdif_dma_config_t dmaConfig; - - memset(s_sdifDmaTable, 0, sizeof(s_sdifDmaTable)); - memset(&dmaConfig, 0, sizeof(dmaConfig)); - - if (content->data != NULL) - { - dmaConfig.enableFixBurstLen = true; - dmaConfig.mode = kSDIF_ChainDMAMode; - dmaConfig.dmaDesBufferStartAddr = s_sdifDmaTable; - dmaConfig.dmaDesBufferLen = SDIF_DMA_TABLE_WORDS; - } - - if (kStatus_Success != SDIF_TransferBlocking(base, &dmaConfig, content)) - { - error = kStatus_Fail; - } - - return error; -} - -static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd) -{ - sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByGpioCD; - - if (cd != NULL) - { - cdType = cd->cdType; - } - - if (cdType == kSDMMCHOST_DetectCardByGpioCD) - { - SDMMCHOST_CARD_DETECT_INIT(); - SDMMCHOST_DetectCardByGpio(); - } - else - { - /* enable card detect status */ - SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base); - } - - return kStatus_Success; -} - -static void SDMMCHOST_CardDetectDeinit(void) -{ - s_sdInsertedFlag = false; -} - -void SDMMCHOST_Delay(uint32_t milliseconds) -{ - SDMMCEVENT_Delay(milliseconds); -} - -status_t SDMMCHOST_WaitCardDetectStatus(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd, bool waitCardStatus) -{ - sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByGpioCD; - - if (cd != NULL) - { - cdType = cd->cdType; - } - - if (waitCardStatus != s_sdInsertedFlag) - { - /* Wait card inserted. */ - do - { - if (cdType == kSDMMCHOST_DetectCardByGpioCD) - { - SDMMCHOST_DetectCardByGpio(); - } - else - { - SDMMCHOST_DetectCardInsertByHost(base, cdType == kSDMMCHOST_DetectCardByHostDATA3); - } - - } while (waitCardStatus != s_sdInsertedFlag); - } - - return kStatus_Success; -} - -bool SDMMCHOST_IsCardPresent(void) -{ - return s_sdInsertedFlag; -} - -void SDMMCHOST_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - if (pwr != NULL) - { - pwr->powerOff(); - SDMMCHOST_Delay(pwr->powerOffDelay_ms); - } - else - { - /* disable the card power */ - SDIF_EnableCardPower(base, false); - /* Delay several milliseconds to make card stable. */ - SDMMCHOST_Delay(500U); - } -} - -void SDMMCHOST_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - /* use user define the power on function */ - if (pwr != NULL) - { - pwr->powerOn(); - SDMMCHOST_Delay(pwr->powerOnDelay_ms); - } - else - { - /* Enable the card power */ - SDIF_EnableCardPower(base, true); - /* Delay several milliseconds to make card stable. */ - SDMMCHOST_Delay(500U); - } -} - -status_t SDMMCHOST_Init(SDMMCHOST_CONFIG *host, void *userData) -{ - sdif_host_t *sdifHost = (sdif_host_t *)host; - - /* init event timer. */ - SDMMCEVENT_InitTimer(); - - /* Initialize SDIF. */ - sdifHost->config.endianMode = kSDMMCHOST_EndianModeLittle; - sdifHost->config.responseTimeout = 0xFFU; - sdifHost->config.cardDetDebounce_Clock = 0xFFFFFFU; - sdifHost->config.dataTimeout = 0xFFFFFFU; - SDIF_Init(sdifHost->base, &(sdifHost->config)); - - /* Define transfer function. */ - sdifHost->transfer = SDMMCHOST_TransferFunction; - - SDMMCHOST_CardDetectInit(sdifHost->base, (userData == NULL) ? NULL : (((sdmmhostcard_usr_param_t *)userData)->cd)); - - return kStatus_Success; -} - -void SDMMCHOST_Reset(SDMMCHOST_TYPE *base) -{ - /* reserved for future */ -} - -void SDMMCHOST_Deinit(void *host) -{ - sdif_host_t *sdifHost = (sdif_host_t *)host; - SDIF_Deinit(sdifHost->base); - SDMMCHOST_CardDetectDeinit(); -} - -void SDMMCHOST_ErrorRecovery(SDMMCHOST_TYPE *base) -{ - /* reserved for future */ -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_event.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_event.c deleted file mode 100644 index 06c95fa476..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_event.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sdmmc_event.h" - -#include - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Get event instance. - * @param eventType The event type - * @return The event instance's pointer. - */ -static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Card detect event. */ -static volatile uint32_t g_eventCardDetect; - -/*! @brief transfer complete event. */ -static volatile uint32_t g_eventTransferComplete; - - -/******************************************************************************* - * Code - ******************************************************************************/ -void SDMMCEVENT_InitTimer(void) -{ - -} - -static volatile uint32_t *SDMMCEVENT_GetInstance(sdmmc_event_t eventType) -{ - volatile uint32_t *event; - - switch (eventType) - { - case kSDMMCEVENT_TransferComplete: - event = &g_eventTransferComplete; - break; - case kSDMMCEVENT_CardDetect: - event = &g_eventCardDetect; - break; - default: - event = NULL; - break; - } - - return event; -} - -bool SDMMCEVENT_Create(sdmmc_event_t eventType) -{ - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - - if (event) - { - *event = 0; - return true; - } - else - { - return false; - } -} - -bool SDMMCEVENT_Wait(sdmmc_event_t eventType, uint32_t timeoutMilliseconds) -{ - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - rt_thread_delay(timeoutMilliseconds); - - if (event) - { - return true; - } - else - { - return false; - } -} - -bool SDMMCEVENT_Notify(sdmmc_event_t eventType) -{ - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - - if (event) - { - *event = 1U; - return true; - } - else - { - return false; - } -} - -void SDMMCEVENT_Delete(sdmmc_event_t eventType) -{ - volatile uint32_t *event = SDMMCEVENT_GetInstance(eventType); - - if (event) - { - *event = 0U; - } -} - -void SDMMCEVENT_Delay(uint32_t milliseconds) -{ - rt_thread_delay(milliseconds); -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_host.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_host.c deleted file mode 100644 index 65b93d8881..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/port/sdif/rt_thread/fsl_sdmmc_host.c +++ /dev/null @@ -1,274 +0,0 @@ -/* - * The Clear BSD License - * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted (subject to the limitations in the disclaimer below) provided - * that the following conditions are met: - * - * o Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * o Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * o Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "fsl_sdmmc_host.h" -#include "fsl_sdmmc_event.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief SDMMCHOST detect card insert status by host controller. - * @param base host base address. - * @param data3 flag indicate use data3 to detect card or not. - */ -static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, bool data3); - -/*! - * @brief SDMMCHOST detect card status by GPIO. - */ -static bool SDMMCHOST_DetectCardByGpio(void); - -/*! - * @brief SDMMCHOST transfer function. - * @param base host base address. - * @param content transfer configurations. - */ -static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content); - -/*! - * @brief card detect deinit function. - */ -static void SDMMCHOST_CardDetectDeinit(void); - -/*! - * @brief card detect deinit function. - * @param host base address. - * @param host detect card configuration. - */ -static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/*! @brief Card detect flag. */ -static volatile bool s_sdInsertedFlag = false; -/*! @brief DMA descriptor table. */ -static uint32_t s_sdifDmaTable[SDIF_DMA_TABLE_WORDS]; -/******************************************************************************* - * Code - ******************************************************************************/ -static bool SDMMCHOST_DetectCardByGpio(void) -{ - if (SDMMCHOST_CARD_DETECT_STATUS() != SDMMCHOST_CARD_INSERT_CD_LEVEL) - { - s_sdInsertedFlag = false; - } - else - { - s_sdInsertedFlag = true; - } - - return s_sdInsertedFlag; -} - -static void SDMMCHOST_DetectCardInsertByHost(SDMMCHOST_TYPE *base, bool data3) -{ - if (SDMMCHOST_CARD_DETECT_INSERT_STATUS(base, data3)) - { - s_sdInsertedFlag = true; - } -} - -/* User defined transfer function. */ -static status_t SDMMCHOST_TransferFunction(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER *content) -{ - status_t error = kStatus_Success; - - sdif_dma_config_t dmaConfig; - - memset(s_sdifDmaTable, 0, sizeof(s_sdifDmaTable)); - memset(&dmaConfig, 0, sizeof(dmaConfig)); - - if (content->data != NULL) - { - dmaConfig.enableFixBurstLen = true; - dmaConfig.mode = kSDIF_ChainDMAMode; - dmaConfig.dmaDesBufferStartAddr = s_sdifDmaTable; - dmaConfig.dmaDesBufferLen = SDIF_DMA_TABLE_WORDS; - } - - if (kStatus_Success != SDIF_TransferBlocking(base, &dmaConfig, content)) - { - error = kStatus_Fail; - } - - return error; -} - -static status_t SDMMCHOST_CardDetectInit(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd) -{ - sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByGpioCD; - - if (cd != NULL) - { - cdType = cd->cdType; - } - - if (cdType == kSDMMCHOST_DetectCardByGpioCD) - { - SDMMCHOST_CARD_DETECT_INIT(); - SDMMCHOST_DetectCardByGpio(); - } - else - { - /* enable card detect status */ - SDMMCHOST_CARD_DETECT_INSERT_ENABLE(base); - } - - return kStatus_Success; -} - -static void SDMMCHOST_CardDetectDeinit(void) -{ - s_sdInsertedFlag = false; -} - -void SDMMCHOST_Delay(uint32_t milliseconds) -{ - SDMMCEVENT_Delay(milliseconds); -} - -status_t SDMMCHOST_WaitCardDetectStatus(SDMMCHOST_TYPE *base, const sdmmchost_detect_card_t *cd, bool waitCardStatus) -{ - sdmmchost_detect_card_type_t cdType = kSDMMCHOST_DetectCardByGpioCD; - - if (cd != NULL) - { - cdType = cd->cdType; - } - - if (waitCardStatus != s_sdInsertedFlag) - { - /* Wait card inserted. */ - do - { - if (cdType == kSDMMCHOST_DetectCardByGpioCD) - { - SDMMCHOST_DetectCardByGpio(); - } - else - { - SDMMCHOST_DetectCardInsertByHost(base, cdType == kSDMMCHOST_DetectCardByHostDATA3); - } - - } while (waitCardStatus != s_sdInsertedFlag); - } - - return kStatus_Success; -} - -bool SDMMCHOST_IsCardPresent(void) -{ - return s_sdInsertedFlag; -} - -void SDMMCHOST_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - if (pwr != NULL) - { - pwr->powerOff(); - SDMMCHOST_Delay(pwr->powerOffDelay_ms); - } - else - { - /* disable the card power */ - SDIF_EnableCardPower(base, false); - /* Delay several milliseconds to make card stable. */ - SDMMCHOST_Delay(500U); - } -} - -void SDMMCHOST_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - /* use user define the power on function */ - if (pwr != NULL) - { - pwr->powerOn(); - SDMMCHOST_Delay(pwr->powerOnDelay_ms); - } - else - { - /* Enable the card power */ - SDIF_EnableCardPower(base, true); - /* Delay several milliseconds to make card stable. */ - SDMMCHOST_Delay(500U); - } -} - -status_t SDMMCHOST_Init(SDMMCHOST_CONFIG *host, void *userData) -{ - sdif_host_t *sdifHost = (sdif_host_t *)host; - - /* init event timer. */ - SDMMCEVENT_InitTimer(); - - /* Initialize SDIF. */ - sdifHost->config.endianMode = kSDMMCHOST_EndianModeLittle; - sdifHost->config.responseTimeout = 0xFFU; - sdifHost->config.cardDetDebounce_Clock = 0xFFFFFFU; - sdifHost->config.dataTimeout = 0xFFFFFFU; - SDIF_Init(sdifHost->base, &(sdifHost->config)); - - /* Define transfer function. */ - sdifHost->transfer = SDMMCHOST_TransferFunction; - - /* Enable the card power here for mmc card case, because mmc card don't need card detect*/ - SDIF_EnableCardPower(sdifHost->base, true); - - SDMMCHOST_CardDetectInit(sdifHost->base, (sdmmchost_detect_card_t *)userData); - - return kStatus_Success; -} - -void SDMMCHOST_Reset(SDMMCHOST_TYPE *base) -{ - /* reserved for future */ -} - -void SDMMCHOST_Deinit(void *host) -{ - sdif_host_t *sdifHost = (sdif_host_t *)host; - SDIF_Deinit(sdifHost->base); - SDMMCHOST_CardDetectDeinit(); -} - -void SDMMCHOST_ErrorRecovery(SDMMCHOST_TYPE *base) -{ - /* reserved for future */ -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/ChangeLogKSDK.txt b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/ChangeLogKSDK.txt new file mode 100644 index 0000000000..f4be6e96fd --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/ChangeLogKSDK.txt @@ -0,0 +1,123 @@ +/*! +@page middleware_log Middleware Change Log + +@section sd SD Card driver for MCUXpresso SDK + The current driver version is 2.4.0. + + - 2.4.0 + - Improvements + - Removed deprecated api in sd driver. + - Added new api SD_PollingCardStatusBusy for application polling card status. + - Improved the read/write/erase function flow. + - Improved the signal line voltage switch flow. + - Added powerOnDelayMS/powerOffDelayMS in sd_usr_param_t to allow redefine the default power on/off delay. + - Added mutual exclusive access for init/deinit/read/write/erase function. + - Fixed the driver strength configurations missed when timing mode switch to non SDR50/SDR104 mode. + - Fixed violations of MISRA C-2012 rule 4.7, 17.7, 10.7, 10.4, 13.5, 14.4. + + - 2.3.3 + - Improvements + - Added host SDR timing mode capability validation during card initialization. + - Added plling card ready for data status when transfer data failed. + - Used cache line size align buffer for SD initialization api. + - Bug Fixes + - Fixed violations of MISRA C-2012 rule 11.9, 15.7, 4.7, 16.4, 10.1, 10.3, 10.4, 11.3, 14.4, 10.6, 17.7, 16.1, 16.3. + + - 2.3.2 + - Improvements + - Moved power off function after card detect in SD_Init for DAT3 detect card feature. + + - 2.3.1 + - Improvements + - Removed the dead loop while polling DAT0 and CMD13 instead of using timeout mechanism. + + - 2.3.0 + - Improvements + - Marked api SD_HostReset/SD_PowerOnCard/SD_PowerOffCard/SD_WaitCardDetectStatus as deprecated. + - Added new api SD_SetCardPower/SD_PollingCardDetectStatus/SD_HostDoReset. + - Added internalBuffer in sd_card_t and removed rawCid/rawCsd/rawScr. + - Added retuning support during data transfer under SDR50/SDR104 mode. + - Increased the read/write blocks failed retry times for stability. + - Added delay while retry the ACMD41 for stability. + + - 2.2.12 + - Improvements + - Increased the sd io driver strength for SD2.0 card. + - Bug Fixes + - Fixed the build warning by changing the old style function declaration static + status_t inline to static inline status_t(found by adding + -Wold-style-declaration in armgcc build flag). + + - 2.2.10 + - Bug Fixes + - Added event value check for all the FreeRTOS events to fix program hangs + when a card event occurs before create. + + - 2.2.7 + - Bug Fixes + - Fixed MDK 66-D warning. + + - 2.2.5 + - Improvements + - Added SD_ReadStatus api to get 512bit SD status. + - Added error log support in sdcard functions. + - Added SDMMC_ENABLE_SOFTWARE_TUNING to enable/disable software tuning and it is disabled by default. + + - 2.2.4 + - Bug Fixes + - Fixed DDR mode data sequence miss issue, which is caused by NIBBLE_POS. + - Improvements + - Increased g_sdmmc 512byte to improve the performance when application use a non-word align data buffer address. + - Enabled auto cmd12 for SD read/write. + + - 2.2.3 + - Bug Fixes + - Added response check for send operation condition command. If not checked, the card may occasionally init fail. + + - 2.2.1 + - Improvements + - Kept SD_Init function for forward compatibility. + + - 2.2.0 + - Improvements + - Separated the SD/MMC/SDIO init API to xxx_CardInit/xxx_HostInit. + - SD_Init/SDIO_Init will be deprecated in the next version. + + - 2.1.6 + - Improvements + - Enhanced SD IO default driver strength. + + - 2.1.5 + - Bug Fixes + - Fixed Coverity issue. + - Fixed SD v1.x card write fail issue. It was caused by the block length set error. + - Fixed card cannot detect dynamically. + + - 2.1.3 + - Bug Fixes + - Fixed Non high-speed sdcard init fail at switch to high speed. + - Improvements + - Added Delay for SDCard power up. + + - 2.1.2 + - Improvements + - Improved SDMMC to support SD v3.0. + + - 2.1.1 + - Bug Fixes + - Fixed the bit mask error in the SD card switch to high speed function. + - Improvements + - Optimized the SD card initialization function. + + - 2.1.0 + - Bug Fixes + - Changed the callback mechanism when sending a command. + - Fixed the performance low issue when transferring data. + - Improvements + - Changed the name of some error codes returned by internal function. + - Merged all host related attributes to one structure. + + - 2.0.0 + - Initial version. + +*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/fsl_sd.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/fsl_sd.c new file mode 100644 index 0000000000..4485c1883a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/fsl_sd.c @@ -0,0 +1,2290 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include "fsl_sd.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*!@brief power reset delay */ +#define SD_POWER_ON_DELAY (400U) +#define SD_POWER_OFF_DELAY (100U) +/*! @brief card access idle timeout value */ +#ifndef SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT +#define SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT (600U) /* more then 500ms timeout value */ +#endif +/*! @brief card cmd13 retry times */ +#ifndef SD_CMD13_RETRY_TIMES +#define SD_CMD13_RETRY_TIMES (10) +#endif +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief Wait write process complete. + * + * @param card Card descriptor. + * @retval kStatus_Timeout Send command timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendCardStatus(sd_card_t *card); + +/*! + * @brief send write success blocks. + * + * @param card Card descriptor. + * @param blocks blocks number wirte successed + * @retval kStatus_SDMMC_TransferFailed Send command failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendWriteSuccessBlocks(sd_card_t *card, uint32_t *blocks); + +/*! + * @brief Send SEND_APPLICATION_COMMAND command. + * + * @param card Card descriptor. + * @param relativeaddress + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_Success Operate successfully. + */ +static inline status_t SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress); + +/*! + * @brief Send GO_IDLE command to set the card to be idle state. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static inline status_t SD_GoIdle(sd_card_t *card); + +/*! + * @brief Send STOP_TRANSMISSION command after multiple blocks read/write. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_StopTransmission(sd_card_t *card); + +/*! + * @brief Send SET_BLOCK_SIZE command. + * + * @param card Card descriptor. + * @param blockSize Block size. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static inline status_t SD_SetBlockSize(sd_card_t *card, uint32_t blockSize); + +/*! + * @brief Send GET_RCA command to get card relative address. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendRca(sd_card_t *card); + +/*! + * @brief Send SWITCH_FUNCTION command to switch the card function group. + * + * @param card Card descriptor. + * @param mode 0 to check function group. 1 to switch function group + * @param group Function group + * @param number Function number in the function group. + * @param status Switch function status. + * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status); + +/*! + * @brief Decode raw SCR register content in the data blocks. + * + * @param card Card descriptor. + * @param rawScr Raw SCR register content. + */ +static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr); + +/*! + * @brief Send GET_SCR command. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_NotSupportYet Not support yet. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendScr(sd_card_t *card); + +/*! + * @brief Switch the card to be high speed mode. + * + * @param card Card descriptor. + * @param group Group number. + * @param functio Function number. + * @retval kStatus_SDMMC_CardNotSupport Card not support. + * @retval kStatus_SDMMC_SwitchFailed Switch failed. + * @retval kStatus_SDMMC_NotSupportYet Not support yet. + * @retval kStatus_Fail Switch failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function); + +/*! + * @brief Send SET_DATA_WIDTH command to set SD bus width. + * + * @param card Card descriptor. + * @param width Data bus width. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_InvalidArgument Invalid argument. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SetDataBusWidth(sd_card_t *card, uint32_t width); + +/*! + * @brief Decode raw CSD register content in the data blocks. + * + * @param card Card descriptor. + * @param rawCsd Raw CSD register content. + */ +static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd); + +/*! + * @brief Send SEND_CSD command to get CSD register content from Card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendCsd(sd_card_t *card); + +/*! + * @brief Decode raw CID register content in the data blocks. + * + * @param rawCid raw CID register content. + * @param card Card descriptor. + */ +static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid); + +/*! + * @brief Send GET_CID command to get CID from card. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_AllSendCid(sd_card_t *card); + +/*! + * @brief Send SEND_OPERATION_CONDITION command. + * + * This function sends host capacity support information and asks the accessed card to send its operating condition + * register content. + * + * @param card Card descriptor. + * @param argument The argument of the send operation condition ncomamnd. + * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Timeout Timeout. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument); + +/*! + * @brief Send GET_INTERFACE_CONDITION command to get card interface condition. + * + * This function checks card interface condition, which includes host supply voltage information and asks the card + * whether card supports the specified host voltage. + * + * @param card Card descriptor. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_SendInterfaceCondition(sd_card_t *card); + +/*! + * @brief Send switch voltage command + * switch card voltage to 1.8v + * + * @param card Card descriptor. + * @param voltage target voltage + */ +static status_t SD_SwitchVoltage(sd_card_t *card, sdmmc_operation_voltage_t voltage); + +/*! + * @brief select bus timing + * select card timing + * @param card Card descriptor. + */ +static status_t SD_SelectBusTiming(sd_card_t *card); + +/*! + * @brief Decode sd 512 bit status + * @param card Card descriptor. + * @param 512 bits satus raw data. + */ +static void SD_DecodeStatus(sd_card_t *card, uint32_t *src); + +/*! + * @brief Read data from specific SD card. + * + * @param card Card descriptor. + * @param buffer Buffer to save data blocks read. + * @param startBlock Card start block number to be read. + * @param blockSize Block size. + * @param blockCount Block count. + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); + +/*! + * @brief Write data to specific card + * + * @param card Card descriptor. + * @param buffer Buffer to be sent. + * @param startBlock Card start block number to be written. + * @param blockSize Block size. + * @param blockCount Block count. + * @param writtenBlocks successfully write blocks + * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Write(sd_card_t *card, + const uint8_t *buffer, + uint32_t startBlock, + uint32_t blockSize, + uint32_t blockCount, + uint32_t *writtenBlocks); + +/*! + * @brief Erase data for the given block range. + * + * @param card Card descriptor. + * @param startBlock Card start block number to be erased. + * @param blockCount The block count to be erased. + * @param timeout timeout value in ms will be used to wait erase done. + * + * @retval kStatus_SDMMC_WaitWriteCompleteFailed wait erase timeout. + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + */ +static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount, uint32_t timeout); + +/*! + * @brief card transfer function. + * + * @param card Card descriptor. + * @param content Transfer content. + * @param retry Retry times + * @retval kStatus_SDMMC_TransferFailed Transfer failed. + * @retval kStatus_Success Operate successfully. + * @retval kStatus_SDMMC_TuningFail tuning fail + */ +static status_t SD_Transfer(sd_card_t *card, sdmmchost_transfer_t *content, uint32_t retry); + +/*! + * @brief card execute tuning function. + * + * @param card Card descriptor. + * @retval kStatus_Success Operate successfully. + * @retval kStatus_SDMMC_TuningFail tuning fail. + * @retval kStatus_SDMMC_TransferFailed transfer fail + */ +static inline status_t SD_ExecuteTuning(sd_card_t *card); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*!@brief sd size map */ +static uint32_t s_sdAuSizeMap[] = {0, + 16 * 1024, + 32 * 1024, + 64 * 1024, + 128 * 1024, + 256 * 1024, + 512 * 1024, + 1024 * 1024, + 2 * 1024 * 1024, + 4 * 1024 * 1024, + 8 * 1024 * 1024, + 12 * 1024 * 1024, + 16 * 1024 * 1024, + 24 * 1024 * 1024, + 32 * 1024 * 1024, + 64 * 1024 * 1024}; +/******************************************************************************* + * Code + ******************************************************************************/ +static status_t SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress) +{ + assert(card != NULL); + + return SDMMC_SendApplicationCommand(card->host, relativeAddress); +} + +static status_t SD_GoIdle(sd_card_t *card) +{ + assert(card != NULL); + + return SDMMC_GoIdle(card->host); +} + +static status_t SD_SetBlockSize(sd_card_t *card, uint32_t blockSize) +{ + assert(card != NULL); + + return SDMMC_SetBlockSize(card->host, blockSize); +} + +static status_t SD_ExecuteTuning(sd_card_t *card) +{ + assert(card != NULL); + + return SDMMCHOST_ExecuteTuning(card->host, (uint32_t)kSD_SendTuningBlock, + (uint32_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer), 64U); +} + +static status_t SD_SwitchIOVoltage(sd_card_t *card, sdmmc_operation_voltage_t voltage) +{ + if ((card->usrParam.ioVoltage != NULL) && (card->usrParam.ioVoltage->type == kSD_IOVoltageCtrlByGpio)) + { + /* make sure card signal line voltage is 3.3v before initalization */ + if (card->usrParam.ioVoltage->func != NULL) + { + card->usrParam.ioVoltage->func(voltage); + } + } + else if ((card->usrParam.ioVoltage != NULL) && (card->usrParam.ioVoltage->type == kSD_IOVoltageCtrlByHost)) + { + SDMMCHOST_SwitchToVoltage(card->host, (uint32_t)voltage); + } + else + { + return kStatus_SDMMC_NotSupportYet; + } + + return kStatus_Success; +} + +static status_t SD_SwitchVoltage(sd_card_t *card, sdmmc_operation_voltage_t voltage) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSD_VoltageSwitch; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + /* check data line and cmd line status */ + if (SDMMCHOST_GetSignalLineStatus(card->host, (uint32_t)kSDMMC_SignalLineData0 | (uint32_t)kSDMMC_SignalLineData1 | + (uint32_t)kSDMMC_SignalLineData2 | + (uint32_t)kSDMMC_SignalLineData3) != 0U) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + /* switch io voltage */ + if (SD_SwitchIOVoltage(card, voltage) == kStatus_SDMMC_NotSupportYet) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + SDMMC_OSADelay(100U); + + /*enable force clock on*/ + SDMMCHOST_ForceClockOn(card->host, true); + /* dealy 1ms,not exactly correct when use while */ + SDMMC_OSADelay(10U); + /*disable force clock on*/ + SDMMCHOST_ForceClockOn(card->host, false); + + /* check data line and cmd line status */ + if (SDMMCHOST_GetSignalLineStatus(card->host, (uint32_t)kSDMMC_SignalLineData0 | (uint32_t)kSDMMC_SignalLineData1 | + (uint32_t)kSDMMC_SignalLineData2 | + (uint32_t)kSDMMC_SignalLineData3) == 0U) + { + error = kStatus_SDMMC_SwitchVoltageFail; + /* power reset the card */ + SD_SetCardPower(card, false); + SD_SetCardPower(card, true); + /* re-check the data line status */ + if (SDMMCHOST_GetSignalLineStatus( + card->host, (uint32_t)kSDMMC_SignalLineData0 | (uint32_t)kSDMMC_SignalLineData1 | + (uint32_t)kSDMMC_SignalLineData2 | (uint32_t)kSDMMC_SignalLineData3) != 0U) + { + error = kStatus_SDMMC_SwitchVoltage18VFail33VSuccess; + SDMMC_LOG( + "\r\nNote: Current card support 1.8V, but board don't support, so sdmmc switch back to 3.3V.\r\n"); + } + else + { + SDMMC_LOG( + "\r\nError: Current card support 1.8V, but board don't support, sdmmc tried to switch back\ + to 3.3V, but failed, please check board setting.\r\n"); + } + } + + return error; +} + +static status_t SD_StopTransmission(sd_card_t *card) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDMMC_StopTransmission; + command.argument = 0U; + command.type = kCARD_CommandTypeAbort; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD12 failed with host error %d, reponse %x\r\n", error, command.response[0U]); + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t SD_Transfer(sd_card_t *card, sdmmchost_transfer_t *content, uint32_t retry) +{ + assert(content != NULL); + status_t error; + uint32_t retuningCount = 3U; + + do + { + error = SDMMCHOST_TransferFunction(card->host, content); + if (error == kStatus_Success) + { + break; + } + + /* if transfer data failed, send cmd12 to abort current transfer */ + if (content->data != NULL) + { + (void)SD_StopTransmission(card); + /* when transfer error occur, polling card status until it is ready for next data transfer, otherwise the + * retry transfer will fail again */ + error = SD_PollingCardStatusBusy(card, SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (error != kStatus_SDMMC_CardStatusIdle) + { + return kStatus_SDMMC_TransferFailed; + } + } + + if ((retry == 0U) || (error == kStatus_SDMMC_ReTuningRequest)) + { + if ((card->currentTiming == kSD_TimingSDR50Mode) || (card->currentTiming == kSD_TimingSDR104Mode)) + { + if (--retuningCount == 0U) + { + break; + } + /* perform retuning */ + if (SD_ExecuteTuning(card) != kStatus_Success) + { + error = kStatus_SDMMC_TuningFail; + SDMMC_LOG("\r\nError: retuning failed.\r\n"); + break; + } + else + { + SDMMC_LOG("\r\nlog: retuning successfully.\r\n"); + continue; + } + } + } + + if (retry != 0U) + { + retry--; + } + else + { + break; + } + + } while (true); + + return error; +} + +static status_t SD_SendCardStatus(sd_card_t *card) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + uint32_t retry = SD_CMD13_RETRY_TIMES; + + command.index = (uint32_t)kSDMMC_SendStatus; + command.argument = card->relativeAddress << 16U; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + while (retry != 0U) + { + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD13 failed with host error %d, response %x\r\n", error, command.response[0U]); + retry--; + continue; + } + else + { + if (((command.response[0U] & SDMMC_MASK(kSDMMC_R1ReadyForDataFlag)) != 0U) && + (SDMMC_R1_CURRENT_STATE(command.response[0U]) != (uint32_t)kSDMMC_R1StateProgram)) + { + error = kStatus_SDMMC_CardStatusIdle; + } + else + { + error = kStatus_SDMMC_CardStatusBusy; + } + break; + } + } + + return error; +} + +status_t SD_PollingCardStatusBusy(sd_card_t *card, uint32_t timeoutMs) +{ + assert(card != NULL); + + uint32_t statusTimeoutUs = timeoutMs * 1000U; + bool cardBusy = false; + status_t error = kStatus_SDMMC_CardStatusBusy; + + do + { + cardBusy = SDMMCHOST_IsCardBusy(card->host); + + if (cardBusy == false) + { + error = SD_SendCardStatus(card); + if (error == kStatus_SDMMC_CardStatusIdle) + { + break; + } + } + else + { + /* Delay 125us to throttle the polling rate */ + statusTimeoutUs -= SDMMC_OSADelayUs(125U); + } + + } while (statusTimeoutUs != 0U); + + return error; +} + +static status_t SD_SendWriteSuccessBlocks(sd_card_t *card, uint32_t *blocks) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + sdmmchost_data_t data = {0}; + status_t error = kStatus_Success; + uint32_t *rawBuffer = (uint32_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + + (void)memset(rawBuffer, 0, 4U); + + /* Wait for the card write process complete because of that card read process and write process use one buffer. */ + error = SD_PollingCardStatusBusy(card, SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (kStatus_SDMMC_CardStatusIdle != error) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = (uint32_t)kSD_ApplicationSendNumberWriteBlocks; + command.responseType = kCARD_ResponseTypeR1; + + data.blockSize = 4U; + data.blockCount = 1U; + data.rxData = rawBuffer; + + content.command = &command; + content.data = &data; + error = SDMMCHOST_TransferFunction(card->host, &content); + if ((kStatus_Success != error) || (((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG) != 0U)) + { + SDMMC_LOG("\r\nError: send ACMD22 failed with host error %d, response %x\r\n", error, command.response[0U]); + } + else + { + *blocks = SWAP_WORD_BYTE_SEQUENCE(*rawBuffer); + } + + return error; +} + +static status_t SD_SendRca(sd_card_t *card) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSD_SendRelativeAddress; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR6; + + content.command = &command; + content.data = NULL; + + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success == error) + { + card->relativeAddress = (command.response[0U] >> 16U); + } + else + { + SDMMC_LOG("\r\nError: send CMD3 failed with host error %d, response %x\r\n", error, command.response[0U]); + } + + return error; +} + +static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status) +{ + assert(card != NULL); + assert(status != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + sdmmchost_data_t data = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSD_Switch; + command.argument = (mode << 31U | 0x00FFFFFFU); + command.argument &= ~((uint32_t)(0xFU) << (group * 4U)); + command.argument |= (number << (group * 4U)); + command.responseType = kCARD_ResponseTypeR1; + + data.blockSize = 64U; + data.blockCount = 1U; + data.rxData = status; + + content.command = &command; + content.data = &data; + error = SDMMCHOST_TransferFunction(card->host, &content); + if ((kStatus_Success != error) || (((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG) != 0U)) + { + SDMMC_LOG("\r\n\r\nError: send CMD6 failed with host error %d, response %x\r\n", error, command.response[0U]); + } + + return error; +} + +static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr) +{ + assert(card != NULL); + assert(rawScr != NULL); + + sd_scr_t *scr; + + scr = &(card->scr); + scr->scrStructure = (uint8_t)((rawScr[0U] & 0xF0000000U) >> 28U); + scr->sdSpecification = (uint8_t)((rawScr[0U] & 0xF000000U) >> 24U); + if ((uint8_t)((rawScr[0U] & 0x800000U) >> 23U) != 0U) + { + scr->flags |= (uint16_t)kSD_ScrDataStatusAfterErase; + } + scr->sdSecurity = (uint8_t)((rawScr[0U] & 0x700000U) >> 20U); + scr->sdBusWidths = (uint8_t)((rawScr[0U] & 0xF0000U) >> 16U); + if ((uint8_t)((rawScr[0U] & 0x8000U) >> 15U) != 0U) + { + scr->flags |= (uint16_t)kSD_ScrSdSpecification3; + } + scr->extendedSecurity = (uint8_t)((rawScr[0U] & 0x7800U) >> 10U); + scr->commandSupport = (uint8_t)(rawScr[0U] & 0x3U); + scr->reservedForManufacturer = rawScr[1U]; + /* Get specification version. */ + if (scr->sdSpecification == 0U) + { + card->version = kSD_SpecificationVersion1_0; + } + else if (scr->sdSpecification == 1U) + { + card->version = kSD_SpecificationVersion1_1; + } + else if (scr->sdSpecification == 2U) + { + card->version = kSD_SpecificationVersion2_0; + if ((card->scr.flags & (uint32_t)kSD_ScrSdSpecification3) != 0U) + { + card->version = kSD_SpecificationVersion3_0; + } + } + else + { + /* reserved */ + } + + if ((card->scr.sdBusWidths & 0x4U) != 0U) + { + card->flags |= (uint32_t)kSD_Support4BitWidthFlag; + } + /* speed class control cmd */ + if ((card->scr.commandSupport & 0x01U) != 0U) + { + card->flags |= (uint32_t)kSD_SupportSpeedClassControlCmd; + } + /* set block count cmd */ + if ((card->scr.commandSupport & 0x02U) != 0U) + { + card->flags |= (uint32_t)kSD_SupportSetBlockCountCmd; + } +} + +static status_t SD_SendScr(sd_card_t *card) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + sdmmchost_data_t data = {0}; + uint32_t *rawScr = (uint32_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + status_t error = kStatus_Success; + + /* memset the global buffer */ + (void)memset(rawScr, 0, 8U); + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = (uint32_t)kSD_ApplicationSendScr; + command.responseType = kCARD_ResponseTypeR1; + command.argument = 0U; + + data.blockSize = 8U; + data.blockCount = 1U; + data.rxData = rawScr; + + content.data = &data; + content.command = &command; + error = SDMMCHOST_TransferFunction(card->host, &content); + if ((kStatus_Success != error) || (((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG) != 0U)) + { + SDMMC_LOG("\r\nError: send ACMD51 failed with host error %d, response %x\r\n", error, command.response[0U]); + } + else + { + SDMMCHOST_ConvertDataToLittleEndian(card->host, rawScr, 2U, kSDMMC_DataPacketFormatMSBFirst); + /* decode scr */ + SD_DecodeScr(card, rawScr); + } + + return error; +} + +static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function) +{ + assert(card != NULL); + + uint32_t *functionStatus = (uint32_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + uint16_t functionGroupInfo[6U] = {0}; + uint32_t currentFunctionStatus = 0U; + status_t error = kStatus_Success; + + /* memset the global buffer */ + (void)memset(functionStatus, 0, 64U); + + /* check if card support CMD6 */ + if ((card->version <= (uint32_t)kSD_SpecificationVersion1_0) || + (0U == (card->csd.cardCommandClass & (uint32_t)kSDMMC_CommandClassSwitch))) + { + SDMMC_LOG("\r\nError: current card not support CMD6\r\n"); + return kStatus_SDMMC_NotSupportYet; + } + + error = SD_SwitchFunction(card, (uint32_t)kSD_SwitchCheck, group, function, functionStatus); + /* Check if card support high speed mode. */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + /* convert to little endian sequence */ + SDMMCHOST_ConvertDataToLittleEndian(card->host, functionStatus, 5U, kSDMMC_DataPacketFormatMSBFirst); + + /* -functionStatus[0U]---bit511~bit480; + -functionStatus[1U]---bit479~bit448; + -functionStatus[2U]---bit447~bit416; + -functionStatus[3U]---bit415~bit384; + -functionStatus[4U]---bit383~bit352; + According to the "switch function status[bits 511~0]" return by switch command in mode "check function": + -Check if function 1(high speed) in function group 1 is supported by checking if bit 401 is set; + -check if function 1 is ready and can be switched by checking if bits 379~376 equal value 1; + */ + functionGroupInfo[5U] = (uint16_t)functionStatus[0U]; + functionGroupInfo[4U] = (uint16_t)(functionStatus[1U] >> 16U); + functionGroupInfo[3U] = (uint16_t)(functionStatus[1U]); + functionGroupInfo[2U] = (uint16_t)(functionStatus[2U] >> 16U); + functionGroupInfo[1U] = (uint16_t)(functionStatus[2U]); + functionGroupInfo[0U] = (uint16_t)(functionStatus[3U] >> 16U); + currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); + + /* check if function is support */ + if (((functionGroupInfo[group] & (1UL << function)) == 0U) || + ((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) + { + SDMMC_LOG("\r\nError: current card not support function %d\r\n", function); + return kStatus_SDMMC_NotSupportYet; + } + + error = SD_SwitchFunction(card, (uint32_t)kSD_SwitchSet, group, function, functionStatus); + /* Switch to high speed mode. */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + /* convert to little endian sequence */ + SDMMCHOST_ConvertDataToLittleEndian(card->host, &functionStatus[3U], 2U, kSDMMC_DataPacketFormatMSBFirst); + + /* According to the "switch function status[bits 511~0]" return by switch command in mode "set function": + -check if group 1 is successfully changed to function 1 by checking if bits 379~376 equal value 1; + */ + currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); + + if (((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) + { + SDMMC_LOG("\r\nError: switch to function %d failed\r\n", function); + return kStatus_SDMMC_SwitchFailed; + } + + return kStatus_Success; +} + +static status_t SD_SetDataBusWidth(sd_card_t *card, uint32_t width) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = (uint32_t)kSD_ApplicationSetBusWdith; + command.responseType = kCARD_ResponseTypeR1; + + if (width == (uint32_t)kSDMMC_BusWdith1Bit) + { + command.argument = 0U; + } + else if (width == (uint32_t)kSDMMC_BusWdith4Bit) + { + command.argument = 2U; + } + else + { + return kStatus_InvalidArgument; + } + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if ((kStatus_Success != error) || (((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG) != 0U)) + { + SDMMC_LOG("\r\nError: send ACMD6 failed with host error %d, response %x\r\n", error, command.response[0U]); + } + + return error; +} + +static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd) +{ + assert(card != NULL); + assert(rawCsd != NULL); + + sd_csd_t *csd; + + csd = &(card->csd); + csd->csdStructure = (uint8_t)((rawCsd[3U] & 0xC0000000U) >> 30U); + csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF0000U) >> 16U); + csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); + csd->transferSpeed = (uint8_t)(rawCsd[3U] & 0xFFU); + csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF00000U) >> 20U); + csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF0000U) >> 16U); + if ((rawCsd[2U] & 0x8000U) != 0U) + { + csd->flags |= (uint16_t)kSD_CsdReadBlockPartialFlag; + } + if ((rawCsd[2U] & 0x4000U) != 0U) + { + csd->flags |= (uint16_t)kSD_CsdReadBlockPartialFlag; + } + if ((rawCsd[2U] & 0x2000U) != 0U) + { + csd->flags |= (uint16_t)kSD_CsdReadBlockMisalignFlag; + } + if ((rawCsd[2U] & 0x1000U) != 0U) + { + csd->flags |= (uint16_t)kSD_CsdDsrImplementedFlag; + } + if (csd->csdStructure == 0U) + { + csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FFU) << 2U); + csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xC0000000U) >> 30U); + csd->readCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x38000000U) >> 27U); + csd->readCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x7000000U) >> 24U); + csd->writeCurrentVddMin = (uint8_t)((rawCsd[1U] & 0xE00000U) >> 20U); + csd->writeCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x1C0000U) >> 18U); + csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x38000U) >> 15U); + + /* Get card total block count and block size. */ + card->blockCount = ((csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U)); + card->blockSize = (1UL << (csd->readBlockLength)); + if (card->blockSize != FSL_SDMMC_DEFAULT_BLOCK_SIZE) + { + card->blockCount = (card->blockCount * card->blockSize); + card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + card->blockCount = (card->blockCount / card->blockSize); + } + } + else if (csd->csdStructure == 1U) + { + card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; + + csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FU) << 16U); + csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xFFFF0000U) >> 16U); + if (csd->deviceSize >= 0xFFFFU) + { + card->flags |= (uint32_t)kSD_SupportSdxcFlag; + } + + card->blockCount = ((csd->deviceSize + 1U) * 1024U); + } + else + { + /* not support csd version */ + } + + if ((uint8_t)((rawCsd[1U] & 0x4000U) >> 14U) != 0U) + { + csd->flags |= (uint16_t)kSD_CsdEraseBlockEnabledFlag; + } + csd->eraseSectorSize = (uint8_t)((rawCsd[1U] & 0x3F80U) >> 7U); + csd->writeProtectGroupSize = (uint8_t)(rawCsd[1U] & 0x7FU); + if ((uint8_t)(rawCsd[0U] & 0x80000000U) != 0U) + { + csd->flags |= (uint16_t)kSD_CsdWriteProtectGroupEnabledFlag; + } + csd->writeSpeedFactor = (uint8_t)((rawCsd[0U] & 0x1C000000U) >> 26U); + csd->writeBlockLength = (uint8_t)((rawCsd[0U] & 0x3C00000U) >> 22U); + if ((uint8_t)((rawCsd[0U] & 0x200000U) >> 21U) != 0U) + { + csd->flags |= (uint16_t)kSD_CsdWriteBlockPartialFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x8000U) >> 15U) != 0U) + { + csd->flags |= (uint16_t)kSD_CsdFileFormatGroupFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x4000U) >> 14U) != 0U) + { + csd->flags |= (uint16_t)kSD_CsdCopyFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x2000U) >> 13U) != 0U) + { + csd->flags |= (uint16_t)kSD_CsdPermanentWriteProtectFlag; + } + if ((uint8_t)((rawCsd[0U] & 0x1000U) >> 12U) != 0U) + { + csd->flags |= (uint16_t)kSD_CsdTemporaryWriteProtectFlag; + } + csd->fileFormat = (uint8_t)((rawCsd[0U] & 0xC00U) >> 10U); +} + +static status_t SD_SendCsd(sd_card_t *card) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDMMC_SendCsd; + command.argument = (card->relativeAddress << 16U); + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success == error) + { + (void)memcpy(card->internalBuffer, (uint8_t *)command.response, 16U); + /* The response is from bit 127:8 in R2, corrisponding to command.response[3U]:command.response[0U][31U:8]. */ + SD_DecodeCsd(card, (uint32_t *)(uint32_t)card->internalBuffer); + } + else + { + error = kStatus_SDMMC_TransferFailed; + SDMMC_LOG("\r\nError: send CMD9(get csd) failed with host error %d, response %x\r\n", error, + command.response[0U]); + } + + return error; +} + +static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid) +{ + assert(card != NULL); + assert(rawCid != NULL); + + sd_cid_t *cid; + + cid = &(card->cid); + cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF000000U) >> 24U); + cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFF00U) >> 8U); + + cid->productName[0U] = (uint8_t)((rawCid[3U] & 0xFFU)); + cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); + cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); + cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); + cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFFU)); + + cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24U); + + cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFFFU) << 8U); + cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFF000000U) >> 24U); + + cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFF00U) >> 8U); +} + +static status_t SD_AllSendCid(sd_card_t *card) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_SDMMC_TransferFailed; + + command.index = (uint32_t)kSDMMC_AllSendCid; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR2; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success == error) + { + (void)memcpy(card->internalBuffer, (uint8_t *)command.response, 16U); + SD_DecodeCid(card, (uint32_t *)(uint32_t)card->internalBuffer); + + error = kStatus_Success; + } + + return error; +} + +static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Fail; + uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; + + command.index = (uint32_t)kSD_ApplicationSendOperationCondition; + command.argument = argument; + command.responseType = kCARD_ResponseTypeR3; + + while (0U != i--) + { + if (kStatus_Success != SD_SendApplicationCmd(card, 0U)) + { + continue; + } + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send ACMD41 failed with host error %d, response %x\r\n", error, command.response[0U]); + return kStatus_SDMMC_TransferFailed; + } + + /* Wait until card exit busy state. */ + if ((command.response[0U] & SDMMC_MASK(kSD_OcrPowerUpBusyFlag)) != 0U) + { + /* high capacity check */ + if ((command.response[0U] & SDMMC_MASK(kSD_OcrCardCapacitySupportFlag)) != 0U) + { + card->flags |= (uint32_t)kSD_SupportHighCapacityFlag; + } + /* 1.8V support */ + if ((command.response[0U] & SDMMC_MASK(kSD_OcrSwitch18AcceptFlag)) != 0U) + { + card->flags |= (uint32_t)kSD_SupportVoltage180v; + } + card->ocr = command.response[0U]; + + return kStatus_Success; + } + + SDMMC_OSADelay(10U); + } + + SDMMC_LOG("\r\nError: send ACMD41 timeout\r\n"); + + return error; +} + +static status_t SD_SendInterfaceCondition(sd_card_t *card) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSD_SendInterfaceCondition; + command.argument = 0x1AAU; + command.responseType = kCARD_ResponseTypeR7; + + content.command = &command; + content.data = NULL; + do + { + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD8 failed with host error %d, response %x\r\n", error, command.response[0U]); + } + else + { + if ((command.response[0U] & 0xFFU) != 0xAAU) + { + error = kStatus_SDMMC_CardNotSupport; + SDMMC_LOG("\r\nError: card not support CMD8\r\n"); + } + else + { + error = kStatus_Success; + } + } + } while ((--i != 0U) && (error != kStatus_Success)); + + return error; +} + +static status_t SD_SelectBusTiming(sd_card_t *card) +{ + assert(card != NULL); + + status_t error = kStatus_SDMMC_SwitchBusTimingFailed; + + if (card->operationVoltage != kSDMMC_OperationVoltage180V) + { + /* group 1, function 1 ->high speed mode*/ + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); + /* If the result isn't "switching to high speed mode(50MHZ) successfully or card doesn't support high speed + * mode". Return failed status. */ + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR25HighSpeedMode; + card->busClock_Hz = + SDMMCHOST_SetCardClock(card->host, FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, SD_CLOCK_50MHZ)); + } + else + { + if (error == kStatus_SDMMC_NotSupportYet) + { + /* if not support high speed, keep the card work at default mode */ + SDMMC_LOG("\r\nNote: High speed mode is not supported by card\r\n"); + return kStatus_Success; + } + } + } + /* card is in UHS_I mode */ + else + { + do + { + if (card->currentTiming == kSD_TimingSDR12DefaultMode) + { + /* if timing not specified, probe card capability from SDR104 mode */ + card->currentTiming = kSD_TimingSDR104Mode; + } + + if (card->currentTiming == kSD_TimingSDR104Mode) + { + if ((card->host->capability & (uint32_t)kSDMMCHOST_SupportSDR104) != 0U) + { + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR104); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR104Mode; + card->busClock_Hz = SDMMCHOST_SetCardClock( + card->host, FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, SD_CLOCK_208MHZ)); + break; + } + } + SDMMC_LOG("\r\nNote: SDR104 mode is not supported\r\n"); + card->currentTiming = kSD_TimingDDR50Mode; + } + + if (card->currentTiming == kSD_TimingDDR50Mode) + { + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionDDR50); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingDDR50Mode; + card->busClock_Hz = SDMMCHOST_SetCardClock( + card->host, FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, SD_CLOCK_50MHZ)); + SDMMCHOST_EnableDDRMode(card->host, true, 0U); + break; + } + SDMMC_LOG("\r\nNote: DDR50 mode is not supported\r\n"); + card->currentTiming = kSD_TimingSDR50Mode; + } + + if (card->currentTiming == kSD_TimingSDR50Mode) + { + if ((card->host->capability & (uint32_t)kSDMMCHOST_SupportSDR50) != 0U) + { + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR50); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR50Mode; + card->busClock_Hz = SDMMCHOST_SetCardClock( + card->host, FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, SD_CLOCK_100MHZ)); + break; + } + } + SDMMC_LOG("\r\nNote: SDR50 mode is not supported\r\n"); + card->currentTiming = kSD_TimingSDR25HighSpeedMode; + } + + if (card->currentTiming == kSD_TimingSDR25HighSpeedMode) + { + error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); + if (error == kStatus_Success) + { + card->currentTiming = kSD_TimingSDR25HighSpeedMode; + card->busClock_Hz = SDMMCHOST_SetCardClock( + card->host, FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, SD_CLOCK_50MHZ)); + break; + } + } + + SDMMC_LOG("\r\nWarning: unknown timing mode\r\n"); + } while (false); + } + + if (error == kStatus_Success) + { + /* Update io strength according to different bus frequency */ + if (card->usrParam.ioStrength != NULL) + { + card->usrParam.ioStrength(card->busClock_Hz); + } + + /* SDR50 and SDR104 mode need tuning */ + if ((card->currentTiming == kSD_TimingSDR50Mode) || (card->currentTiming == kSD_TimingSDR104Mode)) + { + /* execute tuning */ + if (SD_ExecuteTuning(card) != kStatus_Success) + { + SDMMC_LOG("\r\nError: tuning failed for mode %d\r\n", card->currentTiming); + return kStatus_SDMMC_TuningFail; + } + } + } + + return error; +} + +static void SD_DecodeStatus(sd_card_t *card, uint32_t *src) +{ + assert(card != NULL); + assert(src != NULL); + + card->stat.busWidth = (uint8_t)((src[0U] & 0xC0000000U) >> 30U); /* 511-510 */ + card->stat.secureMode = (uint8_t)((src[0U] & 0x20000000U) >> 29U); /* 509 */ + card->stat.cardType = (uint16_t)((src[0U] & 0x0000FFFFU)); /* 495-480 */ + card->stat.protectedSize = src[1U]; /* 479-448 */ + card->stat.speedClass = (uint8_t)((src[2U] & 0xFF000000U) >> 24U); /* 447-440 */ + card->stat.performanceMove = (uint8_t)((src[2U] & 0x00FF0000U) >> 16U); /* 439-432 */ + card->stat.auSize = (uint8_t)((src[2U] & 0x0000F000U) >> 12U); /* 431-428 */ + card->stat.eraseSize = (uint16_t)(((src[2U] & 0x000000FFU) << 8U) | ((src[3U] & 0xFF000000U) >> 24U)); /* 423-408 */ + card->stat.eraseTimeout = (((uint8_t)((src[3U] & 0x00FF0000U) >> 16U)) & 0xFCU) >> 2U; /* 407-402 */ + card->stat.eraseOffset = ((uint8_t)((src[3U] & 0x00FF0000U) >> 16U)) & 0x3U; /* 401-400 */ + card->stat.uhsSpeedGrade = (((uint8_t)((src[3U] & 0x0000FF00U) >> 8U)) & 0xF0U) >> 4U; /* 399-396 */ + card->stat.uhsAuSize = ((uint8_t)((src[3U] & 0x0000FF00U) >> 8U)) & 0xFU; /* 395-392 */ +} + +status_t SD_ReadStatus(sd_card_t *card) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + sdmmchost_data_t data = {0}; + status_t error = kStatus_Success; + uint32_t *rawPointer = (uint32_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + + (void)memset(rawPointer, 0, 64U); + + /* wait card status ready. */ + error = SD_PollingCardStatusBusy(card, SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (kStatus_SDMMC_CardStatusIdle != error) + { + return kStatus_SDMMC_WaitWriteCompleteFailed; + } + + if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) + { + return kStatus_SDMMC_SendApplicationCommandFailed; + } + + command.index = (uint32_t)kSDMMC_SendStatus; + command.responseType = kCARD_ResponseTypeR1; + + data.blockSize = 64U; + data.blockCount = 1U; + data.rxData = rawPointer; + + content.command = &command; + content.data = &data; + error = SD_Transfer(card, &content, 3U); + if ((kStatus_Success != error) || (((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG) != 0U)) + { + SDMMC_LOG("\r\nError: send ACMD13 failed with host error %d, response %x\r\n", error, command.response[0U]); + + return kStatus_SDMMC_TransferFailed; + } + /* switch to little endian sequence */ + SDMMCHOST_ConvertDataToLittleEndian(card->host, rawPointer, 16U, kSDMMC_DataPacketFormatMSBFirst); + SD_DecodeStatus(card, rawPointer); + + return kStatus_Success; +} + +status_t SD_SelectCard(sd_card_t *card, bool isSelected) +{ + assert(card != NULL); + + return SDMMC_SelectCard(card->host, card->relativeAddress, isSelected); +} + +status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength) +{ + assert(card != NULL); + + status_t error; + uint32_t strength = (uint32_t)driverStrength; + + error = SD_SelectFunction(card, kSD_GroupDriverStrength, strength); + + return error; +} + +status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent) +{ + assert(card != NULL); + + status_t error; + uint32_t current = (uint32_t)maxCurrent; + + error = SD_SelectFunction(card, kSD_GroupCurrentLimit, current); + + return error; +} + +static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) +{ + assert(card != NULL); + assert(buffer != NULL); + assert(blockCount != 0U); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + status_t error = kStatus_Success; + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + sdmmchost_data_t data = {0}; + + if ((((card->flags & (uint32_t)kSD_SupportHighCapacityFlag) != 0U) && (blockSize != 512U)) || + (blockSize > card->blockSize) || (blockSize > card->host->maxBlockSize) || ((blockSize % 4U) != 0U)) + { + SDMMC_LOG("\r\nError: read with parameter, block size %d is not support\r\n", blockSize); + return kStatus_SDMMC_CardNotSupport; + } + + /* read command are not allowed while card is programming */ + error = SD_PollingCardStatusBusy(card, SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (kStatus_SDMMC_CardStatusIdle != error) + { + SDMMC_LOG("Error : read failed with wrong card busy\r\n"); + return kStatus_SDMMC_PollingCardIdleFailed; + } + + data.blockSize = blockSize; + data.blockCount = blockCount; + data.rxData = (uint32_t *)(uint32_t)buffer; + data.enableAutoCommand12 = true; + + command.index = (blockCount == 1U) ? (uint32_t)kSDMMC_ReadSingleBlock : (uint32_t)kSDMMC_ReadMultipleBlock; + command.argument = startBlock; + if (0U == (card->flags & (uint32_t)kSD_SupportHighCapacityFlag)) + { + command.argument *= data.blockSize; + } + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = &data; + + error = SD_Transfer(card, &content, 3U); + if (error != kStatus_Success) + { + return error; + } + + return kStatus_Success; +} + +static status_t SD_Write(sd_card_t *card, + const uint8_t *buffer, + uint32_t startBlock, + uint32_t blockSize, + uint32_t blockCount, + uint32_t *writtenBlocks) +{ + assert(card != NULL); + assert(buffer != NULL); + assert(blockCount != 0U); + assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + sdmmchost_data_t data = {0}; + status_t error; + + if ((((card->flags & (uint32_t)kSD_SupportHighCapacityFlag) != 0U) && (blockSize != 512U)) || + (blockSize > card->blockSize) || (blockSize > card->host->maxBlockSize) || ((blockSize % 4U) != 0U)) + { + SDMMC_LOG("\r\nError: write with parameter, block size %d is not support\r\n", blockSize); + return kStatus_SDMMC_CardNotSupport; + } + + /* polling card status idle */ + error = SD_PollingCardStatusBusy(card, SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (kStatus_SDMMC_CardStatusIdle != error) + { + SDMMC_LOG("Error : write failed, card status busy\r\n"); + return kStatus_SDMMC_PollingCardIdleFailed; + } + + data.enableAutoCommand12 = true; + data.blockSize = blockSize; + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + command.index = (blockCount == 1U) ? (uint32_t)kSDMMC_WriteSingleBlock : (uint32_t)kSDMMC_WriteMultipleBlock; + command.argument = startBlock; + if (0U == (card->flags & (uint32_t)kSD_SupportHighCapacityFlag)) + { + command.argument *= data.blockSize; + } + + *writtenBlocks = blockCount; + data.blockCount = blockCount; + data.txData = (const uint32_t *)(uint32_t)buffer; + + content.command = &command; + content.data = &data; + + error = SD_Transfer(card, &content, 3U); + if (error != kStatus_Success) + { + error = SD_SendWriteSuccessBlocks(card, writtenBlocks); + /* check the successfully written block */ + if (error == kStatus_Success) + { + if (*writtenBlocks != 0U) + { + /* written success, but not all the blocks are written */ + error = kStatus_Success; + } + } + SDMMC_LOG("\r\nWarning: write failed with block count %d, successed %d\r\n", blockCount, *writtenBlocks); + } + + return error; +} + +static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount, uint32_t timeout) +{ + assert(card != NULL); + assert(blockCount != 0U); + assert(timeout != 0U); + + uint32_t eraseBlockStart; + uint32_t eraseBlockEnd; + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + /* polling card status idle */ + error = SD_PollingCardStatusBusy(card, SD_CARD_ACCESS_WAIT_IDLE_TIMEOUT); + if (kStatus_SDMMC_CardStatusIdle != error) + { + SDMMC_LOG("Error : write failed, card status busy\r\n"); + return kStatus_SDMMC_PollingCardIdleFailed; + } + + eraseBlockStart = startBlock; + eraseBlockEnd = eraseBlockStart + blockCount - 1U; + if (0U == (card->flags & (uint32_t)kSD_SupportHighCapacityFlag)) + { + eraseBlockStart = eraseBlockStart * FSL_SDMMC_DEFAULT_BLOCK_SIZE; + eraseBlockEnd = eraseBlockEnd * FSL_SDMMC_DEFAULT_BLOCK_SIZE; + } + + /* Send ERASE_WRITE_BLOCK_START command to set the start block number to erase. */ + command.index = (uint32_t)kSD_EraseWriteBlockStart; + command.argument = eraseBlockStart; + command.responseType = kCARD_ResponseTypeR1; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = NULL; + error = SD_Transfer(card, &content, 1U); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD32(erase start) failed with host error %d, response %x\r\n", error, + command.response[0U]); + return kStatus_SDMMC_TransferFailed; + } + + /* Send ERASE_WRITE_BLOCK_END command to set the end block number to erase. */ + command.index = (uint32_t)kSD_EraseWriteBlockEnd; + command.argument = eraseBlockEnd; + + content.command = &command; + content.data = NULL; + error = SD_Transfer(card, &content, 0U); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD33(erase end) failed with host error %d, response %x\r\n", error, + command.response[0U]); + return kStatus_SDMMC_TransferFailed; + } + + /* Send ERASE command to start erase process. */ + command.index = (uint32_t)kSDMMC_Erase; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1b; + command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; + + content.command = &command; + content.data = NULL; + error = SD_Transfer(card, &content, 0U); + if (kStatus_Success != error) + { + SDMMC_LOG("\r\nError: send CMD38(erase) failed with host error %d, response %x\r\n", error, + command.response[0U]); + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +bool SD_CheckReadOnly(sd_card_t *card) +{ + assert(card != NULL); + + return (((card->csd.flags & (uint16_t)kSD_CsdPermanentWriteProtectFlag) != 0U) || + ((card->csd.flags & (uint16_t)kSD_CsdTemporaryWriteProtectFlag)) != 0U); +} + +status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card != NULL); + assert(buffer != NULL); + assert(blockCount != 0U); + assert((blockCount + startBlock) <= card->blockCount); + + uint32_t blockCountOneTime; + uint32_t blockLeft; + uint32_t blockDone = 0U; + uint8_t *nextBuffer = buffer; + bool dataAddrAlign = true; + uint8_t *alignBuffer = (uint8_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + status_t error = kStatus_Success; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + blockLeft = blockCount; + + while (blockLeft != 0U) + { + nextBuffer = (uint8_t *)((uint32_t)buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + if ((!card->noInteralAlign) && (!dataAddrAlign || ((((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U)) != 0U))) + { + blockCountOneTime = 1; + (void)memset(alignBuffer, 0, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + dataAddrAlign = false; + blockLeft -= blockCountOneTime; + } + else + { + if (blockLeft > card->host->maxBlockCount) + { + blockLeft = (blockLeft - card->host->maxBlockCount); + blockCountOneTime = card->host->maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + } + + error = SD_Read(card, dataAddrAlign ? nextBuffer : alignBuffer, (startBlock + blockDone), + FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime); + if (kStatus_Success != error) + { + error = kStatus_SDMMC_TransferFailed; + break; + } + + blockDone += blockCountOneTime; + + if (!card->noInteralAlign && (!dataAddrAlign)) + { + (void)memcpy(nextBuffer, alignBuffer, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) +{ + assert(card != NULL); + assert(buffer != NULL); + assert(blockCount != 0U); + assert((blockCount + startBlock) <= card->blockCount); + + uint32_t blockCountOneTime = 0U; /* The block count can be wrote in one time sending WRITE_BLOCKS command. */ + uint32_t blockWrittenOneTime = 0U; + uint32_t blockLeft = 0U; /* Left block count to be wrote. */ + const uint8_t *nextBuffer; + bool dataAddrAlign = true; + uint8_t *alignBuffer = (uint8_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + status_t error = kStatus_Success; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + blockLeft = blockCount; + while (blockLeft != 0U) + { + nextBuffer = (uint8_t *)((uint32_t)buffer + (blockCount - blockLeft) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); + if (!card->noInteralAlign && (!dataAddrAlign || ((((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U)) != 0U))) + { + blockCountOneTime = 1; + (void)memcpy(alignBuffer, nextBuffer, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + dataAddrAlign = false; + } + else + { + if (blockLeft > card->host->maxBlockCount) + { + blockCountOneTime = card->host->maxBlockCount; + } + else + { + blockCountOneTime = blockLeft; + } + } + + error = SD_Write(card, dataAddrAlign ? nextBuffer : alignBuffer, (startBlock + blockCount - blockLeft), + FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime, &blockWrittenOneTime); + if (kStatus_Success != error) + { + error = kStatus_SDMMC_TransferFailed; + break; + } + + blockLeft -= blockWrittenOneTime; + + if ((!card->noInteralAlign) && !dataAddrAlign) + { + (void)memset(alignBuffer, 0, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + } + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +static uint32_t SD_CalculateEraseTimeout(sd_card_t *card, uint32_t blockCount, uint32_t auSize) +{ + uint32_t auCount = blockCount / (auSize / FSL_SDMMC_DEFAULT_BLOCK_SIZE); + uint32_t timeout_ms = 0U; + + if (auCount == 0U) + { + auCount = 1U; + } + + timeout_ms = auCount * 250U; /* 250 ms erase timeout per AU by default */ + + if ((card->stat.eraseTimeout != 0U) && (card->stat.eraseSize != 0U)) + { + /* timeout determined by the block count to be erased and the au size */ + timeout_ms = auCount * (((uint32_t)card->stat.eraseTimeout * 1000U) / (uint32_t)card->stat.eraseSize + 500U) + + card->stat.eraseOffset * 1000U; + } + + /* convert to ms */ + return timeout_ms < 1000U ? 1000U : timeout_ms; +} + +status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount) +{ + assert(card != NULL); + assert(blockCount != 0U); + assert((blockCount + startBlock) <= card->blockCount); + + uint32_t blockCountOneTime; /* The block count can be erased in one time sending ERASE_BLOCKS command. */ + uint32_t blockDone = 0U; /* The block count has been erased. */ + uint32_t blockLeft; /* Left block count to be erase. */ + status_t error = kStatus_Success; + uint32_t onetimeMaxEraseBlocks = 0U; + uint32_t auSize = 0U; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + /* sdsc card erasable sector is determined by CSD register */ + if (card->csd.csdStructure == 0U) + { + onetimeMaxEraseBlocks = card->csd.eraseSectorSize + 1UL; + } + else + { + /* limit one time maximum erase size to 1 AU */ + if ((card->stat.auSize >= SD_AU_START_VALUE)) + { + /* UHS card should use uhs au size field */ + if (card->operationVoltage == kSDMMC_OperationVoltage180V) + { + auSize = s_sdAuSizeMap[card->stat.uhsAuSize == 0U ? card->stat.auSize : card->stat.uhsAuSize]; + onetimeMaxEraseBlocks = auSize / FSL_SDMMC_DEFAULT_BLOCK_SIZE; + } + else + { + auSize = s_sdAuSizeMap[card->stat.auSize]; + onetimeMaxEraseBlocks = auSize / FSL_SDMMC_DEFAULT_BLOCK_SIZE; + } + + if (card->stat.eraseSize != 0U) + { + onetimeMaxEraseBlocks *= card->stat.eraseSize; + } + } + } + + if (onetimeMaxEraseBlocks == 0U) + { + SDMMC_LOG( + "Warning: AU size in sd descriptor is not set properly, please check if SD_ReadStatus is called before\ + SD_EraseBlocks\r\n"); + error = kStatus_SDMMC_AuSizeNotSetProperly; + } + else + { + blockLeft = blockCount; + while (blockLeft != 0U) + { + if (blockLeft > onetimeMaxEraseBlocks) + { + blockCountOneTime = onetimeMaxEraseBlocks; + blockLeft = blockLeft - blockCountOneTime; + } + else + { + blockCountOneTime = blockLeft; + blockLeft = 0U; + } + + error = SD_Erase(card, (startBlock + blockDone), blockCountOneTime, + SD_CalculateEraseTimeout(card, blockCountOneTime, auSize)); + if (error != kStatus_Success) + { + break; + } + + blockDone += blockCountOneTime; + } + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +static status_t SD_ProbeBusVoltage(sd_card_t *card) +{ + assert(card != NULL); + + uint32_t applicationCommand41Argument = 0U; + status_t error = kStatus_Success; + + /* 3.3V voltage should be supported as default */ + applicationCommand41Argument |= + SDMMC_MASK(kSD_OcrVdd29_30Flag) | SDMMC_MASK(kSD_OcrVdd32_33Flag) | SDMMC_MASK(kSD_OcrVdd33_34Flag); + + if ((card->usrParam.ioVoltage != NULL) && (card->usrParam.ioVoltage->type != kSD_IOVoltageCtrlNotSupport) && + ((card->host->capability & (uint32_t)kSDMMCHOST_SupportVoltage1v8) != 0U) && + ((card->host->capability & ((uint32_t)kSDMMCHOST_SupportSDR104 | (uint32_t)kSDMMCHOST_SupportSDR50 | + (uint32_t)kSDMMCHOST_SupportDDRMode)) != 0U)) + { + /* allow user select the work voltage, if not select, sdmmc will handle it automatically */ + applicationCommand41Argument |= SDMMC_MASK(kSD_OcrSwitch18RequestFlag); + /* reset to 3v3 signal voltage */ + if (SD_SwitchIOVoltage(card, kSDMMC_OperationVoltage330V) == kStatus_Success) + { + /* Host changed the operation signal voltage successfully, then card need power reset */ + SD_SetCardPower(card, false); + SD_SetCardPower(card, true); + } + } + + card->operationVoltage = kSDMMC_OperationVoltage330V; + + /* send card active */ + SDMMCHOST_SendCardActive(card->host); + + do + { + /* card go idle */ + if (kStatus_Success != SD_GoIdle(card)) + { + error = kStatus_SDMMC_GoIdleFailed; + break; + } + + error = SD_SendInterfaceCondition(card); + /* Check card's supported interface condition. */ + if (kStatus_Success == error) + { + /* SDHC or SDXC card */ + applicationCommand41Argument |= SDMMC_MASK(kSD_OcrHostCapacitySupportFlag); + card->flags |= (uint32_t)kSD_SupportSdhcFlag; + } + else + { + /* SDSC card */ + if (kStatus_Success != SD_GoIdle(card)) + { + error = kStatus_SDMMC_GoIdleFailed; + break; + } + } + error = SD_ApplicationSendOperationCondition(card, applicationCommand41Argument); + /* Set card interface condition according to SDHC capability and card's supported interface condition. */ + if (kStatus_Success != error) + { + error = kStatus_SDMMC_HandShakeOperationConditionFailed; + break; + } + + /* check if card support 1.8V */ + if ((card->flags & (uint32_t)kSD_SupportVoltage180v) != 0U) + { + if ((card->usrParam.ioVoltage != NULL) && (card->usrParam.ioVoltage->type == kSD_IOVoltageCtrlNotSupport)) + { + break; + } + + error = SD_SwitchVoltage(card, kSDMMC_OperationVoltage180V); + if (kStatus_SDMMC_SwitchVoltageFail == error) + { + break; + } + + if (error == kStatus_SDMMC_SwitchVoltage18VFail33VSuccess) + { + applicationCommand41Argument &= ~SDMMC_MASK(kSD_OcrSwitch18RequestFlag); + card->flags &= ~(uint32_t)kSD_SupportVoltage180v; + continue; + } + else + { + card->operationVoltage = kSDMMC_OperationVoltage180V; + break; + } + } + break; + } while (true); + + return error; +} + +static status_t sdcard_init(sd_card_t *card) +{ + assert(card != NULL); + assert(card->isHostReady == true); + status_t error = kStatus_Success; + + /* reset variables */ + card->flags = 0U; + /* set DATA bus width */ + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith1Bit); + /*set card freq to 400KHZ*/ + card->busClock_Hz = SDMMCHOST_SetCardClock(card->host, SDMMC_CLOCK_400KHZ); + + error = SD_ProbeBusVoltage(card); + /* probe bus voltage*/ + if (error != kStatus_Success) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + error = SD_AllSendCid(card); + /* Initialize card if the card is SD card. */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_AllSendCidFailed; + } + + error = SD_SendRca(card); + if (kStatus_Success != error) + { + return kStatus_SDMMC_SendRelativeAddressFailed; + } + + error = SD_SendCsd(card); + if (kStatus_Success != error) + { + return kStatus_SDMMC_SendCsdFailed; + } + + error = SD_SelectCard(card, true); + if (kStatus_Success != error) + { + return kStatus_SDMMC_SelectCardFailed; + } + + /* Set to max frequency in non-high speed mode. */ + card->busClock_Hz = SDMMCHOST_SetCardClock(card->host, SD_CLOCK_25MHZ); + + error = SD_SendScr(card); + if (kStatus_Success != error) + { + return kStatus_SDMMC_SendScrFailed; + } + + /* Set to 4-bit data bus mode. */ + if ((card->flags & (uint32_t)kSD_Support4BitWidthFlag) != 0U) + { + error = SD_SetDataBusWidth(card, kSDMMC_BusWdith4Bit); + if (kStatus_Success != error) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith4Bit); + } + + /* try to get card current status */ + error = SD_ReadStatus(card); + if (kStatus_Success != error) + { + return kStatus_SDMMC_SendScrFailed; + } + + error = SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE); + /* set block size */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + error = SD_SelectBusTiming(card); + /* select bus timing */ + if (kStatus_Success != error) + { + return kStatus_SDMMC_SwitchBusTimingFailed; + } + + return kStatus_Success; +} + +status_t SD_CardInit(sd_card_t *card) +{ + assert(card != NULL); + + status_t error = kStatus_Success; + /* create mutex lock */ + (void)SDMMC_OSAMutexCreate(&card->lock); + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + SD_SetCardPower(card, true); + + error = sdcard_init(card); + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +void SD_CardDeinit(sd_card_t *card) +{ + assert(card != NULL); + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + (void)SD_SelectCard(card, false); + SD_HostDoReset(card); + SD_SetCardPower(card, false); + (void)SDMMC_OSAMutexDestroy(&card->lock); +} + +status_t SD_HostInit(sd_card_t *card) +{ + assert(card != NULL); + assert(card->usrParam.cd != NULL); + + status_t error = kStatus_Success; + + if (!card->isHostReady) + { + error = SDMMCHOST_Init(card->host); + if (error != kStatus_Success) + { + return kStatus_Fail; + } + } + + if ((card->usrParam.cd->type == kSD_DetectCardByHostCD) || (card->usrParam.cd->type == kSD_DetectCardByHostDATA3)) + { + (void)SDMMCHOST_CardDetectInit(card->host, card->usrParam.cd); + } + + /* set the host status flag, after the card re-plug in, don't need init host again */ + card->isHostReady = true; + + return kStatus_Success; +} + +void SD_HostDeinit(sd_card_t *card) +{ + assert(card != NULL); + + SDMMCHOST_Deinit(card->host); + /* should re-init host */ + card->isHostReady = false; +} + +void SD_SetCardPower(sd_card_t *card, bool enable) +{ + assert(card != NULL); + + uint32_t powerDelay = 0U; + + if (card->usrParam.pwr != NULL) + { + card->usrParam.pwr(enable); + } + else + { + SDMMCHOST_SetCardPower(card->host, enable); + } + + if (enable) + { + powerDelay = card->usrParam.powerOnDelayMS == 0U ? SD_POWER_ON_DELAY : card->usrParam.powerOnDelayMS; + } + else + { + powerDelay = card->usrParam.powerOffDelayMS == 0U ? SD_POWER_OFF_DELAY : card->usrParam.powerOffDelayMS; + } + + SDMMC_OSADelay(powerDelay); +} + +bool SD_IsCardPresent(sd_card_t *card) +{ + assert(card != NULL); + assert(card->usrParam.cd != NULL); + + if (card->usrParam.cd->type == kSD_DetectCardByGpioCD) + { + if (card->usrParam.cd->cardDetected == NULL) + { + return false; + } + return card->usrParam.cd->cardDetected(); + } + else + { + if (card->isHostReady == false) + { + return false; + } + + if (SDMMCHOST_CardDetectStatus(card->host) == (uint32_t)kSD_Removed) + { + return false; + } + } + + return true; +} + +status_t SD_PollingCardInsert(sd_card_t *card, uint32_t status) +{ + assert(card != NULL); + assert(card->usrParam.cd != NULL); + + if (card->usrParam.cd->type == kSD_DetectCardByGpioCD) + { + if (card->usrParam.cd->cardDetected == NULL) + { + return kStatus_Fail; + } + + do + { + if ((card->usrParam.cd->cardDetected() == true) && (status == (uint32_t)kSD_Inserted)) + { + SDMMC_OSADelay(card->usrParam.cd->cdDebounce_ms); + if (card->usrParam.cd->cardDetected() == true) + { + break; + } + } + + if ((card->usrParam.cd->cardDetected() == false) && (status == (uint32_t)kSD_Removed)) + { + break; + } + } while (true); + } + else + { + if (card->isHostReady == false) + { + return kStatus_Fail; + } + + if (SDMMCHOST_PollingCardDetectStatus(card->host, status, ~0U) != kStatus_Success) + { + return kStatus_Fail; + } + } + + return kStatus_Success; +} + +status_t SD_Init(sd_card_t *card) +{ + assert(card != NULL); + + status_t error = kStatus_Success; + + if (!card->isHostReady) + { + error = SD_HostInit(card); + if (error != kStatus_Success) + { + error = kStatus_SDMMC_HostNotReady; + } + } + else + { + SD_HostDoReset(card); + } + + if (kStatus_Success == error) + { + if (SD_PollingCardInsert(card, kSD_Inserted) != kStatus_Success) + { + error = kStatus_SDMMC_CardDetectFailed; + } + else + { + error = SD_CardInit(card); + if (error != kStatus_Success) + { + error = kStatus_SDMMC_CardInitFailed; + } + } + } + + return error; +} + +void SD_Deinit(sd_card_t *card) +{ + /* card deinitialize */ + SD_CardDeinit(card); + /* host deinitialize */ + SD_HostDeinit(card); +} + +void SD_HostDoReset(sd_card_t *card) +{ + SDMMCHOST_Reset(card->host); +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/fsl_sd.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/fsl_sd.h new file mode 100644 index 0000000000..ac05b61812 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sd/fsl_sd.h @@ -0,0 +1,349 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FSL_SD_H_ +#define _FSL_SD_H_ + +#include "fsl_sdmmc_common.h" +/*! + * @addtogroup sdcard SD Card Driver + * @ingroup card + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief Driver version. */ +#define FSL_SD_DRIVER_VERSION (MAKE_VERSION(2U, 4U, 0U)) /*2.4.0*/ + +/*! @brief SD card flags + * @anchor _sd_card_flag + */ +enum +{ + kSD_SupportHighCapacityFlag = (1U << 1U), /*!< Support high capacity */ + kSD_Support4BitWidthFlag = (1U << 2U), /*!< Support 4-bit data width */ + kSD_SupportSdhcFlag = (1U << 3U), /*!< Card is SDHC */ + kSD_SupportSdxcFlag = (1U << 4U), /*!< Card is SDXC */ + kSD_SupportVoltage180v = (1U << 5U), /*!< card support 1.8v voltage*/ + kSD_SupportSetBlockCountCmd = (1U << 6U), /*!< card support cmd23 flag*/ + kSD_SupportSpeedClassControlCmd = (1U << 7U), /*!< card support speed class control flag */ +}; + +/*! + * @brief SD card state + * + * Define the card structure including the necessary fields to identify and describe the card. + */ +typedef struct _sd_card +{ + sdmmchost_t *host; /*!< Host configuration */ + + sd_usr_param_t usrParam; /*!< user parameter */ + bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ + + bool noInteralAlign; /*!< used to enable/disable the functionality of the exchange buffer */ + uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */ + uint32_t relativeAddress; /*!< Relative address of the card */ + uint32_t version; /*!< Card version */ + uint32_t flags; /*!< Flags in _sd_card_flag */ + uint8_t internalBuffer[FSL_SDMMC_CARD_INTERNAL_BUFFER_SIZE]; /*!< internal buffer */ + uint32_t ocr; /*!< Raw OCR content */ + sd_cid_t cid; /*!< CID */ + sd_csd_t csd; /*!< CSD */ + sd_scr_t scr; /*!< SCR */ + sd_status_t stat; /*!< sd 512 bit status */ + uint32_t blockCount; /*!< Card total block number */ + uint32_t blockSize; /*!< Card block size */ + sd_timing_mode_t currentTiming; /*!< current timing mode */ + sd_driver_strength_t driverStrength; /*!< driver strength */ + sd_max_current_t maxCurrent; /*!< card current limit */ + sdmmc_operation_voltage_t operationVoltage; /*!< card operation voltage */ + sdmmc_osa_mutex_t lock; /*!< card access lock */ +} sd_card_t; + +/************************************************************************************************* + * API + ************************************************************************************************/ +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SDCARD Function + * @{ + */ + +/*! + * @brief Initializes the card on a specific host controller. + * This function initializes the card on a specific host controller, it is consist of + * host init, card detect, card init function, however user can ignore this high level function, + * instead of use the low level function, such as SD_CardInit, SD_HostInit, SD_CardDetect. + * + * Thread safe function, please note that the function will create the mutex lock dynamically by default, + * so to avoid the mutex create redundantly, application must follow bellow sequence for card re-initialization + * @code + * SD_Deinit(card); + * SD_Init(card); + * @endcode + * + * @param card Card descriptor. + * @retval #kStatus_SDMMC_HostNotReady host is not ready. + * @retval #kStatus_SDMMC_GoIdleFailed Go idle failed. + * @retval #kStatus_SDMMC_NotSupportYet Card not support. + * @retval #kStatus_SDMMC_HandShakeOperationConditionFailed Send operation condition failed. + * @retval #kStatus_SDMMC_AllSendCidFailed Send CID failed. + * @retval #kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed. + * @retval #kStatus_SDMMC_SendCsdFailed Send CSD failed. + * @retval #kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. + * @retval #kStatus_SDMMC_SendScrFailed Send SCR failed. + * @retval #kStatus_SDMMC_SetDataBusWidthFailed Set bus width failed. + * @retval #kStatus_SDMMC_SwitchBusTimingFailed Switch high speed failed. + * @retval #kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval #kStatus_Success Operate successfully. + */ +status_t SD_Init(sd_card_t *card); + +/*! + * @brief Deinitializes the card. + * This function deinitializes the specific card and host. + * Please note it is a thread safe function. + * + * @param card Card descriptor. + */ +void SD_Deinit(sd_card_t *card); + +/*! + * @brief Initializes the card. + * + * This function initializes the card only, make sure the host is ready when call this function, + * otherwise it will return kStatus_SDMMC_HostNotReady. + * + * Thread safe function, please note that the function will create the mutex lock dynamically by default, + * so to avoid the mutex create redundantly, application must follow bellow sequence for card re-initialization + * @code + * SD_CardDeinit(card); + * SD_CardInit(card); + * @endcode + * + * @param card Card descriptor. + * @retval #kStatus_SDMMC_HostNotReady host is not ready. + * @retval #kStatus_SDMMC_GoIdleFailed Go idle failed. + * @retval #kStatus_SDMMC_NotSupportYet Card not support. + * @retval #kStatus_SDMMC_HandShakeOperationConditionFailed Send operation condition failed. + * @retval #kStatus_SDMMC_AllSendCidFailed Send CID failed. + * @retval #kStatus_SDMMC_SendRelativeAddressFailed Send relative address failed. + * @retval #kStatus_SDMMC_SendCsdFailed Send CSD failed. + * @retval #kStatus_SDMMC_SelectCardFailed Send SELECT_CARD command failed. + * @retval #kStatus_SDMMC_SendScrFailed Send SCR failed. + * @retval #kStatus_SDMMC_SetDataBusWidthFailed Set bus width failed. + * @retval #kStatus_SDMMC_SwitchBusTimingFailed Switch high speed failed. + * @retval #kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. + * @retval #kStatus_Success Operate successfully. + */ +status_t SD_CardInit(sd_card_t *card); + +/*! + * @brief Deinitializes the card. + * + * This function deinitializes the specific card. + * Please note it is a thread safe function. + * + * + * @param card Card descriptor. + */ +void SD_CardDeinit(sd_card_t *card); + +/*! + * @brief initialize the host. + * + * This function deinitializes the specific host. + * + * @param card Card descriptor. + */ +status_t SD_HostInit(sd_card_t *card); + +/*! + * @brief Deinitializes the host. + * + * This function deinitializes the host. + * + * @param card Card descriptor. + */ +void SD_HostDeinit(sd_card_t *card); + +/*! + * @brief reset the host. + * + * This function reset the specific host. + * + * @param card Card descriptor. + */ +void SD_HostDoReset(sd_card_t *card); + +/*! + * @brief set card power. + * + * The power off operation depend on host or the user define power on function. + * @param card card descriptor. + * @param enable true is power on, false is power off. + */ +void SD_SetCardPower(sd_card_t *card, bool enable); + +/*! + * @brief sd wait card detect function. + * + * Detect card through GPIO, CD, DATA3. + * @param card card descriptor. + * @param status detect status, kSD_Inserted or kSD_Removed. + */ +status_t SD_PollingCardInsert(sd_card_t *card, uint32_t status); + +/*! + * @brief sd card present check function. + * + * @param card card descriptor. + */ +bool SD_IsCardPresent(sd_card_t *card); + +/*! + * @brief Checks whether the card is write-protected. + * + * This function checks if the card is write-protected via the CSD register. + * + * @param card The specific card. + * @retval true Card is read only. + * @retval false Card isn't read only. + */ +bool SD_CheckReadOnly(sd_card_t *card); + +/*! + * @brief Send SELECT_CARD command to set the card to be transfer state or not. + * + * @param card Card descriptor. + * @param isSelected True to set the card into transfer state, false to disselect. + * @retval #kStatus_SDMMC_TransferFailed Transfer failed. + * @retval #kStatus_Success Operate successfully. + */ +status_t SD_SelectCard(sd_card_t *card, bool isSelected); + +/*! + * @brief Send ACMD13 to get the card current status. + * + * @param card Card descriptor. + * @retval #kStatus_SDMMC_TransferFailed Transfer failed. + * @retval #kStatus_SDMMC_SendApplicationCommandFailed send application command failed. + * @retval #kStatus_Success Operate successfully. + */ +status_t SD_ReadStatus(sd_card_t *card); + +/*! + * @brief Reads blocks from the specific card. + * + * This function reads blocks from the specific card with default block size defined by the + * SDHC_CARD_DEFAULT_BLOCK_SIZE. + * + * Please note it is a thread safe function. + * + * @param card Card descriptor. + * @param buffer The buffer to save the data read from card. + * @param startBlock The start block index. + * @param blockCount The number of blocks to read. + * @retval #kStatus_InvalidArgument Invalid argument. + * @retval #kStatus_SDMMC_CardNotSupport Card not support. + * @retval #kStatus_SDMMC_NotSupportYet Not support now. + * @retval #kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval #kStatus_SDMMC_TransferFailed Transfer failed. + * @retval #kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval #kStatus_Success Operate successfully. + */ +status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Writes blocks of data to the specific card. + * + * This function writes blocks to the specific card with default block size 512 bytes. + * + * Please note, + * 1. It is a thread safe function. + * 2. It is a async write function which means that the card status may still busy after the function return. + * Application can call function SD_PollingCardStatusBusy to wait card status idle after the write operation. + * + * @param card Card descriptor. + * @param buffer The buffer holding the data to be written to the card. + * @param startBlock The start block index. + * @param blockCount The number of blocks to write. + * @retval #kStatus_InvalidArgument Invalid argument. + * @retval #kStatus_SDMMC_NotSupportYet Not support now. + * @retval #kStatus_SDMMC_CardNotSupport Card not support. + * @retval #kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval #kStatus_SDMMC_TransferFailed Transfer failed. + * @retval #kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. + * @retval #kStatus_Success Operate successfully. + */ +status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief Erases blocks of the specific card. + * + * This function erases blocks of the specific card with default block size 512 bytes. + * + * Please note, + * 1. It is a thread safe function. + * 2. It is a async erase function which means that the card status may still busy after the function return. + * Application can call function SD_PollingCardStatusBusy to wait card status idle after the erase operation. + * + * @param card Card descriptor. + * @param startBlock The start block index. + * @param blockCount The number of blocks to erase. + * @retval #kStatus_InvalidArgument Invalid argument. + * @retval #kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval #kStatus_SDMMC_TransferFailed Transfer failed. + * @retval #kStatus_SDMMC_WaitWriteCompleteFailed Send status failed. + * @retval #kStatus_Success Operate successfully. + */ +status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount); + +/*! + * @brief select card driver strength + * select card driver strength + * @param card Card descriptor. + * @param driverStrength Driver strength + */ +status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength); + +/*! + * @brief select max current + * select max operation current + * @param card Card descriptor. + * @param maxCurrent Max current + */ +status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent); + +/*! + * @brief Polling card idle status. + * + * This function can be used to polling the status from busy to Idle, the function will return if the card + * status idle or timeout. + * + * @param card Card descriptor. + * @param timeoutMs polling card status timeout value. + * @retval kStatus_Success Operate successfully. + * @retval kStatus_SDMMC_WaitWriteCompleteFailed CMD13 transfer failed. + * @retval kStatus_SDMMC_PollingCardIdleFailed, polling card DAT0 idle failed. + */ +status_t SD_PollingCardStatusBusy(sd_card_t *card, uint32_t timeoutMs); + +/* @} */ + +#if defined(__cplusplus) +} +#endif +/*! @} */ +#endif /* _FSL_SD_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sdio/ChangeLogKSDK.txt b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sdio/ChangeLogKSDK.txt new file mode 100644 index 0000000000..e4d350be2b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sdio/ChangeLogKSDK.txt @@ -0,0 +1,98 @@ +/*! +@page middleware_log Middleware Change Log + +@section sdio SDIO Card driver for MCUXpresso SDK +The current driver version is 2.4.0. + + - 2.4.0 + - Improvements + - Removed deprecated api in sdio driver. + - Improved the signal line voltage switch flow. + - Added powerOnDelayMS/powerOffDelayMS in sdio_usr_param_t to allow redefine the default power on/off delay. + - Added mutual exclusive access for init/deinit/direct/extend function. + - Fixed violations of MISRA C-2012 rule 4.7, 17.7, 10.1, 12.2. + + - 2.3.3 + - Bug Fixes + - Fixed logical dead code coverity issue. + - Improvements + - Removed deprecated api in sdio driver. + + - 2.3.2 + - Improvements + - Added host SDR timing mode capability validation during card initialization. + - Used cache line size align buffer for SDIO initialization api. + - Bug Fixes + - Fixed violations of MISRA C-2012 rule 11.9, 15.7, 4.7, 16.4, 10.1, 10.3, 10.4, 11.3, 14.4, 10.6, 17.7, 16.1, 16.3. + + - 2.3.1 + - Improvements + - Moved power off function after card detect in SD_Init for DAT3 detect card feature. + + - 2.3.0 + - Improvements + - Marked api SDIO_HostReset/SDIO_PowerOnCard/SDIO_PowerOffCard/SDIO_WaitCardDetectStatus as deprecated. + - Added new api SDIO_SetCardPower/SDIO_PollingCardDetectStatus/SDIO_HostDoReset. + - Added internalBuffer in sdio_card_t for card register content extract and improve the data access efficiency. + - Added retry function after switch to target timing failed in SDIO_SelectBusTiming. + - Changed defalut bus clock from 400KHZ to 25MHZ. + + - 2.2.13 + - Improvements + - Removed the sdio card interrupt from sdio host initialization, since the card interrupt enablement should be determined by application. + - Bug Fixes + - Fixed Out-of-bounds write Coverity issue. + + - 2.2.12 + - Improvements + - Added manual tuning function for looking for the tuning window automatically. + - Fixed the build warning by changing the old style function declaration static + status_t inline to static inline status_t(found by adding + -Wold-style-declaration in armgcc build flag). + - Fixed the fall through build warning by adding SUPPRESS_FALL_THROUGH_WARNING() in sdio driver. + + - 2.2.11 + - Bug Fixes + - Added check card async interrupt capability in function + SDIO_GetCardCapability. + - Fixed OUT OF BOUNDS access in function SDIO_IO_Transfer. + + - 2.2.10 + - Bug Fixes + - Fixed SDIO card driver get an incorrect io number when the card io number is + bigger than 2. + - Improvements + - Added SDIO 3.0 support. + - Added API SDIO_IO_RW_Direct for direct read/write card register access. + + - 2.2.9 + - Improvements + - Added API SDIO_SetIOIRQHandler/SDIO_HandlePendingIOInterrupt to handle multi io pending IRQ. + + - 2.2.8 + - Improvements + - Updated sdmmc to support SDIO interrupt. + - Added API SDIO_GetPendingInterrupt to get the pending io interrupt. + + - 2.2.7 + - Bug Fixes + - Fixed MDK 66-D warning. + + - 2.2.6 + - Improvements + - Added an unify transfer interface for SDIO. + - Bug Fixes + - Fixed Wrong pointer address used by SDMMCHOST_Init. + + - 2.1.5 + - Improvements + - Improved SDIO card init sequence and add retry option for SDIO_SwitchToHighSpeed function. + + - 2.1.4 + - Improvements + - Added Go_Idle function for SDIO card. + + - 2.0.0 + - Initial version. + +*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sdio/fsl_sdio.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sdio/fsl_sdio.c new file mode 100644 index 0000000000..25504a5939 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sdio/fsl_sdio.c @@ -0,0 +1,2109 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "fsl_sdio.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief define the tuple number will be read during init */ +#define SDIO_COMMON_CIS_TUPLE_NUM (3U) +/*! @brief SDIO retry times */ +#define SDIO_RETRY_TIMES (1000U) +/*!@brief power reset delay */ +/*!@brief power reset delay */ +#define SDIO_POWER_ON_DELAY (400U) +#define SDIO_POWER_OFF_DELAY (100U) +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/*! + * @brief probe bus voltage. + * @param card Card descriptor. + */ +static status_t SDIO_ProbeBusVoltage(sdio_card_t *card); + +/*! + * @brief send card operation condition + * @param card Card descriptor. + * @param command argment + * @param accept1V8 flag indicate card acccpt 1v8 switch or not + * argument = 0U , means to get the operation condition + * argument !=0 , set the operation condition register + */ +static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument, uint32_t *accept1V8); + +/*! + * @brief card Send relative address + * @param card Card descriptor. + */ +static status_t SDIO_SendRca(sdio_card_t *card); + +/*! + * @brief card select card + * @param card Card descriptor. + * @param select/diselect flag + */ +static inline status_t SDIO_SelectCard(sdio_card_t *card, bool isSelected); + +/*! + * @brief card go idle + * @param card Card descriptor. + */ +static inline status_t SDIO_GoIdle(sdio_card_t *card); + +/*! + * @brief decode CIS + * @param card Card descriptor. + * @param func number + * @param data buffer pointer + * @param tuple code + * @param tuple link + */ +static status_t SDIO_DecodeCIS( + sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink); + +/*! + * @brief switch to the maxium support bus width, depend on the host and card's capability. + * @param card Card descriptor. + */ +static status_t SDIO_SetMaxDataBusWidth(sdio_card_t *card); + +/*! + * @brief sdio card excute tuning. + * @param card Card descriptor. + */ +static status_t SDIO_ExecuteTuning(sdio_card_t *card); + +/*! + * @brief sdio io access direct + * @param card Card descriptor. + * @param direction access direction. + * @param func number + * @param regAddr register address. + * @param dataIn data to write + * @param dataOut data address for read + * @param rawFlag read after write flag, it is used for write access only. + */ +static status_t SDIO_IO_Access_Direct(sdio_card_t *card, + sdio_io_direction_t direction, + sdio_func_num_t func, + uint32_t regAddr, + uint8_t dataIn, + uint8_t *dataOut, + bool rawFlag); +/******************************************************************************* + * Variables + ******************************************************************************/ +/* define the tuple list */ +static const uint32_t s_tupleList[SDIO_COMMON_CIS_TUPLE_NUM] = { + SDIO_TPL_CODE_MANIFID, + SDIO_TPL_CODE_FUNCID, + SDIO_TPL_CODE_FUNCE, +}; + +/******************************************************************************* + * Code + ******************************************************************************/ +static inline status_t SDIO_SelectCard(sdio_card_t *card, bool isSelected) +{ + assert(card != NULL); + + return SDMMC_SelectCard(card->host, card->relativeAddress, isSelected); +} + +static inline status_t SDIO_GoIdle(sdio_card_t *card) +{ + assert(card != NULL); + + return SDMMC_GoIdle(card->host); +} + +static status_t SDIO_SwitchIOVoltage(sdio_card_t *card, sdmmc_operation_voltage_t voltage) +{ + if ((card->usrParam.ioVoltage != NULL) && (card->usrParam.ioVoltage->type == kSD_IOVoltageCtrlByGpio)) + { + /* make sure card signal line voltage is 3.3v before initalization */ + if (card->usrParam.ioVoltage->func != NULL) + { + card->usrParam.ioVoltage->func(voltage); + } + } + else if ((card->usrParam.ioVoltage != NULL) && (card->usrParam.ioVoltage->type == kSD_IOVoltageCtrlByHost)) + { + SDMMCHOST_SwitchToVoltage(card->host, (uint32_t)voltage); + } + else + { + return kStatus_SDMMC_NotSupportYet; + } + + return kStatus_Success; +} + +static status_t SDIO_SwitchVoltage(sdio_card_t *card, sdmmc_operation_voltage_t voltage) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSD_VoltageSwitch; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR1; + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + /* check data line and cmd line status */ + if (SDMMCHOST_GetSignalLineStatus(card->host, (uint32_t)kSDMMC_SignalLineData0 | (uint32_t)kSDMMC_SignalLineData1 | + (uint32_t)kSDMMC_SignalLineData2 | + (uint32_t)kSDMMC_SignalLineData3) != 0U) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + /* switch io voltage */ + if (SDIO_SwitchIOVoltage(card, voltage) == kStatus_SDMMC_NotSupportYet) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + SDMMC_OSADelay(100U); + + /*enable force clock on*/ + SDMMCHOST_ForceClockOn(card->host, true); + /* dealy 1ms,not exactly correct when use while */ + SDMMC_OSADelay(10U); + /*disable force clock on*/ + SDMMCHOST_ForceClockOn(card->host, false); + + /* check data line and cmd line status */ + if (SDMMCHOST_GetSignalLineStatus(card->host, (uint32_t)kSDMMC_SignalLineData0 | (uint32_t)kSDMMC_SignalLineData1 | + (uint32_t)kSDMMC_SignalLineData2 | + (uint32_t)kSDMMC_SignalLineData3) == 0U) + { + error = kStatus_SDMMC_SwitchVoltageFail; + /* power reset the card */ + SDIO_SetCardPower(card, false); + SDIO_SetCardPower(card, true); + /* re-check the data line status */ + if (SDMMCHOST_GetSignalLineStatus( + card->host, (uint32_t)kSDMMC_SignalLineData0 | (uint32_t)kSDMMC_SignalLineData1 | + (uint32_t)kSDMMC_SignalLineData2 | (uint32_t)kSDMMC_SignalLineData3) != 0U) + { + error = kStatus_SDMMC_SwitchVoltage18VFail33VSuccess; + SDMMC_LOG("\r\nNote: Current card support 1.8V, but board don't support, so sdmmc switch back to 3.3V."); + } + else + { + SDMMC_LOG( + "\r\nError: Current card support 1.8V, but board don't support, sdmmc tried to switch back\ + to 3.3V, but failed, please check board setting."); + } + } + + return error; +} + +static status_t SDIO_ExecuteTuning(sdio_card_t *card) +{ + assert(card != NULL); + + return SDMMCHOST_ExecuteTuning(card->host, (uint32_t)kSD_SendTuningBlock, + (uint32_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer), 64U); +} + +static status_t SDIO_SendRca(sdio_card_t *card) +{ + assert(card != NULL); + + uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; + + sdmmchost_transfer_t content = {0}; + sdmmchost_cmd_t command = {0}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDIO_SendRelativeAddress; + command.argument = 0U; + command.responseType = kCARD_ResponseTypeR6; + command.responseErrorFlags = + (uint32_t)kSDIO_StatusR6Error | (uint32_t)kSDIO_StatusIllegalCmd | (uint32_t)kSDIO_StatusCmdCRCError; + + content.command = &command; + content.data = NULL; + + while (--i != 0U) + { + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success == error) + { + /* check illegal state and cmd CRC error, may be the voltage or clock not stable, retry the cmd*/ + if ((command.response[0U] & ((uint32_t)kSDIO_StatusIllegalCmd | (uint32_t)kSDIO_StatusCmdCRCError)) != 0U) + { + continue; + } + + card->relativeAddress = (command.response[0U] >> 16U); + + return kStatus_Success; + } + } + + return kStatus_SDMMC_TransferFailed; +} + +status_t SDIO_CardInActive(sdio_card_t *card) +{ + assert(card != NULL); + + return SDMMC_SetCardInactive(card->host); +} + +static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument, uint32_t *accept1V8) +{ + assert(card != NULL); + + sdmmchost_transfer_t content = {0U}; + sdmmchost_cmd_t command = {0U}; + uint32_t i = SDIO_RETRY_TIMES; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDIO_SendOperationCondition; + command.argument = argument; + command.responseType = kCARD_ResponseTypeR4; + + content.command = &command; + content.data = NULL; + + while (--i != 0U) + { + error = SDMMCHOST_TransferFunction(card->host, &content); + if ((kStatus_Success != error) || (command.response[0U] == 0U)) + { + continue; + } + + /* if argument equal 0, then should check and save the info */ + if ((argument != 0U) && ((command.response[0U] & SDMMC_MASK(kSDIO_OcrPowerUpBusyFlag)) == 0U)) + { + continue; + } + else if (argument == 0U) + { + /* check the io number and ocr value */ + if ((((command.response[0U] & SDIO_OCR_IO_NUM_MASK) >> kSDIO_OcrIONumber) == 0U) || + ((command.response[0U] & 0xFFFFFFU) == 0U)) + { + return kStatus_Fail; + } + + break; + } + else + { + /* check if memory present */ + if ((command.response[0U] & SDMMC_MASK(kSDIO_OcrMemPresent)) == SDMMC_MASK(kSDIO_OcrMemPresent)) + { + card->memPresentFlag = true; + } + /* save the io number */ + card->ioTotalNumber = (uint8_t)((command.response[0U] & SDIO_OCR_IO_NUM_MASK) >> kSDIO_OcrIONumber); + /* save the operation condition */ + card->ocr = command.response[0U] & 0xFFFFFFU; + if (accept1V8 != NULL) + { + *accept1V8 = command.response[0U] & 0x1000000U; + } + + break; + } + } + + return ((i != 0U) ? kStatus_Success : kStatus_Fail); +} + +static status_t SDIO_IO_Access_Direct(sdio_card_t *card, + sdio_io_direction_t direction, + sdio_func_num_t func, + uint32_t regAddr, + uint8_t dataIn, + uint8_t *dataOut, + bool rawFlag) +{ + assert(card != NULL); + assert(func <= kSDIO_FunctionNum7); + + sdmmchost_transfer_t content = {0U}; + sdmmchost_cmd_t command = {0U}; + status_t error = kStatus_Success; + + command.index = (uint32_t)kSDIO_RWIODirect; + command.argument = ((uint32_t)func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS); + + if ((dataOut != NULL) && (direction == kSDIO_IOWrite)) + { + command.argument |= (1UL << SDIO_CMD_ARGUMENT_RW_POS) | ((uint32_t)rawFlag << SDIO_DIRECT_CMD_ARGUMENT_RAW_POS); + } + + if (direction == kSDIO_IOWrite) + { + command.argument |= (uint32_t)dataIn & SDIO_DIRECT_CMD_DATA_MASK; + } + + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = + ((uint32_t)kSDIO_StatusCmdCRCError | (uint32_t)kSDIO_StatusIllegalCmd | (uint32_t)kSDIO_StatusError | + (uint32_t)kSDIO_StatusFunctionNumError | (uint32_t)kSDIO_StatusOutofRange); + + content.command = &command; + content.data = NULL; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success != error) + { + error = kStatus_SDMMC_TransferFailed; + } + + if ((error == kStatus_Success) && (dataOut != NULL)) + { + /* read data from response */ + *dataOut = (uint8_t)(command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK); + } + + return error; +} + +status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data, bool raw) +{ + assert(card != NULL); + assert(func <= kSDIO_FunctionNum7); + + status_t error = kStatus_Success; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + error = SDIO_IO_Access_Direct(card, kSDIO_IOWrite, func, regAddr, *data, data, raw); + if (kStatus_Success != error) + { + error = kStatus_SDMMC_TransferFailed; + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data) +{ + assert(card != NULL); + assert(func <= kSDIO_FunctionNum7); + + status_t error = kStatus_Success; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, func, regAddr, 0, data, false); + if (kStatus_Success != error) + { + error = kStatus_SDMMC_TransferFailed; + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +status_t SDIO_IO_RW_Direct(sdio_card_t *card, + sdio_io_direction_t direction, + sdio_func_num_t func, + uint32_t regAddr, + uint8_t dataIn, + uint8_t *dataOut) +{ + assert(card != NULL); + assert(func <= kSDIO_FunctionNum7); + + status_t error = kStatus_Success; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + error = SDIO_IO_Access_Direct(card, direction, func, regAddr, dataIn, dataOut, true); + if (kStatus_Success != error) + { + error = kStatus_SDMMC_TransferFailed; + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +status_t SDIO_IO_Write_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) +{ + assert(card != NULL); + assert(buffer != NULL); + assert(func <= kSDIO_FunctionNum7); + + sdmmchost_transfer_t content = {0U}; + sdmmchost_cmd_t command = {0U}; + sdmmchost_data_t data = {0U}; + bool blockMode = false; + bool opCode = false; + status_t error = kStatus_Success; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + /* check if card support block mode */ + if (((card->cccrflags & (uint32_t)kSDIO_CCCRSupportMultiBlock) != 0U) && + ((flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK) != 0U)) + { + blockMode = true; + } + + if ((flags & SDIO_EXTEND_CMD_OP_CODE_MASK) != 0U) + { + opCode = true; + } + + /* check the byte size counter in non-block mode + * so you need read CIS for each function first,before you do read/write + */ + if (!blockMode) + { + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (count > card->commonCIS.fn0MaxBlkSize)) + { + error = kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[(uint32_t)func - 1U].ioMaxBlockSize != 0U) && + (count > card->funcCIS[(uint32_t)func - 1U].ioMaxBlockSize)) + { + error = kStatus_SDMMC_SDIO_InvalidArgument; + } + else + { + /* Intentional empty */ + } + } + + if (error == kStatus_Success) + { + command.index = (uint32_t)kSDIO_RWIOExtended; + command.argument = ((uint32_t)func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | + (1UL << SDIO_CMD_ARGUMENT_RW_POS) | (count & SDIO_EXTEND_CMD_COUNT_MASK) | + ((blockMode ? 1UL : 0UL) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | + ((opCode ? 1UL : 0UL) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = + ((uint32_t)kSDIO_StatusCmdCRCError | (uint32_t)kSDIO_StatusIllegalCmd | (uint32_t)kSDIO_StatusError | + (uint32_t)kSDIO_StatusFunctionNumError | (uint32_t)kSDIO_StatusOutofRange); + + if (blockMode) + { + if (func == kSDIO_FunctionNum0) + { + data.blockSize = card->io0blockSize; + } + else + { + data.blockSize = card->ioFBR[(uint32_t)func - 1U].ioBlockSize; + } + data.blockCount = count; + } + else + { + data.blockSize = count; + data.blockCount = 1U; + } + data.txData = (uint32_t *)(uint32_t)buffer; + + content.command = &command; + content.data = &data; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success != error) + { + error = kStatus_SDMMC_TransferFailed; + } + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +status_t SDIO_IO_Read_Extended( + sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) +{ + assert(card != NULL); + assert(buffer != NULL); + assert(func <= kSDIO_FunctionNum7); + + sdmmchost_transfer_t content = {0U}; + sdmmchost_cmd_t command = {0U}; + sdmmchost_data_t data = {0U}; + bool blockMode = false; + bool opCode = false; + status_t error = kStatus_Success; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + /* check if card support block mode */ + if (((card->cccrflags & (uint32_t)kSDIO_CCCRSupportMultiBlock) != 0U) && + ((flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK) != 0U)) + { + blockMode = true; + } + + /* op code =0 : read/write to fixed addr + * op code =1 :read/write addr incrementing + */ + if ((flags & SDIO_EXTEND_CMD_OP_CODE_MASK) != 0U) + { + opCode = true; + } + + /* check the byte size counter in non-block mode + * so you need read CIS for each function first,before you do read/write + */ + if (!blockMode) + { + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (count > card->commonCIS.fn0MaxBlkSize)) + { + error = kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[(uint32_t)func - 1U].ioMaxBlockSize != 0U) && + (count > card->funcCIS[(uint32_t)func - 1U].ioMaxBlockSize)) + { + error = kStatus_SDMMC_SDIO_InvalidArgument; + } + else + { + /* Intentional empty */ + } + } + + if (error == kStatus_Success) + { + command.index = (uint32_t)kSDIO_RWIOExtended; + command.argument = ((uint32_t)func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | + ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | + (count & SDIO_EXTEND_CMD_COUNT_MASK) | + ((blockMode ? 1UL : 0UL) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | + ((opCode ? 1UL : 0UL) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = + ((uint32_t)kSDIO_StatusCmdCRCError | (uint32_t)kSDIO_StatusIllegalCmd | (uint32_t)kSDIO_StatusError | + (uint32_t)kSDIO_StatusFunctionNumError | (uint32_t)kSDIO_StatusOutofRange); + + if (blockMode) + { + if (func == kSDIO_FunctionNum0) + { + data.blockSize = card->io0blockSize; + } + else + { + data.blockSize = card->ioFBR[(uint32_t)func - 1U].ioBlockSize; + } + data.blockCount = count; + } + else + { + data.blockSize = count; + data.blockCount = 1U; + } + data.rxData = (uint32_t *)(uint32_t)buffer; + + content.command = &command; + content.data = &data; + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success != error) + { + error = kStatus_SDMMC_TransferFailed; + } + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +status_t SDIO_IO_Transfer(sdio_card_t *card, + sdio_command_t cmd, + uint32_t argument, + uint32_t blockSize, + uint8_t *txData, + uint8_t *rxData, + uint16_t dataSize, + uint32_t *response) +{ + assert(card != NULL); + + uint32_t actualSize = dataSize; + sdmmchost_transfer_t content = {0U}; + sdmmchost_cmd_t command = {0U}; + sdmmchost_data_t data = {0U}; + uint32_t i = SDIO_RETRY_TIMES; + uint32_t *dataAddr = (uint32_t *)(uint32_t)(txData == NULL ? rxData : txData); + uint8_t *alignBuffer = (uint8_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + status_t error = kStatus_Fail; + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + if ((dataSize != 0U) && (txData != NULL) && (rxData != NULL)) + { + error = kStatus_InvalidArgument; + } + else + { + command.index = (uint32_t)cmd; + command.argument = argument; + command.responseType = kCARD_ResponseTypeR5; + command.responseErrorFlags = + ((uint32_t)kSDIO_StatusCmdCRCError | (uint32_t)kSDIO_StatusIllegalCmd | (uint32_t)kSDIO_StatusError | + (uint32_t)kSDIO_StatusFunctionNumError | (uint32_t)kSDIO_StatusOutofRange); + content.command = &command; + content.data = NULL; + + if (dataSize != 0U) + { + /* if block size bigger than 1, then use block mode */ + if ((argument & SDIO_EXTEND_CMD_BLOCK_MODE_MASK) != 0U) + { + if (dataSize % blockSize != 0U) + { + actualSize = ((dataSize / blockSize) + 1U) * blockSize; + } + + data.blockCount = actualSize / blockSize; + data.blockSize = blockSize; + } + else + { + data.blockCount = 1; + data.blockSize = dataSize; + } + /* if data buffer address can not meet host controller internal DMA requirement, sdio driver will try to use + * internal align buffer if data size is not bigger than internal buffer size, + * Align address transfer always can get a better performance, so if you want sdio driver make buffer + * address align, you should redefine the SDMMC_GLOBAL_BUFFER_SIZE macro to a value which is big enough for + * your application. + */ + if ( +#if SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE != 1U + (((uint32_t)dataAddr & (SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE - 1U)) != 0U) && +#endif + (actualSize <= FSL_SDMMC_DEFAULT_BLOCK_SIZE) && (!card->noInternalAlign)) + { + dataAddr = (uint32_t *)(uint32_t)alignBuffer; + (void)memset(alignBuffer, 0, actualSize); + if (txData != NULL) + { + (void)memcpy(alignBuffer, txData, dataSize); + } + } + + if (rxData != NULL) + { + data.rxData = dataAddr; + } + else + { + data.txData = dataAddr; + } + + content.data = &data; + } + + do + { + error = SDMMCHOST_TransferFunction(card->host, &content); + if (kStatus_Success == error) + { + if ((rxData != NULL) && (dataSize != 0U) && +#if SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE != 1U + (((uint32_t)rxData & (SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE - 1U)) != 0U) && +#endif + (actualSize <= FSL_SDMMC_DEFAULT_BLOCK_SIZE) && (!card->noInternalAlign)) + { + (void)memcpy(rxData, alignBuffer, dataSize); + } + + if (response != NULL) + { + *response = command.response[0]; + } + + error = kStatus_Success; + break; + } + + i--; + } while (i != 0U); + } + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card != NULL); + assert(func <= kSDIO_FunctionNum7); + + uint8_t *tempBuffer = (uint8_t *)FSL_SDMMC_CARD_INTERNAL_BUFFER_ALIGN_ADDR(card->internalBuffer); + uint32_t i = 0U; + status_t error = kStatus_Success; + + (void)memset(tempBuffer, 0, SDIO_CCCR_REG_NUMBER); + + for (i = 0U; i <= SDIO_CCCR_REG_NUMBER; i++) + { + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, SDIO_FBR_BASE((uint32_t)func) + i, 0U, + &tempBuffer[i], false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + } + + switch (func) + { + case kSDIO_FunctionNum0: + + card->sdVersion = tempBuffer[kSDIO_RegSDVersion]; + card->sdioVersion = tempBuffer[kSDIO_RegCCCRSdioVer] >> 4U; + card->cccrVersioin = tempBuffer[kSDIO_RegCCCRSdioVer] & 0xFU; + /* continuous SPI interrupt */ + if ((tempBuffer[kSDIO_RegBusInterface] & 0x40U) != 0U) + { + card->cccrflags |= (uint32_t)kSDIO_CCCRSupportContinuousSPIInt; + } + /* 8bit data bus */ + if ((tempBuffer[kSDIO_RegBusInterface] & 0x4U) != 0U) + { + card->cccrflags |= SDIO_CCCR_SUPPORT_8BIT_BUS; + } + + /* card capability register */ + card->cccrflags |= (tempBuffer[kSDIO_RegCardCapability] & 0xDFUL); + /* master power control */ + if ((tempBuffer[kSDIO_RegPowerControl] & 0x01U) != 0U) + { + card->cccrflags |= (uint32_t)kSDIO_CCCRSupportMasterPowerControl; + } + /* high speed flag */ + if ((tempBuffer[kSDIO_RegBusSpeed] & 0x01U) != 0U) + { + card->cccrflags |= SDIO_CCCR_SUPPORT_HIGHSPEED; + } + /* uhs mode flag */ + card->cccrflags |= (tempBuffer[kSDIO_RegUHSITimingSupport] & 7UL) << 11U; + /* driver type flag */ + card->cccrflags |= (tempBuffer[kSDIO_RegDriverStrength] & 7UL) << 14U; + /* low speed 4bit */ + if ((tempBuffer[kSDIO_RegCardCapability] & 0x80U) != 0U) + { + card->cccrflags |= (uint32_t)kSDIO_CCCRSupportLowSpeed4Bit; + } + /* common CIS pointer */ + card->commonCISPointer = tempBuffer[kSDIO_RegCommonCISPointer] | + ((uint32_t)tempBuffer[(uint32_t)kSDIO_RegCommonCISPointer + 1U] << 8U) | + ((uint32_t)tempBuffer[(uint32_t)kSDIO_RegCommonCISPointer + 2U] << 16U); + + /* check card capability of support async interrupt */ + if ((tempBuffer[kSDIO_RegInterruptExtension] & SDIO_CCCR_ASYNC_INT_MASK) == SDIO_CCCR_ASYNC_INT_MASK) + { + card->cccrflags |= SDIO_CCCR_SUPPORT_ASYNC_INT; + } + + break; + + case kSDIO_FunctionNum1: + case kSDIO_FunctionNum2: + case kSDIO_FunctionNum3: + case kSDIO_FunctionNum4: + case kSDIO_FunctionNum5: + case kSDIO_FunctionNum6: + case kSDIO_FunctionNum7: + card->ioFBR[(uint32_t)func - 1U].ioStdFunctionCode = tempBuffer[0U] & 0x0FU; + card->ioFBR[(uint32_t)func - 1U].ioExtFunctionCode = tempBuffer[1U]; + card->ioFBR[(uint32_t)func - 1U].ioPointerToCIS = + tempBuffer[9U] | ((uint32_t)tempBuffer[10U] << 8U) | ((uint32_t)tempBuffer[11U] << 16U); + card->ioFBR[(uint32_t)func - 1U].ioPointerToCSA = + tempBuffer[12U] | ((uint32_t)tempBuffer[13U] << 8U) | ((uint32_t)tempBuffer[14U] << 16U); + if ((tempBuffer[2U] & 0x01U) != 0U) + { + card->ioFBR[(uint32_t)func - 1U].flags |= (uint8_t)kSDIO_FBRSupportPowerSelection; + } + if ((tempBuffer[0U] & 0x40U) != 0U) + { + card->ioFBR[(uint32_t)func - 1U].flags |= (uint8_t)kSDIO_FBRSupportCSA; + } + + break; + + default: + assert(false); + break; + } + + return kStatus_Success; +} + +status_t SDIO_SetBlockSize(sdio_card_t *card, sdio_func_num_t func, uint32_t blockSize) +{ + assert(card != NULL); + assert(func <= kSDIO_FunctionNum7); + assert(blockSize <= SDIO_MAX_BLOCK_SIZE); + + uint8_t temp = 0U; + status_t error = kStatus_Success; + + /* check the block size for block mode + * so you need read CIS for each function first,before you do read/write + */ + if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && + (blockSize > card->commonCIS.fn0MaxBlkSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[(uint32_t)func - 1U].ioMaxBlockSize != 0U) && + (blockSize > card->funcCIS[(uint32_t)func - 1U].ioMaxBlockSize)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + else + { + /* Intentional empty */ + } + + temp = (uint8_t)(blockSize & 0xFFU); + + error = + SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, + SDIO_FBR_BASE((uint32_t)func) + (uint32_t)kSDIO_RegFN0BlockSizeLow, temp, &temp, true); + if (kStatus_Success != error) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + temp = (uint8_t)((blockSize >> 8U) & 0xFFU); + + error = + SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, + SDIO_FBR_BASE((uint32_t)func) + (uint32_t)kSDIO_RegFN0BlockSizeHigh, temp, &temp, true); + if (kStatus_Success != error) + { + return kStatus_SDMMC_SetCardBlockSizeFailed; + } + + /* record the current block size */ + if (func == kSDIO_FunctionNum0) + { + card->io0blockSize = blockSize; + } + else + { + card->ioFBR[(uint32_t)func - 1U].ioBlockSize = (uint16_t)blockSize; + } + + return kStatus_Success; +} + +status_t SDIO_CardReset(sdio_card_t *card) +{ + status_t error = kStatus_Success; + + error = SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOAbort, 0x08U, NULL, false); + if (error != kStatus_Success) + { + error = kStatus_SDMMC_TransferFailed; + } + + return error; +} + +status_t SDIO_SetDataBusWidth(sdio_card_t *card, sdio_bus_width_t busWidth) +{ + assert(card != NULL); + + uint8_t regBusInterface = 0U; + status_t error = kStatus_Success; + + if (((busWidth == kSDIO_DataBus4Bit) && ((card->cccrflags & (uint32_t)kSDIO_CCCRSupportHighSpeed) == 0U) && + ((card->cccrflags & (uint32_t)kSDIO_CCCRSupportLowSpeed4Bit) == 0U))) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + + if ((((card->cccrflags & SDIO_CCCR_SUPPORT_8BIT_BUS) == 0U) || + ((card->usrParam.capability & (uint32_t)kSDMMC_Support8BitWidth) == 0U) || + ((card->host->capability & (uint32_t)kSDMMCHOST_Support8BitDataWidth) == 0U)) && + (busWidth == kSDIO_DataBus8Bit)) + { + return kStatus_SDMMC_SDIO_InvalidArgument; + } + + /* load bus interface register */ + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegBusInterface, 0U, ®BusInterface, + false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + /* set bus width */ + regBusInterface &= 0xFCU; + regBusInterface |= (uint8_t)busWidth; + + /* write to register */ + error = SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegBusInterface, regBusInterface, + ®BusInterface, true); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + +#if SDMMCHOST_SUPPORT_8_BIT_WIDTH + if (busWidth == kSDIO_DataBus8Bit) + { + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith8Bit); + } + else +#endif + if (busWidth == kSDIO_DataBus4Bit) + { + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith4Bit); + } + else + { + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith1Bit); + } + + return kStatus_Success; +} + +static status_t SDIO_SetMaxDataBusWidth(sdio_card_t *card) +{ + sdio_bus_width_t busWidth = kSDIO_DataBus1Bit; + + if (((card->cccrflags & SDIO_CCCR_SUPPORT_8BIT_BUS) != 0U) && + ((card->usrParam.capability & (uint32_t)kSDMMC_Support8BitWidth) != 0U) && + ((card->host->capability & (uint32_t)kSDMMCHOST_Support8BitDataWidth) != 0U)) + { + busWidth = kSDIO_DataBus8Bit; + } + /* switch data bus width */ + else if ((((card->cccrflags & (uint32_t)kSDIO_CCCRSupportHighSpeed) != 0U) || + ((card->cccrflags & (uint32_t)kSDIO_CCCRSupportLowSpeed4Bit) != 0U)) && + ((card->host->capability & (uint32_t)kSDMMCHOST_Support4BitDataWidth) != 0U)) + { + busWidth = kSDIO_DataBus4Bit; + } + else + { + busWidth = kSDIO_DataBus1Bit; + } + + return SDIO_SetDataBusWidth(card, busWidth); +} + +status_t SDIO_SwitchToHighSpeed(sdio_card_t *card) +{ + assert(card != NULL); + + uint8_t temp = 0U; + uint32_t retryTimes = SDIO_RETRY_TIMES; + status_t status = kStatus_SDMMC_SDIO_SwitchHighSpeedFail; + status_t error = kStatus_Success; + + if ((card->cccrflags & SDIO_CCCR_SUPPORT_HIGHSPEED) != 0U) + { + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, 0U, &temp, false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + do + { + temp &= (uint8_t)~SDIO_CCCR_BUS_SPEED_MASK; + temp |= SDIO_CCCR_ENABLE_HIGHSPEED_MODE; + + retryTimes--; + /* enable high speed mode */ + error = + SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, temp, &temp, true); + if (kStatus_Success != error) + { + continue; + } + /* either EHS=0 and SHS=0 ,the card is still in default mode */ + if ((temp & 0x03U) == 0x03U) + { + card->busClock_Hz = SDMMCHOST_SetCardClock( + card->host, FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, SD_CLOCK_50MHZ)); + status = kStatus_Success; + break; + } + else + { + continue; + } + + } while (retryTimes != 0U); + } + else + { + /* default mode 25MHZ */ + card->busClock_Hz = + SDMMCHOST_SetCardClock(card->host, FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, SD_CLOCK_25MHZ)); + status = kStatus_Success; + } + + return status; +} + +static status_t SDIO_SelectBusTiming(sdio_card_t *card) +{ + assert(card != NULL); + + uint32_t targetBusFreq = SD_CLOCK_25MHZ; + uint32_t targetTiming = 0U; + uint8_t temp = 0U; + uint32_t supportModeFlag = 0U; + uint32_t retryTimes = SDIO_RETRY_TIMES; + status_t error = kStatus_Success; + + do + { + if (card->currentTiming == kSD_TimingSDR12DefaultMode) + { + /* if timing not specified, probe card capability from SDR104 mode */ + card->currentTiming = kSD_TimingSDR104Mode; + } + + if (card->currentTiming == kSD_TimingSDR104Mode) + { + if (((card->host->capability & (uint32_t)kSDMMCHOST_SupportSDR104) != 0U) && + ((card->cccrflags & SDIO_CCCR_SUPPORT_SDR104) == SDIO_CCCR_SUPPORT_SDR104) && + (card->operationVoltage == kSDMMC_OperationVoltage180V)) + { + targetTiming = SDIO_CCCR_ENABLE_SDR104_MODE; + targetBusFreq = FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, SD_CLOCK_208MHZ); + supportModeFlag = SDIO_CCCR_SUPPORT_SDR104; + } + else + { + card->currentTiming = kSD_TimingDDR50Mode; + } + } + + if (card->currentTiming == kSD_TimingDDR50Mode) + { + if (((card->host->capability & (uint32_t)kSDMMCHOST_SupportDDRMode) != 0U) && + ((card->cccrflags & SDIO_CCCR_SUPPORT_DDR50) == SDIO_CCCR_SUPPORT_DDR50) && + (card->operationVoltage == kSDMMC_OperationVoltage180V)) + { + targetTiming = SDIO_CCCR_ENABLE_DDR50_MODE; + targetBusFreq = FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, SD_CLOCK_50MHZ); + supportModeFlag = SDIO_CCCR_SUPPORT_DDR50; + } + else + { + card->currentTiming = kSD_TimingSDR50Mode; + } + } + + if (card->currentTiming == kSD_TimingSDR50Mode) + { + if (((card->host->capability & (uint32_t)kSDMMCHOST_SupportSDR50) != 0U) && + ((card->cccrflags & SDIO_CCCR_SUPPORT_SDR50) == SDIO_CCCR_SUPPORT_SDR50) && + (card->operationVoltage == kSDMMC_OperationVoltage180V)) + { + targetTiming = SDIO_CCCR_ENABLE_SDR50_MODE; + targetBusFreq = FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, SD_CLOCK_100MHZ); + supportModeFlag = SDIO_CCCR_SUPPORT_SDR50; + } + else + { + card->currentTiming = kSD_TimingSDR25HighSpeedMode; + } + } + + if (card->currentTiming == kSD_TimingSDR25HighSpeedMode) + { + if ((card->cccrflags & SDIO_CCCR_SUPPORT_HIGHSPEED) == SDIO_CCCR_SUPPORT_HIGHSPEED) + { + targetTiming = SDIO_CCCR_ENABLE_HIGHSPEED_MODE; + targetBusFreq = FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, SD_CLOCK_50MHZ); + supportModeFlag = SDIO_CCCR_SUPPORT_HIGHSPEED; + } + else + { + card->currentTiming = kSD_TimingSDR12DefaultMode; + } + } + + if (card->currentTiming == kSD_TimingSDR12DefaultMode) + { + /* default timing mode */ + targetBusFreq = SD_CLOCK_25MHZ; + } + + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, 0U, &temp, false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + do + { + temp &= (uint8_t)~SDIO_CCCR_BUS_SPEED_MASK; + temp |= (uint8_t)targetTiming; + + retryTimes--; + error = + SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, temp, &temp, true); + if (kStatus_Success != error) + { + continue; + } + + if ((temp & targetTiming) != targetTiming) + { + continue; + } + + break; + + } while (retryTimes != 0U); + + if (retryTimes == 0U) + { + retryTimes = SDIO_RETRY_TIMES; + /* if cannot switch target timing, it will switch continuously until find a valid timing. */ + card->cccrflags &= ~supportModeFlag; + continue; + } + + break; + + } while (true); + + card->busClock_Hz = + SDMMCHOST_SetCardClock(card->host, FSL_SDMMC_CARD_MAX_BUS_FREQ(card->usrParam.maxFreq, targetBusFreq)); + + /* enable DDR mode if it is the target mode */ + if (card->currentTiming == kSD_TimingDDR50Mode) + { + SDMMCHOST_EnableDDRMode(card->host, true, 0U); + } + + if (card->usrParam.ioStrength != NULL) + { + card->usrParam.ioStrength(card->busClock_Hz); + } + + /* SDR50 and SDR104 mode need tuning */ + if ((card->currentTiming == kSD_TimingSDR50Mode) || (card->currentTiming == kSD_TimingSDR104Mode)) + { + /* execute tuning */ + if (SDIO_ExecuteTuning(card) != kStatus_Success) + { + return kStatus_SDMMC_TuningFail; + } + } + + return kStatus_Success; +} + +status_t SDIO_SetDriverStrength(sdio_card_t *card, sd_driver_strength_t driverStrength) +{ + uint8_t strength = 0U, temp = 0U; + status_t error = kStatus_Success; + + switch (driverStrength) + { + case kSD_DriverStrengthTypeA: + strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_A; + break; + case kSD_DriverStrengthTypeC: + strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_C; + break; + case kSD_DriverStrengthTypeD: + strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_D; + break; + default: + strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_B; + break; + } + + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegDriverStrength, 0U, &temp, false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + temp &= (uint8_t)~SDIO_CCCR_DRIVER_TYPE_MASK; + temp |= strength; + + error = SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegDriverStrength, temp, &temp, true); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + return error; +} + +status_t SDIO_EnableAsyncInterrupt(sdio_card_t *card, bool enable) +{ + assert(card != NULL); + + uint8_t eai = 0U; + status_t error = kStatus_Success; + + if ((card->cccrflags & SDIO_CCCR_SUPPORT_ASYNC_INT) == 0U) + { + return kStatus_SDMMC_NotSupportYet; + } + + /* load interrupt enable register */ + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegInterruptExtension, 0U, &eai, false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + /* if already enable/disable , do not need enable/disable again */ + if (((eai)&SDIO_CCCR_ENABLE_AYNC_INT) == (enable ? SDIO_CCCR_ENABLE_AYNC_INT : 0U)) + { + return kStatus_Success; + } + + /* enable the eai */ + if (enable) + { + eai |= SDIO_CCCR_ENABLE_AYNC_INT; + } + else + { + eai &= (uint8_t) ~(SDIO_CCCR_ENABLE_AYNC_INT); + } + + /* write to register */ + error = + SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegInterruptExtension, eai, &eai, true); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +static status_t SDIO_DecodeCIS( + sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink) +{ + assert(card != NULL); + assert(dataBuffer != NULL); + + if (func == kSDIO_FunctionNum0) + { + /* only decode MANIFID,FUNCID,FUNCE here */ + if (tplCode == SDIO_TPL_CODE_MANIFID) + { + card->commonCIS.mID = dataBuffer[0U] | ((uint16_t)dataBuffer[1U] << 8U); + card->commonCIS.mInfo = dataBuffer[2U] | ((uint16_t)dataBuffer[3U] << 8U); + } + else if (tplCode == SDIO_TPL_CODE_FUNCID) + { + card->commonCIS.funcID = dataBuffer[0U]; + } + else if (tplCode == SDIO_TPL_CODE_FUNCE) + { + /* max transfer block size and data size */ + card->commonCIS.fn0MaxBlkSize = dataBuffer[1U] | ((uint16_t)dataBuffer[2U] << 8U); + /* max transfer speed */ + card->commonCIS.maxTransSpeed = dataBuffer[3U]; + } + else + { + /* reserved here */ + return kStatus_Fail; + } + } + else + { + /* only decode FUNCID,FUNCE here */ + if (tplCode == SDIO_TPL_CODE_FUNCID) + { + card->funcCIS[(uint32_t)func - 1U].funcID = dataBuffer[0U]; + } + else if (tplCode == SDIO_TPL_CODE_FUNCE) + { + if (tplLink == 0x2AU) + { + card->funcCIS[(uint32_t)func - 1U].funcInfo = dataBuffer[1U]; + card->funcCIS[(uint32_t)func - 1U].ioVersion = dataBuffer[2U]; + card->funcCIS[(uint32_t)func - 1U].cardPSN = dataBuffer[3U] | ((uint32_t)dataBuffer[4U] << 8U) | + ((uint32_t)dataBuffer[5U] << 16U) | + ((uint32_t)dataBuffer[6U] << 24U); + card->funcCIS[(uint32_t)func - 1U].ioCSASize = dataBuffer[7U] | ((uint32_t)dataBuffer[8U] << 8U) | + ((uint32_t)dataBuffer[9U] << 16U) | + ((uint32_t)dataBuffer[10U] << 24U); + card->funcCIS[(uint32_t)func - 1U].ioCSAProperty = dataBuffer[11U]; + card->funcCIS[(uint32_t)func - 1U].ioMaxBlockSize = dataBuffer[12U] | ((uint16_t)dataBuffer[13U] << 8U); + card->funcCIS[(uint32_t)func - 1U].ioOCR = dataBuffer[14U] | ((uint32_t)dataBuffer[15U] << 8U) | + ((uint32_t)dataBuffer[16U] << 16U) | + ((uint32_t)dataBuffer[17U] << 24U); + card->funcCIS[(uint32_t)func - 1U].ioOPMinPwr = dataBuffer[18U]; + card->funcCIS[(uint32_t)func - 1U].ioOPAvgPwr = dataBuffer[19U]; + card->funcCIS[(uint32_t)func - 1U].ioOPMaxPwr = dataBuffer[20U]; + card->funcCIS[(uint32_t)func - 1U].ioSBMinPwr = dataBuffer[21U]; + card->funcCIS[(uint32_t)func - 1U].ioSBAvgPwr = dataBuffer[22U]; + card->funcCIS[(uint32_t)func - 1U].ioSBMaxPwr = dataBuffer[23U]; + card->funcCIS[(uint32_t)func - 1U].ioMinBandWidth = dataBuffer[24U] | ((uint16_t)dataBuffer[25U] << 8U); + card->funcCIS[(uint32_t)func - 1U].ioOptimumBandWidth = + dataBuffer[26U] | ((uint16_t)dataBuffer[27U] << 8U); + card->funcCIS[(uint32_t)func - 1U].ioReadyTimeout = dataBuffer[28U] | ((uint16_t)dataBuffer[29U] << 8U); + + card->funcCIS[(uint32_t)func - 1U].ioHighCurrentAvgCurrent = + dataBuffer[34U] | ((uint16_t)dataBuffer[35U] << 8U); + card->funcCIS[(uint32_t)func - 1U].ioHighCurrentMaxCurrent = + dataBuffer[36U] | ((uint16_t)dataBuffer[37U] << 8U); + card->funcCIS[(uint32_t)func - 1U].ioLowCurrentAvgCurrent = + dataBuffer[38U] | ((uint16_t)dataBuffer[39U] << 8U); + card->funcCIS[(uint32_t)func - 1U].ioLowCurrentMaxCurrent = + dataBuffer[40U] | ((uint16_t)dataBuffer[41U] << 8U); + } + else + { + return kStatus_Fail; + } + } + else + { + return kStatus_Fail; + } + } + + return kStatus_Success; +} + +status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *tupleList, uint32_t tupleNum) +{ + assert(card != NULL); + assert(func <= kSDIO_FunctionNum7); + assert(tupleList != NULL); + + uint8_t tplCode = 0U; + uint8_t tplLink = 0U; + uint32_t cisPtr = 0U; + uint32_t i = 0U, num = 0U; + bool tupleMatch = false; + status_t error = kStatus_Success; + + uint8_t dataBuffer[255U] = {0U}; + + /* get the CIS pointer for each function */ + if (func == kSDIO_FunctionNum0) + { + cisPtr = card->commonCISPointer; + } + else + { + cisPtr = card->ioFBR[(uint32_t)func - 1U].ioPointerToCIS; + } + + if (0U == cisPtr) + { + return kStatus_SDMMC_SDIO_ReadCISFail; + } + + do + { + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, cisPtr++, 0U, &tplCode, false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + /* end of chain tuple */ + if (tplCode == 0xFFU) + { + break; + } + + if (tplCode == 0U) + { + continue; + } + + for (i = 0; i < tupleNum; i++) + { + if (tplCode == tupleList[i]) + { + tupleMatch = true; + break; + } + } + + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, cisPtr++, 0U, &tplLink, false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + /* end of chain tuple */ + if (tplLink == 0xFFU) + { + break; + } + + if (tupleMatch) + { + (void)memset(dataBuffer, 0, 255U); + for (i = 0; i < tplLink; i++) + { + error = + SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, cisPtr++, 0U, &dataBuffer[i], false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + } + tupleMatch = false; + /* pharse the data */ + (void)SDIO_DecodeCIS(card, func, dataBuffer, tplCode, tplLink); + /* read finish then return */ + if (++num == tupleNum) + { + break; + } + } + else + { + /* move pointer */ + cisPtr += tplLink; + /* tuple code not match,continue read tuple code */ + continue; + } + } while (true); + return kStatus_Success; +} + +static status_t SDIO_ProbeBusVoltage(sdio_card_t *card) +{ + assert(card != NULL); + + uint32_t ocr = 0U, accept1V8 = 0U; + status_t error = kStatus_Success; + + /* application able to set the supported voltage window */ + if ((card->ocr & SDIO_OCR_VOLTAGE_WINDOW_MASK) != 0U) + { + ocr = card->ocr & SDIO_OCR_VOLTAGE_WINDOW_MASK; + } + else + { + /* 3.3V voltage should be supported as default */ + ocr |= SDMMC_MASK(kSD_OcrVdd29_30Flag) | SDMMC_MASK(kSD_OcrVdd32_33Flag) | SDMMC_MASK(kSD_OcrVdd33_34Flag); + } + + if ((card->operationVoltage != kSDMMC_OperationVoltage180V) && (card->usrParam.ioVoltage != NULL) && + (card->usrParam.ioVoltage->type != kSD_IOVoltageCtrlNotSupport) && + ((card->host->capability & (uint32_t)kSDMMCHOST_SupportVoltage1v8) != 0U) && + ((card->host->capability & ((uint32_t)kSDMMCHOST_SupportSDR104 | (uint32_t)kSDMMCHOST_SupportSDR50 | + (uint32_t)kSDMMCHOST_SupportDDRMode)) != 0U)) + { + /* allow user select the work voltage, if not select, sdmmc will handle it automatically */ + ocr |= SDMMC_MASK(kSD_OcrSwitch18RequestFlag); + + /* reset to 3v3 signal voltage */ + if (SDIO_SwitchIOVoltage(card, kSDMMC_OperationVoltage330V) == kStatus_Success) + { + /* Host changed the operation signal voltage successfully, then card need power reset */ + SDIO_SetCardPower(card, false); + SDIO_SetCardPower(card, true); + } + } + + /* send card active */ + SDMMCHOST_SendCardActive(card->host); + + do + { + /* card go idle */ + if (kStatus_Success != SDIO_GoIdle(card)) + { + return kStatus_SDMMC_GoIdleFailed; + } + + /* Get IO OCR-CMD5 with arg0 ,set new voltage if needed*/ + if (kStatus_Success != SDIO_SendOperationCondition(card, 0U, NULL)) + { + return kStatus_SDMMC_HandShakeOperationConditionFailed; + } + + if (kStatus_Success != SDIO_SendOperationCondition(card, ocr, &accept1V8)) + { + return kStatus_SDMMC_InvalidVoltage; + } + + /* check if card support 1.8V */ + if ((accept1V8 & SDMMC_MASK(kSD_OcrSwitch18AcceptFlag)) != 0U) + { + if ((card->usrParam.ioVoltage != NULL) && (card->usrParam.ioVoltage->type == kSD_IOVoltageCtrlNotSupport)) + { + break; + } + + error = SDIO_SwitchVoltage(card, kSDMMC_OperationVoltage180V); + if (kStatus_SDMMC_SwitchVoltageFail == error) + { + break; + } + + if (error == kStatus_SDMMC_SwitchVoltage18VFail33VSuccess) + { + ocr &= ~SDMMC_MASK(kSD_OcrSwitch18RequestFlag); + error = kStatus_Success; + continue; + } + else + { + card->operationVoltage = kSDMMC_OperationVoltage180V; + break; + } + } + break; + } while (true); + + return error; +} + +static status_t sdiocard_init(sdio_card_t *card) +{ + assert(card != NULL); + + status_t error = kStatus_Success; + + if (!card->isHostReady) + { + return kStatus_SDMMC_HostNotReady; + } + /* Identify mode ,set clock to 400KHZ. */ + card->busClock_Hz = SDMMCHOST_SetCardClock(card->host, SDMMC_CLOCK_400KHZ); + SDMMCHOST_SetCardBusWidth(card->host, kSDMMC_BusWdith1Bit); + + error = SDIO_ProbeBusVoltage(card); + if (error != kStatus_Success) + { + return kStatus_SDMMC_SwitchVoltageFail; + } + + /* there is a memonly card */ + if ((card->ioTotalNumber == 0U) && (card->memPresentFlag)) + { + return kStatus_SDMMC_SDIO_InvalidCard; + } + + /* send relative address ,cmd3*/ + if (kStatus_Success != SDIO_SendRca(card)) + { + return kStatus_SDMMC_SendRelativeAddressFailed; + } + /* select card cmd7 */ + if (kStatus_Success != SDIO_SelectCard(card, true)) + { + return kStatus_SDMMC_SelectCardFailed; + } + + /* get card capability */ + if (kStatus_Success != SDIO_GetCardCapability(card, kSDIO_FunctionNum0)) + { + return kStatus_SDMMC_TransferFailed; + } + + /* read common CIS here */ + if (SDIO_ReadCIS(card, kSDIO_FunctionNum0, s_tupleList, SDIO_COMMON_CIS_TUPLE_NUM) != kStatus_Success) + { + return kStatus_SDMMC_SDIO_ReadCISFail; + } + + /* switch data bus width */ + if (kStatus_Success != SDIO_SetMaxDataBusWidth(card)) + { + return kStatus_SDMMC_SetDataBusWidthFailed; + } + + /* trying switch to card support timing mode. */ + if (kStatus_Success != SDIO_SelectBusTiming(card)) + { + return kStatus_SDMMC_SDIO_SwitchHighSpeedFail; + } + + return kStatus_Success; +} + +status_t SDIO_CardInit(sdio_card_t *card) +{ + assert(card != NULL); + + status_t error = kStatus_Success; + /* create mutex lock */ + (void)SDMMC_OSAMutexCreate(&card->lock); + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + + SDIO_SetCardPower(card, true); + + error = sdiocard_init(card); + + (void)SDMMC_OSAMutexUnlock(&card->lock); + + return error; +} + +void SDIO_CardDeinit(sdio_card_t *card) +{ + assert(card != NULL); + + (void)SDMMC_OSAMutexLock(&card->lock, osaWaitForever_c); + (void)SDIO_CardReset(card); + (void)SDIO_SelectCard(card, false); + SDIO_SetCardPower(card, false); + (void)SDMMC_OSAMutexDestroy(&card->lock); +} + +status_t SDIO_HostInit(sdio_card_t *card) +{ + assert(card != NULL); + + if (!card->isHostReady) + { + if (SDMMCHOST_Init(card->host) != kStatus_Success) + { + return kStatus_Fail; + } + } + + if ((card->usrParam.cd->type == kSD_DetectCardByHostCD) || (card->usrParam.cd->type == kSD_DetectCardByHostDATA3)) + { + (void)SDMMCHOST_CardDetectInit(card->host, card->usrParam.cd); + } + + if (card->usrParam.sdioInt != NULL) + { + (void)SDMMCHOST_CardIntInit(card->host, card->usrParam.sdioInt); + } + + /* set the host status flag, after the card re-plug in, don't need init host again */ + card->isHostReady = true; + + return kStatus_Success; +} + +void SDIO_HostDeinit(sdio_card_t *card) +{ + assert(card != NULL); + + SDMMCHOST_Deinit(card->host); + + /* should re-init host */ + card->isHostReady = false; +} + +void SDIO_HostDoReset(sdio_card_t *card) +{ + SDMMCHOST_Reset(card->host); +} + +status_t SDIO_PollingCardInsert(sdio_card_t *card, uint32_t status) +{ + assert(card != NULL); + assert(card->usrParam.cd != NULL); + + if (card->usrParam.cd->type == kSD_DetectCardByGpioCD) + { + if (card->usrParam.cd->cardDetected == NULL) + { + return kStatus_Fail; + } + + do + { + if ((card->usrParam.cd->cardDetected() == true) && (status == (uint32_t)kSD_Inserted)) + { + SDMMC_OSADelay(card->usrParam.cd->cdDebounce_ms); + if (card->usrParam.cd->cardDetected() == true) + { + break; + } + } + + if ((card->usrParam.cd->cardDetected() == false) && (status == (uint32_t)kSD_Removed)) + { + break; + } + } while (true); + } + else + { + if (card->isHostReady == false) + { + return kStatus_Fail; + } + + if (SDMMCHOST_PollingCardDetectStatus(card->host, status, ~0U) != kStatus_Success) + { + return kStatus_Fail; + } + } + + return kStatus_Success; +} + +bool SDIO_IsCardPresent(sdio_card_t *card) +{ + assert(card != NULL); + assert(card->usrParam.cd != NULL); + + if (card->usrParam.cd->type == kSD_DetectCardByGpioCD) + { + if (card->usrParam.cd->cardDetected == NULL) + { + return false; + } + return card->usrParam.cd->cardDetected(); + } + else + { + if (card->isHostReady == false) + { + return false; + } + + if (SDMMCHOST_CardDetectStatus(card->host) == (uint32_t)kSD_Removed) + { + return false; + } + } + + return true; +} + +void SDIO_SetCardPower(sdio_card_t *card, bool enable) +{ + assert(card != NULL); + + uint32_t powerDelay = 0U; + + if (card->usrParam.pwr != NULL) + { + card->usrParam.pwr(enable); + } + else + { + SDMMCHOST_SetCardPower(card->host, enable); + } + + if (enable) + { + powerDelay = card->usrParam.powerOnDelayMS == 0U ? SDIO_POWER_ON_DELAY : card->usrParam.powerOnDelayMS; + } + else + { + powerDelay = card->usrParam.powerOffDelayMS == 0U ? SDIO_POWER_OFF_DELAY : card->usrParam.powerOffDelayMS; + } + + SDMMC_OSADelay(powerDelay); +} + +status_t SDIO_Init(sdio_card_t *card) +{ + assert(card != NULL); + assert(card->host != NULL); + + status_t error = kStatus_Success; + + if (!card->isHostReady) + { + if (SDIO_HostInit(card) != kStatus_Success) + { + error = kStatus_SDMMC_HostNotReady; + } + } + else + { + /* reset the host */ + SDIO_HostDoReset(card); + } + + if (error == kStatus_Success) + { + /* card detect */ + if (SDIO_PollingCardInsert(card, kSD_Inserted) != kStatus_Success) + { + error = kStatus_SDMMC_CardDetectFailed; + } + else + { + error = SDIO_CardInit(card); + if (error != kStatus_Success) + { + error = kStatus_SDMMC_CardInitFailed; + } + } + } + + return error; +} + +void SDIO_Deinit(sdio_card_t *card) +{ + assert(card != NULL); + + SDIO_CardDeinit(card); + SDIO_HostDeinit(card); +} + +status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool enable) +{ + assert(card != NULL); + assert(func <= kSDIO_FunctionNum7); + + uint8_t intEn = 0U; + status_t error = kStatus_Success; + + /* load io interrupt enable register */ + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, 0U, &intEn, false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + if (enable) + { + /* if already enable , do not need enable again */ + if ((((intEn >> (uint32_t)func) & 0x01U) == 0x01U) && ((intEn & 0x01U) != 0U)) + { + return kStatus_Success; + } + + /* enable the interrupt and interrupt master */ + intEn |= (1U << (uint32_t)func) | 0x01U; + card->ioIntNums++; + } + else + { + /* if already disable , do not need enable again */ + if (((intEn >> (uint32_t)func) & 0x01U) == 0x00U) + { + return kStatus_Success; + } + + /* disable the interrupt, don't disable the interrupt master here */ + intEn &= ~(1U << (uint32_t)func); + if (card->ioIntNums != 0U) + { + card->ioIntNums--; + } + } + + /* write to register */ + error = SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, intEn, &intEn, true); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_GetPendingInterrupt(sdio_card_t *card, uint8_t *pendingInt) +{ + assert(card != NULL); + + status_t error = kStatus_Success; + + /* load io interrupt enable register */ + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOIntPending, 0U, pendingInt, false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable) +{ + assert(card != NULL); + assert(func <= kSDIO_FunctionNum7); + assert(func != kSDIO_FunctionNum0); + + uint8_t ioEn = 0U, ioReady = 0U; + volatile uint32_t i = SDIO_RETRY_TIMES; + uint32_t ioReadyTimeoutMS = + (uint32_t)card->funcCIS[(uint32_t)func - 1U].ioReadyTimeout * SDIO_IO_READY_TIMEOUT_UNIT; + status_t error = kStatus_Success; + + if (ioReadyTimeoutMS != 0U) + { + /* do not poll the IO ready status, but use IO ready timeout */ + i = 1U; + } + + /* load io enable register */ + error = SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOEnable, 0U, &ioEn, false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + /* if already enable/disable , do not need enable/disable again */ + if (((ioEn >> (uint8_t)func) & 0x01U) == (enable ? 1U : 0U)) + { + return kStatus_Success; + } + + /* enable the io */ + if (enable) + { + ioEn |= (1U << (uint32_t)func); + } + else + { + ioEn &= ~(1U << (uint32_t)func); + } + + /* write to register */ + error = SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOEnable, ioEn, &ioEn, true); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + /* if enable io, need check the IO ready status */ + if (enable) + { + do + { + SDMMC_OSADelay(ioReadyTimeoutMS); + /* wait IO ready */ + error = + SDIO_IO_Access_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOReady, 0U, &ioReady, false); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + /* check if IO ready */ + if ((ioReady & (1U << (uint32_t)func)) != 0U) + { + return kStatus_Success; + } + + i--; + } while (i != 0U); + + return kStatus_Fail; + } + + return kStatus_Success; +} + +status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card != NULL); + assert(func <= kSDIO_FunctionMemory); + + uint8_t ioSel = (uint8_t)func; + status_t error = kStatus_Success; + + /* write to register */ + error = + SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegFunctionSelect, ioSel, &ioSel, true); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +status_t SDIO_AbortIO(sdio_card_t *card, sdio_func_num_t func) +{ + assert(card != NULL); + assert(func <= kSDIO_FunctionNum7); + + uint8_t ioAbort = (uint8_t)func; + status_t error = kStatus_Success; + + /* write to register */ + error = SDIO_IO_Access_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOAbort, ioAbort, &ioAbort, true); + if (kStatus_Success != error) + { + return kStatus_SDMMC_TransferFailed; + } + + return kStatus_Success; +} + +void SDIO_SetIOIRQHandler(sdio_card_t *card, sdio_func_num_t func, sdio_io_irq_handler_t handler) +{ + assert(card != NULL); + assert((func <= kSDIO_FunctionNum7) && (func != kSDIO_FunctionNum0)); + + card->ioIRQHandler[(uint32_t)func - 1U] = handler; + card->ioIntIndex = (uint8_t)func; +} + +status_t SDIO_HandlePendingIOInterrupt(sdio_card_t *card) +{ + assert(card != NULL); + + uint8_t i = 0, pendingInt = 0; + + /* call IRQ handler directly if one IRQ handler only */ + if (card->ioIntNums == 1U) + { + if (card->ioIRQHandler[card->ioIntIndex - 1U] != NULL) + { + (card->ioIRQHandler[card->ioIntIndex - 1U])(card, card->ioIntIndex); + } + } + else + { + /* get pending int firstly */ + if (SDIO_GetPendingInterrupt(card, &pendingInt) != kStatus_Success) + { + return kStatus_SDMMC_TransferFailed; + } + + for (i = 1; i <= FSL_SDIO_MAX_IO_NUMS; i++) + { + if ((pendingInt & (1U << i)) != 0U) + { + if ((card->ioIRQHandler[i - 1U]) != NULL) + { + (card->ioIRQHandler[i - 1U])(card, i); + } + } + } + } + + return kStatus_Success; +} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdio.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sdio/fsl_sdio.h similarity index 80% rename from bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdio.h rename to bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sdio/fsl_sdio.h index b740a3d7cb..04886dac2b 100644 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/inc/fsl_sdio.h +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/sdio/fsl_sdio.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -11,7 +11,8 @@ #include "fsl_sdmmc_common.h" /*! - * @addtogroup SDIOCARD + * @addtogroup sdiocard SDIO Card Driver + * @ingroup card * @{ */ @@ -19,7 +20,7 @@ * Definitions ******************************************************************************/ /*! @brief Middleware version. */ -#define FSL_SDIO_DRIVER_VERSION (MAKE_VERSION(2U, 2U, 11U)) /*2.2.11*/ +#define FSL_SDIO_DRIVER_VERSION (MAKE_VERSION(2U, 4U, 0U)) /*2.4.0*/ /*!@brief sdio device support maximum IO number */ #ifndef FSL_SDIO_MAX_IO_NUMS @@ -43,12 +44,14 @@ typedef enum _sdio_io_direction */ struct _sdio_card { - SDMMCHOST_CONFIG host; /*!< Host information */ - sdiocard_usr_param_t usrParam; /*!< user parameter */ - bool noInternalAlign; /*!< use this flag to disable sdmmc align. If disable, sdmmc will not make sure the - data buffer address is word align, otherwise all the transfer are align to low level driver */ - bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ - bool memPresentFlag; /*!< indicate if memory present */ + sdmmchost_t *host; /*!< Host information */ + sdio_usr_param_t usrParam; /*!< user parameter */ + bool noInternalAlign; /*!< use this flag to disable sdmmc align. If disable, sdmmc will not make sure the + data buffer address is word align, otherwise all the transfer are align to low level driver */ + uint8_t internalBuffer[FSL_SDMMC_CARD_INTERNAL_BUFFER_SIZE]; /*!< internal buffer */ + + bool isHostReady; /*!< use this flag to indicate if need host re-init or not*/ + bool memPresentFlag; /*!< indicate if memory present */ uint32_t busClock_Hz; /*!< SD bus clock frequency united in Hz */ uint32_t relativeAddress; /*!< Relative address of the card */ @@ -73,14 +76,14 @@ struct _sdio_card sdio_io_irq_handler_t ioIRQHandler[FSL_SDIO_MAX_IO_NUMS]; /*!< io IRQ handler */ uint8_t ioIntIndex; /*!< used to record current enabled io interrupt index */ uint8_t ioIntNums; /*!< used to record total enabled io interrupt numbers */ + sdmmc_osa_mutex_t lock; /*!< card access lock */ }; /************************************************************************************************* * API ************************************************************************************************/ #if defined(__cplusplus) -extern "C" -{ +extern "C" { #endif /*! * @name Initialization and deinitialization @@ -90,6 +93,14 @@ extern "C" /*! * @brief SDIO card init function * + * + * Thread safe function, please note that the function will create the mutex lock dynamically by default, + * so to avoid the mutex create redundantly, application must follow bellow sequence for card re-initialization + * @code + * SDIO_Deinit(card); + * SDIO_Init(card); + * @endcode + * * @param card Card descriptor. * @retval kStatus_SDMMC_GoIdleFailed * @retval kStatus_SDMMC_HandShakeOperationConditionFailed @@ -107,6 +118,8 @@ status_t SDIO_Init(sdio_card_t *card); /*! * @brief SDIO card deinit, include card and host deinit. * + * Please note it is a thread safe function. + * * @param card Card descriptor. */ void SDIO_Deinit(sdio_card_t *card); @@ -117,6 +130,13 @@ void SDIO_Deinit(sdio_card_t *card); * This function initializes the card only, make sure the host is ready when call this function, * otherwise it will return kStatus_SDMMC_HostNotReady. * + * Thread safe function, please note that the function will create the mutex lock dynamically by default, + * so to avoid the mutex create redundantly, application must follow bellow sequence for card re-initialization + * @code + * SDIO_CardDeinit(card); + * SDIO_CardInit(card); + * @endcode + * * @param card Card descriptor. * @retval kStatus_SDMMC_HostNotReady host is not ready. * @retval kStatus_SDMMC_GoIdleFailed Go idle failed. @@ -139,6 +159,8 @@ status_t SDIO_CardInit(sdio_card_t *card); * * This function deinitializes the specific card. * + * Please note it is a thread safe function. + * * @param card Card descriptor. */ void SDIO_CardDeinit(sdio_card_t *card); @@ -166,27 +188,18 @@ void SDIO_HostDeinit(sdio_card_t *card); * * This function reset the specific host. * - * @param host host descriptor. + * @param card Card descriptor. */ -void SDIO_HostReset(SDMMCHOST_CONFIG *host); +void SDIO_HostDoReset(sdio_card_t *card); /*! - * @brief power on card. - * - * The power on operation depend on host or the user define power on function. - * @param base host base address. - * @param pwr user define power control configuration - */ -void SDIO_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); - -/*! - * @brief power on card. + * @brief set card power. * * The power off operation depend on host or the user define power on function. - * @param base host base address. - * @param pwr user define power control configuration + * @param card card descriptor. + * @param enable true is power on, false is power off. */ -void SDIO_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr); +void SDIO_SetCardPower(sdio_card_t *card, bool enable); /*! * @brief set SDIO card to inactive state @@ -201,7 +214,7 @@ status_t SDIO_CardInActive(sdio_card_t *card); * @brief get SDIO card capability * * @param card Card descriptor. - * @param function IO number + * @param func IO number * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_Success */ @@ -211,8 +224,8 @@ status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func); * @brief set SDIO card block size * * @param card Card descriptor. - * @param function io number - * @param block size + * @param func io number + * @param blockSize block size * @retval kStatus_SDMMC_SetCardBlockSizeFailed * @retval kStatus_SDMMC_SDIO_InvalidArgument * @retval kStatus_Success @@ -232,7 +245,7 @@ status_t SDIO_CardReset(sdio_card_t *card); * @brief set SDIO card data bus width * * @param card Card descriptor. - * @param data bus width + * @param busWidth bus width * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_Success */ @@ -252,9 +265,9 @@ status_t SDIO_SwitchToHighSpeed(sdio_card_t *card); * @brief read SDIO card CIS for each function * * @param card Card descriptor. - * @param function io number - * @param tuple code list - * @param tuple code number + * @param func io number + * @param tupleList code list + * @param tupleNum code number * @retval kStatus_SDMMC_SDIO_ReadCISFail * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_Success @@ -265,14 +278,10 @@ status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *t * @brief sdio wait card detect function. * * Detect card through GPIO, CD, DATA3. - * * @param card card descriptor. - * @param card detect configuration - * @param waitCardStatus wait card detect status + * @param status detect status, kSD_Inserted or kSD_Removed. */ -status_t SDIO_WaitCardDetectStatus(SDMMCHOST_TYPE *hostBase, - const sdmmchost_detect_card_t *cd, - bool waitCardStatus); +status_t SDIO_PollingCardInsert(sdio_card_t *card, uint32_t status); /*! * @brief sdio card present check function. @@ -291,10 +300,12 @@ bool SDIO_IsCardPresent(sdio_card_t *card); /*! * @brief IO direct write transfer function * + * Please note it is a thread safe function. + * * @param card Card descriptor. - * @param function IO numner - * @param register address - * @param the data pinter to write + * @param func IO numner + * @param regAddr register address + * @param data the data pinter to write * @param raw flag, indicate read after write or write only * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_Success @@ -304,9 +315,11 @@ status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t /*! * @brief IO direct read transfer function * + * Please note it is a thread safe function. + * * @param card Card descriptor. - * @param function IO number - * @param register address + * @param func IO number + * @param regAddr register address * @param data pointer to read * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_Success @@ -316,10 +329,12 @@ status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t r /*! * @brief IO direct read/write transfer function * + * Please note it is a thread safe function. + * * @param card Card descriptor. * @param direction io access direction, please reference sdio_io_direction_t. - * @param function IO number - * @param register address + * @param func IO number + * @param regAddr register address * @param dataIn data to write * @param dataOut data pointer for readback data, support both for read and write, when application want readback * the data after write command, dataOut should not be NULL. @@ -337,12 +352,14 @@ status_t SDIO_IO_RW_Direct(sdio_card_t *card, /*! * @brief IO extended write transfer function * + * Please note it is a thread safe function. + * * @param card Card descriptor. - * @param function IO number - * @param register address - * @param data buffer to write - * @param data count - * @param write flags + * @param func IO number + * @param regAddr register address + * @param buffer data buffer to write + * @param count data count + * @param flags write flags * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_SDMMC_SDIO_InvalidArgument * @retval kStatus_Success @@ -352,12 +369,14 @@ status_t SDIO_IO_Write_Extended( /*! * @brief IO extended read transfer function * + * Please note it is a thread safe function. + * * @param card Card descriptor. - * @param function IO number - * @param register address - * @param data buffer to read - * @param data count - * @param write flags + * @param func IO number + * @param regAddr register address + * @param buffer data buffer to read + * @param count data count + * @param flags write flags * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_SDMMC_SDIO_InvalidArgument * @retval kStatus_Success @@ -368,8 +387,8 @@ status_t SDIO_IO_Read_Extended( * @brief enable IO interrupt * * @param card Card descriptor. - * @param function IO number - * @param enable/disable flag + * @param func IO number + * @param enable enable/disable flag * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_Success */ @@ -379,8 +398,8 @@ status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool en * @brief enable IO and wait IO ready * * @param card Card descriptor. - * @param function IO number - * @param enable/disable flag + * @param func IO number + * @param enable enable/disable flag * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_Success */ @@ -390,7 +409,7 @@ status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable); * @brief select IO * * @param card Card descriptor. - * @param function IO number + * @param func IO number * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_Success */ @@ -400,7 +419,7 @@ status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func); * @brief Abort IO transfer * * @param card Card descriptor. - * @param function IO number + * @param func IO number * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_Success */ @@ -420,7 +439,6 @@ status_t SDIO_SetDriverStrength(sdio_card_t *card, sd_driver_strength_t driverSt * @brief Enable/Disable Async interrupt. * * @param card Card descriptor. - * @param func function io number. * @param enable true is enable, false is disable. * @retval kStatus_SDMMC_TransferFailed * @retval kStatus_Success @@ -442,10 +460,11 @@ status_t SDIO_GetPendingInterrupt(sdio_card_t *card, uint8_t *pendingInt); * This function can be used for trnansfer direct/extend command. * Please pay attention to the non-align data buffer address transfer, * if data buffer address can not meet host controller internal DMA requirement, sdio driver will try to use - internal align buffer if data size is not bigger than internal buffer size, + * internal align buffer if data size is not bigger than internal buffer size, * Align address transfer always can get a better performance, so if application want sdio driver make sure buffer - address align, - * please redefine the SDMMC_GLOBAL_BUFFER_SIZE macro to a value which is big enough for your application. + * address align, + * + * Please note it is a thread safe function. * * @param card card descriptor. * @param cmd command to transfer @@ -471,7 +490,7 @@ status_t SDIO_IO_Transfer(sdio_card_t *card, * * @param card card descriptor. * @param func function io number. - * @param handler, io IRQ handler. + * @param handler io IRQ handler. */ void SDIO_SetIOIRQHandler(sdio_card_t *card, sdio_func_num_t func, sdio_io_irq_handler_t handler); @@ -480,17 +499,18 @@ void SDIO_SetIOIRQHandler(sdio_card_t *card, sdio_func_num_t func, sdio_io_irq_h * This function is used to handle the pending io interrupt. * To reigster a IO IRQ handler, * @code - * //initialization * SDIO_EnableIOInterrupt(card, 0, true); * SDIO_SetIOIRQHandler(card, 0, func0_handler); - * //call it in interrupt callback - * SDIO_HandlePendingIOInterrupt(card); + * @endcode + * call it in interrupt callback * @code + * SDIO_HandlePendingIOInterrupt(card); + * @endcode * To releae a IO IRQ handler, * @code * SDIO_EnableIOInterrupt(card, 0, false); * SDIO_SetIOIRQHandler(card, 0, NULL); - * @code + * @endcode * @param card card descriptor. * * @retval kStatus_SDMMC_TransferFailed @@ -503,5 +523,7 @@ status_t SDIO_HandlePendingIOInterrupt(sdio_card_t *card); #if defined(__cplusplus) } #endif -/*! @} */ + +/* @} */ + #endif /* _FSL_SDIO_H_*/ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_mmc.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_mmc.c deleted file mode 100644 index 26796a3573..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_mmc.c +++ /dev/null @@ -1,2671 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include "fsl_mmc.h" - -/******************************************************************************* - * Definitons - ******************************************************************************/ -/*! @brief The divide value used to avoid float point calculation when calculate max speed in normal mode. */ -#define DIVIDER_IN_TRANSFER_SPEED (10U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Send SELECT_CARD command to set the card enter or exit transfer state. - * - * @param card Card descriptor. - * @param isSelected True to enter transfer state. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline MMC_SelectCard(mmc_card_t *card, bool isSelected); - -/*! - * @brief Wait write process complete. - * - * @param card Card descriptor. - * @retval kStatus_Timeout Operation timeout. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_WaitWriteComplete(mmc_card_t *card); - -/*! - * @brief Send SET_BLOCK_COUNT command. - * - * @param card Card descriptor. - * @param blockCount Block count. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline MMC_SetBlockCount(mmc_card_t *card, uint32_t blockCount); - -/*! - * @brief Send GO_IDLE command to reset all cards to idle state - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline MMC_GoIdle(mmc_card_t *card); - -/*! - * @brief Send STOP_TRANSMISSION command to card to stop ongoing data transferring. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_StopTransmission(mmc_card_t *card); - -/*! - * @brief Send SET_BLOCK_SIZE command to set the block length in bytes for MMC cards. - * - * @param card Card descriptor. - * @param blockSize Block size. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline MMC_SetBlockSize(mmc_card_t *card, uint32_t blockSize); - -/*! - * @brief switch voltage. - * - * @param card Card descriptor. - * @param opcode use to send operation condition - * @retval kStatus_SDMMC_HostNotSupport Host doesn't support the voltage window to access the card. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SwitchVoltage(mmc_card_t *card, uint32_t *opCode); - -/*! - * @brief Send SEND_OPERATION_CONDITION command to validate if the card support host's voltage window - * - * @param card Card descriptor. - * @param arg Command argument. - * @retval kStatus_SDMMC_TransferFailed Transfers failed. - * @retval kStatus_Timeout Operation timeout. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SendOperationCondition(mmc_card_t *card, uint32_t arg); - -/*! - * @brief Send SET_RCA command to set the relative address of the card. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SetRelativeAddress(mmc_card_t *card); - -/*! - * @brief Decode CSD register content. - * - * @param card Card descriptor. - * @param rawCsd raw CSD register content. - */ -static void MMC_DecodeCsd(mmc_card_t *card, uint32_t *rawCsd); - -/*! - * @brief Set the card to max transfer speed in non-high speed mode. - * - * @param card Card descriptor. - */ -static void MMC_SetMaxFrequency(mmc_card_t *card); - -/*! - * @brief Set erase unit size of the card - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure Extended CSD failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SetMaxEraseUnitSize(mmc_card_t *card); - -/*! - * @brief Send SWITCH command to set the specific byte in Extended CSD. - * - * Example: - @code - mmc_extended_csd_config_t config; - config.accessMode = kMMC_ExtendedCsdAccessModeSetBits; - config.ByteIndex = 1U; - config.ByteValue = 0x033U; - config.commandSet = kMMC_CommandSetStandard; - MMC_SetExtendedCsdConfig(card, &config); - @endcode - * - * @param card Card descriptor. - * @param config Configuration for Extended CSD. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SetExtendedCsdConfig(mmc_card_t *card, const mmc_extended_csd_config_t *config); - -/*! - * @brief Decode the Extended CSD register - * - * @param card Card descriptor. - * @param rawExtendedCsd Raw extended CSD register content. - */ -static void MMC_DecodeExtendedCsd(mmc_card_t *card, uint32_t *rawExtendedCsd); - -/*! - * @brief Send SEND_EXTENDED_CSD command to get the content of the Extended CSD register - * Allow read the special byte index value if targetAddr is not NULL - * @param card Card descriptor. - * @param targetAddr Pointer to store the target byte value. - * @param byteIndex Target byte index. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SendExtendedCsd(mmc_card_t *card, uint8_t *targetAddr, uint32_t byteIndex); - -/*! - * @brief Set the power class of the card at specific bus width and host intended voltage window. - * - * @param card Card descriptor. - * @return The power class switch status. - */ -static status_t MMC_SetPowerClass(mmc_card_t *card); - -/*! - * @brief Send test pattern to get the functional pin in the MMC bus - * - * @param card Card descriptor. - * @param blockSize Test pattern block size. - * @param pattern Test pattern data buffer. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SendTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern); - -/*! - * @brief Receive test pattern reversed by the card. - * - * @param card Card descriptor. - * @param blockSize Test pattern block size. - * @param pattern Test pattern data buffer. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_ReceiveTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern); - -/*! - * @brief Bus test procedure to get the functional data pin in the bus - * - * @param card Card descriptor. - * @param width Data bus width. - * @retval kStatus_SDMMC_SendTestPatternFailed Send test pattern failed. - * @retval kStatus_SDMMC_ReceiveTestPatternFailed Receive test pattern failed. - * @retval kStatus_Fail Test failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_TestDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width); - -/*! - * @brief Send SET_BUS_WIDTH command to set the bus width. - * - * @param card Card descriptor. - * @param width Data bus width. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SetDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width); - -/*! - * @brief Set max the bus width automatically - * - * @param card Card descriptor. - * @param targetTiming switch target timing - * @retval kStatus_SDMMC_SetDataBusWidthFailed switch fail. - * @retval kStatus_Success switch success. - */ -static status_t MMC_SetMaxDataBusWidth(mmc_card_t *card, mmc_high_speed_timing_t targetTiming); - -/*! - * @brief Switch the card to high speed mode - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support high speed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SelectBusTiming(mmc_card_t *card); - -/*! - * @brief select card HS_TIMING value and card driver strength - * - * @param card Card descriptor. - * @param timing Timing interface value. - * @param driverStrength driver strength value. - * @retval kStatus_Success switch success. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed , config extend csd register fail. - */ -static status_t MMC_SwitchHSTiming(mmc_card_t *card, uint8_t timing, uint8_t driverStrength); - -/*! - * @brief switch to HS400 mode. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. - * @retval kStatus_SDMMC_SwitchBusTimingFailed switch bus timing fail. - * @retval kStatus_SDMMC_SetDataBusWidthFailed switch bus width fail. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SwitchToHS400(mmc_card_t *card); - -/*! - * @brief switch to HS200 mode. - * - * @param card Card descriptor. - * @param freq Target frequency. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. - * @retval kStatus_SDMMC_TuningFail tuning fail. - * @retval kStatus_SDMMC_SetDataBusWidthFailed switch bus width fail. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SwitchToHS200(mmc_card_t *card, uint32_t freq); - -/*! - * @brief switch to HS400 mode. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_ConfigureExtendedCsdFailed Configure extended CSD failed. - * @retval kStatus_SDMMC_SetDataBusWidthFailed switch bus width fail. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SwitchToHighSpeed(mmc_card_t *card); - -/*! - * @brief Decode CID register - * - * @param card Card descriptor. - * @param rawCid Raw CID register content. - */ -static void MMC_DecodeCid(mmc_card_t *card, uint32_t *rawCid); - -/*! - * @brief Send ALL_SEND_CID command - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_AllSendCid(mmc_card_t *card); - -/*! - * @brief Send SEND_CSD command to get CSD from card - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_SendCsd(mmc_card_t *card); - -/*! - * @brief Check if the block range accessed is within current partition. - * - * @param card Card descriptor. - * @param startBlock Start block to access. - * @param blockCount Block count to access. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_CheckBlockRange(mmc_card_t *card, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief Check if the erase group range accessed is within current partition. - * - * @param card Card descriptor. - * @param startGroup Start group to access. - * @param endGroup End group to access. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_CheckEraseGroupRange(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup); - -/*! - * @brief MMC excute tuning function. - * - * @param card Card descriptor. - * @retval kStatus_Success Operate successfully. - * @retval kStatus_SDMMC_TuningFail tuning fail. - * @retval kStatus_SDMMC_TransferFailed transfer fail - */ -static status_t inline MMC_ExecuteTuning(mmc_card_t *card); - -/*! - * @brief Read data from specific MMC card - * - * @param card Card descriptor. - * @param buffer Buffer to save received data. - * @param startBlock Start block to read. - * @param blockSize Block size. - * @param blockCount Block count to read. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. - * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_Read( - mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); - -/*! - * @brief Write data from specific MMC card - * - * @param card Card descriptor. - * @param buffer Buffer to hold the data to write. - * @param startBlock Start block to write. - * @param blockSize Block size. - * @param blockCount Block count to write. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_SDMMC_SetBlockCountFailed Set block count failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t MMC_Write( - mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); - -/*! - * @brief card transfer function wrapper - * This function is used to do tuning before transfer if the cmd won't casue re-tuning - * request, then you can call host transfer function directly - * @param card Card descriptor. - * @param content Transfer content. - * @param retry Retry times. - * @retval kStatus_SDMMC_TransferFailed transfer fail - * @retval kStatus_SDMMC_TuningFail tuning fail - * @retval kStatus_Success transfer success - */ -static status_t MMC_Transfer(mmc_card_t *card, SDMMCHOST_TRANSFER *content, uint32_t retry); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* Frequency unit defined in TRANSFER SPEED field in CSD */ -static const uint32_t g_transerSpeedFrequencyUnit[] = {100000U, 1000000U, 10000000U, 100000000U}; -/* The multiplying value defined in TRANSFER SPEED field in CSD */ -static const uint32_t g_transerSpeedMultiplierFactor[] = {0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, - 35U, 40U, 45U, 52U, 55U, 60U, 70U, 80U}; -/* g_sdmmc statement */ -extern uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)]; - -/******************************************************************************* - * Code - ******************************************************************************/ -static status_t inline MMC_SelectCard(mmc_card_t *card, bool isSelected) -{ - assert(card); - - return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); -} - -static status_t inline MMC_SetBlockCount(mmc_card_t *card, uint32_t blockCount) -{ - assert(card); - - return SDMMC_SetBlockCount(card->host.base, card->host.transfer, blockCount); -} - -static status_t inline MMC_GoIdle(mmc_card_t *card) -{ - assert(card); - - return SDMMC_GoIdle(card->host.base, card->host.transfer); -} - -static status_t inline MMC_SetBlockSize(mmc_card_t *card, uint32_t blockSize) -{ - assert(card); - - return SDMMC_SetBlockSize(card->host.base, card->host.transfer, blockSize); -} - -static status_t MMC_ExecuteTuning(mmc_card_t *card) -{ - assert(card); - - uint32_t blockSize = 0U; - - if (card->busWidth == kMMC_DataBusWidth4bit) - { - blockSize = 64U; - } - else if (card->busWidth == kMMC_DataBusWidth8bit) - { - blockSize = 128U; - } - else - { - /* do not need tuning in this situation */ - return kStatus_Success; - } - - return SDMMC_ExecuteTuning(card->host.base, card->host.transfer, kMMC_SendTuningBlock, blockSize); -} - -static status_t MMC_Transfer(mmc_card_t *card, SDMMCHOST_TRANSFER *content, uint32_t retry) -{ - assert(card->host.transfer); - assert(content); - status_t error; - - do - { - error = card->host.transfer(card->host.base, content); -#if SDMMC_ENABLE_SOFTWARE_TUNING - if (((error == SDMMCHOST_RETUNING_REQUEST) || (error == SDMMCHOST_TUNING_ERROR)) && - ((card->busTiming == kMMC_HighSpeed200Timing) || (card->busTiming == kMMC_HighSpeed400Timing))) - { - /* tuning error need reset tuning circuit */ - if (error == SDMMCHOST_TUNING_ERROR) - { - SDMMCHOST_RESET_TUNING(card->host.base, 100U); - } - /* execute re-tuning */ - if (MMC_ExecuteTuning(card) != kStatus_Success) - { - error = kStatus_SDMMC_TuningFail; - break; - } - else - { - continue; - } - } - else -#endif - if (error != kStatus_Success) - { - error = kStatus_SDMMC_TransferFailed; - } - else - { - } - - if (retry != 0U) - { - retry--; - } - else - { - break; - } - - } while (error != kStatus_Success); - - return error; -} - -static status_t MMC_WaitWriteComplete(mmc_card_t *card) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - - command.index = kSDMMC_SendStatus; - command.argument = card->relativeAddress << 16U; - command.responseType = kCARD_ResponseTypeR1; - - do - { - content.command = &command; - content.data = 0U; - if (kStatus_Success != MMC_Transfer(card, &content, 2U)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* check the response error */ - if ((command.response[0U] & (SDMMC_R1_ALL_ERROR_FLAG | SDMMC_MASK(kSDMMC_R1SwitchErrorFlag)))) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - if ((command.response[0U] & SDMMC_MASK(kSDMMC_R1ReadyForDataFlag)) && - (SDMMC_R1_CURRENT_STATE(command.response[0U]) != kSDMMC_R1StateProgram)) - { - break; - } - } while (true); - - return kStatus_Success; -} - -static status_t MMC_StopTransmission(mmc_card_t *card) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - - command.index = kSDMMC_StopTransmission; - command.argument = 0U; - command.type = kCARD_CommandTypeAbort; - command.responseType = kCARD_ResponseTypeR1b; - command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; - - content.command = &command; - content.data = 0U; - if (kStatus_Success != MMC_Transfer(card, &content, 2U)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -static status_t MMC_SwitchVoltage(mmc_card_t *card, uint32_t *opCode) -{ - mmc_voltage_window_t tempVoltage = kMMC_VoltageWindowNone; - /* Get host's voltage window. */ - if (((kSDMMCHOST_SupportV330 != SDMMCHOST_NOT_SUPPORT) || (kSDMMCHOST_SupportV300 != SDMMCHOST_NOT_SUPPORT)) && - (card->ocr & MMC_OCR_V270TO360_MASK) && ((card->hostVoltageWindowVCC == kMMC_VoltageWindowNone) || - (card->hostVoltageWindowVCC == kMMC_VoltageWindows270to360))) - { - /* Save host intended voltage range */ - tempVoltage = kMMC_VoltageWindows270to360; - /* set the opcode */ - *opCode = MMC_OCR_V270TO360_MASK; - /* power off the card first */ - SDMMCHOST_ENABLE_MMC_POWER(false); - /* power off time */ - SDMMCHOST_Delay(1U); - /*switch voltage to 3.3V*/ - SDMMCHOST_SWITCH_VCC_TO_330V(); - /* repower the card */ - SDMMCHOST_ENABLE_MMC_POWER(true); - /* meet emmc spec, wait 1ms and 74 clocks */ - SDMMCHOST_Delay(2U); - } - - if ((kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) && (card->ocr & MMC_OCR_V170TO195_MASK) && - ((card->hostVoltageWindowVCC == kMMC_VoltageWindowNone) || - (card->hostVoltageWindowVCC == kMMC_VoltageWindow170to195))) - { - /* Save host intended voltage range */ - tempVoltage = kMMC_VoltageWindow170to195; - /* set the opcode */ - *opCode = MMC_OCR_V170TO195_MASK; - /* power off the card first */ - SDMMCHOST_ENABLE_MMC_POWER(false); - /* power off time */ - SDMMCHOST_Delay(1U); - /* switch voltage to 1.8V */ - SDMMCHOST_SWITCH_VCC_TO_180V(); - /* repower the card */ - SDMMCHOST_ENABLE_MMC_POWER(true); - /* meet emmc spec, wait 1ms and 74 clocks */ - SDMMCHOST_Delay(2U); - } - - card->hostVoltageWindowVCC = tempVoltage; - - return kStatus_Success; -} - -static status_t MMC_SendOperationCondition(mmc_card_t *card, uint32_t arg) -{ - assert(card); - assert(card->host.transfer); - - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_TRANSFER content = {0}; - status_t error; - uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; - - /* Send CMD1 with the intended voltage range in the argument(either 0x00FF8000 or 0x00000080) */ - command.index = kMMC_SendOperationCondition; - command.argument = arg; - command.responseType = kCARD_ResponseTypeR3; - - content.command = &command; - content.data = NULL; - do - { - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* record OCR register */ - card->ocr = command.response[0U]; - - if ((arg == 0U) && (command.response[0U] != 0U)) - { - error = kStatus_Success; - } - /* Repeat CMD1 until the busy bit is cleared. */ - else if (!(command.response[0U] & MMC_OCR_BUSY_MASK)) - { - error = kStatus_Timeout; - } - else - { - error = kStatus_Success; - if (((card->ocr & MMC_OCR_ACCESS_MODE_MASK) >> MMC_OCR_ACCESS_MODE_SHIFT) == kMMC_AccessModeSector) - { - card->flags |= kMMC_SupportHighCapacityFlag; - } - } - } while ((i--) && (error != kStatus_Success)); - - return error; -} - -static status_t MMC_SetRelativeAddress(mmc_card_t *card) -{ - assert(card); - assert(card->host.transfer); - - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_TRANSFER content = {0}; - - /* Send CMD3 with a chosen relative address, with value greater than 1 */ - command.index = kMMC_SetRelativeAddress; - command.argument = (MMC_DEFAULT_RELATIVE_ADDRESS << 16U); - command.responseType = kCARD_ResponseTypeR1; - - content.command = &command; - content.data = NULL; - if ((kStatus_Success == card->host.transfer(card->host.base, &content)) || - (!((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG))) - { - card->relativeAddress = MMC_DEFAULT_RELATIVE_ADDRESS; - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static void MMC_DecodeCsd(mmc_card_t *card, uint32_t *rawCsd) -{ - assert(card); - assert(rawCsd); - - mmc_csd_t *csd; - uint32_t multiplier; - - csd = &(card->csd); - csd->csdStructureVersion = (uint8_t)((rawCsd[3U] & 0xC0000000U) >> 30U); - csd->systemSpecificationVersion = (uint8_t)((rawCsd[3U] & 0x3C000000U) >> 26U); - csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF0000U) >> 16U); - csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); - csd->transferSpeed = (uint8_t)(rawCsd[3U] & 0xFFU); - csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF00000U) >> 20U); - /* Max block length read/write one time */ - csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF0000U) >> 16U); - if (rawCsd[2U] & 0x8000U) - { - csd->flags |= kMMC_CsdReadBlockPartialFlag; - } - if (rawCsd[2U] & 0x4000U) - { - csd->flags |= kMMC_CsdWriteBlockMisalignFlag; - } - if (rawCsd[2U] & 0x2000U) - { - csd->flags |= kMMC_CsdReadBlockMisalignFlag; - } - if (rawCsd[2U] & 0x1000U) - { - csd->flags |= kMMC_CsdDsrImplementedFlag; - } - csd->deviceSize = (uint16_t)(((rawCsd[2U] & 0x3FFU) << 2U) + ((rawCsd[1U] & 0xC0000000U) >> 30U)); - csd->readCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x38000000U) >> 27U); - csd->readCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x07000000U) >> 24U); - csd->writeCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x00E00000U) >> 21U); - csd->writeCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x001C0000U) >> 18U); - csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x00038000U) >> 15U); - csd->eraseGroupSize = (uint8_t)((rawCsd[1U] & 0x00007C00U) >> 10U); - csd->eraseGroupSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x000003E0U) >> 5U); - csd->writeProtectGroupSize = (uint8_t)(rawCsd[1U] & 0x0000001FU); - if (rawCsd[0U] & 0x80000000U) - { - csd->flags |= kMMC_CsdWriteProtectGroupEnabledFlag; - } - csd->defaultEcc = (uint8_t)((rawCsd[0U] & 0x60000000U) >> 29U); - csd->writeSpeedFactor = (uint8_t)((rawCsd[0U] & 0x1C000000U) >> 26U); - csd->maxWriteBlockLength = (uint8_t)((rawCsd[0U] & 0x03C00000U) >> 22U); - if (rawCsd[0U] & 0x00200000U) - { - csd->flags |= kMMC_CsdWriteBlockPartialFlag; - } - if (rawCsd[0U] & 0x00010000U) - { - csd->flags |= kMMC_ContentProtectApplicationFlag; - } - if (rawCsd[0U] & 0x00008000U) - { - csd->flags |= kMMC_CsdFileFormatGroupFlag; - } - if (rawCsd[0U] & 0x00004000U) - { - csd->flags |= kMMC_CsdCopyFlag; - } - if (rawCsd[0U] & 0x00002000U) - { - csd->flags |= kMMC_CsdPermanentWriteProtectFlag; - } - if (rawCsd[0U] & 0x00001000U) - { - csd->flags |= kMMC_CsdTemporaryWriteProtectFlag; - } - csd->fileFormat = (uint8_t)((rawCsd[0U] & 0x00000C00U) >> 10U); - csd->eccCode = (uint8_t)((rawCsd[0U] & 0x00000300U) >> 8U); - - /* Calculate the device total block count. */ - /* For the card capacity of witch higher than 2GB, the maximum possible value should be set to this register - is 0xFFF. */ - if (card->csd.deviceSize != 0xFFFU) - { - multiplier = (2U << (card->csd.deviceSizeMultiplier + 2U - 1U)); - card->userPartitionBlocks = (((card->csd.deviceSize + 1U) * multiplier) / FSL_SDMMC_DEFAULT_BLOCK_SIZE); - } - - card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; -} - -static void MMC_SetMaxFrequency(mmc_card_t *card) -{ - assert(card); - - uint32_t frequencyUnit; - uint32_t multiplierFactor; - uint32_t maxBusClock_Hz; - - /* g_fsdhcCommandUnitInTranSpeed and g_transerSpeedMultiplierFactor are used to calculate the max speed in normal - mode not high speed mode. - For cards supporting version 4.0, 4.1, and 4.2 of the specification, the value shall be 20MHz(0x2A). - For cards supporting version 4.3, the value shall be 26 MHz (0x32H). In High speed mode, the max - frequency is decided by CARD_TYPE in Extended CSD. */ - frequencyUnit = g_transerSpeedFrequencyUnit[READ_MMC_TRANSFER_SPEED_FREQUENCY_UNIT(card->csd)]; - multiplierFactor = g_transerSpeedMultiplierFactor[READ_MMC_TRANSFER_SPEED_MULTIPLIER(card->csd)]; - maxBusClock_Hz = (frequencyUnit * multiplierFactor) / DIVIDER_IN_TRANSFER_SPEED; - card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, maxBusClock_Hz); -} - -static status_t MMC_SetMaxEraseUnitSize(mmc_card_t *card) -{ - assert(card); - - uint32_t erase_group_size; - uint32_t erase_group_multiplier; - mmc_extended_csd_config_t extendedCsdconfig; - - if (((!(card->flags & kMMC_SupportHighCapacityFlag)) || (card->extendedCsd.highCapacityEraseUnitSize == 0)) || - (card->extendedCsd.highCapacityEraseTimeout == 0)) - { - erase_group_size = card->csd.eraseGroupSize; - erase_group_multiplier = card->csd.eraseGroupSizeMultiplier; - card->eraseGroupBlocks = ((erase_group_size + 1U) * (erase_group_multiplier + 1U)); - } - else - { - /* Erase Unit Size = 512Kbyte * HC_ERASE_GRP_SIZE. Block size is 512 bytes. */ - card->eraseGroupBlocks = (card->extendedCsd.highCapacityEraseUnitSize * 1024U); - /* Enable high capacity erase unit size. */ - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeSetBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexEraseGroupDefinition; - extendedCsdconfig.ByteValue = 0x01U; /* The high capacity erase unit size enable bit is bit 0 */ - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - } - - return kStatus_Success; -} - -static status_t MMC_SetExtendedCsdConfig(mmc_card_t *card, const mmc_extended_csd_config_t *config) -{ - assert(card); - assert(card->host.transfer); - assert(config); - - uint32_t parameter = 0U; - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_TRANSFER content = {0}; - - parameter |= ((uint32_t)(config->commandSet) << MMC_SWITCH_COMMAND_SET_SHIFT); - parameter |= ((uint32_t)(config->ByteValue) << MMC_SWITCH_VALUE_SHIFT); - parameter |= ((uint32_t)(config->ByteIndex) << MMC_SWITCH_BYTE_INDEX_SHIFT); - parameter |= ((uint32_t)(config->accessMode) << MMC_SWITCH_ACCESS_MODE_SHIFT); - - command.index = kMMC_Switch; - command.argument = parameter; - command.responseType = kCARD_ResponseTypeR1b; /* Send switch command to set the pointed byte in Extended CSD. */ - command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG | SDMMC_MASK(kSDMMC_R1SwitchErrorFlag); - - content.command = &command; - content.data = NULL; - if (kStatus_Success != MMC_Transfer(card, &content, 2U)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Wait for the card write process complete because of that card read process and write process use one buffer. */ - if (kStatus_Success != MMC_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - return kStatus_Success; -} - -static void MMC_DecodeExtendedCsd(mmc_card_t *card, uint32_t *rawExtendedCsd) -{ - assert(card); - assert(rawExtendedCsd); - - uint8_t *buffer = (uint8_t *)rawExtendedCsd; - mmc_extended_csd_t *extendedCsd = &(card->extendedCsd); - - /* Extended CSD is transferred as a data block from least byte indexed 0. */ - extendedCsd->bootPartitionWP = buffer[173U]; - extendedCsd->bootWPStatus = buffer[174U]; - extendedCsd->highDensityEraseGroupDefinition = buffer[175U]; - extendedCsd->bootDataBusConditions = buffer[177U]; - extendedCsd->bootConfigProtect = buffer[178U]; - extendedCsd->partitionConfig = buffer[179U]; - extendedCsd->eraseMemoryContent = buffer[181U]; - extendedCsd->dataBusWidth = buffer[183U]; - extendedCsd->highSpeedTiming = buffer[185U]; - extendedCsd->powerClass = buffer[187U]; - extendedCsd->commandSetRevision = buffer[189U]; - extendedCsd->commandSet = buffer[191U]; - extendedCsd->extendecCsdVersion = buffer[192U]; - extendedCsd->csdStructureVersion = buffer[194U]; - extendedCsd->partitionAttribute = buffer[156U]; - extendedCsd->extPartitionSupport = buffer[494U]; - extendedCsd->cardType = buffer[196U]; - /* This field define the type of the card. The only currently valid values for this field are 0x01 and 0x03. */ - card->flags |= extendedCsd->cardType; - - extendedCsd->ioDriverStrength = buffer[197U]; - - extendedCsd->powerClass52MHz195V = buffer[200U]; - extendedCsd->powerClass26MHz195V = buffer[201U]; - extendedCsd->powerClass52MHz360V = buffer[202U]; - extendedCsd->powerClass26MHz360V = buffer[203U]; - extendedCsd->powerClass200MHZVCCQ130VVCC360V = buffer[236U]; - extendedCsd->powerClass200MHZVCCQ195VVCC360V = buffer[237U]; - extendedCsd->powerClass52MHZDDR195V = buffer[238U]; - extendedCsd->powerClass52MHZDDR360V = buffer[239U]; - extendedCsd->powerClass200MHZDDR360V = buffer[253U]; - extendedCsd->minimumReadPerformance4Bit26MHz = buffer[205U]; - extendedCsd->minimumWritePerformance4Bit26MHz = buffer[206U]; - extendedCsd->minimumReadPerformance8Bit26MHz4Bit52MHz = buffer[207U]; - extendedCsd->minimumWritePerformance8Bit26MHz4Bit52MHz = buffer[208U]; - extendedCsd->minimumReadPerformance8Bit52MHz = buffer[209U]; - extendedCsd->minimumWritePerformance8Bit52MHz = buffer[210U]; - extendedCsd->minReadPerformance8bitAt52MHZDDR = buffer[234U]; - extendedCsd->minWritePerformance8bitAt52MHZDDR = buffer[235U]; - /* Get user partition size. */ - extendedCsd->sectorCount = ((((uint32_t)buffer[215U]) << 24U) + (((uint32_t)buffer[214U]) << 16U) + - (((uint32_t)buffer[213U]) << 8U) + (uint32_t)buffer[212U]); - if (card->flags & kMMC_SupportHighCapacityFlag) - { - card->userPartitionBlocks = card->extendedCsd.sectorCount; - } - - extendedCsd->sleepAwakeTimeout = buffer[217U]; - extendedCsd->sleepCurrentVCCQ = buffer[219U]; - extendedCsd->sleepCurrentVCC = buffer[220U]; - extendedCsd->highCapacityWriteProtectGroupSize = buffer[221U]; - extendedCsd->reliableWriteSectorCount = buffer[222U]; - extendedCsd->highCapacityEraseTimeout = buffer[223U]; - extendedCsd->highCapacityEraseUnitSize = buffer[224U]; - extendedCsd->accessSize = buffer[225U]; - - /* Get boot partition size: 128KB * BOOT_SIZE_MULT*/ - card->bootPartitionBlocks = ((128U * 1024U * buffer[226U]) / FSL_SDMMC_DEFAULT_BLOCK_SIZE); - - /* Check if card support boot mode. */ - if (buffer[228U] & 0x1U) - { - card->flags |= kMMC_SupportAlternateBootFlag; - } - else if (buffer[228U] & 0x2U) - { - card->flags |= kMMC_SupportDDRBootFlag; - } - else if (buffer[228U] & 0x4U) - { - card->flags |= kMMC_SupportHighSpeedBootFlag; - } - else - { - } - /* cache size unit 1kb */ - extendedCsd->cacheSize = (((uint32_t)buffer[252U]) << 24) | (((uint32_t)buffer[251U]) << 16) | - (((uint32_t)buffer[250U]) << 8) | (((uint32_t)buffer[249U])); - - extendedCsd->supportedCommandSet = buffer[504U]; -} - -static status_t MMC_SendExtendedCsd(mmc_card_t *card, uint8_t *targetAddr, uint32_t byteIndex) -{ - assert(card); - assert(card->host.transfer); - - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_DATA data = {0}; - uint32_t i; - - command.index = kMMC_SendExtendedCsd; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1; - - data.blockCount = 1U; - data.blockSize = MMC_EXTENDED_CSD_BYTES; - data.rxData = card->rawExtendedCsd; - - content.command = &command; - content.data = &data; - if ((kStatus_Success == card->host.transfer(card->host.base, &content)) && - (!(command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG))) - { - /* The response is from bit 127:8 in R2, corresponding to command.response[3][31:0] to - command.response[0U][31:8] */ - switch (card->host.config.endianMode) - { - case kSDMMCHOST_EndianModeLittle: - /* Doesn't need to switch byte sequence when decode bytes as little endian sequence. */ - break; - case kSDMMCHOST_EndianModeBig: - /* In big endian mode, the SD bus byte transferred first is the byte stored in highest position - in a word which cause 4 byte's sequence in a word is not consistent with their original sequence - from card. */ - for (i = 0U; i < MMC_EXTENDED_CSD_BYTES / 4U; i++) - { - card->rawExtendedCsd[i] = SWAP_WORD_BYTE_SEQUENCE(card->rawExtendedCsd[i]); - } - break; - case kSDMMCHOST_EndianModeHalfWordBig: - for (i = 0U; i < MMC_EXTENDED_CSD_BYTES / 4U; i++) - { - card->rawExtendedCsd[i] = SWAP_HALF_WROD_BYTE_SEQUENCE(card->rawExtendedCsd[i]); - } - break; - default: - return kStatus_SDMMC_NotSupportYet; - } - if (targetAddr != NULL) - { - *targetAddr = ((uint8_t *)card->rawExtendedCsd)[byteIndex]; - } - else - { - MMC_DecodeExtendedCsd(card, card->rawExtendedCsd); - } - - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static status_t MMC_SetPowerClass(mmc_card_t *card) -{ - assert(card); - - uint8_t mask = 0, shift = 0U; - uint8_t powerClass = 0; - mmc_extended_csd_config_t extendedCsdconfig; - - if ((card->busWidth == kMMC_DataBusWidth4bit) || (card->busWidth == kMMC_DataBusWidth4bitDDR)) - { - mask = MMC_POWER_CLASS_4BIT_MASK; /* The mask of 4 bit bus width's power class */ - shift = 0U; - } - else if ((card->busWidth == kMMC_DataBusWidth8bit) || (card->busWidth == kMMC_DataBusWidth8bitDDR)) - { - mask = MMC_POWER_CLASS_8BIT_MASK; /* The mask of 8 bit bus width's power class */ - shift = 4U; - } - else - { - return kStatus_Success; - } - - switch (card->hostVoltageWindowVCC) - { - case kMMC_VoltageWindows270to360: - - if (card->busTiming == kMMC_HighSpeed200Timing) - { - if (card->hostVoltageWindowVCCQ == kMMC_VoltageWindow170to195) - { - powerClass = ((card->extendedCsd.powerClass200MHZVCCQ195VVCC360V) & mask); - } - else if (card->hostVoltageWindowVCCQ == kMMC_VoltageWindow120) - { - powerClass = ((card->extendedCsd.powerClass200MHZVCCQ130VVCC360V) & mask); - } - } - else if (card->busTiming == kMMC_HighSpeed400Timing) - { - powerClass = ((card->extendedCsd.powerClass200MHZDDR360V) & mask); - } - else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busWidth > kMMC_DataBusWidth8bit)) - { - powerClass = ((card->extendedCsd.powerClass52MHZDDR360V) & mask); - } - else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busClock_Hz > MMC_CLOCK_26MHZ)) - { - powerClass = ((card->extendedCsd.powerClass52MHz360V) & mask); - } - else if (card->busTiming == kMMC_HighSpeedTiming) - { - powerClass = ((card->extendedCsd.powerClass26MHz360V) & mask); - } - - break; - - case kMMC_VoltageWindow170to195: - - if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busClock_Hz <= MMC_CLOCK_26MHZ)) - { - powerClass = ((card->extendedCsd.powerClass26MHz195V) & mask); - } - else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busClock_Hz > MMC_CLOCK_26MHZ)) - { - powerClass = ((card->extendedCsd.powerClass52MHz195V) & mask); - } - else if ((card->busTiming == kMMC_HighSpeedTiming) && (card->busWidth > kMMC_DataBusWidth8bit)) - { - powerClass = ((card->extendedCsd.powerClass52MHZDDR195V) & mask); - } - - break; - default: - powerClass = 0; - break; - } - - /* due to 8bit power class position [7:4] */ - powerClass >>= shift; - - if (powerClass > 0U) - { - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexPowerClass; - extendedCsdconfig.ByteValue = powerClass; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - /* restore power class */ - card->extendedCsd.powerClass = powerClass; - } - - return kStatus_Success; -} - -static status_t MMC_SendTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern) -{ - assert(card); - assert(card->host.transfer); - assert(blockSize <= FSL_SDMMC_DEFAULT_BLOCK_SIZE); - assert(pattern); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_DATA data = {0}; - - command.index = kMMC_SendingBusTest; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1; - - /* Ignore errors in bus test procedure to improve chances that the test will work. */ - data.enableIgnoreError = true; - data.blockCount = 1U; - data.blockSize = blockSize; - data.txData = pattern; - - content.command = &command; - content.data = &data; - if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || - (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -static status_t MMC_ReceiveTestPattern(mmc_card_t *card, uint32_t blockSize, uint32_t *pattern) -{ - assert(card); - assert(card->host.transfer); - assert(blockSize <= FSL_SDMMC_DEFAULT_BLOCK_SIZE); - assert(pattern); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_DATA data = {0}; - - command.index = kMMC_BusTestRead; - command.responseType = kCARD_ResponseTypeR1; - - /* Ignore errors in bus test procedure to improve chances that the test will work. */ - data.enableIgnoreError = true; - data.blockCount = 1U; - data.blockSize = blockSize; - data.rxData = pattern; - - content.command = &command; - content.data = &data; - if ((kStatus_Success != card->host.transfer(card->host.base, &content)) || - ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -static status_t MMC_TestDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width) -{ - assert(card); - - uint32_t blockSize = 0U; - uint32_t tempsendPattern = 0U; - uint32_t *tempPattern = g_sdmmc; - uint32_t xorMask = 0U; - uint32_t xorResult = 0U; - - /* For 8 data lines the data block would be (MSB to LSB): 0x0000_0000_0000_AA55, - For 4 data lines the data block would be (MSB to LSB): 0x0000_005A, - For only 1 data line the data block would be: 0x80 */ - switch (width) - { - case kMMC_DataBusWidth8bit: - case kMMC_DataBusWidth8bitDDR: - blockSize = 8U; - tempPattern[0U] = 0xAA55U; - xorMask = 0xFFFFU; - xorResult = 0xFFFFU; - break; - case kMMC_DataBusWidth4bit: - case kMMC_DataBusWidth4bitDDR: - blockSize = 4U; - tempPattern[0U] = 0x5AU; - xorMask = 0xFFU; - xorResult = 0xFFU; - break; - default: - blockSize = 4U; - tempPattern[0U] = 0x80U; - xorMask = 0xFFU; - xorResult = 0xC0U; - break; - } - switch (card->host.config.endianMode) - { - case kSDMMCHOST_EndianModeLittle: - /* Doesn't need to switch byte sequence when decodes bytes as little endian sequence. */ - break; - case kSDMMCHOST_EndianModeBig: - /* In big endian mode, the byte transferred first is the byte stored in highest byte position in a word - which will cause the card receive the inverted byte sequence in a word in bus test procedure. So the - sequence of 4 bytes stored in a word should be converted. */ - tempPattern[0] = SWAP_WORD_BYTE_SEQUENCE(tempPattern[0]); - xorMask = SWAP_WORD_BYTE_SEQUENCE(xorMask); - xorResult = SWAP_WORD_BYTE_SEQUENCE(xorResult); - break; - case kSDMMCHOST_EndianModeHalfWordBig: - /* In half word big endian mode, the byte transferred first is the lower byte in the higher half word. - 0xAA55U should be converted to 0xAA550000U to set the 0x55 to be the first byte to transfer. */ - tempPattern[0] = SWAP_HALF_WROD_BYTE_SEQUENCE(tempPattern[0]); - xorMask = SWAP_HALF_WROD_BYTE_SEQUENCE(xorMask); - xorResult = SWAP_HALF_WROD_BYTE_SEQUENCE(xorResult); - tempPattern[0] = SWAP_WORD_BYTE_SEQUENCE(tempPattern[0]); - xorMask = SWAP_WORD_BYTE_SEQUENCE(xorMask); - xorResult = SWAP_WORD_BYTE_SEQUENCE(xorResult); - break; - default: - return kStatus_SDMMC_NotSupportYet; - } - - if (kStatus_Success != MMC_SendTestPattern(card, blockSize, tempPattern)) - { - return kStatus_SDMMC_SendTestPatternFailed; - } - /* restore the send pattern */ - tempsendPattern = tempPattern[0U]; - /* reset the global buffer */ - tempPattern[0U] = 0U; - - if (kStatus_Success != MMC_ReceiveTestPattern(card, blockSize, tempPattern)) - { - return kStatus_SDMMC_ReceiveTestPatternFailed; - } - - /* XOR the send pattern and receive pattern */ - if (((tempPattern[0U] ^ tempsendPattern) & xorMask) != xorResult) - { - return kStatus_Fail; - } - - return kStatus_Success; -} - -static status_t MMC_SetDataBusWidth(mmc_card_t *card, mmc_data_bus_width_t width) -{ - assert(card); - - mmc_extended_csd_config_t extendedCsdconfig; - - /* Set data bus width */ - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBusWidth; - extendedCsdconfig.ByteValue = width; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - /* restore data bus width */ - card->extendedCsd.dataBusWidth = width; - - return kStatus_Success; -} - -static status_t MMC_SetMaxDataBusWidth(mmc_card_t *card, mmc_high_speed_timing_t targetTiming) -{ - assert(card); - - status_t error = kStatus_Fail; - - switch (card->busWidth) - { - case kMMC_DataBusWidth1bit: - case kMMC_DataBusWidth8bitDDR: - /* Test and set the data bus width for card. */ - if ((SDMMCHOST_NOT_SUPPORT != kSDMMCHOST_Support8BitBusWidth) && - (card->flags & (kMMC_SupportHighSpeedDDR52MHZ180V300VFlag | kMMC_SupportHighSpeedDDR52MHZ120VFlag)) && - ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed400Timing))) - { - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH8BIT); - if ((kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth8bitDDR)) && - (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth8bitDDR))) - { - error = kStatus_Success; - card->busWidth = kMMC_DataBusWidth8bitDDR; - break; - } - /* HS400 mode only support 8bit data bus */ - else if (card->busTiming == kMMC_HighSpeed400Timing) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - } - case kMMC_DataBusWidth4bitDDR: - if ((SDMMCHOST_NOT_SUPPORT != kSDMMCHOST_Support4BitBusWidth) && - (card->flags & (kMMC_SupportHighSpeedDDR52MHZ180V300VFlag | kMMC_SupportHighSpeedDDR52MHZ120VFlag)) && - ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed400Timing))) - { - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH4BIT); - if ((kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth4bitDDR)) && - (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth4bitDDR))) - { - error = kStatus_Success; - card->busWidth = kMMC_DataBusWidth4bitDDR; - - break; - } - } - case kMMC_DataBusWidth8bit: - if ((SDMMCHOST_NOT_SUPPORT != kSDMMCHOST_Support8BitBusWidth) && - ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed200Timing))) - { - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH8BIT); - if ((kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth8bit)) && - (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth8bit))) - { - error = kStatus_Success; - card->busWidth = kMMC_DataBusWidth8bit; - break; - } - } - - case kMMC_DataBusWidth4bit: - if ((SDMMCHOST_NOT_SUPPORT != kSDMMCHOST_Support4BitBusWidth) && - ((targetTiming == kMMC_HighSpeedTiming) || (targetTiming == kMMC_HighSpeed200Timing))) - { - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH4BIT); - if ((kStatus_Success == MMC_TestDataBusWidth(card, kMMC_DataBusWidth4bit)) && - (kStatus_Success == MMC_SetDataBusWidth(card, kMMC_DataBusWidth4bit))) - { - error = kStatus_Success; - card->busWidth = kMMC_DataBusWidth4bit; - break; - } - /* HS200 mode only support 4bit/8bit data bus */ - else if (targetTiming == kMMC_HighSpeed200Timing) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - } - default: - break; - } - - if (error == kStatus_Fail) - { - /* Card's data bus width will be default 1 bit mode. */ - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); - } - - return kStatus_Success; -} - -static status_t MMC_SwitchHSTiming(mmc_card_t *card, uint8_t timing, uint8_t driverStrength) -{ - assert(card); - - uint8_t hsTiming = 0; - - mmc_extended_csd_config_t extendedCsdconfig; - - /* check the target driver strength support or not */ - if (((card->extendedCsd.ioDriverStrength & (1 << driverStrength)) == 0U) && - (card->extendedCsd.extendecCsdVersion >= kMMC_ExtendedCsdRevision17)) - { - return kStatus_SDMMC_NotSupportYet; - } - /* calucate the register value */ - hsTiming = (timing & 0xF) | (uint8_t)(driverStrength << 4U); - - /* Switch to high speed timing. */ - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexHighSpeedTiming; - extendedCsdconfig.ByteValue = hsTiming; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - - card->extendedCsd.highSpeedTiming = hsTiming; - - return kStatus_Success; -} - -static status_t MMC_SwitchToHighSpeed(mmc_card_t *card) -{ - assert(card); - - uint32_t freq = 0U; - - /* check VCCQ voltage supply */ - if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) - { - if ((card->hostVoltageWindowVCCQ != kMMC_VoltageWindow170to195) && - (card->extendedCsd.extendecCsdVersion > kMMC_ExtendedCsdRevision10)) - { - SDMMCHOST_SWITCH_VOLTAGE180V(card->host.base, true); - card->hostVoltageWindowVCCQ = kMMC_VoltageWindow170to195; - } - } - else if (kSDMMCHOST_SupportV120 != SDMMCHOST_NOT_SUPPORT) - { - if ((card->hostVoltageWindowVCCQ != kMMC_VoltageWindow120) && - (card->extendedCsd.extendecCsdVersion >= kMMC_ExtendedCsdRevision16)) - { - SDMMCHOST_SWITCH_VOLTAGE120V(card->host.base, true); - card->hostVoltageWindowVCCQ = kMMC_VoltageWindow120; - } - } - else - { - card->hostVoltageWindowVCCQ = kMMC_VoltageWindows270to360; - } - - if (kStatus_Success != MMC_SwitchHSTiming(card, kMMC_HighSpeedTiming, kMMC_DriverStrength0)) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - - if ((card->busWidth == kMMC_DataBusWidth4bitDDR) || (card->busWidth == kMMC_DataBusWidth8bitDDR)) - { - freq = MMC_CLOCK_DDR52; - SDMMCHOST_ENABLE_DDR_MODE(card->host.base, true, 0U); - } - else if (card->flags & kMMC_SupportHighSpeed52MHZFlag) - { - freq = MMC_CLOCK_52MHZ; - } - else if (card->flags & kMMC_SupportHighSpeed26MHZFlag) - { - freq = MMC_CLOCK_26MHZ; - } - - card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, freq); - /* config io speed and strength */ - SDMMCHOST_CONFIG_MMC_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_7); - - /* Set card data width, it is nessesary to config the the data bus here, to meet emmc5.0 specification, - * when you are working in DDR mode , HS_TIMING must set before set bus width - */ - if (MMC_SetMaxDataBusWidth(card, kMMC_HighSpeedTiming) != kStatus_Success) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - - card->busTiming = kMMC_HighSpeedTiming; - - return kStatus_Success; -} - -static status_t MMC_SwitchToHS200(mmc_card_t *card, uint32_t freq) -{ - assert(card); - - /* check VCCQ voltage supply */ - if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) - { - if (card->hostVoltageWindowVCCQ != kMMC_VoltageWindow170to195) - { - SDMMCHOST_SWITCH_VOLTAGE180V(card->host.base, true); - card->hostVoltageWindowVCCQ = kMMC_VoltageWindow170to195; - } - } - else if (kSDMMCHOST_SupportV120 != SDMMCHOST_NOT_SUPPORT) - { - if (card->hostVoltageWindowVCCQ != kMMC_VoltageWindow120) - { - SDMMCHOST_SWITCH_VOLTAGE120V(card->host.base, true); - card->hostVoltageWindowVCCQ = kMMC_VoltageWindow120; - } - } - else - { - return kStatus_SDMMC_InvalidVoltage; - } - - /* select bus width before select bus timing for HS200 mode */ - if (MMC_SetMaxDataBusWidth(card, kMMC_HighSpeed200Timing) != kStatus_Success) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - - /* switch to HS200 mode */ - if (kStatus_Success != MMC_SwitchHSTiming(card, kMMC_HighSpeed200Timing, kMMC_DriverStrength0)) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - - card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, freq); - /* config io speed and strength */ - SDMMCHOST_CONFIG_MMC_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); - - /* excute tuning for HS200 */ - if (MMC_ExecuteTuning(card) != kStatus_Success) - { - return kStatus_SDMMC_TuningFail; - } - - /* Wait for the card status ready. */ - if (kStatus_Success != MMC_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - card->busTiming = kMMC_HighSpeed200Timing; - - return kStatus_Success; -} - -static status_t MMC_SwitchToHS400(mmc_card_t *card) -{ - assert(card); - - /* check VCCQ voltage supply */ - if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) - { - if (card->hostVoltageWindowVCCQ != kMMC_VoltageWindow170to195) - { - SDMMCHOST_SWITCH_VOLTAGE180V(card->host.base, true); - card->hostVoltageWindowVCCQ = kMMC_VoltageWindow170to195; - } - } - else if (kSDMMCHOST_SupportV120 != SDMMCHOST_NOT_SUPPORT) - { - if (card->hostVoltageWindowVCCQ != kMMC_VoltageWindow120) - { - SDMMCHOST_SWITCH_VOLTAGE120V(card->host.base, true); - card->hostVoltageWindowVCCQ = kMMC_VoltageWindow120; - } - } - else - { - return kStatus_SDMMC_InvalidVoltage; - } - - /* check data bus width is 8 bit , otherwise return false */ - if (card->busWidth == kMMC_DataBusWidth8bit) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - - /* switch to high speed first */ - card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, MMC_CLOCK_52MHZ); - SDMMCHOST_CONFIG_MMC_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_5); - /*switch to high speed*/ - if (kStatus_Success != MMC_SwitchHSTiming(card, kMMC_HighSpeedTiming, kMMC_DriverStrength0)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - card->busTiming = kMMC_HighSpeed400Timing; - /* switch to 8 bit DDR data bus width */ - if (kStatus_Success != MMC_SetDataBusWidth(card, kMMC_DataBusWidth8bitDDR)) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - /* switch to HS400 */ - if (kStatus_Success != MMC_SwitchHSTiming(card, kMMC_HighSpeed400Timing, kMMC_DriverStrength0)) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - /* config to target freq */ - card->busClock_Hz = - SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMCHOST_SUPPORT_HS400_FREQ); - /* config io speed and strength */ - SDMMCHOST_CONFIG_MMC_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); - /* enable HS400 mode */ - SDMMCHOST_ENABLE_HS400_MODE(card->host.base, true); - /* enable DDR mode */ - SDMMCHOST_ENABLE_DDR_MODE(card->host.base, true, 0U); - /* config strobe DLL */ - SDMMCHOST_CONFIG_STROBE_DLL(card->host.base, SDMMCHOST_STROBE_DLL_DELAY_TARGET, - SDMMCHOST_STROBE_DLL_DELAY_UPDATE_INTERVAL); - /* enable DLL */ - SDMMCHOST_ENABLE_STROBE_DLL(card->host.base, true); - - return kStatus_Success; -} - -static status_t MMC_SelectBusTiming(mmc_card_t *card) -{ - assert(card); - - mmc_high_speed_timing_t targetTiming = card->busTiming; - - switch (targetTiming) - { - case kMMC_HighSpeedTimingNone: - case kMMC_HighSpeed400Timing: - if ((card->flags & (kMMC_SupportHS400DDR200MHZ180VFlag | kMMC_SupportHS400DDR200MHZ120VFlag)) && - ((kSDMMCHOST_SupportHS400 != SDMMCHOST_NOT_SUPPORT))) - { - /* switch to HS200 perform tuning */ - if (kStatus_Success != MMC_SwitchToHS200(card, SDMMCHOST_SUPPORT_HS400_FREQ / 2U)) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - /* switch to HS400 */ - if (kStatus_Success != MMC_SwitchToHS400(card)) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - break; - } - case kMMC_HighSpeed200Timing: - if ((card->flags & (kMMC_SupportHS200200MHZ180VFlag | kMMC_SupportHS200200MHZ120VFlag)) && - ((kSDMMCHOST_SupportHS200 != SDMMCHOST_NOT_SUPPORT))) - { - if (kStatus_Success != MMC_SwitchToHS200(card, SDMMCHOST_SUPPORT_HS200_FREQ)) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - break; - } - case kMMC_HighSpeedTiming: - if (kStatus_Success != MMC_SwitchToHighSpeed(card)) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - break; - - default: - card->busTiming = kMMC_HighSpeedTimingNone; - } - - return kStatus_Success; -} - -static void MMC_DecodeCid(mmc_card_t *card, uint32_t *rawCid) -{ - assert(card); - assert(rawCid); - - mmc_cid_t *cid; - - cid = &(card->cid); - cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF000000U) >> 24U); - cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFF00U) >> 8U); - - cid->productName[0U] = (uint8_t)((rawCid[3U] & 0xFFU)); - cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); - cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); - cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); - cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFFU)); - - cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24U); - - cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFFFU) << 8U); - cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFF000000U) >> 24U); - - cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFF00U) >> 8U); -} - -static status_t MMC_AllSendCid(mmc_card_t *card) -{ - assert(card); - assert(card->host.transfer); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - - command.index = kSDMMC_AllSendCid; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR2; - - content.command = &command; - content.data = NULL; - if (kStatus_Success == card->host.transfer(card->host.base, &content)) - { - memcpy(card->rawCid, command.response, sizeof(card->rawCid)); - MMC_DecodeCid(card, command.response); - - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static status_t MMC_SendCsd(mmc_card_t *card) -{ - assert(card); - assert(card->host.transfer); - - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_TRANSFER content = {0}; - - command.index = kSDMMC_SendCsd; - command.argument = (card->relativeAddress << 16U); - command.responseType = kCARD_ResponseTypeR2; - - content.command = &command; - content.data = 0U; - if (kStatus_Success == card->host.transfer(card->host.base, &content)) - { - memcpy(card->rawCsd, command.response, sizeof(card->rawCsd)); - /* The response is from bit 127:8 in R2, corresponding to command.response[3][31:0] to - command.response[0U][31:8]. */ - MMC_DecodeCsd(card, card->rawCsd); - - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static status_t MMC_CheckBlockRange(mmc_card_t *card, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(blockCount); - - status_t error = kStatus_Success; - uint32_t partitionBlocks; - - switch (card->currentPartition) - { - case kMMC_AccessPartitionUserAera: - { - partitionBlocks = card->userPartitionBlocks; - break; - } - case kMMC_AccessPartitionBoot1: - case kMMC_AccessPartitionBoot2: - { - /* Boot partition 1 and partition 2 have the same partition size. */ - partitionBlocks = card->bootPartitionBlocks; - break; - } - default: - error = kStatus_InvalidArgument; - break; - } - /* Check if the block range accessed is within current partition's block boundary. */ - if ((error == kStatus_Success) && ((startBlock + blockCount) > partitionBlocks)) - { - error = kStatus_InvalidArgument; - } - - return error; -} - -static status_t MMC_CheckEraseGroupRange(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup) -{ - assert(card); - - status_t error = kStatus_Success; - uint32_t partitionBlocks; - uint32_t eraseGroupBoundary; - - switch (card->currentPartition) - { - case kMMC_AccessPartitionUserAera: - { - partitionBlocks = card->userPartitionBlocks; - break; - } - case kMMC_AccessPartitionBoot1: - case kMMC_AccessPartitionBoot2: - { - /* Boot partition 1 and partition 2 have the same partition size. */ - partitionBlocks = card->bootPartitionBlocks; - break; - } - default: - error = kStatus_InvalidArgument; - break; - } - - if (error == kStatus_Success) - { - /* Check if current partition's total block count is integer multiples of the erase group size. */ - if ((partitionBlocks % card->eraseGroupBlocks) == 0U) - { - eraseGroupBoundary = (partitionBlocks / card->eraseGroupBlocks); - } - else - { - /* Card will ignore the unavailable blocks within the last erase group automatically. */ - eraseGroupBoundary = (partitionBlocks / card->eraseGroupBlocks + 1U); - } - - /* Check if the group range accessed is within current partition's erase group boundary. */ - if ((startGroup > eraseGroupBoundary) || (endGroup > eraseGroupBoundary)) - { - error = kStatus_InvalidArgument; - } - } - - return error; -} - -static status_t MMC_Read( - mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) -{ - assert(card); - assert(card->host.transfer); - assert(buffer); - assert(blockCount); - assert(blockSize); - assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); - - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_DATA data = {0}; - SDMMCHOST_TRANSFER content = {0}; - status_t error; - - if (((card->flags & kMMC_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || - (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4U)) - { - return kStatus_SDMMC_CardNotSupport; - } - - /* Wait for the card write process complete because of that card read process and write process use one buffer. */ - if (kStatus_Success != MMC_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - data.blockSize = blockSize; - data.blockCount = blockCount; - data.rxData = (uint32_t *)buffer; - data.enableAutoCommand12 = true; - command.index = kSDMMC_ReadMultipleBlock; - if (data.blockCount == 1U) - { - command.index = kSDMMC_ReadSingleBlock; - } - else - { - if ((!(data.enableAutoCommand12)) && (card->enablePreDefinedBlockCount)) - { - /* If enabled the pre-define count read/write feature of the card, need to set block count firstly. */ - if (kStatus_Success != MMC_SetBlockCount(card, blockCount)) - { - return kStatus_SDMMC_SetBlockCountFailed; - } - } - } - command.argument = startBlock; - if (!(card->flags & kMMC_SupportHighCapacityFlag)) - { - command.argument *= data.blockSize; - } - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; - - content.command = &command; - content.data = &data; - - /* should check tuning error during every transfer */ - error = MMC_Transfer(card, &content, 1U); - if (kStatus_Success != error) - { - return error; - } - - /* When host's AUTO_COMMAND12 feature isn't enabled and PRE_DEFINED_COUNT command isn't enabled in multiple - blocks transmission, sends STOP_TRANSMISSION command. */ - if ((blockCount > 1U) && (!(data.enableAutoCommand12)) && (!card->enablePreDefinedBlockCount)) - { - if (kStatus_Success != MMC_StopTransmission(card)) - { - return kStatus_SDMMC_StopTransmissionFailed; - } - } - - return kStatus_Success; -} - -static status_t MMC_Write( - mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) -{ - assert(card); - assert(card->host.transfer); - assert(buffer); - assert(blockCount); - assert(blockSize); - assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); - - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_DATA data = {0}; - SDMMCHOST_TRANSFER content = {0}; - status_t error; - - /* Check address range */ - if (((card->flags & kMMC_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || - (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4U)) - { - return kStatus_SDMMC_CardNotSupport; - } - - /* Wait for the card's buffer to be not full to write to improve the write performance. */ - while ((GET_SDMMCHOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) - { - } - - /* Wait for the card write process complete */ - if (kStatus_Success != MMC_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - data.blockSize = blockSize; - data.blockCount = blockCount; - data.txData = (const uint32_t *)buffer; - data.enableAutoCommand12 = true; - - command.index = kSDMMC_WriteMultipleBlock; - if (data.blockCount == 1U) - { - command.index = kSDMMC_WriteSingleBlock; - } - else - { - if ((!(data.enableAutoCommand12)) && (card->enablePreDefinedBlockCount)) - { - /* If enabled the pre-define count read/write featue of the card, need to set block count firstly */ - if (kStatus_Success != MMC_SetBlockCount(card, blockCount)) - { - return kStatus_SDMMC_SetBlockCountFailed; - } - } - } - command.argument = startBlock; - if (!(card->flags & kMMC_SupportHighCapacityFlag)) - { - command.argument *= blockSize; - } - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; - - content.command = &command; - content.data = &data; - - /* should check tuning error during every transfer */ - error = MMC_Transfer(card, &content, 1U); - if (kStatus_Success != error) - { - return error; - } - - /* When host's AUTO_COMMAND12 feature isn't enabled and PRE_DEFINED_COUNT command isn't enabled in multiple - blocks transmission, sends STOP_TRANSMISSION command. */ - if ((blockCount > 1U) && (!(data.enableAutoCommand12)) && (!card->enablePreDefinedBlockCount)) - { - if (kStatus_Success != MMC_StopTransmission(card)) - { - return kStatus_SDMMC_StopTransmissionFailed; - } - } - - return kStatus_Success; -} - -status_t MMC_CardInit(mmc_card_t *card) -{ - assert(card); - assert((card->hostVoltageWindowVCC != kMMC_VoltageWindowNone) && - (card->hostVoltageWindowVCC != kMMC_VoltageWindow120)); - - uint32_t opcode = 0U; - - if (!card->isHostReady) - { - return kStatus_SDMMC_HostNotReady; - } - /* set DATA bus width */ - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); - /* Set clock to 400KHz. */ - card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); - /* get host capability first */ - GET_SDMMCHOST_CAPABILITY(card->host.base, &(card->host.capability)); - - /* Send CMD0 to reset the bus */ - if (kStatus_Success != MMC_GoIdle(card)) - { - return kStatus_SDMMC_GoIdleFailed; - } - - /* Hand-shaking with card to validata the voltage range Host first sending its expected - information.*/ - if (kStatus_Success != MMC_SendOperationCondition(card, 0U)) - { - return kStatus_SDMMC_HandShakeOperationConditionFailed; - } - - /* switch the host voltage which the card can support */ - if (kStatus_Success != MMC_SwitchVoltage(card, &opcode)) - { - return kStatus_SDMMC_HandShakeOperationConditionFailed; - } - - /* Get host's access mode. */ - if (card->host.capability.maxBlockLength >= FSL_SDMMC_DEFAULT_BLOCK_SIZE) - { - opcode |= kMMC_AccessModeSector << MMC_OCR_ACCESS_MODE_SHIFT; - } - else - { - opcode |= kMMC_AccessModeByte << MMC_OCR_ACCESS_MODE_SHIFT; - } - - if (kStatus_Success != MMC_SendOperationCondition(card, opcode)) - { - return kStatus_SDMMC_HandShakeOperationConditionFailed; - } - - /* Get card CID */ - if (kStatus_Success != MMC_AllSendCid(card)) - { - return kStatus_SDMMC_AllSendCidFailed; - } - - /* Set the card relative address */ - if (kStatus_Success != MMC_SetRelativeAddress(card)) - { - return kStatus_SDMMC_SetRelativeAddressFailed; - } - - /* Get the CSD register content */ - if (kStatus_Success != MMC_SendCsd(card)) - { - return kStatus_SDMMC_SendCsdFailed; - } - - /* Set to maximum speed in normal mode. */ - MMC_SetMaxFrequency(card); - - /* Send CMD7 with the card's relative address to place the card in transfer state. Puts current selected card in - transfer state. */ - if (kStatus_Success != MMC_SelectCard(card, true)) - { - return kStatus_SDMMC_SelectCardFailed; - } - - /* Get Extended CSD register content. */ - if (kStatus_Success != MMC_SendExtendedCsd(card, NULL, 0U)) - { - return kStatus_SDMMC_SendExtendedCsdFailed; - } - - /* set block size */ - if (kStatus_Success != MMC_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) - { - return kStatus_SDMMC_SetCardBlockSizeFailed; - } - - /* switch to host support speed mode, then switch MMC data bus width and select power class */ - if (kStatus_Success != MMC_SelectBusTiming(card)) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - - /* switch power class */ - if (kStatus_Success != MMC_SetPowerClass(card)) - { - return kStatus_SDMMC_SetPowerClassFail; - } - - /* Set to max erase unit size */ - if (kStatus_Success != MMC_SetMaxEraseUnitSize(card)) - { - return kStatus_SDMMC_EnableHighCapacityEraseFailed; - } - - /* Set card default to access non-boot partition */ - card->currentPartition = kMMC_AccessPartitionUserAera; - - return kStatus_Success; -} - -void MMC_CardDeinit(mmc_card_t *card) -{ - assert(card); - - MMC_SelectCard(card, false); -} - -status_t MMC_HostInit(mmc_card_t *card) -{ - assert(card); - - if ((!card->isHostReady) && SDMMCHOST_Init(&(card->host), NULL) != kStatus_Success) - { - return kStatus_Fail; - } - - /* set the host status flag, after the card re-plug in, don't need init host again */ - card->isHostReady = true; - - return kStatus_Success; -} - -void MMC_HostDeinit(mmc_card_t *card) -{ - assert(card); - - SDMMCHOST_Deinit(&(card->host)); - /* should re-init host */ - card->isHostReady = false; -} - -void MMC_HostReset(SDMMCHOST_CONFIG *host) -{ - SDMMCHOST_Reset(host->base); -} - -void MMC_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - SDMMCHOST_PowerOnCard(base, pwr); -} - -void MMC_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - SDMMCHOST_PowerOffCard(base, pwr); -} - -status_t MMC_Init(mmc_card_t *card) -{ - assert(card); - - if (!card->isHostReady) - { - if (MMC_HostInit(card) != kStatus_Success) - { - return kStatus_SDMMC_HostNotReady; - } - } - else - { - /* reset the host */ - MMC_HostReset(&(card->host)); - } - - /*first power off card*/ - MMC_PowerOffCard(card->host.base, card->usrParam.pwr); - - /*power on card*/ - MMC_PowerOnCard(card->host.base, card->usrParam.pwr); - - return MMC_CardInit(card); -} - -void MMC_Deinit(mmc_card_t *card) -{ - assert(card); - - MMC_CardDeinit(card); - MMC_HostDeinit(card); -} - -bool MMC_CheckReadOnly(mmc_card_t *card) -{ - assert(card); - - return ((card->csd.flags & kMMC_CsdPermanentWriteProtectFlag) || - (card->csd.flags & kMMC_CsdTemporaryWriteProtectFlag)); -} - -status_t MMC_SelectPartition(mmc_card_t *card, mmc_access_partition_t partitionNumber) -{ - assert(card); - - uint8_t bootConfig; - mmc_extended_csd_config_t extendedCsdconfig; - - bootConfig = card->extendedCsd.partitionConfig; - bootConfig &= ~MMC_PARTITION_CONFIG_PARTITION_ACCESS_MASK; - bootConfig |= ((uint32_t)partitionNumber << MMC_PARTITION_CONFIG_PARTITION_ACCESS_SHIFT); - - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexPartitionConfig; - extendedCsdconfig.ByteValue = bootConfig; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - - /* Save current configuration. */ - card->extendedCsd.partitionConfig = bootConfig; - card->currentPartition = partitionNumber; - - return kStatus_Success; -} - -status_t MMC_ReadBlocks(mmc_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(buffer); - assert(blockCount); - - uint32_t blockCountOneTime; /* The block count can be erased in one time sending READ_BLOCKS command. */ - uint32_t blockDone; /* The blocks has been read. */ - uint32_t blockLeft; /* Left blocks to be read. */ - uint8_t *nextBuffer; - bool dataAddrAlign = true; - - blockLeft = blockCount; - blockDone = 0U; - if (kStatus_Success != MMC_CheckBlockRange(card, startBlock, blockCount)) - { - return kStatus_InvalidArgument; - } - - while (blockLeft) - { - nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - if (!card->noInteralAlign && (!dataAddrAlign || (((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U)))) - { - blockLeft--; - blockCountOneTime = 1U; - memset(g_sdmmc, 0U, FSL_SDMMC_DEFAULT_BLOCK_SIZE); - dataAddrAlign = false; - } - else - { - if (blockLeft > card->host.capability.maxBlockCount) - { - blockLeft = (blockLeft - card->host.capability.maxBlockCount); - blockCountOneTime = card->host.capability.maxBlockCount; - } - else - { - blockCountOneTime = blockLeft; - blockLeft = 0U; - } - } - - if (kStatus_Success != MMC_Read(card, dataAddrAlign ? nextBuffer : (uint8_t *)g_sdmmc, (startBlock + blockDone), - FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime)) - { - return kStatus_SDMMC_TransferFailed; - } - - blockDone += blockCountOneTime; - - if (!card->noInteralAlign && (!dataAddrAlign)) - { - memcpy(nextBuffer, (uint8_t *)&g_sdmmc, FSL_SDMMC_DEFAULT_BLOCK_SIZE); - } - } - - return kStatus_Success; -} - -status_t MMC_WriteBlocks(mmc_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(buffer); - assert(blockCount); - - uint32_t blockCountOneTime; - uint32_t blockLeft; - uint32_t blockDone; - const uint8_t *nextBuffer; - bool dataAddrAlign = true; - - blockLeft = blockCount; - blockDone = 0U; - - if (kStatus_Success != MMC_CheckBlockRange(card, startBlock, blockCount)) - { - return kStatus_InvalidArgument; - } - - while (blockLeft) - { - nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - if (!card->noInteralAlign && (!dataAddrAlign || (((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U)))) - { - blockLeft--; - blockCountOneTime = 1U; - memcpy((uint8_t *)&g_sdmmc, nextBuffer, FSL_SDMMC_DEFAULT_BLOCK_SIZE); - dataAddrAlign = false; - } - else - { - if (blockLeft > card->host.capability.maxBlockCount) - { - blockLeft = (blockLeft - card->host.capability.maxBlockCount); - blockCountOneTime = card->host.capability.maxBlockCount; - } - else - { - blockCountOneTime = blockLeft; - blockLeft = 0U; - } - } - - if (kStatus_Success != MMC_Write(card, dataAddrAlign ? nextBuffer : (uint8_t *)g_sdmmc, - (startBlock + blockDone), FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime)) - { - return kStatus_SDMMC_TransferFailed; - } - - blockDone += blockCountOneTime; - if (!card->noInteralAlign) - { - memset(g_sdmmc, 0U, FSL_SDMMC_DEFAULT_BLOCK_SIZE); - } - } - - return kStatus_Success; -} - -status_t MMC_EraseGroups(mmc_card_t *card, uint32_t startGroup, uint32_t endGroup) -{ - assert(card); - assert(card->host.transfer); - - uint32_t startGroupAddress; - uint32_t endGroupAddress; - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_TRANSFER content = {0}; - - if (kStatus_Success != MMC_CheckEraseGroupRange(card, startGroup, endGroup)) - { - return kStatus_InvalidArgument; - } - - /* Wait for the card's buffer to be not full to write to improve the write performance. */ - while ((GET_SDMMCHOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) - { - } - - if (kStatus_Success != MMC_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - /* Calculate the start group address and end group address */ - startGroupAddress = startGroup; - endGroupAddress = endGroup; - if (card->flags & kMMC_SupportHighCapacityFlag) - { - /* The implementation of a higher than 2GB of density of memory will not be backwards compatible with the - lower densities.First of all the address argument for higher than 2GB of density of memory is changed to - be sector address (512B sectors) instead of byte address */ - startGroupAddress = (startGroupAddress * (card->eraseGroupBlocks)); - endGroupAddress = (endGroupAddress * (card->eraseGroupBlocks)); - } - else - { - /* The address unit is byte when card capacity is lower than 2GB */ - startGroupAddress = (startGroupAddress * (card->eraseGroupBlocks) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - endGroupAddress = (endGroupAddress * (card->eraseGroupBlocks) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - } - - /* Set the start erase group address */ - command.index = kMMC_EraseGroupStart; - command.argument = startGroupAddress; - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; - - content.command = &command; - content.data = NULL; - if (kStatus_Success != MMC_Transfer(card, &content, 0U)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Set the end erase group address */ - command.index = kMMC_EraseGroupEnd; - command.argument = endGroupAddress; - - content.command = &command; - content.data = NULL; - if (kStatus_Success != MMC_Transfer(card, &content, 0U)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Start the erase process */ - command.index = kSDMMC_Erase; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1b; - command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; - - content.command = &command; - content.data = NULL; - if (kStatus_Success != MMC_Transfer(card, &content, 0U)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t MMC_SetBootConfigWP(mmc_card_t *card, uint8_t wp) -{ - assert(card); - - mmc_extended_csd_config_t extendedCsdconfig; - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBootConfigWP; - extendedCsdconfig.ByteValue = wp; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - - card->extendedCsd.bootConfigProtect = wp; - - return kStatus_Success; -} - -status_t MMC_SetBootPartitionWP(mmc_card_t *card, mmc_boot_partition_wp_t bootPartitionWP) -{ - assert(card); - - mmc_extended_csd_config_t extendedCsdconfig; - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBootPartitionWP; - extendedCsdconfig.ByteValue = bootPartitionWP; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - - card->extendedCsd.bootPartitionWP = bootPartitionWP; - - return kStatus_Success; -} - -status_t MMC_SetBootConfig(mmc_card_t *card, const mmc_boot_config_t *config) -{ - assert(card); - assert(config); - - uint8_t bootParameter; - uint8_t bootBusWidth = config->bootDataBusWidth; - mmc_extended_csd_config_t extendedCsdconfig; - - if (card->extendedCsd.extendecCsdVersion <= - kMMC_ExtendedCsdRevision13) /* V4.3 or above version card support boot mode */ - { - return kStatus_SDMMC_NotSupportYet; - } - - /* Set the BOOT_CONFIG field of Extended CSD */ - bootParameter = card->extendedCsd.partitionConfig; - bootParameter &= ~(MMC_PARTITION_CONFIG_BOOT_ACK_MASK | MMC_PARTITION_CONFIG_PARTITION_ENABLE_MASK); - bootParameter |= ((config->enableBootAck ? 1U : 0U) << MMC_PARTITION_CONFIG_BOOT_ACK_SHIFT); - bootParameter |= ((uint32_t)(config->bootPartition) << MMC_PARTITION_CONFIG_PARTITION_ENABLE_SHIFT); - - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexPartitionConfig; - extendedCsdconfig.ByteValue = bootParameter; - extendedCsdconfig.commandSet = kMMC_CommandSetStandard; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureExtendedCsdFailed; - } - - card->extendedCsd.partitionConfig = bootParameter; - - /* data bus remapping */ - if (bootBusWidth == kMMC_DataBusWidth1bit) - { - bootBusWidth = 0U; - } - else if ((bootBusWidth == kMMC_DataBusWidth4bit) || (bootBusWidth == kMMC_DataBusWidth4bitDDR)) - { - bootBusWidth = 1U; - } - else - { - bootBusWidth = 2U; - } - - /*Set BOOT_BUS_CONDITIONS in Extended CSD */ - bootParameter = card->extendedCsd.bootDataBusConditions; - bootParameter &= ~(MMC_BOOT_BUS_CONDITION_RESET_BUS_CONDITION_MASK | MMC_BOOT_BUS_CONDITION_BUS_WIDTH_MASK | - MMC_BOOT_BUS_CONDITION_BOOT_MODE_MASK); - bootParameter |= - ((config->retainBootbusCondition ? true : false) << MMC_BOOT_BUS_CONDITION_RESET_BUS_CONDITION_SHIFT); - bootParameter |= bootBusWidth << MMC_BOOT_BUS_CONDITION_BUS_WIDTH_SHIFT; - bootParameter |= (uint32_t)(config->bootTimingMode); - - extendedCsdconfig.accessMode = kMMC_ExtendedCsdAccessModeWriteBits; - extendedCsdconfig.ByteIndex = kMMC_ExtendedCsdIndexBootBusConditions; - extendedCsdconfig.ByteValue = bootParameter; - if (kStatus_Success != MMC_SetExtendedCsdConfig(card, &extendedCsdconfig)) - { - return kStatus_SDMMC_ConfigureBootFailed; - } - - card->extendedCsd.bootDataBusConditions = bootParameter; - /* check and configure the boot config write protect */ - bootParameter = config->pwrBootConfigProtection | ((uint8_t)(config->premBootConfigProtection) << 4U); - if (bootParameter != (card->extendedCsd.bootConfigProtect)) - { - if (kStatus_Success != MMC_SetBootConfigWP(card, bootParameter)) - { - return kStatus_SDMMC_ConfigureBootFailed; - } - } - /* check and configure the boot partition write protect */ - if (card->extendedCsd.bootPartitionWP != (uint8_t)(config->bootPartitionWP)) - { - if (kStatus_Success != MMC_SetBootPartitionWP(card, config->bootPartitionWP)) - { - return kStatus_SDMMC_ConfigureBootFailed; - } - } - - return kStatus_Success; -} - -status_t MMC_StartBoot(mmc_card_t *card, - const mmc_boot_config_t *mmcConfig, - uint8_t *buffer, - SDMMCHOST_BOOT_CONFIG *hostConfig) -{ - assert(card); - assert(mmcConfig); - assert(buffer); - - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_DATA data = {0}; - uint32_t tempClock = 0U; - - if (!card->isHostReady) - { - return kStatus_Fail; - } - - /* send card active */ - SDMMCHOST_SEND_CARD_ACTIVE(card->host.base, 100U); - /* config the host */ - SDMMCHOST_SETMMCBOOTCONFIG(card->host.base, hostConfig); - /* enable MMC boot */ - SDMMCHOST_ENABLE_MMC_BOOT(card->host.base, true); - - if (mmcConfig->bootTimingMode == kMMC_BootModeSDRWithDefaultTiming) - { - /* Set clock to 400KHz. */ - tempClock = SDMMC_CLOCK_400KHZ; - } - else - { - /* Set clock to 52MHZ. */ - tempClock = MMC_CLOCK_52MHZ; - } - SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, tempClock); - - if (mmcConfig->bootTimingMode == kMMC_BootModeDDRTiming) - { - /* enable DDR mode */ - SDMMCHOST_ENABLE_DDR_MODE(card->host.base, true, 0U); - } - - /* data bus remapping */ - if (mmcConfig->bootDataBusWidth == kMMC_DataBusWidth1bit) - { - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); - } - else if ((mmcConfig->bootDataBusWidth == kMMC_DataBusWidth4bit) || - (mmcConfig->bootDataBusWidth == kMMC_DataBusWidth4bitDDR)) - { - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH4BIT); - } - else - { - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH8BIT); - } - - if (kMMC_BootModeAlternative == (uint32_t)SDMMCHOST_GET_HOST_CONFIG_BOOT_MODE(hostConfig)) - { - /* alternative boot mode */ - command.argument = 0xFFFFFFFA; - } - - command.index = kSDMMC_GoIdleState; - - data.blockSize = SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(hostConfig); - data.blockCount = SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(hostConfig); - data.rxData = (uint32_t *)buffer; - SDMMCHOST_ENABLE_BOOT_FLAG(data); - - content.data = &data; - content.command = &command; - - /* should check tuning error during every transfer*/ - if (kStatus_Success != MMC_Transfer(card, &content, 1U)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t MMC_ReadBootData(mmc_card_t *card, uint8_t *buffer, SDMMCHOST_BOOT_CONFIG *hostConfig) -{ - assert(card); - assert(buffer); - - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_DATA data = {0}; - - /* enable MMC boot */ - SDMMCHOST_ENABLE_MMC_BOOT(card->host.base, true); - /* config the host */ - SDMMCHOST_SETMMCBOOTCONFIG(card->host.base, hostConfig); - data.blockSize = SDMMCHOST_GET_HOST_CONFIG_BLOCK_SIZE(hostConfig); - data.blockCount = SDMMCHOST_GET_HOST_CONFIG_BLOCK_COUNT(hostConfig); - data.rxData = (uint32_t *)buffer; - SDMMCHOST_ENABLE_BOOT_CONTINOUS_FLAG(data); - /* no command should be send out */ - SDMMCHOST_EMPTY_CMD_FLAG(command); - - content.data = &data; - content.command = &command; - - /* should check tuning error during every transfer*/ - if (kStatus_Success != MMC_Transfer(card, &content, 1U)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t MMC_StopBoot(mmc_card_t *card, uint32_t bootMode) -{ - assert(card); - /* Disable boot mode */ - if (kMMC_BootModeAlternative == bootMode) - { - /* Send CMD0 to reset the bus */ - if (kStatus_Success != MMC_GoIdle(card)) - { - return kStatus_SDMMC_GoIdleFailed; - } - } - /* disable MMC boot */ - SDMMCHOST_ENABLE_MMC_BOOT(card->host.base, false); - - return kStatus_Success; -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sd.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sd.c deleted file mode 100644 index 6e3599d322..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sd.c +++ /dev/null @@ -1,1982 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ -#include "fsl_sd.h" - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief Wait write process complete. - * - * @param card Card descriptor. - * @retval kStatus_Timeout Send command timeout. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_WaitWriteComplete(sd_card_t *card); - -/*! - * @brief send write success blocks. - * - * @param card Card descriptor. - * @param blocks blocks number wirte successed - * @retval kStatus_SDMMC_TransferFailed Send command failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SendWriteSuccessBlocks(sd_card_t *card, uint32_t *blocks); - -/*! - * @brief Send SEND_APPLICATION_COMMAND command. - * - * @param card Card descriptor. - * @param relativeaddress - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress); - -/*! - * @brief Send GO_IDLE command to set the card to be idle state. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline SD_GoIdle(sd_card_t *card); - -/*! - * @brief Send STOP_TRANSMISSION command after multiple blocks read/write. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_StopTransmission(sd_card_t *card); - -/*! - * @brief Send SET_BLOCK_SIZE command. - * - * @param card Card descriptor. - * @param blockSize Block size. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t inline SD_SetBlockSize(sd_card_t *card, uint32_t blockSize); - -/*! - * @brief Send GET_RCA command to get card relative address. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SendRca(sd_card_t *card); - -/*! - * @brief Send SWITCH_FUNCTION command to switch the card function group. - * - * @param card Card descriptor. - * @param mode 0 to check function group. 1 to switch function group - * @param group Function group - * @param number Function number in the function group. - * @param status Switch function status. - * @retval kStatus_SDMMC_SetCardBlockSizeFailed Set card block size failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status); - -/*! - * @brief Decode raw SCR register content in the data blocks. - * - * @param card Card descriptor. - * @param rawScr Raw SCR register content. - */ -static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr); - -/*! - * @brief Send GET_SCR command. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_NotSupportYet Not support yet. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SendScr(sd_card_t *card); - -/*! - * @brief Switch the card to be high speed mode. - * - * @param card Card descriptor. - * @param group Group number. - * @param functio Function number. - * @retval kStatus_SDMMC_CardNotSupport Card not support. - * @retval kStatus_SDMMC_SwitchFailed Switch failed. - * @retval kStatus_SDMMC_NotSupportYet Not support yet. - * @retval kStatus_Fail Switch failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function); - -/*! - * @brief Send SET_DATA_WIDTH command to set SD bus width. - * - * @param card Card descriptor. - * @param width Data bus width. - * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. - * @retval kStatus_InvalidArgument Invalid argument. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SetDataBusWidth(sd_card_t *card, sd_data_bus_width_t width); - -/*! - * @brief Decode raw CSD register content in the data blocks. - * - * @param card Card descriptor. - * @param rawCsd Raw CSD register content. - */ -static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd); - -/*! - * @brief Send SEND_CSD command to get CSD register content from Card. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SendCsd(sd_card_t *card); - -/*! - * @brief Decode raw CID register content in the data blocks. - * - * @param rawCid raw CID register content. - * @param card Card descriptor. - */ -static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid); - -/*! - * @brief Send GET_CID command to get CID from card. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_AllSendCid(sd_card_t *card); - -/*! - * @brief Send SEND_OPERATION_CONDITION command. - * - * This function sends host capacity support information and asks the accessed card to send its operating condition - * register content. - * - * @param card Card descriptor. - * @param argument The argument of the send operation condition ncomamnd. - * @retval kStatus_SDMMC_SendApplicationCommandFailed Send application command failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Timeout Timeout. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument); - -/*! - * @brief Send GET_INTERFACE_CONDITION command to get card interface condition. - * - * This function checks card interface condition, which includes host supply voltage information and asks the card - * whether card supports the specified host voltage. - * - * @param card Card descriptor. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_SendInterfaceCondition(sd_card_t *card); - -/*! - * @brief Send switch voltage command - * switch card voltage to 1.8v - * - * @param card Card descriptor. - */ -static status_t SD_SwitchVoltage(sd_card_t *card); - -/*! - * @brief select bus timing - * select card timing - * @param card Card descriptor. - */ -static status_t SD_SelectBusTiming(sd_card_t *card); - -/*! - * @brief Decode sd 512 bit status - * @param card Card descriptor. - * @param 512 bits satus raw data. - */ -static void SD_DecodeStatus(sd_card_t *card, uint32_t *src); - -/*! - * @brief Read data from specific SD card. - * - * @param card Card descriptor. - * @param buffer Buffer to save data blocks read. - * @param startBlock Card start block number to be read. - * @param blockSize Block size. - * @param blockCount Block count. - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_SDMMC_WaitWriteCompleteFailed Wait write complete failed. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount); - -/*! - * @brief Write data to specific card - * - * @param card Card descriptor. - * @param buffer Buffer to be sent. - * @param startBlock Card start block number to be written. - * @param blockSize Block size. - * @param blockCount Block count. - * @param blockWritten successfully write blocks - * @retval kStatus_SDMMC_CardNotSupport Card doesn't support. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_SDMMC_StopTransmissionFailed Stop transmission failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_Write(sd_card_t *card, - const uint8_t *buffer, - uint32_t startBlock, - uint32_t blockSize, - uint32_t blockCount, - uint32_t *blockWritten); - -/*! - * @brief Erase data for the given block range. - * - * @param card Card descriptor. - * @param startBlock Card start block number to be erased. - * @param blockCount The block count to be erased. - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - */ -static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount); - -/*! - * @brief card transfer function. - * - * @param card Card descriptor. - * @param content Transfer content. - * @param retry Retry times - * @retval kStatus_SDMMC_TransferFailed Transfer failed. - * @retval kStatus_Success Operate successfully. - * @retval kStatus_SDMMC_TuningFail tuning fail - */ -static status_t SD_Transfer(sd_card_t *card, SDMMCHOST_TRANSFER *content, uint32_t retry); - -/*! - * @brief card execute tuning function. - * - * @param card Card descriptor. - * @retval kStatus_Success Operate successfully. - * @retval kStatus_SDMMC_TuningFail tuning fail. - * @retval kStatus_SDMMC_TransferFailed transfer fail - */ -static status_t inline SD_ExecuteTuning(sd_card_t *card); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* g_sdmmc statement */ -extern uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)]; -static uint32_t s_sdAuSizeMap[] = {0, - 16 * 1024, - 32 * 1024, - 64 * 1024, - 128 * 1024, - 256 * 1024, - 512 * 1024, - 1024 * 1024, - 2 * 1024 * 1024, - 4 * 1024 * 1024, - 8 * 1024 * 1024, - 12 * 1024 * 1024, - 16 * 1024 * 1024, - 24 * 1024 * 1024, - 32 * 1024 * 1024, - 64 * 1024 * 1024}; -/******************************************************************************* - * Code - ******************************************************************************/ -static status_t inline SD_SendApplicationCmd(sd_card_t *card, uint32_t relativeAddress) -{ - assert(card); - - return SDMMC_SendApplicationCommand(card->host.base, card->host.transfer, relativeAddress); -} - -static status_t inline SD_GoIdle(sd_card_t *card) -{ - assert(card); - - return SDMMC_GoIdle(card->host.base, card->host.transfer); -} - -static status_t inline SD_SetBlockSize(sd_card_t *card, uint32_t blockSize) -{ - assert(card); - - return SDMMC_SetBlockSize(card->host.base, card->host.transfer, blockSize); -} - -static status_t inline SD_ExecuteTuning(sd_card_t *card) -{ - assert(card); - - return SDMMC_ExecuteTuning(card->host.base, card->host.transfer, kSD_SendTuningBlock, 64U); -} - -static status_t SD_SwitchVoltage(sd_card_t *card) -{ - assert(card); - - if ((card->usrParam.cardVoltage != NULL) && (card->usrParam.cardVoltage->cardSignalLine1V8 != NULL)) - { - return SDMMC_SwitchToVoltage(card->host.base, card->host.transfer, - card->usrParam.cardVoltage->cardSignalLine1V8); - } - - return SDMMC_SwitchToVoltage(card->host.base, card->host.transfer, NULL); -} - -static status_t SD_StopTransmission(sd_card_t *card) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - status_t error = kStatus_Success; - - command.index = kSDMMC_StopTransmission; - command.argument = 0U; - command.type = kCARD_CommandTypeAbort; - command.responseType = kCARD_ResponseTypeR1b; - command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; - - content.command = &command; - content.data = 0U; - error = card->host.transfer(card->host.base, &content); - if (kStatus_Success != error) - { - SDMMC_LOG("\r\nError: send CMD12 failed with host error %d, reponse %x\r\n", error, command.response[0U]); - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -static status_t SD_Transfer(sd_card_t *card, SDMMCHOST_TRANSFER *content, uint32_t retry) -{ - assert(card->host.transfer); - assert(content); - status_t error; - - do - { - error = card->host.transfer(card->host.base, content); -#if SDMMC_ENABLE_SOFTWARE_TUNING - if (((error == SDMMCHOST_RETUNING_REQUEST) || (error == SDMMCHOST_TUNING_ERROR)) && - (card->currentTiming == kSD_TimingSDR104Mode)) - { - /* tuning error need reset tuning circuit */ - if (error == SDMMCHOST_TUNING_ERROR) - { - SDMMCHOST_RESET_TUNING(card->host.base, 100U); - } - - /* execute re-tuning */ - if (SD_ExecuteTuning(card) != kStatus_Success) - { - error = kStatus_SDMMC_TuningFail; - break; - } - else - { - continue; - } - } - else -#endif - if (error != kStatus_Success) - { - /* if transfer data failed, send cmd12 to abort current transfer */ - if (content->data) - { - SD_StopTransmission(card); - } - } - - if (retry != 0U) - { - retry--; - } - else - { - break; - } - - } while (error != kStatus_Success); - - return error; -} - -static status_t SD_WaitWriteComplete(sd_card_t *card) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - status_t error = kStatus_Success; - - command.index = kSDMMC_SendStatus; - command.argument = card->relativeAddress << 16U; - command.responseType = kCARD_ResponseTypeR1; - - do - { - content.command = &command; - content.data = 0U; - error = SD_Transfer(card, &content, 2U); - if (kStatus_Success != error) - { - SDMMC_LOG("\r\nError: send CMD13 failed with host error %d, response %x", error, command.response[0U]); - break; - } - - if ((command.response[0U] & SDMMC_MASK(kSDMMC_R1ReadyForDataFlag)) && - (SDMMC_R1_CURRENT_STATE(command.response[0U]) != kSDMMC_R1StateProgram)) - { - break; - } - } while (true); - - return error; -} - -static status_t SD_SendWriteSuccessBlocks(sd_card_t *card, uint32_t *blocks) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_DATA data = {0}; - status_t error = kStatus_Success; - - memset(g_sdmmc, 0U, sizeof(g_sdmmc)); - - /* Wait for the card write process complete because of that card read process and write process use one buffer. */ - if (kStatus_Success != SD_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) - { - return kStatus_SDMMC_SendApplicationCommandFailed; - } - - command.index = kSD_ApplicationSendNumberWriteBlocks; - command.responseType = kCARD_ResponseTypeR1; - - data.blockSize = 4U; - data.blockCount = 1U; - data.rxData = &g_sdmmc[0]; - - content.command = &command; - content.data = &data; - error = card->host.transfer(card->host.base, &content); - if ((kStatus_Success != error) || ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) - { - SDMMC_LOG("\r\nError: send ACMD13 failed with host error %d, response %x", error, command.response[0U]); - } - else - { - *blocks = SWAP_WORD_BYTE_SEQUENCE(g_sdmmc[0]); - } - - return error; -} - -static status_t SD_SendRca(sd_card_t *card) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - status_t error = kStatus_Success; - - command.index = kSD_SendRelativeAddress; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR6; - - content.command = &command; - content.data = NULL; - - error = card->host.transfer(card->host.base, &content); - if (kStatus_Success == error) - { - card->relativeAddress = (command.response[0U] >> 16U); - } - else - { - SDMMC_LOG("\r\nError: send CMD3 failed with host error %d, response %x", error, command.response[0U]); - } - - return error; -} - -static status_t SD_SwitchFunction(sd_card_t *card, uint32_t mode, uint32_t group, uint32_t number, uint32_t *status) -{ - assert(card); - assert(status); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_DATA data = {0}; - status_t error = kStatus_Success; - - command.index = kSD_Switch; - command.argument = (mode << 31U | 0x00FFFFFFU); - command.argument &= ~((uint32_t)(0xFU) << (group * 4U)); - command.argument |= (number << (group * 4U)); - command.responseType = kCARD_ResponseTypeR1; - - data.blockSize = 64U; - data.blockCount = 1U; - data.rxData = status; - - content.command = &command; - content.data = &data; - error = card->host.transfer(card->host.base, &content); - if ((kStatus_Success != error) || ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) - { - SDMMC_LOG("\r\n\r\nError: send CMD6 failed with host error %d, response %x", error, command.response[0U]); - } - - return error; -} - -static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr) -{ - assert(card); - assert(rawScr); - - sd_scr_t *scr; - - scr = &(card->scr); - scr->scrStructure = (uint8_t)((rawScr[0U] & 0xF0000000U) >> 28U); - scr->sdSpecification = (uint8_t)((rawScr[0U] & 0xF000000U) >> 24U); - if ((uint8_t)((rawScr[0U] & 0x800000U) >> 23U)) - { - scr->flags |= kSD_ScrDataStatusAfterErase; - } - scr->sdSecurity = (uint8_t)((rawScr[0U] & 0x700000U) >> 20U); - scr->sdBusWidths = (uint8_t)((rawScr[0U] & 0xF0000U) >> 16U); - if ((uint8_t)((rawScr[0U] & 0x8000U) >> 15U)) - { - scr->flags |= kSD_ScrSdSpecification3; - } - scr->extendedSecurity = (uint8_t)((rawScr[0U] & 0x7800U) >> 10U); - scr->commandSupport = (uint8_t)(rawScr[0U] & 0x3U); - scr->reservedForManufacturer = rawScr[1U]; - /* Get specification version. */ - switch (scr->sdSpecification) - { - case 0U: - card->version = kSD_SpecificationVersion1_0; - break; - case 1U: - card->version = kSD_SpecificationVersion1_1; - break; - case 2U: - card->version = kSD_SpecificationVersion2_0; - if (card->scr.flags & kSD_ScrSdSpecification3) - { - card->version = kSD_SpecificationVersion3_0; - } - break; - default: - break; - } - if (card->scr.sdBusWidths & 0x4U) - { - card->flags |= kSD_Support4BitWidthFlag; - } - /* speed class control cmd */ - if (card->scr.commandSupport & 0x01U) - { - card->flags |= kSD_SupportSpeedClassControlCmd; - } - /* set block count cmd */ - if (card->scr.commandSupport & 0x02U) - { - card->flags |= kSD_SupportSetBlockCountCmd; - } -} - -static status_t SD_SendScr(sd_card_t *card) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_DATA data = {0}; - uint32_t *rawScr = g_sdmmc; - status_t error = kStatus_Success; - - /* memset the global buffer */ - memset(g_sdmmc, 0U, sizeof(g_sdmmc)); - - if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) - { - return kStatus_SDMMC_SendApplicationCommandFailed; - } - - command.index = kSD_ApplicationSendScr; - command.responseType = kCARD_ResponseTypeR1; - command.argument = 0U; - - data.blockSize = 8U; - data.blockCount = 1U; - data.rxData = rawScr; - - content.data = &data; - content.command = &command; - error = card->host.transfer(card->host.base, &content); - if ((kStatus_Success != error) || ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) - { - SDMMC_LOG("\r\nError: send ACMD51 failed with host error %d, response %x", error, command.response[0U]); - } - else - { - /* SCR register data byte sequence from card is big endian(MSB first). */ - switch (card->host.config.endianMode) - { - case kSDMMCHOST_EndianModeLittle: - /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in a - word which will cause 4 byte's sequence in a word is not consistent with their original sequence from - card. So the sequence of 4 bytes received in a word should be converted. */ - rawScr[0U] = SWAP_WORD_BYTE_SEQUENCE(rawScr[0U]); - rawScr[1U] = SWAP_WORD_BYTE_SEQUENCE(rawScr[1U]); - break; - case kSDMMCHOST_EndianModeBig: - break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ - case kSDMMCHOST_EndianModeHalfWordBig: - rawScr[0U] = SWAP_HALF_WROD_BYTE_SEQUENCE(rawScr[0U]); - rawScr[1U] = SWAP_HALF_WROD_BYTE_SEQUENCE(rawScr[1U]); - break; - default: - return kStatus_SDMMC_NotSupportYet; - } - memcpy(card->rawScr, rawScr, sizeof(card->rawScr)); - /* decode scr */ - SD_DecodeScr(card, rawScr); - } - - return error; -} - -static status_t SD_SelectFunction(sd_card_t *card, uint32_t group, uint32_t function) -{ - assert(card); - - uint32_t *functionStatus = g_sdmmc; - uint16_t functionGroupInfo[6U] = {0}; - uint32_t currentFunctionStatus = 0U; - - /* memset the global buffer */ - memset(g_sdmmc, 0, sizeof(g_sdmmc)); - - /* check if card support CMD6 */ - if ((card->version <= kSD_SpecificationVersion1_0) || (!(card->csd.cardCommandClass & kSDMMC_CommandClassSwitch))) - { - SDMMC_LOG("\r\nError: current card not support CMD6"); - return kStatus_SDMMC_NotSupportYet; - } - - /* Check if card support high speed mode. */ - if (kStatus_Success != SD_SwitchFunction(card, kSD_SwitchCheck, group, function, functionStatus)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Switch function status byte sequence from card is big endian(MSB first). */ - switch (card->host.config.endianMode) - { - case kSDMMCHOST_EndianModeLittle: - /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in - a word which will cause 4 byte's sequence in a word is not consistent with their original sequence from - card. So the sequence of 4 bytes received in a word should be converted. */ - functionStatus[0U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[0U]); - functionStatus[1U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[1U]); - functionStatus[2U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[2U]); - functionStatus[3U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[3U]); - functionStatus[4U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[4U]); - break; - case kSDMMCHOST_EndianModeBig: - break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ - case kSDMMCHOST_EndianModeHalfWordBig: - functionStatus[0U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[0U]); - functionStatus[1U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[1U]); - functionStatus[2U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[2U]); - functionStatus[3U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[3U]); - functionStatus[4U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[4U]); - break; - default: - return kStatus_SDMMC_NotSupportYet; - } - /* -functionStatus[0U]---bit511~bit480; - -functionStatus[1U]---bit479~bit448; - -functionStatus[2U]---bit447~bit416; - -functionStatus[3U]---bit415~bit384; - -functionStatus[4U]---bit383~bit352; - According to the "switch function status[bits 511~0]" return by switch command in mode "check function": - -Check if function 1(high speed) in function group 1 is supported by checking if bit 401 is set; - -check if function 1 is ready and can be switched by checking if bits 379~376 equal value 1; - */ - functionGroupInfo[5U] = (uint16_t)functionStatus[0U]; - functionGroupInfo[4U] = (uint16_t)(functionStatus[1U] >> 16U); - functionGroupInfo[3U] = (uint16_t)(functionStatus[1U]); - functionGroupInfo[2U] = (uint16_t)(functionStatus[2U] >> 16U); - functionGroupInfo[1U] = (uint16_t)(functionStatus[2U]); - functionGroupInfo[0U] = (uint16_t)(functionStatus[3U] >> 16U); - currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); - - /* check if function is support */ - if (((functionGroupInfo[group] & (1 << function)) == 0U) || - ((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) - { - SDMMC_LOG("\r\nError: current card not support function %d", function); - return kStatus_SDMMC_NotSupportYet; - } - - /* Switch to high speed mode. */ - if (kStatus_Success != SD_SwitchFunction(card, kSD_SwitchSet, group, function, functionStatus)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Switch function status byte sequence from card is big endian(MSB first). */ - switch (card->host.config.endianMode) - { - case kSDMMCHOST_EndianModeLittle: - /* In little endian mode is little endian, SD bus byte transferred first is the byte stored in lowest byte - position in a word which will cause 4 byte's sequence in a word is not consistent with their original - sequence from card. So the sequence of 4 bytes received in a word should be converted. */ - functionStatus[3U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[3U]); - functionStatus[4U] = SWAP_WORD_BYTE_SEQUENCE(functionStatus[4U]); - break; - case kSDMMCHOST_EndianModeBig: - break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ - case kSDMMCHOST_EndianModeHalfWordBig: - functionStatus[3U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[3U]); - functionStatus[4U] = SWAP_HALF_WROD_BYTE_SEQUENCE(functionStatus[4U]); - break; - default: - return kStatus_SDMMC_NotSupportYet; - } - /* According to the "switch function status[bits 511~0]" return by switch command in mode "set function": - -check if group 1 is successfully changed to function 1 by checking if bits 379~376 equal value 1; - */ - currentFunctionStatus = ((functionStatus[3U] & 0xFFU) << 8U) | (functionStatus[4U] >> 24U); - - if (((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) - { - SDMMC_LOG("\r\nError: switch to function %d failed", function); - return kStatus_SDMMC_SwitchFailed; - } - - return kStatus_Success; -} - -static status_t SD_SetDataBusWidth(sd_card_t *card, sd_data_bus_width_t width) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - status_t error = kStatus_Success; - - if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) - { - return kStatus_SDMMC_SendApplicationCommandFailed; - } - - command.index = kSD_ApplicationSetBusWdith; - command.responseType = kCARD_ResponseTypeR1; - switch (width) - { - case kSD_DataBusWidth1Bit: - command.argument = 0U; - break; - case kSD_DataBusWidth4Bit: - command.argument = 2U; - break; - default: - return kStatus_InvalidArgument; - } - - content.command = &command; - content.data = NULL; - error = card->host.transfer(card->host.base, &content); - if ((kStatus_Success != error) || ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) - { - SDMMC_LOG("\r\nError: send ACMD6 failed with host error %d, response %x", error, command.response[0U]); - } - - return error; -} - -static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd) -{ - assert(card); - assert(rawCsd); - - sd_csd_t *csd; - - csd = &(card->csd); - csd->csdStructure = (uint8_t)((rawCsd[3U] & 0xC0000000U) >> 30U); - csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF0000U) >> 16U); - csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); - csd->transferSpeed = (uint8_t)(rawCsd[3U] & 0xFFU); - csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF00000U) >> 20U); - csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF0000U) >> 16U); - if (rawCsd[2U] & 0x8000U) - { - csd->flags |= kSD_CsdReadBlockPartialFlag; - } - if (rawCsd[2U] & 0x4000U) - { - csd->flags |= kSD_CsdReadBlockPartialFlag; - } - if (rawCsd[2U] & 0x2000U) - { - csd->flags |= kSD_CsdReadBlockMisalignFlag; - } - if (rawCsd[2U] & 0x1000U) - { - csd->flags |= kSD_CsdDsrImplementedFlag; - } - switch (csd->csdStructure) - { - case 0: - csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FFU) << 2U); - csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xC0000000U) >> 30U); - csd->readCurrentVddMin = (uint8_t)((rawCsd[1U] & 0x38000000U) >> 27U); - csd->readCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x7000000U) >> 24U); - csd->writeCurrentVddMin = (uint8_t)((rawCsd[1U] & 0xE00000U) >> 20U); - csd->writeCurrentVddMax = (uint8_t)((rawCsd[1U] & 0x1C0000U) >> 18U); - csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x38000U) >> 15U); - - /* Get card total block count and block size. */ - card->blockCount = ((csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U)); - card->blockSize = (1U << (csd->readBlockLength)); - if (card->blockSize != FSL_SDMMC_DEFAULT_BLOCK_SIZE) - { - card->blockCount = (card->blockCount * card->blockSize); - card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; - card->blockCount = (card->blockCount / card->blockSize); - } - break; - case 1: - card->blockSize = FSL_SDMMC_DEFAULT_BLOCK_SIZE; - - csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3FU) << 16U); - csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xFFFF0000U) >> 16U); - if (csd->deviceSize >= 0xFFFFU) - { - card->flags |= kSD_SupportSdxcFlag; - } - - card->blockCount = ((csd->deviceSize + 1U) * 1024U); - break; - default: - break; - } - if ((uint8_t)((rawCsd[1U] & 0x4000U) >> 14U)) - { - csd->flags |= kSD_CsdEraseBlockEnabledFlag; - } - csd->eraseSectorSize = (uint8_t)((rawCsd[1U] & 0x3F80U) >> 7U); - csd->writeProtectGroupSize = (uint8_t)(rawCsd[1U] & 0x7FU); - if ((uint8_t)(rawCsd[0U] & 0x80000000U)) - { - csd->flags |= kSD_CsdWriteProtectGroupEnabledFlag; - } - csd->writeSpeedFactor = (uint8_t)((rawCsd[0U] & 0x1C000000U) >> 26U); - csd->writeBlockLength = (uint8_t)((rawCsd[0U] & 0x3C00000U) >> 22U); - if ((uint8_t)((rawCsd[0U] & 0x200000U) >> 21U)) - { - csd->flags |= kSD_CsdWriteBlockPartialFlag; - } - if ((uint8_t)((rawCsd[0U] & 0x8000U) >> 15U)) - { - csd->flags |= kSD_CsdFileFormatGroupFlag; - } - if ((uint8_t)((rawCsd[0U] & 0x4000U) >> 14U)) - { - csd->flags |= kSD_CsdCopyFlag; - } - if ((uint8_t)((rawCsd[0U] & 0x2000U) >> 13U)) - { - csd->flags |= kSD_CsdPermanentWriteProtectFlag; - } - if ((uint8_t)((rawCsd[0U] & 0x1000U) >> 12U)) - { - csd->flags |= kSD_CsdTemporaryWriteProtectFlag; - } - csd->fileFormat = (uint8_t)((rawCsd[0U] & 0xC00U) >> 10U); -} - -static status_t SD_SendCsd(sd_card_t *card) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - status_t error = kStatus_Success; - - command.index = kSDMMC_SendCsd; - command.argument = (card->relativeAddress << 16U); - command.responseType = kCARD_ResponseTypeR2; - - content.command = &command; - content.data = NULL; - error = card->host.transfer(card->host.base, &content); - if (kStatus_Success == error) - { - memcpy(card->rawCsd, command.response, sizeof(card->rawCsd)); - /* The response is from bit 127:8 in R2, corrisponding to command.response[3U]:command.response[0U][31U:8]. */ - SD_DecodeCsd(card, command.response); - } - else - { - error = kStatus_SDMMC_TransferFailed; - SDMMC_LOG("\r\nError: send CMD9(get csd) failed with host error %d, response %x", error, command.response[0U]); - } - - return error; -} - -static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid) -{ - assert(card); - assert(rawCid); - - sd_cid_t *cid; - - cid = &(card->cid); - cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF000000U) >> 24U); - cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFF00U) >> 8U); - - cid->productName[0U] = (uint8_t)((rawCid[3U] & 0xFFU)); - cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); - cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); - cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); - cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFFU)); - - cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24U); - - cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFFFU) << 8U); - cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFF000000U) >> 24U); - - cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFF00U) >> 8U); -} - -static status_t SD_AllSendCid(sd_card_t *card) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - - command.index = kSDMMC_AllSendCid; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR2; - - content.command = &command; - content.data = NULL; - if (kStatus_Success == card->host.transfer(card->host.base, &content)) - { - memcpy(card->rawCid, command.response, sizeof(card->rawCid)); - SD_DecodeCid(card, command.response); - - return kStatus_Success; - } - - return kStatus_SDMMC_TransferFailed; -} - -static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - status_t error = kStatus_Fail; - uint32_t i = FSL_SDMMC_MAX_VOLTAGE_RETRIES; - - command.index = kSD_ApplicationSendOperationCondition; - command.argument = argument; - command.responseType = kCARD_ResponseTypeR3; - - while (i--) - { - if (kStatus_Success != SD_SendApplicationCmd(card, 0U)) - { - continue; - } - - content.command = &command; - content.data = NULL; - error = card->host.transfer(card->host.base, &content); - if (kStatus_Success != error) - { - SDMMC_LOG("\r\nError: send ACMD41 failed with host error %d, response %x", error, command.response[0U]); - return kStatus_SDMMC_TransferFailed; - } - - /* Wait until card exit busy state. */ - if (command.response[0U] & SDMMC_MASK(kSD_OcrPowerUpBusyFlag)) - { - /* high capacity check */ - if (command.response[0U] & SDMMC_MASK(kSD_OcrCardCapacitySupportFlag)) - { - card->flags |= kSD_SupportHighCapacityFlag; - } - /* 1.8V support */ - if (command.response[0U] & SDMMC_MASK(kSD_OcrSwitch18AcceptFlag)) - { - card->flags |= kSD_SupportVoltage180v; - } - card->ocr = command.response[0U]; - - return kStatus_Success; - } - } - - SDMMC_LOG("\r\nError: send ACMD41 timeout"); - - return error; -} - -static status_t SD_SendInterfaceCondition(sd_card_t *card) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; - status_t error = kStatus_Success; - - command.index = kSD_SendInterfaceCondition; - command.argument = 0x1AAU; - command.responseType = kCARD_ResponseTypeR7; - - content.command = &command; - content.data = NULL; - do - { - error = card->host.transfer(card->host.base, &content); - if (kStatus_Success != error) - { - SDMMC_LOG("\r\nError: send CMD8 failed with host error %d, response %x", error, command.response[0U]); - } - else - { - if ((command.response[0U] & 0xFFU) != 0xAAU) - { - error = kStatus_SDMMC_CardNotSupport; - SDMMC_LOG("\r\nError: card not support CMD8"); - } - else - { - error = kStatus_Success; - } - } - } while (--i && (error != kStatus_Success)); - - return error; -} - -static status_t SD_SelectBusTiming(sd_card_t *card) -{ - assert(card); - - status_t error = kStatus_SDMMC_SwitchBusTimingFailed; - - if (card->operationVoltage != kCARD_OperationVoltage180V) - { - /* Switch the card to high speed mode */ - if (card->host.capability.flags & kSDMMCHOST_SupportHighSpeed) - { - /* group 1, function 1 ->high speed mode*/ - error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); - /* If the result isn't "switching to high speed mode(50MHZ) successfully or card doesn't support high speed - * mode". Return failed status. */ - if (error == kStatus_Success) - { - card->currentTiming = kSD_TimingSDR25HighSpeedMode; - card->busClock_Hz = - SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); - } - else if (error == kStatus_SDMMC_NotSupportYet) - { - /* if not support high speed, keep the card work at default mode */ - SDMMC_LOG("\r\nNote: High speed mode is not supported by card"); - return kStatus_Success; - } - } - else - { - /* if not support high speed, keep the card work at default mode */ - return kStatus_Success; - } - } - /* card is in UHS_I mode */ - else if ((kSDMMCHOST_SupportSDR104 != SDMMCHOST_NOT_SUPPORT) || - (kSDMMCHOST_SupportSDR50 != SDMMCHOST_NOT_SUPPORT) || (kSDMMCHOST_SupportDDR50 != SDMMCHOST_NOT_SUPPORT)) - { - switch (card->currentTiming) - { - /* if not select timing mode, sdmmc will handle it automatically*/ - case kSD_TimingSDR12DefaultMode: - case kSD_TimingSDR104Mode: - error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR104); - if (error == kStatus_Success) - { - card->currentTiming = kSD_TimingSDR104Mode; - card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, - SDMMCHOST_SUPPORT_SDR104_FREQ); - break; - } - SDMMC_LOG("\r\nNote: SDR104 mode is not supported by card"); - - case kSD_TimingDDR50Mode: - error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionDDR50); - if (error == kStatus_Success) - { - card->currentTiming = kSD_TimingDDR50Mode; - card->busClock_Hz = - SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); - SDMMCHOST_ENABLE_DDR_MODE(card->host.base, true, 0U); - break; - } - SDMMC_LOG("\r\nNote: DDR50 mode is not supported by card"); - - case kSD_TimingSDR50Mode: - error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR50); - if (error == kStatus_Success) - { - card->currentTiming = kSD_TimingSDR50Mode; - card->busClock_Hz = - SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_100MHZ); - break; - } - SDMMC_LOG("\r\nNote: SDR50 mode is not supported by card"); - - case kSD_TimingSDR25HighSpeedMode: - error = SD_SelectFunction(card, kSD_GroupTimingMode, kSD_FunctionSDR25HighSpeed); - if (error == kStatus_Success) - { - card->currentTiming = kSD_TimingSDR25HighSpeedMode; - card->busClock_Hz = - SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); - } - break; - - default: - SDMMC_LOG("\r\nWarning: unknown timing mode"); - break; - } - } - else - { - } - - if (error == kStatus_Success) - { - /* SDR50 and SDR104 mode need tuning */ - if ((card->currentTiming == kSD_TimingSDR50Mode) || (card->currentTiming == kSD_TimingSDR104Mode)) - { - /* config IO strength in IOMUX*/ - if (card->currentTiming == kSD_TimingSDR50Mode) - { - SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_7); - } - else - { - SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); - } - /* execute tuning */ - if (SD_ExecuteTuning(card) != kStatus_Success) - { - SDMMC_LOG("\r\nError: tuning failed for mode %d", card->currentTiming); - return kStatus_SDMMC_TuningFail; - } - } - else - { - /* set default IO strength to 4 to cover card adapter driver strength difference */ - SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_4); - } - } - - return error; -} - -static void SD_DecodeStatus(sd_card_t *card, uint32_t *src) -{ - assert(card); - assert(src); - - card->stat.busWidth = (uint8_t)((src[0U] & 0xC0000000U) >> 30U); /* 511-510 */ - card->stat.secureMode = (uint8_t)((src[0U] & 0x20000000U) >> 29U); /* 509 */ - card->stat.cardType = (uint16_t)((src[0U] & 0x0000FFFFU)); /* 495-480 */ - card->stat.protectedSize = src[1U]; /* 479-448 */ - card->stat.speedClass = (uint8_t)((src[2U] & 0xFF000000U) >> 24U); /* 447-440 */ - card->stat.performanceMove = (uint8_t)((src[2U] & 0x00FF0000U) >> 16U); /* 439-432 */ - card->stat.auSize = (uint8_t)((src[2U] & 0x0000F000U) >> 12U); /* 431-428 */ - card->stat.eraseSize = (uint16_t)(((src[2U] & 0x000000FFU) << 8U) | ((src[3U] & 0xFF000000U) >> 24U)); /* 423-408 */ - card->stat.eraseTimeout = (((uint8_t)((src[3U] & 0x00FF0000U) >> 16U)) & 0xFCU) >> 2U; /* 407-402 */ - card->stat.eraseOffset = ((uint8_t)((src[3U] & 0x00FF0000U) >> 16U)) & 0x3U; /* 401-400 */ - card->stat.uhsSpeedGrade = (((uint8_t)((src[3U] & 0x0000FF00U) >> 8U)) & 0xF0U) >> 4U; /* 399-396 */ - card->stat.uhsAuSize = ((uint8_t)((src[3U] & 0x0000FF00U) >> 8U)) & 0xFU; /* 395-392 */ -} - -status_t SD_ReadStatus(sd_card_t *card) -{ - assert(card); - - uint32_t i = 0U; - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_DATA data = {0}; - status_t error = kStatus_Success; - - memset(g_sdmmc, 0U, sizeof(g_sdmmc)); - - /* wait card status ready. */ - if (kStatus_Success != SD_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - if (kStatus_Success != SD_SendApplicationCmd(card, card->relativeAddress)) - { - return kStatus_SDMMC_SendApplicationCommandFailed; - } - - command.index = kSDMMC_SendStatus; - command.responseType = kCARD_ResponseTypeR1; - - data.blockSize = 64U; - data.blockCount = 1U; - data.rxData = &g_sdmmc[0]; - - content.command = &command; - content.data = &data; - error = card->host.transfer(card->host.base, &content); - if ((kStatus_Success != error) || ((command.response[0U]) & SDMMC_R1_ALL_ERROR_FLAG)) - { - SDMMC_LOG("\r\nError: send ACMD13 failed with host error %d, response %x", error, command.response[0U]); - - return kStatus_SDMMC_TransferFailed; - } - - switch (card->host.config.endianMode) - { - case kSDMMCHOST_EndianModeLittle: - /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in - a word which will cause 4 byte's sequence in a word is not consistent with their original sequence from - card. So the sequence of 4 bytes received in a word should be converted. */ - for (i = 0U; i < 16; i++) - { - g_sdmmc[i] = SWAP_WORD_BYTE_SEQUENCE(g_sdmmc[i]); - } - break; - case kSDMMCHOST_EndianModeBig: - break; /* Doesn't need to switch byte sequence when decodes bytes as big endian sequence. */ - case kSDMMCHOST_EndianModeHalfWordBig: - for (i = 0U; i < 16; i++) - { - g_sdmmc[i] = SWAP_HALF_WROD_BYTE_SEQUENCE(g_sdmmc[i]); - } - break; - default: - return kStatus_SDMMC_NotSupportYet; - } - - SD_DecodeStatus(card, g_sdmmc); - - return kStatus_Success; -} - -status_t SD_SelectCard(sd_card_t *card, bool isSelected) -{ - assert(card); - - return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); -} - -status_t SD_SetDriverStrength(sd_card_t *card, sd_driver_strength_t driverStrength) -{ - assert(card); - - status_t error; - uint32_t strength = driverStrength; - - error = SD_SelectFunction(card, kSD_GroupDriverStrength, strength); - - return error; -} - -status_t SD_SetMaxCurrent(sd_card_t *card, sd_max_current_t maxCurrent) -{ - assert(card); - - status_t error; - uint32_t current = maxCurrent; - - error = SD_SelectFunction(card, kSD_GroupCurrentLimit, current); - - return error; -} - -static status_t SD_Read(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockSize, uint32_t blockCount) -{ - assert(card); - assert(buffer); - assert(blockCount); - assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_DATA data = {0}; - - if (((card->flags & kSD_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || - (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4)) - { - SDMMC_LOG("\r\nError: read with parameter, block size %d is not support", blockSize); - return kStatus_SDMMC_CardNotSupport; - } - - /* Wait for the card write process complete because of that card read process and write process use one buffer. */ - if (kStatus_Success != SD_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - data.blockSize = blockSize; - data.blockCount = blockCount; - data.rxData = (uint32_t *)buffer; - data.enableAutoCommand12 = true; - - command.index = (blockCount == 1U) ? kSDMMC_ReadSingleBlock : kSDMMC_ReadMultipleBlock; - command.argument = startBlock; - if (!(card->flags & kSD_SupportHighCapacityFlag)) - { - command.argument *= data.blockSize; - } - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; - - content.command = &command; - content.data = &data; - - return SD_Transfer(card, &content, 1U); -} - -static status_t SD_Write(sd_card_t *card, - const uint8_t *buffer, - uint32_t startBlock, - uint32_t blockSize, - uint32_t blockCount, - uint32_t *writtenBlocks) -{ - assert(card); - assert(buffer); - assert(blockCount); - assert(blockSize == FSL_SDMMC_DEFAULT_BLOCK_SIZE); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - SDMMCHOST_DATA data = {0}; - status_t error; - - if (((card->flags & kSD_SupportHighCapacityFlag) && (blockSize != 512U)) || (blockSize > card->blockSize) || - (blockSize > card->host.capability.maxBlockLength) || (blockSize % 4U)) - { - SDMMC_LOG("\r\nError: write with parameter, block size %d is not support", blockSize); - return kStatus_SDMMC_CardNotSupport; - } - - /* Wait for the card write process complete because of that card read process and write process use one buffer.*/ - if (kStatus_Success != SD_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - - /* Wait for the card's buffer to be not full to write to improve the write performance. */ - while ((GET_SDMMCHOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) - { - } - - data.enableAutoCommand12 = true; - data.blockSize = blockSize; - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; - - command.index = (blockCount == 1U) ? kSDMMC_WriteSingleBlock : kSDMMC_WriteMultipleBlock; - command.argument = startBlock; - if (!(card->flags & kSD_SupportHighCapacityFlag)) - { - command.argument *= data.blockSize; - } - - *writtenBlocks = blockCount; - data.blockCount = blockCount; - data.txData = (const uint32_t *)(buffer); - - content.command = &command; - content.data = &data; - - error = SD_Transfer(card, &content, 0U); - if (error != kStatus_Success) - { - /* check the successfully written block */ - if ((SD_SendWriteSuccessBlocks(card, writtenBlocks) == kStatus_Success)) - { - if (*writtenBlocks) - { - /* written success, but not all the blocks are written */ - error = kStatus_Success; - } - } - SDMMC_LOG("\r\nWarning: write failed with block count %d, successed %d", blockCount, *writtenBlocks); - } - - return error; -} - -static status_t SD_Erase(sd_card_t *card, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(blockCount); - - uint32_t eraseBlockStart; - uint32_t eraseBlockEnd; - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - status_t error = kStatus_Success; - - /* Wait for the card write process complete because of that card read process and write process use one buffer.*/ - if (kStatus_Success != SD_WaitWriteComplete(card)) - { - return kStatus_SDMMC_WaitWriteCompleteFailed; - } - /* Wait for the card's buffer to be not full to write to improve the write performance. */ - while ((GET_SDMMCHOST_STATUS(card->host.base) & CARD_DATA0_STATUS_MASK) != CARD_DATA0_NOT_BUSY) - { - } - - eraseBlockStart = startBlock; - eraseBlockEnd = eraseBlockStart + blockCount - 1U; - if (!(card->flags & kSD_SupportHighCapacityFlag)) - { - eraseBlockStart = eraseBlockStart * FSL_SDMMC_DEFAULT_BLOCK_SIZE; - eraseBlockEnd = eraseBlockEnd * FSL_SDMMC_DEFAULT_BLOCK_SIZE; - } - - /* Send ERASE_WRITE_BLOCK_START command to set the start block number to erase. */ - command.index = kSD_EraseWriteBlockStart; - command.argument = eraseBlockStart; - command.responseType = kCARD_ResponseTypeR1; - command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; - - content.command = &command; - content.data = NULL; - error = SD_Transfer(card, &content, 1U); - if (kStatus_Success != error) - { - SDMMC_LOG("\r\nError: send CMD32(erase start) failed with host error %d, response %x", error, - command.response[0U]); - return kStatus_SDMMC_TransferFailed; - } - - /* Send ERASE_WRITE_BLOCK_END command to set the end block number to erase. */ - command.index = kSD_EraseWriteBlockEnd; - command.argument = eraseBlockEnd; - - content.command = &command; - content.data = NULL; - error = SD_Transfer(card, &content, 0U); - if (kStatus_Success != error) - { - SDMMC_LOG("\r\nError: send CMD33(erase end) failed with host error %d, response %x", error, - command.response[0U]); - return kStatus_SDMMC_TransferFailed; - } - - /* Send ERASE command to start erase process. */ - command.index = kSDMMC_Erase; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1b; - command.responseErrorFlags = SDMMC_R1_ALL_ERROR_FLAG; - - content.command = &command; - content.data = NULL; - error = SD_Transfer(card, &content, 0U); - if (kStatus_Success != error) - { - SDMMC_LOG("\r\nError: send CMD38(erase) failed with host error %d, response %x", error, command.response[0U]); - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -bool SD_CheckReadOnly(sd_card_t *card) -{ - assert(card); - - return ((card->csd.flags & kSD_CsdPermanentWriteProtectFlag) || - (card->csd.flags & kSD_CsdTemporaryWriteProtectFlag)); -} - -status_t SD_ReadBlocks(sd_card_t *card, uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(buffer); - assert(blockCount); - assert((blockCount + startBlock) <= card->blockCount); - - uint32_t blockCountOneTime; - uint32_t blockLeft; - uint32_t blockDone = 0U; - uint8_t *nextBuffer = buffer; - bool dataAddrAlign = true; - - blockLeft = blockCount; - - while (blockLeft) - { - nextBuffer = (buffer + blockDone * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - if (!card->noInteralAlign && (!dataAddrAlign || (((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U)))) - { - blockLeft--; - blockCountOneTime = 1U; - memset(g_sdmmc, 0U, FSL_SDMMC_DEFAULT_BLOCK_SIZE); - dataAddrAlign = false; - } - else - { - if (blockLeft > card->host.capability.maxBlockCount) - { - blockLeft = (blockLeft - card->host.capability.maxBlockCount); - blockCountOneTime = card->host.capability.maxBlockCount; - } - else - { - blockCountOneTime = blockLeft; - blockLeft = 0U; - } - } - - if (kStatus_Success != SD_Read(card, dataAddrAlign ? nextBuffer : (uint8_t *)g_sdmmc, (startBlock + blockDone), - FSL_SDMMC_DEFAULT_BLOCK_SIZE, blockCountOneTime)) - { - return kStatus_SDMMC_TransferFailed; - } - - blockDone += blockCountOneTime; - - if (!card->noInteralAlign && (!dataAddrAlign)) - { - memcpy(nextBuffer, (uint8_t *)&g_sdmmc, FSL_SDMMC_DEFAULT_BLOCK_SIZE); - } - } - - return kStatus_Success; -} - -status_t SD_WriteBlocks(sd_card_t *card, const uint8_t *buffer, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(buffer); - assert(blockCount); - assert((blockCount + startBlock) <= card->blockCount); - - uint32_t blockCountOneTime = 0U; /* The block count can be wrote in one time sending WRITE_BLOCKS command. */ - uint32_t blockWrittenOneTime = 0U; - uint32_t blockLeft = 0U; /* Left block count to be wrote. */ - const uint8_t *nextBuffer; - bool dataAddrAlign = true; - - blockLeft = blockCount; - while (blockLeft) - { - nextBuffer = (buffer + (blockCount - blockLeft) * FSL_SDMMC_DEFAULT_BLOCK_SIZE); - if (!card->noInteralAlign && (!dataAddrAlign || (((uint32_t)nextBuffer) & (sizeof(uint32_t) - 1U)))) - { - blockCountOneTime = 1U; - memcpy((uint8_t *)&g_sdmmc, nextBuffer, FSL_SDMMC_DEFAULT_BLOCK_SIZE); - dataAddrAlign = false; - } - else - { - if (blockLeft > card->host.capability.maxBlockCount) - { - blockCountOneTime = card->host.capability.maxBlockCount; - } - else - { - blockCountOneTime = blockLeft; - } - } - - if (kStatus_Success != SD_Write(card, dataAddrAlign ? nextBuffer : (uint8_t *)g_sdmmc, - (startBlock + blockCount - blockLeft), FSL_SDMMC_DEFAULT_BLOCK_SIZE, - blockCountOneTime, &blockWrittenOneTime)) - { - return kStatus_SDMMC_TransferFailed; - } - - blockLeft -= blockWrittenOneTime; - - if ((!card->noInteralAlign) && !dataAddrAlign) - { - memset(g_sdmmc, 0U, FSL_SDMMC_DEFAULT_BLOCK_SIZE); - } - } - - return kStatus_Success; -} - -status_t SD_EraseBlocks(sd_card_t *card, uint32_t startBlock, uint32_t blockCount) -{ - assert(card); - assert(blockCount); - assert((blockCount + startBlock) <= card->blockCount); - - uint32_t blockCountOneTime; /* The block count can be erased in one time sending ERASE_BLOCKS command. */ - uint32_t blockDone = 0U; /* The block count has been erased. */ - uint32_t blockLeft; /* Left block count to be erase. */ - status_t error; - uint32_t onetimeMaxEraseBlocks = 0U; - - /* sdsc card erasable sector is determined by CSD register */ - if (card->csd.csdStructure == 0U) - { - onetimeMaxEraseBlocks = card->csd.eraseSectorSize + 1U; - } - else - { - /* limit one time maximum erase size to 1 AU */ - if (card->stat.auSize >= SD_AU_START_VALUE) - { - onetimeMaxEraseBlocks = s_sdAuSizeMap[card->stat.auSize] / FSL_SDMMC_DEFAULT_BLOCK_SIZE; - } - } - - if (onetimeMaxEraseBlocks == 0U) - { - SDMMC_LOG( - "Warning: AU size in sd descriptor is not set properly, please check if SD_ReadStatus is called before\ - SD_EraseBlocks"); - return kStatus_SDMMC_AuSizeNotSetProperly; - } - - blockLeft = blockCount; - while (blockLeft) - { - if (blockLeft > onetimeMaxEraseBlocks) - { - blockCountOneTime = onetimeMaxEraseBlocks; - blockLeft = blockLeft - blockCountOneTime; - } - else - { - blockCountOneTime = blockLeft; - blockLeft = 0U; - } - - error = SD_Erase(card, (startBlock + blockDone), blockCountOneTime); - if (error != kStatus_Success) - { - return error; - } - - blockDone += blockCountOneTime; - } - - return kStatus_Success; -} - -status_t SD_ProbeBusVoltage(sd_card_t *card) -{ - assert(card); - - uint32_t applicationCommand41Argument = 0U; - status_t error = kStatus_Success; - - /* 3.3V voltage should be supported as default */ - applicationCommand41Argument |= - SDMMC_MASK(kSD_OcrVdd29_30Flag) | SDMMC_MASK(kSD_OcrVdd32_33Flag) | SDMMC_MASK(kSD_OcrVdd33_34Flag); - /* make sure card signal line voltage is 3.3v before initalization */ - if ((card->usrParam.cardVoltage != NULL) && (card->usrParam.cardVoltage->cardSignalLine3V3 != NULL)) - { - card->usrParam.cardVoltage->cardSignalLine3V3(); - } - else - { - SDMMCHOST_SWITCH_VOLTAGE180V(card->host.base, false); - } - card->operationVoltage = kCARD_OperationVoltage330V; - - /* allow user select the work voltage, if not select, sdmmc will handle it automatically */ - if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) - { - applicationCommand41Argument |= SDMMC_MASK(kSD_OcrSwitch18RequestFlag); - } - - do - { - /* card go idle */ - if (kStatus_Success != SD_GoIdle(card)) - { - error = kStatus_SDMMC_GoIdleFailed; - break; - } - - /* Check card's supported interface condition. */ - if (kStatus_Success == SD_SendInterfaceCondition(card)) - { - /* SDHC or SDXC card */ - applicationCommand41Argument |= SDMMC_MASK(kSD_OcrHostCapacitySupportFlag); - card->flags |= kSD_SupportSdhcFlag; - } - else - { - /* SDSC card */ - if (kStatus_Success != SD_GoIdle(card)) - { - error = kStatus_SDMMC_GoIdleFailed; - break; - } - } - /* Set card interface condition according to SDHC capability and card's supported interface condition. */ - if (kStatus_Success != SD_ApplicationSendOperationCondition(card, applicationCommand41Argument)) - { - error = kStatus_SDMMC_HandShakeOperationConditionFailed; - break; - } - - /* check if card support 1.8V */ - if ((card->flags & kSD_SupportVoltage180v)) - { - error = SD_SwitchVoltage(card); - if (kStatus_SDMMC_SwitchVoltageFail == error) - { - break; - } - - if (error == kStatus_SDMMC_SwitchVoltage18VFail33VSuccess) - { - applicationCommand41Argument &= ~SDMMC_MASK(kSD_OcrSwitch18RequestFlag); - card->flags &= ~kSD_SupportVoltage180v; - continue; - } - else - { - card->operationVoltage = kCARD_OperationVoltage180V; - break; - } - } - - break; - } while (1U); - - return error; -} - -status_t SD_CardInit(sd_card_t *card) -{ - assert(card); - assert(card->isHostReady == true); - - /* reset variables */ - card->flags = 0U; - /* set DATA bus width */ - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); - /*set card freq to 400KHZ*/ - card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); - /* send card active */ - SDMMCHOST_SEND_CARD_ACTIVE(card->host.base, 100U); - /* Get host capability. */ - GET_SDMMCHOST_CAPABILITY(card->host.base, &(card->host.capability)); - - /* probe bus voltage*/ - if (SD_ProbeBusVoltage(card) == kStatus_SDMMC_SwitchVoltageFail) - { - return kStatus_SDMMC_SwitchVoltageFail; - } - - /* Initialize card if the card is SD card. */ - if (kStatus_Success != SD_AllSendCid(card)) - { - return kStatus_SDMMC_AllSendCidFailed; - } - if (kStatus_Success != SD_SendRca(card)) - { - return kStatus_SDMMC_SendRelativeAddressFailed; - } - if (kStatus_Success != SD_SendCsd(card)) - { - return kStatus_SDMMC_SendCsdFailed; - } - if (kStatus_Success != SD_SelectCard(card, true)) - { - return kStatus_SDMMC_SelectCardFailed; - } - - /* Set to max frequency in non-high speed mode. */ - card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_25MHZ); - - if (kStatus_Success != SD_SendScr(card)) - { - return kStatus_SDMMC_SendScrFailed; - } - /* Set to 4-bit data bus mode. */ - if (((card->host.capability.flags) & kSDMMCHOST_Support4BitBusWidth) && (card->flags & kSD_Support4BitWidthFlag)) - { - if (kStatus_Success != SD_SetDataBusWidth(card, kSD_DataBusWidth4Bit)) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH4BIT); - } - - /* set block size */ - if (SD_SetBlockSize(card, FSL_SDMMC_DEFAULT_BLOCK_SIZE)) - { - return kStatus_SDMMC_SetCardBlockSizeFailed; - } - - /* select bus timing */ - if (kStatus_Success != SD_SelectBusTiming(card)) - { - return kStatus_SDMMC_SwitchBusTimingFailed; - } - - /* try to get card current status */ - SD_ReadStatus(card); - - return kStatus_Success; -} - -void SD_CardDeinit(sd_card_t *card) -{ - assert(card); - - SD_SelectCard(card, false); -} - -status_t SD_HostInit(sd_card_t *card) -{ - assert(card); - - if ((!card->isHostReady) && SDMMCHOST_Init(&(card->host), (void *)(&(card->usrParam))) != kStatus_Success) - { - return kStatus_Fail; - } - - /* set the host status flag, after the card re-plug in, don't need init host again */ - card->isHostReady = true; - - return kStatus_Success; -} - -void SD_HostDeinit(sd_card_t *card) -{ - assert(card); - - SDMMCHOST_Deinit(&(card->host)); - /* should re-init host */ - card->isHostReady = false; -} - -void SD_HostReset(SDMMCHOST_CONFIG *host) -{ - SDMMCHOST_Reset(host->base); -} - -void SD_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - SDMMCHOST_PowerOnCard(base, pwr); -} - -void SD_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - SDMMCHOST_PowerOffCard(base, pwr); -} - -status_t SD_WaitCardDetectStatus(SDMMCHOST_TYPE *hostBase, const sdmmchost_detect_card_t *cd, bool waitCardStatus) -{ - return SDMMCHOST_WaitCardDetectStatus(hostBase, cd, waitCardStatus); -} - -bool SD_IsCardPresent(sd_card_t *card) -{ - return SDMMCHOST_IsCardPresent(); -} - -status_t SD_Init(sd_card_t *card) -{ - assert(card); - - if (!card->isHostReady) - { - if (SD_HostInit(card) != kStatus_Success) - { - return kStatus_SDMMC_HostNotReady; - } - } - else - { - SD_HostReset(&(card->host)); - } - SD_PowerOffCard(card->host.base, card->usrParam.pwr); - - if (SD_WaitCardDetectStatus(card->host.base, card->usrParam.cd, true) != kStatus_Success) - { - return kStatus_SDMMC_CardDetectFailed; - } - SD_PowerOnCard(card->host.base, card->usrParam.pwr); - - return SD_CardInit(card); -} - -void SD_Deinit(sd_card_t *card) -{ - /* card deinitialize */ - SD_CardDeinit(card); - /* host deinitialize */ - SD_HostDeinit(card); -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdio.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdio.c deleted file mode 100644 index 2c45f18e36..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdio.c +++ /dev/null @@ -1,1700 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sdio.h" - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief define the tuple number will be read during init */ -#define SDIO_COMMON_CIS_TUPLE_NUM (3U) -/*! @brief SDIO retry times */ -#define SDIO_RETRY_TIMES (1000U) - -/******************************************************************************* - * Prototypes - ******************************************************************************/ -/*! - * @brief probe bus voltage. - * @param card Card descriptor. - */ -static status_t SDIO_ProbeBusVoltage(sdio_card_t *card); - -/*! - * @brief send card operation condition - * @param card Card descriptor. - * @param command argment - * argument = 0U , means to get the operation condition - * argument !=0 , set the operation condition register - */ -static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument); - -/*! - * @brief card Send relative address - * @param card Card descriptor. - */ -static status_t SDIO_SendRca(sdio_card_t *card); - -/*! - * @brief card select card - * @param card Card descriptor. - * @param select/diselect flag - */ -static status_t inline SDIO_SelectCard(sdio_card_t *card, bool isSelected); - -/*! - * @brief card go idle - * @param card Card descriptor. - */ -static status_t inline SDIO_GoIdle(sdio_card_t *card); - -/*! - * @brief decode CIS - * @param card Card descriptor. - * @param func number - * @param data buffer pointer - * @param tuple code - * @param tuple link - */ -static status_t SDIO_DecodeCIS( - sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink); - -/*! - * @brief switch to the maxium support bus width, depend on the host and card's capability. - * @param card Card descriptor. - */ -static status_t SDIO_SetMaxDataBusWidth(sdio_card_t *card); - -/*! - * @brief sdio card excute tuning. - * @param card Card descriptor. - */ - -static status_t SDIO_ExecuteTuning(sdio_card_t *card); - -/******************************************************************************* - * Variables - ******************************************************************************/ -/* define the tuple list */ -static const uint32_t g_tupleList[SDIO_COMMON_CIS_TUPLE_NUM] = { - SDIO_TPL_CODE_MANIFID, - SDIO_TPL_CODE_FUNCID, - SDIO_TPL_CODE_FUNCE, -}; - -/* g_sdmmc statement */ -extern uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)]; -/******************************************************************************* - * Code - ******************************************************************************/ -static status_t inline SDIO_SelectCard(sdio_card_t *card, bool isSelected) -{ - assert(card); - - return SDMMC_SelectCard(card->host.base, card->host.transfer, card->relativeAddress, isSelected); -} - -static status_t inline SDIO_GoIdle(sdio_card_t *card) -{ - assert(card); - - return SDMMC_GoIdle(card->host.base, card->host.transfer); -} - -static status_t SDIO_SwitchVoltage(sdio_card_t *card) -{ - assert(card); - - if ((card->usrParam.cardVoltage != NULL) && (card->usrParam.cardVoltage->cardSignalLine1V8 != NULL)) - { - return SDMMC_SwitchToVoltage(card->host.base, card->host.transfer, - card->usrParam.cardVoltage->cardSignalLine1V8); - } - - return SDMMC_SwitchToVoltage(card->host.base, card->host.transfer, NULL); -} - -static status_t SDIO_ExecuteTuning(sdio_card_t *card) -{ - assert(card); - - return SDMMC_ExecuteTuning(card->host.base, card->host.transfer, kSD_SendTuningBlock, 64U); -} - -static status_t SDIO_SendRca(sdio_card_t *card) -{ - assert(card); - - uint32_t i = FSL_SDMMC_MAX_CMD_RETRIES; - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - - command.index = kSDIO_SendRelativeAddress; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR6; - command.responseErrorFlags = kSDIO_StatusR6Error | kSDIO_StatusIllegalCmd | kSDIO_StatusCmdCRCError; - - content.command = &command; - content.data = NULL; - - while (--i) - { - if (kStatus_Success == card->host.transfer(card->host.base, &content)) - { - /* check illegal state and cmd CRC error, may be the voltage or clock not stable, retry the cmd*/ - if (command.response[0U] & (kSDIO_StatusIllegalCmd | kSDIO_StatusCmdCRCError)) - { - continue; - } - - card->relativeAddress = (command.response[0U] >> 16U); - - return kStatus_Success; - } - } - - return kStatus_SDMMC_TransferFailed; -} - -status_t SDIO_CardInActive(sdio_card_t *card) -{ - assert(card); - - return SDMMC_SetCardInactive(card->host.base, card->host.transfer); -} - -static status_t SDIO_SendOperationCondition(sdio_card_t *card, uint32_t argument) -{ - assert(card); - - SDMMCHOST_TRANSFER content = {0U}; - SDMMCHOST_COMMAND command = {0U}; - uint32_t i = SDIO_RETRY_TIMES; - - command.index = kSDIO_SendOperationCondition; - command.argument = argument; - command.responseType = kCARD_ResponseTypeR4; - - content.command = &command; - content.data = NULL; - - while (--i) - { - if (kStatus_Success != card->host.transfer(card->host.base, &content) || (command.response[0U] == 0U)) - { - continue; - } - - /* if argument equal 0, then should check and save the info */ - if (argument == 0U) - { - /* check if memory present */ - if ((command.response[0U] & SDMMC_MASK(kSDIO_OcrMemPresent)) == SDMMC_MASK(kSDIO_OcrMemPresent)) - { - card->memPresentFlag = true; - } - /* save the io number */ - card->ioTotalNumber = (command.response[0U] & SDIO_OCR_IO_NUM_MASK) >> kSDIO_OcrIONumber; - /* save the operation condition */ - card->ocr = command.response[0U] & 0xFFFFFFU; - - break; - } - /* wait the card is ready for after initialization */ - else if (command.response[0U] & SDMMC_MASK(kSDIO_OcrPowerUpBusyFlag)) - { - break; - } - } - - return ((i != 0U) ? kStatus_Success : kStatus_Fail); -} - -status_t SDIO_IO_Write_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data, bool raw) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - SDMMCHOST_TRANSFER content = {0U}; - SDMMCHOST_COMMAND command = {0U}; - - command.index = kSDIO_RWIODirect; - command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | - ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | - (1U << SDIO_CMD_ARGUMENT_RW_POS) | ((raw ? 1U : 0U) << SDIO_DIRECT_CMD_ARGUMENT_RAW_POS) | - (*data & SDIO_DIRECT_CMD_DATA_MASK); - command.responseType = kCARD_ResponseTypeR5; - command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | - kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); - - content.command = &command; - content.data = NULL; - - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* read data from response */ - *data = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; - - return kStatus_Success; -} - -status_t SDIO_IO_Read_Direct(sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *data) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - SDMMCHOST_TRANSFER content = {0U}; - SDMMCHOST_COMMAND command = {0U}; - - command.index = kSDIO_RWIODirect; - command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | - ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS); - command.responseType = kCARD_ResponseTypeR5; - command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | - kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); - - content.command = &command; - content.data = NULL; - - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* read data from response */ - *data = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; - - return kStatus_Success; -} - -status_t SDIO_IO_RW_Direct(sdio_card_t *card, - sdio_io_direction_t direction, - sdio_func_num_t func, - uint32_t regAddr, - uint8_t dataIn, - uint8_t *dataOut) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - SDMMCHOST_TRANSFER content = {0U}; - SDMMCHOST_COMMAND command = {0U}; - - command.index = kSDIO_RWIODirect; - command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | - ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS); - - if ((dataOut != NULL) && (direction == kSDIO_IOWrite)) - { - command.argument |= (1U << SDIO_CMD_ARGUMENT_RW_POS) | (1U << SDIO_DIRECT_CMD_ARGUMENT_RAW_POS); - } - - if (direction == kSDIO_IOWrite) - { - command.argument |= dataIn & SDIO_DIRECT_CMD_DATA_MASK; - } - - command.responseType = kCARD_ResponseTypeR5; - command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | - kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); - - command.responseType = kCARD_ResponseTypeR5; - command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | - kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); - - content.command = &command; - content.data = NULL; - - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - if (dataOut != NULL) - { - /* read data from response */ - *dataOut = command.response[0U] & SDIO_DIRECT_CMD_DATA_MASK; - } - - return kStatus_Success; -} - -status_t SDIO_IO_Write_Extended( - sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) -{ - assert(card); - assert(buffer); - assert(func <= kSDIO_FunctionNum7); - - SDMMCHOST_TRANSFER content = {0U}; - SDMMCHOST_COMMAND command = {0U}; - SDMMCHOST_DATA data = {0U}; - bool blockMode = false; - bool opCode = false; - - /* check if card support block mode */ - if ((card->cccrflags & kSDIO_CCCRSupportMultiBlock) && (flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK)) - { - blockMode = true; - } - - if (flags & SDIO_EXTEND_CMD_OP_CODE_MASK) - { - opCode = true; - } - - /* check the byte size counter in non-block mode - * so you need read CIS for each function first,before you do read/write - */ - if (!blockMode) - { - if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && - (count > card->commonCIS.fn0MaxBlkSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && - (count > card->funcCIS[func - 1U].ioMaxBlockSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - } - - command.index = kSDIO_RWIOExtended; - command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | - ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | - (1U << SDIO_CMD_ARGUMENT_RW_POS) | (count & SDIO_EXTEND_CMD_COUNT_MASK) | - ((blockMode ? 1 : 0) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | - ((opCode ? 1 : 0) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); - command.responseType = kCARD_ResponseTypeR5; - command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | - kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); - - if (blockMode) - { - if (func == kSDIO_FunctionNum0) - { - data.blockSize = card->io0blockSize; - } - else - { - data.blockSize = card->ioFBR[func - 1U].ioBlockSize; - } - data.blockCount = count; - } - else - { - data.blockSize = count; - data.blockCount = 1U; - } - data.txData = (uint32_t *)buffer; - - content.command = &command; - content.data = &data; - - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDIO_IO_Read_Extended( - sdio_card_t *card, sdio_func_num_t func, uint32_t regAddr, uint8_t *buffer, uint32_t count, uint32_t flags) -{ - assert(card); - assert(buffer); - assert(func <= kSDIO_FunctionNum7); - - SDMMCHOST_TRANSFER content = {0U}; - SDMMCHOST_COMMAND command = {0U}; - SDMMCHOST_DATA data = {0U}; - bool blockMode = false; - bool opCode = false; - - /* check if card support block mode */ - if ((card->cccrflags & kSDIO_CCCRSupportMultiBlock) && (flags & SDIO_EXTEND_CMD_BLOCK_MODE_MASK)) - { - blockMode = true; - } - - /* op code =0 : read/write to fixed addr - * op code =1 :read/write addr incrementing - */ - if (flags & SDIO_EXTEND_CMD_OP_CODE_MASK) - { - opCode = true; - } - - /* check the byte size counter in non-block mode - * so you need read CIS for each function first,before you do read/write - */ - if (!blockMode) - { - if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && - (count > card->commonCIS.fn0MaxBlkSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && - (count > card->funcCIS[func - 1U].ioMaxBlockSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - } - - command.index = kSDIO_RWIOExtended; - command.argument = (func << SDIO_CMD_ARGUMENT_FUNC_NUM_POS) | - ((regAddr & SDIO_CMD_ARGUMENT_REG_ADDR_MASK) << SDIO_CMD_ARGUMENT_REG_ADDR_POS) | - (count & SDIO_EXTEND_CMD_COUNT_MASK) | - ((blockMode ? 1U : 0U) << SDIO_EXTEND_CMD_ARGUMENT_BLOCK_MODE_POS | - ((opCode ? 1U : 0U) << SDIO_EXTEND_CMD_ARGUMENT_OP_CODE_POS)); - command.responseType = kCARD_ResponseTypeR5; - command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | - kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); - - if (blockMode) - { - if (func == kSDIO_FunctionNum0) - { - data.blockSize = card->io0blockSize; - } - else - { - data.blockSize = card->ioFBR[func - 1U].ioBlockSize; - } - data.blockCount = count; - } - else - { - data.blockSize = count; - data.blockCount = 1U; - } - data.rxData = (uint32_t *)buffer; - - content.command = &command; - content.data = &data; - - if (kStatus_Success != card->host.transfer(card->host.base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDIO_IO_Transfer(sdio_card_t *card, - sdio_command_t cmd, - uint32_t argument, - uint32_t blockSize, - uint8_t *txData, - uint8_t *rxData, - uint16_t dataSize, - uint32_t *response) -{ - assert(card != NULL); - - uint32_t actualSize = dataSize; - SDMMCHOST_TRANSFER content = {0U}; - SDMMCHOST_COMMAND command = {0U}; - SDMMCHOST_DATA data = {0U}; - uint32_t i = SDIO_RETRY_TIMES; - uint32_t *dataAddr = (uint32_t *)(txData == NULL ? rxData : txData); - - if ((dataSize != 0U) && (txData != NULL) && (rxData != NULL)) - { - return kStatus_InvalidArgument; - } - - command.index = cmd; - command.argument = argument; - command.responseType = kCARD_ResponseTypeR5; - command.responseErrorFlags = (kSDIO_StatusCmdCRCError | kSDIO_StatusIllegalCmd | kSDIO_StatusError | - kSDIO_StatusFunctionNumError | kSDIO_StatusOutofRange); - content.command = &command; - content.data = NULL; - - if (dataSize) - { - /* if block size bigger than 1, then use block mode */ - if (argument & SDIO_EXTEND_CMD_BLOCK_MODE_MASK) - { - if (dataSize % blockSize != 0) - { - actualSize = ((dataSize / blockSize) + 1) * blockSize; - } - - data.blockCount = actualSize / blockSize; - data.blockSize = blockSize; - } - else - { - data.blockCount = 1; - data.blockSize = dataSize; - } - /* if data buffer address can not meet host controller internal DMA requirement, sdio driver will try to use - * internal align buffer if data size is not bigger than internal buffer size, - * Align address transfer always can get a better performance, so if you want sdio driver make buffer address - * align, you should - * redefine the SDMMC_GLOBAL_BUFFER_SIZE macro to a value which is big enough for your application. - */ - if (((uint32_t)dataAddr & (SDMMCHOST_DMA_BUFFER_ADDR_ALIGN - 1U)) && - (actualSize <= (SDMMC_GLOBAL_BUFFER_SIZE * sizeof(uint32_t))) && (!card->noInternalAlign)) - { - dataAddr = (uint32_t *)g_sdmmc; - memset(g_sdmmc, 0U, actualSize); - if (txData) - { - memcpy(g_sdmmc, txData, dataSize); - } - } - - if (rxData) - { - data.rxData = dataAddr; - } - else - { - data.txData = dataAddr; - } - - content.data = &data; - } - - do - { - if (kStatus_Success == card->host.transfer(card->host.base, &content)) - { - if ((rxData != NULL) && ((uint32_t)rxData & (SDMMCHOST_DMA_BUFFER_ADDR_ALIGN - 1U)) && - (actualSize <= (SDMMC_GLOBAL_BUFFER_SIZE * sizeof(uint32_t))) && (!card->noInternalAlign)) - { - memcpy(rxData, g_sdmmc, dataSize); - } - - if (response != NULL) - { - *response = command.response[0]; - } - - return kStatus_Success; - } - - } while (i--); - - return kStatus_Fail; -} - -status_t SDIO_GetCardCapability(sdio_card_t *card, sdio_func_num_t func) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - uint8_t *tempBuffer = (uint8_t *)g_sdmmc; - uint32_t i = 0U; - - memset(g_sdmmc, 0U, sizeof(g_sdmmc)); - - for (i = 0U; i <= SDIO_CCCR_REG_NUMBER; i++) - { - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, SDIO_FBR_BASE(func) + i, 0U, &tempBuffer[i])) - { - return kStatus_SDMMC_TransferFailed; - } - } - - switch (func) - { - case kSDIO_FunctionNum0: - - card->sdVersion = tempBuffer[kSDIO_RegSDVersion]; - card->sdioVersion = tempBuffer[kSDIO_RegCCCRSdioVer] >> 4U; - card->cccrVersioin = tempBuffer[kSDIO_RegCCCRSdioVer] & 0xFU; - /* continuous SPI interrupt */ - if (tempBuffer[kSDIO_RegBusInterface] & 0x40U) - { - card->cccrflags |= kSDIO_CCCRSupportContinuousSPIInt; - } - /* 8bit data bus */ - if (tempBuffer[kSDIO_RegBusInterface] & 0x4U) - { - card->cccrflags |= SDIO_CCCR_SUPPORT_8BIT_BUS; - } - - /* card capability register */ - card->cccrflags |= (tempBuffer[kSDIO_RegCardCapability] & 0xDFU); - /* master power control */ - if (tempBuffer[kSDIO_RegPowerControl] & 0x01U) - { - card->cccrflags |= kSDIO_CCCRSupportMasterPowerControl; - } - /* high speed flag */ - if (tempBuffer[kSDIO_RegBusSpeed] & 0x01U) - { - card->cccrflags |= SDIO_CCCR_SUPPORT_HIGHSPEED; - } - /* uhs mode flag */ - card->cccrflags |= (tempBuffer[kSDIO_RegUHSITimingSupport] & 7U) << 11U; - /* driver type flag */ - card->cccrflags |= (tempBuffer[kSDIO_RegDriverStrength] & 7U) << 14U; - /* low speed 4bit */ - if (tempBuffer[kSDIO_RegCardCapability] & 0x80U) - { - card->cccrflags |= kSDIO_CCCRSupportLowSpeed4Bit; - } - /* common CIS pointer */ - card->commonCISPointer = tempBuffer[kSDIO_RegCommonCISPointer] | - (tempBuffer[kSDIO_RegCommonCISPointer + 1U] << 8U) | - (tempBuffer[kSDIO_RegCommonCISPointer + 2U] << 16U); - - /* check card capability of support async interrupt */ - if ((tempBuffer[kSDIO_RegInterruptExtension] & SDIO_CCCR_ASYNC_INT_MASK) == SDIO_CCCR_ASYNC_INT_MASK) - { - card->cccrflags |= SDIO_CCCR_SUPPORT_ASYNC_INT; - } - - break; - - case kSDIO_FunctionNum1: - case kSDIO_FunctionNum2: - case kSDIO_FunctionNum3: - case kSDIO_FunctionNum4: - case kSDIO_FunctionNum5: - case kSDIO_FunctionNum6: - case kSDIO_FunctionNum7: - card->ioFBR[func - 1U].ioStdFunctionCode = tempBuffer[0U] & 0x0FU; - card->ioFBR[func - 1U].ioExtFunctionCode = tempBuffer[1U]; - card->ioFBR[func - 1U].ioPointerToCIS = tempBuffer[9U] | (tempBuffer[10U] << 8U) | (tempBuffer[11U] << 16U); - card->ioFBR[func - 1U].ioPointerToCSA = - tempBuffer[12U] | (tempBuffer[13U] << 8U) | (tempBuffer[14U] << 16U); - if (tempBuffer[2U] & 0x01U) - { - card->ioFBR[func - 1U].flags |= kSDIO_FBRSupportPowerSelection; - } - if (tempBuffer[0U] & 0x40U) - { - card->ioFBR[func - 1U].flags |= kSDIO_FBRSupportCSA; - } - - break; - - default: - break; - } - - return kStatus_Success; -} - -status_t SDIO_SetBlockSize(sdio_card_t *card, sdio_func_num_t func, uint32_t blockSize) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - assert(blockSize <= SDIO_MAX_BLOCK_SIZE); - - uint8_t temp = 0U; - - /* check the block size for block mode - * so you need read CIS for each function first,before you do read/write - */ - if ((func == kSDIO_FunctionNum0) && (card->commonCIS.fn0MaxBlkSize != 0U) && - (blockSize > card->commonCIS.fn0MaxBlkSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - else if ((func != kSDIO_FunctionNum0) && (card->funcCIS[func - 1U].ioMaxBlockSize != 0U) && - (blockSize > card->funcCIS[func - 1U].ioMaxBlockSize)) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - - temp = blockSize & 0xFFU; - - if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, - SDIO_FBR_BASE(func) + kSDIO_RegFN0BlockSizeLow, temp, &temp)) - { - return kStatus_SDMMC_SetCardBlockSizeFailed; - } - - temp = (blockSize >> 8U) & 0xFFU; - - if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, - SDIO_FBR_BASE(func) + kSDIO_RegFN0BlockSizeHigh, temp, &temp)) - { - return kStatus_SDMMC_SetCardBlockSizeFailed; - } - - /* record the current block size */ - if (func == kSDIO_FunctionNum0) - { - card->io0blockSize = blockSize; - } - else - { - card->ioFBR[func - 1U].ioBlockSize = blockSize; - } - - return kStatus_Success; -} - -status_t SDIO_CardReset(sdio_card_t *card) -{ - return SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOAbort, 0x08U, NULL); -} - -status_t SDIO_SetDataBusWidth(sdio_card_t *card, sdio_bus_width_t busWidth) -{ - assert(card); - - uint8_t regBusInterface = 0U; - - if (((busWidth == kSDIO_DataBus4Bit) && ((card->cccrflags & kSDIO_CCCRSupportHighSpeed) == 0U) && - ((card->cccrflags & kSDIO_CCCRSupportLowSpeed4Bit) == 0U)) || - (((SDMMCHOST_NOT_SUPPORT == kSDMMCHOST_Support8BitBusWidth) || - ((card->cccrflags & SDIO_CCCR_SUPPORT_8BIT_BUS) == 0U)) && - (busWidth == kSDIO_DataBus8Bit))) - { - return kStatus_SDMMC_SDIO_InvalidArgument; - } - - /* load bus interface register */ - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegBusInterface, 0U, ®BusInterface)) - { - return kStatus_SDMMC_TransferFailed; - } - /* set bus width */ - regBusInterface &= 0xFCU; - regBusInterface |= busWidth; - - /* write to register */ - if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegBusInterface, - regBusInterface, ®BusInterface)) - { - return kStatus_SDMMC_TransferFailed; - } - - if (busWidth == kSDIO_DataBus8Bit) - { - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH8BIT); - } - else if (busWidth == kSDIO_DataBus4Bit) - { - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH4BIT); - } - else - { - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); - } - - return kStatus_Success; -} - -static status_t SDIO_SetMaxDataBusWidth(sdio_card_t *card) -{ - sdio_bus_width_t busWidth = kSDIO_DataBus1Bit; - - if ((SDMMCHOST_NOT_SUPPORT != kSDMMCHOST_Support8BitBusWidth) && - ((card->cccrflags & SDIO_CCCR_SUPPORT_8BIT_BUS) != 0U)) - { - busWidth = kSDIO_DataBus8Bit; - } - - /* switch data bus width */ - if (((card->cccrflags & kSDIO_CCCRSupportHighSpeed) || ((card->cccrflags & kSDIO_CCCRSupportLowSpeed4Bit) != 0U)) && - (busWidth == kSDIO_DataBus1Bit)) - { - busWidth = kSDIO_DataBus4Bit; - } - - return SDIO_SetDataBusWidth(card, busWidth); -} - -status_t SDIO_SwitchToHighSpeed(sdio_card_t *card) -{ - assert(card); - - uint8_t temp = 0U; - uint32_t retryTimes = SDIO_RETRY_TIMES; - status_t status = kStatus_SDMMC_SDIO_SwitchHighSpeedFail; - - if (card->cccrflags & SDIO_CCCR_SUPPORT_HIGHSPEED) - { - if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, 0U, &temp)) - { - return kStatus_SDMMC_TransferFailed; - } - - temp &= ~SDIO_CCCR_BUS_SPEED_MASK; - temp |= SDIO_CCCR_ENABLE_HIGHSPEED_MODE; - - do - { - retryTimes--; - /* enable high speed mode */ - - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, temp, &temp)) - { - continue; - } - /* either EHS=0 and SHS=0 ,the card is still in default mode */ - if ((temp & 0x03U) == 0x03U) - { - /* high speed mode , set freq to 50MHZ */ - card->busClock_Hz = - SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_50MHZ); - status = kStatus_Success; - break; - } - else - { - continue; - } - - } while (retryTimes); - } - else - { - /* default mode 25MHZ */ - card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SD_CLOCK_25MHZ); - status = kStatus_Success; - } - - return status; -} - -static status_t SDIO_SelectBusTiming(sdio_card_t *card) -{ - assert(card); - - uint32_t targetBusFreq = SD_CLOCK_25MHZ; - uint32_t targetTiming = 0U; - uint8_t temp = 0U; - uint32_t supportModeFlag = 0U; - - do - { - switch (card->currentTiming) - { - /* if not select timing mode, sdmmc will handle it automatically*/ - case kSD_TimingSDR12DefaultMode: - case kSD_TimingSDR104Mode: - if ((kSDMMCHOST_SupportSDR104 != SDMMCHOST_NOT_SUPPORT) && - ((card->cccrflags & SDIO_CCCR_SUPPORT_SDR104) == SDIO_CCCR_SUPPORT_SDR104)) - { - card->currentTiming = kSD_TimingSDR104Mode; - targetTiming = SDIO_CCCR_ENABLE_SDR104_MODE; - targetBusFreq = SDMMCHOST_SUPPORT_SDR104_FREQ; - supportModeFlag = SDIO_CCCR_SUPPORT_SDR104; - break; - } - - case kSD_TimingDDR50Mode: - if ((kSDMMCHOST_SupportDDR50 != SDMMCHOST_NOT_SUPPORT) && - ((card->cccrflags & SDIO_CCCR_SUPPORT_DDR50) == SDIO_CCCR_SUPPORT_DDR50)) - { - card->currentTiming = kSD_TimingDDR50Mode; - targetTiming = SDIO_CCCR_ENABLE_DDR50_MODE; - targetBusFreq = SD_CLOCK_50MHZ; - supportModeFlag = SDIO_CCCR_SUPPORT_DDR50; - break; - } - - case kSD_TimingSDR50Mode: - if ((kSDMMCHOST_SupportSDR50 != SDMMCHOST_NOT_SUPPORT) && - ((card->cccrflags & SDIO_CCCR_SUPPORT_SDR50) == SDIO_CCCR_SUPPORT_SDR50)) - { - card->currentTiming = kSD_TimingSDR50Mode; - targetTiming = SDIO_CCCR_ENABLE_SDR50_MODE; - targetBusFreq = SD_CLOCK_100MHZ; - supportModeFlag = SDIO_CCCR_SUPPORT_SDR50; - break; - } - - case kSD_TimingSDR25HighSpeedMode: - if ((card->host.capability.flags & kSDMMCHOST_SupportHighSpeed) && - (card->cccrflags & SDIO_CCCR_SUPPORT_HIGHSPEED) == SDIO_CCCR_SUPPORT_HIGHSPEED) - { - card->currentTiming = kSD_TimingSDR25HighSpeedMode; - targetTiming = SDIO_CCCR_ENABLE_HIGHSPEED_MODE; - targetBusFreq = SD_CLOCK_50MHZ; - supportModeFlag = SDIO_CCCR_SUPPORT_HIGHSPEED; - break; - } - - default: - /* default timing mode */ - card->currentTiming = kSD_TimingSDR12DefaultMode; - return kStatus_Success; - } - - if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, 0U, &temp)) - { - return kStatus_SDMMC_TransferFailed; - } - - temp &= ~SDIO_CCCR_BUS_SPEED_MASK; - temp |= targetTiming; - - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegBusSpeed, temp, &temp)) - { - return kStatus_SDMMC_TransferFailed; - } - /* if cannot switch target timing, it will switch continuously until find a valid timing. */ - if ((temp & targetTiming) != targetTiming) - { - /* need add error log here */ - card->cccrflags &= ~supportModeFlag; - continue; - } - - break; - } while (1); - - card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, targetBusFreq); - - /* enable DDR mode if it is the target mode */ - if (card->currentTiming == kSD_TimingDDR50Mode) - { - SDMMCHOST_ENABLE_DDR_MODE(card->host.base, true, 0U); - } - - /* SDR50 and SDR104 mode need tuning */ - if ((card->currentTiming == kSD_TimingSDR50Mode) || (card->currentTiming == kSD_TimingSDR104Mode)) - { - /* config IO strength in IOMUX*/ - if (card->currentTiming == kSD_TimingSDR50Mode) - { - SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_7); - } - else - { - SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_200MHZ, CARD_BUS_STRENGTH_7); - } - /* execute tuning */ - if (SDIO_ExecuteTuning(card) != kStatus_Success) - { - return kStatus_SDMMC_TuningFail; - } - } - else - { - /* set default IO strength to 4 to cover card adapter driver strength difference */ - SDMMCHOST_CONFIG_SD_IO(CARD_BUS_FREQ_100MHZ1, CARD_BUS_STRENGTH_4); - } - - return kStatus_Success; -} - -status_t SDIO_SetDriverStrength(sdio_card_t *card, sd_driver_strength_t driverStrength) -{ - uint8_t strength = 0U, temp = 0U; - - switch (driverStrength) - { - case kSD_DriverStrengthTypeA: - strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_A; - break; - case kSD_DriverStrengthTypeC: - strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_C; - break; - case kSD_DriverStrengthTypeD: - strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_D; - break; - default: - strength = SDIO_CCCR_ENABLE_DRIVER_TYPE_B; - break; - } - - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegDriverStrength, 0U, &temp)) - { - return kStatus_SDMMC_TransferFailed; - } - - temp &= ~SDIO_CCCR_DRIVER_TYPE_MASK; - temp |= strength; - - return SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegDriverStrength, temp, &temp); -} - -status_t SDIO_EnableAsyncInterrupt(sdio_card_t *card, bool enable) -{ - assert(card); - - uint8_t eai = 0U; - - if ((card->cccrflags & SDIO_CCCR_SUPPORT_ASYNC_INT) == 0U) - { - return kStatus_SDMMC_NotSupportYet; - } - - /* load interrupt enable register */ - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegInterruptExtension, 0U, &eai)) - { - return kStatus_SDMMC_TransferFailed; - } - /* if already enable/disable , do not need enable/disable again */ - if (((eai)&SDIO_CCCR_ENABLE_AYNC_INT) == (enable ? SDIO_CCCR_ENABLE_AYNC_INT : 0U)) - { - return kStatus_Success; - } - - /* enable the eai */ - if (enable) - { - eai |= SDIO_CCCR_ENABLE_AYNC_INT; - } - else - { - eai &= ~(SDIO_CCCR_ENABLE_AYNC_INT); - } - - /* write to register */ - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegInterruptExtension, eai, &eai)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -static status_t SDIO_DecodeCIS( - sdio_card_t *card, sdio_func_num_t func, uint8_t *dataBuffer, uint32_t tplCode, uint32_t tplLink) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - if (func == kSDIO_FunctionNum0) - { - /* only decode MANIFID,FUNCID,FUNCE here */ - if (tplCode == SDIO_TPL_CODE_MANIFID) - { - card->commonCIS.mID = dataBuffer[0U] | (dataBuffer[1U] << 8U); - card->commonCIS.mInfo = dataBuffer[2U] | (dataBuffer[3U] << 8U); - } - else if (tplCode == SDIO_TPL_CODE_FUNCID) - { - card->commonCIS.funcID = dataBuffer[0U]; - } - else if (tplCode == SDIO_TPL_CODE_FUNCE) - { - /* max transfer block size and data size */ - card->commonCIS.fn0MaxBlkSize = dataBuffer[1U] | (dataBuffer[2U] << 8U); - /* max transfer speed */ - card->commonCIS.maxTransSpeed = dataBuffer[3U]; - } - else - { - /* reserved here */ - return kStatus_Fail; - } - } - else - { - /* only decode FUNCID,FUNCE here */ - if (tplCode == SDIO_TPL_CODE_FUNCID) - { - card->funcCIS[func].funcID = dataBuffer[0U]; - } - else if (tplCode == SDIO_TPL_CODE_FUNCE) - { - if (tplLink == 0x2A) - { - card->funcCIS[func - 1U].funcInfo = dataBuffer[1U]; - card->funcCIS[func - 1U].ioVersion = dataBuffer[2U]; - card->funcCIS[func - 1U].cardPSN = - dataBuffer[3U] | (dataBuffer[4U] << 8U) | (dataBuffer[5U] << 16U) | (dataBuffer[6U] << 24U); - card->funcCIS[func - 1U].ioCSASize = - dataBuffer[7U] | (dataBuffer[8U] << 8U) | (dataBuffer[9U] << 16U) | (dataBuffer[10U] << 24U); - card->funcCIS[func - 1U].ioCSAProperty = dataBuffer[11U]; - card->funcCIS[func - 1U].ioMaxBlockSize = dataBuffer[12U] | (dataBuffer[13U] << 8U); - card->funcCIS[func - 1U].ioOCR = - dataBuffer[14U] | (dataBuffer[15U] << 8U) | (dataBuffer[16U] << 16U) | (dataBuffer[17U] << 24U); - card->funcCIS[func - 1U].ioOPMinPwr = dataBuffer[18U]; - card->funcCIS[func - 1U].ioOPAvgPwr = dataBuffer[19U]; - card->funcCIS[func - 1U].ioOPMaxPwr = dataBuffer[20U]; - card->funcCIS[func - 1U].ioSBMinPwr = dataBuffer[21U]; - card->funcCIS[func - 1U].ioSBAvgPwr = dataBuffer[22U]; - card->funcCIS[func - 1U].ioSBMaxPwr = dataBuffer[23U]; - card->funcCIS[func - 1U].ioMinBandWidth = dataBuffer[24U] | (dataBuffer[25U] << 8U); - card->funcCIS[func - 1U].ioOptimumBandWidth = dataBuffer[26U] | (dataBuffer[27U] << 8U); - card->funcCIS[func - 1U].ioReadyTimeout = dataBuffer[28U] | (dataBuffer[29U] << 8U); - - card->funcCIS[func - 1U].ioHighCurrentAvgCurrent = dataBuffer[34U] | (dataBuffer[35U] << 8U); - card->funcCIS[func - 1U].ioHighCurrentMaxCurrent = dataBuffer[36U] | (dataBuffer[37U] << 8U); - card->funcCIS[func - 1U].ioLowCurrentAvgCurrent = dataBuffer[38U] | (dataBuffer[39U] << 8U); - card->funcCIS[func - 1U].ioLowCurrentMaxCurrent = dataBuffer[40U] | (dataBuffer[41U] << 8U); - } - else - { - return kStatus_Fail; - } - } - else - { - return kStatus_Fail; - } - } - - return kStatus_Success; -} - -status_t SDIO_ReadCIS(sdio_card_t *card, sdio_func_num_t func, const uint32_t *tupleList, uint32_t tupleNum) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - assert(tupleList); - - uint8_t tplCode = 0U; - uint8_t tplLink = 0U; - uint32_t cisPtr = 0U; - uint32_t i = 0U, num = 0U; - bool tupleMatch = false; - - uint8_t dataBuffer[255U] = {0U}; - - /* get the CIS pointer for each function */ - if (func == kSDIO_FunctionNum0) - { - cisPtr = card->commonCISPointer; - } - else - { - cisPtr = card->ioFBR[func - 1U].ioPointerToCIS; - } - - if (0U == cisPtr) - { - return kStatus_SDMMC_SDIO_ReadCISFail; - } - - do - { - if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, cisPtr++, 0U, &tplCode)) - { - return kStatus_SDMMC_TransferFailed; - } - /* end of chain tuple */ - if (tplCode == 0xFFU) - { - break; - } - - if (tplCode == 0U) - { - continue; - } - - for (i = 0; i < tupleNum; i++) - { - if (tplCode == tupleList[i]) - { - tupleMatch = true; - break; - } - } - - if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, cisPtr++, 0U, &tplLink)) - { - return kStatus_SDMMC_TransferFailed; - } - /* end of chain tuple */ - if (tplLink == 0xFFU) - { - break; - } - - if (tupleMatch) - { - memset(dataBuffer, 0U, 255U); - for (i = 0; i < tplLink; i++) - { - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, cisPtr++, 0U, &dataBuffer[i])) - { - return kStatus_SDMMC_TransferFailed; - } - } - tupleMatch = false; - /* pharse the data */ - SDIO_DecodeCIS(card, func, dataBuffer, tplCode, tplLink); - /* read finish then return */ - if (++num == tupleNum) - { - break; - } - } - else - { - /* move pointer */ - cisPtr += tplLink; - /* tuple code not match,continue read tuple code */ - continue; - } - } while (1); - return kStatus_Success; -} - -static status_t SDIO_ProbeBusVoltage(sdio_card_t *card) -{ - assert(card); - - uint32_t ocr = 0U; - status_t error = kStatus_Success; - - /* application able to set the supported voltage window */ - if ((card->ocr & SDIO_OCR_VOLTAGE_WINDOW_MASK) != 0U) - { - ocr = card->ocr & SDIO_OCR_VOLTAGE_WINDOW_MASK; - } - else - { - /* 3.3V voltage should be supported as default */ - ocr |= SDMMC_MASK(kSD_OcrVdd29_30Flag) | SDMMC_MASK(kSD_OcrVdd32_33Flag) | SDMMC_MASK(kSD_OcrVdd33_34Flag); - } - - /* allow user select the work voltage, if not select, sdmmc will handle it automatically */ - if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) - { - ocr |= SDMMC_MASK(kSD_OcrSwitch18RequestFlag); - } - - do - { - /* card go idle */ - if (kStatus_Success != SDIO_GoIdle(card)) - { - return kStatus_SDMMC_GoIdleFailed; - } - - /* Get IO OCR-CMD5 with arg0 ,set new voltage if needed*/ - if (kStatus_Success != SDIO_SendOperationCondition(card, 0U)) - { - return kStatus_SDMMC_HandShakeOperationConditionFailed; - } - - if (kStatus_Success != SDIO_SendOperationCondition(card, ocr)) - { - return kStatus_SDMMC_InvalidVoltage; - } - - /* check if card support 1.8V */ - if ((card->ocr & SDMMC_MASK(kSD_OcrSwitch18AcceptFlag)) != 0U) - { - error = SDIO_SwitchVoltage(card); - if (kStatus_SDMMC_SwitchVoltageFail == error) - { - break; - } - - if (error == kStatus_SDMMC_SwitchVoltage18VFail33VSuccess) - { - ocr &= ~SDMMC_MASK(kSD_OcrSwitch18RequestFlag); - error = kStatus_Success; - continue; - } - else - { - card->operationVoltage = kCARD_OperationVoltage180V; - break; - } - } - - break; - } while (1U); - - return error; -} - -status_t SDIO_CardInit(sdio_card_t *card) -{ - assert(card); - - if (!card->isHostReady) - { - return kStatus_SDMMC_HostNotReady; - } - /* Identify mode ,set clock to 400KHZ. */ - card->busClock_Hz = SDMMCHOST_SET_CARD_CLOCK(card->host.base, card->host.sourceClock_Hz, SDMMC_CLOCK_400KHZ); - SDMMCHOST_SET_CARD_BUS_WIDTH(card->host.base, kSDMMCHOST_DATABUSWIDTH1BIT); - SDMMCHOST_SEND_CARD_ACTIVE(card->host.base, 100U); - - /* get host capability */ - GET_SDMMCHOST_CAPABILITY(card->host.base, &(card->host.capability)); - - if (SDIO_ProbeBusVoltage(card) != kStatus_Success) - { - return kStatus_SDMMC_SwitchVoltageFail; - } - - /* there is a memonly card */ - if ((card->ioTotalNumber == 0U) && (card->memPresentFlag)) - { - return kStatus_SDMMC_SDIO_InvalidCard; - } - - /* send relative address ,cmd3*/ - if (kStatus_Success != SDIO_SendRca(card)) - { - return kStatus_SDMMC_SendRelativeAddressFailed; - } - /* select card cmd7 */ - if (kStatus_Success != SDIO_SelectCard(card, true)) - { - return kStatus_SDMMC_SelectCardFailed; - } - - /* get card capability */ - if (kStatus_Success != SDIO_GetCardCapability(card, kSDIO_FunctionNum0)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* read common CIS here */ - if (SDIO_ReadCIS(card, kSDIO_FunctionNum0, g_tupleList, SDIO_COMMON_CIS_TUPLE_NUM)) - { - return kStatus_SDMMC_SDIO_ReadCISFail; - } - - /* switch data bus width */ - if (kStatus_Success != SDIO_SetMaxDataBusWidth(card)) - { - return kStatus_SDMMC_SetDataBusWidthFailed; - } - - /* trying switch to card support timing mode. */ - if (kStatus_Success != SDIO_SelectBusTiming(card)) - { - return kStatus_SDMMC_SDIO_SwitchHighSpeedFail; - } - - return kStatus_Success; -} - -void SDIO_CardDeinit(sdio_card_t *card) -{ - assert(card); - - SDIO_CardReset(card); - SDIO_SelectCard(card, false); -} - -status_t SDIO_HostInit(sdio_card_t *card) -{ - assert(card); - - if ((!card->isHostReady) && SDMMCHOST_Init(&(card->host), (void *)(&(card->usrParam))) != kStatus_Success) - { - return kStatus_Fail; - } - - /* set the host status flag, after the card re-plug in, don't need init host again */ - card->isHostReady = true; - - SDMMCHOST_ENABLE_SDIO_INT(card->host.base); - - return kStatus_Success; -} - -void SDIO_HostDeinit(sdio_card_t *card) -{ - assert(card); - - SDMMCHOST_Deinit(&(card->host)); - - /* should re-init host */ - card->isHostReady = false; -} - -void SDIO_HostReset(SDMMCHOST_CONFIG *host) -{ - SDMMCHOST_Reset(host->base); -} - -status_t SDIO_WaitCardDetectStatus(SDMMCHOST_TYPE *hostBase, const sdmmchost_detect_card_t *cd, bool waitCardStatus) -{ - return SDMMCHOST_WaitCardDetectStatus(hostBase, cd, waitCardStatus); -} - -bool SDIO_IsCardPresent(sdio_card_t *card) -{ - return SDMMCHOST_IsCardPresent(); -} - -void SDIO_PowerOnCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - SDMMCHOST_PowerOnCard(base, pwr); -} - -void SDIO_PowerOffCard(SDMMCHOST_TYPE *base, const sdmmchost_pwr_card_t *pwr) -{ - SDMMCHOST_PowerOffCard(base, pwr); -} - -status_t SDIO_Init(sdio_card_t *card) -{ - assert(card); - assert(card->host.base); - - if (!card->isHostReady) - { - if (SDIO_HostInit(card) != kStatus_Success) - { - return kStatus_SDMMC_HostNotReady; - } - } - else - { - /* reset the host */ - SDIO_HostReset(&(card->host)); - } - /* power off card */ - SDIO_PowerOffCard(card->host.base, card->usrParam.pwr); - /* card detect */ - if (SDIO_WaitCardDetectStatus(card->host.base, card->usrParam.cd, true) != kStatus_Success) - { - return kStatus_SDMMC_CardDetectFailed; - } - /* power on card */ - SDIO_PowerOnCard(card->host.base, card->usrParam.pwr); - - return SDIO_CardInit(card); -} - -void SDIO_Deinit(sdio_card_t *card) -{ - assert(card); - - SDIO_CardDeinit(card); - SDIO_HostDeinit(card); -} - -status_t SDIO_EnableIOInterrupt(sdio_card_t *card, sdio_func_num_t func, bool enable) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - uint8_t intEn = 0U; - - /* load io interrupt enable register */ - if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, 0U, &intEn)) - { - return kStatus_SDMMC_TransferFailed; - } - - if (enable) - { - /* if already enable , do not need enable again */ - if ((((intEn >> func) & 0x01U) == 0x01U) && (intEn & 0x01U)) - { - return kStatus_Success; - } - - /* enable the interrupt and interrupt master */ - intEn |= (1U << func) | 0x01U; - card->ioIntNums++; - } - else - { - /* if already disable , do not need enable again */ - if (((intEn >> func) & 0x01U) == 0x00U) - { - return kStatus_Success; - } - - /* disable the interrupt, don't disable the interrupt master here */ - intEn &= ~(1U << func); - if (card->ioIntNums) - { - card->ioIntNums--; - } - } - - /* write to register */ - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOIntEnable, intEn, &intEn)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDIO_GetPendingInterrupt(sdio_card_t *card, uint8_t *pendingInt) -{ - assert(card); - - /* load io interrupt enable register */ - - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOIntPending, 0U, pendingInt)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDIO_EnableIO(sdio_card_t *card, sdio_func_num_t func, bool enable) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - assert(func != kSDIO_FunctionNum0); - - uint8_t ioEn = 0U, ioReady = 0U; - volatile uint32_t i = SDIO_RETRY_TIMES; - uint32_t ioReadyTimeoutMS = card->funcCIS[func - 1U].ioReadyTimeout * SDIO_IO_READY_TIMEOUT_UNIT; - - if (ioReadyTimeoutMS != 0U) - { - /* do not poll the IO ready status, but use IO ready timeout */ - i = 1U; - } - - /* load io enable register */ - if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOEnable, 0U, &ioEn)) - { - return kStatus_SDMMC_TransferFailed; - } - /* if already enable/disable , do not need enable/disable again */ - if (((ioEn >> func) & 0x01U) == (enable ? 1U : 0U)) - { - return kStatus_Success; - } - - /* enable the io */ - if (enable) - { - ioEn |= (1U << func); - } - else - { - ioEn &= ~(1U << func); - } - - /* write to register */ - if (kStatus_Success != SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOEnable, ioEn, &ioEn)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* if enable io, need check the IO ready status */ - if (enable) - { - do - { - SDMMCHOST_Delay(ioReadyTimeoutMS); - /* wait IO ready */ - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IORead, kSDIO_FunctionNum0, kSDIO_RegIOReady, 0U, &ioReady)) - { - return kStatus_SDMMC_TransferFailed; - } - /* check if IO ready */ - if ((ioReady & (1 << func)) != 0U) - { - return kStatus_Success; - } - - i--; - } while (i); - - return kStatus_Fail; - } - - return kStatus_Success; -} - -status_t SDIO_SelectIO(sdio_card_t *card, sdio_func_num_t func) -{ - assert(card); - assert(func <= kSDIO_FunctionMemory); - - uint8_t ioSel = func; - - /* write to register */ - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegFunctionSelect, ioSel, &ioSel)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDIO_AbortIO(sdio_card_t *card, sdio_func_num_t func) -{ - assert(card); - assert(func <= kSDIO_FunctionNum7); - - uint8_t ioAbort = func; - - /* write to register */ - if (kStatus_Success != - SDIO_IO_RW_Direct(card, kSDIO_IOWrite, kSDIO_FunctionNum0, kSDIO_RegIOAbort, ioAbort, &ioAbort)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -void SDIO_SetIOIRQHandler(sdio_card_t *card, sdio_func_num_t func, sdio_io_irq_handler_t handler) -{ - assert(card); - assert((func <= kSDIO_FunctionNum7) && (func != kSDIO_FunctionNum0)); - - card->ioIRQHandler[func - 1] = handler; - card->ioIntIndex = func; -} - -status_t SDIO_HandlePendingIOInterrupt(sdio_card_t *card) -{ - assert(card); - - uint8_t i = 0, pendingInt = 0; - - /* call IRQ handler directly if one IRQ handler only */ - if (card->ioIntNums == 1U) - { - if (card->ioIRQHandler[card->ioIntIndex - 1]) - { - (card->ioIRQHandler[card->ioIntIndex - 1])(card, card->ioIntIndex); - } - } - else - { - /* get pending int firstly */ - if (SDIO_GetPendingInterrupt(card, &pendingInt) != kStatus_Success) - { - return kStatus_SDMMC_TransferFailed; - } - - for (i = 1; i <= FSL_SDIO_MAX_IO_NUMS; i++) - { - if (pendingInt & (1 << i)) - { - if (card->ioIRQHandler[i - 1]) - { - (card->ioIRQHandler[i - 1])(card, i); - } - } - } - } - - return kStatus_Success; -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdmmc_common.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdmmc_common.c deleted file mode 100644 index bffccc7bc0..0000000000 --- a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/src/fsl_sdmmc_common.c +++ /dev/null @@ -1,393 +0,0 @@ -/* - * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2018 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_sdmmc_common.h" -/******************************************************************************* - * Variables - ******************************************************************************/ -SDK_ALIGN(uint32_t g_sdmmc[SDK_SIZEALIGN(SDMMC_GLOBAL_BUFFER_SIZE, SDMMC_DATA_BUFFER_ALIGN_CACHE)], - MAX(SDMMC_DATA_BUFFER_ALIGN_CACHE, SDMMCHOST_DMA_BUFFER_ADDR_ALIGN)); -/******************************************************************************* - * Code - ******************************************************************************/ -status_t SDMMC_SelectCard(SDMMCHOST_TYPE *base, - SDMMCHOST_TRANSFER_FUNCTION transfer, - uint32_t relativeAddress, - bool isSelected) -{ - assert(transfer); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - - command.index = kSDMMC_SelectCard; - if (isSelected) - { - command.argument = relativeAddress << 16U; - command.responseType = kCARD_ResponseTypeR1; - } - else - { - command.argument = 0U; - command.responseType = kCARD_ResponseTypeNone; - } - - content.command = &command; - content.data = NULL; - if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG)) - { - return kStatus_SDMMC_TransferFailed; - } - - /* Wait until card to transfer state */ - return kStatus_Success; -} - -status_t SDMMC_SendApplicationCommand(SDMMCHOST_TYPE *base, - SDMMCHOST_TRANSFER_FUNCTION transfer, - uint32_t relativeAddress) -{ - assert(transfer); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - - command.index = kSDMMC_ApplicationCommand; - command.argument = (relativeAddress << 16U); - command.responseType = kCARD_ResponseTypeR1; - - content.command = &command; - content.data = 0U; - if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG)) - { - return kStatus_SDMMC_TransferFailed; - } - - if (!(command.response[0U] & SDMMC_MASK(kSDMMC_R1ApplicationCommandFlag))) - { - return kStatus_SDMMC_CardNotSupport; - } - - return kStatus_Success; -} - -status_t SDMMC_SetBlockCount(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockCount) -{ - assert(transfer); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - - command.index = kSDMMC_SetBlockCount; - command.argument = blockCount; - command.responseType = kCARD_ResponseTypeR1; - - content.command = &command; - content.data = 0U; - if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDMMC_GoIdle(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer) -{ - assert(transfer); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - - command.index = kSDMMC_GoIdleState; - - content.command = &command; - content.data = 0U; - if (kStatus_Success != transfer(base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDMMC_SetBlockSize(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer, uint32_t blockSize) -{ - assert(transfer); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - - command.index = kSDMMC_SetBlockLength; - command.argument = blockSize; - command.responseType = kCARD_ResponseTypeR1; - - content.command = &command; - content.data = 0U; - if ((kStatus_Success != transfer(base, &content)) || (command.response[0U] & SDMMC_R1_ALL_ERROR_FLAG)) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDMMC_SetCardInactive(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer) -{ - assert(transfer); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - - command.index = kSDMMC_GoInactiveState; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeNone; - - content.command = &command; - content.data = 0U; - if ((kStatus_Success != transfer(base, &content))) - { - return kStatus_SDMMC_TransferFailed; - } - - return kStatus_Success; -} - -status_t SDMMC_SwitchVoltage(SDMMCHOST_TYPE *base, SDMMCHOST_TRANSFER_FUNCTION transfer) -{ - assert(transfer); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - status_t error = kStatus_Success; - - if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) - { - command.index = kSD_VoltageSwitch; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1; - - content.command = &command; - content.data = NULL; - if (kStatus_Success != transfer(base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - /* disable card clock */ - SDMMCHOST_ENABLE_CARD_CLOCK(base, false); - - /* check data line and cmd line status */ - if ((GET_SDMMCHOST_STATUS(base) & - (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) != 0U) - { - return kStatus_SDMMC_SwitchVoltageFail; - } - - /* host switch to 1.8V */ - SDMMCHOST_SWITCH_VOLTAGE180V(base, true); - - SDMMCHOST_Delay(100U); - - /*enable sd clock*/ - SDMMCHOST_ENABLE_CARD_CLOCK(base, true); - /*enable force clock on*/ - SDMMCHOST_FORCE_SDCLOCK_ON(base, true); - /* dealy 1ms,not exactly correct when use while */ - SDMMCHOST_Delay(10U); - /*disable force clock on*/ - SDMMCHOST_FORCE_SDCLOCK_ON(base, false); - - /* check data line and cmd line status */ - if ((GET_SDMMCHOST_STATUS(base) & - (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) == 0U) - { - error = kStatus_SDMMC_SwitchVoltageFail; - /* power reset the card */ - SDMMCHOST_ENABLE_SD_POWER(false); - SDMMCHOST_Delay(10U); - SDMMCHOST_ENABLE_SD_POWER(true); - SDMMCHOST_Delay(10U); - /* re-check the data line status */ - if ((GET_SDMMCHOST_STATUS(base) & - (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY))) - { - error = kStatus_SDMMC_SwitchVoltage18VFail33VSuccess; - SDMMC_LOG( - "\r\nNote: Current card support 1.8V, but board don't support, so sdmmc switch back to 3.3V."); - } - else - { - SDMMC_LOG( - "\r\nError: Current card support 1.8V, but board don't support, sdmmc tried to switch back\ - to 3.3V, but failed, please check board setting."); - } - } - - return error; - } - else - { - return kStatus_SDMMC_HostNotSupport; - } -} - -status_t SDMMC_SwitchToVoltage(SDMMCHOST_TYPE *base, - SDMMCHOST_TRANSFER_FUNCTION transfer, - sdmmchost_card_switch_voltage_t switchVoltageFunc) -{ - assert(transfer); - - SDMMCHOST_TRANSFER content = {0}; - SDMMCHOST_COMMAND command = {0}; - status_t error = kStatus_Success; - - if (kSDMMCHOST_SupportV180 != SDMMCHOST_NOT_SUPPORT) - { - command.index = kSD_VoltageSwitch; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1; - - content.command = &command; - content.data = NULL; - if (kStatus_Success != transfer(base, &content)) - { - return kStatus_SDMMC_TransferFailed; - } - /* disable card clock */ - SDMMCHOST_ENABLE_CARD_CLOCK(base, false); - - /* check data line and cmd line status */ - if ((GET_SDMMCHOST_STATUS(base) & - (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) != 0U) - { - return kStatus_SDMMC_SwitchVoltageFail; - } - - if (switchVoltageFunc != NULL) - { - switchVoltageFunc(); - } - else - { - /* host switch to 1.8V */ - SDMMCHOST_SWITCH_VOLTAGE180V(base, true); - } - - SDMMCHOST_Delay(100U); - - /*enable sd clock*/ - SDMMCHOST_ENABLE_CARD_CLOCK(base, true); - /*enable force clock on*/ - SDMMCHOST_FORCE_SDCLOCK_ON(base, true); - /* dealy 1ms,not exactly correct when use while */ - SDMMCHOST_Delay(10U); - /*disable force clock on*/ - SDMMCHOST_FORCE_SDCLOCK_ON(base, false); - - /* check data line and cmd line status */ - if ((GET_SDMMCHOST_STATUS(base) & - (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY)) == 0U) - { - error = kStatus_SDMMC_SwitchVoltageFail; - /* power reset the card */ - SDMMCHOST_ENABLE_SD_POWER(false); - SDMMCHOST_Delay(10U); - SDMMCHOST_ENABLE_SD_POWER(true); - SDMMCHOST_Delay(10U); - /* re-check the data line status */ - if ((GET_SDMMCHOST_STATUS(base) & - (CARD_DATA1_STATUS_MASK | CARD_DATA2_STATUS_MASK | CARD_DATA3_STATUS_MASK | CARD_DATA0_NOT_BUSY))) - { - error = kStatus_SDMMC_SwitchVoltage18VFail33VSuccess; - SDMMC_LOG( - "\r\nNote: Current card support 1.8V, but board don't support, so sdmmc switch back to 3.3V."); - } - else - { - SDMMC_LOG( - "\r\nError: Current card support 1.8V, but board don't support, sdmmc tried to switch back\ - to 3.3V, but failed, please check board setting."); - } - } - - return error; - } - else - { - return kStatus_SDMMC_HostNotSupport; - } -} - -status_t SDMMC_ExecuteTuning(SDMMCHOST_TYPE *base, - SDMMCHOST_TRANSFER_FUNCTION transfer, - uint32_t tuningCmd, - uint32_t blockSize) -{ - SDMMCHOST_TRANSFER content = {0U}; - SDMMCHOST_COMMAND command = {0U}; - SDMMCHOST_DATA data = {0U}; - uint32_t buffer[32U] = {0U}; - bool tuningError = true; - - command.index = tuningCmd; - command.argument = 0U; - command.responseType = kCARD_ResponseTypeR1; - - data.blockSize = blockSize; - data.blockCount = 1U; - data.rxData = buffer; - /* add this macro for adpter to different driver */ - SDMMCHOST_ENABLE_TUNING_FLAG(data); - - content.command = &command; - content.data = &data; - - /* enable the standard tuning */ - SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true); - - while (true) - { - /* send tuning block */ - if ((kStatus_Success != transfer(base, &content))) - { - return kStatus_SDMMC_TransferFailed; - } - SDMMCHOST_Delay(1U); - - /*wait excute tuning bit clear*/ - if ((SDMMCHOST_EXECUTE_STANDARD_TUNING_STATUS(base) != 0U)) - { - continue; - } - - /* if tuning error , re-tuning again */ - if ((SDMMCHOST_CHECK_TUNING_ERROR(base) != 0U) && tuningError) - { - tuningError = false; - /* enable the standard tuning */ - SDMMCHOST_EXECUTE_STANDARD_TUNING_ENABLE(base, true); - SDMMCHOST_ADJUST_TUNING_DELAY(base, SDMMCHOST_STANDARD_TUNING_START); - } - else - { - break; - } - } - - /* check tuning result*/ - if (SDMMCHOST_EXECUTE_STANDARD_TUNING_RESULT(base) == 0U) - { - return kStatus_SDMMC_TuningFail; - } - -#if !SDMMC_ENABLE_SOFTWARE_TUNING - SDMMCHOST_AUTO_TUNING_ENABLE(base, true); -#endif - - return kStatus_Success; -} diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdhc/sdmmc_config.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdhc/sdmmc_config.c new file mode 100644 index 0000000000..38f4fa5c3a --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdhc/sdmmc_config.c @@ -0,0 +1,58 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "sdmmc_config.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ +/******************************************************************************* + * Variables + ******************************************************************************/ +/*!brief sdmmc dma buffer */ +SDK_ALIGN(uint32_t s_sdmmcHostDmaBuffer[BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE], + SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE); +#if defined(SDIO_ENABLED) || defined(SD_ENABLED) +static sd_detect_card_t s_cd; +#endif +sdmmchost_t s_host; + +/******************************************************************************* + * Code + ******************************************************************************/ +#ifdef SD_ENABLED +void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, void *userData) +{ + assert(card); + + s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer; + s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE; + ((sd_card_t *)card)->host = &s_host; + ((sd_card_t *)card)->host->hostController.base = BOARD_SDMMC_SD_HOST_BASEADDR; + ((sd_card_t *)card)->host->hostController.sourceClock_Hz = CLOCK_GetFreq(kCLOCK_CoreSysClk); + + ((sd_card_t *)card)->usrParam.cd = &s_cd; + + NVIC_SetPriority(BOARD_SDMMC_SD_HOST_IRQ, hostIRQPriority); +} +#endif + +#ifdef MMC_ENABLED +void BOARD_MMC_Config(void *card, uint32_t hostIRQPriority) +{ + assert(card); + + s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer; + s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE; + ((mmc_card_t *)card)->host = &s_host; + ((mmc_card_t *)card)->host->hostController.base = BOARD_SDMMC_MMC_HOST_BASEADDR; + ((mmc_card_t *)card)->host->hostController.sourceClock_Hz = CLOCK_GetFreq(kCLOCK_CoreSysClk); + ((mmc_card_t *)card)->hostVoltageWindowVCC = BOARD_SDMMC_MMC_VCC_SUPPLY; + ((mmc_card_t *)card)->hostVoltageWindowVCCQ = BOARD_SDMMC_MMC_VCCQ_SUPPLY; + + NVIC_SetPriority(BOARD_SDMMC_MMC_HOST_IRQ, hostIRQPriority); +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdhc/sdmmc_config.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdhc/sdmmc_config.h new file mode 100644 index 0000000000..fb88bab752 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdhc/sdmmc_config.h @@ -0,0 +1,101 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _SDMMC_CONFIG_H_ +#define _SDMMC_CONFIG_H_ + +#ifdef SD_ENABLED +#include "fsl_sd.h" +#endif +#ifdef MMC_ENABLED +#include "fsl_mmc.h" +#endif +#include "clock_config.h" +#include "fsl_sdmmc_host.h" +#include "fsl_sdmmc_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* @brief host basic configuration */ +#define BOARD_SDMMC_SD_HOST_BASEADDR SDHC +#define BOARD_SDMMC_MMC_HOST_BASEADDR SDHC + +#define BOARD_SDMMC_SD_HOST_IRQ SDHC_IRQn +#define BOARD_SDMMC_MMC_HOST_IRQ SDHC_IRQn +/* @brief card detect configuration */ +#define BOARD_SDMMC_SD_CD_GPIO_BASE GPIOB +#define BOARD_SDMMC_SD_CD_GPIO_PIN 20U +#define BOARD_SDMMC_SD_CD_PORT_BASE PORTB +#define BOARD_SDMMC_SD_CD_PORT_IRQ PORTB_IRQn +#define BOARD_SDMMC_SD_CD_IRQ_PRIORITY 6U +#define BOARD_SDMMC_SD_CD_INTTERUPT_TYPE kPORT_InterruptEitherEdge +#define BOARD_SDMMC_SD_CD_INSERT_LEVEL (0U) +#define BOARD_SDMMC_SD_CD_PORT_IRQ_HANDLER PORTB_IRQHandler +/* @brief card detect type + * + * Note: if you want to use DAT3 as card detect pin, please pay attention, DAT3 card detection cannot works during the + * card access, since the DAT3 will be used for data transfer, thus the functionality of card detect interrupt will be + * disabled as soon as card is detected. So If application would like to re-detect sdcard/sdiocard, please calling + * SD_PollingCardInsert/SDIO_PollingCardInsert The function will polling the card detect status and could yield CPU + * while RTOS and non-blocking adapter is using. + * + * Using card detect pin for card detection is recommended. + */ +#define BOARD_SDMMC_SD_CD_TYPE kSD_DetectCardByGpioCD +#define BOARD_SDMMC_SD_CARD_DETECT_DEBOUNCE_DELAY_MS (100U) + +#define BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE (4U) +/* @brief mmc configuration */ +#define BOARD_SDMMC_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360 +#define BOARD_SDMMC_MMC_VCCQ_SUPPLY kMMC_VoltageWindows270to360 + +/* @brief The SDSPI configuration. */ +#define BOARD_SDSPI_HOST_BASE SPI1_BASE /*!< SPI base address for SDSPI */ +#define BOARD_SDSPI_HOST_CD_GPIO_BASE GPIOB /*!< Port related to card detect pin for SDSPI */ +#define BOARD_SDSPI_HOST_CD_PIN 20U /*!< Card detect pin for SDSPI */ + +/*!@ brief host interrupt priority*/ +#define BOARD_SDMMC_SD_HOST_IRQ_PRIORITY (5U) +#define BOARD_SDMMC_MMC_HOST_IRQ_PRIORITY (5U) +/*!@brief dma descriptor buffer size */ +#define BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE (32U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ + +/*! + * @brief BOARD SD configurations. + * @param card card descriptor + * @param cd card detect callback + * @param userData user data for callback + */ +#ifdef SD_ENABLED +void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, void *userData); +#endif + +/*! + * @brief BOARD MMC configurations. + * @param card card descriptor + * @param cd card detect callback + * @param userData user data for callback + */ +#ifdef MMC_ENABLED +void BOARD_MMC_Config(void *card, uint32_t hostIRQPriority); + +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdif/sdmmc_config.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdif/sdmmc_config.c new file mode 100644 index 0000000000..0261dcd879 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdif/sdmmc_config.c @@ -0,0 +1,115 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "sdmmc_config.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +/******************************************************************************* + * Variables + ******************************************************************************/ +/*!brief sdmmc dma buffer */ +SDK_ALIGN(uint32_t s_sdmmcHostDmaBuffer[BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE], + SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE); +#if defined(SDIO_ENABLED) || defined(SD_ENABLED) +static sd_detect_card_t s_cd; +#endif +static sdmmchost_t s_host; +#ifdef SDIO_ENABLED +sdio_card_int_t s_sdioInt; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +void Board_InitSdifUnusedDataPin(void) +{ +} + +uint32_t BOARD_SDIF0ClockConfiguration(void) +{ + return 0; +} + +#ifdef SD_ENABLED +void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, void *userData) +{ + assert(card); + + s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer; + s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE; + ((sd_card_t *)card)->host = &s_host; + ((sd_card_t *)card)->host->hostController.base = BOARD_SDMMC_SD_HOST_BASEADDR; + ((sd_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_SDIF0ClockConfiguration(); + + ((sd_card_t *)card)->usrParam.cd = &s_cd; + + /* This function is used to init the SDIF unused data pin, DATA4 - DATA7, these pin should be configured + * ,otherswise the SDIF will not work, please check the corresponding errata. + */ + Board_InitSdifUnusedDataPin(); + + NVIC_SetPriority(BOARD_SDMMC_SD_HOST_IRQ, hostIRQPriority); +} +#endif + +#ifdef SDIO_ENABLED +void BOARD_SDIO_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, sdio_int_t cardInt) +{ + assert(card); + + s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer; + s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE; + ((sdio_card_t *)card)->host = &s_host; + ((sdio_card_t *)card)->host->hostController.base = BOARD_SDMMC_SDIO_HOST_BASEADDR; + ((sdio_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_SDIF0ClockConfiguration(); + + ((sdio_card_t *)card)->usrParam.cd = &s_cd; + if (cardInt != NULL) + { + s_sdioInt.cardInterrupt = cardInt; + ((sdio_card_t *)card)->usrParam.sdioInt = &s_sdioInt; + } + + /* This function is used to init the SDIF unused data pin, DATA4 - DATA7, these pin should be configured + * ,otherswise the SDIF will not work, please check the corresponding errata. + */ + Board_InitSdifUnusedDataPin(); + + BOARD_SDCardDetectInit(cd, NULL); + + NVIC_SetPriority(BOARD_SDMMC_SDIO_HOST_IRQ, hostIRQPriority); +} +#endif + +#ifdef MMC_ENABLED +void BOARD_MMC_Config(void *card, uint32_t hostIRQPriority) + +{ + assert(card); + + s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer; + s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE; + ((mmc_card_t *)card)->host = &s_host; + ((mmc_card_t *)card)->host->hostController.base = BOARD_SDMMC_MMC_HOST_BASEADDR; + ((mmc_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_SDIF0ClockConfiguration(); + + ((mmc_card_t *)card)->hostVoltageWindowVCC = BOARD_SDMMC_MMC_VCC_SUPPLY; + ((mmc_card_t *)card)->hostVoltageWindowVCCQ = BOARD_SDMMC_MMC_VCCQ_SUPPLY; + + /* This function is used to init the SDIF unused data pin, DATA4 - DATA7, these pin should be configured + * ,otherswise the SDIF will not work, please check the corresponding errata. + */ + Board_InitSdifUnusedDataPin(); + + NVIC_SetPriority(BOARD_SDMMC_MMC_HOST_IRQ, hostIRQPriority); +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdif/sdmmc_config.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdif/sdmmc_config.h new file mode 100644 index 0000000000..166f239143 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/sdif/sdmmc_config.h @@ -0,0 +1,92 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _SDMMC_CONFIG_H_ +#define _SDMMC_CONFIG_H_ + +#ifdef SD_ENABLED +#include "fsl_sd.h" +#endif +#ifdef MMC_ENABLED +#include "fsl_mmc.h" +#endif +#ifdef SDIO_ENABLED +#include "fsl_sdio.h" +#endif +#include "clock_config.h" +#include "fsl_sdmmc_host.h" +#include "fsl_sdmmc_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* @brief host basic configuration */ +#define BOARD_SDMMC_SD_HOST_BASEADDR SDIF +#define BOARD_SDMMC_SD_HOST_IRQ SDIO_IRQn +#define BOARD_SDMMC_MMC_HOST_BASEADDR SDIF +#define BOARD_SDMMC_MMC_HOST_IRQ SDIO_IRQn +#define BOARD_SDMMC_SDIO_HOST_BASEADDR SDIF +#define BOARD_SDMMC_SDIO_HOST_IRQ SDIO_IRQn +/* @brief card detect configuration */ +#define BOARD_SDMMC_SD_CD_TYPE kSD_DetectCardByHostCD +#define BOARD_SDMMC_SD_CARD_DETECT_DEBOUNCE_DELAY_MS (100U) + +/* @brief mmc configuration */ +#define BOARD_SDMMC_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360 +#define BOARD_SDMMC_MMC_VCCQ_SUPPLY kMMC_VoltageWindows270to360 +#define BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE (4U) + +/*!@ brief host interrupt priority*/ +#define BOARD_SDMMC_SD_HOST_IRQ_PRIORITY (5U) +#define BOARD_SDMMC_MMC_HOST_IRQ_PRIORITY (5U) +#define BOARD_SDMMC_SDIO_HOST_IRQ_PRIORITY (5U) +/*!@brief dma descriptor buffer size */ +#define BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE (0x40U) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief BOARD SD configurations. + * @param card card descriptor + * @param cd card detect callback + * @param userData user data for callback + */ +#ifdef SD_ENABLED +void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, void *userData); +#endif + +/*! + * @brief BOARD SDIO configurations. + * @param card card descriptor + * @param cd card detect callback + * @param cardInt card interrupt + */ +#ifdef SDIO_ENABLED +void BOARD_SDIO_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, sdio_int_t cardInt); +#endif + +/*! + * @brief BOARD MMC configurations. + * @param card card descriptor + * @param cd card detect callback + * @param userData user data for callback + */ +#ifdef MMC_ENABLED +void BOARD_MMC_Config(void *card, uint32_t hostIRQPriority); + +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/usdhc/sdmmc_config.c b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/usdhc/sdmmc_config.c new file mode 100644 index 0000000000..49b8940de2 --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/usdhc/sdmmc_config.c @@ -0,0 +1,149 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include "sdmmc_config.h" +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * Prototypes + ******************************************************************************/ +void BOARD_SDCardPowerControl(bool enable); + +/******************************************************************************* + * Variables + ******************************************************************************/ +/*!brief sdmmc dma buffer */ +AT_NONCACHEABLE_SECTION_ALIGN(uint32_t s_sdmmcHostDmaBuffer[BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE], + SDMMCHOST_DMA_DESCRIPTOR_BUFFER_ALIGN_SIZE); +#if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER +/* two cache line length for sdmmc host driver maintain unalign transfer */ +SDK_ALIGN(static uint8_t s_sdmmcCacheLineAlignBuffer[BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U], + BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE); +#endif +#if defined(SDIO_ENABLED) || defined(SD_ENABLED) +static sd_detect_card_t s_cd; +static sd_io_voltage_t s_ioVoltage = { + .type = BOARD_SDMMC_SD_IO_VOLTAGE_CONTROL_TYPE, + .func = NULL, +}; +#endif +sdmmchost_t s_host; +#ifdef SDIO_ENABLED +static sdio_card_int_t s_sdioInt; +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +uint32_t BOARD_USDHC1ClockConfiguration(void) +{ + return 0; +} + +#if defined(SDIO_ENABLED) || defined(SD_ENABLED) +void BOARD_SDCardPowerControl(bool enable) +{ +} + +void BOARD_SD_Pin_Config(uint32_t freq) +{ +} +#endif + +#ifdef SD_ENABLED +void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, void *userData) +{ + assert(card); + + s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer; + s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE; + s_host.enableCacheControl = BOARD_SDMMC_HOST_CACHE_CONTROL; +#if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER + s_host.cacheAlignBuffer = s_sdmmcCacheLineAlignBuffer; + s_host.cacheAlignBufferSize = BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U; +#endif + + ((sd_card_t *)card)->host = &s_host; + ((sd_card_t *)card)->host->hostController.base = BOARD_SDMMC_SD_HOST_BASEADDR; + ((sd_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_USDHC1ClockConfiguration(); + + ((sd_card_t *)card)->usrParam.cd = &s_cd; + ((sd_card_t *)card)->usrParam.pwr = BOARD_SDCardPowerControl; + ((sd_card_t *)card)->usrParam.ioStrength = BOARD_SD_Pin_Config; + ((sd_card_t *)card)->usrParam.ioVoltage = &s_ioVoltage; + ((sd_card_t *)card)->usrParam.maxFreq = BOARD_SDMMC_SD_HOST_SUPPORT_SDR104_FREQ; + + NVIC_SetPriority(BOARD_SDMMC_SD_HOST_IRQ, hostIRQPriority); +} +#endif + +#ifdef SDIO_ENABLED +void BOARD_SDIO_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, sdio_int_t cardInt) +{ + assert(card); + + s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer; + s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE; + s_host.enableCacheControl = BOARD_SDMMC_HOST_CACHE_CONTROL; +#if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER + s_host.cacheAlignBuffer = s_sdmmcCacheLineAlignBuffer; + s_host.cacheAlignBufferSize = BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U; +#endif + + ((sdio_card_t *)card)->host = &s_host; + ((sdio_card_t *)card)->host->hostController.base = BOARD_SDMMC_SDIO_HOST_BASEADDR; + ((sdio_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_USDHC1ClockConfiguration(); + + ((sdio_card_t *)card)->usrParam.cd = &s_cd; + ((sdio_card_t *)card)->usrParam.pwr = BOARD_SDCardPowerControl; + ((sdio_card_t *)card)->usrParam.ioStrength = BOARD_SD_Pin_Config; + ((sdio_card_t *)card)->usrParam.ioVoltage = &s_ioVoltage; + ((sdio_card_t *)card)->usrParam.maxFreq = BOARD_SDMMC_SD_HOST_SUPPORT_SDR104_FREQ; + if (cardInt != NULL) + { + s_sdioInt.cardInterrupt = cardInt; + ((sdio_card_t *)card)->usrParam.sdioInt = &s_sdioInt; + } + + BOARD_SDCardPowerResetInit(); + BOARD_SDCardDetectInit(cd, NULL); + + NVIC_SetPriority(BOARD_SDMMC_SDIO_HOST_IRQ, hostIRQPriority); +} +#endif + +#ifdef MMC_ENABLED +static void BOARD_MMC_Pin_Config(uint32_t freq) +{ +} + +void BOARD_MMC_Config(void *card, uint32_t hostIRQPriority) +{ + assert(card); + + s_host.dmaDesBuffer = s_sdmmcHostDmaBuffer; + s_host.dmaDesBufferWordsNum = BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE; + s_host.enableCacheControl = BOARD_SDMMC_HOST_CACHE_CONTROL; +#if defined SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER && SDMMCHOST_ENABLE_CACHE_LINE_ALIGN_TRANSFER + s_host.cacheAlignBuffer = s_sdmmcCacheLineAlignBuffer; + s_host.cacheAlignBufferSize = BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE * 2U; +#endif + + ((mmc_card_t *)card)->host = &s_host; + ((mmc_card_t *)card)->host->hostController.base = BOARD_SDMMC_MMC_HOST_BASEADDR; + ((mmc_card_t *)card)->host->hostController.sourceClock_Hz = BOARD_USDHC1ClockConfiguration(); + ((mmc_card_t *)card)->usrParam.ioStrength = BOARD_MMC_Pin_Config; + ((mmc_card_t *)card)->usrParam.maxFreq = BOARD_SDMMC_MMC_HOST_SUPPORT_HS200_FREQ; + + ((mmc_card_t *)card)->hostVoltageWindowVCC = BOARD_SDMMC_MMC_VCC_SUPPLY; + ((mmc_card_t *)card)->hostVoltageWindowVCCQ = BOARD_SDMMC_MMC_VCCQ_SUPPLY; + + NVIC_SetPriority(BOARD_SDMMC_MMC_HOST_IRQ, hostIRQPriority); +} +#endif diff --git a/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/usdhc/sdmmc_config.h b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/usdhc/sdmmc_config.h new file mode 100644 index 0000000000..d2479ab48b --- /dev/null +++ b/bsp/lpc55sxx/Libraries/LPC55S6X/middleware/sdmmc/template/usdhc/sdmmc_config.h @@ -0,0 +1,115 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _SDMMC_CONFIG_H_ +#define _SDMMC_CONFIG_H_ + +#ifdef SD_ENABLED +#include "fsl_sd.h" +#endif +#ifdef MMC_ENABLED +#include "fsl_mmc.h" +#endif +#ifdef SDIO_ENABLED +#include "fsl_sdio.h" +#endif +#include "clock_config.h" +#include "fsl_sdmmc_host.h" +#include "fsl_sdmmc_common.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/* @brief host basic configuration */ +#define BOARD_SDMMC_SD_HOST_BASEADDR USDHC1 +#define BOARD_SDMMC_SD_HOST_IRQ USDHC1_IRQn +#define BOARD_SDMMC_MMC_HOST_BASEADDR USDHC1 +#define BOARD_SDMMC_MMC_HOST_IRQ USDHC1_IRQn +#define BOARD_SDMMC_SDIO_HOST_BASEADDR USDHC1 +#define BOARD_SDMMC_SDIO_HOST_IRQ USDHC1_IRQn +/* @brief card detect configuration */ +#define BOARD_SDMMC_SD_CD_GPIO_BASE GPIO2 +#define BOARD_SDMMC_SD_CD_GPIO_PIN 28u +#define BOARD_SDMMC_SD_CD_IRQ_PRIORITY 6U +#define BOARD_SDMMC_SD_CD_IRQ GPIO2_Combined_16_31_IRQn +#define BOARD_SDMMC_SD_CD_INTTERUPT_TYPE kGPIO_IntRisingOrFallingEdge +#define BOARD_SDMMC_SD_CD_INSERT_LEVEL (0U) +#define BOARD_SDMMC_SD_CD_PORT_IRQ_HANDLER GPIO2_Combined_16_31_IRQHandler +/* @brief card detect type + * + * Note: Please pay attention, DAT3 card detection cannot works during the card access, + * since the DAT3 will be used for data transfer, thus the functionality of card detect will be disabled. Using card + * detect pin for card detection is recommended. + */ +#define BOARD_SDMMC_SD_CD_TYPE kSD_DetectCardByGpioCD +#define BOARD_SDMMC_SD_CARD_DETECT_DEBOUNCE_DELAY_MS (100U) +/*! @brief SD power reset */ +#define BOARD_SDMMC_SD_POWER_RESET_GPIO_BASE GPIO1 +#define BOARD_SDMMC_SD_POWER_RESET_GPIO_PIN 5U +/*! @brief SD IO voltage */ +#define BOARD_SDMMC_SD_IO_VOLTAGE_CONTROL_TYPE kSD_IOVoltageCtrlByHost + +#define BOARD_SDMMC_SD_HOST_SUPPORT_SDR104_FREQ (200000000U) +#define BOARD_SDMMC_MMC_HOST_SUPPORT_HS200_FREQ (180000000U) +/*! @brief mmc configuration */ +#define BOARD_SDMMC_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360 +#define BOARD_SDMMC_MMC_VCCQ_SUPPLY kMMC_VoltageWindows270to360 +/*! @brief align with cache line size */ +#define BOARD_SDMMC_DATA_BUFFER_ALIGN_SIZE (32U) + +/*!@ brief host interrupt priority*/ +#define BOARD_SDMMC_SD_HOST_IRQ_PRIORITY (5U) +#define BOARD_SDMMC_MMC_HOST_IRQ_PRIORITY (5U) +#define BOARD_SDMMC_SDIO_HOST_IRQ_PRIORITY (5U) +/*!@brief dma descriptor buffer size */ +#define BOARD_SDMMC_HOST_DMA_DESCRIPTOR_BUFFER_SIZE (32U) +/*! @brief cache maintain function enabled for RW buffer */ +#define BOARD_SDMMC_HOST_CACHE_CONTROL kSDMMCHOST_CacheControlRWBuffer + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/******************************************************************************* + * API + ******************************************************************************/ +/*! + * @brief BOARD SD configurations. + * @param card card descriptor + * @param cd card detect callback + * @param userData user data for callback + */ +#ifdef SD_ENABLED +void BOARD_SD_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, void *userData); +#endif + +/*! + * @brief BOARD SDIO configurations. + * @param card card descriptor + * @param cd card detect callback + * @param cardInt card interrupt + */ +#ifdef SDIO_ENABLED +void BOARD_SDIO_Config(void *card, sd_cd_t cd, uint32_t hostIRQPriority, sdio_int_t cardInt); +#endif + +/*! + * @brief BOARD MMC configurations. + * @param card card descriptor + * @param cd card detect callback + * @param userData user data for callback + */ +#ifdef MMC_ENABLED +void BOARD_MMC_Config(void *card, uint32_t hostIRQPriority); + +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* _BOARD_H_ */ diff --git a/bsp/lpc55sxx/Libraries/drivers/drv_uart.c b/bsp/lpc55sxx/Libraries/drivers/drv_uart.c index d62b676e87..bedbcc9118 100644 --- a/bsp/lpc55sxx/Libraries/drivers/drv_uart.c +++ b/bsp/lpc55sxx/Libraries/drivers/drv_uart.c @@ -132,7 +132,7 @@ static const struct lpc_uart uarts[] = { USART0, FLEXCOMM0_IRQn, - kCLOCK_Flexcomm0, + kCLOCK_Fro12M, &serial0, "uart0", @@ -142,7 +142,7 @@ static const struct lpc_uart uarts[] = { USART1, FLEXCOMM1_IRQn, - kCLOCK_Flexcomm1, + kCLOCK_Fro12M, &serial1, "uart1", @@ -152,7 +152,7 @@ static const struct lpc_uart uarts[] = { USART2, FLEXCOMM2_IRQn, - kCLOCK_Flexcomm2, + kCLOCK_Fro12M, &serial2, "uart2", @@ -162,7 +162,7 @@ static const struct lpc_uart uarts[] = { USART3, FLEXCOMM3_IRQn, - kCLOCK_Flexcomm3, + kCLOCK_Fro12M, &serial3, "uart3", @@ -172,7 +172,7 @@ static const struct lpc_uart uarts[] = { USART4, FLEXCOMM4_IRQn, - kCLOCK_Flexcomm4, + kCLOCK_Fro12M, &serial4, "uart4", @@ -182,7 +182,7 @@ static const struct lpc_uart uarts[] = { USART5, FLEXCOMM5_IRQn, - kCLOCK_Flexcomm5, + kCLOCK_Fro12M, &serial5, "uart5", @@ -192,7 +192,7 @@ static const struct lpc_uart uarts[] = { USART6, FLEXCOMM6_IRQn, - kCLOCK_Flexcomm6, + kCLOCK_Fro12M, &serial6, "uart6", @@ -202,7 +202,7 @@ static const struct lpc_uart uarts[] = { USART7, FLEXCOMM7_IRQn, - kCLOCK_Flexcomm7, + kCLOCK_Fro12M, &serial7, "uart7", diff --git a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/README.md b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/README.md index 0c433ec2c4..a298b887bc 100644 --- a/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/README.md +++ b/bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/README.md @@ -211,6 +211,8 @@ msh /> 维护人: [Magicoe][2] < [magicoe@163.com][3] > +[AlexYang][2] < [alex.yang@nxp.com][3] > + [1]: https://www.rt-thread.org/page/download.html [2]: https://github.com/Magicoe [3]: mailto:magicoe@163.com diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/.vscode/launch.json b/bsp/lpc55sxx/lpc55s69_nxp_evk/.vscode/launch.json deleted file mode 100644 index 4806836f25..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/.vscode/launch.json +++ /dev/null @@ -1,16 +0,0 @@ -{ - "version": "0.2.0", - "configurations": [ - { - "cwd": "${workspaceRoot}", - "executable": "rtthread.elf", - "name": "Debug", - "request": "launch", - "type": "cortex-debug", - "servertype": "jlink", - "interface": "swd", - "device": "LPC55S69_M33_0", - "runToMain": true - }, - ] -} \ No newline at end of file diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_mdk.scf b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash.scf similarity index 81% rename from bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_mdk.scf rename to bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash.scf index 7d91ff9575..67cd92d97b 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_mdk.scf +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash.scf @@ -2,18 +2,19 @@ /* ** ################################################################### ** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 +** LPC55S69JBD64_cm33_core0 +** LPC55S69JEV98_cm33_core0 ** ** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181008 +** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019 +** Version: rev. 1.1, 2019-05-16 +** Build: b210928 ** ** Abstract: ** Linker file for the Keil ARM C/C++ Compiler ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -31,13 +32,13 @@ #if (defined(__stack_size__)) #define Stack_Size __stack_size__ #else - #define Stack_Size 0x1000 + #define Stack_Size 0x0400 #endif #if (defined(__heap_size__)) #define Heap_Size __heap_size__ #else - #define Heap_Size 0x1000 + #define Heap_Size 0x0400 #endif #define m_interrupts_start 0x00000000 @@ -47,7 +48,7 @@ #define m_text_size 0x00071E00 #define m_core1_image_start 0x00072000 -#define m_core1_image_size 0x00026000 +#define m_core1_image_size 0x0002B800 #if (defined(__use_shmem__)) #define m_data_start 0x20000000 @@ -66,12 +67,12 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) + * (.isr_vector,+FIRST) } ER_m_text m_text_start FIXED m_text_size { ; load address = execution address * (InRoot$$Sections) - * (+RO) + .ANY (+RO) } #if (defined(__use_shmem__)) @@ -81,7 +82,7 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz #endif RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - * (+RW +ZI) + .ANY (+RW +ZI) } ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up } @@ -89,16 +90,16 @@ LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region siz } RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) + * (*m_usb_bdt) } RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) + * (*m_usb_global) } } LR_CORE1_IMAGE m_core1_image_start { CORE1_REGION m_core1_image_start m_core1_image_size { - *(M0CODE) + * (.core1_code) } } diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf b/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf deleted file mode 100644 index e0ee619399..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_ns_mdk.scf +++ /dev/null @@ -1,111 +0,0 @@ -#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c -/* -** ################################################################### -** Processors: LPC55S69JBD100_cm33_core0 -** LPC55S69JET98_cm33_core0 -** -** Compiler: Keil ARM C/C++ Compiler -** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 -** Version: rev. 1.0, 2018-08-22 -** Build: b181008 -** -** Abstract: -** Linker file for the Keil ARM C/C++ Compiler -** -** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2018 NXP -** Copyright 2019-2020 Arm Limited. All rights reserved. -** All rights reserved. -** -** SPDX-License-Identifier: BSD-3-Clause -** -** http: www.nxp.com -** mail: support@nxp.com -** -** ################################################################### -*/ - -/* - * Original code taken from RTT project at: - * https://github.com/RT-Thread/rt-thread - * File: bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_mdk.scf - * Git SHA of the original version: 64945ba882d651a14933eb4e7b3d93d10d6daae1 - */ - -/* USB BDT size */ -#define usb_bdt_size 0x0 -/* Sizes */ -#if (defined(__stack_size__)) - #define Stack_Size __stack_size__ -#else - #define Stack_Size 0x1000 -#endif - -#if (defined(__heap_size__)) - #define Heap_Size __heap_size__ -#else - #define Heap_Size 0x1000 -#endif - -#define m_interrupts_start 0x00020000 -#define m_interrupts_size 0x00000200 - -#define m_text_start 0x00020200 -#define m_text_size 0x00031000 - -#define m_core1_image_start 0x00072000 -#define m_core1_image_size 0x00026000 - -#if (defined(__use_shmem__)) - #define m_data_start 0x20033000 - #define m_data_size 0x00010800 - #define m_rpmsg_sh_mem_start 0x20043800 - #define m_rpmsg_sh_mem_size 0x00000800 -#else - #define m_data_start 0x20033000 - #define m_data_size 0x0000cc00 -#endif - -#define m_usb_sram_start 0x40100000 -#define m_usb_sram_size 0x00004000 - - -LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region - - VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address - * (RESET,+FIRST) - } - - ER_m_text m_text_start FIXED m_text_size { ; load address = execution address - * (InRoot$$Sections) - * (+RO) - } - -#if (defined(__use_shmem__)) - RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG - * (rpmsg_sh_mem_section) - } -#endif - - RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data - * (+RW +ZI) - } - ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up - } - ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down - } - - RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { - * (m_usb_bdt) - } - - RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { - * (m_usb_global) - } -} - -LR_CORE1_IMAGE m_core1_image_start { - CORE1_REGION m_core1_image_start m_core1_image_size { - *(M0CODE) - } -} diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvoptx b/bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvoptx index e29ce628a9..7c093ce068 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvoptx +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvoptx @@ -103,7 +103,7 @@ 1 0 0 - 15 + 14 @@ -196,4 +196,1148 @@ + + Applications + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + applications\main.c + main.c + 0 + 0 + + + + + Compiler + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdio.c + cstdio.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\backtrace.c + backtrace.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 3 + 13 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\context_rvds.S + context_rvds.S + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\cpuport.c + cpuport.c + 0 + 0 + + + 3 + 15 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S + syscall_rvds.S + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m33\trustzone.c + trustzone.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 4 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion.c + completion.c + 0 + 0 + + + 4 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 4 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 4 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 4 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 4 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 4 + 23 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 4 + 24 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial.c + serial.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 5 + 26 + 1 + 0 + 0 + 0 + board\MCUX_Config\board\clock_config.c + clock_config.c + 0 + 0 + + + 5 + 27 + 1 + 0 + 0 + 0 + board\MCUX_Config\board\pin_mux.c + pin_mux.c + 0 + 0 + + + 5 + 28 + 1 + 0 + 0 + 0 + board\board.c + board.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\Libraries\drivers\drv_key.c + drv_key.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\Libraries\drivers\drv_led.c + drv_led.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\Libraries\drivers\drv_pin.c + drv_pin.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + ..\Libraries\drivers\drv_uart.c + drv_uart.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 7 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 7 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 7 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\device.c + device.c + 0 + 0 + + + 7 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 7 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 7 + 42 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 7 + 43 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 7 + 44 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 7 + 45 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 7 + 46 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler.c + scheduler.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + Libraries + 0 + 0 + 0 + 0 + + 8 + 50 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_hashcrypt.c + fsl_hashcrypt.c + 0 + 0 + + + 8 + 51 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart_dma.c + fsl_usart_dma.c + 0 + 0 + + + 8 + 52 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi_dma.c + fsl_spi_dma.c + 0 + 0 + + + 8 + 53 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_cmp.c + fsl_cmp.c + 0 + 0 + + + 8 + 54 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_utick.c + fsl_utick.c + 0 + 0 + + + 8 + 55 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_common_arm.c + fsl_common_arm.c + 0 + 0 + + + 8 + 56 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_power.c + fsl_power.c + 0 + 0 + + + 8 + 57 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2s_dma.c + fsl_i2s_dma.c + 0 + 0 + + + 8 + 58 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_gpio.c + fsl_gpio.c + 0 + 0 + + + 8 + 59 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_casper.c + fsl_casper.c + 0 + 0 + + + 8 + 60 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_clock.c + fsl_clock.c + 0 + 0 + + + 8 + 61 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_wwdt.c + fsl_wwdt.c + 0 + 0 + + + 8 + 62 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_reset.c + fsl_reset.c + 0 + 0 + + + 8 + 63 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sctimer.c + fsl_sctimer.c + 0 + 0 + + + 8 + 64 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_common.c + fsl_common.c + 0 + 0 + + + 8 + 65 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rtc.c + fsl_rtc.c + 0 + 0 + + + 8 + 66 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_crc.c + fsl_crc.c + 0 + 0 + + + 8 + 67 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sdif.c + fsl_sdif.c + 0 + 0 + + + 8 + 68 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_plu.c + fsl_plu.c + 0 + 0 + + + 8 + 69 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_mrt.c + fsl_mrt.c + 0 + 0 + + + 8 + 70 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2s.c + fsl_i2s.c + 0 + 0 + + + 8 + 71 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi.c + fsl_spi.c + 0 + 0 + + + 8 + 72 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ctimer.c + fsl_ctimer.c + 0 + 0 + + + 8 + 73 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_gint.c + fsl_gint.c + 0 + 0 + + + 8 + 74 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_dma.c + fsl_dma.c + 0 + 0 + + + 8 + 75 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sysctl.c + fsl_sysctl.c + 0 + 0 + + + 8 + 76 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_flexcomm.c + fsl_flexcomm.c + 0 + 0 + + + 8 + 77 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_pint.c + fsl_pint.c + 0 + 0 + + + 8 + 78 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_powerquad_basic.c + fsl_powerquad_basic.c + 0 + 0 + + + 8 + 79 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart.c + fsl_usart.c + 0 + 0 + + + 8 + 80 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_puf.c + fsl_puf.c + 0 + 0 + + + 8 + 81 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rng.c + fsl_rng.c + 0 + 0 + + + 8 + 82 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_lpadc.c + fsl_lpadc.c + 0 + 0 + + + 8 + 83 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_inputmux.c + fsl_inputmux.c + 0 + 0 + + + 8 + 84 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c_dma.c + fsl_i2c_dma.c + 0 + 0 + + + 8 + 85 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c.c + fsl_i2c.c + 0 + 0 + + + 8 + 86 + 2 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\arm\startup_LPC55S69_cm33_core0.s + startup_LPC55S69_cm33_core0.s + 0 + 0 + + + 8 + 87 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\system_LPC55S69_cm33_core0.c + system_LPC55S69_cm33_core0.c + 0 + 0 + + + 8 + 88 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_anactrl.c + fsl_anactrl.c + 0 + 0 + + + 8 + 89 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_iap.c + fsl_iap.c + 0 + 0 + + + 8 + 90 + 1 + 0 + 0 + 0 + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ostimer.c + fsl_ostimer.c + 0 + 0 + + + diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvprojx b/bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvprojx index 6147f130d3..9633575635 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvprojx +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/project.uvprojx @@ -1,43 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rtthread-lpc55s6x 0x4 ARM-ADS - 6120000::V6.12::.\ARMCLANG + 6160000::V6.16::ARMCLANG 1 LPC55S69JBD100:cm33_core0 NXP - NXP.LPC55S69_DFP.13.0.0 + NXP.LPC55S69_DFP.14.0.0 https://mcuxpresso.nxp.com/cmsis_pack/repo/ IRAM(0x20000000,0x044000) IRAM2(0x04000000,0x8000) IROM(0x00000000,0x098000) XRAM(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE - - + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM)) 0 $$Device:LPC55S69JBD100$fsl_device_registers.h - - - - - - - - - + + + + + + + + + $$Device:LPC55S69JBD100$LPC55S69_cm33_core0.xml 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -79,15 +82,15 @@ 0 0 - - + + 0 0 0 0 0 - + 0 @@ -101,15 +104,15 @@ 0 0 3 - - + + 1 - - - - + + + + SARMV8M.DLL -MPU TCM.DLL @@ -136,10 +139,10 @@ 1 BIN\UL2V8M.DLL "" () - - - - + + + + 0 @@ -172,7 +175,7 @@ 0 0 "Cortex-M33" - + 0 0 0 @@ -306,7 +309,7 @@ 0x8000 - + 1 @@ -334,9 +337,9 @@ 0 --target=arm-arm-none-eabi - CPU_LPC55S69JBD100_cm33_core0, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS, __RTTHREAD__, RT_USING_ARM_LIBC - - applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m33;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\MCUX_Config\board;..\Libraries\drivers;..\Libraries\drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\Libraries\LPC55S6X\CMSIS\Include;..\Libraries\LPC55S6X\components\codec;..\Libraries\LPC55S6X\LPC55S6X;..\Libraries\LPC55S6X\LPC55S6X\drivers;..\Libraries\LPC55S6X\middleware\sdmmc\inc;..\Libraries\LPC55S6X\middleware\sdmmc\port;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc + __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, CPU_LPC55S69JBD100_cm33_core0 + + ..\..\..\components\libc\posix\ipc;board;..\..\..\components\drivers\include;board\MCUX_Config\board;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\Libraries\LPC55S6X\middleware\sdmmc\port;..\Libraries\drivers;..\..\..\components\libc\posix\io\poll;..\Libraries\drivers\config;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m33;..\..\..\components\drivers\include;..\Libraries\LPC55S6X\middleware\sdmmc\inc;..\..\..\components\libc\posix\io\stdio;applications;..\Libraries\LPC55S6X\CMSIS\Core\Include;..\Libraries\LPC55S6X\components\codec;.;..\..\..\components\libc\compilers\common\extension;..\Libraries\LPC55S6X\LPC55S6X;..\Libraries\LPC55S6X\LPC55S6X\drivers;..\..\..\components\drivers\include;..\..\..\include @@ -349,12 +352,12 @@ 0 0 0 - 4 + 2 - - - - + -x assembler-with-cpp + + + @@ -366,13 +369,13 @@ 0 0x00000000 0x02000000 - - .\board\linker_scripts\LPC55S69_cm33_core0_flash_mdk.scf - - - - - + + .\board\linker_scripts\LPC55S69_cm33_core0_flash.scf + + + + + @@ -395,50 +398,36 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdio.c 1 ..\..\..\components\libc\compilers\common\cstdio.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cwchar.c 1 @@ -454,43 +443,31 @@ 1 ..\..\..\libcpu\arm\common\backtrace.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m33\context_rvds.S - - cpuport.c 1 ..\..\..\libcpu\arm\cortex-m33\cpuport.c - - syscall_rvds.S 2 ..\..\..\libcpu\arm\cortex-m33\syscall_rvds.S - - trustzone.c 1 @@ -506,57 +483,41 @@ 1 ..\..\..\components\drivers\ipc\completion.c - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c - - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - serial.c 1 @@ -572,43 +533,31 @@ 1 board\MCUX_Config\board\clock_config.c - - pin_mux.c 1 board\MCUX_Config\board\pin_mux.c - - board.c 1 board\board.c - - drv_key.c 1 ..\Libraries\drivers\drv_key.c - - drv_led.c 1 ..\Libraries\drivers\drv_led.c - - drv_pin.c 1 ..\Libraries\drivers\drv_pin.c - - drv_uart.c 1 @@ -624,22 +573,16 @@ 1 ..\..\..\components\finsh\shell.c - - msh.c 1 ..\..\..\components\finsh\msh.c - - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - - cmd.c 1 @@ -655,85 +598,61 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - device.c 1 ..\..\..\src\device.c - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - mempool.c 1 ..\..\..\src\mempool.c - - object.c 1 ..\..\..\src\object.c - - scheduler.c 1 ..\..\..\src\scheduler.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -749,316 +668,201 @@ 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_hashcrypt.c - - fsl_usart_dma.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart_dma.c - - fsl_spi_dma.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi_dma.c - - - - fsl_sdmmc_host.c - 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_host.c - - - - - fsl_sdmmc_event.c - 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_event.c - - - fsl_cmp.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_cmp.c - - fsl_utick.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_utick.c - - - fsl_sd.c + fsl_common_arm.c 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sd.c + ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_common_arm.c - - fsl_power.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_power.c - - - - fsl_sdmmc_common.c - 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sdmmc_common.c - - - fsl_i2s_dma.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2s_dma.c - - fsl_gpio.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_gpio.c - - fsl_casper.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_casper.c - - fsl_clock.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_clock.c - - fsl_wwdt.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_wwdt.c - - fsl_reset.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_reset.c - - fsl_sctimer.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sctimer.c - - fsl_common.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_common.c - - fsl_rtc.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rtc.c - - fsl_crc.c 1 ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_crc.c - 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1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_mrt.c - - - fsl_ostimer.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ostimer.c - - - fsl_pint.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_pint.c - - - fsl_plu.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_plu.c - - - fsl_power.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_power.c - - - fsl_powerquad_basic.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_powerquad_basic.c - - - fsl_prince.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_prince.c - - - fsl_puf.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_puf.c - - - fsl_reset.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_reset.c - - - fsl_rng.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rng.c - - - fsl_rtc.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rtc.c - - - fsl_sctimer.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sctimer.c - - - fsl_sdif.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sdif.c - - - fsl_spi.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi.c - - - fsl_spi_dma.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi_dma.c - - - fsl_sysctl.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sysctl.c - - - fsl_usart.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart.c - - - fsl_usart_dma.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart_dma.c - - - fsl_utick.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_utick.c - - - fsl_wwdt.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_wwdt.c - - - fsl_sd.c - 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sd.c - - - fsl_sdmmc_common.c - 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sdmmc_common.c - - - fsl_sdmmc_event.c - 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_event.c - - - fsl_sdmmc_host.c - 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_host.c - - - arm_keil_lib_power_cm33_core0.lib - 4 - ..\Libraries\LPC55S6X\LPC55S6X\arm\keil_lib_power_cm33_core0.lib - - - - - TFM - - - tfm_sst_api.c - 1 - .\packages\trusted-firmware-m-v1.0-beta\interface\src\tfm_sst_api.c - - - tfm_ns_lock_rt-thread.c - 1 - .\packages\trusted-firmware-m-v1.0-beta\interface\src\tfm_ns_lock_rt-thread.c - - - s_veneers.o - 3 - .\packages\trusted-firmware-m-v1.0-beta\cmake_build\install\export\tfm\veneers\s_veneers.o - - - - - - - - - - - - - - diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/template.uvoptx b/bsp/lpc55sxx/lpc55s69_nxp_evk/template.uvoptx index e29ce628a9..de8517f45d 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/template.uvoptx +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/template.uvoptx @@ -103,7 +103,7 @@ 1 0 0 - 15 + 14 diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk/template.uvprojx b/bsp/lpc55sxx/lpc55s69_nxp_evk/template.uvprojx index f86e1f2f6c..9933560b89 100644 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk/template.uvprojx +++ b/bsp/lpc55sxx/lpc55s69_nxp_evk/template.uvprojx @@ -10,13 +10,13 @@ rtthread-lpc55s6x 0x4 ARM-ADS - 6120000::V6.12::.\ARMCLANG + 6160000::V6.16::ARMCLANG 1 LPC55S69JBD100:cm33_core0 NXP - NXP.LPC55S69_DFP.13.0.0 + NXP.LPC55S69_DFP.14.0.0 https://mcuxpresso.nxp.com/cmsis_pack/repo/ IRAM(0x20000000,0x044000) IRAM2(0x04000000,0x8000) IROM(0x00000000,0x098000) XRAM(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE @@ -352,9 +352,9 @@ 0 0 0 - 4 + 2 - + -x assembler-with-cpp @@ -370,7 +370,7 @@ 0x00000000 0x02000000 - .\board\linker_scripts\LPC55S69_cm33_core0_flash_mdk.scf + .\board\linker_scripts\LPC55S69_cm33_core0_flash.scf --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/.config b/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/.config deleted file mode 100644 index 64e944c0ba..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/.config +++ /dev/null @@ -1,828 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# -CONFIG_SOC_LPC55S6x=y - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=4 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=100 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -CONFIG_RT_USING_TIMER_SOFT=y -CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="uart" -CONFIG_RT_VER_NUM=0x40101 -CONFIG_ARCH_ARM=y -CONFIG_RT_USING_CPU_FFS=y -CONFIG_ARCH_ARM_CORTEX_M=y -CONFIG_ARCH_ARM_CORTEX_FPU=y -CONFIG_ARCH_ARM_CORTEX_M33=y -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_POSIX=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 -CONFIG_DFS_FD_MAX=16 -# CONFIG_RT_USING_DFS_MNTTABLE is not set -CONFIG_RT_USING_DFS_ELMFAT=y - -# -# elm-chan's FatFs, Generic FAT Filesystem Module -# -CONFIG_RT_DFS_ELM_CODE_PAGE=437 -CONFIG_RT_DFS_ELM_WORD_ACCESS=y -# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set -# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set -CONFIG_RT_DFS_ELM_USE_LFN_3=y -CONFIG_RT_DFS_ELM_USE_LFN=3 -CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y -# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set -# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set -CONFIG_RT_DFS_ELM_LFN_UNICODE=0 -CONFIG_RT_DFS_ELM_MAX_LFN=255 -CONFIG_RT_DFS_ELM_DRIVES=2 -CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 -# CONFIG_RT_DFS_ELM_USE_ERASE is not set -CONFIG_RT_DFS_ELM_REENTRANT=y -CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_FAL is not set -# CONFIG_RT_USING_LWP is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -CONFIG_RT_SERIAL_USING_DMA=y -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -CONFIG_RT_USING_HWTIMER=y -# CONFIG_RT_USING_CPUTIME is not set -CONFIG_RT_USING_I2C=y -# CONFIG_RT_I2C_DEBUG is not set -CONFIG_RT_USING_I2C_BITOPS=y -# CONFIG_RT_I2C_BITOPS_DEBUG is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -CONFIG_RT_USING_ADC=y -# CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -CONFIG_RT_USING_RTC=y -# CONFIG_RT_USING_ALARM is not set -# CONFIG_RT_USING_SOFT_RTC is not set -CONFIG_RT_USING_SDIO=y -CONFIG_RT_SDIO_STACK_SIZE=512 -CONFIG_RT_SDIO_THREAD_PRIORITY=15 -CONFIG_RT_MMCSD_STACK_SIZE=1024 -CONFIG_RT_MMCSD_THREAD_PREORITY=22 -CONFIG_RT_MMCSD_MAX_PARTITION=16 -# CONFIG_RT_SDIO_DEBUG is not set -CONFIG_RT_USING_SPI=y -# CONFIG_RT_USING_SPI_BITOPS is not set -# CONFIG_RT_USING_QSPI is not set -# CONFIG_RT_USING_SPI_MSD is not set -# CONFIG_RT_USING_SFUD is not set -# CONFIG_RT_USING_ENC28J60 is not set -# CONFIG_RT_USING_SPI_WIFI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 - -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -CONFIG_PKG_USING_TFM=y -CONFIG_PKG_TFM_PATH="/packages/security/trusted-firmware-m" -CONFIG_PKG_USING_TFM_NXP_LPC55_V1_BETA=y -# CONFIG_PKG_USING_TFM_LATEST_VERSION is not set -CONFIG_PKG_TFM_VER="nxp-lpc55-v1.0-beta" -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set - -# -# PainterEngine: A cross-platform graphics application framework written in C language -# -# CONFIG_PKG_USING_PAINTERENGINE is not set -# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_RTDUINO is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_ESP_IDF is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set -# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set -# CONFIG_PKG_USING_QPARAM is not set - -# -# Privated Packages of RealThread -# -# CONFIG_PKG_USING_CODEC is not set -# CONFIG_PKG_USING_PLAYER is not set -# CONFIG_PKG_USING_MPLAYER is not set -# CONFIG_PKG_USING_PERSIMMON_SRC is not set -# CONFIG_PKG_USING_JS_PERSIMMON is not set -# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set - -# -# Network Utilities -# -# CONFIG_PKG_USING_WICED is not set -# CONFIG_PKG_USING_CLOUDSDK is not set -# CONFIG_PKG_USING_POWER_MANAGER is not set -# CONFIG_PKG_USING_RT_OTA is not set -# CONFIG_PKG_USING_RTINSIGHT is not set -# CONFIG_PKG_USING_SMARTCONFIG is not set -# CONFIG_PKG_USING_RTX is not set -# CONFIG_RT_USING_TESTCASE is not set -# CONFIG_PKG_USING_NGHTTP2 is not set -# CONFIG_PKG_USING_AVS is not set -# CONFIG_PKG_USING_ALI_LINKKIT is not set -# CONFIG_PKG_USING_STS is not set -# CONFIG_PKG_USING_DLMS is not set -# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set -# CONFIG_PKG_USING_ZBAR is not set -# CONFIG_PKG_USING_MCF is not set -# CONFIG_PKG_USING_URPC is not set -# CONFIG_PKG_USING_DCM is not set -# CONFIG_PKG_USING_EMQ is not set -# CONFIG_PKG_USING_CFGM is not set -# CONFIG_PKG_USING_RT_CMSIS_DAP is not set -# CONFIG_PKG_USING_SMODULE is not set -# CONFIG_PKG_USING_SNFD is not set -# CONFIG_PKG_USING_UDBD is not set -# CONFIG_PKG_USING_BENCHMARK is not set -# CONFIG_PKG_USING_UBJSON is not set -# CONFIG_PKG_USING_DATATYPE is not set -# CONFIG_PKG_USING_FASTFS is not set -# CONFIG_PKG_USING_RIL is not set -# CONFIG_PKG_USING_WATCH_DCM_SVC is not set -# CONFIG_PKG_USING_WATCH_APP_FWK is not set -# CONFIG_PKG_USING_GUI_TEST is not set -# CONFIG_PKG_USING_PMEM is not set -# CONFIG_PKG_USING_LWRDP is not set -# CONFIG_PKG_USING_MASAN is not set -# CONFIG_PKG_USING_BSDIFF_LIB is not set -# CONFIG_PKG_USING_PRC_DIFF is not set - -# -# RT-Thread Smart -# -# CONFIG_PKG_USING_UKERNEL is not set -# CONFIG_PKG_USING_TRACE_AGENT is not set -CONFIG_SOC_LPC55S6X_SERIES=y - -# -# Hardware Drivers Config -# -CONFIG_SOC_LPC55S6X=y - -# -# On-chip Peripheral Drivers -# -# CONFIG_BSP_USING_DMA is not set -CONFIG_BSP_USING_PIN=y -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART0=y -# CONFIG_HW_UART0_BAUDRATE_9600 is not set -CONFIG_HW_UART0_BAUDRATE_115200=y -# CONFIG_BSP_USING_UART2 is not set -CONFIG_BSP_USING_I2C=y -CONFIG_BSP_USING_I2C1=y -CONFIG_HW_I2C1_BAUDRATE_100kHZ=y -# CONFIG_HW_I2C1_BAUDRATE_400kHZ is not set -CONFIG_BSP_USING_I2C4=y -CONFIG_HW_I2C4_BAUDRATE_100kHZ=y -# CONFIG_HW_I2C4_BAUDRATE_400kHZ is not set -CONFIG_BSP_USING_SPI=y -# CONFIG_BSP_USING_SPI3 is not set -CONFIG_BSP_USING_SPI8=y -CONFIG_BSP_USING_ADC=y -CONFIG_BSP_USING_ADC0_CH0=y -# CONFIG_BSP_USING_ADC0_CH1 is not set -CONFIG_BSP_USING_SDIO=y -CONFIG_BSP_USING_RTC=y -# CONFIG_BSP_USING_WDT is not set -CONFIG_BSP_USING_HWTIMER=y -CONFIG_BSP_USING_CTIMER0=y -# CONFIG_BSP_USING_CTIMER1 is not set -# CONFIG_BSP_USING_CTIMER3 is not set -# CONFIG_BSP_USING_CTIMER4 is not set -CONFIG_BSP_USING_PWM=y -CONFIG_BSP_USING_CTIMER2_MAT0=y -# CONFIG_BSP_USING_CTIMER2_MAT1 is not set -# CONFIG_BSP_USING_CTIMER2_MAT2 is not set - -# -# Onboard Peripheral Drivers -# -CONFIG_BSP_USING_LED=y -CONFIG_BSP_USING_KEY=y -CONFIG_BSP_USING_MMA8562=y -CONFIG_BSP_USING_MMA8562I2C="i2c4" - -# -# Board extended module Drivers -# diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/Kconfig b/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/Kconfig deleted file mode 100644 index 73956cbde0..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/Kconfig +++ /dev/null @@ -1,26 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../../.." - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -config SOC_LPC55S6x - bool - select ARCH_ARM_CORTEX_M33 - default y - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" -source "../Libraries/Kconfig" -source "../lpc55s69_nxp_evk/board/Kconfig" diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/SConscript b/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/SConscript deleted file mode 100644 index e12c0b66bb..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/SConscript +++ /dev/null @@ -1,18 +0,0 @@ -# for module compiling -import os -from building import * - -cwd = GetCurrentDir() + '/../lpc55s69_nxp_evk' -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(path, 'SConscript')) - -pkg = GetCurrentDir() + '/packages' -if os.path.isfile(os.path.join(pkg, 'SConscript')): - objs = objs + SConscript(os.path.join(pkg, 'SConscript')) - -Return('objs') diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/SConstruct b/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/SConstruct deleted file mode 100644 index 679bd64947..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/SConstruct +++ /dev/null @@ -1,65 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -try: - from building import * -except: - print('Cannot found RT-Thread root directory, please check RTT_ROOT') - print(RTT_ROOT) - exit(-1) - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -if rtconfig.PLATFORM == 'armcc': - env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, - # overwrite cflags, because cflags has '--C99' - CXXCOM = '$CXX -o $TARGET --cpp -c $CXXFLAGS $_CCCOMCOM $SOURCES') -else: - env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS, - CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES') - -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM in ['iccarm']: - env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(ARFLAGS = ['']) - env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') - -Export('RTT_ROOT') -Export('rtconfig') - -SDK_ROOT = os.path.abspath('./') - -if os.path.exists(SDK_ROOT + '/Libraries'): - libraries_path_prefix = SDK_ROOT + '/Libraries' -else: - libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries' - -SDK_LIB = libraries_path_prefix -Export('SDK_LIB') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) - -objs = objs + SConscript('../Libraries/drivers/SConscript') -objs = objs + SConscript('../Libraries/LPC55S6X/SConscript') - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/project.uvoptx b/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/project.uvoptx deleted file mode 100644 index eb8dbe3130..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/project.uvoptx +++ /dev/null @@ -1,199 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rtthread-lpc55s6x - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 8 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 15 - - - - - - - - - - .\flashdebug.ini - BIN\CMSIS_AGDI_V8M.DLL - - - - 0 - DLGTARM - (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - DLGUARM - - - - 0 - CMSIS_AGDI_V8M - -X"Any" -UAny -O206 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO11 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640.FLM -FS00 -FL098000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FF1LPC55XX_S_640.FLM -FS110000000 -FL198000 -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM) - - - 0 - UL2V8M - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM)) - - - - - 0 - - - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - 1 - 0 - 0 - 2 - 5000000 - - - - - diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/project.uvprojx b/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/project.uvprojx deleted file mode 100644 index 5e9bf6cdd6..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/project.uvprojx +++ /dev/null @@ -1,1314 +0,0 @@ - - - 2.1 -
### uVision Project, (C) Keil Software
- - - rtthread-lpc55s6x - 0x4 - ARM-ADS - 6120000::V6.12::.\ARMCLANG - 6120000::V6.12::.\ARMCLANG - 1 - - - LPC55S69JBD100:cm33_core0 - NXP - NXP.LPC55S69_DFP.1.0.0 - http://mcuxpresso.nxp.com/cmsis_pack/repo/ - IRAM(0x20000000,0x044000) IRAM2(0x04000000,0x8000) IROM(0x00000000,0x098000) XRAM(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE - - - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM)) - 0 - $$Device:LPC55S69JBD100$fsl_device_registers.h - - - - - - - - - - $$Device:LPC55S69JBD100$LPC55S69_cm33_core0.xml - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-lpc55s6x - 1 - 0 - 0 - 1 - 1 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - - - - SARMV8M.DLL - -MPU - TCM.DLL - -pCM33 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4101 - - 1 - BIN\UL2V8M.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M33" - - 0 - 0 - 0 - 1 - 1 - 1 - 0 - 2 - 0 - 1 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x44000 - - - 1 - 0x0 - 0x98000 - - - 1 - 0x40100000 - 0x4000 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x98000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x40100000 - 0x4000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x44000 - - - 0 - 0x4000000 - 0x8000 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 3 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - - --target=arm-arm-none-eabi - CPU_LPC55S69JBD100_cm33_core0, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS, __RTTHREAD__, RT_USING_ARM_LIBC - - ..\lpc55s69_nxp_evk\applications;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\lpc55s69_nxp_evk\board;..\lpc55s69_nxp_evk\board\MCUX_Config\board;..\Libraries\drivers;..\Libraries\drivers\config;..\..\..\components\dfs\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\finsh;.;..\..\..\include;..\Libraries\LPC55S6X\CMSIS\Include;..\Libraries\LPC55S6X\components\codec;..\Libraries\LPC55S6X\LPC55S6X;..\Libraries\LPC55S6X\LPC55S6X\drivers;..\Libraries\LPC55S6X\middleware\sdmmc\inc;..\Libraries\LPC55S6X\middleware\sdmmc\port;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc;packages\trusted-firmware-m-nxp-lpc55-v1.0-beta\interface\include - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x02000000 - - ..\lpc55s69_nxp_evk\board\linker_scripts\LPC55S69_cm33_core0_flash_ns_mdk.scf - - - - - - - - - - - Applications - - - main.c - 1 - ..\lpc55s69_nxp_evk\applications\main.c - - - - - mnt.c - 1 - ..\lpc55s69_nxp_evk\applications\mnt.c - - - - - Compiler - - - syscall_mem.c - 1 - ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - - - - syscalls.c - 1 - ..\..\..\components\libc\compilers\armlibc\syscalls.c - - - - - cctype.c - 1 - ..\..\..\components\libc\compilers\common\cctype.c - - - - - cstdio.c - 1 - ..\..\..\components\libc\compilers\common\cstdio.c - - - - - cstdlib.c - 1 - ..\..\..\components\libc\compilers\common\cstdlib.c - - - - - cstring.c - 1 - ..\..\..\components\libc\compilers\common\cstring.c - - - - - ctime.c - 1 - ..\..\..\components\libc\compilers\common\ctime.c - - - - - cwchar.c - 1 - ..\..\..\components\libc\compilers\common\cwchar.c - - - - - CPU - - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c - - - - - div0.c - 1 - ..\..\..\libcpu\arm\common\div0.c - - - - - showmem.c - 1 - ..\..\..\libcpu\arm\common\showmem.c - - - - - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - - - - - cpuport.c - 1 - ..\..\..\libcpu\arm\cortex-m4\cpuport.c - - - - - DeviceDrivers - - - hwtimer.c - 1 - ..\..\..\components\drivers\hwtimer\hwtimer.c - - - - - i2c-bit-ops.c - 1 - ..\..\..\components\drivers\i2c\i2c-bit-ops.c - - - - - i2c_core.c - 1 - ..\..\..\components\drivers\i2c\i2c_core.c - - - - - i2c_dev.c - 1 - ..\..\..\components\drivers\i2c\i2c_dev.c - - - - - completion.c - 1 - ..\..\..\components\drivers\ipc\completion.c - - - - - dataqueue.c - 1 - ..\..\..\components\drivers\ipc\dataqueue.c - - - - - pipe.c - 1 - ..\..\..\components\drivers\ipc\pipe.c - - - - - ringblk_buf.c - 1 - ..\..\..\components\drivers\ipc\ringblk_buf.c - - - - - ringbuffer.c - 1 - ..\..\..\components\drivers\ipc\ringbuffer.c - - - - - waitqueue.c - 1 - ..\..\..\components\drivers\ipc\waitqueue.c - - - - - workqueue.c - 1 - ..\..\..\components\drivers\ipc\workqueue.c - - - - - adc.c - 1 - ..\..\..\components\drivers\misc\adc.c - - - - - pin.c - 1 - ..\..\..\components\drivers\misc\pin.c - - - - - rt_drv_pwm.c - 1 - ..\..\..\components\drivers\misc\rt_drv_pwm.c - - - - - rtc.c - 1 - ..\..\..\components\drivers\rtc\rtc.c - - - - - block_dev.c - 1 - ..\..\..\components\drivers\sdio\block_dev.c - - - - - mmc.c - 1 - ..\..\..\components\drivers\sdio\mmc.c - - - - - mmcsd_core.c - 1 - ..\..\..\components\drivers\sdio\mmcsd_core.c - - - - - sd.c - 1 - ..\..\..\components\drivers\sdio\sd.c - - - - - sdio.c - 1 - ..\..\..\components\drivers\sdio\sdio.c - - - - - serial.c - 1 - ..\..\..\components\drivers\serial\serial.c - - - - - spi_core.c - 1 - ..\..\..\components\drivers\spi\spi_core.c - - - - - spi_dev.c - 1 - ..\..\..\components\drivers\spi\spi_dev.c - - - - - Drivers - - - clock_config.c - 1 - ..\lpc55s69_nxp_evk\board\MCUX_Config\board\clock_config.c - - - - - pin_mux.c - 1 - ..\lpc55s69_nxp_evk\board\MCUX_Config\board\pin_mux.c - - - - - board.c - 1 - ..\lpc55s69_nxp_evk\board\board.c - - - - - drv_adc.c - 1 - ..\Libraries\drivers\drv_adc.c - - - - - drv_hwtimer.c - 1 - ..\Libraries\drivers\drv_hwtimer.c - - - - - drv_i2c.c - 1 - ..\Libraries\drivers\drv_i2c.c - - - - - drv_key.c - 1 - ..\Libraries\drivers\drv_key.c - - - - - drv_led.c - 1 - ..\Libraries\drivers\drv_led.c - - - - - drv_mma8562.c - 1 - ..\Libraries\drivers\drv_mma8562.c - - - - - drv_pin.c - 1 - ..\Libraries\drivers\drv_pin.c - - - - - drv_pwm.c - 1 - ..\Libraries\drivers\drv_pwm.c - - - - - drv_rtc.c - 1 - ..\Libraries\drivers\drv_rtc.c - - - - - drv_sd.c - 1 - ..\Libraries\drivers\drv_sd.c - - - - - drv_spi.c - 1 - ..\Libraries\drivers\drv_spi.c - - - - - drv_uart.c - 1 - ..\Libraries\drivers\drv_uart.c - - - - - Filesystem - - - devfs.c - 1 - ..\..\..\components\dfs\filesystems\devfs\devfs.c - - - - - dfs_elm.c - 1 - ..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c - - - - - ff.c - 1 - ..\..\..\components\dfs\filesystems\elmfat\ff.c - - - - - ffunicode.c - 1 - ..\..\..\components\dfs\filesystems\elmfat\ffunicode.c - - - - - dfs.c - 1 - ..\..\..\components\dfs\src\dfs.c - - - - - dfs_file.c - 1 - ..\..\..\components\dfs\src\dfs_file.c - - - - - dfs_fs.c - 1 - ..\..\..\components\dfs\src\dfs_fs.c - - - - - dfs_posix.c - 1 - ..\..\..\components\dfs\src\dfs_posix.c - - - - - Finsh - - - shell.c - 1 - ..\..\..\components\finsh\shell.c - - - - - msh.c - 1 - ..\..\..\components\finsh\msh.c - - - - - msh_parse.c - 1 - ..\..\..\components\finsh\msh_parse.c - - - - - cmd.c - 1 - ..\..\..\components\finsh\cmd.c - - - - - msh_file.c - 1 - ..\..\..\components\finsh\msh_file.c - - - - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - - - components.c - 1 - ..\..\..\src\components.c - - - - - device.c - 1 - ..\..\..\src\device.c - - - - - idle.c - 1 - ..\..\..\src\idle.c - - - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - - - irq.c - 1 - ..\..\..\src\irq.c - - - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - - - mem.c - 1 - ..\..\..\src\mem.c - - - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - - - object.c - 1 - ..\..\..\src\object.c - - - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - - - thread.c - 1 - ..\..\..\src\thread.c - - - - - timer.c - 1 - ..\..\..\src\timer.c - - - - - Libraries - - - fsl_hashcrypt.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_hashcrypt.c - - - - - fsl_usart_dma.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_usart_dma.c - - - - - fsl_spi_dma.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_spi_dma.c - - - - - fsl_sdmmc_host.c - 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_host.c - - - - - fsl_sdmmc_event.c - 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\port\sdif\rt_thread\fsl_sdmmc_event.c - - - - - fsl_cmp.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_cmp.c - - - - - fsl_utick.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_utick.c - - - - - fsl_sd.c - 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sd.c - - - - - fsl_power.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_power.c - - - - - fsl_sdmmc_common.c - 1 - ..\Libraries\LPC55S6X\middleware\sdmmc\src\fsl_sdmmc_common.c - - - - - fsl_i2s_dma.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2s_dma.c - - - - - fsl_gpio.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_gpio.c - - - - - fsl_casper.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_casper.c - - - - - fsl_clock.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_clock.c - - - - - fsl_wwdt.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_wwdt.c - - - - - fsl_reset.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_reset.c - - - - - fsl_sctimer.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sctimer.c - - - - - fsl_common.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_common.c - - - - - fsl_rtc.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rtc.c - - - - - fsl_crc.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_crc.c - - - - - fsl_sdif.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_sdif.c - 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- - - - fsl_rng.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_rng.c - - - - - fsl_lpadc.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_lpadc.c - - - - - fsl_inputmux.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_inputmux.c - - - - - fsl_i2c_dma.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c_dma.c - - - - - fsl_prince.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_prince.c - - - - - fsl_i2c.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_i2c.c - - - - - startup_LPC55S69_cm33_core0.s - 2 - ..\Libraries\LPC55S6X\LPC55S6X\arm\startup_LPC55S69_cm33_core0.s - - - - - system_LPC55S69_cm33_core0.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\system_LPC55S69_cm33_core0.c - - - - - arm_keil_lib_power_cm33_core0.lib - 4 - ..\Libraries\LPC55S6X\LPC55S6X\arm\keil_lib_power_cm33_core0.lib - - - - - fsl_anactrl.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_anactrl.c - - - - - fsl_iap.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_iap.c - - - - - fsl_ostimer.c - 1 - ..\Libraries\LPC55S6X\LPC55S6X\drivers\fsl_ostimer.c - - - - - TFM - - - tfm_ns_lock_rt-thread.c - 1 - packages\trusted-firmware-m-nxp-lpc55-v1.0-beta\interface\src\tfm_ns_lock_rt-thread.c - - - - - tfm_sst_api.c - 1 - packages\trusted-firmware-m-nxp-lpc55-v1.0-beta\interface\src\tfm_sst_api.c - - - - - veneers_s_veneers.o - 3 - packages\trusted-firmware-m-nxp-lpc55-v1.0-beta\cmake_build\install\export\tfm\veneers\s_veneers.o - - - - - - - - - - - - diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/rtconfig.h b/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/rtconfig.h deleted file mode 100644 index 325f14ba84..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/rtconfig.h +++ /dev/null @@ -1,269 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -#define SOC_LPC55S6x - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 -#define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 - -/* kservice optimization */ - -#define RT_DEBUG - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "uart" -#define RT_VER_NUM 0x40101 -#define ARCH_ARM -#define RT_USING_CPU_FFS -#define ARCH_ARM_CORTEX_M -#define ARCH_ARM_CORTEX_FPU -#define ARCH_ARM_CORTEX_M33 - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 -#define RT_USING_MSH -#define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 -#define RT_USING_DFS -#define DFS_USING_POSIX -#define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 -#define DFS_FD_MAX 16 -#define RT_USING_DFS_ELMFAT - -/* elm-chan's FatFs, Generic FAT Filesystem Module */ - -#define RT_DFS_ELM_CODE_PAGE 437 -#define RT_DFS_ELM_WORD_ACCESS -#define RT_DFS_ELM_USE_LFN_3 -#define RT_DFS_ELM_USE_LFN 3 -#define RT_DFS_ELM_LFN_UNICODE_0 -#define RT_DFS_ELM_LFN_UNICODE 0 -#define RT_DFS_ELM_MAX_LFN 255 -#define RT_DFS_ELM_DRIVES 2 -#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 -#define RT_DFS_ELM_REENTRANT -#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 -#define RT_USING_DFS_DEVFS - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_USING_DMA -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_HWTIMER -#define RT_USING_I2C -#define RT_USING_I2C_BITOPS -#define RT_USING_PIN -#define RT_USING_ADC -#define RT_USING_PWM -#define RT_USING_RTC -#define RT_USING_SDIO -#define RT_SDIO_STACK_SIZE 512 -#define RT_SDIO_THREAD_PRIORITY 15 -#define RT_MMCSD_STACK_SIZE 1024 -#define RT_MMCSD_THREAD_PREORITY 22 -#define RT_MMCSD_MAX_PARTITION 16 -#define RT_USING_SPI - -/* Using USB */ - - -/* C/C++ and POSIX layer */ - -#define RT_LIBC_DEFAULT_TIMEZONE 8 - -/* POSIX (Portable Operating System Interface) layer */ - - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - - -/* Network */ - - -/* Utilities */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - -#define PKG_USING_TFM -#define PKG_USING_TFM_NXP_LPC55_V1_BETA - -/* language packages */ - -/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ - - -/* XML: Extensible Markup Language */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* PainterEngine: A cross-platform graphics application framework written in C language */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - - -/* Kendryte SDK */ - - -/* AI packages */ - - -/* miscellaneous packages */ - -/* project laboratory */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - - -/* Privated Packages of RealThread */ - - -/* Network Utilities */ - - -/* RT-Thread Smart */ - -#define SOC_LPC55S6X_SERIES - -/* Hardware Drivers Config */ - -#define SOC_LPC55S6X - -/* On-chip Peripheral Drivers */ - -#define BSP_USING_PIN -#define BSP_USING_UART -#define BSP_USING_UART0 -#define HW_UART0_BAUDRATE_115200 -#define BSP_USING_I2C -#define BSP_USING_I2C1 -#define HW_I2C1_BAUDRATE_100kHZ -#define BSP_USING_I2C4 -#define HW_I2C4_BAUDRATE_100kHZ -#define BSP_USING_SPI -#define BSP_USING_SPI8 -#define BSP_USING_ADC -#define BSP_USING_ADC0_CH0 -#define BSP_USING_SDIO -#define BSP_USING_RTC -#define BSP_USING_HWTIMER -#define BSP_USING_CTIMER0 -#define BSP_USING_PWM -#define BSP_USING_CTIMER2_MAT0 - -/* Onboard Peripheral Drivers */ - -#define BSP_USING_LED -#define BSP_USING_KEY -#define BSP_USING_MMA8562 -#define BSP_USING_MMA8562I2C "i2c4" - -/* Board extended module Drivers */ - - -#endif diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/rtconfig.py b/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/rtconfig.py deleted file mode 100644 index a789fbda1f..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/rtconfig.py +++ /dev/null @@ -1,161 +0,0 @@ -import os -import sys - -# toolchains options -ARCH='arm' -CPU='cortex-m4' -CROSS_TOOL='gcc' -BOARD_NAME = 'lpcxpresso' - -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'C:\Users\XXYYZZ' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = r'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iccarm' - EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -BUILD = 'debug' -#BUILD = 'release' - -if PLATFORM == 'gcc': - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - STRIP = PREFIX + 'strip' - - DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' - CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry' - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry' - LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ../lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -gdwarf-2' - AFLAGS += ' -gdwarf-2' - CFLAGS += ' -O0' - else: - CFLAGS += ' -O2 -Os' - - POST_ACTION = OBJCPY + ' -O binary --remove-section=.boot_data --remove-section=.image_vertor_table --remove-section=.ncache $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - - # module setting - CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti ' - M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC ' - M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC' - M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\ - ' -shared -fPIC -nostartfiles -static-libgcc' - M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - CXX = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --cpu ' + CPU + '.fp.sp' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --libpath "' + EXEC_PATH + '/ARM/ARMCC/lib" --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "./LPC55S69_cm33_core0_flash.scf" ' - - LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)' - - CFLAGS += ' --diag_suppress=66,1296,186,6134' - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' - - EXEC_PATH += '/arm/bin40/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - CXXFLAGS = CFLAGS - CFLAGS += ' --c99' - - POST_ACTION = 'fromelf -z $TARGET' - # POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iccarm': - CC = 'iccarm' - CXX = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = ' -D__FPU_PRESENT' - - CFLAGS = DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=' + CPU - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu ' + CPU - AFLAGS += ' --fpu None' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = ' --config "board/linker_scripts/LPC55S69_cm33_core0_flash_iar.icf"' - LFLAGS += ' --redirect _Printf=_PrintfTiny' - LFLAGS += ' --redirect _Scanf=_ScanfSmall' - LFLAGS += ' --entry __iar_program_start' - - CXXFLAGS = CFLAGS - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' - -def dist_handle(BSP_ROOT, dist_dir): - cwd_path = os.getcwd() - sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) - from sdk_dist import dist_do_building - dist_do_building(BSP_ROOT, dist_dir) - diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/template.uvoptx b/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/template.uvoptx deleted file mode 100644 index eb8dbe3130..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/template.uvoptx +++ /dev/null @@ -1,199 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - - 0 - 0 - - - - rtthread-lpc55s6x - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\build\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 8 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 15 - - - - - - - - - - .\flashdebug.ini - BIN\CMSIS_AGDI_V8M.DLL - - - - 0 - DLGTARM - (6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0) - - - 0 - ARMDBGFLAGS - - - - 0 - DLGUARM - - - - 0 - CMSIS_AGDI_V8M - -X"Any" -UAny -O206 -S9 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO11 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640.FLM -FS00 -FL098000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FF1LPC55XX_S_640.FLM -FS110000000 -FL198000 -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM) - - - 0 - UL2V8M - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM)) - - - - - 0 - - - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - 1 - 0 - 0 - 2 - 5000000 - - - - - diff --git a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/template.uvprojx b/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/template.uvprojx deleted file mode 100644 index 93beea542c..0000000000 --- a/bsp/lpc55sxx/lpc55s69_nxp_evk_ns/template.uvprojx +++ /dev/null @@ -1,391 +0,0 @@ - - - - 2.1 - -
### uVision Project, (C) Keil Software
- - - - rtthread-lpc55s6x - 0x4 - ARM-ADS - 6120000::V6.12::.\ARMCLANG - 6120000::V6.12::.\ARMCLANG - 1 - - - LPC55S69JBD100:cm33_core0 - NXP - NXP.LPC55S69_DFP.1.0.0 - http://mcuxpresso.nxp.com/cmsis_pack/repo/ - IRAM(0x20000000,0x044000) IRAM2(0x04000000,0x8000) IROM(0x00000000,0x098000) XRAM(0x40100000,0x4000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE - - - UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000 -FN2 -FF0LPC55XX_640 -FS00 -FL098000 -FF1LPC55XX_S_640 -FS110000000 -FL198000 -FP0($$Device:LPC55S69JBD100$arm\LPC55XX_640.FLM) -FP1($$Device:LPC55S69JBD100$arm\LPC55XX_S_640.FLM)) - 0 - $$Device:LPC55S69JBD100$fsl_device_registers.h - - - - - - - - - - $$Device:LPC55S69JBD100$LPC55S69_cm33_core0.xml - 0 - 0 - - - - - - - 0 - 0 - 0 - 0 - 1 - - .\build\ - rtthread-lpc55s6x - 1 - 0 - 0 - 1 - 1 - .\build\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - - 0 - 0 - - - 0 - 0 - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - 1 - - - - - - - SARMV8M.DLL - -MPU - TCM.DLL - -pCM33 - - - - 1 - 0 - 0 - 0 - 16 - - - - - 1 - 0 - 0 - 1 - 1 - 4101 - - 1 - BIN\UL2V8M.DLL - "" () - - - - - 0 - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M33" - - 0 - 0 - 0 - 1 - 1 - 1 - 0 - 2 - 0 - 1 - 0 - 8 - 0 - 0 - 0 - 0 - 3 - 4 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x44000 - - - 1 - 0x0 - 0x98000 - - - 1 - 0x40100000 - 0x4000 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x98000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x40100000 - 0x4000 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x44000 - - - 0 - 0x4000000 - 0x8000 - - - - - - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 3 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - - --target=arm-arm-none-eabi - CPU_LPC55S69JBD100_cm33_core0, ARM_MATH_CM33, RT_USING_ARM_LIBC - - - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 0 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x02000000 - - ..\lpc55s69_nxp_evk\board\linker_scripts\LPC55S69_cm33_core0_flash_ns_mdk.scf - - - --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab) - - - - - - - - - - - - - - -