mirror of
https://github.com/RT-Thread/rt-thread.git
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[bsp][hpmicro][hpm6e00evk] add hpm6e00evk support
- added hpm6e00evk support Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
This commit is contained in:
Fan YANG
Rbb666
@@ -341,6 +341,7 @@ jobs:
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- "hpmicro/hpm5300evk"
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- "hpmicro/hpm5301evklite"
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- "hpmicro/hpm6800evk"
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- "hpmicro/hpm6e00evk"
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- RTT_BSP: "llvm-arm"
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RTT_TOOL_CHAIN: "llvm-arm"
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SUB_RTT_BSP:
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,12 @@
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mainmenu "RT-Thread Configuration"
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BSP_DIR := .
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RTT_DIR := ../../..
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PKGS_DIR := packages
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source "$(RTT_DIR)/Kconfig"
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osource "$PKGS_DIR/Kconfig"
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rsource "../libraries/Kconfig"
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rsource "board/Kconfig"
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@@ -0,0 +1,115 @@
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# HPMicro HPM6E00EVK BSP(Board Support Package) Introduction
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[中文页](README_zh.md) |
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## Introduction
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This document provides brief introduction of the BSP (board support package) for the HPM6E00EVK development board.
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The document consists of the following parts:
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- HPM6E00EVK Board Resources Introduction
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- Quickly Getting Started
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- Refreences
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By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
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## Board Resources Introduction
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HPM6E00EVK is a development board based on the RISC-V core launched by HPMicro, with rich on-board resources and on-chip resources for Connectivity, Audio, motor control，etc.
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## Peripheral Condition
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Each peripheral supporting condition for this BSP is as follows:
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| **On-board Peripherals** | **Support** | **Note** |
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| ------------------------ | ----------- | ------------------------------------- |
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| USB | √ | |
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| QSPI Flash | √ | |
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| Ethernet | √ | |
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| GPIO | √ | |
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| SPI | √ | |
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| I2C | √ | |
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| RTC | √ | |
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| PWM | √ | |
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| On-Board Debugger | √ | ft2232 |
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## Execution Instruction
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### Quickly Getting Started
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The BSP support being build via the 'scons' command, below is the steps of compiling the example via the 'scons' command
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#### Parpare Environment
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- Step 1: Prepare [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
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- Step 2: Prepare [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
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- Download the package and extract it into a specified directory, for example: `C:\DevTools\riscv32-gnu-toolchain`
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- Step 3: Set environment variable `RTT_RISCV_TOOLCHAIN` to `<TOOLCHAIN_DIR>\bin`
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- For example: `C:\DevTools\riscv32-gnu-toolchain\bin`
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- Step 4: Prepare [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
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- Download and extract it to specified directory, for example: `C:\DevTools\openocd-hpmicro`
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- Add `OpenOCD` environment variable `OPENOCD_HPMICRO` to `<OPENOCD_HPMICRO_DIR>\bin`
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- For example: `C:\DevTools\openocd-hpmicro\bin`
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#### Configure and Build project
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Open RT-Thread ENV command-line, and change directory to this BSP directory, then users can:
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- Configure the project via `menuconfig` in `RT-Thread ENV`
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- Build the project using `scons -jN`, `N` equals to the number of CPU cores
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- Clean the project using `scons -c`
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#### Hardware Connection
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- Switch BOOT pin to 2'b00
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- Connect the `PWR_DEBUG` port to PC via TYPE-C cable
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#### Dowload / Debug
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- Users can download the project via the below command:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
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```
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- Users can debug the project via the below command:
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- Connect debugger via `OpenOCD`:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg
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```
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- Start Debugger via `GDB`:
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```console
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%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
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```
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- In the `gdb shell`, type the following commands:
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```console
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load
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c
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```
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### **Running Results**
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Once the project is successfully downloaded, the system runs automatically. The LED on the board will flash periodically.
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Connect the serial port of the board to the PC, communicate with it via a serial terminal tool(115200-8-1-N). Reset the board and the startup information of RT-Thread will be observed:
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```
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\ | /
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- RT - Thread Operating System
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/ | \ 5.0.1 build Aug 16 2023 18:18:18
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2006 - 2023 Copyright by RT-Thread team
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```
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## **References**
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- [RT-Thread Documnent Center](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
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- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
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- [HPM6800EVK RT-Thread BSP Package](https://github.com/hpmicro/rtt-bsp-hpm6e00evk)
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@@ -0,0 +1,114 @@
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# 先楫 HPM6E00EVK BSP(板级支持包)说明
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[English](README.md) |
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## 简介
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本文档为 HPM6E00EVK 的 BSP (板级支持包) 说明。
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本文包含如下部分:
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- HPM6E00EVK 板级资源介绍
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- 快速上手指南
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- 参考链接
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通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
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## 板级资源介绍
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HPM6800EVK 是由先楫半导体推出的一款基于RISCV内核的开发板，带有丰富的片上资源和板上资源，可用于网络互联、音频和电机控制等应用。
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开发板外观如下图所示：
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## 板载外设
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本 BSP 目前对外设的支持情况如下:
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| **板载外设** | **支持情况** | **备注** |
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| ------------------------ | ----------- | ------------------------------------- |
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| USB | √ | |
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| QSPI Flash | √ | |
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| 以太网 | √ | |
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| GPIO | √ | |
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| SPI | √ | |
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| I2C | √ | |
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| RTC | √ | |
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| PWM | √ | |
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| 板载调试器 | √ | ft2232 |
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## 使用说明
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### 快速开始
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本BSP支持通过`scons`命令来完成编译，在开始之前，需要先准备好开发所需的环境。
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#### 准备环境
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- 步骤 1: 准备 [RT-Thread ENV](https://www.rt-thread.org/download.html#download-rt-thread-env-tool)
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- 步骤 2: 准备 [toolcahin](https://github.com/helloeagleyang/riscv32-gnu-toolchain-win/archive/2022.04.12.zip)
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- 下载并解压到指定的目录，如: `C:\DevTools\riscv32-gnu-toolchain`
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- 步骤 3: 设置环境变量： `RTT_RISCV_TOOLCHAIN` 为 `<TOOLCHAIN_DIR>\bin`， 如: `C:\DevTools\riscv32-gnu-toolchain\bin`
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- 步骤 4: 准备 [OpenOCD](https://github.com/hpmicro/rtt-debugger-support-package/archive/v0.4.0.zip)
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- 下载并解压到指定目录，如: `C:\DevTools\openocd-hpmicro`
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- 将 `OPENOCD_HPMICRO`环境变量设置为 `<OPENOCD_HPMICRO_DIR>\bin`，如： `C:\DevTools\openocd-hpmicro\bin`
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#### 配置和构建工程
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通过 RT-Thread ENV 命令行切换目录到当前BSP所在目录后，用户可以:
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- 通过 `menuconfig` 命令 配置RT-Thread BSP的功能
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- 通过 `scons -jN` 命令完成构建, 其中`N` 最大值可以指定为CP拥有的物理内核数
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- 通过 `scons -c` 命令清除构建
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#### 硬件连接
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- 将BOOT 引脚拨到2'b00
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- 通过 TYPE-C线将板上的 `PWR_DEBUG` 连接到电脑
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#### 下载 和 调试
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- 通过如下命令完成下载:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg -c "init; halt; flash write_image erase rtthread.elf; reset; shutdown"
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```
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- 通过如下命令实现调试:
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- 通过 `OpenOCD` 来连接开发板:
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```console
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%OPENOCD_HPMICRO%\openocd.exe -f boards\debug_scripts\probes\ft2232.cfg -f boards\debug_scripts\soc\hpm6e80-single-core.cfg -f boards\debug_scripts\boards\hpm6e00evk.cfg
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```
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- 通过 `GDB` 实现调试:
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```console
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%RTT_EXEC_PATH%\riscv32-unknown-elf-gdb.exe rtthread.elf
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```
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- 在`GDB Shell`中使用如下命令来加载和运行:
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```console
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load
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c
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```
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### **运行结果**
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一旦成功下载，程序会自动运行并打印如下结果，板载LED灯会周期性闪烁。
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配置好串口终端(串口配置为115200, 8-N-1),按复位键后，串口终端会打印如下日志：
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```
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\ | /
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- RT - Thread Operating System
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/ | \ 5.0.1 build Aug 16 2023 18:18:18
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2006 - 2023 Copyright by RT-Thread team
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```
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## **参考链接**
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- [RT-Thread 文档中心](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/README)
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- [RT-Thread Env](https://github.com/RT-Thread/rtthread-manual-doc/blob/master/env/env.md)
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- [HPM6800EVK RT-Thread BSP 包](https://github.com/hpmicro/rtt-bsp-hpm6e00evk)
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@@ -0,0 +1,17 @@
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# for module compiling
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import os
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Import('RTT_ROOT')
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from building import *
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cwd = GetCurrentDir()
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objs = []
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list = os.listdir(cwd)
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ASFLAGS = ' -I' + cwd
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for d in list:
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path = os.path.join(cwd, d)
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if os.path.isfile(os.path.join(path, 'SConscript')):
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objs = objs + SConscript(os.path.join(d, 'SConscript'))
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Return('objs')
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@@ -0,0 +1,75 @@
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import os
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import sys
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import rtconfig
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if os.getenv('RTT_ROOT'):
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RTT_ROOT = os.getenv('RTT_ROOT')
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else:
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RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../../rt-thread')
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sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
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try:
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from building import *
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except:
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print('Cannot found RT-Thread root directory, please check RTT_ROOT')
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print(RTT_ROOT)
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exit(-1)
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TARGET = 'rtthread.' + rtconfig.TARGET_EXT
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AddOption('--run',
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dest = 'run',
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type='string',
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nargs=1,
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action = 'store',
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default = "",
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help = 'Upload or debug application using openocd')
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DefaultEnvironment(tools=[])
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env = Environment(tools = ['mingw'],
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AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
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CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
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AR = rtconfig.AR, ARFLAGS = '-rc',
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LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS,
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CXXCOM = '$CXX -o $TARGET -c $CXXFLAGS $_CCCOMCOM $SOURCES')
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env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
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env['ASCOM'] = env['ASPPCOM']
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Export('RTT_ROOT')
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Export('rtconfig')
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SDK_ROOT = os.path.abspath('./')
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if os.path.exists(os.path.join(SDK_ROOT, 'libraries')):
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libraries_path_prefix = os.path.join(SDK_ROOT, 'libraries')
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else:
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libraries_path_prefix = os.path.join(os.path.dirname(SDK_ROOT), 'libraries')
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SDK_LIB = libraries_path_prefix
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Export('SDK_LIB')
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GDB = rtconfig.GDB
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# prepare building environment
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objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
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hpm_library = 'hpm_sdk'
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rtconfig.BSP_LIBRARY_TYPE = hpm_library
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# include soc
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objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
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# include libraries
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objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
|
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|
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# include components
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objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'components', 'SConscript')))
|
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|
||||
|
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# includes rtt drivers
|
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objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
|
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|
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# make a building
|
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DoBuilding(TARGET, objs)
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@@ -0,0 +1,14 @@
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import rtconfig
|
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|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
src = Glob('*.c')
|
||||
|
||||
CPPDEFINES=[]
|
||||
CPPPATH = [cwd]
|
||||
|
||||
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,43 @@
|
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/*
|
||||
* Copyright (c) 2021-2024 HPMicro
|
||||
*
|
||||
* Change Logs:
|
||||
* Date Author Notes
|
||||
* 2021-08-13 Fan YANG first version
|
||||
*
|
||||
*/
|
||||
|
||||
#include <rtthread.h>
|
||||
#include <rtdevice.h>
|
||||
#include "rtt_board.h"
|
||||
|
||||
void thread_entry(void *arg);
|
||||
|
||||
int main(void)
|
||||
{
|
||||
app_init_led_pins();
|
||||
|
||||
static uint32_t led_thread_arg = 0;
|
||||
rt_thread_t led_thread = rt_thread_create("led_th", thread_entry, &led_thread_arg, 1024, 1, 10);
|
||||
rt_thread_startup(led_thread);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void thread_entry(void *arg)
|
||||
{
|
||||
while(1){
|
||||
app_led_write(0, APP_LED_ON);
|
||||
rt_thread_mdelay(500);
|
||||
app_led_write(0, APP_LED_OFF);
|
||||
rt_thread_mdelay(500);
|
||||
app_led_write(1, APP_LED_ON);
|
||||
rt_thread_mdelay(500);
|
||||
app_led_write(1, APP_LED_OFF);
|
||||
rt_thread_mdelay(500);
|
||||
app_led_write(2, APP_LED_ON);
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||||
rt_thread_mdelay(500);
|
||||
app_led_write(2, APP_LED_OFF);
|
||||
rt_thread_mdelay(500);
|
||||
}
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,19 @@
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the general drivers
|
||||
src = Split("""
|
||||
board.c
|
||||
rtt_board.c
|
||||
pinmux.c
|
||||
fal_flash_port.c
|
||||
hpm_wm8960.c
|
||||
""")
|
||||
|
||||
CPPPATH = [cwd]
|
||||
CPPDEFINES=['D45', 'HPM6880']
|
||||
|
||||
group = DefineGroup('Board', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,80 @@
|
||||
# Copyright (c) 2024 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
# openocd flash driver argument:
|
||||
# - option0:
|
||||
# [31:28] Flash probe type
|
||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit 6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# [15:8] Dummy cycles
|
||||
# 0 - Auto-probed / detected / default value
|
||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
|
||||
# [7:4] Misc.
|
||||
# 0 - Not used
|
||||
# 1 - SPI mode
|
||||
# 2 - Internal loopback
|
||||
# 3 - External DQS
|
||||
# [3:0] Frequency option
|
||||
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
|
||||
# - option1:
|
||||
# [31:20] Reserved
|
||||
# [19:16] IO voltage
|
||||
# 0 - 3V / 1 - 1.8V
|
||||
# [15:12] Pin group
|
||||
# 0 - 1st group / 1 - 2nd group
|
||||
# [11:8] Connection selection
|
||||
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
|
||||
# [7:0] Drive Strength
|
||||
# 0 - Default value
|
||||
|
||||
# xpi0 configs
|
||||
# - flash driver: hpm_xpi
|
||||
# - flash ctrl index: 0xF3000000
|
||||
# - base address: 0x80000000
|
||||
# - flash size: 0x2000000
|
||||
# - flash option0: 0x7
|
||||
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x7
|
||||
|
||||
proc init_clock {} {
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4002000
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0x1
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4002000
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0x2
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000800
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000810
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000820
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4000830
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0xFFFFFFFF
|
||||
echo "clocks has been enabled!"
|
||||
}
|
||||
|
||||
|
||||
$_TARGET0 configure -event reset-init {
|
||||
init_clock
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event gdb-attach {
|
||||
reset halt
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
# Copyright 2021 hpmicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
adapter srst delay 500
|
||||
|
||||
source [find interface/cmsis-dap.cfg]
|
||||
|
||||
transport select jtag
|
||||
reset_config srst_only
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright 2021 hpmicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
reset_config trst_and_srst
|
||||
adapter srst delay 50
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
|
||||
ftdi_layout_init 0x0208 0x020b
|
||||
ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800
|
||||
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright 2021 hpmicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
reset_config trst_and_srst
|
||||
adapter srst delay 50
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6014
|
||||
|
||||
ftdi_layout_init 0x0018 0x001b
|
||||
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
|
||||
@@ -0,0 +1,11 @@
|
||||
# Copyright 2021 hpmicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
adapter srst delay 500
|
||||
|
||||
source [find interface/jlink.cfg]
|
||||
|
||||
transport select jtag
|
||||
reset_config srst_only
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright 2021 hpmicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
bindto 0.0.0.0
|
||||
adapter speed 10000
|
||||
adapter srst delay 500
|
||||
reset_config srst_only
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi_vid_pid 0x0403 0x6010
|
||||
|
||||
ftdi_layout_init 0x0008 0x010b
|
||||
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
|
||||
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
|
||||
@@ -0,0 +1,63 @@
|
||||
# Copyright (c) 2024 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
|
||||
set _CHIP hpm6e00
|
||||
set _CPUTAPID 0x1000563D
|
||||
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGET0 $_CHIP.cpu0
|
||||
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
|
||||
|
||||
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
|
||||
|
||||
targets $_TARGET0
|
||||
|
||||
proc dmi_write {reg value} {
|
||||
$::_TARGET0 riscv dmi_write ${reg} ${value}
|
||||
}
|
||||
|
||||
proc dmi_read {reg} {
|
||||
set v [$::_TARGET0 riscv dmi_read ${reg}]
|
||||
return ${v}
|
||||
}
|
||||
proc dmi_write_memory {addr value} {
|
||||
dmi_write 0x39 ${addr}
|
||||
dmi_write 0x3C ${value}
|
||||
}
|
||||
|
||||
proc dmi_read_memory {addr} {
|
||||
set sbcs [expr { 0x100000 | [dmi_read 0x38] }]
|
||||
dmi_write 0x38 ${sbcs}
|
||||
dmi_write 0x39 ${addr}
|
||||
set value [dmi_read 0x3C]
|
||||
return ${value}
|
||||
}
|
||||
|
||||
proc release_core1 {} {
|
||||
dmi_write_memory 0xF4002C00 0x1000
|
||||
}
|
||||
|
||||
set _TARGET1 $_CHIP.cpu1
|
||||
target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
|
||||
$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
|
||||
|
||||
$_TARGET1 configure -event examine-start {
|
||||
release_core1
|
||||
}
|
||||
|
||||
$_TARGET1 configure -event reset-deassert-pre {
|
||||
$::_TARGET0 arp_poll
|
||||
release_core1
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event reset-end {
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF4002010
|
||||
$::_TARGET0 riscv dmi_write 0x3C 0x2
|
||||
}
|
||||
|
||||
proc reset_soc {} {
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF410001C
|
||||
$::_TARGET0 riscv dmi_write 0x3C 24000000
|
||||
}
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (c) 2024 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
set _CHIP hpm6e00
|
||||
set _CPUTAPID 0x1000563D
|
||||
jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
|
||||
|
||||
set _TARGET0 $_CHIP.cpu0
|
||||
target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
|
||||
|
||||
$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
|
||||
|
||||
targets $_TARGET0
|
||||
|
||||
proc reset_soc {} {
|
||||
$::_TARGET0 riscv dmi_write 0x39 0xF410001C
|
||||
$::_TARGET0 riscv dmi_write 0x3C 24000000
|
||||
}
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* Copyright (c) 2022 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _FAL_CFG_H_
|
||||
#define _FAL_CFG_H_
|
||||
|
||||
#include <rtconfig.h>
|
||||
#include <board.h>
|
||||
|
||||
#ifdef RT_USING_FAL
|
||||
#define NOR_FLASH_DEV_NAME "norflash0"
|
||||
#define NOR_FLASH_MEM_BASE 0x80000000UL
|
||||
#define NOR_FLASH_SIZE_IN_BYTES 0x1000000UL
|
||||
|
||||
/* ===================== Flash device Configuration ========================= */
|
||||
extern const struct fal_flash_dev stm32f2_onchip_flash;
|
||||
extern struct fal_flash_dev nor_flash0;
|
||||
|
||||
/* flash device table */
|
||||
#define FAL_FLASH_DEV_TABLE \
|
||||
{ \
|
||||
&nor_flash0, \
|
||||
}
|
||||
/* ====================== Partition Configuration ========================== */
|
||||
#ifdef FAL_PART_HAS_TABLE_CFG
|
||||
/* partition table */
|
||||
#ifdef CONFIG_WEBNET_FAL_FS
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 6*1024*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "fs", NOR_FLASH_DEV_NAME, 6*1024*1024, 10*1024*1024, 0}, \
|
||||
}
|
||||
#else
|
||||
#define FAL_PART_TABLE \
|
||||
{ \
|
||||
{FAL_PART_MAGIC_WORD, "app", NOR_FLASH_DEV_NAME, 0, 4*1024*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "easyflash", NOR_FLASH_DEV_NAME, 4*1024*1024, 3*1024*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "download", NOR_FLASH_DEV_NAME, 7*1024*1024, 8*1024*1024, 0}, \
|
||||
{FAL_PART_MAGIC_WORD, "flashdb", NOR_FLASH_DEV_NAME, 15*1024*1024, 1*1024*1024, 0}, \
|
||||
}
|
||||
#endif
|
||||
#endif /* FAL_PART_HAS_TABLE_CFG */
|
||||
#endif /* RT_USING_FAL */
|
||||
|
||||
#endif /* _FAL_CFG_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* Copyright (c) 2023 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef HPM_PINMUX_H
|
||||
#define HPM_PINMUX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
void init_uart_pins(UART_Type *ptr);
|
||||
void init_uart_pin_as_gpio(UART_Type *ptr);
|
||||
void init_i2c_pins_as_gpio(I2C_Type *ptr);
|
||||
void init_i2c_pins(I2C_Type *ptr);
|
||||
void init_femc_pins(void);
|
||||
void init_ppi_pins(void);
|
||||
void init_sdm_pins(void);
|
||||
void init_pwm_pin_as_sdm_clock(void);
|
||||
void init_gpio_pins(void);
|
||||
void init_spi_pins(SPI_Type *ptr);
|
||||
void init_spi_pins_with_gpio_as_cs(SPI_Type *ptr);
|
||||
void init_gptmr_pins(GPTMR_Type *ptr);
|
||||
void init_hall_trgm_pins(void);
|
||||
void init_qei_trgm_pins(void);
|
||||
void init_butn_pins(void);
|
||||
void init_acmp_pins(void);
|
||||
void init_pwm_pins(PWMV2_Type *ptr);
|
||||
void init_usb_pins(void);
|
||||
void init_i2s_pins(I2S_Type *ptr);
|
||||
void init_qeo_pins(QEOV2_Type *ptr);
|
||||
void init_sei_pins(SEI_Type *ptr, uint8_t sei_ctrl_idx);
|
||||
void init_qeiv2_uvw_pins(QEIV2_Type *ptr);
|
||||
void init_qeiv2_ab_pins(QEIV2_Type *ptr);
|
||||
void init_qeiv2_abz_pins(QEIV2_Type *ptr);
|
||||
void init_rdc_pin(void);
|
||||
void init_dao_pins(void);
|
||||
void init_pdm_pins(void);
|
||||
void init_enet_pins(ENET_Type *ptr);
|
||||
void init_enet_pps_pins(void);
|
||||
void init_adc16_pins(void);
|
||||
void init_adc_bldc_pins(void);
|
||||
void init_adc_qeiv2_pins(void);
|
||||
void init_can_pins(MCAN_Type *ptr);
|
||||
void init_led_pins_as_gpio(void);
|
||||
void init_led_pins_as_pwm(void);
|
||||
void init_plb_pins(void);
|
||||
void init_esc_pins(void);
|
||||
void init_esc_in_out_pin(void);
|
||||
void init_tsw_pins(void);
|
||||
void init_tamper_pins(void);
|
||||
void init_pwm_fault_pins(void);
|
||||
void init_uart_break_signal_pin(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* HPM_PINMUX_H */
|
||||
@@ -0,0 +1,131 @@
|
||||
/*
|
||||
* Copyright (c) 2023-2024 HPMicro
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#include "board.h"
|
||||
#include "rtt_board.h"
|
||||
#include "hpm_uart_drv.h"
|
||||
#include "hpm_gpio_drv.h"
|
||||
#include "hpm_pmp_drv.h"
|
||||
#include "assert.h"
|
||||
#include "hpm_clock_drv.h"
|
||||
#include "hpm_sysctl_drv.h"
|
||||
#include <rthw.h>
|
||||
#include <rtthread.h>
|
||||
#include "hpm_dma_mgr.h"
|
||||
#include "hpm_mchtmr_drv.h"
|
||||
|
||||
extern int rt_hw_uart_init(void);
|
||||
void os_tick_config(void);
|
||||
void rtt_board_init(void);
|
||||
|
||||
void rt_hw_board_init(void)
|
||||
{
|
||||
rtt_board_init();
|
||||
|
||||
/* Call the RT-Thread Component Board Initialization */
|
||||
rt_components_board_init();
|
||||
}
|
||||
|
||||
void os_tick_config(void)
|
||||
{
|
||||
sysctl_config_clock(HPM_SYSCTL, clock_node_mchtmr0, clock_source_osc0_clk0, 1);
|
||||
sysctl_add_resource_to_cpu0(HPM_SYSCTL, sysctl_resource_mchtmr0);
|
||||
mchtmr_set_compare_value(HPM_MCHTMR, BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND);
|
||||
enable_mchtmr_irq();
|
||||
}
|
||||
|
||||
void rtt_board_init(void)
|
||||
{
|
||||
board_init_clock();
|
||||
board_init_console();
|
||||
board_init_pmp();
|
||||
|
||||
dma_mgr_init();
|
||||
|
||||
/* initialize memory system */
|
||||
rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
|
||||
|
||||
/* Configure the OS Tick */
|
||||
os_tick_config();
|
||||
|
||||
/* Initialize the UART driver first, because later driver initialization may require the rt_kprintf */
|
||||
rt_hw_uart_init();
|
||||
|
||||
/* Set console device */
|
||||
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
|
||||
}
|
||||
|
||||
void app_init_led_pins(void)
|
||||
{
|
||||
gpio_set_pin_output(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN);
|
||||
gpio_set_pin_output(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN);
|
||||
gpio_set_pin_output(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN);
|
||||
|
||||
gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, APP_LED_OFF);
|
||||
gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, APP_LED_OFF);
|
||||
gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, APP_LED_OFF);
|
||||
}
|
||||
|
||||
void app_led_write(uint32_t index, bool state)
|
||||
{
|
||||
switch (index)
|
||||
{
|
||||
case 0:
|
||||
gpio_write_pin(APP_LED0_GPIO_CTRL, APP_LED0_GPIO_INDEX, APP_LED0_GPIO_PIN, state);
|
||||
break;
|
||||
case 1:
|
||||
gpio_write_pin(APP_LED1_GPIO_CTRL, APP_LED1_GPIO_INDEX, APP_LED1_GPIO_PIN, state);
|
||||
break;
|
||||
case 2:
|
||||
gpio_write_pin(APP_LED2_GPIO_CTRL, APP_LED2_GPIO_INDEX, APP_LED2_GPIO_PIN, state);
|
||||
break;
|
||||
default:
|
||||
/* Suppress the toolchain warnings */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void rt_hw_console_output(const char *str)
|
||||
{
|
||||
while (*str != '\0')
|
||||
{
|
||||
uart_send_byte(BOARD_APP_UART_BASE, *str++);
|
||||
}
|
||||
}
|
||||
|
||||
void app_init_usb_pins(void)
|
||||
{
|
||||
board_init_usb_pins();
|
||||
}
|
||||
|
||||
ATTR_PLACE_AT(".isr_vector") void mchtmr_isr(void)
|
||||
{
|
||||
HPM_MCHTMR->MTIMECMP = HPM_MCHTMR->MTIME + BOARD_MCHTMR_FREQ_IN_HZ / RT_TICK_PER_SECOND;
|
||||
|
||||
rt_tick_increase();
|
||||
}
|
||||
|
||||
void rt_hw_cpu_reset(void)
|
||||
{
|
||||
HPM_PPOR->RESET_ENABLE = (1UL << 31);
|
||||
HPM_PPOR->SOFTWARE_RESET = 1000U;
|
||||
while(1) {
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
|
||||
|
||||
#ifdef RT_USING_CACHE
|
||||
void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
|
||||
{
|
||||
if (ops == RT_HW_CACHE_FLUSH) {
|
||||
l1c_dc_flush((uint32_t)addr, size);
|
||||
} else {
|
||||
l1c_dc_invalidate((uint32_t)addr, size);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright (c) 2021 hpmicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _RTT_BOARD_H
|
||||
#define _RTT_BOARD_H
|
||||
#include "hpm_common.h"
|
||||
#include "hpm_soc.h"
|
||||
|
||||
/* gpio section */
|
||||
#define APP_LED0_GPIO_CTRL HPM_GPIO0
|
||||
#define APP_LED0_GPIO_INDEX GPIO_DI_GPIOE
|
||||
#define APP_LED0_GPIO_PIN 14
|
||||
#define APP_LED1_GPIO_CTRL HPM_GPIO0
|
||||
#define APP_LED1_GPIO_INDEX GPIO_DI_GPIOE
|
||||
#define APP_LED1_GPIO_PIN 15
|
||||
#define APP_LED2_GPIO_CTRL HPM_GPIO0
|
||||
#define APP_LED2_GPIO_INDEX GPIO_DI_GPIOE
|
||||
#define APP_LED2_GPIO_PIN 4
|
||||
#define APP_LED_ON (0)
|
||||
#define APP_LED_OFF (1)
|
||||
|
||||
|
||||
|
||||
/* mchtimer section */
|
||||
#define BOARD_MCHTMR_FREQ_IN_HZ (24000000UL)
|
||||
|
||||
/* CAN section */
|
||||
#define BOARD_CAN_NAME "can4"
|
||||
#define BOARD_CAN_HWFILTER_INDEX (4U)
|
||||
|
||||
/* UART section */
|
||||
#define BOARD_UART_NAME "uart1"
|
||||
#define BOARD_UART_RX_BUFFER_SIZE BSP_UART1_RX_BUFSIZE
|
||||
|
||||
|
||||
/* audio section */
|
||||
#define BOARD_AUDIO_CODEC_I2C_NAME "i2c0"
|
||||
#define BOARD_AUDIO_CODEC_I2S_NAME "i2s0"
|
||||
|
||||
/* PWM section */
|
||||
#define BOARD_PWM_NAME "pwm1"
|
||||
#define BOARD_PWM_CHANNEL (0U)
|
||||
|
||||
#define IRQn_PendSV IRQn_DEBUG0
|
||||
|
||||
/***************************************************************
|
||||
*
|
||||
* RT-Thread related definitions
|
||||
*
|
||||
**************************************************************/
|
||||
extern unsigned int __heap_start__;
|
||||
extern unsigned int __heap_end__;
|
||||
|
||||
#define RT_HW_HEAP_BEGIN ((void*)&__heap_start__)
|
||||
#define RT_HW_HEAP_END ((void*)&__heap_end__)
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint16_t vdd;
|
||||
uint8_t bus_width;
|
||||
uint8_t drive_strength;
|
||||
}sdxc_io_cfg_t;
|
||||
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
|
||||
void app_init_led_pins(void);
|
||||
void app_led_write(uint32_t index, bool state);
|
||||
void app_init_usb_pins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* _RTT_BOARD_H */
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 320 KiB |
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,110 @@
|
||||
# Copyright 2021-2023 HPMicro
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
|
||||
import os
|
||||
import sys
|
||||
|
||||
# toolchains options
|
||||
ARCH='risc-v'
|
||||
CPU='hpmicro'
|
||||
SOC_FAMILY='HPM6E00'
|
||||
CHIP_NAME='HPM6E80'
|
||||
|
||||
CROSS_TOOL='gcc'
|
||||
|
||||
# bsp lib config
|
||||
BSP_LIBRARY_TYPE = None
|
||||
|
||||
# Fallback toolchain info
|
||||
FALLBACK_TOOLCHAIN_VENDOR='RISC-V'
|
||||
FALLBACK_TOOLCHAIN_PKG='RISC-V-GCC-RV32'
|
||||
FALLBACK_TOOLCHAIN_VER='2022-04-12'
|
||||
|
||||
if os.getenv('RTT_CC'):
|
||||
CROSS_TOOL = os.getenv('RTT_CC')
|
||||
|
||||
RTT_EXEC_PATH = os.getenv('RTT_EXEC_PATH')
|
||||
if RTT_EXEC_PATH != None:
|
||||
folders = RTT_EXEC_PATH.split(os.sep)
|
||||
# If the `RT-Thread Env` is from the RT-Thread Studio, generate the RTT_EXEC_PATH using `FALLBACK_TOOLCHAIN_INFO`
|
||||
if 'arm_gcc' in folders and 'platform' in folders:
|
||||
RTT_EXEC_PATH = ''
|
||||
for path in folders:
|
||||
if path != 'platform':
|
||||
RTT_EXEC_PATH = RTT_EXEC_PATH + path + os.sep
|
||||
else:
|
||||
break
|
||||
RTT_EXEC_PATH = os.path.join(RTT_EXEC_PATH, 'repo', 'Extract', 'ToolChain_Support_Packages', FALLBACK_TOOLCHAIN_VENDOR, FALLBACK_TOOLCHAIN_PKG, FALLBACK_TOOLCHAIN_VER, 'bin')
|
||||
# Override the 'RTT_RISCV_TOOLCHAIN' only if the `RT-Thread ENV` is from the RT-Thread Studio
|
||||
if 'platform' in folders:
|
||||
os.environ['RTT_RISCV_TOOLCHAIN'] = RTT_EXEC_PATH
|
||||
|
||||
# cross_tool provides the cross compiler
|
||||
# EXEC_PATH is the compiler path, for example, GNU RISC-V toolchain, IAR
|
||||
if CROSS_TOOL == 'gcc':
|
||||
PLATFORM = 'gcc'
|
||||
if os.getenv('RTT_RISCV_TOOLCHAIN'):
|
||||
EXEC_PATH = os.getenv('RTT_RISCV_TOOLCHAIN')
|
||||
else:
|
||||
EXEC_PATH = r'/opt/riscv-gnu-gcc/bin'
|
||||
else:
|
||||
print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
|
||||
|
||||
BUILD = 'flash_debug'
|
||||
|
||||
if PLATFORM == 'gcc':
|
||||
PREFIX = 'riscv32-unknown-elf-'
|
||||
CC = PREFIX + 'gcc'
|
||||
CXX = PREFIX + 'g++'
|
||||
AS = PREFIX + 'gcc'
|
||||
AR = PREFIX + 'ar'
|
||||
LINK = PREFIX + 'gcc'
|
||||
GDB = PREFIX + 'gdb'
|
||||
TARGET_EXT = 'elf'
|
||||
SIZE = PREFIX + 'size'
|
||||
OBJDUMP = PREFIX + 'objdump'
|
||||
OBJCPY = PREFIX + 'objcopy'
|
||||
STRIP = PREFIX + 'strip'
|
||||
|
||||
ARCH_ABI = ' -mcmodel=medlow '
|
||||
DEVICE = ARCH_ABI + ' -DUSE_NONVECTOR_MODE=1 ' + ' -ffunction-sections -fdata-sections -fno-common '
|
||||
CFLAGS = DEVICE
|
||||
AFLAGS = CFLAGS
|
||||
LFLAGS = ARCH_ABI + ' --specs=nano.specs --specs=nosys.specs -u _printf_float -u _scanf_float -nostartfiles -Wl,--gc-sections '
|
||||
|
||||
CPATH = ''
|
||||
LPATH = ''
|
||||
|
||||
if BUILD == 'ram_debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
CFLAGS += ' -O0'
|
||||
LFLAGS += ' -O0'
|
||||
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
|
||||
elif BUILD == 'ram_release':
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
LINKER_FILE = 'board/linker_scripts/ram_rtt.ld'
|
||||
elif BUILD == 'flash_debug':
|
||||
CFLAGS += ' -gdwarf-2'
|
||||
AFLAGS += ' -gdwarf-2'
|
||||
CFLAGS += ' -O0'
|
||||
LFLAGS += ' -O0'
|
||||
CFLAGS += ' -DFLASH_XIP=1'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
elif BUILD == 'flash_release':
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
CFLAGS += ' -DFLASH_XIP=1'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
else:
|
||||
CFLAGS += ' -O2'
|
||||
LFLAGS += ' -O2'
|
||||
LINKER_FILE = 'board/linker_scripts/flash_rtt.ld'
|
||||
LFLAGS += ' -T ' + LINKER_FILE
|
||||
|
||||
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
|
||||
|
||||
# module setting
|
||||
CXXFLAGS = CFLAGS + ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
|
||||
CFLAGS = CFLAGS + ' -std=gnu11'
|
||||
@@ -0,0 +1,19 @@
|
||||
Import('rtconfig')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
|
||||
# add the startup files
|
||||
|
||||
src = Glob('*.c')
|
||||
|
||||
if rtconfig.PLATFORM == 'gcc':
|
||||
src += [os.path.join('toolchains', 'gcc', 'start.S')]
|
||||
src += [os.path.join('toolchains', 'gcc', 'port_gcc.S')]
|
||||
|
||||
CPPPATH = [cwd]
|
||||
CPPDEFINES=['D45', rtconfig.CHIP_NAME]
|
||||
|
||||
group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
|
||||
|
||||
Return('group')
|
||||
@@ -0,0 +1,128 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2024 HPMicro
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#include "hpm_common.h"
|
||||
#include "hpm_soc.h"
|
||||
#include "hpm_l1c_drv.h"
|
||||
#include <rtthread.h>
|
||||
|
||||
void system_init(void);
|
||||
|
||||
extern int entry(void);
|
||||
|
||||
extern void __libc_init_array(void);
|
||||
extern void __libc_fini_array(void);
|
||||
|
||||
void system_init(void)
|
||||
{
|
||||
disable_global_irq(CSR_MSTATUS_MIE_MASK);
|
||||
disable_irq_from_intc();
|
||||
enable_irq_from_intc();
|
||||
enable_global_irq(CSR_MSTATUS_MIE_MASK);
|
||||
#ifndef CONFIG_NOT_ENABLE_ICACHE
|
||||
l1c_ic_enable();
|
||||
#endif
|
||||
#ifndef CONFIG_NOT_ENABLE_DCACHE
|
||||
l1c_dc_enable();
|
||||
#endif
|
||||
}
|
||||
|
||||
__attribute__((weak)) void c_startup(void)
|
||||
{
|
||||
uint32_t i, size;
|
||||
#ifdef FLASH_XIP
|
||||
extern uint8_t __vector_ram_start__[], __vector_ram_end__[], __vector_load_addr__[];
|
||||
size = __vector_ram_end__ - __vector_ram_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__vector_ram_start__ + i) = *(__vector_load_addr__ + i);
|
||||
}
|
||||
#endif
|
||||
|
||||
extern uint8_t __etext[];
|
||||
extern uint8_t __bss_start__[], __bss_end__[];
|
||||
extern uint8_t __tbss_start__[], __tbss_end__[];
|
||||
extern uint8_t __tdata_start__[], __tdata_end__[];
|
||||
extern uint8_t __data_start__[], __data_end__[];
|
||||
extern uint8_t __noncacheable_bss_start__[], __noncacheable_bss_end__[];
|
||||
extern uint8_t __ramfunc_start__[], __ramfunc_end__[];
|
||||
extern uint8_t __noncacheable_init_start__[], __noncacheable_init_end__[];
|
||||
|
||||
/* tbss section */
|
||||
size = __tbss_end__ - __tbss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__tbss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* bss section */
|
||||
size = __bss_end__ - __bss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__bss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* noncacheable bss section */
|
||||
size = __noncacheable_bss_end__ - __noncacheable_bss_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__noncacheable_bss_start__ + i) = 0;
|
||||
}
|
||||
|
||||
/* tdata section LMA: etext */
|
||||
size = __tdata_end__ - __tdata_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__tdata_start__ + i) = *(__etext + i);
|
||||
}
|
||||
|
||||
/* data section LMA: etext */
|
||||
size = __data_end__ - __data_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__data_start__ + i) = *(__etext + (__tdata_end__ - __tdata_start__) + i);
|
||||
}
|
||||
|
||||
/* ramfunc section LMA: etext + data length */
|
||||
size = __ramfunc_end__ - __ramfunc_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__ramfunc_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + i);
|
||||
}
|
||||
|
||||
/* noncacheable init section LMA: etext + data length + ramfunc length */
|
||||
size = __noncacheable_init_end__ - __noncacheable_init_start__;
|
||||
for (i = 0; i < size; i++) {
|
||||
*(__noncacheable_init_start__ + i) = *(__etext + (__data_end__ - __tdata_start__) + (__ramfunc_end__ - __ramfunc_start__) + i);
|
||||
}
|
||||
}
|
||||
|
||||
__attribute__((weak)) int main(void)
|
||||
{
|
||||
while(1);
|
||||
}
|
||||
|
||||
void reset_handler(void)
|
||||
{
|
||||
/**
|
||||
* Disable preemptive interrupt
|
||||
*/
|
||||
HPM_PLIC->FEATURE = 0;
|
||||
/*
|
||||
* Initialize LMA/VMA sections.
|
||||
* Relocation for any sections that need to be copied from LMA to VMA.
|
||||
*/
|
||||
c_startup();
|
||||
|
||||
/* Call platform specific hardware initialization */
|
||||
system_init();
|
||||
|
||||
/* Do global constructors */
|
||||
__libc_init_array();
|
||||
|
||||
|
||||
|
||||
/* Entry function */
|
||||
entry();
|
||||
}
|
||||
|
||||
|
||||
__attribute__((weak)) void _init()
|
||||
{
|
||||
}
|
||||
@@ -0,0 +1,23 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
#include "cpuport.h"
|
||||
|
||||
.globl rt_hw_do_after_save_above
|
||||
.type rt_hw_do_after_save_above,@function
|
||||
rt_hw_do_after_save_above:
|
||||
addi sp, sp, -4
|
||||
STORE ra, 0 * REGBYTES(sp)
|
||||
|
||||
csrr t1, mcause
|
||||
andi t1, t1, 0x3FF
|
||||
/* get ISR */
|
||||
la t2, trap_entry
|
||||
jalr t2
|
||||
|
||||
LOAD ra, 0 * REGBYTES(sp)
|
||||
addi sp, sp, 4
|
||||
ret
|
||||
@@ -0,0 +1,92 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2023 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
#include <rtconfig.h>
|
||||
#include "hpm_csr_regs.h"
|
||||
.section .start, "ax"
|
||||
|
||||
.global _start
|
||||
.type _start,@function
|
||||
|
||||
_start:
|
||||
/* Initialize global pointer */
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
la tp, __thread_pointer
|
||||
.option pop
|
||||
|
||||
#ifdef __riscv_flen
|
||||
/* Enable FPU */
|
||||
li t0, CSR_MSTATUS_FS_MASK
|
||||
csrrs t0, mstatus, t0
|
||||
|
||||
/* Initialize FCSR */
|
||||
fscsr zero
|
||||
#endif
|
||||
|
||||
#ifdef INIT_EXT_RAM_FOR_DATA
|
||||
la t0, _stack_in_dlm
|
||||
mv sp, t0
|
||||
call _init_ext_ram
|
||||
#endif
|
||||
|
||||
/* Initialize stack pointer */
|
||||
la t0, _stack
|
||||
mv sp, t0
|
||||
|
||||
#ifdef __nds_execit
|
||||
/* Initialize EXEC.IT table */
|
||||
la t0, _ITB_BASE_
|
||||
csrw uitb, t0
|
||||
#endif
|
||||
|
||||
#ifdef __riscv_flen
|
||||
/* Enable FPU */
|
||||
li t0, CSR_MSTATUS_FS_MASK
|
||||
csrrs t0, mstatus, t0
|
||||
|
||||
/* Initialize FCSR */
|
||||
fscsr zero
|
||||
#endif
|
||||
|
||||
#ifdef HPM_USING_VECTOR_PREEMPTED_MODE
|
||||
/* Initial machine trap-vector Base */
|
||||
la t0, __vector_table
|
||||
csrw mtvec, t0
|
||||
/* Enable vectored external PLIC interrupt */
|
||||
csrsi CSR_MMISC_CTL, 2
|
||||
#else
|
||||
/* Initial machine trap-vector Base */
|
||||
la t0, SW_handler
|
||||
csrw mtvec, t0
|
||||
/* Disable vectored external PLIC interrupt */
|
||||
csrci CSR_MMISC_CTL, 2
|
||||
#endif
|
||||
|
||||
/* System reset handler */
|
||||
call reset_handler
|
||||
|
||||
/* Infinite loop, if returned accidently */
|
||||
1: j 1b
|
||||
|
||||
.weak nmi_handler
|
||||
nmi_handler:
|
||||
1: j 1b
|
||||
|
||||
.global default_irq_handler
|
||||
.weak default_irq_handler
|
||||
.align 2
|
||||
default_irq_handler:
|
||||
1: j 1b
|
||||
|
||||
.macro IRQ_HANDLER irq
|
||||
.weak default_isr_\irq
|
||||
.set default_isr_\irq, default_irq_handler
|
||||
.long default_isr_\irq
|
||||
.endm
|
||||
|
||||
#include "vectors.S"
|
||||
@@ -0,0 +1,174 @@
|
||||
/*
|
||||
* Copyright (c) 2021-2024 HPMicro
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*
|
||||
*/
|
||||
.section .vector_table, "a"
|
||||
.global __vector_table
|
||||
.align 9
|
||||
__vector_table:
|
||||
.weak default_isr_trap
|
||||
.set default_isr_trap, SW_handler
|
||||
.long default_isr_trap
|
||||
IRQ_HANDLER 1 /* GPIO0_A IRQ handler */
|
||||
IRQ_HANDLER 2 /* GPIO0_B IRQ handler */
|
||||
IRQ_HANDLER 3 /* GPIO0_C IRQ handler */
|
||||
IRQ_HANDLER 4 /* GPIO0_D IRQ handler */
|
||||
IRQ_HANDLER 5 /* GPIO0_E IRQ handler */
|
||||
IRQ_HANDLER 6 /* GPIO0_F IRQ handler */
|
||||
IRQ_HANDLER 7 /* GPIO0_V IRQ handler */
|
||||
IRQ_HANDLER 8 /* GPIO0_W IRQ handler */
|
||||
IRQ_HANDLER 9 /* GPIO0_X IRQ handler */
|
||||
IRQ_HANDLER 10 /* GPIO0_Y IRQ handler */
|
||||
IRQ_HANDLER 11 /* GPIO0_Z IRQ handler */
|
||||
IRQ_HANDLER 12 /* GPIO1_A IRQ handler */
|
||||
IRQ_HANDLER 13 /* GPIO1_B IRQ handler */
|
||||
IRQ_HANDLER 14 /* GPIO1_C IRQ handler */
|
||||
IRQ_HANDLER 15 /* GPIO1_D IRQ handler */
|
||||
IRQ_HANDLER 16 /* GPIO1_E IRQ handler */
|
||||
IRQ_HANDLER 17 /* GPIO1_F IRQ handler */
|
||||
IRQ_HANDLER 18 /* GPIO1_V IRQ handler */
|
||||
IRQ_HANDLER 19 /* GPIO1_W IRQ handler */
|
||||
IRQ_HANDLER 20 /* GPIO1_X IRQ handler */
|
||||
IRQ_HANDLER 21 /* GPIO1_Y IRQ handler */
|
||||
IRQ_HANDLER 22 /* GPIO1_Z IRQ handler */
|
||||
IRQ_HANDLER 23 /* GPTMR0 IRQ handler */
|
||||
IRQ_HANDLER 24 /* GPTMR1 IRQ handler */
|
||||
IRQ_HANDLER 25 /* GPTMR2 IRQ handler */
|
||||
IRQ_HANDLER 26 /* GPTMR3 IRQ handler */
|
||||
IRQ_HANDLER 27 /* GPTMR4 IRQ handler */
|
||||
IRQ_HANDLER 28 /* GPTMR5 IRQ handler */
|
||||
IRQ_HANDLER 29 /* GPTMR6 IRQ handler */
|
||||
IRQ_HANDLER 30 /* GPTMR7 IRQ handler */
|
||||
IRQ_HANDLER 31 /* UART0 IRQ handler */
|
||||
IRQ_HANDLER 32 /* UART1 IRQ handler */
|
||||
IRQ_HANDLER 33 /* UART2 IRQ handler */
|
||||
IRQ_HANDLER 34 /* UART3 IRQ handler */
|
||||
IRQ_HANDLER 35 /* UART4 IRQ handler */
|
||||
IRQ_HANDLER 36 /* UART5 IRQ handler */
|
||||
IRQ_HANDLER 37 /* UART6 IRQ handler */
|
||||
IRQ_HANDLER 38 /* UART7 IRQ handler */
|
||||
IRQ_HANDLER 39 /* I2C0 IRQ handler */
|
||||
IRQ_HANDLER 40 /* I2C1 IRQ handler */
|
||||
IRQ_HANDLER 41 /* I2C2 IRQ handler */
|
||||
IRQ_HANDLER 42 /* I2C3 IRQ handler */
|
||||
IRQ_HANDLER 43 /* SPI0 IRQ handler */
|
||||
IRQ_HANDLER 44 /* SPI1 IRQ handler */
|
||||
IRQ_HANDLER 45 /* SPI2 IRQ handler */
|
||||
IRQ_HANDLER 46 /* SPI3 IRQ handler */
|
||||
IRQ_HANDLER 47 /* TSNS IRQ handler */
|
||||
IRQ_HANDLER 48 /* MBX0A IRQ handler */
|
||||
IRQ_HANDLER 49 /* MBX0B IRQ handler */
|
||||
IRQ_HANDLER 50 /* MBX1A IRQ handler */
|
||||
IRQ_HANDLER 51 /* MBX1B IRQ handler */
|
||||
IRQ_HANDLER 52 /* EWDG0 IRQ handler */
|
||||
IRQ_HANDLER 53 /* EWDG1 IRQ handler */
|
||||
IRQ_HANDLER 54 /* EWDG2 IRQ handler */
|
||||
IRQ_HANDLER 55 /* EWDG3 IRQ handler */
|
||||
IRQ_HANDLER 56 /* HDMA IRQ handler */
|
||||
IRQ_HANDLER 57 /* LOBS IRQ handler */
|
||||
IRQ_HANDLER 58 /* ADC0 IRQ handler */
|
||||
IRQ_HANDLER 59 /* ADC1 IRQ handler */
|
||||
IRQ_HANDLER 60 /* ADC2 IRQ handler */
|
||||
IRQ_HANDLER 61 /* ADC3 IRQ handler */
|
||||
IRQ_HANDLER 62 /* ACMP0[0] IRQ handler */
|
||||
IRQ_HANDLER 63 /* ACMP0[1] IRQ handler */
|
||||
IRQ_HANDLER 64 /* ACMP1[0] IRQ handler */
|
||||
IRQ_HANDLER 65 /* ACMP1[1] IRQ handler */
|
||||
IRQ_HANDLER 66 /* ACMP2[0] IRQ handler */
|
||||
IRQ_HANDLER 67 /* ACMP2[1] IRQ handler */
|
||||
IRQ_HANDLER 68 /* ACMP3[0] IRQ handler */
|
||||
IRQ_HANDLER 69 /* ACMP3[1] IRQ handler */
|
||||
IRQ_HANDLER 70 /* I2S0 IRQ handler */
|
||||
IRQ_HANDLER 71 /* I2S1 IRQ handler */
|
||||
IRQ_HANDLER 72 /* DAO IRQ handler */
|
||||
IRQ_HANDLER 73 /* PDM IRQ handler */
|
||||
IRQ_HANDLER 74 /* UART8 IRQ handler */
|
||||
IRQ_HANDLER 75 /* UART9 IRQ handler */
|
||||
IRQ_HANDLER 76 /* UART10 IRQ handler */
|
||||
IRQ_HANDLER 77 /* UART11 IRQ handler */
|
||||
IRQ_HANDLER 78 /* UART12 IRQ handler */
|
||||
IRQ_HANDLER 79 /* UART13 IRQ handler */
|
||||
IRQ_HANDLER 80 /* UART14 IRQ handler */
|
||||
IRQ_HANDLER 81 /* UART15 IRQ handler */
|
||||
IRQ_HANDLER 82 /* I2C4 IRQ handler */
|
||||
IRQ_HANDLER 83 /* I2C5 IRQ handler */
|
||||
IRQ_HANDLER 84 /* I2C6 IRQ handler */
|
||||
IRQ_HANDLER 85 /* I2C7 IRQ handler */
|
||||
IRQ_HANDLER 86 /* SPI4 IRQ handler */
|
||||
IRQ_HANDLER 87 /* SPI5 IRQ handler */
|
||||
IRQ_HANDLER 88 /* SPI6 IRQ handler */
|
||||
IRQ_HANDLER 89 /* SPI7 IRQ handler */
|
||||
IRQ_HANDLER 90 /* MCAN0 IRQ handler */
|
||||
IRQ_HANDLER 91 /* MCAN1 IRQ handler */
|
||||
IRQ_HANDLER 92 /* MCAN2 IRQ handler */
|
||||
IRQ_HANDLER 93 /* MCAN3 IRQ handler */
|
||||
IRQ_HANDLER 94 /* MCAN4 IRQ handler */
|
||||
IRQ_HANDLER 95 /* MCAN5 IRQ handler */
|
||||
IRQ_HANDLER 96 /* MCAN6 IRQ handler */
|
||||
IRQ_HANDLER 97 /* MCAN7 IRQ handler */
|
||||
IRQ_HANDLER 98 /* PTPC IRQ handler */
|
||||
IRQ_HANDLER 99 /* QEI0 IRQ handler */
|
||||
IRQ_HANDLER 100 /* QEI1 IRQ handler */
|
||||
IRQ_HANDLER 101 /* QEI2 IRQ handler */
|
||||
IRQ_HANDLER 102 /* QEI3 IRQ handler */
|
||||
IRQ_HANDLER 103 /* PWM0 IRQ handler */
|
||||
IRQ_HANDLER 104 /* PWM1 IRQ handler */
|
||||
IRQ_HANDLER 105 /* PWM2 IRQ handler */
|
||||
IRQ_HANDLER 106 /* PWM3 IRQ handler */
|
||||
IRQ_HANDLER 107 /* RDC0 IRQ handler */
|
||||
IRQ_HANDLER 108 /* RDC1 IRQ handler */
|
||||
IRQ_HANDLER 109 /* SDM0 IRQ handler */
|
||||
IRQ_HANDLER 110 /* SDM1 IRQ handler */
|
||||
IRQ_HANDLER 111 /* SEI[0] IRQ handler */
|
||||
IRQ_HANDLER 112 /* SEI[1] IRQ handler */
|
||||
IRQ_HANDLER 113 /* SEI[2] IRQ handler */
|
||||
IRQ_HANDLER 114 /* SEI[3] IRQ handler */
|
||||
IRQ_HANDLER 115 /* MTG0 IRQ handler */
|
||||
IRQ_HANDLER 116 /* MTG1 IRQ handler */
|
||||
IRQ_HANDLER 117 /* VSC0 IRQ handler */
|
||||
IRQ_HANDLER 118 /* VSC1 IRQ handler */
|
||||
IRQ_HANDLER 119 /* CLC0[0] IRQ handler */
|
||||
IRQ_HANDLER 120 /* CLC0[1] IRQ handler */
|
||||
IRQ_HANDLER 121 /* CLC1[0] IRQ handler */
|
||||
IRQ_HANDLER 122 /* CLC1[1] IRQ handler */
|
||||
IRQ_HANDLER 123 /* TRGMUX0 IRQ handler */
|
||||
IRQ_HANDLER 124 /* TRGMUX1 IRQ handler */
|
||||
IRQ_HANDLER 125 /* ENET0 IRQ handler */
|
||||
IRQ_HANDLER 126 /* NTMR0 IRQ handler */
|
||||
IRQ_HANDLER 127 /* USB0 IRQ handler */
|
||||
IRQ_HANDLER 128 /* TSW[0] IRQ handler */
|
||||
IRQ_HANDLER 129 /* TSW[1] IRQ handler */
|
||||
IRQ_HANDLER 130 /* TSW[2] IRQ handler */
|
||||
IRQ_HANDLER 131 /* TSW[3] IRQ handler */
|
||||
IRQ_HANDLER 132 /* TSW_PTP_EVT IRQ handler */
|
||||
IRQ_HANDLER 133 /* ESC IRQ handler */
|
||||
IRQ_HANDLER 134 /* ESC_SYNC0 IRQ handler */
|
||||
IRQ_HANDLER 135 /* ESC_SYNC1 IRQ handler */
|
||||
IRQ_HANDLER 136 /* ESC_RESET IRQ handler */
|
||||
IRQ_HANDLER 137 /* XPI0 IRQ handler */
|
||||
IRQ_HANDLER 138 /* FEMC IRQ handler */
|
||||
IRQ_HANDLER 139 /* PPI IRQ handler */
|
||||
IRQ_HANDLER 140 /* XDMA IRQ handler */
|
||||
IRQ_HANDLER 141 /* FFA IRQ handler */
|
||||
IRQ_HANDLER 142 /* SDP IRQ handler */
|
||||
IRQ_HANDLER 143 /* RNG IRQ handler */
|
||||
IRQ_HANDLER 144 /* PKA IRQ handler */
|
||||
IRQ_HANDLER 145 /* PSEC IRQ handler */
|
||||
IRQ_HANDLER 146 /* PGPIO IRQ handler */
|
||||
IRQ_HANDLER 147 /* PEWDG IRQ handler */
|
||||
IRQ_HANDLER 148 /* PTMR IRQ handler */
|
||||
IRQ_HANDLER 149 /* PUART IRQ handler */
|
||||
IRQ_HANDLER 150 /* FUSE IRQ handler */
|
||||
IRQ_HANDLER 151 /* SECMON IRQ handler */
|
||||
IRQ_HANDLER 152 /* RTC IRQ handler */
|
||||
IRQ_HANDLER 153 /* PAD_WAKEUP IRQ handler */
|
||||
IRQ_HANDLER 154 /* BGPIO IRQ handler */
|
||||
IRQ_HANDLER 155 /* BVIO IRQ handler */
|
||||
IRQ_HANDLER 156 /* BROWNOUT IRQ handler */
|
||||
IRQ_HANDLER 157 /* SYSCTL IRQ handler */
|
||||
IRQ_HANDLER 158 /* CPU0 IRQ handler */
|
||||
IRQ_HANDLER 159 /* CPU1 IRQ handler */
|
||||
IRQ_HANDLER 160 /* DEBUG0 IRQ handler */
|
||||
IRQ_HANDLER 161 /* DEBUG1 IRQ handler */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,13 @@
|
||||
# for module compiling
|
||||
import os
|
||||
Import('rtconfig')
|
||||
Import('RTT_ROOT')
|
||||
from building import *
|
||||
|
||||
cwd = GetCurrentDir()
|
||||
objs = []
|
||||
|
||||
objs = objs + SConscript(os.path.join(cwd, rtconfig.CHIP_NAME, 'SConscript'))
|
||||
ASFLAGS = ' -I' + cwd
|
||||
|
||||
Return('objs')
|
||||
Reference in New Issue
Block a user