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[bsp][hpmicro] upgrade hpm_sdk to v1.6.0

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- upgraded hpm_sdk to v1.6.0

Signed-off-by: Fan YANG <fan.yang@hpmicro.com>
This commit is contained in:
Fan YANG
2024-08-26 10:41:15 +08:00
committed by Rbb666
parent a8ff514d09
commit e19b63e5fb
903 changed files with 355984 additions and 9877 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/hpmicro/hpm5300evk/SConstruct
+1 -1
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@@ -59,7 +59,7 @@ hpm_library = 'hpm_sdk'
rtconfig.BSP_LIBRARY_TYPE = hpm_library
# include soc
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
bsp/hpmicro/hpm5300evk/board/rtt_board.c
+11
View File
@@ -116,3 +116,14 @@ void rt_hw_cpu_reset(void)
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
#ifdef RT_USING_CACHE
void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
{
if (ops == RT_HW_CACHE_FLUSH) {
l1c_dc_flush((uint32_t)addr, size);
} else {
l1c_dc_invalidate((uint32_t)addr, size);
}
}
#endif
bsp/hpmicro/hpm5300evk/rtconfig.py
+1
View File
@@ -7,6 +7,7 @@ import sys
# toolchains options
ARCH='risc-v'
CPU='hpmicro'
SOC_FAMILY='HPM5300'
CHIP_NAME='HPM5361'
CROSS_TOOL='gcc'
bsp/hpmicro/hpm5301evklite/SConstruct
+1 -1
View File
@@ -59,7 +59,7 @@ hpm_library = 'hpm_sdk'
rtconfig.BSP_LIBRARY_TYPE = hpm_library
# include soc
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
bsp/hpmicro/hpm5301evklite/rtconfig.py
+1
View File
@@ -7,6 +7,7 @@ import sys
# toolchains options
ARCH='risc-v'
CPU='hpmicro'
SOC_FAMILY='HPM5300'
CHIP_NAME='HPM5301'
CROSS_TOOL='gcc'
bsp/hpmicro/hpm6200evk/.config
+125 -31
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/hpm6200evk/SConstruct
+1 -1
View File
@@ -59,7 +59,7 @@ hpm_library = 'hpm_sdk'
rtconfig.BSP_LIBRARY_TYPE = hpm_library
# include soc
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
bsp/hpmicro/hpm6200evk/board/board.c
+2 -3
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023 HPMicro
* Copyright (c) 2023-2024 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*
*
@@ -8,7 +8,6 @@
#include "board.h"
#include "hpm_uart_drv.h"
#include "hpm_gptmr_drv.h"
#include "hpm_lcdc_drv.h"
#include "hpm_i2c_drv.h"
#include "hpm_gpio_drv.h"
#include "pinmux.h"
@@ -520,7 +519,7 @@ void board_init_clock(void)
clock_add_to_group(clock_mot2, 0);
clock_add_to_group(clock_mot3, 0);
clock_add_to_group(clock_acmp, 0);
clock_add_to_group(clock_msyn, 0);
clock_add_to_group(clock_synt, 0);
clock_add_to_group(clock_lmm0, 0);
clock_add_to_group(clock_lmm1, 0);
bsp/hpmicro/hpm6200evk/board/rtt_board.c
+11
View File
@@ -116,3 +116,14 @@ void rt_hw_cpu_reset(void)
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
#ifdef RT_USING_CACHE
void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
{
if (ops == RT_HW_CACHE_FLUSH) {
l1c_dc_flush((uint32_t)addr, size);
} else {
l1c_dc_invalidate((uint32_t)addr, size);
}
}
#endif
bsp/hpmicro/hpm6200evk/rtconfig.h
+77 -11
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/hpm6200evk/rtconfig.py
+1
View File
@@ -7,6 +7,7 @@ import sys
# toolchains options
ARCH='risc-v'
CPU='hpmicro'
SOC_FAMILY='HPM6200'
CHIP_NAME='HPM6280'
CROSS_TOOL='gcc'
bsp/hpmicro/hpm6300evk/SConstruct
+1 -1
View File
@@ -59,7 +59,7 @@ hpm_library = 'hpm_sdk'
rtconfig.BSP_LIBRARY_TYPE = hpm_library
# include soc
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
bsp/hpmicro/hpm6300evk/board/board.c
+13 -18
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023 HPMicro
* Copyright (c) 2022-2024 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*
*/
@@ -7,7 +7,6 @@
#include "board.h"
#include "hpm_uart_drv.h"
#include "hpm_gptmr_drv.h"
#include "hpm_lcdc_drv.h"
#include "hpm_i2c_drv.h"
#include "hpm_gpio_drv.h"
#include "hpm_femc_drv.h"
@@ -458,7 +457,7 @@ void board_init_clock(void)
clock_add_to_group(clock_mot1, 0);
clock_add_to_group(clock_acmp, 0);
clock_add_to_group(clock_dao, 0);
clock_add_to_group(clock_msyn, 0);
clock_add_to_group(clock_synt, 0);
clock_add_to_group(clock_lmm0, 0);
clock_add_to_group(clock_pdm, 0);
@@ -647,9 +646,10 @@ void _init_ext_ram(void)
femc_sdram_config_t sdram_config = {0};
femc_default_config(HPM_FEMC, &config);
config.dqs = FEMC_DQS_INTERNAL;
femc_init(HPM_FEMC, &config);
femc_get_typical_sdram_config(HPM_FEMC, &sdram_config);
sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4;
sdram_config.prescaler = 0x3;
sdram_config.burst_len_in_byte = 8;
@@ -657,18 +657,14 @@ void _init_ext_ram(void)
sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS;
sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;
sdram_config.precharge_to_act_in_ns = 18; /* Trp */
sdram_config.act_to_rw_in_ns = 18; /* Trcd */
sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */
sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
sdram_config.cke_off_in_ns = 42; /* Trcd */
sdram_config.act_to_precharge_in_ns = 42; /* Tras */
sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */
sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */
sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */
sdram_config.refresh_recover_in_ns = 60; /* Trc */
sdram_config.act_to_precharge_in_ns = 42; /* Tras */
sdram_config.act_to_rw_in_ns = 18; /* Trcd */
sdram_config.precharge_to_act_in_ns = 18; /* Trp */
sdram_config.act_to_act_in_ns = 12; /* Trrd */
sdram_config.idle_timeout_in_ns = 6;
sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED;
sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
sdram_config.self_refresh_recover_in_ns = 72; /* Txsr */
sdram_config.cs = BOARD_SDRAM_CS;
sdram_config.base_address = BOARD_SDRAM_ADDRESS;
@@ -676,9 +672,8 @@ void _init_ext_ram(void)
sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE;
sdram_config.delay_cell_disable = false;
sdram_config.delay_cell_value = 29;
sdram_config.delay_cell_disable = true;
sdram_config.delay_cell_value = 0;
femc_config_sdram(HPM_FEMC, femc_clk_in_hz, &sdram_config);
}
bsp/hpmicro/hpm6300evk/board/rtt_board.c
+11
View File
@@ -116,3 +116,14 @@ void rt_hw_cpu_reset(void)
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
#ifdef RT_USING_CACHE
void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
{
if (ops == RT_HW_CACHE_FLUSH) {
l1c_dc_flush((uint32_t)addr, size);
} else {
l1c_dc_invalidate((uint32_t)addr, size);
}
}
#endif
bsp/hpmicro/hpm6300evk/rtconfig.py
+1
View File
@@ -7,6 +7,7 @@ import sys
# toolchains options
ARCH='risc-v'
CPU='hpmicro'
SOC_FAMILY='HPM6300'
CHIP_NAME='HPM6360'
CROSS_TOOL='gcc'
bsp/hpmicro/hpm6750evk/SConstruct
+1 -1
View File
@@ -59,7 +59,7 @@ hpm_library = 'hpm_sdk'
rtconfig.BSP_LIBRARY_TYPE = hpm_library
# include soc
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
bsp/hpmicro/hpm6750evk/board/board.c
+11 -14
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023 HPMicro
* Copyright (c) 2021-2024 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*
*/
@@ -717,7 +717,7 @@ void board_init_clock(void)
clock_add_to_group(clock_mot3, 0);
clock_add_to_group(clock_acmp, 0);
clock_add_to_group(clock_dao, 0);
clock_add_to_group(clock_msyn, 0);
clock_add_to_group(clock_synt, 0);
clock_add_to_group(clock_lmm0, 0);
clock_add_to_group(clock_lmm1, 0);
clock_add_to_group(clock_pdm, 0);
@@ -1058,6 +1058,8 @@ void _init_ext_ram(void)
femc_default_config(HPM_FEMC, &config);
femc_init(HPM_FEMC, &config);
femc_get_typical_sdram_config(HPM_FEMC, &sdram_config);
sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4;
sdram_config.prescaler = 0x3;
sdram_config.burst_len_in_byte = 8;
@@ -1065,18 +1067,14 @@ void _init_ext_ram(void)
sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS;
sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;
sdram_config.precharge_to_act_in_ns = 18; /* Trp */
sdram_config.act_to_rw_in_ns = 18; /* Trcd */
sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */
sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
sdram_config.cke_off_in_ns = 42; /* Trcd */
sdram_config.act_to_precharge_in_ns = 42; /* Tras */
sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */
sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */
sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */
sdram_config.refresh_recover_in_ns = 60; /* Trc */
sdram_config.act_to_precharge_in_ns = 42; /* Tras */
sdram_config.act_to_rw_in_ns = 18; /* Trcd */
sdram_config.precharge_to_act_in_ns = 18; /* Trp */
sdram_config.act_to_act_in_ns = 12; /* Trrd */
sdram_config.idle_timeout_in_ns = 6;
sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED;
sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
sdram_config.self_refresh_recover_in_ns = 72; /* Txsr */
sdram_config.cs = BOARD_SDRAM_CS;
sdram_config.base_address = BOARD_SDRAM_ADDRESS;
@@ -1084,7 +1082,6 @@ void _init_ext_ram(void)
sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE;
sdram_config.delay_cell_disable = true;
sdram_config.delay_cell_value = 0;
bsp/hpmicro/hpm6750evk/rtconfig.py
+1
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@@ -7,6 +7,7 @@ import sys
# toolchains options
ARCH='risc-v'
CPU='hpmicro'
SOC_FAMILY='HPM6700'
CHIP_NAME='HPM6750'
CROSS_TOOL='gcc'
bsp/hpmicro/hpm6750evk2/.config
+39 -10
View File
@@ -14,7 +14,6 @@ CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
# CONFIG_RT_USING_HOOKLIST is not set
@@ -24,6 +23,8 @@ CONFIG_IDLE_THREAD_STACK_SIZE=2048
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
# CONFIG_RT_USING_TIMER_ALL_SOFT is not set
# CONFIG_RT_USING_CPU_USAGE_TRACER is not set
#
# kservice optimization
@@ -136,6 +137,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
# Device Drivers
#
# CONFIG_RT_USING_DM is not set
# CONFIG_RT_USING_DEV_BUS is not set
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_UNAMED_PIPE_NUMBER=64
CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
@@ -156,6 +158,8 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_ZERO is not set
# CONFIG_RT_USING_RANDOM is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
@@ -170,9 +174,6 @@ CONFIG_RT_USING_RTC=y
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_LCD is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_DEV_BUS is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_VIRTIO is not set
CONFIG_RT_USING_PIN=y
@@ -191,16 +192,17 @@ CONFIG_RT_CHERRYUSB_HOST_EHCI_HPM=y
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ST is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_ESP is not set
# CONFIG_RT_CHERRYUSB_HOST_DWC2_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_STANDARD is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_ES is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_SUNXI is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_BK is not set
# CONFIG_RT_CHERRYUSB_HOST_MUSB_CUSTOM is not set
# CONFIG_RT_CHERRYUSB_HOST_PUSB2 is not set
# CONFIG_RT_CHERRYUSB_HOST_XHCI is not set
CONFIG_RT_CHERRYUSB_HOST_CDC_ACM=y
CONFIG_RT_CHERRYUSB_HOST_HID=y
# CONFIG_RT_CHERRYUSB_HOST_MSC is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_RNDIS is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_ECM is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_RNDIS is not set
# CONFIG_RT_CHERRYUSB_HOST_CDC_NCM is not set
# CONFIG_RT_CHERRYUSB_HOST_VIDEO is not set
# CONFIG_RT_CHERRYUSB_HOST_AUDIO is not set
@@ -211,9 +213,7 @@ CONFIG_RT_CHERRYUSB_HOST_HID=y
# CONFIG_RT_CHERRYUSB_HOST_CH34X is not set
# CONFIG_RT_CHERRYUSB_HOST_CP210X is not set
# CONFIG_RT_CHERRYUSB_HOST_PL2303 is not set
CONFIG_RT_CHERRYUSB_HOST_TEMPLATE=y
CONFIG_TEST_USBH_CDC_ACM=1
CONFIG_TEST_USBH_HID=1
# CONFIG_CHERRYUSB_HOST_TEMPLATE is not set
# end of Device Drivers
#
@@ -291,6 +291,7 @@ CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_LINK_STATUS_CALLBACK is not set
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
@@ -385,6 +386,8 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
# end of Using USB legacy version
# CONFIG_RT_USING_FDT is not set
# end of RT-Thread Components
#
@@ -412,6 +415,7 @@ CONFIG_RT_LWIP_USING_PING=y
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_NANOPB is not set
# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set
#
# Wi-Fi
@@ -674,6 +678,8 @@ CONFIG_PKG_NETUTILS_VER_NUM=0x99999
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
# end of enhanced kernel services
# CONFIG_PKG_USING_AUNITY is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
@@ -770,6 +776,21 @@ CONFIG_PKG_NETUTILS_VER_NUM=0x99999
# CONFIG_PKG_USING_STM32_SDIO is not set
# end of STM32 HAL & SDK Drivers
#
# Infineon HAL Packages
#
# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set
# CONFIG_PKG_USING_INFINEON_CMSIS is not set
# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set
# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set
# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set
# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set
# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set
# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set
# CONFIG_PKG_USING_INFINEON_USBDEV is not set
# end of Infineon HAL Packages
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_ESP_IDF is not set
@@ -963,6 +984,7 @@ CONFIG_PKG_NETUTILS_VER_NUM=0x99999
#
# Signal Processing and Control Algorithm Packages
#
# CONFIG_PKG_USING_APID is not set
# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
# CONFIG_PKG_USING_QPID is not set
# CONFIG_PKG_USING_UKAL is not set
@@ -1306,9 +1328,16 @@ CONFIG_BSP_USING_RTC=y
# CONFIG_BSP_USING_DAO is not set
# CONFIG_BSP_USING_PDM is not set
# CONFIG_BSP_USING_I2S is not set
# CONFIG_BSP_USING_USB is not set
CONFIG_BSP_USING_USB=y
CONFIG_BSP_USING_USB_DEVICE=y
# CONFIG_BSP_USING_USB_HOST is not set
# CONFIG_BSP_USING_WDG is not set
# CONFIG_BSP_USING_CAN is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_CAMERA is not set
# CONFIG_BSP_USING_JPEG is not set
# CONFIG_BSP_USING_CAM is not set
# CONFIG_BSP_USING_PANEL is not set
# CONFIG_BSP_USING_RTT_LCD_DRIVER is not set
# end of On-chip Peripheral Drivers
# end of Hardware Drivers Config
bsp/hpmicro/hpm6750evk2/SConstruct
+1 -1
View File
@@ -59,7 +59,7 @@ hpm_library = 'hpm_sdk'
rtconfig.BSP_LIBRARY_TYPE = hpm_library
# include soc
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
bsp/hpmicro/hpm6750evk2/board/board.c
+11 -14
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023 HPMicro
* Copyright (c) 2021-2024 HPMicro
* SPDX-License-Identifier: BSD-3-Clause
*
*/
@@ -688,7 +688,7 @@ void board_init_clock(void)
clock_add_to_group(clock_mot3, 0);
clock_add_to_group(clock_acmp, 0);
clock_add_to_group(clock_dao, 0);
clock_add_to_group(clock_msyn, 0);
clock_add_to_group(clock_synt, 0);
clock_add_to_group(clock_lmm0, 0);
clock_add_to_group(clock_lmm1, 0);
clock_add_to_group(clock_pdm, 0);
@@ -1008,6 +1008,8 @@ void _init_ext_ram(void)
femc_default_config(HPM_FEMC, &config);
femc_init(HPM_FEMC, &config);
femc_get_typical_sdram_config(HPM_FEMC, &sdram_config);
sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4;
sdram_config.prescaler = 0x3;
sdram_config.burst_len_in_byte = 8;
@@ -1015,18 +1017,14 @@ void _init_ext_ram(void)
sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS;
sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;
sdram_config.precharge_to_act_in_ns = 18; /* Trp */
sdram_config.act_to_rw_in_ns = 18; /* Trcd */
sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */
sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
sdram_config.cke_off_in_ns = 42; /* Trcd */
sdram_config.act_to_precharge_in_ns = 42; /* Tras */
sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */
sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */
sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */
sdram_config.refresh_recover_in_ns = 60; /* Trc */
sdram_config.act_to_precharge_in_ns = 42; /* Tras */
sdram_config.act_to_rw_in_ns = 18; /* Trcd */
sdram_config.precharge_to_act_in_ns = 18; /* Trp */
sdram_config.act_to_act_in_ns = 12; /* Trrd */
sdram_config.idle_timeout_in_ns = 6;
sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED;
sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
sdram_config.self_refresh_recover_in_ns = 72; /* Txsr */
sdram_config.cs = BOARD_SDRAM_CS;
sdram_config.base_address = BOARD_SDRAM_ADDRESS;
@@ -1034,7 +1032,6 @@ void _init_ext_ram(void)
sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE;
sdram_config.delay_cell_disable = true;
sdram_config.delay_cell_value = 0;
bsp/hpmicro/hpm6750evk2/rtconfig.h
+6 -4
View File
@@ -9,7 +9,6 @@
#define RT_THREAD_PRIORITY_32
#define RT_THREAD_PRIORITY_MAX 32
#define RT_TICK_PER_SECOND 1000
#define RT_USING_OVERFLOW_CHECK
#define RT_USING_HOOK
#define RT_HOOK_USING_FUNC_PTR
#define RT_USING_IDLE_HOOK
@@ -102,9 +101,6 @@
#define RT_CHERRYUSB_HOST_EHCI_HPM
#define RT_CHERRYUSB_HOST_CDC_ACM
#define RT_CHERRYUSB_HOST_HID
#define RT_CHERRYUSB_HOST_TEMPLATE
#define TEST_USBH_CDC_ACM 1
#define TEST_USBH_HID 1
/* end of Device Drivers */
/* C/C++ and POSIX layer */
@@ -312,6 +308,10 @@
/* end of STM32 HAL & SDK Drivers */
/* Infineon HAL Packages */
/* end of Infineon HAL Packages */
/* Kendryte SDK */
/* end of Kendryte SDK */
@@ -405,6 +405,8 @@
#define BSP_USING_UART
#define BSP_USING_UART0
#define BSP_USING_RTC
#define BSP_USING_USB
#define BSP_USING_USB_DEVICE
/* end of On-chip Peripheral Drivers */
/* end of Hardware Drivers Config */
bsp/hpmicro/hpm6750evk2/rtconfig.py
+2 -1
View File
@@ -1,4 +1,4 @@
# Copyright 2021-2023 HPMicro
# Copyright 2021-2024 HPMicro
# SPDX-License-Identifier: BSD-3-Clause
import os
@@ -7,6 +7,7 @@ import sys
# toolchains options
ARCH='risc-v'
CPU='hpmicro'
SOC_FAMILY='HPM6700'
CHIP_NAME='HPM6750'
CROSS_TOOL='gcc'
bsp/hpmicro/hpm6750evkmini/SConstruct
+1 -1
View File
@@ -59,7 +59,7 @@ hpm_library = 'hpm_sdk'
rtconfig.BSP_LIBRARY_TYPE = hpm_library
# include soc
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
bsp/hpmicro/hpm6750evkmini/board/board.c
+12 -15
View File
@@ -729,7 +729,7 @@ void board_init_clock(void)
clock_add_to_group(clock_mot3, 0);
clock_add_to_group(clock_acmp, 0);
clock_add_to_group(clock_dao, 0);
clock_add_to_group(clock_msyn, 0);
clock_add_to_group(clock_synt, 0);
clock_add_to_group(clock_lmm0, 0);
clock_add_to_group(clock_lmm1, 0);
clock_add_to_group(clock_pdm, 0);
@@ -1069,6 +1069,8 @@ void _init_ext_ram(void)
femc_default_config(HPM_FEMC, &config);
femc_init(HPM_FEMC, &config);
femc_get_typical_sdram_config(HPM_FEMC, &sdram_config);
sdram_config.bank_num = FEMC_SDRAM_BANK_NUM_4;
sdram_config.prescaler = 0x3;
sdram_config.burst_len_in_byte = 8;
@@ -1076,18 +1078,14 @@ void _init_ext_ram(void)
sdram_config.col_addr_bits = FEMC_SDRAM_COLUMN_ADDR_9_BITS;
sdram_config.cas_latency = FEMC_SDRAM_CAS_LATENCY_3;
sdram_config.precharge_to_act_in_ns = 18; /* Trp */
sdram_config.act_to_rw_in_ns = 18; /* Trcd */
sdram_config.refresh_recover_in_ns = 70; /* Trfc/Trc */
sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
sdram_config.cke_off_in_ns = 42; /* Trcd */
sdram_config.act_to_precharge_in_ns = 42; /* Tras */
sdram_config.self_refresh_recover_in_ns = 66; /* Txsr */
sdram_config.refresh_to_refresh_in_ns = 66; /* Trfc/Trc */
sdram_config.refresh_to_refresh_in_ns = 60; /* Trc */
sdram_config.refresh_recover_in_ns = 60; /* Trc */
sdram_config.act_to_precharge_in_ns = 42; /* Tras */
sdram_config.act_to_rw_in_ns = 18; /* Trcd */
sdram_config.precharge_to_act_in_ns = 18; /* Trp */
sdram_config.act_to_act_in_ns = 12; /* Trrd */
sdram_config.idle_timeout_in_ns = 6;
sdram_config.cs_mux_pin = FEMC_IO_MUX_NOT_USED;
sdram_config.write_recover_in_ns = 12; /* Twr/Tdpl */
sdram_config.self_refresh_recover_in_ns = 72; /* Txsr */
sdram_config.cs = BOARD_SDRAM_CS;
sdram_config.base_address = BOARD_SDRAM_ADDRESS;
@@ -1095,7 +1093,6 @@ void _init_ext_ram(void)
sdram_config.port_size = BOARD_SDRAM_PORT_SIZE;
sdram_config.refresh_count = BOARD_SDRAM_REFRESH_COUNT;
sdram_config.refresh_in_ms = BOARD_SDRAM_REFRESH_IN_MS;
sdram_config.data_width_in_byte = BOARD_SDRAM_DATA_WIDTH_IN_BYTE;
sdram_config.delay_cell_disable = true;
sdram_config.delay_cell_value = 0;
@@ -1134,9 +1131,9 @@ uint32_t board_sd_configure_clock(SDXC_Type *ptr, uint32_t freq, bool need_inver
else if (freq <= 100000000UL) {
clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 4);
}
/* Configure the clock to 133MHz for SDR104/HS200/HS400 */
/* Configure the clock to 166MHz for SDR104/HS200/HS400 */
else if (freq <= 208000000UL) {
clock_set_source_divider(sdxc_clk, clk_src_pll1_clk1, 3);
clock_set_source_divider(sdxc_clk, clk_src_pll2_clk0, 2);
}
/* For other unsupported clock ranges, configure the clock to 24MHz */
else {
bsp/hpmicro/hpm6750evkmini/rtconfig.py
+1
View File
@@ -7,6 +7,7 @@ import sys
# toolchains options
ARCH='risc-v'
CPU='hpmicro'
SOC_FAMILY='HPM6700'
CHIP_NAME='HPM6750'
CROSS_TOOL='gcc'
bsp/hpmicro/hpm6800evk/SConstruct
+1 -1
View File
@@ -59,7 +59,7 @@ hpm_library = 'hpm_sdk'
rtconfig.BSP_LIBRARY_TYPE = hpm_library
# include soc
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.CHIP_NAME, 'SConscript')))
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library,'soc', rtconfig.SOC_FAMILY, rtconfig.CHIP_NAME, 'SConscript')))
# include libraries
objs.extend(SConscript(os.path.join(libraries_path_prefix, hpm_library, 'SConscript')))
bsp/hpmicro/hpm6800evk/board/rtt_board.c
+11
View File
@@ -119,3 +119,14 @@ void rt_hw_cpu_reset(void)
}
MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reset, reset the board);
#ifdef RT_USING_CACHE
void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
{
if (ops == RT_HW_CACHE_FLUSH) {
l1c_dc_flush((uint32_t)addr, size);
} else {
l1c_dc_invalidate((uint32_t)addr, size);
}
}
#endif
bsp/hpmicro/hpm6800evk/rtconfig.py
+1
View File
@@ -7,6 +7,7 @@ import sys
# toolchains options
ARCH='risc-v'
CPU='hpmicro'
SOC_FAMILY='HPM6800'
CHIP_NAME='HPM6880'
CROSS_TOOL='gcc'
bsp/hpmicro/libraries/drivers/SConscript
+1 -1
View File
@@ -29,7 +29,7 @@ if GetDepend('BSP_USING_ETH'):
if GetDepend('BSP_USING_SDXC'):
src += ['drv_sdio.c']
if GetDepend('BSP_USING_PWM'):
if GetDepend('BSP_USING_PWM') or GetDepend('BSP_USING_PWMV2'):
src += ['drv_pwm.c']
if GetDepend('BSP_USING_GPTMR'):
bsp/hpmicro/libraries/drivers/drv_adc.c
+19 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023 HPMicro
* Copyright (c) 2021-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,6 +36,7 @@ typedef struct
static uint32_t hpm_adc_init_clock(struct rt_adc_device *device);
static void hpm_adc_init_pins(struct rt_adc_device *device);
static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled);
static rt_err_t hpm_get_adc_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value);
@@ -121,6 +122,22 @@ static uint32_t hpm_adc_init_clock(struct rt_adc_device *device)
return clock_freq;
}
static void hpm_adc_init_pins(struct rt_adc_device *device)
{
hpm_rtt_adc *hpm_adc;
RT_ASSERT(device != RT_NULL);
hpm_adc = (hpm_rtt_adc *)device->parent.user_data;
#if defined(ADC12_SOC_MAX_CH_NUM)
if (hpm_adc->is_adc12)
{
board_init_adc12_pins();
} else
#endif
{
board_init_adc16_pins();
}
}
static rt_err_t init_adc_config(hpm_rtt_adc *adc)
{
hpm_stat_t ret;
@@ -208,6 +225,7 @@ static rt_err_t hpm_adc_enabled(struct rt_adc_device *device, rt_int8_t channel,
{
if (!hpm_adc->adc_enabled)
{
hpm_adc_init_pins(device);
(void)hpm_adc_init_clock(device);
ret = init_adc_config(hpm_adc);
if (ret != RT_EOK) {
@@ -251,7 +269,6 @@ static rt_err_t hpm_get_adc_value(struct rt_adc_device *device, rt_int8_t channe
#ifdef BSP_USING_ADC16
hpm_stat_t status = adc16_get_oneshot_result((ADC16_Type *)hpm_adc->adc_base, adc_chn, &val);
*value = val;
// rt_kprintf("%s, status=%d\n", __func__, status);
#endif
}
bsp/hpmicro/libraries/drivers/drv_can.c
+2 -2
View File
@@ -347,7 +347,7 @@ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg)
else if (arg_val == RT_DEVICE_CAN_INT_ERR)
{
uint8_t irq_txrx_mask = CAN_EVENT_ERROR;
uint8_t irq_error_mask = CAN_ERROR_ARBITRAITION_LOST_INT_ENABLE | CAN_ERROR_PASSIVE_INT_ENABLE | CAN_ERROR_BUS_ERROR_INT_ENABLE;
uint8_t irq_error_mask = CAN_ERROR_ARBITRATION_LOST_INT_ENABLE | CAN_ERROR_PASSIVE_INT_ENABLE | CAN_ERROR_BUS_ERROR_INT_ENABLE;
drv_can->can_config.irq_txrx_enable_mask &= (uint8_t)~irq_txrx_mask;
drv_can->can_config.irq_error_enable_mask &= (uint8_t)~irq_error_mask;
can_disable_tx_rx_irq(drv_can->can_base, irq_txrx_mask);
@@ -377,7 +377,7 @@ static rt_err_t hpm_can_control(struct rt_can_device *can, int cmd, void *arg)
else if (arg_val == RT_DEVICE_CAN_INT_ERR)
{
uint8_t irq_txrx_mask = CAN_EVENT_ERROR;
uint8_t irq_error_mask = CAN_ERROR_ARBITRAITION_LOST_INT_ENABLE | CAN_ERROR_PASSIVE_INT_ENABLE | CAN_ERROR_BUS_ERROR_INT_ENABLE;
uint8_t irq_error_mask = CAN_ERROR_ARBITRATION_LOST_INT_ENABLE | CAN_ERROR_PASSIVE_INT_ENABLE | CAN_ERROR_BUS_ERROR_INT_ENABLE;
drv_can->can_config.irq_txrx_enable_mask |= irq_txrx_mask;
drv_can->can_config.irq_error_enable_mask |= irq_error_mask;
can_enable_tx_rx_irq(drv_can->can_base, irq_txrx_mask);
bsp/hpmicro/libraries/drivers/drv_enet.c
+6 -7
View File
@@ -208,9 +208,14 @@ static rt_err_t hpm_enet_init(enet_device *init)
enet_rgmii_set_clock_delay(init->instance, init->tx_delay, init->rx_delay);
}
#endif
/* Get the default interrupt config */
enet_get_default_interrupt_config(init->instance, &init->int_config);
/* Initialize eth controller */
enet_controller_init(init->instance, init->media_interface, &init->desc, &init->mac_config, &init->int_config);
enet_controller_init(init->instance, init->media_interface, &init->desc, &init->mac_config, &init->int_config);
/* Disable LPI interrupt */
enet_disable_lpi_interrupt(init->instance);
#if __USE_ENET_PTP
/* initialize PTP Clock */
@@ -581,12 +586,6 @@ int rt_hw_eth_init(void)
s_geths[i]->enet_dev->ptp_config = *s_geths[i]->ptp_config;
s_geths[i]->enet_dev->ptp_timestamp = *s_geths[i]->ptp_timestamp;
#endif
/* Set the interrupt enable mask */
s_geths[i]->enet_dev->int_config.int_enable = enet_normal_int_sum_en /* Enable normal interrupt summary */
| enet_receive_int_en; /* Enable receive interrupt */
/* Set the interrupt disable mask */
s_geths[i]->enet_dev->int_config.int_mask = enet_rgsmii_int_mask;
/* Set the irq number */
s_geths[i]->enet_dev->irq_number = s_geths[i]->irq_num;
bsp/hpmicro/libraries/drivers/drv_gpio.c
+38 -35
View File
File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/drivers/drv_i2c.c
+3 -98
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023 HPMicro
* Copyright (c) 2022-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -157,101 +157,6 @@ void i2c3_isr(void)
SDK_DECLARE_EXT_ISR_M(IRQn_I2C3, i2c3_isr);
#endif
static hpm_stat_t i2c_transfer(I2C_Type *ptr, const uint16_t device_address,
uint8_t *buf, const uint32_t size, uint16_t flags)
{
uint32_t ctrl = 0;
uint32_t retry = 0;
uint32_t left = 0;
if (((size == 0) || (size > I2C_SOC_TRANSFER_COUNT_MAX))) {
return status_invalid_argument;
}
/* W1C, clear CMPL bit to avoid blocking the transmission */
ptr->STATUS = I2C_STATUS_CMPL_MASK;
ptr->CMD = I2C_CMD_CLEAR_FIFO;
ptr->ADDR = I2C_ADDR_ADDR_SET(device_address);
if (flags & RT_I2C_RD) {
ctrl |= I2C_CTRL_DIR_SET(I2C_DIR_MASTER_READ);
} else {
ctrl |= I2C_CTRL_DIR_SET(I2C_DIR_MASTER_WRITE);/* is write flag */
}
/* no start signal send*/
if (flags & RT_I2C_NO_START) {
ctrl |= I2C_CTRL_PHASE_START_SET(false) | I2C_CTRL_PHASE_STOP_SET(true) \
| I2C_CTRL_PHASE_ADDR_SET(true);
} else if (flags & RT_I2C_NO_STOP) { /* no end signal send*/
ctrl |= I2C_CTRL_PHASE_START_SET(true) | I2C_CTRL_PHASE_STOP_SET(false) \
| I2C_CTRL_PHASE_ADDR_SET(true);
} else {
ctrl |= I2C_CTRL_PHASE_START_SET(true) | I2C_CTRL_PHASE_STOP_SET(true) \
| I2C_CTRL_PHASE_ADDR_SET(true);
}
ptr->CTRL = ctrl | I2C_CTRL_PHASE_DATA_SET(true) \
| I2C_CTRL_DATACNT_HIGH_SET(I2C_DATACNT_MAP(size) >> 8U) \
| I2C_CTRL_DATACNT_SET(I2C_DATACNT_MAP(size));
/* disable auto ack */
ptr->INTEN |= I2C_EVENT_BYTE_RECEIVED;
ptr->CMD = I2C_CMD_ISSUE_DATA_TRANSMISSION;
retry = 0;
left = size;
if (flags & RT_I2C_RD) {
while (left) {
if (!(ptr->STATUS & I2C_STATUS_FIFOEMPTY_MASK)) {
*(buf++) = ptr->DATA;
left--;
if (left == 0) {
ptr->CMD = I2C_CMD_NACK;
} else {
/* ACK is sent when reading */
if (!(flags & RT_I2C_NO_READ_ACK)) {
ptr->CMD = I2C_CMD_ACK;
}
}
retry = 0;
} else {
if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) {
break;
}
retry++;
}
}
if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) {
return status_timeout;
}
} else {
while (left) {
if (!(ptr->STATUS & I2C_STATUS_FIFOFULL_MASK)) {
ptr->DATA = *(buf++);
left--;
retry = 0;
} else {
if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) {
break;
}
retry++;
}
}
if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) {
return status_timeout;
}
}
retry = 0;
while (!(ptr->STATUS & I2C_STATUS_CMPL_MASK)) {
if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) {
break;
}
retry++;
};
if (retry > HPM_I2C_DRV_DEFAULT_RETRY_COUNT) {
return status_timeout;
}
if (i2c_get_data_count(ptr) && (size)) {
return status_i2c_transmit_not_completed;
}
}
static hpm_stat_t i2c_tx_trigger_dma(DMA_Type *dma_ptr, uint8_t ch_num, I2C_Type *i2c_ptr, uint32_t src, uint32_t size)
{
dma_handshake_config_t config;
@@ -398,7 +303,7 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct
}
else
{
i2c_transfer(i2c_info->base, msg->addr, dummy_buf, transfer_len, msg->flags);
i2c_master_transfer(i2c_info->base, msg->addr, dummy_buf, transfer_len, msg->flags);
}
dummy_buf += transfer_len;
remaining_size -= transfer_len;
@@ -451,7 +356,7 @@ static rt_ssize_t hpm_i2c_master_transfer(struct rt_i2c_bus_device *bus, struct
}
else
{
i2c_transfer(i2c_info->base, msg->addr, dummy_buf, transfer_len, msg->flags);
i2c_master_transfer(i2c_info->base, msg->addr, dummy_buf, transfer_len, msg->flags);
}
dummy_buf += transfer_len;
remaining_size -= transfer_len;
bsp/hpmicro/libraries/drivers/drv_pwm.c
+125 -25
View File
File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/drivers/drv_sdio.c
+13
View File
@@ -13,6 +13,7 @@
* 2024-05-23 HPMicro Fixed unaligned transfer issue in the SDIO case
* 2024-05-25 HPMicro Added HS200 & HS400 support, optimize the cache-management policy for read
* 2024-05-26 HPMicro Added UHS-I support, added DDR50 and High Speed DDR mode support
* 2024-06-19 HPMicro Added timeout check for SDXC transfer
*/
#include <rtthread.h>
@@ -336,11 +337,17 @@ static hpm_stat_t hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_co
}
/* Wait until idle */
volatile uint32_t interrupt_status = sdxc_get_interrupt_status(base);
volatile rt_base_t start_tick = rt_tick_get();
while (!IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_CMD_COMPLETE_MASK))
{
interrupt_status = sdxc_get_interrupt_status(base);
status = sdxc_parse_interrupt_status(base);
HPM_BREAK_IF(status != status_success);
rt_base_t current_tick = rt_tick_get();
if ((current_tick - start_tick) > RT_TICK_PER_SECOND)
{
return -RT_ETIMEOUT;
}
}
sdxc_clear_interrupt_status(base, SDXC_INT_STAT_CMD_COMPLETE_MASK);
if (status == status_success)
@@ -350,11 +357,17 @@ static hpm_stat_t hpm_sdmmc_transfer(SDXC_Type *base, sdxc_adma_config_t *dma_co
if ((status == status_success) && (data != RT_NULL))
{
interrupt_status = sdxc_get_interrupt_status(base);
start_tick = rt_tick_get();
while (!IS_HPM_BITMASK_SET(interrupt_status, SDXC_INT_STAT_XFER_COMPLETE_MASK | SDXC_STS_ERROR))
{
interrupt_status = sdxc_get_interrupt_status(base);
status = sdxc_parse_interrupt_status(base);
HPM_BREAK_IF(status != status_success);
rt_base_t current_tick = rt_tick_get();
if ((current_tick - start_tick) > RT_TICK_PER_SECOND)
{
return -RT_ETIMEOUT;
}
}
}
bsp/hpmicro/libraries/drivers/drv_spi.c
+92 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023 HPMicro
* Copyright (c) 2021-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -9,6 +9,7 @@
* 2023-02-15 HPMicro Add DMA support
* 2023-07-14 HPMicro Manage the DMA buffer alignment in driver
* 2023-12-14 HPMicro change state blocking wait to interrupt semaphore wait for DMA
* 2024-06-10 HPMicro Add the SPI pin settings
*/
#include <rtthread.h>
@@ -42,6 +43,7 @@ struct hpm_spi
rt_sem_t spi_xfer_done_sem;
rt_sem_t txdma_xfer_done_sem;
rt_sem_t rxdma_xfer_done_sem;
void (*spi_pins_init)(SPI_Type *spi_base);
};
static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg);
@@ -59,6 +61,11 @@ static struct hpm_spi hpm_spis[] =
.tx_dmamux = HPM_DMA_SRC_SPI0_TX,
.rx_dmamux = HPM_DMA_SRC_SPI0_RX,
.spi_irq = IRQn_SPI0,
#if !defined BSP_SPI0_USING_HARD_CS
.spi_pins_init = init_spi_pins_with_gpio_as_cs,
#else
.spi_pins_init = init_spi_pins,
#endif
},
#endif
#if defined(BSP_USING_SPI1)
@@ -71,6 +78,11 @@ static struct hpm_spi hpm_spis[] =
.tx_dmamux = HPM_DMA_SRC_SPI1_TX,
.rx_dmamux = HPM_DMA_SRC_SPI1_RX,
.spi_irq = IRQn_SPI1,
#if !defined BSP_SPI1_USING_HARD_CS
.spi_pins_init = init_spi_pins_with_gpio_as_cs,
#else
.spi_pins_init = init_spi_pins,
#endif
},
#endif
#if defined(BSP_USING_SPI2)
@@ -83,6 +95,11 @@ static struct hpm_spi hpm_spis[] =
.tx_dmamux = HPM_DMA_SRC_SPI2_TX,
.rx_dmamux = HPM_DMA_SRC_SPI2_RX,
.spi_irq = IRQn_SPI2,
#if !defined BSP_SPI2_USING_HARD_CS
.spi_pins_init = init_spi_pins_with_gpio_as_cs,
#else
.spi_pins_init = init_spi_pins,
#endif
},
#endif
#if defined(BSP_USING_SPI3)
@@ -95,6 +112,79 @@ static struct hpm_spi hpm_spis[] =
.tx_dmamux = HPM_DMA_SRC_SPI3_TX,
.rx_dmamux = HPM_DMA_SRC_SPI3_RX,
.spi_irq = IRQn_SPI3,
#if !defined BSP_SPI3_USING_HARD_CS
.spi_pins_init = init_spi_pins_with_gpio_as_cs,
#else
.spi_pins_init = init_spi_pins,
#endif
},
#endif
#if defined(BSP_USING_SPI4)
{
.bus_name = "spi4",
.spi_base = HPM_SPI4,
#if defined(BSP_SPI4_USING_DMA)
.enable_dma = RT_TRUE,
#endif
.tx_dmamux = HPM_DMA_SRC_SPI4_TX,
.rx_dmamux = HPM_DMA_SRC_SPI4_RX,
.spi_irq = IRQn_SPI4,
#if !defined BSP_SPI4_USING_HARD_CS
.spi_pins_init = init_spi_pins_with_gpio_as_cs,
#else
.spi_pins_init = init_spi_pins,
#endif
},
#endif
#if defined(BSP_USING_SPI5)
{
.bus_name = "spi5",
.spi_base = HPM_SPI5,
#if defined(BSP_SPI5_USING_DMA)
.enable_dma = RT_TRUE,
#endif
.tx_dmamux = HPM_DMA_SRC_SPI5_TX,
.rx_dmamux = HPM_DMA_SRC_SPI5_RX,
.spi_irq = IRQn_SPI5,
#if !defined BSP_SPI5_USING_HARD_CS
.spi_pins_init = init_spi_pins_with_gpio_as_cs,
#else
.spi_pins_init = init_spi_pins,
#endif
},
#endif
#if defined(BSP_USING_SPI6)
{
.bus_name = "spi6",
.spi_base = HPM_SPI6,
#if defined(BSP_SPI6_USING_DMA)
.enable_dma = RT_TRUE,
#endif
.tx_dmamux = HPM_DMA_SRC_SPI6_TX,
.rx_dmamux = HPM_DMA_SRC_SPI6_RX,
.spi_irq = IRQn_SPI6,
#if !defined BSP_SPI6_USING_HARD_CS
.spi_pins_init = init_spi_pins_with_gpio_as_cs,
#else
.spi_pins_init = init_spi_pins,
#endif
},
#endif
#if defined(BSP_USING_SPI7)
{
.bus_name = "spi7",
.spi_base = HPM_SPI7,
#if defined(BSP_SPI7_USING_DMA)
.enable_dma = RT_TRUE,
#endif
.tx_dmamux = HPM_DMA_SRC_SPI7_TX,
.rx_dmamux = HPM_DMA_SRC_SPI7_RX,
.spi_irq = IRQn_SPI7,
#if !defined BSP_SPI7_USING_HARD_CS
.spi_pins_init = init_spi_pins_with_gpio_as_cs,
#else
.spi_pins_init = init_spi_pins,
#endif
},
#endif
};
@@ -197,7 +287,7 @@ static rt_err_t hpm_spi_configure(struct rt_spi_device *device, struct rt_spi_co
spi_master_get_default_timing_config(&timing_config);
spi_master_get_default_format_config(&format_config);
init_spi_pins_with_gpio_as_cs(spi->spi_base);
spi->spi_pins_init(spi->spi_base);
timing_config.master_config.clk_src_freq_in_hz = board_init_spi_clock(spi->spi_base);
bsp/hpmicro/libraries/drivers/drv_uart_v2.c
+24 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022-2023 HPMicro
* Copyright (c) 2022-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -9,6 +9,7 @@
* 2022-07-28 HPMicro Fix compiling warning if RT_SERIAL_USING_DMA was not defined
* 2022-08-08 HPMicro Integrate DMA Manager and support dynamic DMA resource assignment'
* 2023-03-07 HPMicro Fix the issue that the data_width was not initialized before setup dma handshake
* 2024-06-10 HPMicro Fix memory leakage issue
*
*/
#include <rtthread.h>
@@ -34,6 +35,7 @@ typedef struct dma_channel {
void (*tranfer_done)(struct rt_serial_device *serial);
void (*tranfer_abort)(struct rt_serial_device *serial);
void (*tranfer_error)(struct rt_serial_device *serial);
void *ringbuf_ptr;
} hpm_dma_channel_handle_t;
//static struct dma_channel dma_channels[DMA_SOC_CHANNEL_NUM];
@@ -596,6 +598,10 @@ static void uart_rx_done(struct rt_serial_device *serial)
uint32_t aligned_size = aligned_end - aligned_start;
l1c_dc_invalidate(aligned_start, aligned_size);
}
/* if open uart again after closing uart, an idle interrupt may be triggered, but uart initialization is not performed at this time, and the program exits if the rxfifo is empty. */
if (rx_fifo == RT_NULL) {
return;
}
rt_ringbuffer_put(&(rx_fifo->rb), uart->rx_idle_tmp_buffer, uart_recv_data_count);
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE);
#else
@@ -903,9 +909,17 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void
else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) {
dma_mgr_disable_chn_irq(&uart->tx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL);
dma_abort_channel(uart->tx_chn_ctx.resource.base, uart->tx_chn_ctx.resource.channel);
if (uart->tx_chn_ctx.ringbuf_ptr != RT_NULL) {
rt_free(uart->tx_chn_ctx.ringbuf_ptr);
uart->tx_chn_ctx.ringbuf_ptr = RT_NULL;
}
} else if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) {
dma_mgr_disable_chn_irq(&uart->rx_chn_ctx.resource, DMA_INTERRUPT_MASK_ALL);
dma_abort_channel(uart->rx_chn_ctx.resource.base, uart->rx_chn_ctx.resource.channel);
if (uart->rx_chn_ctx.ringbuf_ptr != RT_NULL) {
rt_free(uart->rx_chn_ctx.ringbuf_ptr);
uart->rx_chn_ctx.ringbuf_ptr = RT_NULL;
}
}
#endif
break;
@@ -932,6 +946,10 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void
RT_ASSERT(rx_fifo != RT_NULL);
tmp_buffer = rt_malloc(serial->config.rx_bufsz + HPM_L1C_CACHELINE_SIZE);
RT_ASSERT(tmp_buffer != RT_NULL);
if (uart->rx_chn_ctx.ringbuf_ptr != RT_NULL) {
rt_free(uart->rx_chn_ctx.ringbuf_ptr);
}
uart->rx_chn_ctx.ringbuf_ptr = (void *)tmp_buffer;
tmp_buffer += (HPM_L1C_CACHELINE_SIZE - ((rt_ubase_t) tmp_buffer % HPM_L1C_CACHELINE_SIZE));
rt_ringbuffer_init(&rx_fifo->rb, tmp_buffer, serial->config.rx_bufsz);
rt_ringbuffer_reset(&rx_fifo->rb);
@@ -947,7 +965,11 @@ static rt_err_t hpm_uart_control(struct rt_serial_device *serial, int cmd, void
RT_ASSERT(tx_fifo != RT_NULL);
tmp_buffer = rt_malloc(serial->config.tx_bufsz + HPM_L1C_CACHELINE_SIZE);
RT_ASSERT(tmp_buffer != RT_NULL);
tmp_buffer+= (HPM_L1C_CACHELINE_SIZE - ((rt_ubase_t) tmp_buffer % HPM_L1C_CACHELINE_SIZE));
if (uart->tx_chn_ctx.ringbuf_ptr != RT_NULL) {
rt_free(uart->tx_chn_ctx.ringbuf_ptr);
}
uart->tx_chn_ctx.ringbuf_ptr = (void *)tmp_buffer;
tmp_buffer += (HPM_L1C_CACHELINE_SIZE - ((rt_ubase_t) tmp_buffer % HPM_L1C_CACHELINE_SIZE));
rt_ringbuffer_init(&tx_fifo->rb, tmp_buffer, serial->config.tx_bufsz);
rt_ringbuffer_reset(&tx_fifo->rb);
tx_fifo->activated = RT_FALSE;
bsp/hpmicro/libraries/hpm_sdk/CHANGELOG.md
+254 -1
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/SConscript
+18 -5
View File
@@ -5,7 +5,7 @@ from building import *
cwd = GetCurrentDir()
# Update include path
path = [ cwd + '/arch', cwd + "/drivers/inc", cwd + '/soc/ip']
path = [ cwd + '/arch', cwd + "/drivers/inc", cwd + '/soc/' + rtconfig.SOC_FAMILY + '/' + '/ip']
# The set of source files associated with this SConscript file.
src = []
@@ -13,11 +13,14 @@ src = []
CPPDEFINES=[]
src += ['drivers/src/hpm_pmp_drv.c']
src += ['drivers/src/hpm_pllctl_drv.c']
src += ['drivers/src/hpm_pllctlv2_drv.c']
src += ['drivers/src/hpm_pcfg_drv.c']
if rtconfig.CHIP_NAME == "HPM6750" or rtconfig.CHIP_NAME == "HPM6360" or rtconfig.CHIP_NAME == "HPM6280":
if rtconfig.SOC_FAMILY == "HPM6700":
src += ['drivers/src/hpm_pllctl_drv.c']
else:
src += ['drivers/src/hpm_pllctlv2_drv.c']
if rtconfig.SOC_FAMILY == "HPM6700" or rtconfig.SOC_FAMILY == "HPM6300" or rtconfig.SOC_FAMILY == "HPM6200":
src += ['drivers/src/hpm_dma_drv.c']
else:
src += ['drivers/src/hpm_dmav2_drv.c']
@@ -77,7 +80,10 @@ if GetDepend(['BSP_USING_FEMC']):
if GetDepend(['BSP_USING_PWM']):
src += ['drivers/src/hpm_pwm_drv.c']
if GetDepend(['BSP_USING_USB']) or GetDepend(['RT_USING_CHERRYUSB']):
if GetDepend(['BSP_USING_PWMV2']):
src += ['drivers/src/hpm_pwmv2_drv.c']
if GetDepend(['BSP_USING_USB']):
src += ['drivers/src/hpm_usb_drv.c']
if GetDepend(['BSP_USING_I2S']):
@@ -110,6 +116,13 @@ if GetDepend(['BSP_USING_MIPI_CSI']):
if GetDepend(['BSP_USING_MIPI_DSI']):
src += ['drivers/src/hpm_mipi_dsi_drv.c']
src += ['drivers/src/hpm_mipi_dsi_phy_drv.c']
if GetDepend(['BSP_USING_LVB']):
src += ['drivers/src/hpm_lvb_drv.c']
if GetDepend(['BSP_USING_LCB']):
src += ['drivers/src/hpm_lcb_drv.c']
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES)
Return ('group')
bsp/hpmicro/libraries/hpm_sdk/components/SConscript
+5 -5
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@@ -16,11 +16,11 @@ src = []
src += [ os.path.join(cwd, 'debug_console', 'hpm_debug_console.c') ]
src += [ os.path.join(cwd, 'dma_mgr', 'hpm_dma_mgr.c') ]
if GetDepend(['BSP_USING_TOUCH_GT911']):
src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_touch_gt911.c') ]
src += [os.path.join(cwd, 'touch', 'gt911', 'hpm_gt911.c') ]
path += [ os.path.join(cwd, 'touch', 'gt911') ]
CPPDEFINES += ['CONFIG_TOUCH_GT911=1']
if GetDepend(['BSP_USING_TOUCH_GT9xx']):
src += [os.path.join(cwd, 'touch', 'gt9xx', 'hpm_touch_gt9xx.c') ]
src += [os.path.join(cwd, 'touch', 'gt9xx', 'hpm_gt9xx.c') ]
path += [ os.path.join(cwd, 'touch', 'gt9xx') ]
CPPDEFINES += ['CONFIG_TOUCH_GT9XX=1']
if GetDepend(['BSP_USING_TOUCH_FT5406']):
src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_touch_ft5406.c') ]
src += [ os.path.join(cwd, 'touch', 'ft5406', 'hpm_ft5406.c') ]
bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978.c
+405
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978.h
+215
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/components/codec/wm8978/hpm_wm8978_regs.h
+549
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.c
+10 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021 HPMicro
* Copyright (c) 2021-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -39,6 +39,15 @@ uint8_t console_receive_byte(void)
return c;
}
uint8_t console_try_receive_byte(void)
{
uint8_t c = 0;
uart_try_receive_byte(g_console_uart, &c);
return c;
}
void console_send_byte(uint8_t c)
{
while (status_success != uart_send_byte(g_console_uart, c)) {
bsp/hpmicro/libraries/hpm_sdk/components/debug_console/hpm_debug_console.h
+2 -2
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021 HPMicro
* Copyright (c) 2021-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -26,7 +26,7 @@ extern "C" {
hpm_stat_t console_init(console_config_t *cfg);
uint8_t console_receive_byte(void);
uint8_t console_try_receive_byte(void);
void console_send_byte(uint8_t c);
#if defined(__cplusplus)
bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.c
+110 -10
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022 HPMicro
* Copyright (c) 2022-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -354,6 +354,10 @@ void dma_mgr_get_default_chn_config(dma_mgr_chn_conf_t *config)
config->en_infiniteloop = false;
config->handshake_opt = DMA_MGR_HANDSHAKE_OPT_ONE_BURST;
config->burst_opt = DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE;
config->en_src_burst_in_fixed_trans = false;
config->en_dst_burst_in_fixed_trans = false;
config->swap_mode = DMA_MGR_SWAP_MODE_TABLE;
config->swap_table = 0;
}
hpm_stat_t dma_mgr_setup_channel(const dma_resource_t *resource, dma_mgr_chn_conf_t *config)
@@ -382,14 +386,22 @@ hpm_stat_t dma_mgr_setup_channel(const dma_resource_t *resource, dma_mgr_chn_con
dma_config.size_in_byte = config->size_in_byte;
dma_config.linked_ptr = config->linked_ptr;
dma_config.interrupt_mask = config->interrupt_mask;
#ifdef DMA_MGR_HAS_INFINITE_LOOP
#if defined(DMA_MGR_HAS_INFINITE_LOOP) && DMA_MGR_HAS_INFINITE_LOOP
dma_config.en_infiniteloop = config->en_infiniteloop;
#endif
#ifdef DMA_MGR_HAS_HANDSHAKE_OPT
#if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT
dma_config.handshake_opt = config->handshake_opt;
#endif
#ifdef DMA_MGR_HAS_BURST_OPT
#if defined(DMA_MGR_HAS_BURST_OPT) && DMA_MGR_HAS_BURST_OPT
dma_config.burst_opt = config->burst_opt;
#endif
#if defined(DMA_MGR_HAS_BURST_IN_FIXED_TRANS) && DMA_MGR_HAS_BURST_IN_FIXED_TRANS
dma_config.en_src_burst_in_fixed_trans = config->en_src_burst_in_fixed_trans;
dma_config.en_dst_burst_in_fixed_trans = config->en_dst_burst_in_fixed_trans;
#endif
#if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP
dma_config.swap_mode = config->swap_mode;
dma_config.swap_table = config->swap_table;
#endif
status = dma_setup_channel(resource->base, resource->channel, &dma_config, false);
}
@@ -419,14 +431,22 @@ hpm_stat_t dma_mgr_config_linked_descriptor(const dma_resource_t *resource, dma_
dma_config.size_in_byte = config->size_in_byte;
dma_config.linked_ptr = config->linked_ptr;
dma_config.interrupt_mask = config->interrupt_mask;
#ifdef DMA_MGR_HAS_INFINITE_LOOP
#if defined(DMA_MGR_HAS_INFINITE_LOOP) && DMA_MGR_HAS_INFINITE_LOOP
dma_config.en_infiniteloop = config->en_infiniteloop;
#endif
#ifdef DMA_MGR_HAS_HANDSHAKE_OPT
#if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT
dma_config.handshake_opt = config->handshake_opt;
#endif
#ifdef DMA_MGR_HAS_BURST_OPT
#if defined(DMA_MGR_HAS_BURST_OPT) && DMA_MGR_HAS_BURST_OPT
dma_config.burst_opt = config->burst_opt;
#endif
#if defined(DMA_MGR_HAS_BURST_IN_FIXED_TRANS) && DMA_MGR_HAS_BURST_IN_FIXED_TRANS
dma_config.en_src_burst_in_fixed_trans = config->en_src_burst_in_fixed_trans;
dma_config.en_dst_burst_in_fixed_trans = config->en_dst_burst_in_fixed_trans;
#endif
#if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP
dma_config.swap_mode = config->swap_mode;
dma_config.swap_table = config->swap_table;
#endif
status = dma_config_linked_descriptor(resource->base, (dma_linked_descriptor_t *)descriptor, resource->channel, &dma_config);
}
@@ -696,7 +716,7 @@ hpm_stat_t dma_mgr_set_chn_infinite_loop_mode(const dma_resource_t *resource, bo
if (chn_ctx == NULL) {
status = status_invalid_argument;
} else {
#ifdef DMA_MGR_HAS_INFINITE_LOOP
#if defined(DMA_MGR_HAS_INFINITE_LOOP) && DMA_MGR_HAS_INFINITE_LOOP
dma_set_infinite_loop_mode(resource->base, resource->channel, infinite_loop);
status = status_success;
#else
@@ -716,7 +736,7 @@ hpm_stat_t dma_mgr_set_chn_src_busrt_option(const dma_resource_t *resource, uint
if (chn_ctx == NULL) {
status = status_invalid_argument;
} else {
#ifdef DMA_MGR_HAS_BURST_OPT
#if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT
dma_set_src_busrt_option(resource->base, resource->channel, burst_opt);
status = status_success;
#else
@@ -736,7 +756,7 @@ hpm_stat_t dma_mgr_set_chn_handshake_option(const dma_resource_t *resource, uint
if (chn_ctx == NULL) {
status = status_invalid_argument;
} else {
#ifdef DMA_MGR_HAS_HANDSHAKE_OPT
#if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT
dma_set_handshake_option(resource->base, resource->channel, handshake_opt);
status = status_success;
#else
@@ -776,3 +796,83 @@ hpm_stat_t dma_mgr_check_chn_transfer_status(const dma_resource_t *resource, uin
}
return stat;
}
hpm_stat_t dma_mgr_set_source_burst_in_fixed_transize_enable(const dma_resource_t *resource, bool enable)
{
hpm_stat_t status;
dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource);
if (chn_ctx == NULL) {
status = status_invalid_argument;
} else {
#if defined(DMA_MGR_HAS_BURST_IN_FIXED_TRANS) && DMA_MGR_HAS_BURST_IN_FIXED_TRANS
dma_set_source_burst_in_fixed_transize_enable(resource->base, resource->channel, enable);
status = status_success;
#else
(void)enable;
status = status_fail;
#endif
}
return status;
}
hpm_stat_t dma_mgr_set_destination_burst_in_fix_transize_enable(const dma_resource_t *resource, bool enable)
{
hpm_stat_t status;
dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource);
if (chn_ctx == NULL) {
status = status_invalid_argument;
} else {
#if defined(DMA_MGR_HAS_BURST_IN_FIXED_TRANS) && DMA_MGR_HAS_BURST_IN_FIXED_TRANS
dma_set_destination_burst_in_fixed_transize_enable(resource->base, resource->channel, enable);
status = status_success;
#else
(void)enable;
status = status_fail;
#endif
}
return status;
}
hpm_stat_t dma_mgr_set_swap_mode(const dma_resource_t *resource, uint8_t swap_mode)
{
hpm_stat_t status;
dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource);
if (chn_ctx == NULL) {
status = status_invalid_argument;
} else {
#if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP
dma_set_swap_mode(resource->base, resource->channel, swap_mode);
status = status_success;
#else
(void)swap_mode;
status = status_fail;
#endif
}
return status;
}
hpm_stat_t dma_mgr_set_swap_table(const dma_resource_t *resource, uint32_t swap_table)
{
hpm_stat_t status;
dma_chn_context_t *chn_ctx = dma_mgr_search_chn_context(resource);
if (chn_ctx == NULL) {
status = status_invalid_argument;
} else {
#if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP
dma_set_swap_table(resource->base, resource->channel, swap_table);
status = status_success;
#else
(void)swap_table;
status = status_fail;
#endif
}
return status;
}
bsp/hpmicro/libraries/hpm_sdk/components/dma_mgr/hpm_dma_mgr.h
+82 -16
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022 HPMicro
* Copyright (c) 2022-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -19,10 +19,20 @@
#include "hpm_soc_feature.h"
#ifdef HPMSOC_HAS_HPMSDK_DMAV2
#define DMA_MGR_HAS_INFINITE_LOOP (1U)
#define DMA_MGR_HAS_HALF_TC_INT (1U)
#define DMA_MGR_HAS_HANDSHAKE_OPT (1U)
#define DMA_MGR_HAS_BURST_OPT (1U)
#define DMA_MGR_HAS_INFINITE_LOOP (1U)
#define DMA_MGR_HAS_HALF_TC_INT (1U)
#define DMA_MGR_HAS_HANDSHAKE_OPT (1U)
#define DMA_MGR_HAS_BURST_OPT (1U)
#if defined(HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS) && (HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS == 1)
#define DMA_MGR_HAS_BURST_IN_FIXED_TRANS HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS
#else
#define DMA_MGR_HAS_BURST_IN_FIXED_TRANS 0
#endif
#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1)
#define DMA_MGR_HAS_BYTE_ORDER_SWAP HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP
#else
#define DMA_MGR_HAS_BYTE_ORDER_SWAP 0
#endif
#endif
#define DMA_MGR_CHANNEL_PRIORITY_LOW DMA_CHANNEL_PRIORITY_LOW
@@ -52,7 +62,7 @@
#define DMA_MGR_ADDRESS_CONTROL_DECREMENT DMA_ADDRESS_CONTROL_DECREMENT
#define DMA_MGR_ADDRESS_CONTROL_FIXED DMA_ADDRESS_CONTROL_FIXED
#ifdef DMA_MGR_HAS_BURST_OPT
#if defined(DMA_MGR_HAS_BURST_OPT) && DMA_MGR_HAS_BURST_OPT
#define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE DMA_SRC_BURST_OPT_STANDAND_SIZE
#define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE DMA_SRC_BURST_OPT_CUSTOM_SIZE
#else
@@ -60,7 +70,7 @@
#define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE 0
#endif
#ifdef DMA_MGR_HAS_HANDSHAKE_OPT
#if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT
#define DMA_MGR_HANDSHAKE_OPT_ONE_BURST DMA_HANDSHAKE_OPT_ONE_BURST
#define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE DMA_HANDSHAKE_OPT_ALL_TRANSIZE
#else
@@ -72,21 +82,33 @@
#define DMA_MGR_CHANNEL_STATUS_ERROR DMA_CHANNEL_STATUS_ERROR
#define DMA_MGR_CHANNEL_STATUS_ABORT DMA_CHANNEL_STATUS_ABORT
#define DMA_MGR_CHANNEL_STATUS_TC DMA_CHANNEL_STATUS_TC
#ifdef DMA_MGR_HAS_HALF_TC_INT
#if defined(DMA_MGR_HAS_HALF_TC_INT) && DMA_MGR_HAS_HALF_TC_INT
#define DMA_MGR_CHANNEL_STATUS_HALF_TC DMA_CHANNEL_STATUS_HALF_TC
#else
#define DMA_MGR_CHANNEL_STATUS_HALF_TC 0
#endif
#define DMA_MGR_INTERRUPT_MASK_NONE DMA_INTERRUPT_MASK_NONE
#define DMA_MGR_INTERRUPT_MASK_ERROR DMA_INTERRUPT_MASK_ERROR
#define DMA_MGR_INTERRUPT_MASK_ABORT DMA_INTERRUPT_MASK_ABORT
#define DMA_MGR_INTERRUPT_MASK_TC DMA_INTERRUPT_MASK_TERMINAL_COUNT
#ifdef DMA_MGR_HAS_HALF_TC_INT
#define DMA_MGR_INTERRUPT_MASK_HALF_TC DMA_INTERRUPT_MASK_HALF_TC
#define DMA_MGR_INTERRUPT_MASK_NONE DMA_INTERRUPT_MASK_NONE
#define DMA_MGR_INTERRUPT_MASK_ERROR DMA_INTERRUPT_MASK_ERROR
#define DMA_MGR_INTERRUPT_MASK_ABORT DMA_INTERRUPT_MASK_ABORT
#define DMA_MGR_INTERRUPT_MASK_TC DMA_INTERRUPT_MASK_TERMINAL_COUNT
#if defined(DMA_MGR_HAS_HALF_TC_INT) && DMA_MGR_HAS_HALF_TC_INT
#define DMA_MGR_INTERRUPT_MASK_HALF_TC DMA_INTERRUPT_MASK_HALF_TC
#else
#define DMA_MGR_INTERRUPT_MASK_HALF_TC 0
#define DMA_MGR_INTERRUPT_MASK_HALF_TC 0
#endif
#define DMA_MGR_INTERRUPT_MASK_ALL DMA_INTERRUPT_MASK_ALL
#if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP
#define DMA_MGR_SWAP_MODE_TABLE DMA_SWAP_MODE_TABLE
#define DMA_MGR_SWAP_MODE_BYTE DMA_SWAP_MODE_BYTE
#define DMA_MGR_SWAP_MODE_HALF_WORD DMA_SWAP_MODE_HALF_WORD
#define DMA_MGR_SWAP_MODE_WORD DMA_SWAP_MODE_WORD
#else
#define DMA_MGR_SWAP_MODE_TABLE 0
#define DMA_MGR_SWAP_MODE_BYTE 0
#define DMA_MGR_SWAP_MODE_HALF_WORD 0
#define DMA_MGR_SWAP_MODE_WORD 0
#endif
#define DMA_MGR_INTERRUPT_MASK_ALL DMA_INTERRUPT_MASK_ALL
#ifdef __cplusplus
@@ -137,6 +159,10 @@ typedef struct hpm_dma_mgr_chn_conf {
bool en_infiniteloop; /**< Infinite loop transfer enable. Attention: only DMAV2 support */
uint8_t handshake_opt; /**< Handshake transfer option. Attention: only DMAV2 support */
uint8_t burst_opt; /**< Burst size option. Attention: only DMAV2 support */
bool en_src_burst_in_fixed_trans; /**< Source address burst in fix transfer size enable, discard src_addr_ctrl setting. Attention: only DMAV2 support */
bool en_dst_burst_in_fixed_trans; /**< Destination address burst in fix transfer size enable, discard dst_addr_ctrl setting. Attention: only DMAV2 support */
uint8_t swap_mode; /**< Swap Mode. Attention: only DMAV2 support */
uint32_t swap_table; /**< Swap Table. Attention: only DMAV2 support */
} dma_mgr_chn_conf_t;
typedef struct hpm_dma_mgr_linked_descriptor {
@@ -550,6 +576,46 @@ hpm_stat_t dma_mgr_abort_chn_transfer(const dma_resource_t *resource);
*/
hpm_stat_t dma_mgr_check_chn_transfer_status(const dma_resource_t *resource, uint32_t *status);
/**
* @brief Set DMA channel source burst in fixed transfer size enable or disable
*
* @param [in] resource DMA resource
* @param[in] enable false - disable; true - enable
*
*/
hpm_stat_t dma_mgr_set_source_burst_in_fixed_transize_enable(const dma_resource_t *resource, bool enable);
/**
* @brief Set DMA channel destination burst in fixed transfer size enable or disable
*
* @param [in] resource DMA resource
* @param[in] enable false - disable; true - enable
*
*/
hpm_stat_t dma_mgr_set_destination_burst_in_fix_transize_enable(const dma_resource_t *resource, bool enable);
/**
* @brief Set DMA channel swap mode
*
* @param [in] resource DMA resource
* @param[in] swap_mode swap mode
* @arg @ref DMA_MGR_SWAP_MODE_TABLE
* @arg @ref DMA_MGR_SWAP_MODE_BYTE
* @arg @ref DMA_MGR_SWAP_MODE_HALF_WORD
* @arg @ref DMA_MGR_SWAP_MODE_WORD
*
*/
hpm_stat_t dma_mgr_set_swap_mode(const dma_resource_t *resource, uint8_t swap_mode);
/**
* @brief Set DMA channel swap table
*
* @param [in] resource DMA resource
* @param[in] swap_table swap table
*
*/
hpm_stat_t dma_mgr_set_swap_table(const dma_resource_t *resource, uint32_t swap_table);
#ifdef __cplusplus
}
#endif
bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/hpm_enet_phy_common.h
+6
View File
@@ -32,4 +32,10 @@
#include "hpm_lan8720_regs.h"
#endif
#if defined(__USE_JL1111) && __USE_JL1111
#include "hpm_jl1111.h"
#include "hpm_jl1111_regs.h"
#endif
#endif /* HPM_ENET_PHY_H */
bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111.c
+122
View File
@@ -0,0 +1,122 @@
/*
* Copyright (c) 2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
/*---------------------------------------------------------------------
* Includes
*---------------------------------------------------------------------
*/
#include "hpm_enet_drv.h"
#include "hpm_jl1111_regs.h"
#include "hpm_jl1111.h"
/*---------------------------------------------------------------------
* Internal API
*---------------------------------------------------------------------
*/
static bool jl1111_check_id(ENET_Type *ptr)
{
uint16_t id1, id2;
id1 = enet_read_phy(ptr, JL1111_ADDR, JL1111_PHYID1);
id2 = enet_read_phy(ptr, JL1111_ADDR, JL1111_PHYID2);
if (JL1111_PHYID1_OUI_MSB_GET(id1) == JL1111_ID1 && JL1111_PHYID2_OUI_LSB_GET(id2) == JL1111_ID2) {
return true;
} else {
return false;
}
}
/*---------------------------------------------------------------------
* API
*---------------------------------------------------------------------
*/
void jl1111_reset(ENET_Type *ptr)
{
uint16_t data;
/* PHY reset */
enet_write_phy(ptr, JL1111_ADDR, JL1111_BMCR, JL1111_BMCR_RESET_SET(1));
/* wait until the reset is completed */
do {
data = enet_read_phy(ptr, JL1111_ADDR, JL1111_BMCR);
} while (JL1111_BMCR_RESET_GET(data));
}
void jl1111_basic_mode_default_config(ENET_Type *ptr, jl1111_config_t *config)
{
(void)ptr;
config->loopback = false; /* Disable PCS loopback mode */
#if defined(__DISABLE_AUTO_NEGO) && (__DISABLE_AUTO_NEGO)
config->auto_negotiation = false; /* Disable Auto-Negotiation */
config->speed = enet_phy_port_speed_100mbps;
config->duplex = enet_phy_duplex_full;
#else
config->auto_negotiation = true; /* Enable Auto-Negotiation */
#endif
}
bool jl1111_basic_mode_init(ENET_Type *ptr, jl1111_config_t *config)
{
uint16_t data = 0;
data |= JL1111_BMCR_RESET_SET(0) /* Normal operation */
| JL1111_BMCR_LOOPBACK_SET(config->loopback) /* configure PCS loopback mode */
| JL1111_BMCR_ANE_SET(config->auto_negotiation) /* configure Auto-Negotiation */
| JL1111_BMCR_PWD_SET(0) /* Normal operation */
| JL1111_BMCR_ISOLATE_SET(0) /* Normal operation */
| JL1111_BMCR_RESTART_AN_SET(0) /* Normal operation (ignored when Auto-Negotiation is disabled) */
| JL1111_BMCR_COLLISION_TEST_SET(0); /* Normal operation */
if (config->auto_negotiation == 0) {
data |= JL1111_BMCR_SPEED0_SET(config->speed); /* Set port speed */
data |= JL1111_BMCR_DUPLEX_SET(config->duplex); /* Set duplex mode */
}
/* check the id of jl1111 */
if (jl1111_check_id(ptr) == false) {
return false;
}
enet_write_phy(ptr, JL1111_ADDR, JL1111_BMCR, data);
return true;
}
void jl1111_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status)
{
uint16_t data, anar, anlpar;
data = enet_read_phy(ptr, JL1111_ADDR, JL1111_BMSR);
status->enet_phy_link = JL1111_BMSR_LINK_STATUS_GET(data);
anar = enet_read_phy(ptr, JL1111_ADDR, JL1111_ANAR);
anlpar = enet_read_phy(ptr, JL1111_ADDR, JL1111_ANLPAR);
data = anar & anlpar;
if (JL1111_ANAR_100BASE_TX_GET(data)) {
if (JL1111_ANAR_100BASE_TX_FD_GET(data)) {
status->enet_phy_speed = enet_phy_port_speed_100mbps;
status->enet_phy_duplex = enet_phy_duplex_full;
} else {
status->enet_phy_speed = enet_phy_port_speed_100mbps;
status->enet_phy_duplex = enet_phy_duplex_half;
}
} else if (JL1111_ANAR_10BASE_T_GET(data)) {
if (JL1111_ANAR_10BASE_T_FD_GET(data)) {
status->enet_phy_speed = enet_phy_port_speed_10mbps;
status->enet_phy_duplex = enet_phy_duplex_full;
} else {
status->enet_phy_speed = enet_phy_port_speed_10mbps;
status->enet_phy_duplex = enet_phy_duplex_half;
}
} else {
}
}
bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111.h
+55
View File
@@ -0,0 +1,55 @@
/*
* Copyright (c) 2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef HPM_JL1111_H
#define HPM_JL1111_H
/*---------------------------------------------------------------------
* Includes
*---------------------------------------------------------------------
*/
#include "hpm_enet_phy.h"
#include "hpm_common.h"
#include "hpm_enet_regs.h"
/*---------------------------------------------------------------------
* Macro Const Definitions
*---------------------------------------------------------------------
*/
#ifndef JL1111_ADDR
#define JL1111_ADDR (0U)
#endif
#define JL1111_ID1 (0x937CU)
#define JL1111_ID2 (0x10U)
/*---------------------------------------------------------------------
* Typedef Struct Declarations
*---------------------------------------------------------------------
*/
typedef struct {
bool loopback;
uint8_t speed;
bool auto_negotiation;
uint8_t duplex;
} jl1111_config_t;
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*---------------------------------------------------------------------
* Exported Functions
*---------------------------------------------------------------------
*/
void jl1111_reset(ENET_Type *ptr);
void jl1111_basic_mode_default_config(ENET_Type *ptr, jl1111_config_t *config);
bool jl1111_basic_mode_init(ENET_Type *ptr, jl1111_config_t *config);
void jl1111_get_phy_status(ENET_Type *ptr, enet_phy_status_t *status);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* HPM_JL1111_H */
bsp/hpmicro/libraries/hpm_sdk/components/enet_phy/jl1111/hpm_jl1111_regs.h
+734
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/cc10128007.c
+139
View File
@@ -0,0 +1,139 @@
/*
* Copyright (c) 2023 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#include "hpm_panel.h"
#include "hpm_pixelmux_drv.h"
#include "hpm_lvb_drv.h"
static void lvds_panel_lvb_init(hpm_panel_t *panel)
{
LVB_Type *lvb_base = panel->hw_if.video.lvds.lvb_base;
lvb_config_t lvb_config;
lvb_get_default_config(&lvb_config);
lvb_config.split_mode_en = false;
lvb_config.txclk_shift = lvb_txclk_shift_1100011;
lvb_init(lvb_base, &lvb_config);
lvb_ch_config_t lvb_ch_cfg;
lvb_ch_cfg.map = lvb_ch_mapping_vesa;
if (panel->hw_if.video.lvds.channel_di_index == 0)
lvb_ch_cfg.data_src = lvb_ch_data_source_di0;
else
lvb_ch_cfg.data_src = lvb_ch_data_source_di1;
if (panel->hw_if.video.lvds.channel_index == 0) {
lvb_ch_config(lvb_base, lvb_ch_num_0, &lvb_ch_cfg);
lvb_ch_enable(lvb_base, lvb_ch_num_0);
} else {
lvb_ch_config(lvb_base, lvb_ch_num_1, &lvb_ch_cfg);
lvb_ch_enable(lvb_base, lvb_ch_num_1);
}
}
static void lvds_panel_phy_init(hpm_panel_t *panel)
{
LVB_Type *lvb_base = panel->hw_if.video.lvds.lvb_base;
lvds_phy_clk_param_t param;
uint32_t pixel_clk = panel->hw_if.lcdc_pixel_clk_khz * 1000;
pixelmux_lvds_phy_calc_pll_cfg(pixel_clk, false, &param);
lvb_lvds_phy_lane_config_t lvds_lane_cfg;
lvb_lvds_phy_lane_get_default_config(&lvds_lane_cfg);
lvds_lane_cfg.fvco_div4 = param.reg.data_rate_div4;
if (panel->hw_if.video.lvds.channel_index == 0) {
pixelmux_config_lvds_tx_phy0_clk(&param.reg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx0, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx1, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx2, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx3, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_txck, &lvds_lane_cfg);
lvb_lvds_phy0_poweron(lvb_base);
while (lvb_lvds_phy0_pll_is_lock(lvb_base) == false) {
}
} else {
pixelmux_config_lvds_tx_phy1_clk(&param.reg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx0, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx1, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx2, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx3, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_txck, &lvds_lane_cfg);
lvb_lvds_phy1_poweron(lvb_base);
while (lvb_lvds_phy1_pll_is_lock(lvb_base) == false) {
}
}
}
static void reset(hpm_panel_t *panel)
{
if (!panel->hw_if.set_reset_pin_level)
return;
panel->hw_if.set_reset_pin_level(0);
hpm_panel_delay_us(2000);
panel->hw_if.set_reset_pin_level(1);
hpm_panel_delay_us(2000);
}
static void init(hpm_panel_t *panel)
{
if (panel->hw_if.set_video_router)
panel->hw_if.set_video_router();
lvds_panel_lvb_init(panel);
lvds_panel_phy_init(panel);
}
static void power_on(hpm_panel_t *panel)
{
if (panel->state.power_state != HPM_PANEL_STATE_POWER_ON &&
panel->hw_if.set_backlight) {
if (panel->state.backlight_percent == 0)
panel->state.backlight_percent = 100;
panel->hw_if.set_backlight(panel->state.backlight_percent);
panel->state.power_state = HPM_PANEL_STATE_POWER_ON;
}
}
static void power_off(hpm_panel_t *panel)
{
if (panel->state.power_state != HPM_PANEL_STATE_POWER_OFF &&
panel->hw_if.set_backlight) {
panel->hw_if.set_backlight(0);
panel->state.power_state = HPM_PANEL_STATE_POWER_OFF;
}
}
hpm_panel_t panel_cc10128007 = {
.name = "cc10128007",
.if_type = HPM_PANEL_IF_TYPE_LVDS_SINGLE,
.timing = {
.pixel_clock_khz = 74250,
.hactive = 800,
.hfront_porch = 60,
.hback_porch = 60,
.hsync_len = 40,
.vactive = 1280,
.vfront_porch = 18,
.vback_porch = 18,
.vsync_len = 6,
},
.funcs = {
.reset = reset,
.init = init,
.power_on = power_on,
.power_off = power_off,
},
};
bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/mc10128007_31b.c
+354
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/tm070rdh13.c
+73
View File
@@ -0,0 +1,73 @@
/*
* Copyright (c) 2023 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#include "hpm_panel.h"
static void reset(hpm_panel_t *panel)
{
if (!panel->hw_if.set_reset_pin_level)
return;
panel->hw_if.set_reset_pin_level(0);
hpm_panel_delay_ms(20);
panel->hw_if.set_reset_pin_level(1);
hpm_panel_delay_ms(20);
}
static void init(hpm_panel_t *panel)
{
if (panel->hw_if.set_video_router)
panel->hw_if.set_video_router();
}
static void power_on(hpm_panel_t *panel)
{
if (panel->state.power_state != HPM_PANEL_STATE_POWER_ON &&
panel->hw_if.set_backlight) {
if (panel->state.backlight_percent == 0)
panel->state.backlight_percent = 100;
panel->hw_if.set_backlight(panel->state.backlight_percent);
panel->state.power_state = HPM_PANEL_STATE_POWER_ON;
}
}
static void power_off(hpm_panel_t *panel)
{
if (panel->state.power_state != HPM_PANEL_STATE_POWER_OFF &&
panel->hw_if.set_backlight) {
panel->hw_if.set_backlight(0);
panel->state.power_state = HPM_PANEL_STATE_POWER_OFF;
}
}
hpm_panel_t panel_tm070rdh13 = {
.name = "tm070rdh13",
.if_type = HPM_PANEL_IF_TYPE_RGB,
.timing = {
.pixel_clock_khz = 60000,
.hactive = 800,
.hfront_porch = 50,
.hback_porch = 36,
.hsync_len = 10,
.hsync_pol = 1,
.vactive = 480,
.vfront_porch = 10,
.vback_porch = 20,
.vsync_len = 3,
.vsync_pol = 1,
},
.funcs = {
.reset = reset,
.init = init,
.power_on = power_on,
.power_off = power_off,
},
};
bsp/hpmicro/libraries/hpm_sdk/components/panel/panels/tm103xdgp01.c
+107
View File
@@ -0,0 +1,107 @@
/*
* Copyright (c) 2023 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#include "hpm_panel.h"
#include "hpm_pixelmux_drv.h"
#include "hpm_lvb_drv.h"
static void lvds_panel_lvb_init(hpm_panel_t *panel)
{
LVB_Type *lvb_base = panel->hw_if.video.lvds.lvb_base;
lvb_config_t lvb_config;
lvb_get_default_config(&lvb_config);
lvb_config.split_mode_en = true;
lvb_config.txclk_shift = lvb_txclk_shift_1100011;
lvb_init(lvb_base, &lvb_config);
lvb_ch_config_t lvb_ch_cfg;
lvb_ch_cfg.map = lvb_ch_mapping_vesa;
if (panel->hw_if.video.lvds.channel_di_index == 0)
lvb_ch_cfg.data_src = lvb_ch_data_source_di0;
else
lvb_ch_cfg.data_src = lvb_ch_data_source_di1;
lvb_ch_config(lvb_base, lvb_ch_num_0, &lvb_ch_cfg);
lvb_ch_config(lvb_base, lvb_ch_num_1, &lvb_ch_cfg);
lvb_ch_enable(lvb_base, lvb_ch_num_0);
lvb_ch_enable(lvb_base, lvb_ch_num_1);
}
static void lvds_panel_phy_init(hpm_panel_t *panel)
{
LVB_Type *lvb_base = panel->hw_if.video.lvds.lvb_base;
lvds_phy_clk_param_t param;
uint32_t pixel_clk = panel->hw_if.lcdc_pixel_clk_khz * 1000;
pixelmux_lvds_phy_calc_pll_cfg(pixel_clk, true, &param);
pixelmux_config_lvds_tx_phy0_clk(&param.reg);
pixelmux_config_lvds_tx_phy1_clk(&param.reg);
lvb_lvds_phy_lane_config_t lvds_lane_cfg;
lvb_lvds_phy_lane_get_default_config(&lvds_lane_cfg);
lvds_lane_cfg.fvco_div4 = param.reg.data_rate_div4;
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx0, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx1, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx2, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_tx3, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds0_txck, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx0, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx1, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx2, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_tx3, &lvds_lane_cfg);
lvb_lvds_phy_lane_init(lvb_base, lvb_lvds_lane_idx_lvds1_txck, &lvds_lane_cfg);
lvb_lvds_phy0_poweron(lvb_base);
lvb_lvds_phy1_poweron(lvb_base);
while (lvb_lvds_phy_split_pll_is_lock(lvb_base) == false) {
}
}
static void reset(hpm_panel_t *panel)
{
if (!panel->hw_if.set_reset_pin_level)
return;
panel->hw_if.set_reset_pin_level(0);
hpm_panel_delay_us(2000);
panel->hw_if.set_reset_pin_level(1);
hpm_panel_delay_us(2000);
}
static void init(hpm_panel_t *panel)
{
if (panel->hw_if.set_video_router)
panel->hw_if.set_video_router();
lvds_panel_lvb_init(panel);
lvds_panel_phy_init(panel);
}
hpm_panel_t panel_tm103xdgp01 = {
.name = "tm103xdgp01",
.if_type = HPM_PANEL_IF_TYPE_LVDS_SPLIT,
.timing = {
.pixel_clock_khz = 45000,
.hactive = 1920,
.hfront_porch = 32,
.hback_porch = 32,
.hsync_len = 64,
.vactive = 720,
.vfront_porch = 2,
.vback_porch = 2,
.vsync_len = 4,
},
.funcs = {
.reset = reset,
.init = init,
},
};
bsp/hpmicro/libraries/hpm_sdk/components/ppi/hpm_ppi.c
+271
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bsp/hpmicro/libraries/hpm_sdk/components/ppi/hpm_ppi.h
+58
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@@ -0,0 +1,58 @@
/*
* Copyright (c) 2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef _HPM_PPI_H
#define _HPM_PPI_H
/*---------------------------------------------------------------------
* Includes
*---------------------------------------------------------------------
*/
#include "hpm_ppi_drv.h"
/**
* @brief ppi async sram config structure
*
*/
typedef struct {
uint32_t base_address; /**< external SRAM base address, should be 1MB aligned */
uint32_t size_in_byte; /**< external SRAM size in byte */
ppi_port_size_t port_size; /**< port size */
bool ad_mux_mode; /**< addr and data mux mode */
bool cs_valid_polarity; /**< cs valid polarity */
bool dm_valid_polarity; /**< dm valid polarity */
bool addr_valid_polarity; /**< addr valid polarity */
uint8_t adv_ctrl_pin; /**< adv ctrl pin number, 0 - 7 */
uint8_t rel_ctrl_pin; /**< rel ctrl pin number, 0 - 7 */
uint8_t wel_ctrl_pin; /**< wel ctrl pin number, 0 - 7 */
uint8_t as_in_ns; /**< address setup time */
uint8_t ah_in_ns; /**< address hold time */
uint8_t rel_in_ns; /**< RE low time */
uint8_t reh_in_ns; /**< RE high time */
uint8_t wel_in_ns; /**< WE low time */
uint8_t weh_in_ns; /**< WE high time */
} ppi_async_sram_config_t;
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/**
* @brief config async sram
*
* @param[in] ppi PPI base address
* @param[in] cs_index cs index, value: 0 - 3
* @param[in] cmd_index cmd start index
* @param[in] config async sram config structure pointer, @ref ppi_async_sram_config_t
*/
void ppi_config_async_sram(PPI_Type *ppi, uint8_t cs_index, uint8_t cmd_start_index, ppi_async_sram_config_t *config);
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _HPM_PPI_H */
bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.c
+824
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/components/spi/hpm_spi.h
+181
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@@ -23,6 +23,10 @@
#define SPI_CS_ACTIVE 0
#endif
#ifndef USE_DMA_MGR
#define USE_DMA_MGR (0U)
#endif
/* Every transaction can be delineated by 3 dma descriptions: SPI control, SPI cmd, SPI data */
#define SPI_DMA_DESC_COUNT_PER_TRANS (3U)
@@ -58,6 +62,23 @@ typedef struct {
dma_linked_descriptor_t *dma_linked_descriptor;
} spi_context_t;
/**
* @brief spi configuration init structure
*/
typedef struct {
spi_mode_selection_t mode; /*!< the spi operating mode */
spi_data_phase_format_t io_mode; /*!< the spi data line mode */
spi_sclk_idle_state_t clk_polarity; /*!< CPOL */
spi_sclk_sampling_clk_edges_t clk_phase; /*!< CPHA */
spi_shift_direction_t direction; /*!< MSB or LSB data shift direction */
uint8_t data_len; /*!< the unit is bit (1~32bit) */
bool data_merge; /*!< data Merge mode*/
} spi_initialize_config_t;
#if USE_DMA_MGR
typedef void (*spi_dma_complete_cb)(uint32_t channel);
#endif
#ifdef __cplusplus
extern "C" {
#endif
@@ -85,6 +106,166 @@ hpm_stat_t hpm_spi_setup_dma_transfer(spi_context_t *context, spi_control_config
*/
hpm_stat_t hpm_spi_release_gpio_cs(spi_context_t *context);
/**
* @brief spi get default init config
*
* @note it's no command/address/token phase, only data phase.
*
* @param [out] config spi_init_config_t
*/
void hpm_spi_get_default_init_config(spi_initialize_config_t *config);
/**
* @brief initialize for spi
*
* @note it's no command/address/token phase, only data phase.
*
* @param [in] ptr SPI base address
* @param [in] config spi_init_config_t struct
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_initialize(SPI_Type *ptr, spi_initialize_config_t *config);
/**
* @brief set spi sclk frequency for spi master
*
* @param [in] ptr SPI base address
* @param [in] freq spi sclk frequency
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_set_sclk_frequency(SPI_Type *ptr, uint32_t freq);
/**
* @brief transmit and receive block for spi
*
* @note it's no command/address/token phase, only data phase.
*
* @param [in] ptr SPI base address
* @param [in] wbuff spi sent data buff address
* @param [out] rbuff spi receive data buff address
* @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX
* @param [in] timeout wait time. unit is millisecond
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_transmit_receive_blocking(SPI_Type *ptr, uint8_t *wbuff, uint8_t *rbuff, uint32_t size, uint32_t timeout);
/**
* @brief receive block for spi
*
* @note it's no command/address/token phase, only data phase.
*
* @param [in] ptr SPI base address
* @param [out] buff spi receive data buff address
* @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX
* @param [in] timeout wait time. unit is millisecond
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_receive_blocking(SPI_Type *ptr, uint8_t *buff, uint32_t size, uint32_t timeout);
/**
* @brief transmit block for spi
*
* @note it's no command/address/token phase, only data phase.
*
* @param [in] ptr SPI base address
* @param [in] buff spi sent data buff address
* @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX
* @param [in] timeout wait time. unit is millisecond
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_transmit_blocking(SPI_Type *ptr, uint8_t *buff, uint32_t size, uint32_t timeout);
/**
* @brief transmit and receive setup dma for spi
*
* @note it's no command/address/token phase, only data phase.
* main configuration spi dma related, call this API after configuring DMA best
*
* @param [in] ptr SPI base address
* @param [in] size spi sent and receive data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_transmit_receive_setup_dma(SPI_Type *ptr, uint32_t size);
/**
* @brief receive setup dma for spi
*
* @note it's no command/address/token phase, only data phase.
* main configuration spi dma related, call this API after configuring DMA best
*
* @param [in] ptr SPI base address
* @param [in] size spi receive data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_receive_setup_dma(SPI_Type *ptr, uint32_t size);
/**
* @brief transmit setup dma for spi
*
* @note it's no command/address/token phase, only data phase.
* main configuration spi dma related, call this API after configuring DMA best
*
* @param [in] ptr SPI base address
* @param [in] size spi transmit data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_transmit_setup_dma(SPI_Type *ptr, uint32_t size);
#if USE_DMA_MGR
/**
* @brief Install callback for SPI DMA channel transmit and receive complete
*
* @note it's no command/address/token phase, only data phase.
*
* @param [in] ptr SPI base address
* @param [in] tx_complete callback for SPI TX DMA
* @param [in] rx_complete callback for SPI RX DMA
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_dma_install_callback(SPI_Type *ptr,
spi_dma_complete_cb tx_complete,
spi_dma_complete_cb rx_complete);
/**
* @brief transmit and receive noblock for spi
*
* @note it's no command/address/token phase, only data phase. use dma
*
* @param [in] ptr SPI base address
* @param [in] wbuff spi sent data buff address
* @param [out] rbuff spi receive data buff address
* @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_transmit_receive_nonblocking(SPI_Type *ptr, uint8_t *wbuff, uint8_t *rbuff, uint32_t size);
/**
* @brief receive noblock for spi
*
* @note it's no command/address/token phase, only data phase. use dma
*
* @param [in] ptr SPI base address
* @param [out] buff spi receive data buff address
* @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_receive_nonblocking(SPI_Type *ptr, uint8_t *buff, uint32_t size);
/**
* @brief transmit noblock for spi
*
* @note it's no command/address/token phase, only data phase. use dma
*
* @param [in] ptr SPI base address
* @param [in] buff spi sent data buff address
* @param [in] size spi sent data count(word unit), not greater than SPI_SOC_TRANSFER_COUNT_MAX
* @retval hpm_stat_t status_success if spi in busy status
*/
hpm_stat_t hpm_spi_transmit_nonblocking(SPI_Type *ptr, uint8_t *buff, uint32_t size);
#endif
#ifdef __cplusplus
}
#endif
bsp/hpmicro/libraries/hpm_sdk/components/touch/ft5406/hpm_touch_ft5406.c
+5
View File
@@ -49,3 +49,8 @@ hpm_stat_t touch_init(I2C_Type *i2c_ptr)
#endif
return stat;
}
hpm_stat_t touch_config(bool exchange_xy, bool reverse_x, bool reverse_y)
{
return status_fail;
}
bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_gt9xx.c
+144
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@@ -0,0 +1,144 @@
/*
* Copyright (c) 2021 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#include "hpm_gt9xx.h"
static uint8_t g_i2c_addr;
hpm_stat_t gt9xx_read_data(gt9xx_context_t *context, uint16_t addr, uint8_t *buf, uint32_t size)
{
uint8_t r[2];
r[0] = addr >> 8;
r[1] = addr & 0xFF;
return i2c_master_address_read(context->ptr, g_i2c_addr, r, sizeof(r), buf, size);
}
hpm_stat_t gt9xx_write_data(gt9xx_context_t *context, uint16_t addr, uint8_t *buf, uint32_t size)
{
uint8_t r[2];
r[0] = addr >> 8;
r[1] = addr & 0xFF;
return i2c_master_address_write(context->ptr, g_i2c_addr, r, sizeof(r), buf, size);
}
hpm_stat_t gt9xx_read_register(gt9xx_context_t *context, uint16_t reg, uint8_t *buf)
{
return gt9xx_read_data(context, reg, buf, 1);
}
hpm_stat_t gt9xx_write_register(gt9xx_context_t *context, uint16_t reg, uint8_t val)
{
return gt9xx_write_data(context, reg, &val, 1);
}
hpm_stat_t gt9xx_soft_reset(gt9xx_context_t *context)
{
return gt9xx_write_register(context, GT9XX_CMD, 0);
}
static uint8_t gt9xx_calcualte_config_data_checksum(uint8_t *config)
{
uint8_t checksum = 0;
for (uint32_t i = 0; i < GT9XX_CONFIG_DATA_SIZE - 2; i++) {
checksum += config[i];
}
return (~checksum + 1);
}
hpm_stat_t gt9xx_read_config(gt9xx_context_t *context, uint8_t *buf, uint8_t size)
{
return gt9xx_read_data(context, GT9XX_CONFIG, buf, size);
}
hpm_stat_t gt9xx_init(gt9xx_context_t *context, uint16_t width, uint16_t height)
{
hpm_stat_t stat = status_success;
uint8_t config[GT9XX_CONFIG_DATA_SIZE] = {0};
#ifdef GT9XX_I2C_ADDR
g_i2c_addr = GT9XX_I2C_ADDR;
stat = gt9xx_read_data(context, GT9XX_CONFIG, config, sizeof(config));
if (stat != status_success) {
return stat;
}
#elif !GT9XX_NO_AUTO_PROBE
g_i2c_addr = GT9XX_I2C_ADDR0;
stat = gt9xx_read_data(context, GT9XX_CONFIG, config, sizeof(config));
if (stat != status_success) {
printf("0x%x failed to init GT9XX", g_i2c_addr);
g_i2c_addr = GT9XX_I2C_ADDR1;
printf(", try 0x%x\n", g_i2c_addr);
stat = gt9xx_read_data(context, GT9XX_CONFIG, config, sizeof(config));
}
if (stat != status_success) {
return stat;
}
#else
g_i2c_addr = GT9XX_I2C_ADDR0;
stat = gt9xx_read_data(context, GT9XX_CONFIG, config, sizeof(config));
if (stat != status_success) {
return stat;
}
#endif
if (config[GT9XX_CONFIG_DATA_SIZE - 2] != gt9xx_calcualte_config_data_checksum(config)) {
return status_fail;
}
/* < 90: fixed config; >=90 custom config */
if (config[GT9XX_CONFIG_DATA_CONFIG_VERSION] < 90) {
printf("ERR: GTXXX custom config can't be supported\n");
return status_fail;
} else {
context->abs_x_max = config[GT9XX_CONFIG_DATA_RESOLUTION_XH];
context->abs_x_max <<= 8;
context->abs_x_max |= config[GT9XX_CONFIG_DATA_RESOLUTION_XL];
context->abs_y_max = config[GT9XX_CONFIG_DATA_RESOLUTION_YH];
context->abs_y_max <<= 8;
context->abs_y_max |= config[GT9XX_CONFIG_DATA_RESOLUTION_YL];
}
/* stat = gt9xx_read_data(context, GT9XX_ID_B0, (uint8_t*)&val, sizeof(val)); */
/* if (stat != status_success) { */
/* return stat; */
/* } */
/* if (val != GT9XX_PRODUCT_ID) { */
/* return status_fail; */
/* } */
config[GT9XX_CONFIG_DATA_RESOLUTION_XL] = width & 0xFF;
config[GT9XX_CONFIG_DATA_RESOLUTION_XH] = width >> 8;
config[GT9XX_CONFIG_DATA_RESOLUTION_YL] = height & 0xFF;
config[GT9XX_CONFIG_DATA_RESOLUTION_YH] = height >> 8;
config[GT9XX_CONFIG_DATA_TOUCH_NUMBER] = 5;
config[GT9XX_CONFIG_DATA_MODULE_SWITCH1] = (config[GT9XX_CONFIG_DATA_MODULE_SWITCH1] & ~0x3);
config[GT9XX_CONFIG_DATA_SIZE - 2] = gt9xx_calcualte_config_data_checksum(config);
config[GT9XX_CONFIG_DATA_SIZE - 1] = 1;
/*
* for (uint8_t i = 0; i < 5; i++) {
* gt9xx_write_data(context, GT9XX_CONFIG, config, GT9XX_CONFIG_DATA_SIZE);
* }
*/
gt9xx_write_register(context, GT9XX_CMD, GT9XX_CMD_SOFT_RESET);
return status_success;
}
hpm_stat_t gt9xx_read_touch_data(gt9xx_context_t *context,
gt9xx_touch_data_t *touch_data)
{
hpm_stat_t stat = status_success;
stat = gt9xx_read_data(context, GT9XX_STATUS,
(uint8_t *)touch_data, sizeof(gt9xx_touch_data_t));
if (stat != status_success) {
return stat;
}
return stat;
}
bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_gt9xx.h
+136
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@@ -0,0 +1,136 @@
/*
* Copyright (c) 2021 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef HPM_GT9XX_H
#define HPM_GT9XX_H
#include "board.h"
#include "hpm_common.h"
#include "hpm_i2c_drv.h"
#ifdef BOARD_GT9XX_ADDR
/* if i2c addres is specified by board, use it */
#define GT9XX_I2C_ADDR BOARD_GT9XX_ADDR
/* no auto probe in this case */
#define GT9XX_NO_AUTO_PROBE 1
#else
#undef GT9XX_I2C_ADDR
/* enable auto probe */
#ifndef GT9XX_NO_AUTO_PROBE
#define GT9XX_NO_AUTO_PROBE 0
#endif
/* i2c device address candidates */
#define GT9XX_I2C_ADDR0 (0x14U)
#define GT9XX_I2C_ADDR1 (0x5DU)
#endif
#define GT9XX_PRODUCT_ID (0x313139U)
/*
* GT9XX registers at operation mode
*/
#define GT9XX_CMD (0x8040U)
#define GT9XX_CMD_READ_COORD_STAT (0U)
#define GT9XX_CMD_READ_RAW_DATA (1U)
#define GT9XX_CMD_SOFT_RESET (2U)
#define GT9XX_CMD_READ_SCREEN_OFF (5U)
#define GT9XX_CONFIG (0x8047U)
#define GT9XX_ID_B0 (0x8140U)
#define GT9XX_ID_B1 (0x8141U)
#define GT9XX_ID_B2 (0x8142U)
#define GT9XX_ID_B4 (0x8143U)
#define GT9XX_FW_VERSION_L (0x8144U)
#define GT9XX_FW_VERSION_H (0x8145U)
#define GT9XX_TOUCH_XL (0x8146U)
#define GT9XX_TOUCH_XH (0x8147U)
#define GT9XX_TOUCH_YL (0x8148U)
#define GT9XX_TOUCH_YH (0x8149U)
#define GT9XX_VENDOR_ID (0x814AU)
#define GT9XX_STATUS (0x814EU)
#define GT9XX_GET_STATUS_NUM_OF_POINTS(x) ((x) & 0xFU)
#define GT9XX_GET_STATUS_LARGE_DETECT(x) (((x) & 0x40U) >> 6)
#define GT9XX_GET_STATUS_BUFFER_STAT(x) (((x) & 0x80U) >> 7)
#define GT9XX_FIRST_POINT (0x814FU)
#define GT9XX_MAX_TOUCH_POINTS (5U)
#define GT9XX_CONFIG_DATA_SIZE (186U)
#define GT9XX_CONFIG_DATA_CONFIG_VERSION (0U)
#define GT9XX_CONFIG_DATA_RESOLUTION_XL (1U)
#define GT9XX_CONFIG_DATA_RESOLUTION_XH (2U)
#define GT9XX_CONFIG_DATA_RESOLUTION_YL (3U)
#define GT9XX_CONFIG_DATA_RESOLUTION_YH (4U)
#define GT9XX_CONFIG_DATA_TOUCH_NUMBER (5U)
#define GT9XX_CONFIG_DATA_MODULE_SWITCH1 (6U)
typedef struct {
uint8_t track_id;
uint8_t x_l;
uint8_t x_h;
uint8_t y_l;
uint8_t y_h;
uint8_t size_l;
uint8_t size_h;
uint8_t reserved;
} gt9xx_touch_point_t;
typedef struct {
uint8_t status;
gt9xx_touch_point_t points[GT9XX_MAX_TOUCH_POINTS];
} gt9xx_touch_data_t;
typedef struct {
I2C_Type *ptr;
uint16_t abs_x_max;
uint16_t abs_y_max;
bool exchange_xy;
bool reverse_x;
bool reverse_y;
} gt9xx_context_t;
#ifdef __cplusplus
extern "C" {
#endif
/*
* gt9xx initialization routine
*/
hpm_stat_t gt9xx_init(gt9xx_context_t *context, uint16_t width, uint16_t height);
/*
* gt9xx read touch data
*/
hpm_stat_t gt9xx_read_touch_data(gt9xx_context_t *context,
gt9xx_touch_data_t *touch_data);
/*
* gt9xx read data
*/
hpm_stat_t gt9xx_read_data(gt9xx_context_t *context, uint16_t addr,
uint8_t *buf, uint32_t size);
/*
* gt9xx write value to given register
*/
hpm_stat_t gt9xx_write_register(gt9xx_context_t *context,
uint16_t reg, uint8_t val);
/*
* gt9xx read value of given register
*/
hpm_stat_t gt9xx_read_register(gt9xx_context_t *context, uint16_t reg, uint8_t *buf);
/*
* gt9xx read config data
*/
hpm_stat_t gt9xx_read_config(gt9xx_context_t *context, uint8_t *buf, uint8_t size);
#ifdef __cplusplus
}
#endif
#endif /* HPM_GT9XX_H */
bsp/hpmicro/libraries/hpm_sdk/components/touch/gt9xx/hpm_touch_gt9xx.c
+93
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@@ -0,0 +1,93 @@
/*
* Copyright (c) 2021 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#include "board.h"
#include "hpm_touch.h"
#include "hpm_gpio_drv.h"
#include "hpm_gt9xx.h"
#include "hpm_touch.h"
gt9xx_context_t gt9xx = {0};
hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points)
{
hpm_stat_t stat = status_success;
gt9xx_touch_data_t touch_data = {0};
uint8_t num, i;
uint16_t tmp;
stat = gt9xx_read_touch_data(&gt9xx, &touch_data);
if (stat != status_success) {
printf("gt9xx read data failed\n");
return stat;
}
/* the buffer status is ready*/
if (GT9XX_GET_STATUS_BUFFER_STAT(touch_data.status) == 1) {
num = GT9XX_GET_STATUS_NUM_OF_POINTS(touch_data.status);
*num_of_points = num;
if (num > 0 && num <= GT9XX_MAX_TOUCH_POINTS) {
for (i = 0; i < num; i++) {
points[i].x = (touch_data.points[i].x_h & 0xF) << 8 | touch_data.points[i].x_l;
points[i].y = (touch_data.points[i].y_h & 0xF) << 8 | touch_data.points[i].y_l;
if (gt9xx.reverse_x)
points[i].x = gt9xx.abs_x_max - points[i].x;
if (gt9xx.reverse_y)
points[i].y = gt9xx.abs_y_max - points[i].y;
if (gt9xx.exchange_xy) {
tmp = points[i].x;
points[i].x = points[i].y;
points[i].y = tmp;
}
}
} else {
stat = status_touch_points_over_number;
}
gt9xx_write_register(&gt9xx, GT9XX_STATUS, 0);
} else {
stat = status_touch_buffer_no_ready;
}
return stat;
}
void pull_int_pin(bool high)
{
gpio_set_pin_output(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN);
gpio_write_pin(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN, high);
}
void float_int_pin(void)
{
gpio_set_pin_input(BOARD_CAP_INTR_GPIO, BOARD_CAP_INTR_GPIO_INDEX, BOARD_CAP_INTR_GPIO_PIN);
}
hpm_stat_t touch_init(I2C_Type *i2c_ptr)
{
hpm_stat_t stat = status_success;
gt9xx.ptr = i2c_ptr;
stat = gt9xx_init(&gt9xx, BOARD_LCD_WIDTH, BOARD_LCD_HEIGHT);
if (stat != status_success) {
return stat;
}
gt9xx_write_register(&gt9xx, GT9XX_CMD, GT9XX_CMD_READ_COORD_STAT);
return stat;
}
hpm_stat_t touch_config(bool exchange_xy, bool reverse_x, bool reverse_y)
{
gt9xx.exchange_xy = exchange_xy;
gt9xx.reverse_x = reverse_x;
gt9xx.reverse_y = reverse_y;
return status_success;
}
bsp/hpmicro/libraries/hpm_sdk/components/touch/hpm_touch.h
+5 -5
View File
@@ -13,11 +13,11 @@
#if defined(CONFIG_TOUCH_FT5406) && (CONFIG_TOUCH_FT5406 == 1)
#include "hpm_ft5406.h"
#define HPM_TOUCH_MAX_POINTS (FT5406_MAX_TOUCH_POINTS)
#elif defined(CONFIG_TOUCH_GT911) && (CONFIG_TOUCH_GT911 == 1)
#include "hpm_gt911.h"
#define HPM_TOUCH_MAX_POINTS (GT911_MAX_TOUCH_POINTS)
#elif defined(CONFIG_TOUCH_GT9XX) && (CONFIG_TOUCH_GT9XX == 1)
#include "hpm_gt9xx.h"
#define HPM_TOUCH_MAX_POINTS (GT9XX_MAX_TOUCH_POINTS)
#else
#error "unknown touch type, either have CONFIG_FT5406 or CONFIG_GT911 defined"
#error "unknown touch type, either have CONFIG_FT5406 or CONFIG_GT9XX defined"
#endif
enum {
@@ -35,7 +35,7 @@ extern "C" {
#endif
hpm_stat_t touch_init(I2C_Type *i2c_ptr);
hpm_stat_t touch_config(bool exchange_xy, bool reverse_x, bool reverse_y);
hpm_stat_t touch_get_data(touch_point_t *points, uint8_t *num_of_points);
#ifdef __cplusplus
bsp/hpmicro/libraries/hpm_sdk/components/usb/device/hpm_usb_device.c
+4 -4
View File
@@ -207,8 +207,11 @@ bool usb_device_edpt_open(usb_device_handle_t *handle, usb_endpoint_config_t *co
memset(p_qhd, 0, sizeof(dcd_qhd_t));
p_qhd->zero_length_termination = 1;
p_qhd->max_packet_size = config->max_packet_size;
p_qhd->max_packet_size = config->max_packet_size & 0x7FFu;
p_qhd->qtd_overlay.next = USB_SOC_DCD_QTD_NEXT_INVALID;
if (config->xfer == usb_xfer_isochronous) {
p_qhd->iso_mult = ((config->max_packet_size >> 11u) & 0x3u) + 1u;
}
usb_dcd_edpt_open(handle->regs, config);
@@ -274,9 +277,6 @@ bool usb_device_edpt_xfer(usb_device_handle_t *handle, uint8_t ep_addr, uint8_t
p_qhd->qtd_overlay.next = core_local_mem_to_sys_address(0, (uint32_t) first_p_qtd); /* link qtd to qhd */
if (usb_dcd_edpt_get_type(handle->regs, ep_addr) == usb_xfer_isochronous) {
p_qhd->iso_mult = 1;
}
usb_dcd_edpt_xfer(handle->regs, ep_idx);
return true;
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_adc16_drv.h
+30 -4
View File
@@ -118,7 +118,6 @@ typedef struct {
uint8_t res;
uint8_t conv_mode;
uint32_t adc_clk_div;
uint16_t conv_duration;
bool port3_realtime;
bool wait_dis;
bool sel_sync_ahb;
@@ -344,8 +343,8 @@ hpm_stat_t adc16_set_pmt_config(ADC16_Type *ptr, adc16_pmt_config_t *config);
*
* @param[in] ptr An ADC16 peripheral base address.
* @param[in] trig_ch An ADC16 peripheral trigger channel.
* @param[in] enable A enable control
* @return A result of setting queue enable in preemption
* @param[in] enable Set true to enable and false to disable.
* @return A result of setting queue enable in preemption.
* @retval status_success Get the result of an ADC16 conversion in oneshot mode successfully.
* @retval status_invalid_argument Get the result of an ADC16 conversion in oneshot mode unsuccessfully due to passing invalid arguments.
*/
@@ -353,6 +352,32 @@ hpm_stat_t adc16_set_pmt_queue_enable(ADC16_Type *ptr, uint8_t trig_ch, bool ena
/** @} */
/**
* @name Enablement Control
* @{
*/
/**
* @brief Enable the hw trigger control for the sequence mode.
*
* @param[in] ptr An ADC16 peripheral base address.
*
*/
static inline void adc16_seq_enable_hw_trigger(ADC16_Type *ptr)
{
ptr->SEQ_CFG0 |= ADC16_SEQ_CFG0_HW_TRIG_EN_MASK;
}
/**
* @brief Disable the hw trigger control for the sequence mode.
*
* @param[in] ptr An ADC16 peripheral base address.
*
*/
static inline void adc16_seq_disable_hw_trigger(ADC16_Type *ptr)
{
ptr->SEQ_CFG0 &= ~ADC16_SEQ_CFG0_HW_TRIG_EN_MASK;
}
/** @} */
/**
* @name DMA Control
* @{
@@ -556,7 +581,6 @@ hpm_stat_t adc16_trigger_seq_by_sw(ADC16_Type *ptr);
*/
hpm_stat_t adc16_trigger_pmt_by_sw(ADC16_Type *ptr, uint8_t trig_ch);
/**
* @brief Get the result in oneshot mode.
*
@@ -602,10 +626,12 @@ void adc16_disable_temp_sensor(ADC16_Type *ptr);
*
* @param[in] ptr An ADC16 peripheral base address.
*/
#if defined(HPM_IP_FEATURE_ADC16_HAS_MOT_EN) && HPM_IP_FEATURE_ADC16_HAS_MOT_EN
static inline void adc16_enable_motor(ADC16_Type *ptr)
{
ptr->ANA_CTRL0 |= ADC16_ANA_CTRL0_MOTO_EN_MASK;
}
#endif
/** @} */
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_cam_drv.h
+3
View File
@@ -11,6 +11,7 @@
#include "hpm_common.h"
#include "hpm_display_common.h"
#include "hpm_cam_regs.h"
#include "hpm_soc_feature.h"
/**
* @brief CAM driver APIs
@@ -80,7 +81,9 @@ typedef struct {
uint32_t width;
uint32_t height;
bool pixclk_sampling_falling;
#if defined(HPM_IP_FEATURE_CAM_INV_DEN) && (HPM_IP_FEATURE_CAM_INV_DEN == 1)
bool de_active_low; /* de_active_low must is same with hsync_active_low when dvp be used */
#endif
bool hsync_active_low;
bool vsync_active_low;
bool color_ext;
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_can_drv.h
+26 -18
View File
@@ -39,6 +39,7 @@ enum {
status_can_tx_fifo_full = MAKE_STATUS(status_group_can, 6), /**< CAN TX fifo full */
status_can_filter_index_invalid = MAKE_STATUS(status_group_can, 7), /**< CAN filter index is invalid */
status_can_filter_num_invalid = MAKE_STATUS(status_group_can, 8), /**< CAN filter number is invalid */
status_can_invalid_bit_timing = MAKE_STATUS(status_group_can, 9), /**< Invalid CAN bit timing parameter */
};
/**
@@ -56,10 +57,10 @@ enum {
/**
* @brief CAN Secondary Transmit buffer Status
*/
#define CAN_STB_IS_EMPTY (0U) /**< CAN Sencondary Transmit buffer is empty */
#define CAN_STB_LESS_EQUAL_HALF_FULL (1U) /**< CAN Sencondary Transmit buffer <= 1/2 * FULL */
#define CAN_STB_MORE_THAN_HALF_FULL (2U) /**< CAN Sencondary Transmit buffer > 1/2 * FULL */
#define CAN_STB_IS_FULL (3U) /**< CAN Sencondary Transmit buffer is full */
#define CAN_STB_IS_EMPTY (0U) /**< CAN Secondary Transmit buffer is empty */
#define CAN_STB_LESS_EQUAL_HALF_FULL (1U) /**< CAN Secondary Transmit buffer <= 1/2 * FULL */
#define CAN_STB_MORE_THAN_HALF_FULL (2U) /**< CAN Secondary Transmit buffer > 1/2 * FULL */
#define CAN_STB_IS_FULL (3U) /**< CAN Secondary Transmit buffer is full */
/**
* @brief CAN Receive Buffer States
@@ -73,14 +74,14 @@ enum {
* @brief CAN Error interrupts/flags
*
*/
#define CAN_ERROR_WARNING_LIMIT_FLAG (CAN_ERRINT_EWARN_MASK) /**< CAN Error Limit reached */
#define CAN_ERROR_PASSIVE_MODE_ACTIVE_FLAG (CAN_ERRINT_EPASS_MASK) /**< CAN Passive mode active */
#define CAN_ERROR_PASSIVE_INT_ENABLE (CAN_ERRINT_EPIE_MASK) /**< CAN Passive Interrupt Enable */
#define CAN_ERROR_PASSIVE_INT_FLAG (CAN_ERRINT_EPIF_MASK) /**< CAN Passive Interrupt Flag */
#define CAN_ERROR_ARBITRAITION_LOST_INT_ENABLE (CAN_ERRINT_ALIE_MASK) /**< CAN Abitration Lost Interrupt Enable */
#define CAN_ERROR_ARBITRAITION_LOST_INT_FLAG (CAN_ERRINT_ALIE_MASK) /**< CAN arbitration Lost Interrupt Flag */
#define CAN_ERROR_BUS_ERROR_INT_ENABLE (CAN_ERRINT_BEIE_MASK) /**< CAN BUS error Interrupt Enable */
#define CAN_ERROR_BUS_ERROR_INT_FLAG (CAN_ERRINT_BEIF_MASK) /**< CAN BUS error Interrupt flag */
#define CAN_ERROR_WARNING_LIMIT_FLAG (CAN_ERRINT_EWARN_MASK) /**< CAN Error Limit reached */
#define CAN_ERROR_PASSIVE_MODE_ACTIVE_FLAG (CAN_ERRINT_EPASS_MASK) /**< CAN Passive mode active */
#define CAN_ERROR_PASSIVE_INT_ENABLE (CAN_ERRINT_EPIE_MASK) /**< CAN Passive Interrupt Enable */
#define CAN_ERROR_PASSIVE_INT_FLAG (CAN_ERRINT_EPIF_MASK) /**< CAN Passive Interrupt Flag */
#define CAN_ERROR_ARBITRATION_LOST_INT_ENABLE (CAN_ERRINT_ALIE_MASK) /**< CAN Arbitration Lost Interrupt Enable */
#define CAN_ERROR_ARBITRATION_LOST_INT_FLAG (CAN_ERRINT_ALIE_MASK) /**< CAN arbitration Lost Interrupt Flag */
#define CAN_ERROR_BUS_ERROR_INT_ENABLE (CAN_ERRINT_BEIE_MASK) /**< CAN BUS error Interrupt Enable */
#define CAN_ERROR_BUS_ERROR_INT_FLAG (CAN_ERRINT_BEIF_MASK) /**< CAN BUS error Interrupt flag */
/**
* @brief CAN Error Kinds
@@ -110,7 +111,7 @@ typedef enum _can_mode {
*/
typedef enum _can_bit_timing_option {
can_bit_timing_can2_0, /**< CAN 2.0 bit timing option */
can_bit_timing_canfd_norminal, /**< CANFD norminal timing option */
can_bit_timing_canfd_nominal, /**< CANFD nominal timing option */
can_bit_timing_canfd_data, /**< CANFD data timing option */
} can_bit_timing_option_t;
@@ -245,7 +246,7 @@ typedef struct {
bool enable_self_ack; /**< CAN self-ack flag */
bool disable_ptb_retransmission; /**< disable re-transmission for primary transmit buffer */
bool disable_stb_retransmission; /**< disable re-transmission for secondary transmit buffer */
bool enable_tdc; /**< Enable transmittor delay compensation */
bool enable_tdc; /**< Enable transmitter delay compensation */
uint8_t filter_list_num; /**< element number of CAN filters in filter list */
can_filter_config_t *filter_list; /**< CAN filter list pointer */
@@ -279,6 +280,15 @@ static inline void can_reset(CAN_Type *base, bool enable)
}
}
/**
* @brief Force CAN controller to Bus-off mode
* @param [in] base CAN base address
*/
static inline void can_force_bus_off(CAN_Type *base)
{
base->CMD_STA_CMD_CTRL = CAN_CMD_STA_CMD_CTRL_BUSOFF_MASK;
}
/**
* @brief Set CAN mode
*
@@ -811,10 +821,8 @@ hpm_stat_t can_get_default_config(can_config_t *config);
*/
hpm_stat_t can_init(CAN_Type *base, can_config_t *config, uint32_t src_clk_freq);
/**
* @brief De-initialize the CAN controller
*
* @param [in] base CAN base address
*/
void can_deinit(CAN_Type *base);
@@ -920,7 +928,7 @@ hpm_stat_t can_send_high_priority_message_nonblocking(CAN_Type *base, const can_
* @param [in] base CAN base address
* @param [out] message CAN message buffer
*
* @retval status_success API exection is successful
* @retval status_success API execution is successful
* @retval status_invalid_argument Invalid parameters
* @retval status_can_bit_error CAN bit error happened during receiving message
* @retval status_can_form_error CAN form error happened during receiving message
@@ -940,7 +948,7 @@ hpm_stat_t can_receive_message_blocking(CAN_Type *base, can_receive_buf_t *messa
* @param [in] base CAN base address
* @param [out] message CAN message buffer
*
* @retval status_success API exection is successful
* @retval status_success API execution is successful
* @retval status_invalid_argument Invalid parameters
* @retval status_can_bit_error CAN bit error happened during receiving message
* @retval status_can_form_error CAN form error happened during receiving message
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_clc_drv.h
+435
View File
File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_common.h
+79 -71
View File
@@ -156,6 +156,7 @@ enum {
status_group_ffa,
status_group_mcan,
status_group_ewdg,
status_group_esc,
status_group_middleware_start = 500,
status_group_sdmmc = status_group_middleware_start,
@@ -174,87 +175,16 @@ enum {
};
#if defined(__GNUC__)
/* alway_inline */
#define ATTR_ALWAYS_INLINE __attribute__((always_inline))
/* weak */
#define ATTR_WEAK __attribute__((weak))
/* alignment */
#define ATTR_ALIGN(alignment) __attribute__((aligned(alignment)))
/* place var_declare at section_name, e.x. PLACE_AT(".target_section", var); */
#define ATTR_PLACE_AT(section_name) __attribute__((section(section_name)))
#define ATTR_PLACE_AT_WITH_ALIGNMENT(section_name, alignment) \
ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment)
#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable.bss")
#define ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment)
#define ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_PLACE_AT(".noncacheable.bss")
#define ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment)
/* initialize variable x with y using PLACE_AT_NONCACHEABLE_INIT(x) = {y}; */
#define ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_PLACE_AT(".noncacheable.init")
#define ATTR_PLACE_AT_NONCACHEABLE_INIT_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment)
#define ATTR_RAMFUNC ATTR_PLACE_AT(".fast")
#define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \
ATTR_RAMFUNC ATTR_ALIGN(alignment)
#define ATTR_SHARE_MEM ATTR_PLACE_AT(".sh_mem")
#define NOP() __asm volatile("nop")
#define WFI() __asm volatile("wfi")
#define HPM_ATTR_MACHINE_INTERRUPT __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)))
#define HPM_ATTR_SUPERVISOR_INTERRUPT __attribute__ ((section(".isr_s_vector"), interrupt("supervisor"), aligned(4)))
#elif defined(__ICCRISCV__)
/* alway_inline */
#define ATTR_ALWAYS_INLINE __attribute__((always_inline))
/* weak */
#define ATTR_WEAK __weak
/* alignment */
#define ATTR_ALIGN(alignment) __attribute__((aligned(alignment)))
/* place var_declare at section_name, e.x. PLACE_AT(".target_section", var); */
#define ATTR_PLACE_AT(section_name) __attribute__((section(section_name)))
#define ATTR_PLACE_AT_WITH_ALIGNMENT(section_name, alignment) \
ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment)
#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable.bss")
#define ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment)
#define ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_PLACE_AT(".noncacheable.bss")
#define ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment)
/* initialize variable x with y using PLACE_AT_NONCACHEABLE_INIT(x) = {y}; */
#define ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_PLACE_AT(".noncacheable.init")
#define ATTR_PLACE_AT_NONCACHEABLE_INIT_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment)
#define ATTR_RAMFUNC ATTR_PLACE_AT(".fast")
#define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \
ATTR_RAMFUNC ATTR_ALIGN(alignment)
#define ATTR_SHARE_MEM ATTR_PLACE_AT(".sh_mem")
#define NOP() __asm volatile("nop")
#define WFI() __asm volatile("wfi")
#define HPM_ATTR_MACHINE_INTERRUPT __machine __interrupt
#define HPM_ATTR_SUPERVISOR_INTERRUPT __supervisor __interrupt
@@ -270,6 +200,58 @@ struct timeval {
#error Unknown toolchain
#endif
#if defined(__GNUC__) || defined(__ICCRISCV__)
/* alway_inline */
#define ATTR_ALWAYS_INLINE __attribute__((always_inline))
/* alignment */
#define ATTR_ALIGN(alignment) __attribute__((aligned(alignment)))
#define ATTR_PACKED __attribute__((packed, aligned(1)))
/* place var_declare at section_name, e.x. PLACE_AT(".target_section", var); */
#define ATTR_PLACE_AT(section_name) __attribute__((section(section_name)))
#define ATTR_PLACE_AT_WITH_ALIGNMENT(section_name, alignment) \
ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment)
#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable")
#define ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment)
#define ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_PLACE_AT(".noncacheable.bss")
#define ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment)
/* initialize variable x with y using PLACE_AT_NONCACHEABLE_INIT(x) = {y}; */
#define ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_PLACE_AT(".noncacheable.init")
#define ATTR_PLACE_AT_NONCACHEABLE_INIT_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment)
/* .fast_ram section */
#define ATTR_PLACE_AT_FAST_RAM ATTR_PLACE_AT(".fast_ram")
#define ATTR_PLACE_AT_FAST_RAM_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_FAST_RAM ATTR_ALIGN(alignment)
#define ATTR_PLACE_AT_FAST_RAM_BSS ATTR_PLACE_AT(".fast_ram.bss")
#define ATTR_PLACE_AT_FAST_RAM_BSS_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_FAST_RAM_BSS ATTR_ALIGN(alignment)
#define ATTR_PLACE_AT_FAST_RAM_INIT ATTR_PLACE_AT(".fast_ram.init")
#define ATTR_PLACE_AT_FAST_RAM_INIT_WITH_ALIGNMENT(alignment) \
ATTR_PLACE_AT_FAST_RAM_INIT ATTR_ALIGN(alignment)
#define ATTR_RAMFUNC ATTR_PLACE_AT(".fast")
#define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \
ATTR_RAMFUNC ATTR_ALIGN(alignment)
#define ATTR_SHARE_MEM ATTR_PLACE_AT(".sh_mem")
#define NOP() __asm volatile("nop")
#define WFI() __asm volatile("wfi")
#endif
#ifdef __cplusplus
extern "C" {
#endif
@@ -333,6 +315,32 @@ static inline uint32_t get_first_set_bit_from_msb(uint32_t value)
return i;
}
/**
* @brief Convert the elapsed ticks to microseconds according to the source clock frequency
* @param [in] ticks elapsed ticks
* @param [in] src_clk_freq The Frequency of the source
*
* @return elapsed microseconds
*/
static inline uint32_t hpm_convert_ticks_to_us(uint32_t ticks, uint32_t src_clk_freq)
{
uint32_t ticks_per_us = (src_clk_freq + 1000000UL - 1UL) / 1000000UL;
return (ticks + ticks_per_us - 1UL) / ticks_per_us;
}
/**
* @brief Convert the elapsed ticks to milliseconds according to the source clock frequency
* @param [in] ticks elapsed ticks
* @param [in] src_clk_freq The Frequency of the source
*
* @return elapsed milliseconds
*/
static inline uint32_t hpm_convert_ticks_to_ms(uint32_t ticks, uint32_t src_clk_freq)
{
uint32_t ticks_per_ms = (src_clk_freq + 1000UL - 1UL) / 1000UL;
return (ticks + ticks_per_ms - 1UL) / ticks_per_ms;
}
#ifdef __cplusplus
}
#endif
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dao_drv.h
+1 -1
View File
@@ -44,7 +44,7 @@ typedef struct dao_config {
bool enable_mono_output;
uint8_t default_output_level;
uint8_t channel_count;
#if defined(DAO_SOC_SUPPORT_DATA_FORMAT_CONFIG) && (DAO_SOC_SUPPORT_DATA_FORMAT_CONFIG == 1)
#if defined(HPM_IP_FEATURE_DAO_DATA_FORMAT_CONFIG) && (HPM_IP_FEATURE_DAO_DATA_FORMAT_CONFIG == 1)
bool enable_tdm_mode;
bool frame_start_at_rising_edge;
uint8_t protocol;
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dma_drv.h
+1 -1
View File
@@ -497,7 +497,7 @@ static inline uint32_t dma_check_transfer_status(DMA_Type *ptr, uint8_t ch_index
*/
static inline void dma_clear_transfer_status(DMA_Type *ptr, uint8_t ch_index)
{
ptr->INTSTATUS &= ~((1 << (DMA_STATUS_TC_SHIFT + ch_index)) | (1 << (DMA_STATUS_ERROR_SHIFT + ch_index)) | (1 << (DMA_STATUS_ABORT_SHIFT + ch_index)));
ptr->INTSTATUS = ((1 << (DMA_STATUS_TC_SHIFT + ch_index)) | (1 << (DMA_STATUS_ERROR_SHIFT + ch_index)) | (1 << (DMA_STATUS_ABORT_SHIFT + ch_index)));
}
/**
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_dmav2_drv.h
+75 -2
View File
@@ -70,6 +70,11 @@
#define DMA_HANDSHAKE_OPT_ONE_BURST (0U)
#define DMA_HANDSHAKE_OPT_ALL_TRANSIZE (1U)
#define DMA_SWAP_MODE_TABLE (0U)
#define DMA_SWAP_MODE_BYTE (1U)
#define DMA_SWAP_MODE_HALF_WORD (2U)
#define DMA_SWAP_MODE_WORD (3U)
#define DMA_INTERRUPT_MASK_NONE (0U)
#define DMA_INTERRUPT_MASK_ERROR DMAV2_CHCTRL_CTRL_INTERRMASK_MASK
#define DMA_INTERRUPT_MASK_ABORT DMAV2_CHCTRL_CTRL_INTABTMASK_MASK
@@ -106,9 +111,9 @@ typedef struct dma_linked_descriptor {
uint32_t src_addr; /**< Source address */
uint32_t req_ctrl; /**< Request select */
uint32_t dst_addr; /**< Destination address */
uint32_t reserved0; /**< not used on dmav2 */
uint32_t swap_table; /**< Swap table */
uint32_t linked_ptr; /**< Linked descriptor address */
uint32_t reserved1; /**< not used on dmav2 */
uint32_t reserved0; /**< not used on dmav2 */
} dma_linked_descriptor_t;
/* @brief Channel config */
@@ -129,6 +134,14 @@ typedef struct dma_channel_config {
bool en_infiniteloop; /**< Infinite loop transfer enable. Attention: only DMAV2 support */
uint8_t handshake_opt; /**< Handshake transfer option. Attention: only DMAV2 support */
uint8_t burst_opt; /**< Burst size option. Attention: only DMAV2 support */
#if defined(HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS) && (HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS == 1)
bool en_src_burst_in_fixed_trans; /**< Source burst in fix transfer size enable, discard src_addr_ctrl setting. Attention: only DMAV2 support */
bool en_dst_burst_in_fixed_trans; /**< Destination burst in fix transfer size enable, discard dst_addr_ctrl setting. Attention: only DMAV2 support */
#endif
#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1)
uint8_t swap_mode; /**< Swap Mode. Attention: only DMAV2 support */
uint32_t swap_table; /**< Swap Table. Attention: only DMAV2 support */
#endif
} dma_channel_config_t;
/* @brief Channel config */
@@ -467,6 +480,66 @@ static inline void dma_set_handshake_option(DMAV2_Type *ptr, uint32_t ch_index,
ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) | DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(handshake_opt);
}
#if defined(HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS) && (HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS == 1)
/**
* @brief Set DMA channel source burst in fixed transfer size enable or disable
*
* @param[in] ptr DMA base address
* @param[in] ch_index Index of the channel
* @param[in] enable false - disable; true - enable
*
*/
static inline void dma_set_source_burst_in_fixed_transize_enable(DMAV2_Type *ptr, uint32_t ch_index, bool enable)
{
ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SRC_FIXBURST_MASK) | DMAV2_CHCTRL_CTRL_SRC_FIXBURST_SET(enable);
}
/**
* @brief Set DMA channel destination burst in fixed transfer size enable or disable
*
* @param[in] ptr DMA base address
* @param[in] ch_index Index of the channel
* @param[in] enable false - disable; true - enable
*
*/
static inline void dma_set_destination_burst_in_fixed_transize_enable(DMAV2_Type *ptr, uint32_t ch_index, bool enable)
{
ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_DST_FIXBURST_MASK) | DMAV2_CHCTRL_CTRL_DST_FIXBURST_SET(enable);
}
#endif
#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1)
/**
* @brief Set DMA channel swap mode
*
* @param[in] ptr DMA base address
* @param[in] ch_index Index of the channel
* @param[in] swap_mode swap mode
* @arg @ref DMA_SWAP_MODE_TABLE
* @arg @ref DMA_SWAP_MODE_BYTE
* @arg @ref DMA_SWAP_MODE_HALF_WORD
* @arg @ref DMA_SWAP_MODE_WORD
*
*/
static inline void dma_set_swap_mode(DMAV2_Type *ptr, uint32_t ch_index, uint8_t swap_mode)
{
ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMAV2_CHCTRL_CTRL_SWAP_CTL_MASK) | DMAV2_CHCTRL_CTRL_SWAP_CTL_SET(swap_mode);
}
/**
* @brief Set DMA channel swap table
*
* @param[in] ptr DMA base address
* @param[in] ch_index Index of the channel
* @param[in] swap_table swap table
*
*/
static inline void dma_set_swap_table(DMAV2_Type *ptr, uint32_t ch_index, uint32_t swap_table)
{
ptr->CHCTRL[ch_index].SWAPTABLE = swap_table;
}
#endif
/**
* @brief Abort channel transfer with mask
*
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_enet_drv.h
+13 -3
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023 HPMicro
* Copyright (c) 2021-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -59,7 +59,8 @@
typedef enum {
enet_normal_int_sum_en = ENET_DMA_INTR_EN_NIE_MASK,
enet_aboarmal_int_sum_en = ENET_DMA_INTR_EN_AIE_MASK,
enet_receive_int_en = ENET_DMA_INTR_EN_RIE_MASK
enet_receive_int_en = ENET_DMA_INTR_EN_RIE_MASK,
enet_transmit_int_en = ENET_DMA_INTR_EN_TIE_MASK
} enet_interrupt_enable_t;
/** @brief interrupt mask type */
@@ -153,6 +154,7 @@ typedef enum {
/** @brief enet interface selections */
typedef enum {
enet_inf_mii = 0,
enet_inf_rmii = 4,
enet_inf_rgmii = 1
} enet_inf_type_t;
@@ -232,7 +234,7 @@ typedef enum {
enet_pps_ctrl_bin_4096hz_digital_2048hz,
enet_pps_ctrl_bin_8192hz_digital_4096hz,
enet_pps_ctrl_bin_16384hz_digital_8192hz,
enet_pps_ctrl_bin_32867hz_digital_16384hz
enet_pps_ctrl_bin_32768hz_digital_16384hz
} enet_pps_ctrl_t;
/** @brief PPS0 commands */
@@ -545,6 +547,14 @@ extern "C" {
*/
void enet_get_default_tx_control_config(ENET_Type *ptr, enet_tx_control_config_t *config);
/**
* @brief Get a default interrupt config
*
* @param[in] ptr An Ethernet peripheral base address
* @param[in] config A pointer to a interrupt config structure
*/
void enet_get_default_interrupt_config(ENET_Type *ptr, enet_int_config_t *config);
/**
* @brief Get interrupt status
*
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_esc_drv.h
+347
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ewdg_drv.h
+4 -6
View File
@@ -19,6 +19,9 @@
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief EWDG error codes
@@ -159,9 +162,7 @@ typedef enum {
typedef enum {
ewdg_low_power_mode_halt = 0, /*!< Watchdog is halted in low power mode */
ewdg_low_power_mode_work_clock_div_4 = 1, /*!< Watchdog is will work with 1/4 normal clock in low power mode */
ewdg_low_power_mode_work_clock_div_2 = 2, /*!< Watchdog is will work with 1/2 normal clock in low power mode */
ewdg_low_power_mode_work_clock_normal = 3, /*!< Watchdog is will work with normal clock in low power mode */
ewdg_low_power_mode_work_clock_normal = 1, /*!< Watchdog is will work with normal clock in low power mode */
} ewdg_low_power_mode_t;
/***
@@ -505,9 +506,6 @@ void ewdg_disable_reset(EWDG_Type *ptr, uint32_t mask);
*/
void ewdg_switch_clock_source(EWDG_Type *ptr, ewdg_cnt_clk_sel_t clk_sel);
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_femc_drv.h
+4 -4
View File
@@ -114,18 +114,18 @@ typedef struct {
uint8_t prescaler; /**< presecaler */
uint8_t port_size; /**< SDRAM port size */
uint8_t burst_len_in_byte; /**< 1/2/4/8 bytes */
uint8_t cke_off_in_ns; /**< Tcks */
uint8_t cke_off_in_ns;
uint8_t act_to_precharge_in_ns; /**< Tras */
uint8_t precharge_to_act_in_ns; /**< Trp */
uint8_t act_to_rw_in_ns; /**< Trcd */
uint8_t act_to_act_in_ns; /**< Trrd */
uint8_t refresh_to_refresh_in_ns; /**< Trc */
uint8_t write_recover_in_ns; /**< Tdpl */
uint8_t write_recover_in_ns; /**< Twr */
uint8_t self_refresh_recover_in_ns; /**< Txsr */
uint8_t refresh_recover_in_ns; /**< Txsr */
uint8_t refresh_recover_in_ns; /**< Trc */
uint8_t refresh_in_ms; /**< Tref */
uint8_t idle_timeout_in_ns;
uint8_t data_width_in_byte;
uint8_t cmd_data_width;
uint8_t auto_refresh_count_in_one_burst;
bool delay_cell_disable; /**< Delay cell disable */
uint8_t delay_cell_value; /**< Delay cell value */
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ffa_drv.h
+62
View File
@@ -9,6 +9,7 @@
#include "hpm_common.h"
#include "hpm_ffa_regs.h"
#include "hpm_soc_ip_feature.h"
/**
* @brief FFA driver APIs
@@ -36,6 +37,10 @@
#define FFA_DATA_TYPE_REAL_Q15 (1U) /* !< FFA Data type: Real Q15 */
#define FFA_DATA_TYPE_COMPLEX_Q31 (2U) /* !< FFA Data type: Complex Q31 */
#define FFA_DATA_TYPE_COMPLEX_Q15 (3U) /* !< FFA Data type: Complex Q15 */
#if defined(HPM_IP_FEATURE_FFA_FP32) && HPM_IP_FEATURE_FFA_FP32
#define FFA_DATA_TYPE_COMPLEX_FP32 (4U) /* !< FFA Data type: Complex Q15 */
#define FFA_DATA_TYPE_REAL_FP32 (5U) /* !< FFA Data type: Complex Q15 */
#endif
/**
* @brief FFA Q31 data type definition
@@ -100,6 +105,14 @@ enum {
status_ffa_read_error = MAKE_STATUS(status_group_ffa, 4), /*!< FFA read error */
};
#if defined(HPM_IP_FEATURE_FFA_FP32) && HPM_IP_FEATURE_FFA_FP32
typedef enum {
input_data = 0,
output_data = 1,
coeff_data = 2
} ffa_fp32_status_source_t;
#endif
#ifdef __cplusplus
extern "C" {
#endif
@@ -157,6 +170,55 @@ static inline void ffa_disable_interrupt(FFA_Type *ptr, uint32_t mask)
ptr->INT_EN &= ~mask;
}
#if defined(HPM_IP_FEATURE_FFA_FP32) && HPM_IP_FEATURE_FFA_FP32
static inline void ffa_enable_fp32_interrupt(FFA_Type *ptr, uint32_t mask)
{
ptr->FP_CTRL |= mask;
}
static inline void ffa_disable_fp32_interrupt(FFA_Type *ptr, uint32_t mask)
{
ptr->FP_CTRL &= ~mask;
}
static inline void ffa_set_fp_status_source(FFA_Type *ptr, ffa_fp32_status_source_t source)
{
ptr->FP_CTRL = FFA_FP_CTRL_EXP_ST_SEL_SET(source);
}
static inline void ffa_enable_fp_bias(FFA_Type *ptr)
{
ptr->FP_CTRL |= FFA_FP_CTRL_OPT_BIAS_EXP_MASK;
}
static inline void ffa_disable_fp_bias(FFA_Type *ptr)
{
ptr->FP_CTRL &= ~FFA_FP_CTRL_OPT_BIAS_EXP_MASK;
}
static inline void ffa_set_coef_max_index(FFA_Type *ptr, uint8_t max)
{
ptr->FP_CTRL = (ptr->FP_CTRL & ~FFA_FP_CTRL_COEF_MAX_MASK) | FFA_FP_CTRL_COEF_MAX_SET(max);
}
static inline void ffa_set_output_max_index(FFA_Type *ptr, uint8_t max)
{
ptr->FP_CTRL = (ptr->FP_CTRL & ~FFA_FP_CTRL_OUT_MAX_MASK) | FFA_FP_CTRL_OUT_MAX_SET(max);
}
static inline void ffa_set_input_max_index(FFA_Type *ptr, uint8_t max)
{
ptr->FP_CTRL = (ptr->FP_CTRL & ~FFA_FP_CTRL_IN_MAX_MASK) | FFA_FP_CTRL_IN_MAX_SET(max);
}
static inline uint32_t ffa_get_fp_status(FFA_Type *ptr)
{
return ptr->FP_ST;
}
#endif
/**
* @brief Start an FFT operation
*
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_gptmr_drv.h
+169 -2
View File
File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_i2c_drv.h
+5 -1
View File
@@ -163,10 +163,14 @@ static inline void i2c_clear_fifo(I2C_Type *ptr)
* @param [in] ptr I2C base address
* @retval data count value in byte
*/
static inline uint8_t i2c_get_data_count(I2C_Type *ptr)
static inline uint16_t i2c_get_data_count(I2C_Type *ptr)
{
uint32_t i2c_ctrl = ptr->CTRL;
#ifdef I2C_CTRL_DATACNT_HIGH_MASK
return (I2C_CTRL_DATACNT_HIGH_GET(i2c_ctrl) << 8U) + I2C_CTRL_DATACNT_GET(i2c_ctrl);
#else
return I2C_CTRL_DATACNT_GET(i2c_ctrl);
#endif
}
/**
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lcdc_drv.h
+2 -2
View File
@@ -153,7 +153,7 @@ static inline void lcdc_disable_interrupt(LCDC_Type *ptr, uint32_t interrupt_mas
*/
static inline void lcdc_clear_status(LCDC_Type *ptr, uint32_t mask)
{
ptr->ST |= mask;
ptr->ST = mask;
}
/**
@@ -203,7 +203,7 @@ static inline bool lcdc_check_dma_status(LCDC_Type *ptr, uint32_t mask)
*/
static inline void lcdc_clear_dma_status(LCDC_Type *ptr, uint32_t mask)
{
ptr->DMA_ST |= mask;
ptr->DMA_ST = mask;
}
/**
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_lobs_drv.h
+283
View File
File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mbx_drv.h
+2 -2
View File
@@ -57,7 +57,7 @@ static inline void mbx_set_bus_access_response(MBX_Type *ptr, mbx_bus_access_res
* @param[in] ptr MBX base address
* @param[in] mask Mask of interrupts to be enabled
*/
static inline void mbx_enable_intr(MBX_Type *ptr, uint8_t mask)
static inline void mbx_enable_intr(MBX_Type *ptr, uint32_t mask)
{
ptr->CR |= mask;
}
@@ -68,7 +68,7 @@ static inline void mbx_enable_intr(MBX_Type *ptr, uint8_t mask)
* @param[in] ptr MBX base address
* @param[in] mask Mask of interrupts to be disabled
*/
static inline void mbx_disable_intr(MBX_Type *ptr, uint8_t mask)
static inline void mbx_disable_intr(MBX_Type *ptr, uint32_t mask)
{
ptr->CR &= ~mask;
}
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mcan_drv.h
+61 -27
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2023 HPMicro
* Copyright (c) 2023-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -26,19 +26,20 @@ extern "C" {
enum {
status_mcan_filter_index_out_of_range = MAKE_STATUS(status_group_mcan, 0),
status_mcan_rxfifo_empty,
status_mcan_rxfifo_full,
status_mcan_txbuf_full,
status_mcan_txfifo_full,
status_mcan_rxfifo0_busy,
status_mcan_rxfifo1_busy,
status_mcan_txbuf_index_out_of_range,
status_mcan_rxbuf_index_out_of_range,
status_mcan_rxbuf_empty,
status_mcan_tx_evt_fifo_empty,
status_mcan_timestamp_not_exist,
status_mcan_ram_out_of_range,
status_mcan_timeout,
status_mcan_rxfifo_empty = MAKE_STATUS(status_group_mcan, 1),
status_mcan_rxfifo_full = MAKE_STATUS(status_group_mcan, 2),
status_mcan_txbuf_full = MAKE_STATUS(status_group_mcan, 3),
status_mcan_txfifo_full = MAKE_STATUS(status_group_mcan, 4),
status_mcan_rxfifo0_busy = MAKE_STATUS(status_group_mcan, 5),
status_mcan_rxfifo1_busy = MAKE_STATUS(status_group_mcan, 6),
status_mcan_txbuf_index_out_of_range = MAKE_STATUS(status_group_mcan, 7),
status_mcan_rxbuf_index_out_of_range = MAKE_STATUS(status_group_mcan, 8),
status_mcan_rxbuf_empty = MAKE_STATUS(status_group_mcan, 9),
status_mcan_tx_evt_fifo_empty = MAKE_STATUS(status_group_mcan, 10),
status_mcan_timestamp_not_exist = MAKE_STATUS(status_group_mcan, 11),
status_mcan_ram_out_of_range = MAKE_STATUS(status_group_mcan, 12),
status_mcan_timeout = MAKE_STATUS(status_group_mcan, 13),
status_mcan_invalid_bit_timing = MAKE_STATUS(status_group_mcan, 14),
};
/**
@@ -646,6 +647,15 @@ typedef struct mcan_timeout_config_struct {
uint16_t timeout_period; /*!< Timeout period */
} mcan_timeout_config_t;
/**
* @brief MCAN Transmitter Delay Compensation Configuration
*/
typedef struct mcan_tdc_config_t {
uint8_t ssp_offset; /*!< SSP offset */
uint8_t filter_window_length; /*!< Filter Window Length */
} mcan_tdc_config_t;
/**
* @brief MCAN Configuration Structure
*/
@@ -678,7 +688,7 @@ typedef struct mcan_config_struct {
bool enable_tdc; /*!< Enable transmitter delay compensation */
bool enable_restricted_operation_mode; /*!< Enable Restricted Operation Mode: Receive only */
bool disable_auto_retransmission; /*!< Disable auto retransmission */
uint8_t padding[2];
mcan_tdc_config_t tdc_config; /*!< Transmitter Delay Compensation Configuration */
mcan_internal_timestamp_config_t timestamp_cfg; /*!< Internal Timestamp Configuration */
mcan_tsu_config_t tsu_config; /*!< TSU configuration */
mcan_ram_config_t ram_config; /*!< MCAN RAM configuration */
@@ -734,15 +744,6 @@ typedef struct mcan_protocol_status {
bool in_error_passive_state; /*!< Node is in error passive state */
} mcan_protocol_status_t;
/**
* @brief MCAN Transmitter Delay Compensation Configuration
*/
typedef struct mcan_tdc_config_t {
uint8_t ssp_offset; /*!< SSP offset */
uint8_t filter_window_length; /*!< Filter Window Length */
} mcan_tdc_config_t;
/**
* @brief MCAN Message Storage Indicator Types
*/
@@ -987,7 +988,7 @@ static inline void mcan_enable_write_to_prot_config_registers(MCAN_Type *ptr)
}
/**
* @brief Disalbe Write Access to Protected Configuration Registers
* @brief Disable Write Access to Protected Configuration Registers
* @param [in] ptr MCAN base
*/
static inline void mcan_disable_write_to_prot_config_registers(MCAN_Type *ptr)
@@ -1339,6 +1340,27 @@ static inline void mcan_send_add_request(MCAN_Type *ptr, uint32_t index)
ptr->TXBAR = (1UL << index);
}
/**
* @brief Request several transmission via specified TXBUF/FIFO Bit masks
* MCAN IP will transmit data in the buffer if corresponding bit in index_bitmask is asserted
* @param [in] ptr MCAN Base
* @param [in] index_bitmask TXFIFO/BUF bit masks
*/
static inline void mcan_send_add_multiple_requests(MCAN_Type *ptr, uint32_t index_bitmask)
{
ptr->TXBAR = index_bitmask;
}
/**
* @brief Cancel the TXBUF Send request
* @param [in] ptr MCAN Base
* @param [in] index TXBUF index
*/
static inline void mcan_cancel_tx_buf_send_request(MCAN_Type *ptr, uint32_t index)
{
ptr->TXBCR = (1UL << index);
}
/**
* @brief Check whether the Transmission completed via specified TXBUF/TXFIFO
* @param [in] ptr MCAN base
@@ -1685,6 +1707,18 @@ hpm_stat_t mcan_read_tx_evt_fifo(MCAN_Type *ptr, mcan_tx_event_fifo_elem_t *tx_e
*/
hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame);
/**
* @brief Request TXFIFO and fill data into TXFIFO
* @note This API can be used to prepare the data for several CAN frames prior to transmission.
* After this operation, software can call `mcan_send_add_request(ptr, *fifo_index)` API to trigger a transmission
* or call `mcan_send_add_requests(ptr, fifo_index_masks)` to trigger several transmissions
* @param [in] ptr MCAN base
* @param [in] tx_frame CAN Transmit Message buffer
* @param [out] fifo_index The index of the element in FIFO assigned to the tx_frame
* @return status_success if no errors reported
*/
hpm_stat_t mcan_request_and_fill_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index);
/**
* @brief Transmit CAN message via TX FIFO in non-blocking way
* @param [in] ptr MCAN base
@@ -1723,7 +1757,7 @@ hpm_stat_t mcan_receive_from_buf_blocking(MCAN_Type *ptr, uint32_t index, mcan_r
hpm_stat_t mcan_receive_from_fifo_blocking(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame);
/**
* @brief Get Timstamp from MCAN TX Event
* @brief Get Timestamp from MCAN TX Event
* @param [in] ptr MCAN base
* @param [in] tx_evt TX Event Element
* @param [out] timestamp Timestamp value
@@ -1736,7 +1770,7 @@ hpm_stat_t mcan_get_timestamp_from_tx_event(MCAN_Type *ptr,
mcan_timestamp_value_t *timestamp);
/**
* @brief Get Timstamp from MCAN RX frame
* @brief Get Timestamp from MCAN RX frame
* @param [in] ptr MCAN base
* @param [in] rx_msg Received message
* @param [out] timestamp Timestamp value
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_mtg_drv.h
+726
View File
File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pixelmux_drv.h
+24
View File
@@ -75,6 +75,16 @@ typedef enum {
pixelmux_mipi_dsi0_sel_lcdc1
} pixelmux_mipi_dsi0_select_t;
/**
* @brief mipi dsi pixel data type
*/
typedef enum {
pixelmux_mipi_dsi_data_type_rgb565 = 0,
pixelmux_mipi_dsi_data_type_rgb666 = 3,
pixelmux_mipi_dsi_data_type_rgb666_packed = 4,
pixelmux_mipi_dsi_data_type_rgb888 = 5,
} pixelmux_mipi_dsi_data_type_t;
/**
* @brief cam1 pixel data source
*/
@@ -226,6 +236,20 @@ void pixelmux_mipi_dsi0_data_source_enable(pixelmux_mipi_dsi0_select_t src);
*/
void pixelmux_mipi_dsi0_data_source_disable(void);
/**
* @brief set data type for mipi dsi1
*
* @param[in] type mipi dsi data type
*/
void pixelmux_mipi_dsi1_set_data_type(pixelmux_mipi_dsi_data_type_t type);
/**
* @brief set data type for mipi dsi0
*
* @param[in] type mipi dsi data type
*/
void pixelmux_mipi_dsi0_set_data_type(pixelmux_mipi_dsi_data_type_t type);
/**
* @brief select pixel data source and enable for camera1
*
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_plb_drv.h
+44 -4
View File
@@ -29,10 +29,30 @@
*
*/
typedef enum plb_chn {
plb_chn0 = 0,
plb_chn1 = 1,
plb_chn2 = 2,
plb_chn3 = 3,
#ifdef PLB_TYPE_B_0
plb_chn0 = PLB_TYPE_B_0,
#endif
#ifdef PLB_TYPE_B_1
plb_chn1 = PLB_TYPE_B_1,
#endif
#ifdef PLB_TYPE_B_2
plb_chn2 = PLB_TYPE_B_2,
#endif
#ifdef PLB_TYPE_B_3
plb_chn3 = PLB_TYPE_B_3,
#endif
#ifdef PLB_TYPE_B_4
plb_chn4 = PLB_TYPE_B_4,
#endif
#ifdef PLB_TYPE_B_5
plb_chn5 = PLB_TYPE_B_5,
#endif
#ifdef PLB_TYPE_B_6
plb_chn6 = PLB_TYPE_B_6,
#endif
#ifdef PLB_TYPE_B_7
plb_chn7 = PLB_TYPE_B_7,
#endif
} plb_chn_t;
/**
@@ -40,10 +60,30 @@ typedef enum plb_chn {
*
*/
typedef enum plb_type_a_lut_num {
#ifdef PLB_TYPE_A_0
plb_type_a_table0 = PLB_TYPE_A_0,
#endif
#ifdef PLB_TYPE_A_1
plb_type_a_table1 = PLB_TYPE_A_1,
#endif
#ifdef PLB_TYPE_A_2
plb_type_a_table2 = PLB_TYPE_A_2,
#endif
#ifdef PLB_TYPE_A_3
plb_type_a_table3 = PLB_TYPE_A_3,
#endif
#ifdef PLB_TYPE_A_4
plb_type_a_table4 = PLB_TYPE_A_4,
#endif
#ifdef PLB_TYPE_A_5
plb_type_a_table5 = PLB_TYPE_A_5,
#endif
#ifdef PLB_TYPE_A_6
plb_type_a_table6 = PLB_TYPE_A_6,
#endif
#ifdef PLB_TYPE_A_7
plb_type_a_table7 = PLB_TYPE_A_7,
#endif
} plb_type_a_lut_num_t;
/**
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pllctlv2_drv.h
+13 -1
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2022 HPMicro
* Copyright (c) 2022-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -137,6 +137,18 @@ static inline void pllctlv2_set_pll_step_time(PLLCTLV2_Type *ptr, uint8_t pll, u
*/
void pllctlv2_set_postdiv(PLLCTLV2_Type *ptr, uint8_t pll, uint8_t div_index, uint8_t div_value);
/**
* @brief Set the PLL via the low-level MFI, MFD and MFN
* PLL frequency = REF CLOCK * (mfi + 1.0 * mfn / mfd)
* @param [in] ptr PLLCTLV2 base
* @param [in] pll PLL index
* @param [in] mfi MFI value
* @param [in] mfn MFN value
* @retval status_invalid_argument some parameters are invalid
* @retval status_success operation is successful
*/
hpm_stat_t pllctlv2_set_pll_with_mfi_mfn(PLLCTLV2_Type *ptr, uint8_t pll, uint32_t mfi, uint32_t mfn);
/**
* @brief Initialize PLL to specified frequency
* Note: the specified PLL clock needs to be enabled before being configured
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_ppi_drv.h
+366
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwm_drv.h
+20 -1
View File
@@ -14,7 +14,7 @@
/**
* @brief PWM driver APIs
* @defgroup pwm_interface PWM driver APIs
* @ingroup io_interfaces
* @ingroup motor_interfaces
* @{
*
*/
@@ -94,6 +94,7 @@ typedef enum pwm_fault_source {
pwm_fault_source_internal_3 = PWM_GCR_FAULTI3EN_MASK, /**< FAULTI3 */
pwm_fault_source_external_0 = PWM_GCR_FAULTE0EN_MASK, /**< EXFAULTI0 */
pwm_fault_source_external_1 = PWM_GCR_FAULTE1EN_MASK, /**< EXFAULTI1 */
pwm_fault_source_debug = PWM_GCR_DEBUGFAULT_MASK, /**< Debug fault */
} pwm_fault_source_t;
/**
@@ -217,7 +218,9 @@ static inline void pwm_deinit(PWM_Type *pwm_x)
pwm_x->FRCMD = 0;
pwm_x->GCR = 0;
pwm_x->SHCR = 0;
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
pwm_x->HRPWM_CFG = 0;
#endif
for (uint8_t i = 0; i < PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT; i++) {
pwm_x->PWMCFG[i] = 0;
}
@@ -1000,6 +1003,22 @@ hpm_stat_t pwm_update_raw_cmp_edge_aligned(PWM_Type *pwm_x, uint8_t cmp_index,
hpm_stat_t pwm_update_raw_cmp_central_aligned(PWM_Type *pwm_x, uint8_t cmp1_index,
uint8_t cmp2_index, uint32_t target_cmp1, uint32_t target_cmp2);
#if defined(PWM_SOC_HRPWM_SUPPORT) && PWM_SOC_HRPWM_SUPPORT
/**
* @brief recovery hrpwm output
*
* @param pwm_x @ref PWM_Type PWM base address
*/
static inline void pwm_recovery_hrpwm_output(PWM_Type *pwm_x)
{
pwm_x->HRPWM_CFG |= PWM_HRPWM_CFG_CAL_SW_EN_MASK;
pwm_x->ANA_CFG0 |= PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK;
pwm_x->ANA_CFG0 &= ~PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK;
pwm_x->ANA_CFG0 |= PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK;
pwm_x->ANA_CFG0 &= ~PWM_ANA_CFG0_CAL_SW_TRIG_H_MASK;
pwm_x->HRPWM_CFG &= ~PWM_HRPWM_CFG_CAL_SW_EN_MASK;
}
/**
* @brief Enable high-precision pwm
*
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_pwmv2_drv.h
+1958
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeiv2_drv.h
+186 -12
View File
File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_qeov2_drv.h
+676
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File diff suppressed because it is too large Load Diff
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rdc_drv.h
+90 -1
View File
@@ -134,6 +134,11 @@ typedef enum rdc_input_acc_chn {
rdc_acc_chn_q = 1
} rdc_input_acc_chn_t;
typedef enum rdc_input_max_min_value_source {
rdc_value_at_adc = 0,
rdc_value_at_iir = 1
} rdc_input_max_min_value_source_t;
/**
* @brief Rdc status flags
*
@@ -188,7 +193,11 @@ typedef struct rdc_output_cfg {
*/
typedef struct rdc_input_cfg {
rdc_rectify_signal_t rectify_signal_sel; /**< Select reference point of rectify signal */
uint8_t acc_cycle_len; /**< Accumulate time, support on the fly change */
#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR)
bool acc_fast; /**< every adc value can be as one accumulate value, */
rdc_input_max_min_value_source_t max_min_value_position; /**< max min value position */
#endif
uint8_t acc_cycle_len; /**< Accumulate time, support on the fly change, Only acc_fast is zero, this bit is available */
rdc_acc_stamp_time_t acc_stamp; /**< Time stamp selection for accumulation */
uint32_t acc_input_chn_i; /**< Input channel selection for i_channel */
uint32_t acc_input_port_i; /**< Input port selection for i_channel */
@@ -205,6 +214,10 @@ typedef struct rdc_acc_cfg {
uint16_t continue_edge_num: 3; /**< Filtering val: 1 - 8 */
uint16_t edge_distance: 6; /**< Minimum distance between two edges 0-63 */
};
#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR)
bool enable_i_thrs_data_for_acc; /**< enable thrs data for accumulate */
bool enable_q_thrs_data_for_acc; /**< enable thrs data for accumulate */
#endif
uint8_t right_shift_without_sign; /**< Right shift without sign bit */
bool error_data_remove; /**< Toxic accumulation data be removed */
uint32_t exc_carrier_period; /**< The num in clock cycle for period of excitation 0-NULL others-cycles */
@@ -214,6 +227,19 @@ typedef struct rdc_acc_cfg {
uint32_t amp_min; /**< The minimum of acc amplitude */
} rdc_acc_cfg_t;
#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR)
/**
* @brief IIR Filter Configuration
*
*/
typedef struct rdc_iir_cfg {
float b; /**< IIR parameter for b branch */
float a1; /**< IIR parameter a1 for a1 branch*/
float a2; /**< IIR parameter a1 for a2 branch*/
bool enable_lowpass; /**< IIR in lowpass mode */
} rdc_iir_cfg_t;
#endif
/** @} */
/**
@@ -269,6 +295,69 @@ static inline void rdc_acc_disable(RDC_Type *ptr)
ptr->RDC_CTL &= ~RDC_RDC_CTL_ACC_EN_MASK;
}
#if defined(HPM_IP_FEATURE_RDC_IIR) && (HPM_IP_FEATURE_RDC_IIR)
/**
* @brief Enable IIR for adc input
*
* @param ptr @ref RDC_Type base
*/
static inline void rdc_irr_enable(RDC_Type *ptr)
{
ptr->RDC_CTL |= RDC_RDC_CTL_IIR_EN_MASK;
}
/**
* @brief Disable IIR for adc input
*
* @param ptr @ref RDC_Type base
*/
static inline void rdc_irr_disable(RDC_Type *ptr)
{
ptr->RDC_CTL &= ~RDC_RDC_CTL_IIR_EN_MASK;
}
/**
* @brief enable i thrs data for accumulate
*
* @param ptr @ref RDC_Type base
*/
static inline void rdc_enable_i_channel_thrs_data_for_acc(RDC_Type *ptr)
{
ptr->THRS_I |= RDC_THRS_I_THRS4ACC_MASK;
}
/**
* @brief disable i thrs data for accumulate
*
* @param ptr @ref RDC_Type base
*/
static inline void rdc_disable_i_channel_thrs_data_for_acc(RDC_Type *ptr)
{
ptr->THRS_I &= ~RDC_THRS_I_THRS4ACC_MASK;
}
/**
* @brief enable q thrs data for accumulate
*
* @param ptr @ref RDC_Type base
*/
static inline void rdc_enable_q_channel_thrs_data_for_acc(RDC_Type *ptr)
{
ptr->THRS_Q |= RDC_THRS_Q_THRS4ACC_MASK;
}
/**
* @brief disable q thrs data for accumulate
*
* @param ptr @ref RDC_Type base
*/
static inline void rdc_disable_q_channel_thrs_data_for_acc(RDC_Type *ptr)
{
ptr->THRS_Q &= ~RDC_THRS_Q_THRS4ACC_MASK;
}
#endif
/**
* @brief Get the accumulate value
*
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_def.h
+1 -1
View File
@@ -59,7 +59,7 @@ typedef enum {
} xpi_xfer_channel_t;
/**
* @brief XPI Channel defitions
* @brief XPI Channel definitions
*/
typedef enum {
xpi_channel_a1, /**< Port: Channel A1 */
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_romapi_xpi_nor_def.h
+1 -1
View File
@@ -205,7 +205,7 @@ enum {
};
/**
* @brief Device Mode confiuration structure
* @brief Device Mode configuration structure
*/
typedef struct {
uint8_t cfg_cmd_type; /**< Configuration command type */
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_rtc_drv.h
+6 -3
View File
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021-2023 HPMicro
* Copyright (c) 2021-2024 HPMicro
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -17,7 +17,10 @@
#include "hpm_common.h"
#include "hpm_rtc_regs.h"
#ifndef __ICCRISCV__
#include <sys/time.h>
#endif
#include <time.h>
/**
* @brief RTC alarm configuration
@@ -25,7 +28,7 @@
typedef struct {
uint16_t index; /**< RTC alarm index */
uint16_t type; /**< Alarm type */
time_t period; /**< ALarm period */
time_t period; /**< Alarm period */
} rtc_alarm_config_t;
/**
@@ -59,7 +62,7 @@ hpm_stat_t rtc_config_time(RTC_Type *base, time_t time);
* @brief Configure RTC Alarm
* @param [in] base RTC base address
* @param [in] config RTC alarm configuration pointer
* @retval API execution status status_success or status_invalid_arugment;
* @retval API execution status status_success or status_invalid_argument;
*/
hpm_stat_t rtc_config_alarm(RTC_Type *base, rtc_alarm_config_t *config);
bsp/hpmicro/libraries/hpm_sdk/drivers/inc/hpm_sdp_drv.h
+224 -28
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File diff suppressed because it is too large Load Diff

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