Mirrors_Framework/rt-thread
1
0
Fork 0
mirror of https://github.com/RT-Thread/rt-thread.git synced 2026-09-20 17:44:20 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

update Stellaris Peripheral Driver Library to r8264.

Browse Source 
git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1869 bbd45198-f89e-11dd-88c7-29a3b14d5316
This commit is contained in:
wuyangyong
2011-12-23 03:20:26 +00:00
parent 315fffcfcb
commit 646c1443db
203 changed files with 77918 additions and 41464 deletions
Download Patch File Download Diff File Expand all files Collapse all files
bsp/lm3s8962/Libraries/SConscript
+7 -2
View File
@@ -6,9 +6,13 @@ from building import *
cwd = GetCurrentDir()
src = Glob('driverlib/*.c')
# cortex-m3 no FPU.
if rtconfig.PART_TYPE.startswith('PART_LM4F') != True:
SrcRemove(src, 'fpu.c')
# add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += ['startup/gcc/startup_LPC17xx.s']
src += ['startup/gcc/start_gcc.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['startup/arm/start_rvds.S']
elif rtconfig.CROSS_TOOL == 'iar':
@@ -16,6 +20,7 @@ elif rtconfig.CROSS_TOOL == 'iar':
CPPPATH = [cwd]
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
CPPDEFINES = [rtconfig.PART_TYPE]
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/lm3s8962/Libraries/driverlib/adc.c
+168 -88
View File
@@ -2,7 +2,7 @@
//
// adc.c - Driver for the ADC.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -33,6 +33,7 @@
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_sysctl.h"
#include "driverlib/adc.h"
#include "driverlib/debug.h"
#include "driverlib/interrupt.h"
@@ -46,6 +47,7 @@
#define ADC_SEQ (ADC_O_SSMUX0)
#define ADC_SEQ_STEP (ADC_O_SSMUX1 - ADC_O_SSMUX0)
#define ADC_SSMUX (ADC_O_SSMUX0 - ADC_O_SSMUX0)
#define ADC_SSEMUX (ADC_O_SSEMUX0 - ADC_O_SSMUX0)
#define ADC_SSCTL (ADC_O_SSCTL0 - ADC_O_SSMUX0)
#define ADC_SSFIFO (ADC_O_SSFIFO0 - ADC_O_SSMUX0)
#define ADC_SSFSTAT (ADC_O_SSFSTAT0 - ADC_O_SSMUX0)
@@ -70,10 +72,10 @@ static unsigned char g_pucOversampleFactor[3];
//! ADC sample sequence interrupt occurs.
//!
//! This function sets the handler to be called when a sample sequence
//! interrupt occurs. This will enable the global interrupt in the interrupt
//! controller; the sequence interrupt must be enabled with ADCIntEnable(). It
//! is the interrupt handler's responsibility to clear the interrupt source via
//! ADCIntClear().
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; the sequence interrupt must be enabled with
//! ADCIntEnable(). It is the interrupt handler's responsibility to clear the
//! interrupt source via ADCIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@@ -117,9 +119,9 @@ ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum,
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This function unregisters the interrupt handler. This will disable the
//! global interrupt in the interrupt controller; the sequence interrupt must
//! be disabled via ADCIntDisable().
//! This function unregisters the interrupt handler. This function disables
//! the global interrupt in the interrupt controller; the sequence interrupt
//! must be disabled via ADCIntDisable().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@@ -225,9 +227,9 @@ ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the specified sample sequence.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//! This function returns the interrupt status for the specified sample
//! sequence. Either the raw interrupt status or the status of interrupts that
//! are allowed to reflect to the processor can be returned.
//!
//! \return The current raw or masked interrupt status.
//
@@ -257,7 +259,7 @@ ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
ulTemp = HWREG(ulBase + ADC_O_RIS) & (0x10000 | (1 << ulSequenceNum));
//
// If the digital comparator status bit is set, reflect it to the
// If the digital comparator status bit is set, reflect it to the
// appropriate sequence bit.
//
if(ulTemp & 0x10000)
@@ -281,17 +283,17 @@ ADCIntStatus(unsigned long ulBase, unsigned long ulSequenceNum,
//! \param ulSequenceNum is the sample sequence number.
//!
//! The specified sample sequence interrupt is cleared, so that it no longer
//! asserts. This must be done in the interrupt handler to keep it from being
//! called again immediately upon exit.
//! asserts. This function must be called in the interrupt handler to keep
//! the interrupt from being triggered again immediately upon exit.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
@@ -379,10 +381,10 @@ ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
//! respect to the other sample sequences.
//!
//! This function configures the initiation criteria for a sample sequence.
//! Valid sample sequences range from zero to three; sequence zero will capture
//! up to eight samples, sequences one and two will capture up to four samples,
//! and sequence three will capture a single sample. The trigger condition and
//! priority (with respect to other sample sequence execution) is set.
//! Valid sample sequencers range from zero to three; sequencer zero captures
//! up to eight samples, sequencers one and two capture up to four samples,
//! and sequencer three captures a single sample. The trigger condition and
//! priority (with respect to other sample sequencer execution) are set.
//!
//! The \e ulTrigger parameter can take on the following values:
//!
@@ -395,7 +397,9 @@ ADCSequenceDisable(unsigned long ulBase, unsigned long ulSequenceNum)
//! - \b ADC_TRIGGER_COMP2 - A trigger generated by the third analog
//! comparator; configured with ComparatorConfigure().
//! - \b ADC_TRIGGER_EXTERNAL - A trigger generated by an input from the Port
//! B4 pin.
//! B4 pin. Note that some microcontrollers can
//! select from any GPIO using the
//! GPIOADCTriggerEnable() function.
//! - \b ADC_TRIGGER_TIMER - A trigger generated by a timer; configured with
//! TimerControlTrigger().
//! - \b ADC_TRIGGER_PWM0 - A trigger generated by the first PWM generator;
@@ -472,42 +476,40 @@ ADCSequenceConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
//! \param ulSequenceNum is the sample sequence number.
//! \param ulStep is the step to be configured.
//! \param ulConfig is the configuration of this step; must be a logical OR of
//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, and one of the
//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH15). For parts
//! with the digital comparator feature, the follow values may also be OR'd
//! into the \e ulConfig value to enable the digital comparater feature:
//! \b ADC_CTL_CE and one of the comparater selects (\b ADC_CTL_CMP0 through
//! \b ADC_CTL_CMP7).
//! \b ADC_CTL_TS, \b ADC_CTL_IE, \b ADC_CTL_END, \b ADC_CTL_D, one of the
//! input channel selects (\b ADC_CTL_CH0 through \b ADC_CTL_CH23), and one of
//! the digital comparator selects (\b ADC_CTL_CMP0 through \b ADC_CTL_CMP7).
//!
//! This function will set the configuration of the ADC for one step of a
//! sample sequence. The ADC can be configured for single-ended or
//! differential operation (the \b ADC_CTL_D bit selects differential
//! operation when set), the channel to be sampled can be chosen (the
//! \b ADC_CTL_CH0 through \b ADC_CTL_CH15 values), and the internal
//! temperature sensor can be selected (the \b ADC_CTL_TS bit). Additionally,
//! this step can be defined as the last in the sequence (the \b ADC_CTL_END
//! bit) and it can be configured to cause an interrupt when the step is
//! complete (the \b ADC_CTL_IE bit). If the digital comparators are present
//! on the device, this step may also be configured send the ADC sample to
//! the selected comparator (the \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7
//! values) by using the \b ADC_CTL_CE bit. The configuration is used by the
//! ADC at the appropriate time when the trigger for this sequence occurs.
//! This function configures the ADC for one step of a sample sequence. The
//! ADC can be configured for single-ended or differential operation
//! (the \b ADC_CTL_D bit selects differential operation when set), the
//! channel to be sampled can be chosen (the \b ADC_CTL_CH0 through
//! \b ADC_CTL_CH23 values), and the internal temperature sensor can be
//! selected (the \b ADC_CTL_TS bit). Additionally, this step can be defined
//! as the last in the sequence (the \b ADC_CTL_END bit) and it can be
//! configured to cause an interrupt when the step is complete (the
//! \b ADC_CTL_IE bit). If the digital comparators are present on the device,
//! this step may also be configured to send the ADC sample to the selected
//! comparator using \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7. The configuration
//! is used by the ADC at the appropriate time when the trigger for
//! this sequence occurs.
//!
//! \note If the Digitial Comparator is present and enabled using the
//! \b ADC_CTL_CE bit, the ADC sample will NOT be written into the ADC
//! sequence data FIFO.
//! \b ADC_CTL_CMP0 through \b ADC_CTL_CMP7 selects, the ADC sample is NOT
//! written into the ADC sequence data FIFO.
//!
//! The \e ulStep parameter determines the order in which the samples are
//! captured by the ADC when the trigger occurs. It can range from zero to
//! seven for the first sample sequence, from zero to three for the second and
//! third sample sequence, and can only be zero for the fourth sample sequence.
//! seven for the first sample sequencer, from zero to three for the second and
//! third sample sequencer, and can only be zero for the fourth sample
//! sequencer.
//!
//! Differential mode only works with adjacent channel pairs (for example, 0
//! and 1). The channel select must be the number of the channel pair to
//! sample (for example, \b ADC_CTL_CH0 for 0 and 1, or \b ADC_CTL_CH1 for 2
//! and 3) or undefined results will be returned by the ADC. Additionally, if
//! and 3) or undefined results are returned by the ADC. Additionally, if
//! differential mode is selected when the temperature sensor is being sampled,
//! undefined results will be returned by the ADC.
//! undefined results are returned by the ADC.
//!
//! It is the responsibility of the caller to ensure that a valid configuration
//! is specified; this function does not check the validity of the specified
@@ -549,6 +551,13 @@ ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
~(0x0000000f << ulStep)) |
((ulConfig & 0x0f) << ulStep));
//
// Set the upper bits of the analog mux value for this step.
//
HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) &
~(0x0000000f << ulStep)) |
(((ulConfig & 0xf00) >> 8) << ulStep));
//
// Set the control value for this step.
//
@@ -595,9 +604,9 @@ ADCSequenceStepConfigure(unsigned long ulBase, unsigned long ulSequenceNum,
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This determines if a sample sequence overflow has occurred. This will
//! happen if the captured samples are not read from the FIFO before the next
//! trigger occurs.
//! This function determines if a sample sequence overflow has occurred.
//! Overflow happens if the captured samples are not read from the FIFO before
//! the next trigger occurs.
//!
//! \return Returns zero if there was not an overflow, and non-zero if there
//! was.
@@ -625,9 +634,9 @@ ADCSequenceOverflow(unsigned long ulBase, unsigned long ulSequenceNum)
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This will clear an overflow condition on one of the sample sequences. The
//! overflow condition must be cleared in order to detect a subsequent overflow
//! condition (it otherwise causes no harm).
//! This function clears an overflow condition on one of the sample sequences.
//! The overflow condition must be cleared in order to detect a subsequent
//! overflow condition (it otherwise causes no harm).
//!
//! \return None.
//
@@ -654,8 +663,8 @@ ADCSequenceOverflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This determines if a sample sequence underflow has occurred. This will
//! happen if too many samples are read from the FIFO.
//! This function determines if a sample sequence underflow has occurred.
//! Underflow happens if too many samples are read from the FIFO.
//!
//! \return Returns zero if there was not an underflow, and non-zero if there
//! was.
@@ -683,8 +692,8 @@ ADCSequenceUnderflow(unsigned long ulBase, unsigned long ulSequenceNum)
//! \param ulBase is the base address of the ADC module.
//! \param ulSequenceNum is the sample sequence number.
//!
//! This will clear an underflow condition on one of the sample sequences. The
//! underflow condition must be cleared in order to detect a subsequent
//! This function clears an underflow condition on one of the sample sequencers.
//! The underflow condition must be cleared in order to detect a subsequent
//! underflow condition (it otherwise causes no harm).
//!
//! \return None.
@@ -713,12 +722,12 @@ ADCSequenceUnderflowClear(unsigned long ulBase, unsigned long ulSequenceNum)
//! \param ulSequenceNum is the sample sequence number.
//! \param pulBuffer is the address where the data is stored.
//!
//! This function copies data from the specified sample sequence output FIFO to
//! a memory resident buffer. The number of samples available in the hardware
//! FIFO are copied into the buffer, which is assumed to be large enough to
//! hold that many samples. This will only return the samples that are
//! presently available, which may not be the entire sample sequence if it is
//! in the process of being executed.
//! This function copies data from the specified sample sequencer output FIFO
//! to a memory resident buffer. The number of samples available in the
//! hardware FIFO are copied into the buffer, which is assumed to be large
//! enough to hold that many samples. This function only returns the samples
//! that are presently available, which may not be the entire sample sequence
//! if it is in the process of being executed.
//!
//! \return Returns the number of samples copied to the buffer.
//
@@ -794,8 +803,8 @@ ADCProcessorTrigger(unsigned long ulBase, unsigned long ulSequenceNum)
//
// Generate a processor trigger for this sample sequence.
//
HWREG(ulBase + ADC_O_PSSI) = ((ulSequenceNum & 0xffff0000) |
(1 << (ulSequenceNum & 0xf)));
HWREG(ulBase + ADC_O_PSSI) |= ((ulSequenceNum & 0xffff0000) |
(1 << (ulSequenceNum & 0xf)));
}
//*****************************************************************************
@@ -905,6 +914,13 @@ ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
~(0x0000000f << ulStep)) |
((ulConfig & 0x0f) << ulStep));
//
// Set the upper bits of the analog mux value for this step.
//
HWREG(ulBase + ADC_SSEMUX) = ((HWREG(ulBase + ADC_SSEMUX) &
~(0x0000000f << ulStep)) |
(((ulConfig & 0xf00) >> 8) << ulStep));
//
// Set the control value for this step.
//
@@ -936,9 +952,9 @@ ADCSoftwareOversampleStepConfigure(unsigned long ulBase,
//! This function copies data from the specified sample sequence output FIFO to
//! a memory resident buffer with software oversampling applied. The requested
//! number of samples are copied into the data buffer; if there are not enough
//! samples in the hardware FIFO to satisfy this many oversampled data items
//! then incorrect results will be returned. It is the caller's responsibility
//! to read only the samples that are available and wait until enough data is
//! samples in the hardware FIFO to satisfy this many oversampled data items,
//! then incorrect results are returned. It is the caller's responsibility to
//! read only the samples that are available and wait until enough data is
//! available, for example as a result of receiving an interrupt.
//!
//! \return None.
@@ -999,21 +1015,18 @@ ADCSoftwareOversampleDataGet(unsigned long ulBase, unsigned long ulSequenceNum,
//! be used to provide better resolution on the sampled data. Oversampling is
//! accomplished by averaging multiple samples from the same analog input. Six
//! different oversampling rates are supported; 2x, 4x, 8x, 16x, 32x, and 64x.
//! Specifying an oversampling factor of zero will disable hardware
//! Specifying an oversampling factor of zero disables hardware
//! oversampling.
//!
//! Hardware oversampling applies uniformly to all sample sequencers. It does
//! not reduce the depth of the sample sequencers like the software
//! oversampling APIs; each sample written into the sample sequence FIFO is a
//! oversampling APIs; each sample written into the sample sequencer FIFO is a
//! fully oversampled analog input reading.
//!
//! Enabling hardware averaging increases the precision of the ADC at the cost
//! of throughput. For example, enabling 4x oversampling reduces the
//! throughput of a 250 Ksps ADC to 62.5 Ksps.
//!
//! \note Hardware oversampling is available beginning with Rev C0 of the
//! Stellaris microcontroller.
//!
//! \return None.
//
//*****************************************************************************
@@ -1051,7 +1064,7 @@ ADCHardwareOversampleConfigure(unsigned long ulBase, unsigned long ulFactor)
//! \param ulComp is the index of the comparator to configure.
//! \param ulConfig is the configuration of the comparator.
//!
//! This function will configure a comparator. The \e ulConfig parameter is
//! This function configures a comparator. The \e ulConfig parameter is
//! the result of a logical OR operation between the \b ADC_COMP_TRIG_xxx, and
//! \b ADC_COMP_INT_xxx values.
//!
@@ -1178,7 +1191,7 @@ ADCComparatorRegionSet(unsigned long ulBase, unsigned long ulComp,
//! \param bInterrupt is the flag to indicate reset of Interrupt conditions.
//!
//! Because the digital comparator uses current and previous ADC values, this
//! function is provide to allow the comparator to be reset to its initial
//! function allows the comparator to be reset to its initial
//! value to prevent stale data from being used when a sequence is enabled.
//!
//! \return None.
@@ -1272,8 +1285,8 @@ ADCComparatorIntEnable(unsigned long ulBase, unsigned long ulSequenceNum)
//!
//! \param ulBase is the base address of the ADC module.
//!
//! This returns the digitial comparator interrupt status bits. This status
//! is sequence agnostic.
//! This function returns the digitial comparator interrupt status bits. This
//! status is sequence agnostic.
//!
//! \return The current comparator interrupt status.
//
@@ -1326,10 +1339,12 @@ ADCComparatorIntClear(unsigned long ulBase, unsigned long ulStatus)
//! \param ulRef is the reference to use.
//!
//! The ADC reference is set as specified by \e ulRef. It must be one of
//! \b ADC_REF_INT or \b ADC_REF_EXT_3V, for internal or external reference.
//! If \b ADC_REF_INT is chosen, then an internal 3V reference is used and
//! no external reference is needed. If \b ADC_REF_EXT_3V is chosen, then a 3V
//! reference must be supplied to the AVREF pin.
//! \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V for internal or
//! external reference. If \b ADC_REF_INT is chosen, then an internal 3V
//! reference is used and no external reference is needed. If
//! \b ADC_REF_EXT_3V is chosen, then a 3V reference must be supplied to the
//! AVREF pin. If \b ADC_REF_EXT_1V is chosen, then a 1V external referece
//! must be supplied to the AVREF pin.
//!
//! \note The ADC reference can only be selected on parts that have an external
//! reference. Consult the data sheet for your part to determine if there is
@@ -1345,12 +1360,13 @@ ADCReferenceSet(unsigned long ulBase, unsigned long ulRef)
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT((ulRef == ADC_REF_INT) || (ulRef == ADC_REF_EXT_3V));
ASSERT((ulRef == ADC_REF_INT) || (ulRef == ADC_REF_EXT_3V) ||
(ulRef == ADC_REF_EXT_1V));
//
// Set the reference.
//
HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF) |
HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_VREF_M) |
ulRef;
}
@@ -1360,8 +1376,8 @@ ADCReferenceSet(unsigned long ulBase, unsigned long ulRef)
//!
//! \param ulBase is the base address of the ADC module.
//!
//! Returns the value of the ADC reference setting. The returned value will be
//! one of \b ADC_REF_INT or \b ADC_REF_EXT_3V.
//! Returns the value of the ADC reference setting. The returned value is one
//! of \b ADC_REF_INT, \b ADC_REF_EXT_3V, or \b ADC_REF_EXT_1V.
//!
//! \note The value returned by this function is only meaningful if used on a
//! part that is capable of using an external reference. Consult the data
@@ -1381,7 +1397,71 @@ ADCReferenceGet(unsigned long ulBase)
//
// Return the value of the reference.
//
return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF);
return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_VREF_M);
}
//*****************************************************************************
//
//! Selects the ADC resolution.
//!
//! \param ulBase is the base address of the ADC module.
//! \param ulResolution is the ADC bit resolution.
//!
//! The ADC resolution is set as specified by \e ulResolution. It must be one
//! of \b ADC_RES_12BIT or \b ADC_RES_10BIT.
//!
//! \note The ADC resolution can only be set on parts that are capable of
//! changing ADC resolution mode. Consult the data sheet for your part to
//! determine if it is capable of operating in more than one resolution mode.
//!
//! \return None.
//
//*****************************************************************************
void
ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
ASSERT((ulResolution == ADC_RES_10BIT) || (ulResolution == ADC_RES_12BIT));
//
// Set the resolution.
//
HWREG(ulBase + ADC_O_CTL) = (HWREG(ulBase + ADC_O_CTL) & ~ADC_CTL_RES) |
ulResolution;
}
//*****************************************************************************
//
//! Gets the setting of ADC resolution.
//!
//! \param ulBase is the base address of the ADC module.
//!
//! The ADC resolution is returned as one of \b ADC_RES_12BIT or
//! \b ADC_RES_10BIT.
//!
//! \note The value returned by this function is only meaningful if used on a
//! part that is capable of changing ADC resolution mode. Consult the
//! data sheet for your part to determine if it is capable of operating in
//! more than one resolution mode.
//!
//! \return The current setting of the ADC resolution.
//
//*****************************************************************************
unsigned long
ADCResolutionGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT((ulBase == ADC0_BASE) || (ulBase == ADC1_BASE));
//
// Get the resolution and return it to the caller.
//
return(HWREG(ulBase + ADC_O_CTL) & ADC_CTL_RES);
}
//*****************************************************************************
bsp/lm3s8962/Libraries/driverlib/adc.h
+21 -2
View File
@@ -2,7 +2,7 @@
//
// adc.h - ADC headers for using the ADC driver functions.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -80,6 +80,14 @@ extern "C"
#define ADC_CTL_CH13 0x0000000D // Input channel 13
#define ADC_CTL_CH14 0x0000000E // Input channel 14
#define ADC_CTL_CH15 0x0000000F // Input channel 15
#define ADC_CTL_CH16 0x00000100 // Input channel 16
#define ADC_CTL_CH17 0x00000101 // Input channel 17
#define ADC_CTL_CH18 0x00000102 // Input channel 18
#define ADC_CTL_CH19 0x00000103 // Input channel 19
#define ADC_CTL_CH20 0x00000104 // Input channel 20
#define ADC_CTL_CH21 0x00000105 // Input channel 21
#define ADC_CTL_CH22 0x00000106 // Input channel 22
#define ADC_CTL_CH23 0x00000107 // Input channel 23
#define ADC_CTL_CMP0 0x00080000 // Select Comparator 0
#define ADC_CTL_CMP1 0x00090000 // Select Comparator 1
#define ADC_CTL_CMP2 0x000A0000 // Select Comparator 2
@@ -173,6 +181,15 @@ extern "C"
//*****************************************************************************
#define ADC_REF_INT 0x00000000 // Internal reference
#define ADC_REF_EXT_3V 0x00000001 // External 3V reference
#define ADC_REF_EXT_1V 0x00000003 // External 1V reference
//*****************************************************************************
//
// Values that can be passed to ADCResolutionSet as the ulResolution parameter.
//
//*****************************************************************************
#define ADC_RES_10BIT 0x00000000 // 10-bit resolution
#define ADC_RES_12BIT 0x00000010 // 12-bit resolution
//*****************************************************************************
//
@@ -243,6 +260,8 @@ extern void ADCComparatorIntClear(unsigned long ulBase,
unsigned long ulStatus);
extern void ADCReferenceSet(unsigned long ulBase, unsigned long ulRef);
extern unsigned long ADCReferenceGet(unsigned long ulBase);
extern void ADCResolutionSet(unsigned long ulBase, unsigned long ulResolution);
extern unsigned long ADCResolutionGet(unsigned long ulBase);
extern void ADCPhaseDelaySet(unsigned long ulBase, unsigned long ulPhase);
extern unsigned long ADCPhaseDelayGet(unsigned long ulBase);
bsp/lm3s8962/Libraries/driverlib/can.c
+154 -154
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/can.h
+6 -6
View File
@@ -2,7 +2,7 @@
//
// can.h - Defines and Macros for the CAN controller.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -179,25 +179,25 @@ typedef struct
//! Buffer 1 segments, measured in time quanta. The valid values for this
//! setting range from 2 to 16.
//
unsigned int uSyncPropPhase1Seg;
unsigned long ulSyncPropPhase1Seg;
//
//! This value holds the Phase Buffer 2 segment in time quanta. The valid
//! values for this setting range from 1 to 8.
//
unsigned int uPhase2Seg;
unsigned long ulPhase2Seg;
//
//! This value holds the Resynchronization Jump Width in time quanta. The
//! valid values for this setting range from 1 to 4.
//
unsigned int uSJW;
unsigned long ulSJW;
//
//! This value holds the CAN_CLK divider used to determine time quanta.
//! The valid values for this setting range from 1 to 1023.
//
unsigned int uQuantumPrescaler;
unsigned long ulQuantumPrescaler;
}
tCANBitClkParms;
bsp/lm3s8962/Libraries/driverlib/comp.c
+22 -22
View File
@@ -2,7 +2,7 @@
//
// comp.c - Driver for the analog comparator.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -45,8 +45,8 @@
//! \param ulComp is the index of the comparator to configure.
//! \param ulConfig is the configuration of the comparator.
//!
//! This function will configure a comparator. The \e ulConfig parameter is
//! the result of a logical OR operation between the \b COMP_TRIG_xxx,
//! This function configures a comparator. The \e ulConfig parameter is the
//! result of a logical OR operation between the \b COMP_TRIG_xxx,
//! \b COMP_INT_xxx, \b COMP_ASRCP_xxx, and \b COMP_OUTPUT_xxx values.
//!
//! The \b COMP_TRIG_xxx term can take on the following values:
@@ -117,8 +117,8 @@ ComparatorConfigure(unsigned long ulBase, unsigned long ulComp,
//! \param ulBase is the base address of the comparator module.
//! \param ulRef is the desired reference voltage.
//!
//! This function will set the internal reference voltage value. The voltage
//! is specified as one of the following values:
//! This function sets the internal reference voltage value. The voltage is
//! specified as one of the following values:
//!
//! - \b COMP_REF_OFF to turn off the reference voltage
//! - \b COMP_REF_0V to set the reference voltage to 0 V
@@ -212,9 +212,9 @@ ComparatorValueGet(unsigned long ulBase, unsigned long ulComp)
//! \param pfnHandler is a pointer to the function to be called when the
//! comparator interrupt occurs.
//!
//! This sets the handler to be called when the comparator interrupt occurs.
//! This will enable the interrupt in the interrupt controller; it is the
//! interrupt-handler's responsibility to clear the interrupt source via
//! This function sets the handler to be called when the comparator interrupt occurs
//! and enables the interrupt in the interrupt controller. It is the interrupt
//! handler's responsibility to clear the interrupt source via
//! ComparatorIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
@@ -256,9 +256,9 @@ ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp,
//! \param ulBase is the base address of the comparator module.
//! \param ulComp is the index of the comparator.
//!
//! This function will clear the handler to be called when a comparator
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//! This function clears the handler to be called when a comparator interrupt
//! occurs. This function also masks off the interrupt in the interrupt controller
//! so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@@ -299,7 +299,7 @@ ComparatorIntUnregister(unsigned long ulBase, unsigned long ulComp)
//! \param ulComp is the index of the comparator.
//!
//! This function enables generation of an interrupt from the specified
//! comparator. Only comparators whose interrupts are enabled can be reflected
//! comparator. Only enabled comparator interrupts can be reflected
//! to the processor.
//!
//! \return None.
@@ -328,7 +328,7 @@ ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp)
//! \param ulComp is the index of the comparator.
//!
//! This function disables generation of an interrupt from the specified
//! comparator. Only comparators whose interrupts are enabled can be reflected
//! comparator. Only enabled comparator interrupts can be reflected
//! to the processor.
//!
//! \return None.
@@ -358,7 +358,7 @@ ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp)
//! \param bMasked is \b false if the raw interrupt status is required and
//! \b true if the masked interrupt status is required.
//!
//! This returns the interrupt status for the comparator. Either the raw or
//! This function returns the interrupt status for the comparator. Either the raw or
//! the masked interrupt status can be returned.
//!
//! \return \b true if the interrupt is asserted and \b false if it is not
@@ -397,18 +397,18 @@ ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp,
//! \param ulComp is the index of the comparator.
//!
//! The comparator interrupt is cleared, so that it no longer asserts. This
//! must be done in the interrupt handler to keep it from being called again
//! immediately upon exit. Note that for a level triggered interrupt, the
//! interrupt cannot be cleared until it stops asserting.
//! fucntion must be called in the interrupt handler to keep the handler from
//! being called again immediately upon exit. Note that for a level-triggered
//! interrupt, the interrupt cannot be cleared until it stops asserting.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
bsp/lm3s8962/Libraries/driverlib/comp.h
+2 -2
View File
@@ -2,7 +2,7 @@
//
// comp.h - Prototypes for the analog comparator driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
bsp/lm3s8962/Libraries/driverlib/cpu.c
+3 -4
View File
@@ -3,7 +3,7 @@
// cpu.c - Instruction wrappers for special CPU instructions needed by the
// drivers.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -19,7 +19,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -360,8 +360,7 @@ CPUbasepriSet(unsigned long ulNewBasepri)
//
// Set the BASEPRI register
//
__asm(" msr BASEPRI, r0\n"
" bx lr\n");
__asm(" msr BASEPRI, r0\n");
}
#endif
bsp/lm3s8962/Libraries/driverlib/cpu.h
+2 -2
View File
@@ -2,7 +2,7 @@
//
// cpu.h - Prototypes for the CPU instruction wrapper functions.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
bsp/lm3s8962/Libraries/driverlib/debug.h
+2 -2
View File
@@ -2,7 +2,7 @@
//
// debug.h - Macros for assisting debug of the driver library.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
bsp/lm3s8962/Libraries/driverlib/eeprom.c
+1110
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/eeprom.h
+264
View File
@@ -0,0 +1,264 @@
//*****************************************************************************
//
// eeprom.h - Prototypes for the EEPROM driver.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __EEPROM_H__
#define __EEPROM_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup eeprom_api
//! @{
//
//*****************************************************************************
//*****************************************************************************
//
// Values returned by EEPROMInit.
//
//*****************************************************************************
//
//! This value may be returned from a call to EEPROMInit(). It indicates that
//! no previous write operations were interrupted by a reset event and that the
//! EEPROM peripheral is ready for use.
//
#define EEPROM_INIT_OK 0
//
//! This value may be returned from a call to EEPROMInit(). It indicates that
//! a previous data or protection write operation was interrupted by a reset
//! event. The EEPROM peripheral has recovered its state but the last write
//! operation may have been lost. The application must check the validity of
//! data it has written and retry any writes as required.
//
#define EEPROM_INIT_RETRY 1
//
//! This value may be returned from a call to EEPROMInit(). It indicates that a
//! previous data or protection write operation was interrupted by a reset
//! event and that the EEPROM peripheral was unable to clean up after the
//! problem. This situation may be resolved with another reset or may be fatal
//! depending upon the cause of the problem. For example, if the voltage to
//! the part is unstable, retrying once the voltage has stabilized may clear
//! the error.
//
#define EEPROM_INIT_ERROR 2
//*****************************************************************************
//
// Error indicators returned by various EEPROM API calls. These will be ORed
// together into the final return code.
//
//*****************************************************************************
//
//! This return code bit indicates that the EEPROM programming state machine
//! failed to write a value due to the voltage level dropping below that
//! required for EEPROM programming. The operation may be retried once the
//! voltage stabilizes.
//
#define EEPROM_RC_INVPL 0x00000100
//
//! This return code bit indicates that an attempt was made to read from
//! the EEPROM while a write operation was in progress.
//
#define EEPROM_RC_WRBUSY 0x00000020
//
//! This return code bit indicates that an attempt was made to write a
//! value but the destination permissions disallow write operations. This
//! may be due to the destination block being locked, access protection set
//! to prohibit writes or an attempt to write a password when one is already
//! written.
//
#define EEPROM_RC_NOPERM 0x00000010
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently copying to or from the internal copy buffer to make room for
//! a newly written value. It is provided as a status indicator and does not
//! indicate an error.
//
#define EEPROM_RC_WKCOPY 0x00000008
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently erasing the internal copy buffer. It is provided as a
//! status indicator and does not indicate an error.
//
#define EEPROM_RC_WKERASE 0x00000004
//
//! This return code bit indicates that the EEPROM programming state machine
//! is currently working. No new write operations should be attempted until
//! this bit is clear.
//
#define EEPROM_RC_WORKING 0x00000001
//*****************************************************************************
//
// Values that can be passed to EEPROMBlockProtectSet() in the ulProtect
// parameter, and returned by EEPROMBlockProtectGet().
//
//*****************************************************************************
//
//! This bit may be ORed with the protection option passed to
//! EEPROMBlockProtectSet() or returned from EEPROMBlockProtectGet(). It
//! restricts EEPROM access to threads running in supervisor mode and prevents
//! access to an EEPROM block when the CPU is in user mode.
//
#define EEPROM_PROT_SUPERVISOR_ONLY 0x00000008
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer
//! read/write access when no password is set or when a password is set and
//! the block is unlocked, and read-only access when a password is set but
//! the block is locked.
//
#define EEPROM_PROT_RW_LRO_URW 0x00000000
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer neither
//! read nor write access unless it is protected by a password and unlocked.
//
#define EEPROM_PROT_NA_LNA_URW 0x00000001
//
//! This value may be passed to EEPROMBlockProtectSet() or returned from
//! EEPROMBlockProtectGet(). It indicates that the block should offer
//! read-only access when no password is set or when a password is set and the
//! block is unlocked. When a password is set and the block is locked, neither
//! read nor write access is permitted.
//
#define EEPROM_PROT_RO_LNA_URO 0x00000002
//*****************************************************************************
//
//! This value may be passed to EEPROMIntEnable() and EEPROMIntDisable() and is
//! returned by EEPROMIntStatus() if an EEPROM interrupt is currently being
//! signaled.
//
//*****************************************************************************
#define EEPROM_INT_PROGRAM 0x00000004
//*****************************************************************************
//
//! Returns the EEPROM block number containing a given offset address.
//!
//! \param ulAddr is the linear, byte address of the EEPROM location whose
//! block number is to be returned. This is a zero-based offset from the start
//! of the EEPROM storage.
//!
//! This macro may be used to translate an EEPROM address offset into a
//! block number suitable for use in any of the driver's block protection
//! functions. The address provided is expressed as a byte offset from the
//! base of the EEPROM.
//!
//! \return Returns the zero-based block number which contains the passed
//! address.
//
//*****************************************************************************
#define EEPROMBlockFromAddr(ulAddr) ((ulAddr) >> 6)
//*****************************************************************************
//
//! Returns the offset address of the first word in an EEPROM block.
//!
//! \param ulBlock is the index of the EEPROM block whose first word address
//! is to be returned.
//!
//! This macro may be used to determine the address of the first word in a
//! given EEPROM block. The address returned is expressed as a byte offset
//! from the base of EEPROM storage.
//!
//! \return Returns the address of the first word in the given EEPROM block.
//
//*****************************************************************************
#define EEPROMAddrFromBlock(ulBlock) ((ulBlock) << 6)
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern unsigned long EEPROMInit(void);
extern unsigned long EEPROMSizeGet(void);
extern unsigned long EEPROMBlockCountGet(void);
extern void EEPROMRead(unsigned long *pulData, unsigned long ulAddress,
unsigned long ulCount);
extern unsigned long EEPROMProgram(unsigned long *pulData,
unsigned long ulAddress,
unsigned long ulCount);
extern unsigned long EEPROMProgramNonBlocking(unsigned long ulData,
unsigned long ulAddress);
extern unsigned long EEPROMStatusGet(void);
extern unsigned long EEPROMMassErase(void);
extern unsigned long EEPROMBlockProtectGet(unsigned long ulBlock);
extern unsigned long EEPROMBlockProtectSet(unsigned long ulBlock,
unsigned long ulProtect);
extern unsigned long EEPROMBlockPasswordSet(unsigned long ulBlock,
unsigned long *pulPassword,
unsigned long ulCount);
extern unsigned long EEPROMBlockLock(unsigned long ulBlock);
extern unsigned long EEPROMBlockUnlock(unsigned long ulBlock,
unsigned long *pulPassword,
unsigned long ulCount);
extern void EEPROMBlockHide(unsigned long ulBlock);
extern void EEPROMIntEnable(unsigned long ulIntFlags);
extern void EEPROMIntDisable(unsigned long ulIntFlags);
extern unsigned long EEPROMIntStatus(tBoolean bMasked);
extern void EEPROMIntClear(unsigned long ulIntFlags);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __EEPROM_H__
bsp/lm3s8962/Libraries/driverlib/epi.c
+135 -43
View File
@@ -2,7 +2,7 @@
//
// epi.c - Driver for the EPI module.
//
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -50,9 +50,10 @@
//! - \b EPI_MODE_GENERAL - use for general-purpose mode operation
//! - \b EPI_MODE_SDRAM - use with SDRAM device
//! - \b EPI_MODE_HB8 - use with host-bus 8-bit interface
//! - \b EPI_MODE_HB16 - use with host-bus 16-bit interface
//! - \b EPI_MODE_DISABLE - disable the EPI module
//!
//! Selection of any of the above modes will enable the EPI module, except
//! Selection of any of the above modes enables the EPI module, except
//! for \b EPI_MODE_DISABLE which should be used to disable the module.
//!
//! \return None.
@@ -68,6 +69,7 @@ EPIModeSet(unsigned long ulBase, unsigned long ulMode)
ASSERT((ulMode == EPI_MODE_GENERAL) ||
(ulMode == EPI_MODE_SDRAM) ||
(ulMode == EPI_MODE_HB8) ||
(ulMode == EPI_MODE_HB16) ||
(ulMode == EPI_MODE_DISABLE));
//
@@ -84,15 +86,15 @@ EPIModeSet(unsigned long ulBase, unsigned long ulMode)
//! \param ulDivider is the value of the clock divider to be applied to
//! the external interface (0-65535).
//!
//! This functions sets the clock divider(s) that will be used to determine the
//! This function sets the clock divider(s) that is used to determine the
//! clock rate of the external interface. The \e ulDivider value is used to
//! derive the EPI clock rate from the system clock based upon the following
//! derive the EPI clock rate from the system clock based on the following
//! formula.
//!
//! EPIClock = (Divider == 0) ? SysClk : (SysClk / (((Divider / 2) + 1) * 2))
//!
//! For example, a divider value of 1 results in an EPI clock rate of half
//! the system clock, value of 2 or 3 yield one quarter of the system clock and
//! the system clock, value of 2 or 3 yields one quarter of the system clock and
//! a value of 4 results in one sixth of the system clock rate.
//!
//! In cases where a dual chip select mode is in use and different clock rates
@@ -213,16 +215,15 @@ EPIConfigSDRAMSet(unsigned long ulBase, unsigned long ulConfig,
//! rate resulting from the divider in the lower 16 bits of the parameter passed
//! to EPIDividerSet().
//! - one of \b EPI_HB8_CSCFG_CS, \b EPI_HB8_CSCFG_ALE,
//! \b EPI_HB8_CSCFG_DUAL_CS or \b EPI_HB8_CSCFG_ALE_DUAL. \b EPI_HB8_CSCFG_CS
//! sets EPI30 to operate as a Chip Select (CSn) signal. When using this mode,
//! \b EPI_HB8_MODE_ADMUX must not be specified. \b EPI_HB8_CSCFG_ALE sets
//! EPI30 to operate as an address latch (ALE). \b EPI_HB8_CSCFG_DUAL_CS sets
//! EPI30 to operate as CS0n and EPI27 as CS1n with the asserted chip select
//! determined from the most significant address bit for the respective external
//! address map. \b EPI_HB8_CSCFG_DUAL_ALE sets EPI30 as an address latch (ALE),
//! EPI27 as CS0n and EPI26 as CS1n with the asserted chip select determined
//! from the most significant address bit for the respective external address
//! map.
//! \b EPI_HB8_CSCFG_DUAL_CS or \b EPI_HB8_CSCFG_ALE_DUAL_CS.
//! \b EPI_HB8_CSCFG_CS sets EPI30 to operate as a Chip Select (CSn) signal.
//! \b EPI_HB8_CSCFG_ALE sets EPI30 to operate as an address latch (ALE).
//! \b EPI_HB8_CSCFG_DUAL_CS sets EPI30 to operate as CS0n and EPI27 as CS1n
//! with the asserted chip select determined from the most significant address
//! bit for the respective external address map. \b EPI_HB8_CSCFG_ALE_DUAL_CS
//! sets EPI30 as an address latch (ALE), EPI27 as CS0n and EPI26 as CS1n with
//! the asserted chip select determined from the most significant address bit
//! for the respective external address map.
//!
//! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a
//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this
@@ -248,7 +249,9 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
//
HWREG(ulBase + EPI_O_HB8CFG2) = (((ulConfig & EPI_HB8_WORD_ACCESS) ?
EPI_HB8CFG2_WORD : 0) |
((ulConfig & EPI_HB8_CSBAUD_DUAL) ? EPI_HB8CFG2_CSBAUD : 0) | ((ulConfig & EPI_HB8_CSCFG_MASK) << 15));
((ulConfig & EPI_HB8_CSBAUD_DUAL) ?
EPI_HB8CFG2_CSBAUD : 0) |
((ulConfig & EPI_HB8_CSCFG_MASK) << 15));
//
// Fill in the max wait field of the configuration word.
//
@@ -261,6 +264,96 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
HWREG(ulBase + EPI_O_HB8CFG) = ulConfig;
}
//*****************************************************************************
//
//! Configures the interface for Host-bus 16 operation.
//!
//! \param ulBase is the EPI module base address.
//! \param ulConfig is the interface configuration.
//! \param ulMaxWait is the maximum number of external clocks to wait
//! if a FIFO ready signal is holding off the transaction.
//!
//! This function is used to configure the interface when used in Host-bus 16
//! operation as chosen with the function EPIModeSet(). The parameter
//! \e ulConfig is the logical OR of any of the following:
//!
//! - one of \b EPI_HB16_MODE_ADMUX, \b EPI_HB16_MODE_ADDEMUX,
//! \b EPI_HB16_MODE_SRAM, or \b EPI_HB16_MODE_FIFO to select the HB16 mode
//! - \b EPI_HB16_USE_TXEMPTY - enable TXEMPTY signal with FIFO
//! - \b EPI_HB16_USE_RXFULL - enable RXFULL signal with FIFO
//! - \b EPI_HB16_WRHIGH - use active high write strobe, otherwise it is
//! active low
//! - \b EPI_HB16_RDHIGH - use active high read strobe, otherwise it is
//! active low
//! - one of \b EPI_HB16_WRWAIT_0, \b EPI_HB16_WRWAIT_1, \b EPI_HB16_WRWAIT_2,
//! or \b EPI_HB16_WRWAIT_3 to select the number of write wait states (default
//! is 0 wait states)
//! - one of \b EPI_HB16_RDWAIT_0, \b EPI_HB16_RDWAIT_1, \b EPI_HB16_RDWAIT_2,
//! or \b EPI_HB16_RDWAIT_3 to select the number of read wait states (default
//! is 0 wait states)
//! - \b EPI_HB16_WORD_ACCESS - use Word Access mode to route bytes to the
//! correct byte lanes allowing data to be stored in bits [31:16]. If absent,
//! all data transfers use bits [15:0].
//! - \b EPI_HB16_BSEL - enables byte selects. In this mode, two EPI signals
//! operate as byte selects allowing 8-bit transfers. If this flag is not
//! specified, data must be read and written using only 16-bit transfers.
//! - \b EPI_HB16_CSBAUD_DUAL - use different baud rates when accessing devices
//! on each CSn. CS0n uses the baud rate specified by the lower 16 bits of the
//! divider passed to EPIDividerSet() and CS1n uses the divider passed in the
//! upper 16 bits. If this option is absent, both chip selects use the baud
//! rate resulting from the divider in the lower 16 bits of the parameter passed
//! to EPIDividerSet().
//! - one of \b EPI_HB16_CSCFG_CS, \b EPI_HB16_CSCFG_ALE,
//! \b EPI_HB16_CSCFG_DUAL_CS or \b EPI_HB16_CSCFG_ALE_DUAL_CS.
//! \b EPI_HB16_CSCFG_CS sets EPI30 to operate as a Chip Select (CSn) signal.
//! \b EPI_HB16_CSCFG_ALE sets EPI30 to operate as an address latch (ALE).
//! \b EPI_HB16_CSCFG_DUAL_CS sets EPI30 to operate as CS0n and EPI27 as CS1n
//! with the asserted chip select determined from the most significant address
//! bit for the respective external address map. \b EPI_HB16_CSCFG_ALE_DUAL_CS
//! sets EPI30 as an address latch (ALE), EPI27 as CS0n and EPI26 as CS1n with
//! the asserted chip select determined from the most significant address bit
//! for the respective external address map.
//!
//! The parameter \e ulMaxWait is used if the FIFO mode is chosen. If a
//! FIFO is used along with RXFULL or TXEMPTY ready signals, then this
//! parameter determines the maximum number of clocks to wait when the
//! transaction is being held off by by the FIFO using one of these ready
//! signals. A value of 0 means to wait forever.
//!
//! \return None.
//
//*****************************************************************************
void
EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxWait)
{
//
// Check the arguments.
//
ASSERT(ulBase == EPI0_BASE);
ASSERT(ulMaxWait < 256);
//
// Determine the CS and word access modes.
//
HWREG(ulBase + EPI_O_HB16CFG2) = (((ulConfig & EPI_HB16_WORD_ACCESS) ?
EPI_HB16CFG2_WORD : 0) |
((ulConfig & EPI_HB16_CSBAUD_DUAL) ?
EPI_HB16CFG2_CSBAUD : 0) |
((ulConfig & EPI_HB16_CSCFG_MASK) << 15));
//
// Fill in the max wait field of the configuration word.
//
ulConfig &= ~EPI_HB16CFG_MAXWAIT_M;
ulConfig |= ulMaxWait << EPI_HB16CFG_MAXWAIT_S;
//
// Write the main HostBus16 configuration register.
//
HWREG(ulBase + EPI_O_HB16CFG) = ulConfig;
}
//*****************************************************************************
//
//! Configures the interface for general-purpose mode operation.
@@ -274,9 +367,8 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
//!
//! This function is used to configure the interface when used in
//! general-purpose operation as chosen with the function EPIModeSet(). The
//! parameter
//! \e ulConfig is the logical OR of any of the following:
//!
//! parameter \e ulConfig is the logical OR of any of the following:
//!
//! - \b EPI_GPMODE_CLKPIN - interface clock is output on a pin
//! - \b EPI_GPMODE_CLKGATE - clock is stopped when there is no transaction,
//! otherwise it is free-running
@@ -288,13 +380,13 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
//! - \b EPI_GPMODE_FRAME50 - framing signal is 50/50 duty cycle, otherwise it
//! is a pulse
//! - \b EPI_GPMODE_READWRITE - read and write strobes are emitted on pins
//! - \b EPI_GPMODE_WRITE2CYCLE - a two cycle write is used, otherwise a
//! - \b EPI_GPMODE_WRITE2CYCLE - a two-cycle write is used, otherwise a
//! single-cycle write is used
//! - \b EPI_GPMODE_READ2CYCLE - a two cycle read is used, otherwise a
//! - \b EPI_GPMODE_READ2CYCLE - a two-cycle read is used, otherwise a
//! single-cycle read is used
//! - \b EPI_GPMODE_ASIZE_NONE, \b EPI_GPMODE_ASIZE_4,
//! \b EPI_GPMODE_ASIZE_12, or \b EPI_GPMODE_ASIZE_20 to choose no address
//! bus, or and address bus size of 4, 12, or 20 bits
//! bus or an address bus size of 4, 12, or 20 bits
//! - \b EPI_GPMODE_DSIZE_8, \b EPI_GPMODE_DSIZE_16,
//! \b EPI_GPMODE_DSIZE_24, or \b EPI_GPMODE_DSIZE_32 to select a data bus
//! size of 8, 16, 24, or 32 bits
@@ -313,7 +405,7 @@ EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
//! external clock enable is used, this parameter determines the maximum
//! number of clocks to wait when the external clock enable signal is holding
//! off a transaction. A value of 0 means to wait forever. If a non-zero
//! value is used and exceeded, an interrupt will occur and the transaction
//! value is used and exceeded, an interrupt occurs and the transaction
//! aborted.
//!
//! \return None.
@@ -422,7 +514,7 @@ EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap)
//! Once configured, the non-blocking read is started by calling
//! EPINonBlockingReadStart(). If the addresses to be read from the device
//! are in a sequence, it is not necessary to call this function multiple
//! times. Until it is changed, the EPI module will remember the last address
//! times. Until it is changed, the EPI module stores the last address
//! that was used for a non-blocking read (per channel).
//!
//! \return None.
@@ -468,9 +560,9 @@ EPINonBlockingReadConfigure(unsigned long ulBase, unsigned long ulChannel,
//!
//! This function starts a non-blocking read that was previously configured
//! with the function EPINonBlockingReadConfigure(). Once this function is
//! called, the EPI module will begin reading data from the external device
//! into the read FIFO. The EPI will stop reading when the FIFO fills up
//! and resume reading when the application drains the FIFO, until the
//! called, the EPI module begins reading data from the external device
//! into the read FIFO. The EPI stops reading when the FIFO fills up
//! and resumes reading when the application drains the FIFO, until the
//! total specified count of data items has been read.
//!
//! Once a read transaction is completed and the FIFO drained, another
@@ -534,7 +626,7 @@ EPINonBlockingReadStop(unsigned long ulBase, unsigned long ulChannel)
ulOffset = ulChannel * (EPI_O_RPSTD1 - EPI_O_RPSTD0);
//
// Write a 0 to the read count register, which will cancel the transaction.
// Write a 0 to the read count register, which cancels the transaction.
//
HWREG(ulBase + EPI_O_RPSTD0 + ulOffset) = 0;
}
@@ -612,10 +704,10 @@ EPINonBlockingReadAvail(unsigned long ulBase)
//! be stored.
//!
//! This function reads 32-bit data items from the read FIFO and stores
//! the values in a caller supplied buffer. The function will read and store
//! the values in a caller-supplied buffer. The function reads and stores
//! data from the FIFO until there is no more data in the FIFO or the maximum
//! count is reached as specified in the parameter \e ulCount. The actual
//! count of items will be returned.
//! count of items is returned.
//!
//! \return The number of items read from the FIFO.
//
@@ -634,8 +726,8 @@ EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount,
ASSERT(pulBuf);
//
// Read from the FIFO while there are any items to read, and
// the callers specified count is not exceeded.
// Read from the FIFO while there are any items to read and
// the caller's specified count is not exceeded.
//
while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
{
@@ -663,14 +755,14 @@ EPINonBlockingReadGet32(unsigned long ulBase, unsigned long ulCount,
//!
//! \param ulBase is the EPI module base address.
//! \param ulCount is the maximum count of items to read.
//! \param pusBuf is the caller supplied buffer where the read data should
//! \param pusBuf is the caller-supplied buffer where the read data should
//! be stored.
//!
//! This function reads 16-bit data items from the read FIFO and stores
//! the values in a caller supplied buffer. The function will read and store
//! the values in a caller-supplied buffer. The function reads and stores
//! data from the FIFO until there is no more data in the FIFO or the maximum
//! count is reached as specified in the parameter \e ulCount. The actual
//! count of items will be returned.
//! count of items is returned.
//!
//! \return The number of items read from the FIFO.
//
@@ -690,12 +782,12 @@ EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount,
//
// Read from the FIFO while there are any items to read, and
// the callers specified count is not exceeded.
// the caller's specified count is not exceeded.
//
while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
{
//
// Read from the FIFO and store in the caller supplied buffer.
// Read from the FIFO and store in the caller-supplied buffer.
//
*pusBuf = (unsigned short)HWREG(ulBase + EPI_O_READFIFO);
@@ -718,14 +810,14 @@ EPINonBlockingReadGet16(unsigned long ulBase, unsigned long ulCount,
//!
//! \param ulBase is the EPI module base address.
//! \param ulCount is the maximum count of items to read.
//! \param pucBuf is the caller supplied buffer where the read data should
//! \param pucBuf is the caller-supplied buffer where the read data should
//! be stored.
//!
//! This function reads 8-bit data items from the read FIFO and stores
//! the values in a caller supplied buffer. The function will read and store
//! the values in a caller-supplied buffer. The function reads and stores
//! data from the FIFO until there is no more data in the FIFO or the maximum
//! count is reached as specified in the parameter \e ulCount. The actual
//! count of items will be returned.
//! count of items is returned.
//!
//! \return The number of items read from the FIFO.
//
@@ -745,7 +837,7 @@ EPINonBlockingReadGet8(unsigned long ulBase, unsigned long ulCount,
//
// Read from the FIFO while there are any items to read, and
// the callers specified count is not exceeded.
// the caller's specified count is not exceeded.
//
while(HWREG(ulBase + EPI_O_RFIFOCNT) && ulCount--)
{
@@ -1047,7 +1139,7 @@ EPIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//!
//! \param ulBase is the EPI module base address.
//!
//! This function will disable and clear the handler to be called when the
//! This function disables and clears the handler to be called when the
//! EPI interrupt occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
bsp/lm3s8962/Libraries/driverlib/epi.h
+36 -2
View File
@@ -2,7 +2,7 @@
//
// epi.h - Prototypes and macros for the EPI module.
//
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -44,6 +44,7 @@ extern "C"
#define EPI_MODE_GENERAL 0x00000010
#define EPI_MODE_SDRAM 0x00000011
#define EPI_MODE_HB8 0x00000012
#define EPI_MODE_HB16 0x00000013
#define EPI_MODE_DISABLE 0x00000000
//*****************************************************************************
@@ -115,6 +116,37 @@ extern "C"
#define EPI_HB8_CSCFG_MASK 0x00000600
//*****************************************************************************
//
// Values that can be passed to EPIConfigHB16ModeSet()
//
//*****************************************************************************
#define EPI_HB16_USE_TXEMPTY 0x00800000
#define EPI_HB16_USE_RXFULL 0x00400000
#define EPI_HB16_WRHIGH 0x00200000
#define EPI_HB16_RDHIGH 0x00100000
#define EPI_HB16_WRWAIT_0 0x00000000
#define EPI_HB16_WRWAIT_1 0x00000040
#define EPI_HB16_WRWAIT_2 0x00000080
#define EPI_HB16_WRWAIT_3 0x000000C0
#define EPI_HB16_RDWAIT_0 0x00000000
#define EPI_HB16_RDWAIT_1 0x00000010
#define EPI_HB16_RDWAIT_2 0x00000020
#define EPI_HB16_RDWAIT_3 0x00000030
#define EPI_HB16_MODE_ADMUX 0x00000000
#define EPI_HB16_MODE_ADDEMUX 0x00000001
#define EPI_HB16_MODE_SRAM 0x00000002
#define EPI_HB16_MODE_FIFO 0x00000003
#define EPI_HB16_BSEL 0x00000004
#define EPI_HB16_WORD_ACCESS 0x00000100
#define EPI_HB16_CSCFG_ALE 0x00000000
#define EPI_HB16_CSCFG_CS 0x00000200
#define EPI_HB16_CSCFG_DUAL_CS 0x00000400
#define EPI_HB16_CSCFG_ALE_DUAL_CS 0x00000600
#define EPI_HB16_CSBAUD_DUAL 0x00000800
#define EPI_HB16_CSCFG_MASK 0x00000600
//*****************************************************************************
//
// Values that can be passed to EPIConfigSDRAMSet()
@@ -196,6 +228,8 @@ extern void EPIConfigGPModeSet(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxWait);
extern void EPIConfigHB8Set(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxWait);
extern void EPIConfigHB16Set(unsigned long ulBase, unsigned long ulConfig,
unsigned long ulMaxWait);
extern void EPIAddressMapSet(unsigned long ulBase, unsigned long ulMap);
extern void EPINonBlockingReadConfigure(unsigned long ulBase,
unsigned long ulChannel,
bsp/lm3s8962/Libraries/driverlib/ethernet.c
+159 -70
View File
@@ -2,7 +2,7 @@
//
// ethernet.c - Driver for the Integrated Ethernet Controller
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -44,14 +44,14 @@
//! \param ulBase is the base address of the controller.
//! \param ulEthClk is the rate of the clock supplied to the Ethernet module.
//!
//! This function will prepare the Ethernet controller for first time use in
//! This function prepares the Ethernet controller for first-time use in
//! a given hardware/software configuration. This function should be called
//! before any other Ethernet API functions are called.
//!
//! The peripheral clock will be the same as the processor clock. This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//! The peripheral clock is the same as the processor clock. This value is
//! returned by SysCtlClockGet(), or it can be explicitly hard-coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtlClockGet()).
//!
//! This function replaces the original EthernetInit() API and performs the
//! same actions. A macro is provided in <tt>ethernet.h</tt> to map the
@@ -112,14 +112,16 @@ EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk)
//!
//! The Ethernet controller provides three control registers that are used
//! to configure the controller's operation. The transmit control register
//! provides settings to enable full duplex operation, to auto-generate the
//! provides settings to enable full-duplex operation, to auto-generate the
//! frame check sequence, and to pad the transmit packets to the minimum
//! length as required by the IEEE standard. The receive control register
//! provides settings to enable reception of packets with bad frame check
//! sequence values and to enable multi-cast or promiscuous modes. The
//! timestamp control register provides settings that enable support logic in
//! the controller that allow the use of the General Purpose Timer 3 to capture
//! timestamps for the transmitted and received packets.
//! timestamps for the transmitted and received packets. Note that not all
//! devices support this functionality; see the data sheet to determine if
//! this feature is supported.
//!
//! The \e ulConfig parameter is the logical OR of the following values:
//!
@@ -183,11 +185,11 @@ EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig)
//!
//! \param ulBase is the base address of the controller.
//!
//! This function will query the control registers of the Ethernet controller
//! and return a bit-mapped configuration value.
//! This function queries the control registers of the Ethernet controller
//! and returns a bit-mapped configuration value.
//!
//! \sa The description of the EthernetConfigSet() function provides detailed
//! information for the bit-mapped configuration values that will be returned.
//! information for the bit-mapped configuration values that are returned.
//!
//! \return Returns the bit-mapped Ethernet controller configuration value.
//
@@ -219,7 +221,7 @@ EthernetConfigGet(unsigned long ulBase)
//! \param ulBase is the base address of the controller.
//! \param pucMACAddr is the pointer to the array of MAC-48 address octets.
//!
//! This function will program the IEEE-defined MAC-48 address specified in
//! This function programs the IEEE-defined MAC-48 address specified in
//! \e pucMACAddr into the Ethernet controller. This address is used by the
//! Ethernet controller for hardware-level filtering of incoming Ethernet
//! packets (when promiscuous mode is not enabled).
@@ -282,7 +284,7 @@ EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr)
//! \param pucMACAddr is the pointer to the location in which to store the
//! array of MAC-48 address octets.
//!
//! This function will read the currently programmed MAC address into the
//! This function reads the currently programmed MAC address into the
//! \e pucMACAddr buffer.
//!
//! \sa Refer to EthernetMACAddrSet() API description for more details about
@@ -329,8 +331,8 @@ EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr)
//! the EthernetMACAddrSet() function, this API function can be called to
//! enable the controller for normal operation.
//!
//! This function will enable the controller's transmitter and receiver, and
//! will reset the receive FIFO.
//! This function enables the controller's transmitter and receiver, and
//! resets the receive FIFO.
//!
//! \return None.
//
@@ -371,8 +373,8 @@ EthernetEnable(unsigned long ulBase)
//! \param ulBase is the base address of the controller.
//!
//! When terminating operations on the Ethernet interface, this function should
//! be called. This function will disable the transmitter and receiver, and
//! will clear out the receive FIFO.
//! be called. This function disables the transmitter and receiver, and
//! clears out the receive FIFO.
//!
//! \return None.
//
@@ -416,8 +418,7 @@ EthernetDisable(unsigned long ulBase)
//! packets available in the receive FIFO. When the last bytes of a packet are
//! successfully received (that is, the frame check sequence bytes), the packet
//! count is incremented. Once the packet has been fully read (including the
//! frame check sequence bytes) from the FIFO, the packet count will be
//! decremented.
//! frame check sequence bytes) from the FIFO, the packet count is decremented.
//!
//! \return Returns \b true if there are one or more packets available in the
//! receive FIFO, including the current packet being read, and \b false
@@ -448,7 +449,7 @@ EthernetPacketAvail(unsigned long ulBase)
//! packet at a time. After the packet has been written into the FIFO, the
//! transmit request bit must be set to enable the transmission of the packet.
//! Only after the packet has been transmitted can a new packet be written
//! into the FIFO. This function will simply check to see if a packet is
//! into the FIFO. This function simply checks to see if a packet is
//! in progress. If so, there is no space available in the transmit FIFO.
//!
//! \return Returns \b true if a space is available in the transmit FIFO, and
@@ -609,20 +610,20 @@ EthernetPacketGetInternal(unsigned long ulBase, unsigned char *pucBuf,
//! \param lBufLen is the maximum number of bytes to be read into the buffer.
//!
//! This function reads a packet from the receive FIFO of the controller and
//! places it into \e pucBuf. If no packet is available the function will
//! return immediately. Otherwise, the function will read the entire packet
//! from the receive FIFO. If there are more bytes in the packet than will fit
//! into \e pucBuf (as specified by \e lBufLen), the function will return the
//! negated length of the packet and the buffer will contain \e lBufLen bytes
//! of the packet. Otherwise, the function will return the length of the
//! packet that was read and \e pucBuf will contain the entire packet
//! places it into \e pucBuf. If no packet is available the function
//! returns immediately. Otherwise, the function reads the entire packet
//! from the receive FIFO. If there are more bytes in the packet than can fit
//! into \e pucBuf (as specified by \e lBufLen), the function returns the
//! negated length of the packet and the buffer contains \e lBufLen bytes
//! of the packet. Otherwise, the function returns the length of the
//! packet that was read and \e pucBuf contains the entire packet
//! (excluding the frame check sequence bytes).
//!
//! This function replaces the original EthernetPacketNonBlockingGet() API and
//! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
//! map the original API to this API.
//!
//! \note This function will return immediately if no packet is available.
//! \note This function returns immediately if no packet is available.
//!
//! \return Returns \b 0 if no packet is available, the negated packet length
//! \b -n if the packet is too large for \e pucBuf, and the packet length \b n
@@ -663,16 +664,16 @@ EthernetPacketGetNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
//! \param lBufLen is the maximum number of bytes to be read into the buffer.
//!
//! This function reads a packet from the receive FIFO of the controller and
//! places it into \e pucBuf. The function will wait until a packet is
//! available in the FIFO. Then the function will read the entire packet
//! from the receive FIFO. If there are more bytes in the packet than will
//! fit into \e pucBuf (as specified by \e lBufLen), the function will return
//! the negated length of the packet and the buffer will contain \e lBufLen
//! bytes of the packet. Otherwise, the function will return the length of
//! the packet that was read and \e pucBuf will contain the entire packet
//! places it into \e pucBuf. The function waits until a packet is
//! available in the FIFO. Then the function reads the entire packet
//! from the receive FIFO. If there are more bytes in the packet than can
//! fit into \e pucBuf (as specified by \e lBufLen), the function returns
//! the negated length of the packet and the buffer contains \e lBufLen
//! bytes of the packet. Otherwise, the function returns the length of
//! the packet that was read and \e pucBuf contains the entire packet
//! (excluding the frame check sequence bytes).
//!
//! \note This function is blocking and will not return until a packet arrives.
//! \note This function is blocking and does not return until a packet arrives.
//!
//! \return Returns the negated packet length \b -n if the packet is too large
//! for \e pucBuf, and returns the packet length \b n otherwise.
@@ -832,10 +833,10 @@ EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf,
//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
//! into the transmit FIFO of the controller and then activates the
//! transmitter for this packet. If no space is available in the FIFO, the
//! function will return immediately. If space is available, the
//! function will return once \e lBufLen bytes of the packet have been placed
//! into the FIFO and the transmitter has been started. The function will not
//! wait for the transmission to complete. The function will return the
//! function returns immediately. If space is available, the
//! function returns once \e lBufLen bytes of the packet have been placed
//! into the FIFO and the transmitter has been started. The function does not
//! wait for the transmission to complete. The function returns the
//! negated \e lBufLen if the length is larger than the space available in
//! the transmit FIFO.
//!
@@ -843,7 +844,7 @@ EthernetPacketPutInternal(unsigned long ulBase, unsigned char *pucBuf,
//! performs the same actions. A macro is provided in <tt>ethernet.h</tt> to
//! map the original API to this API.
//!
//! \note This function does not block and will return immediately if no space
//! \note This function does not block and returns immediately if no space
//! is available for the transmit packet.
//!
//! \return Returns \b 0 if no space is available in the transmit FIFO, the
@@ -886,14 +887,14 @@ EthernetPacketPutNonBlocking(unsigned long ulBase, unsigned char *pucBuf,
//!
//! This function writes \e lBufLen bytes of the packet contained in \e pucBuf
//! into the transmit FIFO of the controller and then activates the transmitter
//! for this packet. This function will wait until the transmit FIFO is empty.
//! Once space is available, the function will return once \e lBufLen bytes of
//! for this packet. This function waits until the transmit FIFO is empty.
//! Once space is available, the function returns once \e lBufLen bytes of
//! the packet have been placed into the FIFO and the transmitter has been
//! started. The function will not wait for the transmission to complete. The
//! function will return the negated \e lBufLen if the length is larger than
//! started. The function does not wait for the transmission to complete. The
//! function returns the negated \e lBufLen if the length is larger than
//! the space available in the transmit FIFO.
//!
//! \note This function blocks and will wait until space is available for the
//! \note This function blocks and waits until space is available for the
//! transmit packet before returning.
//!
//! \return Returns the negated packet length \b -lBufLen if the packet is too
@@ -933,9 +934,10 @@ EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf,
//! enabled Ethernet interrupts occur.
//!
//! This function sets the handler to be called when the Ethernet interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific Ethernet interrupts must be enabled via EthernetIntEnable(). It
//! is the interrupt handler's responsibility to clear the interrupt source.
//! occurs. This function enables the global interrupt in the interrupt
//! controller; specific Ethernet interrupts must be enabled via
//! EthernetIntEnable(). It is the interrupt handler's responsibility to clear
//! the interrupt source.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@@ -969,9 +971,9 @@ EthernetIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//!
//! \param ulBase is the base address of the controller.
//!
//! This function unregisters the interrupt handler. This will disable the
//! global interrupt in the interrupt controller so that the interrupt handler
//! no longer is called.
//! This function unregisters the interrupt handler. This function disables
//! the global interrupt in the interrupt controller so that the interrupt
//! handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@@ -1005,16 +1007,17 @@ EthernetIntUnregister(unsigned long ulBase)
//! \param ulBase is the base address of the controller.
//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated Ethernet interrupt sources. Only the sources that
//! are enabled can be reflected to the processor interrupt; disabled sources
//! have no effect on the processor.
//! This function enables the indicated Ethernet interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//!
//! The \e ulIntFlags parameter is the logical OR of any of the following:
//!
//! - \b ETH_INT_PHY - An interrupt from the PHY has occurred. The integrated
//! PHY supports a number of interrupt conditions. The PHY register, PHY_MR17,
//! must be read to determine which PHY interrupt has occurred. This register
//! can be read using the EthernetPHYRead() API function.
//! PHY supports a number of interrupt conditions. The appropriate PHY
//! register, PHY_MR17 or PHY_MR29 depending on the device class, must be read
//! to determine which PHY interrupt has occurred. This register can be read
//! using the EthernetPHYRead() API function.
//! - \b ETH_INT_MDIO - This interrupt indicates that a transaction on the
//! management interface has completed successfully.
//! - \b ETH_INT_RXER - This interrupt indicates that an error has occurred
@@ -1093,9 +1096,9 @@ EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param bMasked is false if the raw interrupt status is required and true
//! if the masked interrupt status is required.
//!
//! This returns the interrupt status for the Ethernet controller. Either the
//! raw interrupt status or the status of interrupts that are allowed to
//! reflect to the processor can be returned.
//! This function returns the interrupt status for the Ethernet controller.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! values described in EthernetIntEnable().
@@ -1138,20 +1141,20 @@ EthernetIntStatus(unsigned long ulBase, tBoolean bMasked)
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified Ethernet interrupt sources are cleared so that they no longer
//! assert. This must be done in the interrupt handler to keep it from being
//! called again immediately upon exit.
//! assert. This function must be called in the interrupt handler to keep the
//! interrupt from being triggered again immediately upon exit.
//!
//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
//! parameter to EthernetIntEnable().
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
@@ -1173,6 +1176,42 @@ EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags)
HWREG(ulBase + MAC_O_IACK) = ulIntFlags;
}
//*****************************************************************************
//
//! Sets the PHY address.
//!
//! \param ulBase is the base address of the controller.
//! \param ucAddr is the address of the PHY.
//!
//! This function sets the address of the PHY that is accessed via
//! EthernetPHYRead() and EthernePHYWrite(). This configuration is only needed
//! when connecting to an external PHY via MII, and should not be used on
//! devices that have integrated PHYs.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr)
{
//
// Check the arguments.
//
ASSERT(ulBase == ETH_BASE);
//
// Wait for any pending transaction to complete.
//
while(HWREG(ulBase + MAC_O_MCTL) & MAC_MCTL_START)
{
}
//
// Set the PHY address.
//
HWREG(ulBase + MAC_O_MADD) = ucAddr;
}
//*****************************************************************************
//
//! Writes to the PHY register.
@@ -1181,7 +1220,7 @@ EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags)
//! \param ucRegAddr is the address of the PHY register to be accessed.
//! \param ulData is the data to be written to the PHY register.
//!
//! This function will write the \e ulData to the PHY register specified by
//! This function writes the \e ulData to the PHY register specified by
//! \e ucRegAddr.
//!
//! \return None.
@@ -1229,7 +1268,7 @@ EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
//! \param ulBase is the base address of the controller.
//! \param ucRegAddr is the address of the PHY register to be accessed.
//!
//! This function will return the contents of the PHY register specified by
//! This function returns the contents of the PHY register specified by
//! \e ucRegAddr.
//!
//! \return Returns the 16-bit value read from the PHY.
@@ -1269,6 +1308,56 @@ EthernetPHYRead(unsigned long ulBase, unsigned char ucRegAddr)
return(HWREG(ulBase + MAC_O_MRXD) & MAC_MRXD_MDRX_M);
}
//*****************************************************************************
//
//! Powers off the Ethernet PHY.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function powers off the Ethernet PHY, reducing the current
//! consumption of the device. While in the powered off state, the Ethernet
//! controller is unable to connect to the Ethernet.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetPHYPowerOff(unsigned long ulBase)
{
//
// Set the PWRDN bit and clear the ANEGEN bit in the PHY, putting it into
// its low power mode.
//
EthernetPHYWrite(ulBase, PHY_MR0,
(EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_ANEGEN) |
PHY_MR0_PWRDN);
}
//*****************************************************************************
//
//! Powers on the Ethernet PHY.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function powers on the Ethernet PHY, enabling it return to normal
//! operation. By default, the PHY is powered on, so this function is only
//! called if EthernetPHYPowerOff() has previously been called.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetPHYPowerOn(unsigned long ulBase)
{
//
// Clear the PWRDN bit and set the ANEGEN bit in the PHY, putting it into
// normal operating mode.
//
EthernetPHYWrite(ulBase, PHY_MR0,
(EthernetPHYRead(ulBase, PHY_MR0) & ~PHY_MR0_PWRDN) |
PHY_MR0_ANEGEN);
}
//*****************************************************************************
//
// Close the Doxygen group.
bsp/lm3s8962/Libraries/driverlib/ethernet.h
+5 -2
View File
@@ -2,7 +2,7 @@
//
// ethernet.h - Defines and Macros for the ethernet module.
//
// Copyright (c) 2006-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2006-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -136,10 +136,13 @@ extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void EthernetPHYAddrSet(unsigned long ulBase, unsigned char ucAddr);
extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr,
unsigned long ulData);
extern unsigned long EthernetPHYRead(unsigned long ulBase,
unsigned char ucRegAddr);
extern void EthernetPHYPowerOff(unsigned long ulBase);
extern void EthernetPHYPowerOn(unsigned long ulBase);
//*****************************************************************************
//
bsp/lm3s8962/Libraries/driverlib/fan.c
+633
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/fan.h
+168
View File
@@ -0,0 +1,168 @@
//*****************************************************************************
//
// fan.h - Prototypes and macros for the Fan controller.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __FAN_H__
#define __FAN_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Fan status values that can be returned from the FanChannelStatus() function.
//
//*****************************************************************************
#define FAN_STATUS_STALLED 0
#define FAN_STATUS_CHANGING 1
#define FAN_STATUS_LOCKED 2
#define FAN_STATUS_NOATTAIN 3
//*****************************************************************************
//
// Configuration flags to be used with FanChannelConfigManual() and
// FanChannelConfigAuto().
//
//*****************************************************************************
#define FAN_CONFIG_RESTART (1 << 15)
#define FAN_CONFIG_NORESTART (0 << 15)
#define FAN_CONFIG_ACCEL_FAST (1 << 14)
#define FAN_CONFIG_ACCEL_SLOW (0 << 14)
#define FAN_CONFIG_HYST_1 (0 << 11)
#define FAN_CONFIG_HYST_2 (1 << 11)
#define FAN_CONFIG_HYST_4 (2 << 11)
#define FAN_CONFIG_HYST_8 (3 << 11)
#define FAN_CONFIG_HYST_16 (4 << 11)
#define FAN_CONFIG_HYST_32 (5 << 11)
#define FAN_CONFIG_HYST_64 (6 << 11)
#define FAN_CONFIG_HYST_128 (7 << 11)
#define FAN_CONFIG_START_2 (0 << 8)
#define FAN_CONFIG_START_4 (1 << 8)
#define FAN_CONFIG_START_8 (2 << 8)
#define FAN_CONFIG_START_16 (3 << 8)
#define FAN_CONFIG_START_32 (4 << 8)
#define FAN_CONFIG_START_64 (5 << 8)
#define FAN_CONFIG_START_128 (6 << 8)
#define FAN_CONFIG_START_256 (7 << 8)
#define FAN_CONFIG_START_DUTY_OFF (0 << 6)
#define FAN_CONFIG_START_DUTY_50 (1 << 6)
#define FAN_CONFIG_START_DUTY_75 (2 << 6)
#define FAN_CONFIG_START_DUTY_100 (3 << 6)
#define FAN_CONFIG_AVG_NONE (0 << 4)
#define FAN_CONFIG_AVG_2 (1 << 4)
#define FAN_CONFIG_AVG_4 (2 << 4)
#define FAN_CONFIG_AVG_8 (3 << 4)
#define FAN_CONFIG_TACH_1 (0 << 2)
#define FAN_CONFIG_TACH_2 (1 << 2)
#define FAN_CONFIG_TACH_4 (2 << 2)
#define FAN_CONFIG_TACH_8 (3 << 2)
//*****************************************************************************
//
// Interrupt configuration/status flags to be used with the following
// functions: FanIntEnable(), FanIntDisable(), FanIntStatus(), FanIntClear().
//
//*****************************************************************************
#define FAN_CH5_INT_AUTO_SPEED_OK (1 << 22)
#define FAN_CH5_INT_MANUAL_SPEED_CHANGE (1 << 22)
#define FAN_CH5_INT_AUTO_SPEED_ERROR (1 << 21)
#define FAN_CH5_INT_MANUAL_SPEED_UPDATE (1 << 21)
#define FAN_CH5_INT_STALL (1 << 20)
#define FAN_CH4_INT_AUTO_SPEED_OK (1 << 18)
#define FAN_CH4_INT_MANUAL_SPEED_CHANGE (1 << 18)
#define FAN_CH4_INT_AUTO_SPEED_ERROR (1 << 17)
#define FAN_CH4_INT_MANUAL_SPEED_UPDATE (1 << 17)
#define FAN_CH4_INT_STALL (1 << 16)
#define FAN_CH3_INT_AUTO_SPEED_OK (1 << 14)
#define FAN_CH3_INT_MANUAL_SPEED_CHANGE (1 << 14)
#define FAN_CH3_INT_AUTO_SPEED_ERROR (1 << 13)
#define FAN_CH3_INT_MANUAL_SPEED_UPDATE (1 << 13)
#define FAN_CH3_INT_STALL (1 << 12)
#define FAN_CH2_INT_AUTO_SPEED_OK (1 << 10)
#define FAN_CH2_INT_MANUAL_SPEED_CHANGE (1 << 10)
#define FAN_CH2_INT_AUTO_SPEED_ERROR (1 << 9)
#define FAN_CH2_INT_MANUAL_SPEED_UPDATE (1 << 9)
#define FAN_CH2_INT_STALL (1 << 8)
#define FAN_CH1_INT_AUTO_SPEED_OK (1 << 6)
#define FAN_CH1_INT_MANUAL_SPEED_CHANGE (1 << 6)
#define FAN_CH1_INT_AUTO_SPEED_ERROR (1 << 5)
#define FAN_CH1_INT_MANUAL_SPEED_UPDATE (1 << 5)
#define FAN_CH1_INT_STALL (1 << 4)
#define FAN_CH0_INT_AUTO_SPEED_OK (1 << 2)
#define FAN_CH0_INT_MANUAL_SPEED_CHANGE (1 << 2)
#define FAN_CH0_INT_AUTO_SPEED_ERROR (1 << 1)
#define FAN_CH0_INT_MANUAL_SPEED_UPDATE (1 << 1)
#define FAN_CH0_INT_STALL (1 << 0)
#define FAN_CHx_INT_AUTO_SPEED_OK(x) (1 << (((x) * 4) + 2))
#define FAN_CHx_INT_MANUAL_SPEED_CHANGE(x) (1 << (((x) * 4) + 2))
#define FAN_CHx_INT_AUTO_SPEED_ERROR(x) (1 << (((x) * 4) + 1))
#define FAN_CHx_INT_MANUAL_SPEED_UPDATE(x) (1 << (((x) * 4) + 1))
#define FAN_CHx_INT_STALL(x) (1 << ((x) * 4))
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
extern void FanChannelEnable(unsigned long ulBase, unsigned long ulChannel);
extern void FanChannelDisable(unsigned long ulBase, unsigned long ulChannel);
extern unsigned long FanChannelStatus(unsigned long ulBase,
unsigned long ulChannel);
extern void FanChannelConfigManual(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulConfig);
extern void FanChannelConfigAuto(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulConfig);
extern void FanChannelDutySet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulDuty);
extern unsigned long FanChannelDutyGet(unsigned long ulBase,
unsigned long ulChannel);
extern void FanChannelRPMSet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulRPM);
extern unsigned long FanChannelRPMGet(unsigned long ulBase,
unsigned long ulChannel);
extern void FanIntEnable(unsigned long ulBase, unsigned long ulFlags);
extern void FanIntDisable(unsigned long ulBase, unsigned long ulFlags);
extern unsigned long FanIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void FanIntClear(unsigned long ulBase, unsigned long ulFlags);
extern void FanIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void FanIntUnregister(unsigned long ulBase);
extern unsigned long FanChannelsGet(unsigned long ulBase);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FAN_H__
bsp/lm3s8962/Libraries/driverlib/flash.c
+71 -69
View File
@@ -2,7 +2,7 @@
//
// flash.c - Driver for programming the on-chip flash.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -70,7 +70,8 @@ static const unsigned long g_pulFMPRERegs[] =
//! Gets the number of processor clocks per micro-second.
//!
//! This function returns the number of clocks per micro-second, as presently
//! known by the flash controller.
//! known by the flash controller. This function is only valid on Sandstorm-
//! and Fury-class devices.
//!
//! \return Returns the number of processor clocks per micro-second.
//
@@ -93,7 +94,7 @@ FlashUsecGet(void)
//! This function is used to tell the flash controller the number of processor
//! clocks per micro-second. This value must be programmed correctly or the
//! flash most likely will not program correctly; it has no affect on reading
//! flash.
//! flash. This function is only valid on Sandstorm- and Fury-class devices.
//!
//! \return None.
//
@@ -113,11 +114,11 @@ FlashUsecSet(unsigned long ulClocks)
//!
//! \param ulAddress is the start address of the flash block to be erased.
//!
//! This function will erase a 1 kB block of the on-chip flash. After erasing,
//! the block will be filled with 0xFF bytes. Read-only and execute-only
//! blocks cannot be erased.
//! This function erases a 1-kB block of the on-chip flash. After erasing,
//! the block is filled with 0xFF bytes. Read-only and execute-only blocks
//! cannot be erased.
//!
//! This function will not return until the block has been erased.
//! This function does not return until the block has been erased.
//!
//! \return Returns 0 on success, or -1 if an invalid block address was
//! specified or the block is write-protected.
@@ -132,9 +133,10 @@ FlashErase(unsigned long ulAddress)
ASSERT(!(ulAddress & (FLASH_ERASE_SIZE - 1)));
//
// Clear the flash access interrupt.
// Clear the flash access and error interrupts.
//
HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
FLASH_FCMISC_ERMISC);
//
// Erase the block.
@@ -150,9 +152,10 @@ FlashErase(unsigned long ulAddress)
}
//
// Return an error if an access violation occurred.
// Return an error if an access violation or erase error occurred.
//
if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
FLASH_FCRIS_ERRIS))
{
return(-1);
}
@@ -173,19 +176,16 @@ FlashErase(unsigned long ulAddress)
//! \param ulCount is the number of bytes to be programmed. Must be a multiple
//! of four.
//!
//! This function will program a sequence of words into the on-chip flash.
//! Programming each location consists of the result of an AND operation
//! of the new data and the existing data; in other words bits that contain
//! 1 can remain 1 or be changed to 0, but bits that are 0 cannot be changed
//! to 1. Therefore, a word can be programmed multiple times as long as these
//! rules are followed; if a program operation attempts to change a 0 bit to
//! a 1 bit, that bit will not have its value changed.
//! This function programs a sequence of words into the on-chip flash.
//! Each word in a page of flash can only be programmed one time between an
//! erase of that page; programming a word multiple times results in an
//! unpredictable value in that word of flash.
//!
//! Since the flash is programmed one word at a time, the starting address and
//! byte count must both be multiples of four. It is up to the caller to
//! Because the flash is programmed one word at a time, the starting address
//! and byte count must both be multiples of four. It is up to the caller to
//! verify the programmed contents, if such verification is required.
//!
//! This function will not return until the data has been programmed.
//! This function does not return until the data has been programmed.
//!
//! \return Returns 0 on success, or -1 if a programming error is encountered.
//
@@ -201,9 +201,10 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress,
ASSERT(!(ulCount & 3));
//
// Clear the flash access interrupt.
// Clear the flash access and error interrupts.
//
HWREG(FLASH_FCMISC) = FLASH_FCMISC_AMISC;
HWREG(FLASH_FCMISC) = (FLASH_FCMISC_AMISC | FLASH_FCMISC_VOLTMISC |
FLASH_FCMISC_INVDMISC | FLASH_FCMISC_PROGMISC);
//
// See if this device has a write buffer.
@@ -280,7 +281,8 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress,
//
// Return an error if an access violation occurred.
//
if(HWREG(FLASH_FCRIS) & FLASH_FCRIS_ARIS)
if(HWREG(FLASH_FCRIS) & (FLASH_FCRIS_ARIS | FLASH_FCRIS_VOLTRIS |
FLASH_FCRIS_INVDRIS | FLASH_FCRIS_PROGRIS))
{
return(-1);
}
@@ -297,7 +299,7 @@ FlashProgram(unsigned long *pulData, unsigned long ulAddress,
//!
//! \param ulAddress is the start address of the flash block to be queried.
//!
//! This function will get the current protection for the specified 2 kB block
//! This function gets the current protection for the specified 2-kB block
//! of flash. Each block can be read/write, read-only, or execute-only.
//! Read/write blocks can be read, executed, erased, and programmed. Read-only
//! blocks can be read and executed. Execute-only blocks can only be executed;
@@ -390,17 +392,17 @@ FlashProtectGet(unsigned long ulAddress)
//! \param eProtect is the protection to be applied to the block. Can be one
//! of \b FlashReadWrite, \b FlashReadOnly, or \b FlashExecuteOnly.
//!
//! This function will set the protection for the specified 2 kB block of
//! flash. Blocks which are read/write can be made read-only or execute-only.
//! Blocks which are read-only can be made execute-only. Blocks which are
//! This function sets the protection for the specified 2-kB block of
//! flash. Blocks that are read/write can be made read-only or execute-only.
//! Blocks that are read-only can be made execute-only. Blocks that are
//! execute-only cannot have their protection modified. Attempts to make the
//! block protection less stringent (that is, read-only to read/write) will
//! result in a failure (and be prevented by the hardware).
//! block protection less stringent (that is, read-only to read/write)
//! result in a failure (and are prevented by the hardware).
//!
//! Changes to the flash protection are maintained only until the next reset.
//! This allows the application to be executed in the desired flash protection
//! environment to check for inappropriate flash access (via the flash
//! interrupt). To make the flash protection permanent, use the
//! This protocol allows the application to be executed in the desired flash
//! protection environment to check for inappropriate flash access (via the
//! flash interrupt). To make the flash protection permanent, use the
//! FlashProtectSave() function.
//!
//! \return Returns 0 on success, or -1 if an invalid address or an invalid
@@ -536,7 +538,7 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
{
ulProtectRE &= ~(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30);
ulProtectRE |= (HWREG(g_pulFMPRERegs[ulBank]) &
(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
(FLASH_FMP_BLOCK_31 | FLASH_FMP_BLOCK_30));
}
//
@@ -555,11 +557,11 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
//
//! Saves the flash protection settings.
//!
//! This function will make the currently programmed flash protection settings
//! permanent. This is a non-reversible operation; a chip reset or power cycle
//! will not change the flash protection.
//! This function makes the currently programmed flash protection settings
//! permanent. On some devices, this operation is non-reversible; a chip reset
//! or power cycle does not change the flash protection.
//!
//! This function will not return until the protection has been saved.
//! This function does not return until the protection has been saved.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
@@ -567,7 +569,7 @@ FlashProtectSet(unsigned long ulAddress, tFlashProtection eProtect)
long
FlashProtectSave(void)
{
int ulTemp, ulLimit;
unsigned long ulTemp, ulLimit;
//
// If running on a Sandstorm-class device, only trigger a save of the first
@@ -604,8 +606,8 @@ FlashProtectSave(void)
//! \param pulUser0 is a pointer to the location to store USER Register 0.
//! \param pulUser1 is a pointer to the location to store USER Register 1.
//!
//! This function will read the contents of user registers (0 and 1), and
//! store them in the specified locations.
//! This function reads the contents of user registers (0 and 1), and
//! stores them in the specified locations.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
@@ -646,7 +648,7 @@ FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1)
//! \param ulUser0 is the value to store in USER Register 0.
//! \param ulUser1 is the value to store in USER Register 1.
//!
//! This function will set the contents of the user registers (0 and 1) to
//! This function sets the contents of the user registers (0 and 1) to
//! the specified values.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
@@ -679,11 +681,11 @@ FlashUserSet(unsigned long ulUser0, unsigned long ulUser1)
//
//! Saves the user registers.
//!
//! This function will make the currently programmed user register settings
//! permanent. This is a non-reversible operation; a chip reset or power cycle
//! will not change this setting.
//! This function makes the currently programmed user register settings
//! permanent. On some devices, this operation is non-reversible; a chip reset
//! or power cycle does not change this setting.
//!
//! This function will not return until the protection has been saved.
//! This function does not return until the protection has been saved.
//!
//! \return Returns 0 on success, or -1 if a hardware error is encountered.
//
@@ -739,12 +741,12 @@ FlashUserSave(void)
//! \param pfnHandler is a pointer to the function to be called when the flash
//! interrupt occurs.
//!
//! This sets the handler to be called when the flash interrupt occurs. The
//! flash controller can generate an interrupt when an invalid flash access
//! This function sets the handler to be called when the flash interrupt occurs.
//! The flash controller can generate an interrupt when an invalid flash access
//! occurs, such as trying to program or erase a read-only block, or trying to
//! read from an execute-only block. It can also generate an interrupt when a
//! program or erase operation has completed. The interrupt will be
//! automatically enabled when the handler is registered.
//! program or erase operation has completed. The interrupt is automatically
//! enabled when the handler is registered.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@@ -770,9 +772,9 @@ FlashIntRegister(void (*pfnHandler)(void))
//
//! Unregisters the interrupt handler for the flash interrupt.
//!
//! This function will clear the handler to be called when the flash interrupt
//! occurs. This will also mask off the interrupt in the interrupt controller
//! so that the interrupt handler is no longer called.
//! This function clears the handler to be called when the flash interrupt
//! occurs. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler is no longer called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@@ -801,9 +803,9 @@ FlashIntUnregister(void)
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
//!
//! Enables the indicated flash controller interrupt sources. Only the sources
//! that are enabled can be reflected to the processor interrupt; disabled
//! sources have no effect on the processor.
//! This function enables the indicated flash controller interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
@@ -824,9 +826,9 @@ FlashIntEnable(unsigned long ulIntFlags)
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_ACCESS values.
//!
//! Disables the indicated flash controller interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//! This function disables the indicated flash controller interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
@@ -847,9 +849,9 @@ FlashIntDisable(unsigned long ulIntFlags)
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the flash controller. Either the raw
//! interrupt status or the status of interrupts that are allowed to reflect to
//! the processor can be returned.
//! This function returns the interrupt status for the flash controller.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//!
//! \return The current interrupt status, enumerated as a bit field of
//! \b FLASH_INT_PROGRAM and \b FLASH_INT_ACCESS.
@@ -880,17 +882,17 @@ FlashIntStatus(tBoolean bMasked)
//! Can be any of the \b FLASH_INT_PROGRAM or \b FLASH_INT_AMISC values.
//!
//! The specified flash controller interrupt sources are cleared, so that they
//! no longer assert. This must be done in the interrupt handler to keep it
//! from being called again immediately upon exit.
//! no longer assert. This function must be called in the interrupt handler
//! to keep the interrupt from being triggered again immediately upon exit.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
bsp/lm3s8962/Libraries/driverlib/flash.h
+9 -4
View File
@@ -2,7 +2,7 @@
//
// flash.h - Prototypes for the flash driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -56,8 +56,13 @@ tFlashProtection;
// returned from FlashIntStatus().
//
//*****************************************************************************
#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask
#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask
#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask
#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask
#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask
//*****************************************************************************
//
bsp/lm3s8962/Libraries/driverlib/fpu.c
+284
View File
@@ -0,0 +1,284 @@
//*****************************************************************************
//
// fpu.c - Routines for manipulating the floating-point unit in the Cortex-M
// processor.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
//*****************************************************************************
//
//! \addtogroup fpu_api
//! @{
//
//*****************************************************************************
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"
#include "fpu.h"
//*****************************************************************************
//
//! Enables the floating-point unit.
//!
//! This function enables the floating-point unit, allowing the floating-point
//! instructions to be executed. This function must be called prior to
//! performing any hardware floating-point operations; failure to do so results
//! in a NOCP usage fault.
//!
//! \return None.
//
//*****************************************************************************
void
FPUEnable(void)
{
//
// Enable the coprocessors used by the floating-point unit.
//
HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);
}
//*****************************************************************************
//
//! Disables the floating-point unit.
//!
//! This function disables the floating-point unit, preventing floating-point
//! instructions from executing (generating a NOCP usage fault instead).
//!
//! \return None.
//
//*****************************************************************************
void
FPUDisable(void)
{
//
// Disable the coprocessors used by the floating-point unit.
//
HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
NVIC_CPAC_CP10_DIS | NVIC_CPAC_CP11_DIS);
}
//*****************************************************************************
//
//! Enables the stacking of floating-point registers.
//!
//! This function enables the stacking of floating-point registers s0-s15 when
//! an interrupt is handled. When enabled, space is reserved on the stack for
//! the floating-point context and the floating-point state is saved into this
//! stack space. Upon return from the interrupt, the floating-point context is
//! restored.
//!
//! If the floating-point registers are not stacked, floating-point
//! instructions cannot be safely executed in an interrupt handler because the
//! values of s0-s15 are not likely to be preserved for the interrupted code.
//! On the other hand, stacking the floating-point registers increases the
//! stacking operation from 8 words to 26 words, also increasing the interrupt
//! response latency.
//!
//! \return None.
//
//*****************************************************************************
void
FPUStackingEnable(void)
{
//
// Enable automatic state preservation for the floating-point unit, and
// disable lazy state preservation (meaning that the floating-point state
// is always stacked when floating-point instructions are used).
//
HWREG(NVIC_FPCC) = (HWREG(NVIC_FPCC) & ~NVIC_FPCC_LSPEN) | NVIC_FPCC_ASPEN;
}
//*****************************************************************************
//
//! Enables the lazy stacking of floating-point registers.
//!
//! This function enables the lazy stacking of floating-point registers s0-s15
//! when an interrupt is handled. When lazy stacking is enabled, space is
//! reserved on the stack for the floating-point context, but the
//! floating-point state is not saved. If a floating-point instruction is
//! executed from within the interrupt context, the floating-point context is
//! first saved into the space reserved on the stack. On completion of the
//! interrupt handler, the floating-point context is only restored if it was
//! saved (as the result of executing a floating-point instruction).
//!
//! This method provides a compromise between fast interrupt response (because
//! the floating-point state is not saved on interrupt entry) and the ability
//! to use floating-point in interrupt handlers (because the floating-point
//! state is saved if floating-point instructions are used).
//!
//! \return None.
//
//*****************************************************************************
void
FPULazyStackingEnable(void)
{
//
// Enable automatic and lazy state preservation for the floating-point
// unit.
//
HWREG(NVIC_FPCC) |= NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN;
}
//*****************************************************************************
//
//! Disables the stacking of floating-point registers.
//!
//! This function disables the stacking of floating-point registers s0-s15 when
//! an interrupt is handled. When floating-point context stacking is disabled,
//! floating-point operations performed in an interrupt handler destroy the
//! floating-point context of the main thread of execution.
//!
//! \return None.
//
//*****************************************************************************
void
FPUStackingDisable(void)
{
//
// Disable automatic and lazy state preservation for the floating-point
// unit.
//
HWREG(NVIC_FPCC) &= ~(NVIC_FPCC_ASPEN | NVIC_FPCC_LSPEN);
}
//*****************************************************************************
//
//! Selects the format of half-precision floating-point values.
//!
//! \param ulMode is the format for half-precision floating-point value, which
//! is either \b FPU_HALF_IEEE or \b FPU_HALF_ALTERNATE.
//!
//! This function selects between the IEEE half-precision floating-point
//! representation and the Cortex-M processor alternative representation. The
//! alternative representation has a larger range but does not have a way to
//! encode infinity (positive or negative) or NaN (quiet or signaling). The
//! default setting is the IEEE format.
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPUHalfPrecisionModeSet(unsigned long ulMode)
{
//
// Set the half-precision floating-point format.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_AHP)) | ulMode;
}
//*****************************************************************************
//
//! Selects the NaN mode.
//!
//! \param ulMode is the mode for NaN results; which is either
//! \b FPU_NAN_PROPAGATE or \b FPU_NAN_DEFAULT.
//!
//! This function selects the handling of NaN results during floating-point
//! computations. NaNs can either propagate (the default), or they can return
//! the default NaN.
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPUNaNModeSet(unsigned long ulMode)
{
//
// Set the NaN mode.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_DN)) | ulMode;
}
//*****************************************************************************
//
//! Selects the flush-to-zero mode.
//!
//! \param ulMode is the flush-to-zero mode; which is either
//! \b FPU_FLUSH_TO_ZERO_DIS or \b FPU_FLUSH_TO_ZERO_EN.
//!
//! This function enables or disables the flush-to-zero mode of the
//! floating-point unit. When disabled (the default), the floating-point unit
//! is fully IEEE compliant. When enabled, values close to zero are treated as
//! zero, greatly improving the execution speed at the expense of some accuracy
//! (as well as IEEE compliance).
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPUFlushToZeroModeSet(unsigned long ulMode)
{
//
// Set the flush-to-zero mode.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_FZ)) | ulMode;
}
//*****************************************************************************
//
//! Selects the rounding mode for floating-point results.
//!
//! \param ulMode is the rounding mode.
//!
//! This function selects the rounding mode for floating-point results. After
//! a floating-point operation, the result is rounded toward the specified
//! value. The default mode is \b FPU_ROUND_NEAREST.
//!
//! The following rounding modes are available (as specified by \e ulMode):
//!
//! - \b FPU_ROUND_NEAREST - round toward the nearest value
//! - \b FPU_ROUND_POS_INF - round toward positive infinity
//! - \b FPU_ROUND_NEG_INF - round toward negative infinity
//! - \b FPU_ROUND_ZERO - round toward zero
//!
//! \note Unless this function is called prior to executing any floating-point
//! instructions, the default mode is used.
//!
//! \return None.
//
//*****************************************************************************
void
FPURoundingModeSet(unsigned long ulMode)
{
//
// Set the rounding mode.
//
HWREG(NVIC_FPDSC) = (HWREG(NVIC_FPDSC) & ~(NVIC_FPDSC_RMODE_M)) | ulMode;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
bsp/lm3s8962/Libraries/driverlib/fpu.h
+97
View File
@@ -0,0 +1,97 @@
//*****************************************************************************
//
// fpu.h - Prototypes for the floatint point manipulation routines.
//
// Copyright (c) 2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __FPU_H__
#define __FPU_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to FPUHalfPrecisionSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_HALF_IEEE 0x00000000
#define FPU_HALF_ALTERNATE 0x04000000
//*****************************************************************************
//
// Values that can be passed to FPUNaNModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_NAN_PROPAGATE 0x00000000
#define FPU_NAN_DEFAULT 0x02000000
//*****************************************************************************
//
// Values that can be passed to FPUFlushToZeroModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_FLUSH_TO_ZERO_DIS 0x00000000
#define FPU_FLUSH_TO_ZERO_EN 0x01000000
//*****************************************************************************
//
// Values that can be passed to FPURoundingModeSet as the ulMode parameter.
//
//*****************************************************************************
#define FPU_ROUND_NEAREST 0x00000000
#define FPU_ROUND_POS_INF 0x00400000
#define FPU_ROUND_NEG_INF 0x00800000
#define FPU_ROUND_ZERO 0x00c00000
//*****************************************************************************
//
// Prototypes.
//
//*****************************************************************************
extern void FPUEnable(void);
extern void FPUDisable(void);
extern void FPUStackingEnable(void);
extern void FPULazyStackingEnable(void);
extern void FPUStackingDisable(void);
extern void FPUHalfPrecisionModeSet(unsigned long ulMode);
extern void FPUNaNModeSet(unsigned long ulMode);
extern void FPUFlushToZeroModeSet(unsigned long ulMode);
extern void FPURoundingModeSet(unsigned long ulMode);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __FPU_H__
bsp/lm3s8962/Libraries/driverlib/gpio.c
+672 -205
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/gpio.h
+28 -612
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/hibernate.c
+479 -199
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/hibernate.h
+35 -13
View File
@@ -2,7 +2,7 @@
//
// hibernate.h - API definition for the Hibernation module.
//
// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -41,34 +41,50 @@ extern "C"
// Macros needed for selecting the clock source for HibernateClockSelect()
//
//*****************************************************************************
#define HIBERNATE_CLOCK_SEL_RAW 0x04
#define HIBERNATE_CLOCK_SEL_DIV128 0x00
#define HIBERNATE_CLOCK_SEL_RAW 0x00000004
#define HIBERNATE_CLOCK_SEL_DIV128 0x00000000
//*****************************************************************************
//
// Macros need to configure wake events for HibernateWakeSet()
//
//*****************************************************************************
#define HIBERNATE_WAKE_PIN 0x10
#define HIBERNATE_WAKE_RTC 0x08
#define HIBERNATE_WAKE_PIN 0x00000010
#define HIBERNATE_WAKE_RTC 0x00000008
#define HIBERNATE_WAKE_LOW_BAT 0x00000200
//*****************************************************************************
//
// Macros needed to configure low battery detect for HibernateLowBatSet()
//
//*****************************************************************************
#define HIBERNATE_LOW_BAT_DETECT 0x20
#define HIBERNATE_LOW_BAT_ABORT 0xA0
#define HIBERNATE_LOW_BAT_DETECT 0x00000020
#define HIBERNATE_LOW_BAT_ABORT 0x000000A0
#define HIBERNATE_LOW_BAT_1_9V 0x00000000
#define HIBERNATE_LOW_BAT_2_1V 0x00002000
#define HIBERNATE_LOW_BAT_2_3V 0x00004000
#define HIBERNATE_LOW_BAT_2_5V 0x00006000
//*****************************************************************************
//
// Macros defining interrupt source bits for the interrupt functions.
//
//*****************************************************************************
#define HIBERNATE_INT_PIN_WAKE 0x08
#define HIBERNATE_INT_LOW_BAT 0x04
#define HIBERNATE_INT_RTC_MATCH_0 0x01
#define HIBERNATE_INT_RTC_MATCH_1 0x02
#define HIBERNATE_INT_WR_COMPLETE 0x00000010
#define HIBERNATE_INT_PIN_WAKE 0x00000008
#define HIBERNATE_INT_LOW_BAT 0x00000004
#define HIBERNATE_INT_RTC_MATCH_0 0x00000001
#define HIBERNATE_INT_RTC_MATCH_1 0x00000002
//*****************************************************************************
//
// Macros defining oscillator configuration options for the
// HibernateClockConfig() function.
//
//*****************************************************************************
#define HIBERNATE_OSC_LOWDRIVE 0x00040000
#define HIBERNATE_OSC_HIGHDRIVE 0x00060000
#define HIBERNATE_OSC_DISABLE 0x00010000
//*****************************************************************************
//
@@ -101,7 +117,13 @@ extern void HibernateIntRegister(void (*pfnHandler)(void));
extern void HibernateIntUnregister(void);
extern unsigned long HibernateIntStatus(tBoolean bMasked);
extern void HibernateIntClear(unsigned long ulIntFlags);
extern unsigned int HibernateIsActive(void);
extern unsigned long HibernateIsActive(void);
extern void HibernateRTCSSMatch0Set(unsigned long ulMatch);
extern unsigned long HibernateRTCSSMatch0Get(void);
extern unsigned long HibernateRTCSSGet(void);
extern void HibernateClockConfig(unsigned long ulConfig);
extern void HibernateBatCheckStart(void);
extern unsigned long HibernateBatCheckDone(void);
//*****************************************************************************
//
bsp/lm3s8962/Libraries/driverlib/i2c.c
+555 -105
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/i2c.h
+31 -2
View File
@@ -2,7 +2,7 @@
//
// i2c.h - Prototypes for the I2C Driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -65,6 +65,8 @@ extern "C"
0x00000001
#define I2C_MASTER_CMD_BURST_SEND_FINISH \
0x00000005
#define I2C_MASTER_CMD_BURST_SEND_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_BURST_RECEIVE_START \
@@ -75,6 +77,8 @@ extern "C"
0x00000005
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP \
0x00000004
#define I2C_MASTER_CMD_QUICK_COMMAND \
0x00000027
//*****************************************************************************
//
@@ -95,6 +99,9 @@ extern "C"
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte
#define I2C_SLAVE_ACT_OWN2SEL 0x00000008 // Master requested secondary slave
#define I2C_SLAVE_ACT_QCMD 0x00000010 // Master has sent a Quick Command
#define I2C_SLAVE_ACT_QCMD_DATA 0x00000020 // Master Quick Command value
//*****************************************************************************
//
@@ -103,6 +110,14 @@ extern "C"
//*****************************************************************************
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries
//*****************************************************************************
//
// I2C Master interrupts.
//
//*****************************************************************************
#define I2C_MASTER_INT_TIMEOUT 0x00000002 // Clock Timeout Interrupt.
#define I2C_MASTER_INT_DATA 0x00000001 // Data Interrupt.
//*****************************************************************************
//
// I2C Slave interrupts.
@@ -133,6 +148,18 @@ extern void I2CMasterIntClear(unsigned long ulBase);
extern void I2CMasterIntDisable(unsigned long ulBase);
extern void I2CMasterIntEnable(unsigned long ulBase);
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void I2CMasterIntEnableEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern void I2CMasterIntDisableEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern unsigned long I2CMasterIntStatusEx(unsigned long ulBase,
tBoolean bMasked);
extern void I2CMasterIntClearEx(unsigned long ulBase,
unsigned long ulIntFlags);
extern void I2CMasterTimeoutSet(unsigned long ulBase, unsigned long ulValue);
extern void I2CSlaveACKOverride(unsigned long ulBase, tBoolean bEnable);
extern void I2CSlaveACKValueSet(unsigned long ulBase, tBoolean bACK);
extern unsigned long I2CMasterLineStateGet(unsigned long ulBase);
extern void I2CMasterSlaveAddrSet(unsigned long ulBase,
unsigned char ucSlaveAddr,
tBoolean bReceive);
@@ -141,6 +168,8 @@ extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData);
extern void I2CSlaveDisable(unsigned long ulBase);
extern void I2CSlaveEnable(unsigned long ulBase);
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr);
extern void I2CSlaveAddressSet(unsigned long ulBase, unsigned char ucAddrNum,
unsigned char ucSlaveAddr);
extern void I2CSlaveIntClear(unsigned long ulBase);
extern void I2CSlaveIntDisable(unsigned long ulBase);
extern void I2CSlaveIntEnable(unsigned long ulBase);
bsp/lm3s8962/Libraries/driverlib/i2s.c
+151 -153
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/i2s.h
+2 -2
View File
@@ -2,7 +2,7 @@
//
// i2s.h - Prototypes and macros for the I2S controller.
//
// Copyright (c) 2008-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2008-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
bsp/lm3s8962/Libraries/driverlib/interrupt.c
+112 -84
View File
@@ -2,7 +2,7 @@
//
// interrupt.c - Driver for the NVIC Interrupt Controller.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -59,7 +59,58 @@ static const unsigned long g_pulRegs[] =
{
0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3, NVIC_PRI0, NVIC_PRI1,
NVIC_PRI2, NVIC_PRI3, NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13
NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11, NVIC_PRI12, NVIC_PRI13,
NVIC_PRI14, NVIC_PRI15, NVIC_PRI16, NVIC_PRI17, NVIC_PRI18, NVIC_PRI19,
NVIC_PRI20, NVIC_PRI21, NVIC_PRI22, NVIC_PRI23, NVIC_PRI24, NVIC_PRI25,
NVIC_PRI26, NVIC_PRI27, NVIC_PRI28, NVIC_PRI29, NVIC_PRI30, NVIC_PRI31,
NVIC_PRI32
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt enable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulEnRegs[] =
{
NVIC_EN0, NVIC_EN1, NVIC_EN2, NVIC_EN3, NVIC_EN4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt disable for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulDisRegs[] =
{
NVIC_DIS0, NVIC_DIS1, NVIC_DIS2, NVIC_DIS3, NVIC_DIS4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt pend for that interrupt.
//
//*****************************************************************************
static const unsigned long g_pulPendRegs[] =
{
NVIC_PEND0, NVIC_PEND1, NVIC_PEND2, NVIC_PEND3, NVIC_PEND4
};
//*****************************************************************************
//
// This is a mapping between interrupt number (for the peripheral interrupts
// only) and the register that contains the interrupt unpend for that
// interrupt.
//
//*****************************************************************************
static const unsigned long g_pulUnpendRegs[] =
{
NVIC_UNPEND0, NVIC_UNPEND1, NVIC_UNPEND2, NVIC_UNPEND3, NVIC_UNPEND4
};
//*****************************************************************************
@@ -97,30 +148,32 @@ IntDefaultHandler(void)
//
//*****************************************************************************
#if defined(ewarm)
#pragma data_alignment=1024
static __no_init void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) @ "VTABLE";
#elif defined(sourcerygxx)
static __attribute__((section(".cs3.region-head.ram")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#elif defined(ccs)
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
#elif defined(ccs) || defined(DOXYGEN)
#pragma DATA_ALIGN(g_pfnRAMVectors, 1024)
#pragma DATA_SECTION(g_pfnRAMVectors, ".vtable")
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
#else
static __attribute__((section("vtable")))
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void);
void (*g_pfnRAMVectors[NUM_INTERRUPTS])(void) __attribute__ ((aligned(1024)));
#endif
//*****************************************************************************
//
//! Enables the processor interrupt.
//!
//! Allows the processor to respond to interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//! This function allows the processor to respond to interrupts. This function
//! does not affect the set of interrupts enabled in the interrupt controller;
//! it just gates the single interrupt from the controller to the processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! <tt>tBoolean</tt>, a compiler error occurs in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were disabled when the function was
@@ -140,14 +193,15 @@ IntMasterEnable(void)
//
//! Disables the processor interrupt.
//!
//! Prevents the processor from receiving interrupts. This does not affect the
//! set of interrupts enabled in the interrupt controller; it just gates the
//! single interrupt from the controller to the processor.
//! This function prevents the processor from receiving interrupts. This
//! function does not affect the set of interrupts enabled in the interrupt
//! controller; it just gates the single interrupt from the controller to the
//! processor.
//!
//! \note Previously, this function had no return value. As such, it was
//! possible to include <tt>interrupt.h</tt> and call this function without
//! having included <tt>hw_types.h</tt>. Now that the return is a
//! <tt>tBoolean</tt>, a compiler error will occur in this case. The solution
//! <tt>tBoolean</tt>, a compiler error occurs in this case. The solution
//! is to include <tt>hw_types.h</tt> before including <tt>interrupt.h</tt>.
//!
//! \return Returns \b true if interrupts were already disabled when the
@@ -172,22 +226,20 @@ IntMasterDisable(void)
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor. When the interrupt occurs,
//! if it is enabled (via IntEnable()), the handler function will be called in
//! interrupt context. Since the handler function can preempt other code, care
//! must be taken to protect memory or peripherals that are accessed by the
//! handler and other non-handler code.
//! if it is enabled (via IntEnable()), the handler function is called in
//! interrupt context. Because the handler function can preempt other code,
//! care must be taken to protect memory or peripherals that are accessed by
//! the handler and other non-handler code.
//!
//! \note The use of this function (directly or indirectly via a peripheral
//! driver interrupt register function) moves the interrupt vector table from
//! flash to SRAM. Therefore, care must be taken when linking the application
//! to ensure that the SRAM vector table is located at the beginning of SRAM;
//! otherwise NVIC will not look in the correct portion of memory for the
//! otherwise the NVIC does not look in the correct portion of memory for the
//! vector table (it requires the vector table be on a 1 kB memory alignment).
//! Normally, the SRAM vector table is so placed via the use of linker scripts;
//! some tool chains, such as the evaluation version of RV-MDK, do not support
//! linker scripts and therefore will not produce a valid executable. See the
//! discussion of compile-time versus run-time interrupt handler registration
//! in the introduction to this chapter.
//! Normally, the SRAM vector table is so placed via the use of linker scripts.
//! See the discussion of compile-time versus run-time interrupt handler
//! registration in the introduction to this chapter.
//!
//! \return None.
//
@@ -224,7 +276,7 @@ IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
}
//
// Point NVIC at the RAM vector table.
// Point the NVIC at the RAM vector table.
//
HWREG(NVIC_VTABLE) = (unsigned long)g_pfnRAMVectors;
}
@@ -242,7 +294,7 @@ IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void))
//! \param ulInterrupt specifies the interrupt in question.
//!
//! This function is used to indicate that no handler should be called when the
//! given interrupt is asserted to the processor. The interrupt source will be
//! given interrupt is asserted to the processor. The interrupt source is
//! automatically disabled (via IntDisable()) if necessary.
//!
//! \sa IntRegister() for important information about registering interrupt
@@ -348,7 +400,7 @@ IntPriorityGroupingGet(void)
//! correspond to higher interrupt priorities; priority 0 is the highest
//! interrupt priority.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits. The remaining bits can be
//! used to sub-prioritize the interrupt sources, and may be used by the
@@ -458,19 +510,13 @@ IntEnable(unsigned long ulInterrupt)
//
HWREG(NVIC_ST_CTRL) |= NVIC_ST_CTRL_INTEN;
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Enable the general interrupt.
//
HWREG(NVIC_EN0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Enable the general interrupt.
//
HWREG(NVIC_EN1) = 1 << (ulInterrupt - 48);
HWREG(g_pulEnRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
@@ -526,19 +572,13 @@ IntDisable(unsigned long ulInterrupt)
//
HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_INTEN);
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Disable the general interrupt.
//
HWREG(NVIC_DIS0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Disable the general interrupt.
//
HWREG(NVIC_DIS1) = 1 << (ulInterrupt - 48);
HWREG(g_pulDisRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
@@ -548,13 +588,13 @@ IntDisable(unsigned long ulInterrupt)
//!
//! \param ulInterrupt specifies the interrupt to be pended.
//!
//! The specified interrupt is pended in the interrupt controller. This will
//! cause the interrupt controller to execute the corresponding interrupt
//! handler at the next available time, based on the current interrupt state
//! priorities. For example, if called by a higher priority interrupt handler,
//! the specified interrupt handler will not be called until after the current
//! interrupt handler has completed execution. The interrupt must have been
//! enabled for it to be called.
//! The specified interrupt is pended in the interrupt controller. Pending an
//! interrupt causes the interrupt controller to execute the corresponding
//! interrupt handler at the next available time, based on the current
//! interrupt state priorities. For example, if called by a higher priority
//! interrupt handler, the specified interrupt handler is not called until
//! after the current interrupt handler has completed execution. The interrupt
//! must have been enabled for it to be called.
//!
//! \return None.
//
@@ -591,19 +631,13 @@ IntPendSet(unsigned long ulInterrupt)
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTSET;
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Pend the general interrupt.
//
HWREG(NVIC_PEND0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Pend the general interrupt.
//
HWREG(NVIC_PEND1) = 1 << (ulInterrupt - 48);
HWREG(g_pulPendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
@@ -613,10 +647,10 @@ IntPendSet(unsigned long ulInterrupt)
//!
//! \param ulInterrupt specifies the interrupt to be unpended.
//!
//! The specified interrupt is unpended in the interrupt controller. This will
//! cause any previously generated interrupts that have not been handled yet
//! (due to higher priority interrupts or the interrupt no having been enabled
//! yet) to be discarded.
//! The specified interrupt is unpended in the interrupt controller. Unpending
//! an interrupt causes any previously generated interrupts that have not been
//! handled yet (due to higher priority interrupts or the interrupt not having
//! been enabled yet) to be discarded.
//!
//! \return None.
//
@@ -646,19 +680,13 @@ IntPendClear(unsigned long ulInterrupt)
//
HWREG(NVIC_INT_CTRL) |= NVIC_INT_CTRL_PENDSTCLR;
}
else if((ulInterrupt >= 16) && (ulInterrupt <= 47))
else if(ulInterrupt >= 16)
{
//
// Unpend the general interrupt.
//
HWREG(NVIC_UNPEND0) = 1 << (ulInterrupt - 16);
}
else if(ulInterrupt >= 48)
{
//
// Unpend the general interrupt.
//
HWREG(NVIC_UNPEND1) = 1 << (ulInterrupt - 48);
HWREG(g_pulUnpendRegs[(ulInterrupt - 16) / 32]) =
1 << ((ulInterrupt - 16) & 31);
}
}
@@ -666,19 +694,19 @@ IntPendClear(unsigned long ulInterrupt)
//
//! Sets the priority masking level
//!
//! \param ulPriorityMask is the priority level that will be masked.
//! \param ulPriorityMask is the priority level that is masked.
//!
//! This function sets the interrupt priority masking level so that all
//! interrupts at the specified or lesser priority level is masked. This
//! can be used to globally disable a set of interrupts with priority below
//! a predetermined threshold. A value of 0 disables priority
//! interrupts at the specified or lesser priority level are masked. Masking
//! interrupts can be used to globally disable a set of interrupts with
//! priority below a predetermined threshold. A value of 0 disables priority
//! masking.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//! a priority level mask of 4 allows interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater are blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits.
//!
@@ -701,10 +729,10 @@ IntPriorityMaskSet(unsigned long ulPriorityMask)
//! masking is disabled.
//!
//! Smaller numbers correspond to higher interrupt priorities. So for example
//! a priority level mask of 4 will allow interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater will be blocked.
//! a priority level mask of 4 allows interrupts of priority level 0-3,
//! and interrupts with a numerical priority of 4 and greater are blocked.
//!
//! The hardware priority mechanism will only look at the upper N bits of the
//! The hardware priority mechanism only looks at the upper N bits of the
//! priority level (where N is 3 for the Stellaris family), so any
//! prioritization must be performed in those bits.
//!
bsp/lm3s8962/Libraries/driverlib/interrupt.h
+2 -2
View File
@@ -2,7 +2,7 @@
//
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
bsp/lm3s8962/Libraries/driverlib/lpc.c
+1533
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/lpc.h
+470
View File
@@ -0,0 +1,470 @@
//*****************************************************************************
//
// lpc.h - Prototypes for the Low Pin Count (LPC) driver.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __LPC_H__
#define __LPC_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to LPCConfigSet as the ulConfig value, and
// returned from LPCConfigGet.
//
//*****************************************************************************
#define LPC_CFG_WAKE 0x00000100 // Restart the LPC Bus
//*****************************************************************************
//
// Values that can be returned from LPCStatus.
//
//*****************************************************************************
#define LPC_STATUS_RST 0x00000400 // LPC is in Reset
#define LPC_STATUS_BUSY 0x00000200 // LPC is Busy
#define LPC_STATUS_SLEEP 0x00000100 // LPC is in Sleep Mode
#define LPC_STATUS_CA7 0x00000080 // Channel 7 Active
#define LPC_STATUS_CA6 0x00000040 // Channel 6 Active
#define LPC_STATUS_CA5 0x00000020 // Channel 5 Active
#define LPC_STATUS_CA4 0x00000010 // Channel 4 Active
#define LPC_STATUS_CA3 0x00000008 // Channel 3 Active
#define LPC_STATUS_CA2 0x00000004 // Channel 2 Active
#define LPC_STATUS_CA1 0x00000002 // Channel 1 Active
#define LPC_STATUS_CA0 0x00000001 // Channel 0 Active
//*****************************************************************************
//
// Values that can be passed to LPCIRQSet and LPCIRQClear in the ulIRQ
// parameter and returned from LPCIRQGet.
//
//*****************************************************************************
#define LPC_IRQ15 0x80000000 // Serial IRQ15
#define LPC_IRQ14 0x40000000 // Serial IRQ14
#define LPC_IRQ13 0x20000000 // Serial IRQ13
#define LPC_IRQ12 0x10000000 // Serial IRQ12
#define LPC_IRQ11 0x08000000 // Serial IRQ11
#define LPC_IRQ10 0x04000000 // Serial IRQ10
#define LPC_IRQ9 0x02000000 // Serial IRQ9
#define LPC_IRQ8 0x01000000 // Serial IRQ8
#define LPC_IRQ7 0x00800000 // Serial IRQ7
#define LPC_IRQ6 0x00400000 // Serial IRQ6
#define LPC_IRQ5 0x00200000 // Serial IRQ5
#define LPC_IRQ4 0x00100000 // Serial IRQ4
#define LPC_IRQ3 0x00080000 // Serial IRQ3
#define LPC_IRQ2 0x00040000 // Serial IRQ2
#define LPC_IRQ1 0x00020000 // Serial IRQ1
#define LPC_IRQ0 0x00010000 // Serial IRQ0
//*****************************************************************************
//
// Addition values that can be returned from LPCIRQGet.
//
//*****************************************************************************
#define LPC_IRQ_BUSY 0x00000004 // SERIRQ frame in progress
#define LPC_IRQ_CONT 0x00000001 // SERIRQ in Continuous Mode
//*****************************************************************************
//
// Values that can be passed as the ulChannel parameter in LPCChannel...
// API calls.
//
//*****************************************************************************
#define LPC_CHAN_CH0 0 // LPC Channel 0
#define LPC_CHAN_CH1 1 // LPC Channel 1
#define LPC_CHAN_CH2 2 // LPC Channel 2
#define LPC_CHAN_CH3 3 // LPC Channel 3
#define LPC_CHAN_CH4 4 // LPC Channel 4
#define LPC_CHAN_CH5 5 // LPC Channel 5
#define LPC_CHAN_CH6 6 // LPC Channel 6
#define LPC_CHAN_CH7 7 // LPC Channel 7 (COMx)
#define LPC_CHAN_COMx 7 // LPC Channel 7 (COMx)
//*****************************************************************************
//
// Values that can be passed as part of the ulConfig parameter in the
// LPCChannelConfig... functions.
//
//*****************************************************************************
#define LPC_CHAN_IRQSEL2_NONE 0x00000000 // LPC Channel IRQSEL2 Disabled
#define LPC_CHAN_IRQSEL2_IRQ0 0x00080000 // LPC Channel IRQSEL2 IRQ0
#define LPC_CHAN_IRQSEL2_IRQ1 0x10080000 // LPC Channel IRQSEL2 IRQ1
#define LPC_CHAN_IRQSEL2_IRQ2 0x20080000 // LPC Channel IRQSEL2 IRQ2
#define LPC_CHAN_IRQSEL2_IRQ3 0x30080000 // LPC Channel IRQSEL2 IRQ3
#define LPC_CHAN_IRQSEL2_IRQ4 0x40080000 // LPC Channel IRQSEL2 IRQ4
#define LPC_CHAN_IRQSEL2_IRQ5 0x50080000 // LPC Channel IRQSEL2 IRQ5
#define LPC_CHAN_IRQSEL2_IRQ6 0x60080000 // LPC Channel IRQSEL2 IRQ6
#define LPC_CHAN_IRQSEL2_IRQ7 0x70080000 // LPC Channel IRQSEL2 IRQ7
#define LPC_CHAN_IRQSEL2_IRQ8 0x80080000 // LPC Channel IRQSEL2 IRQ8
#define LPC_CHAN_IRQSEL2_IRQ9 0x90080000 // LPC Channel IRQSEL2 IRQ9
#define LPC_CHAN_IRQSEL2_IRQ10 0xA0080000 // LPC Channel IRQSEL2 IRQ10
#define LPC_CHAN_IRQSEL2_IRQ11 0xB0080000 // LPC Channel IRQSEL2 IRQ11
#define LPC_CHAN_IRQSEL2_IRQ12 0xC0080000 // LPC Channel IRQSEL2 IRQ12
#define LPC_CHAN_IRQSEL2_IRQ13 0xD0080000 // LPC Channel IRQSEL2 IRQ13
#define LPC_CHAN_IRQSEL2_IRQ14 0xE0080000 // LPC Channel IRQSEL2 IRQ14
#define LPC_CHAN_IRQSEL2_IRQ15 0xF0080000 // LPC Channel IRQSEL2 IRQ15
#define LPC_CHAN_COMxIRQ_DISABLE \
0x00000000 // LCP Channel COMx IRQ Disabled
#define LPC_CHAN_COMxIRQ_ENABLE 0x00080000 // LCP Channel COMx IRQ Enabled
#define LPC_CHAN_IRQSEL1_NONE 0x00000000 // LPC Channel IRQSEL1 Disabled
#define LPC_CHAN_IRQSEL1_IRQ0 0x00040000 // LPC Channel IRQSEL1 IRQ0
#define LPC_CHAN_IRQSEL1_IRQ1 0x01040000 // LPC Channel IRQSEL1 IRQ1
#define LPC_CHAN_IRQSEL1_IRQ2 0x02040000 // LPC Channel IRQSEL1 IRQ2
#define LPC_CHAN_IRQSEL1_IRQ3 0x03040000 // LPC Channel IRQSEL1 IRQ3
#define LPC_CHAN_IRQSEL1_IRQ4 0x04040000 // LPC Channel IRQSEL1 IRQ4
#define LPC_CHAN_IRQSEL1_IRQ5 0x05040000 // LPC Channel IRQSEL1 IRQ5
#define LPC_CHAN_IRQSEL1_IRQ6 0x06040000 // LPC Channel IRQSEL1 IRQ6
#define LPC_CHAN_IRQSEL1_IRQ7 0x07040000 // LPC Channel IRQSEL1 IRQ7
#define LPC_CHAN_IRQSEL1_IRQ8 0x08040000 // LPC Channel IRQSEL1 IRQ8
#define LPC_CHAN_IRQSEL1_IRQ9 0x09040000 // LPC Channel IRQSEL1 IRQ9
#define LPC_CHAN_IRQSEL1_IRQ10 0x0A040000 // LPC Channel IRQSEL1 IRQ10
#define LPC_CHAN_IRQSEL1_IRQ11 0x0B040000 // LPC Channel IRQSEL1 IRQ11
#define LPC_CHAN_IRQSEL1_IRQ12 0x0C040000 // LPC Channel IRQSEL1 IRQ12
#define LPC_CHAN_IRQSEL1_IRQ13 0x0D040000 // LPC Channel IRQSEL1 IRQ13
#define LPC_CHAN_IRQSEL1_IRQ14 0x0E040000 // LPC Channel IRQSEL1 IRQ14
#define LPC_CHAN_IRQSEL1_IRQ15 0x0F040000 // LPC Channel IRQSEL1 IRQ15
#define LPC_CHAN_IRQSEL0_NONE 0x00000000 // LPC Channel IRQSEL0 Disabled
#define LPC_CHAN_IRQSEL0_IRQ0 0x00000000 // LPC Channel IRQSEL0 IRQ0
#define LPC_CHAN_IRQSEL0_IRQ1 0x00100000 // LPC Channel IRQSEL0 IRQ1
#define LPC_CHAN_IRQSEL0_IRQ2 0x00200000 // LPC Channel IRQSEL0 IRQ2
#define LPC_CHAN_IRQSEL0_IRQ3 0x00300000 // LPC Channel IRQSEL0 IRQ3
#define LPC_CHAN_IRQSEL0_IRQ4 0x00400000 // LPC Channel IRQSEL0 IRQ4
#define LPC_CHAN_IRQSEL0_IRQ5 0x00500000 // LPC Channel IRQSEL0 IRQ5
#define LPC_CHAN_IRQSEL0_IRQ6 0x00600000 // LPC Channel IRQSEL0 IRQ6
#define LPC_CHAN_IRQSEL0_IRQ7 0x00700000 // LPC Channel IRQSEL0 IRQ7
#define LPC_CHAN_IRQSEL0_IRQ8 0x00800000 // LPC Channel IRQSEL0 IRQ8
#define LPC_CHAN_IRQSEL0_IRQ9 0x00900000 // LPC Channel IRQSEL0 IRQ9
#define LPC_CHAN_IRQSEL0_IRQ10 0x00A00000 // LPC Channel IRQSEL0 IRQ10
#define LPC_CHAN_IRQSEL0_IRQ11 0x00B00000 // LPC Channel IRQSEL0 IRQ11
#define LPC_CHAN_IRQSEL0_IRQ12 0x00C00000 // LPC Channel IRQSEL0 IRQ12
#define LPC_CHAN_IRQSEL0_IRQ13 0x00D00000 // LPC Channel IRQSEL0 IRQ13
#define LPC_CHAN_IRQSEL0_IRQ14 0x00E00000 // LPC Channel IRQSEL0 IRQ14
#define LPC_CHAN_IRQSEL0_IRQ15 0x00F00000 // LPC Channel IRQSEL0 IRQ15
#define LPC_CHAN_IRQEN0_OFF 0x00000000 // LPC Channel IRQEN0 Disabled
#define LPC_CHAN_IRQEN0_TRG1 0x00010000 // LPC Channel IRQEN0 Trigger 1
#define LPC_CHAN_IRQEN0_TRG2 0x00020000 // LPC Channel IRQEN0 Trigger 2
#define LPC_CHAN_IRQEN0_TRG3 0x00030000 // LPC Channel IRQEN0 Trigger 3
#define LPC_CHAN_MBARB_ENABLED 0x00000000 // LPC Channel Mailbox Arbritration
// enabled.
#define LPC_CHAN_MBARB_DISABLED 0x00008000 // LPC Channel Mailbox Arbritration
// disabled.
#define LPC_CHAN_SIZE_4 0x00000000 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_8 0x00000004 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_16 0x00000008 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_32 0x0000000C // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_64 0x00000010 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_128 0x00000014 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_256 0x00000018 // Mailbox IO/Memory Window size
// is 4 Bytes.
#define LPC_CHAN_SIZE_512 0x0000001C // Mailbox IO/Memory Window size
// is 4 Bytes.
//*****************************************************************************
//
// Values that can be passed to LCPChannelConfigCOMxSet as the ulCOMxMode
// parameter or returned from LPCChannelConfigGet in the pulCOMxMode
// parameter.
//
//*****************************************************************************
#define LPC_COMx_MODE_FRMHNML 0x00000000 // Normal From Host model.
#define LPC_COMx_MODE_FRMHIGN 0x00020000 // Ignore From Host data.
#define LPC_COMx_MODE_FRMHDMA 0x00040000 // COMx DMA on From Host data to
// memory
#define LPC_COMx_MODE_UARTDMA 0x00060000 // COMx DMA on From Host data to
// UART1
//*****************************************************************************
//
// Additinal values that can be returned from LPCChannelConfigGet in the
// pulCOMxMode parameter.
//
//*****************************************************************************
#define LPC_COMx_ENABLED 0x00010000 // COMx mode enabled.
//*****************************************************************************
//
// Values that can be passed to LPCIntEnable, LPCIntDisable, and LPCIntClear
// as the ulIntFlags parameter and returned by LPCIntStatus.
//
//*****************************************************************************
#define LPC_INT_RST 0x80000000 // LPC Bus Enters or Exits
// Reset State.
#define LPC_INT_SLEEP 0x40000000 // LPC Bus Enters or Exits
// Sleep State.
#define LPC_INT_COMx 0x20000000 // COMx has read/written
// data.
#define LPC_INT_SIRQ 0x10000000 // SERIRQ frame has completed
#define LPC_INT_CH6_EP_TO_HOST (1 << 24) // To-Host has been read.
#define LPC_INT_CH6_EP_FROM_DATA \
(2 << 24) // From-Host has been written as
// data.
#define LPC_INT_CH6_EP_FROM_CMD (4 << 24) // From-Host has been written as
// command.
#define LPC_INT_CH6_MB_HOST_WON (1 << 24) // Host Won (HW1ST)
#define LPC_INT_CH6_MB_HOST_WRITE \
(2 << 24) // Host Wrote Last Byte.
#define LPC_INT_CH6_MB_HOST_READ \
(4 << 24) // Host Read Last Byte
#define LPC_INT_CH6_MB_MCU_LOST (8 << 24) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH5_EP_TO_HOST (1 << 20) // To-Host has been read.
#define LPC_INT_CH5_EP_FROM_DATA \
(2 << 20) // From-Host has been written as
// data.
#define LPC_INT_CH5_EP_FROM_CMD (4 << 20) // From-Host has been written as
// command.
#define LPC_INT_CH5_MB_HOST_WON (1 << 20) // Host Won (HW1ST)
#define LPC_INT_CH5_MB_HOST_WRITE \
(2 << 20) // Host Wrote Last Byte.
#define LPC_INT_CH5_MB_HOST_READ \
(4 << 20) // Host Read Last Byte
#define LPC_INT_CH5_MB_MCU_LOST (8 << 20) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH4_EP_TO_HOST (1 << 16) // To-Host has been read.
#define LPC_INT_CH4_EP_FROM_DATA \
(2 << 16) // From-Host has been written as
// data.
#define LPC_INT_CH4_EP_FROM_CMD (4 << 16) // From-Host has been written as
// command.
#define LPC_INT_CH4_MB_HOST_WON (1 << 16) // Host Won (HW1ST)
#define LPC_INT_CH4_MB_HOST_WRITE \
(2 << 16) // Host Wrote Last Byte.
#define LPC_INT_CH4_MB_HOST_READ \
(4 << 16) // Host Read Last Byte
#define LPC_INT_CH4_MB_MCU_LOST (8 << 16) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH3_EP_TO_HOST (1 << 12) // To-Host has been read.
#define LPC_INT_CH3_EP_FROM_DATA \
(2 << 12) // From-Host has been written as
// data.
#define LPC_INT_CH3_EP_FROM_CMD (4 << 12) // From-Host has been written as
// command.
#define LPC_INT_CH3_MB_HOST_WON (1 << 12) // Host Won (HW1ST)
#define LPC_INT_CH3_MB_HOST_WRITE \
(2 << 12) // Host Wrote Last Byte.
#define LPC_INT_CH3_MB_HOST_READ \
(4 << 12) // Host Read Last Byte
#define LPC_INT_CH3_MB_MCU_LOST (8 << 12) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH2_EP_TO_HOST (1 << 8) // To-Host has been read.
#define LPC_INT_CH2_EP_FROM_DATA \
(2 << 8) // From-Host has been written as
// data.
#define LPC_INT_CH2_EP_FROM_CMD (4 << 8) // From-Host has been written as
// command.
#define LPC_INT_CH2_MB_HOST_WON (1 << 8) // Host Won (HW1ST)
#define LPC_INT_CH2_MB_HOST_WRITE \
(2 << 8) // Host Wrote Last Byte.
#define LPC_INT_CH2_MB_HOST_READ \
(4 << 8) // Host Read Last Byte
#define LPC_INT_CH2_MB_MCU_LOST (8 << 8) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH1_EP_TO_HOST (1 << 4) // To-Host has been read.
#define LPC_INT_CH1_EP_FROM_DATA \
(2 << 4) // From-Host has been written as
// data.
#define LPC_INT_CH1_EP_FROM_CMD (4 << 4) // From-Host has been written as
// command.
#define LPC_INT_CH1_MB_HOST_WON (1 << 4) // Host Won (HW1ST)
#define LPC_INT_CH1_MB_HOST_WRITE \
(2 << 4) // Host Wrote Last Byte.
#define LPC_INT_CH1_MB_HOST_READ \
(4 << 4) // Host Read Last Byte
#define LPC_INT_CH1_MB_MCU_LOST (8 << 4) // MCU Lost (when host had HW1ST).
#define LPC_INT_CH0_EP_TO_HOST (1 << 0) // To-Host has been read.
#define LPC_INT_CH0_EP_FROM_DATA \
(2 << 0) // From-Host has been written as
// data.
#define LPC_INT_CH0_EP_FROM_CMD (4 << 0) // From-Host has been written as
// command.
#define LPC_INT_CH0_MB_HOST_WON (1 << 0) // Host Won (HW1ST)
#define LPC_INT_CH0_MB_HOST_WRITE \
(2 << 0) // Host Wrote Last Byte.
#define LPC_INT_CH0_MB_HOST_READ \
(4 << 0) // Host Read Last Byte
#define LPC_INT_CH0_MB_MCU_LOST (8 << 0) // MCU Lost (when host had HW1ST).
//*****************************************************************************
//
// Values that can be passed to LPCCOMxInt... functions as the ulIntFlags
// parameter and returned by LPCIntStatus.
//
//*****************************************************************************
#define LPC_COMx_INT_CX 0x02000000 // Raw Event State for COMx
#define LPC_COMx_INT_CXTX 0x01000000 // Raw Event State for COMx TX
#define LPC_COMx_INT_CXRX 0x00800000 // Raw Event State for COMx RX
#define LPC_COMx_MASK_CX 0x00200000 // Event Mask for COMx
#define LPC_COMx_MASK_CXTX 0x00100000 // Event Mask for COMx TX
#define LPC_COMx_MASK_CXRX 0x00080000 // Event Mask for COMx RX
//*****************************************************************************
//
// Values that can be passed to the LPCChannelDMAConfigSet function as part
// of the ulConfig or ulMask parameter, or can be returned from the
// LPCChannelConfigGet function.
//
//*****************************************************************************
#define LPC_DMA_CH3_WEN 0x00000080 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH3_REN 0x00000040 // Trigger DMA when "From Host"
// data buffer is full.
#define LPC_DMA_CH2_WEN 0x00000020 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH2_REN 0x00000010 // Trigger DMA when "From Host"
// data buffer is full.
#define LPC_DMA_CH1_WEN 0x00000008 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH1_REN 0x00000004 // Trigger DMA when "From Host"
// data buffer is full.
#define LPC_DMA_CH0_WEN 0x00000002 // Trigger DMA for "To Host" data
// buffer is empty.
#define LPC_DMA_CH0_REN 0x00000001 // Trigger DMA when "From Host"
// data buffer is full.
//*****************************************************************************
//
// Values that can be passed to the LPCChannelStatusSet and
// LPCChannelStatusClear function, and returned by the LPCChannelStatusGet
// function.
//
//*****************************************************************************
#define LPC_CH_ST_USER0 0x00000100 // User Status Bit 0
#define LPC_CH_ST_USER1 0x00000200 // User Status Bit 1
#define LPC_CH_ST_USER2 0x00000400 // User Status Bit 2
#define LPC_CH_ST_USER3 0x00000800 // User Status Bit 3
#define LPC_CH_ST_USER4 0x00001000 // User Status Bit 4
//*****************************************************************************
//
// Additinoal values that can be returned by the LPCChannelStatusGet function.
//
//*****************************************************************************
#define LPC_CH_ST_LASTHW 0x00000080 // Last Host Write
#define LPC_CH_ST_HW1ST 0x00000040 // First Host Write
#define LPC_CH_ST_LASTSW 0x00000020 // Last Slave Write
#define LPC_CH_ST_SW1ST 0x00000010 // First Slave Write
#define LPC_CH_ST_CMD 0x00000008 // Command or Data
#define LPC_CH_ST_FRMH 0x00000002 // From-Host Transaction
#define LPC_CH_ST_TOH 0x00000001 // To-Host Transaction
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void LPCConfigSet(unsigned long ulBase, unsigned long ulConfig);
extern unsigned long LPCConfigGet(unsigned long ulBase);
extern unsigned long LPCStatusGet(unsigned long ulBase,
unsigned long *pulCount,
unsigned long *pulPoolSize);
extern void LPCStatusBlockAddressSet(unsigned long ulBase,
unsigned long ulAddress,
tBoolean bEnabled);
extern unsigned LPCStatusBlockAddressGet(unsigned long ulBase);
extern void LPCSCIAssert(unsigned long ulBase, unsigned long ulCount);
extern void LPCIRQConfig(unsigned long ulBase, tBoolean bIRQPulse,
tBoolean bIRQOnChange);
extern void LPCIRQSet(unsigned long ulBase, unsigned long ulIRQ);
extern void LPCIRQClear(unsigned long ulBase, unsigned long ulIRQ);
extern unsigned long LPCIRQGet(unsigned long ulBase);
extern void LPCIRQSend(unsigned long ulBase);
extern void LPCIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void LPCIntUnregister(unsigned long ulBase);
extern void LPCIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void LPCIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long LPCIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void LPCIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void LPCChannelEnable(unsigned long ulBase, unsigned long ulChannel);
extern void LPCChannelDisable(unsigned long ulBase, unsigned long ulChannel);
extern void LPCChannelConfigEPSet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulConfig,
unsigned long ulAddress,
unsigned long ulOffset);
extern void LPCChannelConfigMBSet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulConfig,
unsigned long ulAddress,
unsigned long ulOffset);
extern void LPCChannelConfigCOMxSet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulConfig,
unsigned long ulAddress,
unsigned long ulOffset,
unsigned long ulCOMxMode);
extern unsigned long LPCChannelConfigGet(unsigned long ulBase,
unsigned long ulChannel,
unsigned long *pulAddress,
unsigned long *pulOffset,
unsigned long *pulCOMxMode);
extern unsigned long LPCChannelPoolAddressGet(unsigned long ulBase,
unsigned long ulChannel);
extern unsigned long LPCChannelStatusGet(unsigned long ulBase,
unsigned long ulChannel);
extern void LPCChannelStatusSet(unsigned long ulBase, unsigned long ulChannel,
unsigned long ulStatus);
extern void LPCChannelStatusClear(unsigned long ulBase,
unsigned long ulChannel,
unsigned long ulStatus);
extern void LPCChannelDMAConfigSet(unsigned long ulBase,
unsigned long ulConfig,
unsigned long ulMask);
extern unsigned long LPCChannelDMAConfigGet(unsigned long ulBase);
extern unsigned char LPCByteRead(unsigned long ulBase, unsigned long ulOffset);
extern void LPCByteWrite(unsigned long ulBase, unsigned long ulOffset,
unsigned char ucData);
extern unsigned short LPCHalfWordRead(unsigned long ulBase,
unsigned long ulOffset);
extern void LPCHalfWordWrite(unsigned long ulBase, unsigned long ulOffset,
unsigned short usData);
extern unsigned long LPCWordRead(unsigned long ulBase, unsigned long ulOffset);
extern void LPCWordWrite(unsigned long ulBase, unsigned long ulOffset,
unsigned long ulData);
extern void LPCCOMxIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
extern void LPCCOMxIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long LPCCOMxIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void LPCCOMxIntClear(unsigned long ulBase, unsigned long ulIntFlags);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __LPC_H__
bsp/lm3s8962/Libraries/driverlib/mpu.c
+33 -34
View File
@@ -2,7 +2,7 @@
//
// mpu.c - Driver for the Cortex-M3 memory protection unit (MPU).
//
// Copyright (c) 2007-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2007-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -42,14 +42,13 @@
//!
//! \param ulMPUConfig is the logical OR of the possible configurations.
//!
//! This function enables the Cortex-M3 memory protection unit. It also
//! configures the default behavior when in privileged mode and while
//! handling a hard fault or NMI. Prior to enabling the MPU, at least one
//! region must be set by calling MPURegionSet() or else by enabling the
//! default region for privileged mode by passing the
//! \b MPU_CONFIG_PRIV_DEFAULT flag to MPUEnable().
//! Once the MPU is enabled, a memory management fault will be generated
//! for any memory access violations.
//! This function enables the Cortex-M memory protection unit. It also
//! configures the default behavior when in privileged mode and while handling
//! a hard fault or NMI. Prior to enabling the MPU, at least one region must
//! be set by calling MPURegionSet() or else by enabling the default region for
//! privileged mode by passing the \b MPU_CONFIG_PRIV_DEFAULT flag to
//! MPUEnable(). Once the MPU is enabled, a memory management fault is
//! generated for memory access violations.
//!
//! The \e ulMPUConfig parameter should be the logical OR of any of the
//! following:
@@ -63,8 +62,8 @@
//! disabled while in one of these exception handlers and the default
//! memory map is applied.
//! - \b MPU_CONFIG_NONE chooses none of the above options. In this case,
//! no default memory map is provided in privileged mode, and the MPU will
//! not be enabled in the fault handlers.
//! no default memory map is provided in privileged mode, and the MPU isl
//! not enabled in the fault handlers.
//!
//! \return None.
//
@@ -89,7 +88,7 @@ MPUEnable(unsigned long ulMPUConfig)
//
//! Disables the MPU for use.
//!
//! This function disables the Cortex-M3 memory protection unit. When the
//! This function disables the Cortex-M memory protection unit. When the
//! MPU is disabled, the default memory map is used and memory management
//! faults are not generated.
//!
@@ -109,9 +108,8 @@ MPUDisable(void)
//
//! Gets the count of regions supported by the MPU.
//!
//! This function is used to get the number of regions that are supported by
//! the MPU. This is the total number that are supported, including regions
//! that are already programmed.
//! This function is used to get the total number of regions that are supported
//! by the MPU, including regions that are already programmed.
//!
//! \return The number of memory protection regions that are available
//! for programming using MPURegionSet().
@@ -121,7 +119,7 @@ unsigned long
MPURegionCountGet(void)
{
//
// Read the DREGION field of the MPU type register, and mask off
// Read the DREGION field of the MPU type register and mask off
// the bits of interest to get the count of regions.
//
return((HWREG(NVIC_MPU_TYPE) & NVIC_MPU_TYPE_DREGION_M)
@@ -135,9 +133,9 @@ MPURegionCountGet(void)
//! \param ulRegion is the region number to enable.
//!
//! This function is used to enable a memory protection region. The region
//! should already be set up with the MPURegionSet() function. Once enabled,
//! the memory protection rules of the region will be applied and access
//! violations will cause a memory management fault.
//! should already be configured with the MPURegionSet() function. Once
//! enabled, the memory protection rules of the region are applied and access
//! violations cause a memory management fault.
//!
//! \return None.
//
@@ -168,7 +166,7 @@ MPURegionEnable(unsigned long ulRegion)
//! \param ulRegion is the region number to disable.
//!
//! This function is used to disable a previously enabled memory protection
//! region. The region will remain configured if it is not overwritten with
//! region. The region remains configured if it is not overwritten with
//! another call to MPURegionSet(), and can be enabled again by calling
//! MPURegionEnable().
//!
@@ -204,16 +202,16 @@ MPURegionDisable(unsigned long ulRegion)
//! \param ulFlags is a set of flags to define the attributes of the region.
//!
//! This function sets up the protection rules for a region. The region has
//! a base address and a set of attributes including the size, which must
//! be a power of 2. The base address parameter, \e ulAddr, must be aligned
//! according to the size.
//! a base address and a set of attributes including the size. The base
//! address parameter, \e ulAddr, must be aligned according to the size, and
//! the size must be a power of 2.
//!
//! The \e ulFlags parameter is the logical OR of all of the attributes
//! of the region. It is a combination of choices for region size,
//! execute permission, read/write permissions, disabled sub-regions,
//! and a flag to determine if the region is enabled.
//!
//! The size flag determines the size of a region, and must be one of the
//! The size flag determines the size of a region and must be one of the
//! following:
//!
//! - \b MPU_RGN_SIZE_32B
@@ -263,8 +261,8 @@ MPURegionDisable(unsigned long ulRegion)
//!
//! The region is automatically divided into 8 equally-sized sub-regions by
//! the MPU. Sub-regions can only be used in regions of size 256 bytes
//! or larger. Any of these 8 sub-regions can be disabled. This allows
//! for creation of ``holes'' in a region which can be left open, or overlaid
//! or larger. Any of these 8 sub-regions can be disabled, allowing for
//! creation of ``holes'' in a region which can be left open, or overlaid
//! by another region with different attributes. Any of the 8 sub-regions
//! can be disabled with a logical OR of any of the following flags:
//!
@@ -293,7 +291,7 @@ MPURegionDisable(unsigned long ulRegion)
//! MPU_SUB_RGN_DISABLE_2 | MPU_RGN_ENABLE)
//! </code>
//!
//! \note This function will write to multiple registers and is not protected
//! \note This function writes to multiple registers and is not protected
//! from interrupts. It is possible that an interrupt which accesses a
//! region may occur while that region is in the process of being changed.
//! The safest way to handle this is to disable a region before changing it.
@@ -342,9 +340,9 @@ MPURegionSet(unsigned long ulRegion, unsigned long ulAddr,
//! meanings and format of the parameters is the same as that of the
//! MPURegionSet() function.
//!
//! This function can be used to save the configuration of a region for
//! later use with the MPURegionSet() function. The region's enable state
//! will be preserved in the attributes that are saved.
//! This function can be used to save the configuration of a region for later
//! use with the MPURegionSet() function. The region's enable state is
//! preserved in the attributes that are saved.
//!
//! \return None.
//
@@ -383,8 +381,9 @@ MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr,
//! \param pfnHandler is a pointer to the function to be called when the
//! memory management fault occurs.
//!
//! This sets and enables the handler to be called when the MPU generates
//! a memory management fault due to a protection region access violation.
//! This function sets and enables the handler to be called when the MPU
//! generates a memory management fault due to a protection region access
//! violation.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@@ -415,7 +414,7 @@ MPUIntRegister(void (*pfnHandler)(void))
//
//! Unregisters an interrupt handler for the memory management fault.
//!
//! This function will disable and clear the handler to be called when a
//! This function disables and clears the handler to be called when a
//! memory management fault occurs.
//!
//! \sa IntRegister() for important information about registering interrupt
bsp/lm3s8962/Libraries/driverlib/mpu.h
+2 -2
View File
@@ -2,7 +2,7 @@
//
// mpu.h - Defines and Macros for the memory protection unit.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
bsp/lm3s8962/Libraries/driverlib/peci.c
+971
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/peci.h
+226
View File
@@ -0,0 +1,226 @@
//*****************************************************************************
//
// peci.h - Prototypes for Platform Environment Control Interface (PECI)
// driver.
//
// Copyright (c) 2010-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
#ifndef __PECI_H__
#define __PECI_H__
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
// Values that can be passed to PECIConfigDomain, PECIEnableDomain,
// PECIDisableDomain, PECIReadDomainValue, PECIReadDomainMax, and
// PECIClearDomain as the ulDomain parameter.
//
//*****************************************************************************
#define PECI_DOMAIN_M0D0 0 // Microprocessor 0 / Domain 0
#define PECI_DOMAIN_M0D1 1 // Microprocessor 0 / Domain 1
#define PECI_DOMAIN_M1D0 2 // Microprocessor 1 / Domain 0
#define PECI_DOMAIN_M1D1 3 // Microprocessor 1 / Domain 1
//*****************************************************************************
//
// Values that can be passed to PECIIntEnable, PECIIntDisable, and PECIIntClear
// as the ulIntFlags parameter and returned by PECIIntStatus.
//
//*****************************************************************************
#define PECI_READ 0x00000001 // End of PECI Poll
#define PECI_ERR 0x00000002 // Error on PECI Poll
#define PECI_AC 0x00000004 // Advanced Command Complete
#define PECI_M0D0 0x00030000 // Microprocessor 0 / Domain 0
#define PECI_M0D1 0x000C0000 // Microprocessor 0 / Domain 1
#define PECI_M1D0 0x00300000 // Microprocessor 1 / Domain 0
#define PECI_M1D1 0x00C00000 // Microprocessor 1 / Domain 1
//*****************************************************************************
//
// Additional values that can be returned by PECIIntStatus.
//
//*****************************************************************************
#define PECI_M0D0_MODE1_HIGH 0x00030000 // Microprocessor 0 / Domain 0
// Mode 1
// Temperature IS above HIGH
#define PECI_M0D0_MODE2_MID 0x00020000 // Microprocessor 0 / Domain 0
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M0D0_MODE2_HIGH 0x00030000 // Microprocessor 0 / Domain 0
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M0D0_MODE3_LOW 0x00010000 // Microprocessor 0 / Domain 0
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M0D0_MODE3_MID 0x00020000 // Microprocessor 0 / Domain 0
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M0D0_MODE3_HIGH 0x00030000 // Microprocessor 0 / Domain 0
// Mode 3
// Temperature CROSSED above HIGH
#define PECI_M0D1_MODE1_HIGH 0x00030000 // Microprocessor 0 / Domain 1
// Mode 1
// Temperature IS above HIGH
#define PECI_M0D1_MODE2_MID 0x00020000 // Microprocessor 0 / Domain 1
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M0D1_MODE2_HIGH 0x00030000 // Microprocessor 0 / Domain 1
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M0D1_MODE3_LOW 0x00010000 // Microprocessor 0 / Domain 1
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M0D1_MODE3_MID 0x00020000 // Microprocessor 0 / Domain 1
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M0D1_MODE3_HIGH 0x00030000 // Microprocessor 0 / Domain 1
// Mode 3
// Temperature CROSSED above HIGH
#define PECI_M1D0_MODE1_HIGH 0x00030000 // Microprocessor 1 / Domain 0
// Mode 1
// Temperature IS above HIGH
#define PECI_M1D0_MODE2_MID 0x00020000 // Microprocessor 1 / Domain 0
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M1D0_MODE2_HIGH 0x00030000 // Microprocessor 1 / Domain 0
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M1D0_MODE3_LOW 0x00010000 // Microprocessor 1 / Domain 0
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M1D0_MODE3_MID 0x00020000 // Microprocessor 1 / Domain 0
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M1D0_MODE3_HIGH 0x00030000 // Microprocessor 1 / Domain 0
// Mode 3
// Temperature CROSSED above HIGH
#define PECI_M1D1_MODE1_HIGH 0x00030000 // Microprocessor 1 / Domain 1
// Mode 1
// Temperature IS above HIGH
#define PECI_M1D1_MODE2_MID 0x00020000 // Microprocessor 1 / Domain 1
// Mode 2
// Temperature CROSSED above LOW
#define PECI_M1D1_MODE2_HIGH 0x00030000 // Microprocessor 1 / Domain 1
// Mode 2
// Temperature CROSSED above HIGH
#define PECI_M1D1_MODE3_LOW 0x00010000 // Microprocessor 1 / Domain 1
// Mode 3
// Temperature CROSSED below LOW
#define PECI_M1D1_MODE3_MID 0x00020000 // Microprocessor 1 / Domain 1
// Mode 3
// Temperature CROSSED above LOW or
// Temperature CROSSED below HIGH
#define PECI_M1D1_MODE3_HIGH 0x00030000 // Microprocessor 1 / Domain 1
// Mode 3
// Temperature CROSSED above HIGH
//*****************************************************************************
//
// Values that can be passed to PECIIntEnable as the ulIntMode parameter.
//
//*****************************************************************************
#define PECI_M0D0_MODE1 0x00010000 // Domain Interrupt Mode 1
#define PECI_M0D0_MODE2 0x00020000 // Domain Interrupt Mode 2
#define PECI_M0D0_MODE3 0x00030000 // Domain Interrupt Mode 3
#define PECI_M0D1_MODE1 0x00040000 // Domain Interrupt Mode 1
#define PECI_M0D1_MODE2 0x00080000 // Domain Interrupt Mode 2
#define PECI_M0D1_MODE3 0x000C0000 // Domain Interrupt Mode 3
#define PECI_M1D0_MODE1 0x00100000 // Domain Interrupt Mode 1
#define PECI_M1D0_MODE2 0x00200000 // Domain Interrupt Mode 2
#define PECI_M1D0_MODE3 0x00300000 // Domain Interrupt Mode 3
#define PECI_M1D1_MODE1 0x00400000 // Domain Interrupt Mode 1
#define PECI_M1D1_MODE2 0x00800000 // Domain Interrupt Mode 2
#define PECI_M1D1_MODE3 0x00C00000 // Domain Interrupt Mode 3
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
extern void PECIConfigSet(unsigned long ulBase, unsigned long ulPECIClk,
unsigned long ulBaud, unsigned long ulPoll,
unsigned long ulOffset, unsigned long ulRetry);
extern void PECIConfigGet(unsigned long ulBase, unsigned long ulPECIClk,
unsigned long *pulBaud, unsigned long *pulPoll,
unsigned long *pulOffset, unsigned long *pulRetry);
extern void PECIBypassEnable(unsigned long ulBase);
extern void PECIBypassDisable(unsigned long ulBase);
extern void PECIDomainConfigSet(unsigned long ulBase, unsigned long ulDomain,
unsigned long ulHigh, unsigned long ulLow);
extern void PECIDomainConfigGet(unsigned long ulBase, unsigned long ulDomain,
unsigned long *pulHigh, unsigned long *pulLow);
extern void PECIDomainEnable(unsigned long ulBase, unsigned long ulDomain);
extern void PECIDomainDisable(unsigned long ulBase, unsigned long ulDomain);
extern unsigned long PECIDomainValueGet(unsigned long ulBase,
unsigned long ulDomain);
extern unsigned long PECIDomainMaxReadGet(unsigned long ulBase,
unsigned long ulDomain);
extern void PECIDomainValueClear(unsigned long ulBase, unsigned long ulDomain);
extern void PECIDomainMaxReadClear(unsigned long ulBase,
unsigned long ulDomain);
extern void PECIIntRegister(unsigned long ulBase, void (*pfnHandler)(void));
extern void PECIIntUnregister(unsigned long ulBase);
extern void PECIIntEnable(unsigned long ulBase, unsigned long ulIntFlags,
unsigned long ulIntMode);
extern void PECIIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
extern unsigned long PECIIntStatus(unsigned long ulBase, tBoolean bMasked);
extern void PECIIntClear(unsigned long ulBase, unsigned long ulIntFlags);
extern void PECIAdvCmdSend(unsigned long ulBase, unsigned char ucCmd,
unsigned char ucHidRe, unsigned char ucDomain,
unsigned char ucProcAdd, unsigned long ulArg,
unsigned char ucSize, unsigned long ulData0,
unsigned long ulData1);
extern unsigned long PECIAdvCmdSendNonBlocking(unsigned long ulBase,
unsigned char ucCmd,
unsigned char ucHidRe,
unsigned char ucDomain,
unsigned char ucProcAdd,
unsigned long ulArg,
unsigned char ucSize,
unsigned long ulData0,
unsigned long ulData1);
extern unsigned long PECIAdvCmdStatusGet(unsigned long ulBase,
unsigned long *pulData0,
unsigned long *pulData1);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // __PECI_H__
bsp/lm3s8962/Libraries/driverlib/pin_map.h
+51199 -14231
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/pwm.c
+383 -265
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/pwm.h
+2 -2
View File
@@ -2,7 +2,7 @@
//
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
bsp/lm3s8962/Libraries/driverlib/qei.c
+60 -58
View File
@@ -2,7 +2,7 @@
//
// qei.c - Driver for the Quadrature Encoder with Index.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -43,8 +43,8 @@
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will enable operation of the quadrature encoder module. It must be
//! configured before it is enabled.
//! This function enables operation of the quadrature encoder module. The
//! module must be configured before it is enabled.
//!
//! \sa QEIConfigure()
//!
@@ -71,7 +71,7 @@ QEIEnable(unsigned long ulBase)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will disable operation of the quadrature encoder module.
//! This function disables operation of the quadrature encoder module.
//!
//! \return None.
//
@@ -99,22 +99,22 @@ QEIDisable(unsigned long ulBase)
//! for a description of this parameter.
//! \param ulMaxPosition specifies the maximum position value.
//!
//! This will configure the operation of the quadrature encoder. The
//! This function configures the operation of the quadrature encoder. The
//! \e ulConfig parameter provides the configuration of the encoder and is the
//! logical OR of several values:
//!
//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B to specify if edges
//! - \b QEI_CONFIG_CAPTURE_A or \b QEI_CONFIG_CAPTURE_A_B specify if edges
//! on channel A or on both channels A and B should be counted by the
//! position integrator and velocity accumulator.
//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX to specify if the
//! - \b QEI_CONFIG_NO_RESET or \b QEI_CONFIG_RESET_IDX specify if the
//! position integrator should be reset when the index pulse is detected.
//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR to specify if
//! - \b QEI_CONFIG_QUADRATURE or \b QEI_CONFIG_CLOCK_DIR specify if
//! quadrature signals are being provided on ChA and ChB, or if a direction
//! signal and a clock are being provided instead.
//! - \b QEI_CONFIG_NO_SWAP or \b QEI_CONFIG_SWAP to specify if the signals
//! provided on ChA and ChB should be swapped before being processed.
//!
//! \e ulMaxPosition is the maximum value of the position integrator, and is
//! \e ulMaxPosition is the maximum value of the position integrator and is
//! the value used to reset the position capture when in index reset mode and
//! moving in the reverse (negative) direction.
//!
@@ -150,11 +150,11 @@ QEIConfigure(unsigned long ulBase, unsigned long ulConfig,
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current position of the encoder. Depending upon the
//! configuration of the encoder, and the incident of an index pulse, this
//! This function returns the current position of the encoder. Depending upon
//! the configuration of the encoder, and the incident of an index pulse, this
//! value may or may not contain the expected data (that is, if in reset on
//! index mode, if an index pulse has not been encountered, the position
//! counter will not be aligned with the index pulse yet).
//! counter is not yet aligned with the index pulse).
//!
//! \return The current position of the encoder.
//
@@ -180,8 +180,8 @@ QEIPositionGet(unsigned long ulBase)
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulPosition is the new position for the encoder.
//!
//! This sets the current position of the encoder; the encoder position will
//! then be measured relative to this value.
//! This function sets the current position of the encoder; the encoder
//! position is then measured relative to this value.
//!
//! \return None.
//
@@ -206,9 +206,10 @@ QEIPositionSet(unsigned long ulBase, unsigned long ulPosition)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current direction of rotation. In this case, current
//! means the most recently detected direction of the encoder; it may not be
//! presently moving but this is the direction it last moved before it stopped.
//! This function returns the current direction of rotation. In this case,
//! current means the most recently detected direction of the encoder; it may
//! not be presently moving but this is the direction it last moved before it
//! stopped.
//!
//! \return Returns 1 if moving in the forward direction or -1 if moving in the
//! reverse direction.
@@ -234,9 +235,9 @@ QEIDirectionGet(unsigned long ulBase)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the error indicator for the quadrature encoder. It is an
//! error for both of the signals of the quadrature input to change at the same
//! time.
//! This function returns the error indicator for the quadrature encoder. It
//! is an error for both of the signals of the quadrature input to change at
//! the same time.
//!
//! \return Returns \b true if an error has occurred and \b false otherwise.
//
@@ -261,9 +262,9 @@ QEIErrorGet(unsigned long ulBase)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will enable operation of the velocity capture in the quadrature
//! encoder module. It must be configured before it is enabled. Velocity
//! capture will not occur if the quadrature encoder is not enabled.
//! This function enables operation of the velocity capture in the quadrature
//! encoder module. The module must be configured before velocity capture is
//! enabled.
//!
//! \sa QEIVelocityConfigure() and QEIEnable()
//!
@@ -290,7 +291,7 @@ QEIVelocityEnable(unsigned long ulBase)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This will disable operation of the velocity capture in the quadrature
//! This function disables operation of the velocity capture in the quadrature
//! encoder module.
//!
//! \return None.
@@ -322,8 +323,8 @@ QEIVelocityDisable(unsigned long ulBase)
//! \param ulPeriod specifies the number of clock ticks over which to measure
//! the velocity; must be non-zero.
//!
//! This will configure the operation of the velocity capture portion of the
//! quadrature encoder. The position increment signal is predivided as
//! This function configures the operation of the velocity capture portion of
//! the quadrature encoder. The position increment signal is predivided as
//! specified by \e ulPreDiv before being accumulated by the velocity capture.
//! The divided signal is accumulated over \e ulPeriod system clock before
//! being saved and resetting the accumulator.
@@ -360,10 +361,10 @@ QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv,
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This returns the current speed of the encoder. The value returned is the
//! number of pulses detected in the specified time period; this number can be
//! multiplied by the number of time periods per second and divided by the
//! number of pulses per revolution to obtain the number of revolutions per
//! This function returns the current speed of the encoder. The value returned
//! is the number of pulses detected in the specified time period; this number
//! can be multiplied by the number of time periods per second and divided by
//! the number of pulses per revolution to obtain the number of revolutions per
//! second.
//!
//! \return Returns the number of pulses captured in the given time period.
@@ -391,11 +392,11 @@ QEIVelocityGet(unsigned long ulBase)
//! \param pfnHandler is a pointer to the function to be called when the
//! quadrature encoder interrupt occurs.
//!
//! This sets the handler to be called when a quadrature encoder interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific quadrature encoder interrupts must be enabled via QEIIntEnable().
//! It is the interrupt handler's responsibility to clear the interrupt source
//! via QEIIntClear().
//! This function registers the handler to be called when a quadrature encoder
//! interrupt occurs. This function enables the global interrupt in the
//! interrupt controller; specific quadrature encoder interrupts must be
//! enabled via QEIIntEnable(). It is the interrupt handler's responsibility to
//! clear the interrupt source via QEIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@@ -435,9 +436,9 @@ QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//!
//! \param ulBase is the base address of the quadrature encoder module.
//!
//! This function will clear the handler to be called when a quadrature encoder
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//! This function unregisters the handler to be called when a quadrature
//! encoder interrupt occurs. This function also masks off the interrupt in
//! the interrupt controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@@ -480,9 +481,9 @@ QEIIntUnregister(unsigned long ulBase)
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//!
//! Enables the indicated quadrature encoder interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//! This function enables the indicated quadrature encoder interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
@@ -507,12 +508,12 @@ QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR,
//! \b QEI_INTTIMER, or \b QEI_INTINDEX values.
//!
//! Disables the indicated quadrature encoder interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor.
//! This function disables the indicated quadrature encoder interrupt sources.
//! Only the sources that are enabled can be reflected to the processor
//! interrupt; disabled sources have no effect on the processor.
//!
//! \return None.
//
@@ -539,9 +540,9 @@ QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param bMasked is false if the raw interrupt status is required and true if
//! the masked interrupt status is required.
//!
//! This returns the interrupt status for the quadrature encoder module.
//! Either the raw interrupt status or the status of interrupts that are
//! allowed to reflect to the processor can be returned.
//! This function returns the interrupt status for the quadrature encoder
//! module. Either the raw interrupt status or the status of interrupts that
//! are allowed to reflect to the processor can be returned.
//!
//! \return Returns the current interrupt status, enumerated as a bit field of
//! \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, and \b QEI_INTINDEX.
@@ -575,21 +576,22 @@ QEIIntStatus(unsigned long ulBase, tBoolean bMasked)
//!
//! \param ulBase is the base address of the quadrature encoder module.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//! Can be any of the \b QEI_INTERROR, \b QEI_INTDIR, \b QEI_INTTIMER, or
//! \b QEI_INTINDEX values.
//! This parameter can be any of the \b QEI_INTERROR, \b QEI_INTDIR,
//! \b QEI_INTTIMER, or \b QEI_INTINDEX values.
//!
//! The specified quadrature encoder interrupt sources are cleared, so that
//! they no longer assert. This must be done in the interrupt handler to keep
//! it from being called again immediately upon exit.
//! they no longer assert. This function must be called in the interrupt
//! handler to keep the interrupt from being triggered again immediately upon
//! exit.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
bsp/lm3s8962/Libraries/driverlib/qei.h
+2 -2
View File
@@ -2,7 +2,7 @@
//
// qei.h - Prototypes for the Quadrature Encoder Driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
bsp/lm3s8962/Libraries/driverlib/rom.h
+3410 -500
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/rom_map.h
+1474 -10
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/rvmdk/driverlib.lib
BIN
View File
Binary file not shown.
bsp/lm3s8962/Libraries/driverlib/ssi.c
+206 -59
View File
@@ -2,7 +2,7 @@
//
// ssi.c - Driver for Synchronous Serial Interface.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -37,6 +37,83 @@
#include "driverlib/interrupt.h"
#include "driverlib/ssi.h"
//*****************************************************************************
//
// A mapping of timer base address to interupt number.
//
//*****************************************************************************
static const unsigned long g_ppulSSIIntMap[][2] =
{
{ SSI0_BASE, INT_SSI0 },
{ SSI1_BASE, INT_SSI1 },
{ SSI2_BASE, INT_SSI2 },
{ SSI3_BASE, INT_SSI3 },
};
//*****************************************************************************
//
//! \internal
//! Checks an SSI base address.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function determines if a SSI module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static tBoolean
SSIBaseValid(unsigned long ulBase)
{
return((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE) ||
(ulBase == SSI2_BASE) || (ulBase == SSI3_BASE));
}
#endif
//*****************************************************************************
//
//! \internal
//! Gets the SSI interrupt number.
//!
//! \param ulBase specifies the SSI module base address.
//!
//! Given a SSI base address, returns the corresponding interrupt number.
//!
//! \return Returns an SSI interrupt number, or -1 if \e ulBase is invalid.
//
//*****************************************************************************
static long
SSIIntNumberGet(unsigned long ulBase)
{
unsigned long ulIdx;
//
// Loop through the table that maps SSI base addresses to interrupt
// numbers.
//
for(ulIdx = 0; ulIdx < (sizeof(g_ppulSSIIntMap) /
sizeof(g_ppulSSIIntMap[0])); ulIdx++)
{
//
// See if this base address matches.
//
if(g_ppulSSIIntMap[ulIdx][0] == ulBase)
{
//
// Return the corresponding interrupt number.
//
return(g_ppulSSIIntMap[ulIdx][1]);
}
}
//
// The base address could not be found, so return an error.
//
return(-1);
}
//*****************************************************************************
//
//! Configures the synchronous serial interface.
@@ -55,7 +132,7 @@
//! \e ulProtocol parameter can be one of the following values:
//! \b SSI_FRF_MOTO_MODE_0, \b SSI_FRF_MOTO_MODE_1, \b SSI_FRF_MOTO_MODE_2,
//! \b SSI_FRF_MOTO_MODE_3, \b SSI_FRF_TI, or \b SSI_FRF_NMW. The Motorola
//! frame formats imply the following polarity and phase configurations:
//! frame formats encode the following polarity and phase configurations:
//!
//! <pre>
//! Polarity Phase Mode
@@ -66,26 +143,27 @@
//! </pre>
//!
//! The \e ulMode parameter defines the operating mode of the SSI module. The
//! SSI module can operate as a master or slave; if a slave, the SSI can be
//! configured to disable output on its serial output line. The \e ulMode
//! SSI module can operate as a master or slave; if it is a slave, the SSI can
//! be configured to disable output on its serial output line. The \e ulMode
//! parameter can be one of the following values: \b SSI_MODE_MASTER,
//! \b SSI_MODE_SLAVE, or \b SSI_MODE_SLAVE_OD.
//!
//! The \e ulBitRate parameter defines the bit rate for the SSI. This bit rate
//! must satisfy the following clock ratio criteria:
//!
//! - FSSI >= 2 * bit rate (master mode)
//! - FSSI >= 12 * bit rate (slave modes)
//! - FSSI >= 2 * bit rate (master mode); this speed cannot exceed 25 MHz.
//! - FSSI >= 12 * bit rate or 6 * bit rate (slave modes), depending on the
//! capability of the specific microcontroller
//!
//! where FSSI is the frequency of the clock supplied to the SSI module.
//!
//! The \e ulDataWidth parameter defines the width of the data transfers, and
//! The \e ulDataWidth parameter defines the width of the data transfers and
//! can be a value between 4 and 16, inclusive.
//!
//! The peripheral clock will be the same as the processor clock. This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//! The peripheral clock is the same as the processor clock. This value is
//! returned by SysCtlClockGet(), or it can be explicitly hard coded if it is
//! constant and known (to save the code/execution overhead of a call to
//! SysCtlClockGet()).
//!
//! This function replaces the original SSIConfig() API and performs the same
//! actions. A macro is provided in <tt>ssi.h</tt> to map the original API to
@@ -108,7 +186,7 @@ SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk,
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulProtocol == SSI_FRF_MOTO_MODE_0) ||
(ulProtocol == SSI_FRF_MOTO_MODE_1) ||
(ulProtocol == SSI_FRF_MOTO_MODE_2) ||
@@ -170,7 +248,7 @@ SSIEnable(unsigned long ulBase)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Read-modify-write the enable bit.
@@ -195,7 +273,7 @@ SSIDisable(unsigned long ulBase)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Read-modify-write the enable bit.
@@ -211,11 +289,11 @@ SSIDisable(unsigned long ulBase)
//! \param pfnHandler is a pointer to the function to be called when the
//! synchronous serial interface interrupt occurs.
//!
//! This sets the handler to be called when an SSI interrupt
//! occurs. This will enable the global interrupt in the interrupt controller;
//! specific SSI interrupts must be enabled via SSIIntEnable(). If necessary,
//! it is the interrupt handler's responsibility to clear the interrupt source
//! via SSIIntClear().
//! This function registers the handler to be called when an SSI interrupt
//! occurs. This function enables the global interrupt in the interrupt
//! controller; specific SSI interrupts must be enabled via SSIIntEnable(). If
//! necessary, it is the interrupt handler's responsibility to clear the
//! interrupt source via SSIIntClear().
//!
//! \sa IntRegister() for important information about registering interrupt
//! handlers.
@@ -231,12 +309,12 @@ SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Determine the interrupt number based on the SSI port.
//
ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
ulInt = SSIIntNumberGet(ulBase);
//
// Register the interrupt handler, returning an error if an error occurs.
@@ -255,8 +333,8 @@ SSIIntRegister(unsigned long ulBase, void (*pfnHandler)(void))
//!
//! \param ulBase specifies the SSI module base address.
//!
//! This function will clear the handler to be called when a SSI
//! interrupt occurs. This will also mask off the interrupt in the interrupt
//! This function clears the handler to be called when an SSI interrupt
//! occurs. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//!
//! \sa IntRegister() for important information about registering interrupt
@@ -273,12 +351,12 @@ SSIIntUnregister(unsigned long ulBase)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Determine the interrupt number based on the SSI port.
//
ulInt = (ulBase == SSI0_BASE) ? INT_SSI0 : INT_SSI1;
ulInt = SSIIntNumberGet(ulBase);
//
// Disable the interrupt.
@@ -298,10 +376,11 @@ SSIIntUnregister(unsigned long ulBase)
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be enabled.
//!
//! Enables the indicated SSI interrupt sources. Only the sources that are
//! enabled can be reflected to the processor interrupt; disabled sources have
//! no effect on the processor. The \e ulIntFlags parameter can be any of the
//! \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR values.
//! This function enables the indicated SSI interrupt sources. Only the
//! sources that are enabled can be reflected to the processor interrupt;
//! disabled sources have no effect on the processor. The \e ulIntFlags
//! parameter can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or
//! \b SSI_RXOR values.
//!
//! \return None.
//
@@ -312,7 +391,7 @@ SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Enable the specified interrupts.
@@ -327,9 +406,9 @@ SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags)
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be disabled.
//!
//! Disables the indicated SSI interrupt sources. The \e ulIntFlags parameter
//! can be any of the \b SSI_TXFF, \b SSI_RXFF, \b SSI_RXTO, or \b SSI_RXOR
//! values.
//! This function disables the indicated SSI interrupt sources. The
//! \e ulIntFlags parameter can be any of the \b SSI_TXFF, \b SSI_RXFF,
//! \b SSI_RXTO, or \b SSI_RXOR values.
//!
//! \return None.
//
@@ -340,7 +419,7 @@ SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Disable the specified interrupts.
@@ -370,7 +449,7 @@ SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Return either the interrupt status or the raw interrupt status as
@@ -393,20 +472,20 @@ SSIIntStatus(unsigned long ulBase, tBoolean bMasked)
//! \param ulBase specifies the SSI module base address.
//! \param ulIntFlags is a bit mask of the interrupt sources to be cleared.
//!
//! The specified SSI interrupt sources are cleared so that they no longer
//! assert. This function must be called in the interrupt handler to keep the
//! interrupts from being recognized again immediately upon exit. The
//! This function clears the specified SSI interrupt sources so that they no
//! longer assert. This function must be called in the interrupt handler to
//! keep the interrupts from being triggered again immediately upon exit. The
//! \e ulIntFlags parameter can consist of either or both the \b SSI_RXTO and
//! \b SSI_RXOR values.
//!
//! \note Since there is a write buffer in the Cortex-M3 processor, it may take
//! several clock cycles before the interrupt source is actually cleared.
//! \note Because there is a write buffer in the Cortex-M processor, it may
//! take several clock cycles before the interrupt source is actually cleared.
//! Therefore, it is recommended that the interrupt source be cleared early in
//! the interrupt handler (as opposed to the very last action) to avoid
//! returning from the interrupt handler before the interrupt source is
//! actually cleared. Failure to do so may result in the interrupt handler
//! being immediately reentered (since NVIC still sees the interrupt source
//! asserted).
//! being immediately reentered (because the interrupt controller still sees
//! the interrupt source asserted).
//!
//! \return None.
//
@@ -417,7 +496,7 @@ SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Clear the requested interrupt sources.
@@ -449,7 +528,7 @@ SSIDataPut(unsigned long ulBase, unsigned long ulData)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS_M))) == 0);
@@ -495,7 +574,7 @@ SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulData & (0xfffffffe << (HWREG(ulBase + SSI_O_CR0) &
SSI_CR0_DSS_M))) == 0);
@@ -540,7 +619,7 @@ SSIDataGet(unsigned long ulBase, unsigned long *pulData)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Wait until there is data to be read.
@@ -565,7 +644,7 @@ SSIDataGet(unsigned long ulBase, unsigned long *pulData)
//!
//! This function gets received data from the receive FIFO of the specified SSI
//! module and places that data into the location specified by the \e ulData
//! parameter. If there is no data in the FIFO, then this function returns a
//! parameter. If there is no data in the FIFO, then this function returns a
//! zero.
//!
//! This function replaces the original SSIDataNonBlockingGet() API and
@@ -587,7 +666,7 @@ SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Check for data to read.
@@ -610,7 +689,7 @@ SSIDataGetNonBlocking(unsigned long ulBase, unsigned long *pulData)
//! \param ulBase is the base address of the SSI port.
//! \param ulDMAFlags is a bit mask of the DMA features to enable.
//!
//! The specified SSI DMA features are enabled. The SSI can be
//! This function enables the specified SSI DMA features. The SSI can be
//! configured to use DMA for transmit and/or receive data transfers.
//! The \e ulDMAFlags parameter is the logical OR of any of the following
//! values:
@@ -630,10 +709,10 @@ SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Set the requested bits in the UART DMA control register.
// Set the requested bits in the SSI DMA control register.
//
HWREG(ulBase + SSI_O_DMACTL) |= ulDMAFlags;
}
@@ -661,10 +740,10 @@ SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Clear the requested bits in the UART DMA control register.
// Clear the requested bits in the SSI DMA control register.
//
HWREG(ulBase + SSI_O_DMACTL) &= ~ulDMAFlags;
}
@@ -675,10 +754,10 @@ SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags)
//!
//! \param ulBase is the base address of the SSI port.
//!
//! Allows the caller to determine whether all transmitted bytes have cleared
//! the transmitter hardware. If \b false is returned, then the transmit FIFO
//! is empty and all bits of the last transmitted word have left the hardware
//! shift register.
//! This function allows the caller to determine whether all transmitted bytes
//! have cleared the transmitter hardware. If \b false is returned, then the
//! transmit FIFO is empty and all bits of the last transmitted word have left
//! the hardware shift register.
//!
//! \return Returns \b true if the SSI is transmitting or \b false if all
//! transmissions are complete.
@@ -690,7 +769,7 @@ SSIBusy(unsigned long ulBase)
//
// Check the arguments.
//
ASSERT((ulBase == SSI0_BASE) || (ulBase == SSI1_BASE));
ASSERT(SSIBaseValid(ulBase));
//
// Determine if the SSI is busy.
@@ -698,6 +777,74 @@ SSIBusy(unsigned long ulBase)
return((HWREG(ulBase + SSI_O_SR) & SSI_SR_BSY) ? true : false);
}
//*****************************************************************************
//
//! Sets the data clock source for the specified SSI peripheral.
//!
//! \param ulBase is the base address of the SSI port.
//! \param ulSource is the baud clock source for the SSI.
//!
//! This function allows the baud clock source for the SSI to be selected.
//! The possible clock source are the system clock (\b SSI_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b SSI_CLOCK_PIOSC).
//!
//! Changing the baud clock source changes the data rate generated by the
//! SSI. Therefore, the data rate should be reconfigured after any change to
//! the SSI clock source.
//!
//! \note The ability to specify the SSI baud clock source varies with the
//! Stellaris part and SSI in use. Please consult the data sheet for the part
//! you are using to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
void
SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
ASSERT((ulSource == SSI_CLOCK_SYSTEM) || (ulSource == SSI_CLOCK_PIOSC));
//
// Set the SSI clock source.
//
HWREG(ulBase + SSI_O_CC) = ulSource;
}
//*****************************************************************************
//
//! Gets the data clock source for the specified SSI peripheral.
//!
//! \param ulBase is the base address of the SSI port.
//!
//! This function returns the data clock source for the specified SSI. The
//! possible data clock source are the system clock (\b SSI_CLOCK_SYSTEM) or
//! the precision internal oscillator (\b SSI_CLOCK_PIOSC).
//!
//! \note The ability to specify the SSI data clock source varies with the
//! Stellaris part and SSI in use. Please consult the data sheet for the part
//! you are using to determine whether this support is available.
//!
//! \return None.
//
//*****************************************************************************
unsigned long
SSIClockSourceGet(unsigned long ulBase)
{
//
// Check the arguments.
//
ASSERT(SSIBaseValid(ulBase));
//
// Return the SSI clock source.
//
return(HWREG(ulBase + SSI_O_CC));
}
//*****************************************************************************
//
// Close the Doxygen group.
bsp/lm3s8962/Libraries/driverlib/ssi.h
+13 -2
View File
@@ -2,7 +2,7 @@
//
// ssi.h - Prototypes for the Synchronous Serial Interface Driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -71,6 +71,15 @@ extern "C"
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive
//*****************************************************************************
//
// Values that can be passed to SSIClockSourceSet() or returned from
// SSIClockSourceGet().
//
//*****************************************************************************
#define SSI_CLOCK_SYSTEM 0x00000000
#define SSI_CLOCK_PIOSC 0x00000001
//*****************************************************************************
//
// Prototypes for the APIs.
@@ -96,6 +105,8 @@ extern void SSIIntUnregister(unsigned long ulBase);
extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
extern tBoolean SSIBusy(unsigned long ulBase);
extern void SSIClockSourceSet(unsigned long ulBase, unsigned long ulSource);
extern unsigned long SSIClockSourceGet(unsigned long ulBase);
//*****************************************************************************
//
bsp/lm3s8962/Libraries/driverlib/sysctl.c
+1067 -306
View File
File diff suppressed because it is too large Load Diff
bsp/lm3s8962/Libraries/driverlib/sysctl.h
+178 -3
View File
@@ -2,7 +2,7 @@
//
// sysctl.h - Prototypes for the system control driver.
//
// Copyright (c) 2005-2010 Texas Instruments Incorporated. All rights reserved.
// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
@@ -18,7 +18,7 @@
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 6459 of the Stellaris Peripheral Driver Library.
// This is part of revision 8264 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************
@@ -55,7 +55,10 @@ extern "C"
#endif
#define SYSCTL_PERIPH_ADC0 0x00100001 // ADC0
#define SYSCTL_PERIPH_ADC1 0x00100002 // ADC1
#ifndef DEPRECATED
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM
#endif
#define SYSCTL_PERIPH_PWM0 0x00100010 // PWM
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2
@@ -103,6 +106,72 @@ extern "C"
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU
#define SYSCTL_PERIPH2_ADC0 0xf0003800 // ADC 0
#define SYSCTL_PERIPH2_ADC1 0xf0003801 // ADC 1
#define SYSCTL_PERIPH2_CAN0 0xf0003400 // CAN 0
#define SYSCTL_PERIPH2_CAN1 0xf0003401 // CAN 1
#define SYSCTL_PERIPH2_CAN2 0xf0003402 // CAN 2
#define SYSCTL_PERIPH2_COMP0 0xf0003c00 // Analog comparator 0
#define SYSCTL_PERIPH_EEPROM0 0xf0005800 // EEPROM 0
#define SYSCTL_PERIPH_FAN0 0xf0005400 // FAN 0
#define SYSCTL_PERIPH2_GPIOA 0xf0000800 // GPIO A
#define SYSCTL_PERIPH2_GPIOB 0xf0000801 // GPIO B
#define SYSCTL_PERIPH2_GPIOC 0xf0000802 // GPIO C
#define SYSCTL_PERIPH2_GPIOD 0xf0000803 // GPIO D
#define SYSCTL_PERIPH2_GPIOE 0xf0000804 // GPIO E
#define SYSCTL_PERIPH2_GPIOF 0xf0000805 // GPIO F
#define SYSCTL_PERIPH2_GPIOG 0xf0000806 // GPIO G
#define SYSCTL_PERIPH2_GPIOH 0xf0000807 // GPIO H
#define SYSCTL_PERIPH2_GPIOJ 0xf0000808 // GPIO J
#define SYSCTL_PERIPH_GPIOK 0xf0000809 // GPIO K
#define SYSCTL_PERIPH_GPIOL 0xf000080a // GPIO L
#define SYSCTL_PERIPH_GPIOM 0xf000080b // GPIO M
#define SYSCTL_PERIPH_GPION 0xf000080c // GPIO N
#define SYSCTL_PERIPH_GPIOP 0xf000080d // GPIO P
#define SYSCTL_PERIPH_GPIOQ 0xf000080e // GPIO Q
#define SYSCTL_PERIPH_GPIOR 0xf000080f // GPIO R
#define SYSCTL_PERIPH_GPIOS 0xf0000810 // GPIO S
#define SYSCTL_PERIPH2_HIB 0xf0001400 // Hibernation module
#define SYSCTL_PERIPH2_I2C0 0xf0002000 // I2C 0
#define SYSCTL_PERIPH2_I2C1 0xf0002001 // I2C 1
#define SYSCTL_PERIPH_I2C2 0xf0002002 // I2C 2
#define SYSCTL_PERIPH_I2C3 0xf0002003 // I2C 3
#define SYSCTL_PERIPH_I2C4 0xf0002004 // I2C 4
#define SYSCTL_PERIPH_I2C5 0xf0002005 // I2C 5
#define SYSCTL_PERIPH_LPC0 0xf0004800 // LPC 0
#define SYSCTL_PERIPH_PECI0 0xf0005000 // PECI 0
#define SYSCTL_PERIPH2_PWM0 0xf0004000 // PWM 0
#define SYSCTL_PERIPH_PWM1 0xf0004001 // PWM 1
#define SYSCTL_PERIPH2_QEI0 0xf0004400 // QEI 0
#define SYSCTL_PERIPH2_QEI1 0xf0004401 // QEI 1
#define SYSCTL_PERIPH2_SSI0 0xf0001c00 // SSI 0
#define SYSCTL_PERIPH2_SSI1 0xf0001c01 // SSI 1
#define SYSCTL_PERIPH_SSI2 0xf0001c02 // SSI 2
#define SYSCTL_PERIPH_SSI3 0xf0001c03 // SSI 3
#define SYSCTL_PERIPH2_TIMER0 0xf0000400 // Timer 0
#define SYSCTL_PERIPH2_TIMER1 0xf0000401 // Timer 1
#define SYSCTL_PERIPH2_TIMER2 0xf0000402 // Timer 2
#define SYSCTL_PERIPH2_TIMER3 0xf0000403 // Timer 3
#define SYSCTL_PERIPH_TIMER4 0xf0000404 // Timer 4
#define SYSCTL_PERIPH_TIMER5 0xf0000405 // Timer 5
#define SYSCTL_PERIPH_WTIMER0 0xf0005c00 // Wide Timer 0
#define SYSCTL_PERIPH_WTIMER1 0xf0005c01 // Wide Timer 1
#define SYSCTL_PERIPH_WTIMER2 0xf0005c02 // Wide Timer 2
#define SYSCTL_PERIPH_WTIMER3 0xf0005c03 // Wide Timer 3
#define SYSCTL_PERIPH_WTIMER4 0xf0005c04 // Wide Timer 4
#define SYSCTL_PERIPH_WTIMER5 0xf0005c05 // Wide Timer 5
#define SYSCTL_PERIPH2_UART0 0xf0001800 // UART 0
#define SYSCTL_PERIPH2_UART1 0xf0001801 // UART 1
#define SYSCTL_PERIPH2_UART2 0xf0001802 // UART 2
#define SYSCTL_PERIPH_UART3 0xf0001803 // UART 3
#define SYSCTL_PERIPH_UART4 0xf0001804 // UART 4
#define SYSCTL_PERIPH_UART5 0xf0001805 // UART 5
#define SYSCTL_PERIPH_UART6 0xf0001806 // UART 6
#define SYSCTL_PERIPH_UART7 0xf0001807 // UART 7
#define SYSCTL_PERIPH2_UDMA 0xf0000c00 // uDMA
#define SYSCTL_PERIPH2_USB0 0xf0002800 // USB 0
#define SYSCTL_PERIPH2_WDOG0 0xf0000000 // Watchdog 0
#define SYSCTL_PERIPH2_WDOG1 0xf0000001 // Watchdog 1
//*****************************************************************************
//
@@ -194,6 +263,7 @@ extern "C"
//
//*****************************************************************************
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset
#define SYSCTL_CAUSE_WDOG1 0x00000020 // Watchdog1 reset
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset
@@ -393,16 +463,115 @@ extern "C"
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz
#define SYSCTL_XTAL_18MHZ 0x000005C0 // External crystal is 18.0 MHz
#define SYSCTL_XTAL_20MHZ 0x00000600 // External crystal is 20.0 MHz
#define SYSCTL_XTAL_24MHZ 0x00000640 // External crystal is 24.0 MHz
#define SYSCTL_XTAL_25MHZ 0x00000680 // External crystal is 25.0 MHz
#define SYSCTL_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_OSC_INT4 0x00000020 // Osc source is int. osc /4
#define SYSCTL_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_OSC_EXT4_19 0x80000028 // Osc source is ext. 4.19 MHz
#define SYSCTL_OSC_EXT32 0x80000038 // Osc source is ext. 32 KHz
#define SYSCTL_INT_PIOSC_DIS 0x00000004 // Disable interal precision osc.
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlDeepSleepClockSet()
// API as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_DSLP_DIV_1 0x00000000 // Deep-sleep clock is osc /1
#define SYSCTL_DSLP_DIV_2 0x00800000 // Deep-sleep clock is osc /2
#define SYSCTL_DSLP_DIV_3 0x01000000 // Deep-sleep clock is osc /3
#define SYSCTL_DSLP_DIV_4 0x01800000 // Deep-sleep clock is osc /4
#define SYSCTL_DSLP_DIV_5 0x02000000 // Deep-sleep clock is osc /5
#define SYSCTL_DSLP_DIV_6 0x02800000 // Deep-sleep clock is osc /6
#define SYSCTL_DSLP_DIV_7 0x03000000 // Deep-sleep clock is osc /7
#define SYSCTL_DSLP_DIV_8 0x03800000 // Deep-sleep clock is osc /8
#define SYSCTL_DSLP_DIV_9 0x04000000 // Deep-sleep clock is osc /9
#define SYSCTL_DSLP_DIV_10 0x04800000 // Deep-sleep clock is osc /10
#define SYSCTL_DSLP_DIV_11 0x05000000 // Deep-sleep clock is osc /11
#define SYSCTL_DSLP_DIV_12 0x05800000 // Deep-sleep clock is osc /12
#define SYSCTL_DSLP_DIV_13 0x06000000 // Deep-sleep clock is osc /13
#define SYSCTL_DSLP_DIV_14 0x06800000 // Deep-sleep clock is osc /14
#define SYSCTL_DSLP_DIV_15 0x07000000 // Deep-sleep clock is osc /15
#define SYSCTL_DSLP_DIV_16 0x07800000 // Deep-sleep clock is osc /16
#define SYSCTL_DSLP_DIV_17 0x08000000 // Deep-sleep clock is osc /17
#define SYSCTL_DSLP_DIV_18 0x08800000 // Deep-sleep clock is osc /18
#define SYSCTL_DSLP_DIV_19 0x09000000 // Deep-sleep clock is osc /19
#define SYSCTL_DSLP_DIV_20 0x09800000 // Deep-sleep clock is osc /20
#define SYSCTL_DSLP_DIV_21 0x0A000000 // Deep-sleep clock is osc /21
#define SYSCTL_DSLP_DIV_22 0x0A800000 // Deep-sleep clock is osc /22
#define SYSCTL_DSLP_DIV_23 0x0B000000 // Deep-sleep clock is osc /23
#define SYSCTL_DSLP_DIV_24 0x0B800000 // Deep-sleep clock is osc /24
#define SYSCTL_DSLP_DIV_25 0x0C000000 // Deep-sleep clock is osc /25
#define SYSCTL_DSLP_DIV_26 0x0C800000 // Deep-sleep clock is osc /26
#define SYSCTL_DSLP_DIV_27 0x0D000000 // Deep-sleep clock is osc /27
#define SYSCTL_DSLP_DIV_28 0x0D800000 // Deep-sleep clock is osc /28
#define SYSCTL_DSLP_DIV_29 0x0E000000 // Deep-sleep clock is osc /29
#define SYSCTL_DSLP_DIV_30 0x0E800000 // Deep-sleep clock is osc /30
#define SYSCTL_DSLP_DIV_31 0x0F000000 // Deep-sleep clock is osc /31
#define SYSCTL_DSLP_DIV_32 0x0F800000 // Deep-sleep clock is osc /32
#define SYSCTL_DSLP_DIV_33 0x10000000 // Deep-sleep clock is osc /33
#define SYSCTL_DSLP_DIV_34 0x10800000 // Deep-sleep clock is osc /34
#define SYSCTL_DSLP_DIV_35 0x11000000 // Deep-sleep clock is osc /35
#define SYSCTL_DSLP_DIV_36 0x11800000 // Deep-sleep clock is osc /36
#define SYSCTL_DSLP_DIV_37 0x12000000 // Deep-sleep clock is osc /37
#define SYSCTL_DSLP_DIV_38 0x12800000 // Deep-sleep clock is osc /38
#define SYSCTL_DSLP_DIV_39 0x13000000 // Deep-sleep clock is osc /39
#define SYSCTL_DSLP_DIV_40 0x13800000 // Deep-sleep clock is osc /40
#define SYSCTL_DSLP_DIV_41 0x14000000 // Deep-sleep clock is osc /41
#define SYSCTL_DSLP_DIV_42 0x14800000 // Deep-sleep clock is osc /42
#define SYSCTL_DSLP_DIV_43 0x15000000 // Deep-sleep clock is osc /43
#define SYSCTL_DSLP_DIV_44 0x15800000 // Deep-sleep clock is osc /44
#define SYSCTL_DSLP_DIV_45 0x16000000 // Deep-sleep clock is osc /45
#define SYSCTL_DSLP_DIV_46 0x16800000 // Deep-sleep clock is osc /46
#define SYSCTL_DSLP_DIV_47 0x17000000 // Deep-sleep clock is osc /47
#define SYSCTL_DSLP_DIV_48 0x17800000 // Deep-sleep clock is osc /48
#define SYSCTL_DSLP_DIV_49 0x18000000 // Deep-sleep clock is osc /49
#define SYSCTL_DSLP_DIV_50 0x18800000 // Deep-sleep clock is osc /50
#define SYSCTL_DSLP_DIV_51 0x19000000 // Deep-sleep clock is osc /51
#define SYSCTL_DSLP_DIV_52 0x19800000 // Deep-sleep clock is osc /52
#define SYSCTL_DSLP_DIV_53 0x1A000000 // Deep-sleep clock is osc /53
#define SYSCTL_DSLP_DIV_54 0x1A800000 // Deep-sleep clock is osc /54
#define SYSCTL_DSLP_DIV_55 0x1B000000 // Deep-sleep clock is osc /55
#define SYSCTL_DSLP_DIV_56 0x1B800000 // Deep-sleep clock is osc /56
#define SYSCTL_DSLP_DIV_57 0x1C000000 // Deep-sleep clock is osc /57
#define SYSCTL_DSLP_DIV_58 0x1C800000 // Deep-sleep clock is osc /58
#define SYSCTL_DSLP_DIV_59 0x1D000000 // Deep-sleep clock is osc /59
#define SYSCTL_DSLP_DIV_60 0x1D800000 // Deep-sleep clock is osc /60
#define SYSCTL_DSLP_DIV_61 0x1E000000 // Deep-sleep clock is osc /61
#define SYSCTL_DSLP_DIV_62 0x1E800000 // Deep-sleep clock is osc /62
#define SYSCTL_DSLP_DIV_63 0x1F000000 // Deep-sleep clock is osc /63
#define SYSCTL_DSLP_DIV_64 0x1F800000 // Deep-sleep clock is osc /64
#define SYSCTL_DSLP_OSC_MAIN 0x00000000 // Osc source is main osc
#define SYSCTL_DSLP_OSC_INT 0x00000010 // Osc source is int. osc
#define SYSCTL_DSLP_OSC_INT30 0x00000030 // Osc source is int. 30 KHz
#define SYSCTL_DSLP_OSC_EXT32 0x00000070 // Osc source is ext. 32 KHz
#define SYSCTL_DSLP_PIOSC_PD 0x00000002 // Power down PIOSC in deep-sleep
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlPIOSCCalibrate()
// API as the ulType parameter.
//
//*****************************************************************************
#define SYSCTL_PIOSC_CAL_AUTO 0x00000200 // Automatic calibration
#define SYSCTL_PIOSC_CAL_FACT 0x00000100 // Factory calibration
#define SYSCTL_PIOSC_CAL_USER 0x80000100 // User-supplied calibration
//*****************************************************************************
//
// The following are values that can be passed to the SysCtlMOSCConfigSet() API
// as the ulConfig parameter.
//
//*****************************************************************************
#define SYSCTL_MOSC_VALIDATE 0x00000001 // Enable MOSC validation
#define SYSCTL_MOSC_INTERRUPT 0x00000002 // Generate interrupt on MOSC fail
#define SYSCTL_MOSC_NO_XTAL 0x00000004 // No crystal is attached to MOSC
//*****************************************************************************
//
// Prototypes for the APIs.
@@ -412,6 +581,9 @@ extern unsigned long SysCtlSRAMSizeGet(void);
extern unsigned long SysCtlFlashSizeGet(void);
extern tBoolean SysCtlPinPresent(unsigned long ulPin);
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral);
extern tBoolean SysCtlPeripheralReady(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOn(unsigned long ulPeripheral);
extern void SysCtlPeripheralPowerOff(unsigned long ulPeripheral);
extern void SysCtlPeripheralReset(unsigned long ulPeripheral);
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral);
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral);
@@ -437,8 +609,11 @@ extern void SysCtlResetCauseClear(unsigned long ulCauses);
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig,
unsigned long ulDelay);
extern void SysCtlDelay(unsigned long ulCount);
extern void SysCtlMOSCConfigSet(unsigned long ulConfig);
extern unsigned long SysCtlPIOSCCalibrate(unsigned long ulType);
extern void SysCtlClockSet(unsigned long ulConfig);
extern unsigned long SysCtlClockGet(void);
extern void SysCtlDeepSleepClockSet(unsigned long ulConfig);
extern void SysCtlPWMClockSet(unsigned long ulConfig);
extern unsigned long SysCtlPWMClockGet(void);
extern void SysCtlADCSpeedSet(unsigned long ulSpeed);

Some files were not shown because too many files have changed in this diff Show More